ky, SGS-THOMSO Jl Ses THOMSON Z8470 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER TWO INDEPENDENT FULL-DUPLEX CHAN- NELS WITH SEPARATE MODEM CONTROLS. MODEM STATUS CAN BE MONITORED RECEIVER DATA REGISTERS ARE QUADRU- PLY BUFFERED : THE TRANSMITTER IS DOUBLY BUFFERED INTERRUPT FEATURES INCLUDE A PRO- GRAMMABLE INTERRUPT VECTOR, A "STATUS AFFECTS VECTOR" MODE FOR pie 40 pieao FAST INTERRUPT PROCESSING, AND THE (Plastic and Frit-Seal) (Ceramic) STANDARD Z80 PERIPHERAL DAISY-CHAIN INTERRUPT STRUCTURE THAT PROVIDES AUTOMATIC INTERRUPT VECTORING WITH NO EXTERNAL LOGIC INx1 CLOCK MODE, DATA RATES ARE 0 TO 500K BITS/SECOND WITH A 2.5MHz CLOCK, OR 0 TO 800K BITS/SECOND WITH A 4.0MHz Cc CLOCK, OR 0 TO 1200K BIT/SECOND WITHA PLCOC44 6.0MHz CLOCK (Plastic) a PROGRAMMABLE OPTIONS INCLUDE 1, 1 1/2 (Ordering information at the end of the datasheet) OR 2 STOP BITS ; EVEN, ODD OR NO PARITY ; AND x1, x16, x32 AND x64 CLOCK MODES BREAK GENERATION AND DETECTION AS LOGIC FUNCTIONS WELL AS PARITY-, OVERRUN- AND FRAM- ING-ERROR DETECTION ARE AVAILABLE -]o, Rada | 0 os P= DESCRIPTION oar ae wet The Z80 DART (Dual-Channel Asynchronous Re- ]e xa |-_ me ceiver/Transmitter) is a dual-channel multi-function +o atsa p-~ se peripheral component that satisfies a wide variety crs [7 comrnae of asynchronous serial data communications re- ee bob quirements in microcomputer systems. The Z80 ry aeser, aero DART is used as a serial-to-parallel, parallel-to-ser- cowraor | -+| ino _Rxo8 > ial converter/controller in asynchronous applica- cou) ~ *] Re wee i tions. In addition, the device also provides modem al oo winove |> controls for both channels. In applications where +] an _ cre modem controis are not needed, these lines can be amay | = Jian ace \o woven used for general-purpose I/O. vaca | * sae Sat The Z80 SIO, a more versatile device, provides syn- comrmor | =] to bcos |= chronous (Bisync, HDLC and SDLC) as well as f | asynchronous operation. Veo ONO ck The Z80 DART is fabricated with n-channel silicon- gate depletion-load technology, and is packaged in a 40 pin plastic or ceramic DIP. February 1989 1/14 22528470 Figure 1 : Dual ine pine Configuration. a, Q 1 40 [J Og 0,2 3s [} 2 os (3 38 T] D; G a at L) 0, int Os as [] ine iQ) 6 36 [) && o(]7 34 [J BA mi C] 28 3f oo Yoo C] 3 32D) ao windva C) 10 yearo a GND RIA (1 30 [] winpys RxDa (] 12 29 Fy iB fata (13 ze [7] 8xd6 aca (] 4 27 [) ReTxC8 TxD [] 15 26 [} tx08 pira [] 16 25 [J oTRe atsa () 7 24 [[] ATSB osa (] 13 2a [] crse ocba (] 19 22 [DF oc0e cer (] 20 21 [0 RESET Figure 2 : Chip Carrier Pin Configuration. zoo 7 cs oe a- re] sseas ey a0201 44 43 42 61 40 39 [} BA 38 cd 37 Dao 38 [J GND 3s 0) wapye 28444 a4 [] SYNE 33 1) Rxo8 a2 PJ) axe 3t 0 cB 30 f] Ta0B 29 nc 8099 20 21 22 23:24 25 26 27 e 5~8677 NC. << iw = iO <tc [<< xi 1 QO jo |O ees ckERKE eS ee jz lo }8 je IG lz la ad cra Note : NC = No Connection Z80 SIO-0 or Dart in Asynchronous Mode. PIN DESCRIPTIONS B/A. Channel A Or B Select (Input, High Selects Channel B). This input defines which channel is ac- cessed during a data transfer between the CPU and the Z80 DART. C/D. Contro! Or Data Select (Input, High Selects Control). This input specifies the type of information (control or data) transferred on the data bus be- tween the CPU and the Z80 DART. 2/14 ki SGS-THOMSON CE. Chip Enable (input, Active Low). A Low at this input enables the Z80 DART to accept command or data input from the CPU during a write cycle, or to transmit data to the CPU during a read cycle. CLK. System Clock (Input). The Z80 DART uses the standard Z80 single-phase system clock to syn- chronize internal signals. CTSA, CTSB. Clear To Send (Inputs, Active Low). When programmed as Auto Enables, a Low on these inputs enables the respective transmitter. If not programmed as Auto Enables, these inputs may be programmed as general-purpose inputs. Both in- puts are Schmitt-trigger buffered to accomodate slow-risetime signals. Do-D7. System Data Bus (Bidirectional, 3-state) transfers data and commands between the CPU and the Z80 DART. DCDA, DCDB. Data Carrier Detect (Inputs, Active Low). These pins function as receiver enables if the Z80 DART is programmed for Auto Enables ; other- wise they may be used as general-purpose input pins. Both pins are Schmitt-trigger buffered. DTRA, DTRB. Data Terminal Ready (Outputs, Ac- tive Low). These outputs follow the state pro- grammed into the DTR bit. They can also be programmed as general-purpose outputs. IEI. interrupt Enable In (Input, Active High) is used with IEO to form a priority daisy chain when there is more than one interrupt-driven device. A High on this line indicates that no other device of higher priority is being serviced by a CPU interrupt service routine. IEO. Interrupt Enable Out (Output, Active High). IEO is High only if IEl is High and the CPU is not servic- ing an interrupt from this 280 DART. Thus, this sig- nal blocks lower priority devices from interrupting while a higher priority device is being serviced by its CPU interrupt service routine. INT. Interrupt Request (Output, Open Drain, Active Low). When _the Z80 DART is requesting an inter- rupt, it pulls INT Low. M1. Machine Cycle One (Input from Z80 CPU, Ac- tive Low). When M1 and RD are both active, the Z80 CPU is fetching an instruction from memory ; when M1 is active while IORQ is active, the Z80 DART ac- cepts M1 and IORQ as an interrupt acknowledge if the Z80 DART is the highest priority device that has interrupted the Z80 CPU. IORQ. Input/Output Request (input from CPU, Ac- tive Low). IORQis used in conjunction with B/A, C/D, CE and RD to transfer commands and data between the CPU and the Z80 DART. When CE, RD and MICROELECTRONICS 226IORQ are all active, the channel selected by B/A transfers data to the CPU (a read operation). When CE and IORQ are active, but RD is inactive, the channel selected by B/A is written to by the CPU with either data or control information as specified by C/D. RxCA, RxCB. Aeceiver Clocks (Inputs). Receive data is sampled on the rising edge of RxC. The Re- ceive Clocks may be 1, 16, 32 or 64 times the data rate. RD. Read Cycle Status (Input from GPU, Active Low). If RD is active, a memory or I/O read oper- ation is in progress. RxDA, RxDB. Receive Data (Inputs, Active High). RESET. Aeset(|nput, Active Low). Disables both re- ceivers and transmitters, forces TxDA and TxDB marking, forces the modem controls High and dis- ables all interrupts. RIA, RIB. Aing Indicator(Inputs, Active Low). These inputs are similar to CTS and DCD. The Z80 DART detects both logic level transitions and interrupts the CPU. When not used in switched-line applications, these inputs can be used as general-purpose in- puts. RTSA, RTSB. Request to Send (Outputs, Active Low). When the RTS bitis set, the RTS output goes Low. When the RTS bit is reset. the output goes High after the transmitter empties. TxCA, TxCB. Transmitter Clocks (Inputs). TxD changes on the falling edge of TxC. The Transmit- ter Clocks may be 1, 16, 32 or 64 times the data rate ; however, the clock multiplier for the transmit- ter and the receiver must be the same. The Trans- mitt Clock inputs are Schmitt-triggered buffered. Both the Receiver and Transmitter Clocks may be driven by the Z80 CTC Counter Time Circuit for pro- grammable baud rate generation. TxDA, TxDB. Transmitt Data (Outputs, Active High). W/RDYA, W/RDYB. Wait/Ready (Outputs, open drain when programmed for Wait function, driven High and Low when programmed for Ready func- tion). These dual-purpose outputs may be pro- grammed as Ready lines for a DMA controller or as Wait lines that synchronize the CPU to the Z80 DART data rate. The reset state is open drain. Z8470 FUNCTIONAL DESCRIPTION The functional capabilities of the Z80 DART can be described from two different points of view : as a data communication device, it transmits and re- ceives serial data, and meets the requirements of asynchronous data communication protocols ; as a Z80 family peripheral, it interacts with the Z80 CPU and other 280 peripheral circuits, and shares the data, address and control buses, as well as being a part of the Z80 interrupt structure. As a peripheral to other microprocessors, the Z80 DART offers valu- able features such as non-vectored interrupts, poll- ing and simple hand-shake capability. The first part of the following functional description introduces Z80 DART data communications capa- bilities ; the second part describes the interaction between the CPU and the Z80 DART. The Z80 DART offers RS-232 serial communica- tions support by providing device signals for exter- nal modem control. !n addition to dual-channel Request To Send, Clear To Send, and Data Carrier Detect ports, the Z80 DART also features a dual channel Ring Indicator (RIA, RIB) input to facilitate local/remote or station-to-station communication capability. COMMUNICATIONS CAPABILITIES. The Z80 DART provides two independent full-du- plex channels receiver/transmitter. The following is a short description of receiver/transmitter capa- bilities. For more details, refer to the Asynchronous Mode section of the Z80 Family Technical Manual. The Z80 DART offers transmission and reception of five to eigh bits per character, plus optional even or odd parity. The transmitter can supply one, one and a half or two stop bits per character and can provide a break output at any time. The receiver break detection logic interrupts the CPU both at the start and end of a received break. Reception is protected from spikes by a transient spike rejection mechanism that checks the signal one-half a bit time after a Low level is detected on the Receive Data input. If the Low does not persist (as in the case of a transient) the character assembly process is not started. Framing errors and overrun errors are detected and buffered together with the character on which they occurred. Vectored interrupts allow fast servicing of interrupting conditions using dedicated routines. 77 S&S:THOMSON sia MICRC ELECT SONICS 22728470 Figure 3 : Block Diagram. INTEANAL CONTROL Logic CHANNEL A READIWRITE REGISTERS, ~ SERIAL DATA ~~ CHANNEG A _ we CHANNEL CLOCKS. | WAITIREADY HANNE, & i ae ORE UISCHETE, CONTROL AND BIATUS ae OTHER CONTROLS. eo AA ft cPU aus HO INTERNAL BUS CONTAOK my + mouEM OR pa OTHER CONTROLS CHANNEL & DISCRETE CONTROL AND ln INTERRUAT *4 CONTROL - LINES. INTERRUPT CONTROL LOGIC CIIANNEL @ READAWRITE REGISTERS STATUS + RB "SERIAL ATA --- Voc GND CLK CHANTFL B we. CHANALE CLOCK pe warrcer acy Furthermore, a built-in checking process avoids in- terpreting a framing error as a new start bit : a fram- ing error results in the addition of one-halt a bit time to the point at which the search for the next start bit is begun. The Z80 DART does not require symmetric Trans- mitt and Receive Clock signals-a-feature that allows it to be used with a Z80 CTC or any other clock source. The transmitter and receiver can handle data at a rate of 1, 1/16, 1/32 or 1/64 of the clock rate supplied to the Receive and Transmit Clock in- puts. When using Channel B, the bit rates for trans- mit and receive operations must be the same because RxC and TxC are bonded together (RxTxCB). VO INTERFACE CAPABILITIES The 280 DART offers the choice of Polling, Interrupt (vectored or non-vectored) and Block Transfer modes to transfer data, status and control informa- tion to and from the CPU. The Block Transfer mode can be implemented under CPU or DMA control. POLLING There are no interrupts in the Polled mode. Status registers RRO and RR1 are updated at appropriate times for each function being performed. All the in- terrupt modes or the Z80 DART must be disabled to operate the device in a polled environment. While in its Polling sequence, the CPU examines the status contained in RRO for each channel ; the RRO status bits serve as an acknowledge to the Poll inquiry. The two RRO status bits Do and Dz indicate that a data transfer is needed. The status also indi- 44 ir SGS-THOMSON cates Error or other special status conditions (see "Z80 DART Programming"). The Special receive Condition status contained in RR1 does not have to be read in a Polling sequence because the status bits in RR1 are accompanied by a Receive Charac- ter Available status in RRO. INTERRUPTS The Z80 DART offers an elaborate interrupts scheme that provides fast interrupt response in real- time applications. As a member of the Z80 family, the Z80 DART can be daisy-chained along with other Z80 peripherals or peripheral interrupt-priority resolution. In addition, the internal interrupts of the Z80 DART are nested to prioritize the various inter- rupts generated by Channels A and B. Channel B registers WR2 and RR2 contain the interrupt vector that ponts to an interrupt service routine in the mem- ory. To eliminate the necessity of writing a status analysis routine, the Z80 DART can modify the in- terrupt vector in RR2 so it points directly to one of eight interrupt service routines. This is done under program control by setting a program bit (WR1, D2) in Channel B called "Status Affects Vector". When this bit is set the interrupt vector in RR2 is modified according to the assigned priority of the various in- terrupting conditions. Transmit interrupts, Receive interrupts and Exter- nal/Status interrupts are the main sources of inter- rupts. Each interrupt source is enabled under program control with Channel A having a higher priority than Channel B, and with Receiver, Trans- mit and External/Status interrupts prioritized in that order within each channel. When the Transmit inter- MISROBLECTEOUSE 228rupt is enabled, the CPU is interrupted by the trans- mit buffer becoming empty. (This implies that the transmitter must have had a data character written into it so it can become empty). When enabled, the receiver can interrupt the CPU in one of three ways : = Interrupt on the first received character Interrupt on all received characters a Interrupt on a Special Receive condition Interrupt On First Character is typically used with the Block Transfer mode. interrupt On All Receive Char- acters can optionally modify the interrupt vector in the event of a parity error. The Special Receive Con- dition interrupt can occur on a character basis. The Special Receive condition can cause an interrupt only if the Interrupt On First Receive Character or Interrupt On All Receive Character mode is se- lected. In Interrupt On First Receive Character, an interrupt can occur from Special Receive conditions (except Parity Error) after the first receive character interrupt (example : Receive Overrun interrupt). The main function of the External/Status interrupt is to monitor the signal transitions of the CTS, DCD and RI pins ; however, an External/Status interrupt is also caused by the detection of a Break sequence in the data stream. The interrupt caused by the Break sequence has a special feature that allows the Z80 DART to interrupt when the Break sequence is detected or terminated. This feature facilitates the proper termination of the current message, correct initialization of the next message, and the accurate timing of the Break condition. CPU/DMA BLOCK TRANSFER The Z80 DART provides a Block Transfer mode to accomodate CPU block transfer functions and DMA block transfers (Z80 DMA or_other design). The Block Transfer mode uses the W/RDY outputin con- junction with the Wait/Ready bits of Write Regis- ter 1. The W/RDY output can be defined under software control as a Wait line in the CPU Block Transfer mode or as a Ready line in the DMA Block Transfer mode. To a DMA controller, the Z80 DART Ready output indicates that the Z80 DART is ready to transfer data to or from memory. To the CPU the Wait output in- dicates that the 280 DART is not ready to transfer data, thereby requesting the CPU to extend the I/O cycle. 28470 INTERNAL ARCHITECTURE The device internal structure includes a Z80 CPU interface, internal control and interrupt logic, and two full-duplex channels. Each channel contains read and write registers, and discrete control and status logic that provides the interface to modems or other external devices. The read and write register group includes five 8-bit control registers and two status registers. The inter- rupt vector is written into an additional 8-bit register (Write register 2) in Channel B that may be read through Read Register 2 in Channel B. The regis- ters for both channel are designated as follows : WRO-WR5-Write Register 0 through 5 RRO-RR2-Read registers 0 through 2 The bit assignment and functional grouping of each register is configured to simplify and organize the programming process. The logic for both channels provides formats, bit synchronization and validation for data transferred to and from the channel interlace. The modem con- trolinputs Clear to Send (CTS), Data Carrier Detect (DCD) and Ring Indicator (RI) are monitored by the control logic under program control. All the modem control signals are general-purpose in nature and can be used for functions other than modem con- trol. For automatic interrupt vectoring, the interrupt con- trol logic determines which channel and which de- vice within the channel has the highest priority. Priority is fixed with Channel A assigned a higher priority than Channel B ; Receive, Transmit and Ex- ternal/Status interrupts are prioritized in that order within each channel. DATA PATH The transmit and receive data path illustrated for Channel A in figure 4 is identical for both channels. The receiver has three 8-bit buffer registers in a FIFO arrangement in addition to the 8-bit receive shift register. This scheme creates additional time for the CPU to service a Receive Character Avail- able interrupt in a high-speed data transfer. The transmitter has an 8-bit transmit data register that is loaded from the internal data bus, and a 9-bit transmit shift register that is loaded from the trans- mit data register. 57 S6S:THOMSON 5/14 MICROELECTEORICE 229Z8470 Figure 4 : Data Path. 110 DATA BUFFER TRANSMIT DATA RECEIVE RECEIVE DATA ERROR p- ~- FIFO FIFO RECEIVE RaCA ] CLOCK LOGIC TRANSMIT zeit peLay [> T*PA SHIFT REGisTER | START RECEIVE TRANSMIT FA Lock Loaic [7 C4 err RECEIVE 1 oetay 3BITS >] SHIFT REGISTER ERROR (8 BITS) LOGIC READ, WRITE AND INTERRUPT TIMING READ CYCLE The timing signals generated by a Z80 CPU input instruction to read a Data or Status byte from the 280 DART are illustrated in figure 5a. Figure 5a : Read Cycle. WRITE CYCLE Figure 5b illustrates the timing and data signals generated by a Z80 CPU output instruction to write a Data or Control byte into the Z80 DART. Figure 5b : Write Cycle. ty Tz Tw 3 ty cLOCK ce eK / cHanne.appress = cE SX / CHANNEL ADDRESS x 7 tora NAA / (ona RD Ab mi M1 DATA 4 out ) DATA x IN x 6/14 (7 SGS-THOMSON 230INTERRUPT ACKNOWLEDGE CYCLE After receiving an Interrupt Request signal (INT pulled Low), the Z80_CPU sends an Interrupt Ac- knowledge signal (M1 and IORQ both Low). The daisy-chained interrupt circuits determine the hig- hest priority interrupt requestor. The IEI of the hig- hest priority peripheral is terminated High. For any peripheral that has no interrupt pending or under service, IEO = IEI. Any peripheral that does have an interrupt pending or under service forces its IEO Low. To insure stable conditions in the daisy chain, all in- terrupt status signals are prevented from changing while M1 is Low. When IORQ is Low, the highest priority interrupt requestor (the one with IEI High) places its interrupt vector on the data bus and sets its internal interrupt-under-service latch. Refer to the 280 Family Technical Manual tor addi- tional details on the interrupt daisy chain and inter- rupt nesting. RETURN FROM INTERRUPT CYCLE Normally, the Z80 CPU issues a RETI (Return From Interrupt) instruction at the end of an interrupt ser- vice routine. RETI is a 2-byte opcode (ED-4D) that resets the interrupt-under-service latch to terminate the interrupt that has just been processed. When used with other CPUs, the Z80 DART allows the user to return from the interrupt cycle with a spe- cial command called Return From Interrupt" in Write Register 0 of Channel A. This command is in- terpreted by the Z80 DART in exactly the same way it would interpret a RETI command on the data bus. Figure 5c : Interrupt Acknowledge Cycle. 28470 Figure 5d : Return from Interrupt Cycle. Z80 DART PROGRAMMING To program the Z80 DART, the system program first issues a series of commands that initialize the basic mode and then other commands that qualify condi- tions within the selected mode. For example, the character length, clock rate, number of stop bits, even or odd parity are first set, then the Interrupt mode and, finally, receiver or transmitter enable. Both channels contain command registers that must be programmed via the system program prior to operation. The Channel Select input (B/A) and the Control/Data input (C/D) are the command structure addressing controls, and are normally controlled by the CPU address bus. WRITE REGISTERS The 280 DART contains six registers (WRO-WRS5) in each channel that are programmed separately by the system program to configure the functional per- sonality of the channels (figure 4). With the excep- tion of WRO, programming the write registers requires two bytes. The first byte contains three bits (Do-Dz} that point to the selected register ; the sec- ond byte is the actual control word that is written into the register to configure the Z80 DART. WR is a special case in that all the basic commands (CMDo-CMDz) can be accessed with a single byte. Reset (internal or external) initializes the ponter bits Do-De to point to WRO. This means that a register DATA (vector \ cannot be pointed to in the same operation as a channel reset. SGS-THOMSON ms ki SY wicaox.sersan:cs 23128470 Write Register Functions WRO Register Pointers, Initialization Commands for the Various Modes, etc. WR1 Transmit/Receive Interrupt and Data Transfer Mode Definition WR2 Interrupt Vector (Channel B only) WR3 Receive Parameters and Control WR4 Transmit/Receive Miscellaneous Parameters and Modes WRS5 Transmit Parameters and Controls READ REGISTERS The Z80 DART contains three registers (RRO-RR2) that can be read to obtain the status information for each channel (except for RR2, which applies to Channel B only). The status information includes error conditions, interrupt vector and standard com- munications-interface signals. 8/14 ky SGS-THOMSON To read the contents of a selected read register other than RRO, the system program must first write the pointer byte to WRO in exactly the same way as a write register operation. Then, by executing an input instruction, the contents of the addressed read register can be read by the CPU. The status bits of RRO and RR1 are carefully grouped to simplify status monitoring. For example, when the interrupt vector indicates that a Special Receive Conditions interrupt has occurred, all the appropriate error bits can be read from a single reg- ister (RR1). Read Register Functions RRO Transmit/Receive Buffer Status, Interrupt Status and External Status RRt Special Receive Condition Status RR2 Modified Interrupt Vector (channel B only) Mi SROBLEST ROK ICS 232Z80 DART READ AND WRITE REGISTERS 28470 READ REGISTER 0 [o,]0,]o.:0.[,]es]0, [>] 2 WRITE REGISTER 2 (CHANNEL B ONLY) v3 INTEARUPT va VECTOR v5 v6 vw? WHITE REGISTER 4 [eos JaTe [Tor T0.77] LL parivy ENABLE PARITY EVEN/ODD NOT USED 1 STOP BITICHARACTER t% STOP BITSICHARACTER 2 STOP BITSICHARACTER NOT USEO 4 X1 CLOCK MODE X16 CLOCK MODE X32 CLOCK MODE X64 CLOCK MODE READ REGISTER t* READ REGISTER 2 [o,}>s]s Te [osi0,[0,]>] LL ax CHARACTER AVAILABLE ALL SENT L. ve INT PENDING (CH. A ONLY) NOT USED vee + Tx BUFFER EMPTY PART ERROR 3 pco Ax OVERAUN ERROR a NE oo A FRAMING ERROR va 5 USED WITH EXTERNAL, v = crs STATUS INTERRUPT" NOT USED 5 _.. NOT USFO MODE *Used With Specia Receive Condition Mace Vb BREAK vr cw tVanable i Status Ater's Vector 35 Programme? WHITE REGISTER 0 WHITE REGISTER 1 [Tos Tor Is. [osToTo [es] Taye a ~To 0 0 0 REGISTERS | EXT INT ENABLE 0 0 1 REGISTER Tx INT ENABLE y Oo REGISTER? STATUS AFFECTS VECTOR 0 1 4 REGISTERS (CH. B ONLY) 1 9 0 REGISTERS 1 0 1 REGISTERS 00 Rains Uisance f RxINT ON FIRST CHARACTER OR ON INT ON ALL Rx CHARACTERS (PARITY | special AFFECTS VECTOR} RECEIVE 9 0 G9 NULL CODE 1 4 INT ON ALL Ax CHARACTERS (PARITY | CONDITION oo 1 NOT USEO DOES NOT AFFECT VECTOR) + 0 RESET EXTISTATUS INTERRUPTS . 1 1 CHANNEL RESET WAITIREADY ON AT 1 0 0 ENABLE INT ON NEXT Rx CHARACTER - 1 @ 1. AESET TINT PENDING L WAITIREADY FUNCTION 1 + o ERROR RESET WAITIREADY ENABLE 1 1 1 RETURN FROM INT (CH.A ONLY) NOT USED WRITE REGISTER 3 L Ax ENABLE NOT USED (MUST BE PROGRAMMED 0) AUTO ENABLES 0 = - AK SBITSICHARACTER 1 Rx? BITSICHARACTER a 1 , Aix 6 BITSICHAAACTER Aix 8 BITSICHARACTER awae WRITE REGISTER 5 ESCOESCRESCN CH NOT USED RIS NOT USED Tx ENABLE SEND BREAK Tx 5 BITS (OA LESSVCHAAACTER Tx 7 BITSICHARACTER: Tx 8 BITS/CHARACTER Tx @ BITSICHARACTER oR = yecTog &r SGS-THOMSON 9/14 MICROELECTRONICS 23328470 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vi Voltage on all Inputs and Outputs with Respect to GND 0.3 to + 7.0 Vv Ta Operating Ambient Temperature As Specified in Ordering Information Tstg Storage Temperature 65 to + 150 Cc Stresses greater than those listed under Absolute Maximun Ratings may cause permanent damage to the device. This is a stress rating only ; operation of the device at any condition above those indicated in the operational sections of these specifications is not im- plied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TEST CONDITIONS The characteristics below apply for the following test asy conditions, unless otherwise noted. All voltages are referenced to GND (OV). Positive current flows into 21K the referenced pin. Available operating temperature FROM OUTPUT ranges are: UNGER TEST = 0'Cto+ 70C, +4.75V< Veo <+5.25V 100 pF 250 a 40 C to + 85C, . +4.75V<Veco<+5.25V =a 55C to+ 125C, a = +45V<Vecos+55V DC CHARACTERISTICS Symbol Parameter Test Conditions Min. Max. Unit Vitec Clock Input Low Voltage -0.3 | +045 Vv Vinc Clock Input High Voltage Voc -0.6] + 5.5 Vv Vic Input Low Voltage - 0.3 +08 Vv Vin Input High Voltage + 2.0 +55 Vv VoL Output Low Voltage lo, = 2.0 mA +04 v Vou Output High Voltage lon = 250 pA +24 Vv IL Input/3-State Output Leakage Current 04<V<24V -10 +10 pA Linn RI Pin Leakage Current O< Vin < Veco - 40 +10 uA lec Power Supply Current 100 mA Ta = 0 Ct0 70 C, Voc = 5VE5%, 1o"n4 [7 SGS-THOMSON YF sicromscrnemes 234AC CHARACTERISTICS 28470 Ca, CO, WA j il int wrRDy Kaz SGS-THO vy Semone 11/14 23528470 AC CHARACTERISTICS (continued) Z8470, | Z8470A | Z28470B Ne Symbol Parameter Min. |Max.| Min. |Max.| Min. |Max. (ns) | (ns) | (ns) | (ns) | (ns) | (ns) 1 TcC Clack Cycle Time 400 |4000] 250 | 4000] 165 |4000 2 TwCh Clock Width (high) 4170 |2000) 105 |2000] 70 |2000 3 TIC Clock Fall Time 30 30 15 4 Trc Clock Rise Time 30 30 15 5 TwCl Clock Width (low) 170 |2000| 105 |2000| 70 |2000 6 TsAD(C) CE, C/D, B/A to Clock T Setup Time 180 145 60 7 TsCS(C) IORQ, RD, to Clock 7 Setup Time 240 115 60 8 TdC(DO) Clock T to Data Out Delay 240 220 150 9 TsDI(C) Data in to Clock T Setup Time (write or MI cycle) 50 50 30 10 TdRD(DOz) RD 7 to Data Out Float Delay 230 110 90 am TdlO(DOl IORQ | to Data Out Delay (INTACK cycle) 340 160 100 12 TsM\(C) MI to Clock T Setup Time 210 90 75 13 TsIEIIO) IEl to IORQ L Setup Time (INTA cycle) 200 140 120 14] TdMI(IEO) MI J to IEO J Delay (interrupt before Mi) 300 190 160 15 Td EI(IEOr) IEI T to IEO T Delay (after ED decode) 150 100 70 16 Td EWEOF) EI 1 to IEO 1 Delay 150 100 70 17 TdC(INT) Clock 7 to INT J Delay 200 200 150 18] Tdlo(w/RWt) | IORQ . or CE 1 to W/RDY ~ Delay (wait mode) 300 210 175 19 TdC(W/RR} Clock T to W/RDY ~ Delay (ready mode) 120 120 100 20} TdC(W/RWz) Clock | to W/RDY Float Delay (wait mode) 150 130 110 12/14 236AC CHARACTERISTICS (continued) 28470 CTs, OCD, SYNC Tat WIRDY winDy Int AC CHARACTERISTICS (continued) Z8470 | Z8470A | Z8470B Ne Symbol Parameter Unit Min. |Max.| Min. |Max.| Min. |Max. (ns) | (ns) | (ns) | (ns) | (ns) | (ns) 1 TwPh Pulse Width (high) 200 200 200 2 TwPI Pulse Width (low) 200 200 200 3 TeTxC Tx Cycle Time 400] - | 400] | 330] 4 TwTxCl TxC Width (low) 180 | | 180| | 100] o 5 TwTxCh TxC Width (high) 180 | ~ | 180] | 100] o 6 | TdTxC(TxD) | TxC | to TxD Delay 400 300 220 7 | TdTxC(wRRf) | TxC J to WRDY J Delay Ck Periods | 5 | 9 | 5 | 9 | 5 | 8 (ready mode) 8 | TdTxC(INT) | TxC J to INT J Delay Clk Periods | 5 | 9 | 5 | 9 |] 5 |] 9 9 TcRxC RxC Cycle Time 400 | | 400] = | 330] 10 TwRxCl RxC Width (low) 180] | 180] | 100] 11 TwRxCh RxC Width (high) 180 | | 180} | 100] o 12 TsRxD(RxC) RxD to RxC T Setup Time (xl mode) 0 0 0 13 ThRxD(RxC) | RxD Hold Time (x| mode) 140 140 100 14| TdRxC(WARRf) | RAxC T to WRDY J Delay Clk Periods | 10 | 13 | 10 | 13 | 10 | 13 (ready mode) 15| TdRxC(INT) | Rx T to INT J Delay Clk Periods | 10 | 12 | 10 | 13 | 10 | 13 37 S65:THOMSON = 237Z8470 ORDERING INFORMATION Type Package Temp. Clock Description 28470B1 DIP-40 (plastic) O/+ 70C Z80 Dual 28470F1 DIP-40 (frit seal) O/+ 70C Channel 2847001 DIP-40 (ceramic) O/+ 70C 2.5 MHz Asynchronous 28470D6 DIP-40 (ceramic) 40/+ 86C . Receiver 28470D2 DIP-40 (ceramic) 66/ + 125C Transmitter Z8444C1 PLCC44 (plastic chip-carrier) Of/+ 70C 28470AB1 DIP-40 (plastic) O/+ 70C Z8470AF1 DIP-40 (frit seal) O/+ 70C Z8470AD1 DIP-40 (ceramic) O/+ 70C 4 MHz Z8470AD6 DIP-40 (ceramic) 40/+ 85C Z8470AD2 DIP-40 (ceramic) 55/+ 126C Z8444AC1 PLCC44 (plastic chip-carrier) O/+ 70C 2Z8470BB1 DIP-40 (plastic) O/+ 70C Z8470BF1 DIP-40 (frit seal) 0/+ 70C Z8470BD1 DIP-40 (ceramic) O/+ 70C 6 MHz 2Z8470BD6 DIP-40 (ceramic) 40/+ 85C 28470BD2 DIP-40 (ceramic) 6/ + 125C Z8444BC1 PLCC44 (plastic chip-carrier) O/+ 70C 14/14 SGS-THOMSON 238 ky MICROELECTRONICS