Data Sheet
26185.202
8-BIT SERIAL-INPUT, CONSTANT-
CURRENT LATCHED LED DRIVER
Always order by complete part number, e.g., A6277EA .
The A6277x is specifically designed for LED-display applications.
Each BiCMOS device includes an 8-bit CMOS shift register, accompa-
nying data latches, and eight npn constant-current sink drivers. Two
package styles and two operating temperature ranges are available.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V logic supply, typical serial
data-input rates are up to 20 MHz. The LED drive current is deter-
mined by the user’s selection of a single resistor. A CMOS serial data
output permits cascade connections in applications requiring additional
drive lines. For inter-digit blanking, all output drivers can be disabled
with an ENABLE input high. In addition, a HIGH/LOW function
enables full selected current with the application of a logic low, or 50%
selected current with the application of a logic high.
The first character of the part number suffix determines the device
operating temperature range. Suffix ‘E–’ is for -40°C to +85°C, and
suffix ‘S–’ is -20°C to +85°C. Two package styles are provided for
through-hole DIP (suffix ‘–A’) or surface-mount SOIC (suffix ‘–LW’)
applications. The copper lead frame and low logic-power dissipation
allow the dual in-line package to sink 122 mA through all outputs
continuously over the operating temperature range (1.0 V drop,
+85°C).
Note that the A6277EA (DIP) and the A6277ELW
(SOIC) are electrically identical and share a
common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD ...................... 7.0 V
Output Voltage Range,
VO............................ -0.5 V to +24 V
Output Current, IO.......................150 mA
Input Voltage Range,
VI.................... -0.4 V to VDD + 0.4 V
Package Power Dissipation,
PD..................................... See Graph
Operating Temperature Range, TA
Suffix ‘S-’ ................ -20°C to +85°C
Suffix ‘E-’................ -40°C to +85°C
Storage Temperature Range,
TS........................... -55°C to +150°C
Caution: These CMOS devices have input
static protection (Class 2) but are still suscep-
tible to damage if exposed to extremely high
static electrical charges.
6277
FEATURES
■To 150 mA Constant-Current Outputs
■Under-Voltage Lockout
■Low-Power CMOS Logic and Latches
■High Data Input Rate
■Similar to Toshiba TD62715FN
■High/Low Output Current Function
Digital “Dim” Control
A6277ELW
REGISTER
LATCHES
5
10 11
12
13
14
15
6
7
8
9
16
POWER
GROUND
POWER
GROUND
HIGH/LOW
(CURRENT)
OUT
1
OUT
2
Dwg. PP-029-17A
OUT
0
OUT
4
OUT
6
OUT
5
OUT
3
OUT
7
LOGIC
GROUND 1
2
3
17
19
4
18
20
SERIAL
DATA OUT
LOGIC
SUPPLY
SERIAL
DATA IN
OUTPUT
ENABLE
LATCH
ENABLE
CLOCK CK
V
DD
OE
R
EXT
I
REGULATOR
L
O
SUB SUB
SERIAL
DATA OUT
2
1
FF
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
2
Copyright © 2001, Allegro MicroSystems, Inc.
50 75 100 125 150
2.5
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN °C
2.0
1.5
1.0
25
SUFFIX 'A', R = 55°C/W
θJA
Dwg. GP-018-1
SUFFIX 'LW', R = 70°C/W
θJA
FUNCTIONAL BLOCK DIAGRAM
MOS
BIPOLAR
LOGIC
GROUND
LATCH
ENABLE
OUTPUT ENABLE
(ACTIVE LOW)
SERIAL DATA
OUT
CLOCK
SERIAL
DATA IN SERIAL-PARALLEL SHIFT REGISTER
LATCHES
VDD LOGIC
SUPPLY
R
OUT0OUT1
Dwg. FP-013-7
OUT2OUTN
I
REGULATOR
O
UVLO
POWER
GROUND
POWER
GROUND SUB
HIGH/LOW
(CURRENT)
FF
SERIAL DATA
OUT
EXT
1
2
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
www.allegromicro.com
3
TRUTH TABLE
Serial Shift Register Contents Serial Latch Latch Contents Output Output Contents
Data Clock Data Enable Enable
Input Input I1I2I3... IN-1 INOutput Input I1I2I3... IN-1 INInput I1I2I3... IN-1 IN
HHR
1R2... RN-2 RN-1 RN-1
LLR
1R2... RN-2 RN-1 RN-1
XR
1R2R3... RN-1 RNRN
XXX...X X X L R
1R2R3... RN-1 RN
P1P2P3... PN-1 PNPNHP
1P2P3... PN-1 PNLP
1P2P3... PN-1 PN
X X X ... X X H H H H ... H H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
CLOCK and SERIAL DATA IN SERIAL DATA OUT
LATCH ENABLE and HIGH/LOWOUTPUT ENABLE (active low)
Dwg. EP-010-11
IN
VDD
Dwg. EP-010-12
IN
VDD
Dwg. EP-010-13
IN
VDD
V
DD
Dwg. EP-063-6
OUT
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
4
ELECTRICAL CHARACTERISTICS at TA = +25°C, VH/L = VDD = 5 V (unless otherwise noted).
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Supply Voltage Range VDD Operating 4.5 5.0 5.5 V
Under-Voltage Lockout VDD(UV) VDD = 0 to 5 V 3.4 – 4.0 V
Output Current IOVCE = 1.0 V, REXT = 160 Ω100 120 140 mA
(any single output) VCE = 0.4 V, REXT = 470 Ω34 42 48 mA
Output Current Matching ∆IO0.4 V ≤ VCE(A) = VCE(B) ≤ 1.0 V:
(difference between any REXT = 160 Ω–±1.5 ±6.0 %
two outputs at same VCE)REXT = 470 Ω–±1.5 ±6.0 %
Output Leakage Current ICEX VOH = 20 V – 1.0 5.0 µA
Logic Input Voltage VIH 0.7VDD ––V
VIL – – 0.3VDD V
SERIAL DATA OUT Voltage VOL IOL = 1.0 mA – – 0.4 V
(SDO1 & SDO2)VOH IOH = -1.0 mA 4.6 – – V
Input Resistance RIENABLE input, pull up 150 300 600 kΩ
LATCH & HIGH/LOW inputs, pull down 100 270 400 kΩ
Supply Current IDD(OFF) REXT = open, VOE = 5 V – 0.8 1.6 mA
REXT = 470 Ω, VOE = 5 V 3.5 6.5 9.5 mA
REXT = 160 Ω, VOE = 5 V 14 17 22 mA
IDD(ON) REXT = 470 Ω, VOE = 0 V 5.0 10 15 mA
REXT = 160 Ω, VOE = 0 V 20 27 40 mA
Typical Data is at VDD = 5 V and is for design information only.
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
www.allegromicro.com
5
RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Conditions Min. Typ. Max. Unit
Supply Voltage VDD 4.5 5.0 5.5 V
Output Voltage VO– 1.0 4.0 V
Output Current IOContinuous, any one output – – 150 mA
IOH SERIAL DATA OUT – – -1.0 mA
IOL SERIAL DATA OUT – – 1.0 mA
Logic Input Voltage VIH 0.7VDD –– V
VIL – – 0.3VDD V
Clock Frequency fCK Cascade operation – – 10 MHz
SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V,
REXT = 470 Ω, IO = 40 mA, VL = 3 V, RL = 65 Ω, CL = 10.5 pF.
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Propagation Delay Time tpHL CLOCK-OUTn– 350 1000 ns
LATCH-OUTn– 350 1000 ns
ENABLE-OUTn– 350 1000 ns
CLOCK-SERIAL DATA OUT1–40– ns
Propagation Delay Time tpLH CLOCK-OUTn– 300 1000 ns
LATCH-OUTn– 400 1000 ns
ENABLE-OUTn– 380 1000 ns
CLOCK-SERIAL DATA OUT2–40– ns
Output Fall Time tf90% to 10% voltage 150 250 1000 ns
Output Rise Time tr10% to 90% voltage 150 250 600 ns
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
6
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D).......................................... 60 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 20 ns
C. Clock Pulse Width, tw(CK) ............................................... 50 ns
D. Time Between Clock Activation
and Latch Enable, tsu(L) ............................................ 100 ns
E. Latch Enable Pulse Width, tw(L) ................................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 µs
NOTE – Timing is representative of a 10 MHz clock.
Significantly higher speeds are attainable.
—Max. Clock Transition Time, tr or tf.............................. 10 µs
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-to-
parallel conversion). The latches will continue to accept new
data as long as the LATCH ENABLE is held high. Applica-
tions where the latches are bypassed (LATCH ENABLE tied
high) will require that the OUTPUT ENABLE input be high
during serial data entry.
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
CLOCK
SERIAL
DATA IN
LATCH
ENABLE
OUTPUT
ENABLE
OUTN
Dwg. WP-029-3
50%
SERIAL
DATA OUT.
1
DATA
DATA
50%
50%
50%
C
A B
D E
LOW = ALL OUTPUTS ENABLED
p
t
DATA
50%
p
t
LOW = OUTPUT ON
HIGH = OUTPUT OFF
SERIAL
DATA OUT.
2DATA50%
p
t
OUTPUT
ENABLE
OUT
N
Dwg. WP-030-1
DATA
10%
50%
dis(BQ)
t
F
en(BQ)
t
HIGH = ALL OUTPUTS DISABLED (BLANKED)
f
t
r
t
90%
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
www.allegromicro.com
7
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE
A6277xA A6277xLW
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-17
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
80
T
A
= +25°C
V
DD
= 5 V
Rθ
JA
= 55°C/W
120
140 V
CE
= 1 V
V
CE
= 2 V
V
CE
= 4 V
V
CE
= 3 V
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-15
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 3 V
V
CE
= 4 V
80
T
A
= +50°C
V
DD
= 5 V
Rθ
JA
= 55°C/W
120
140 V
CE
= 1 V
V
CE
= 2 V
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-14
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 4 V
80
T
A
= +50°C
V
DD
= 5 V
R
θ
JA
= 70°C/W
120
140 V
CE
= 1 V
V
CE
= 2 V
V
CE
= 3 V
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-16
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 4 V
80
T
A
= +25°C
V
DD
= 5 V
Rθ
JA
= 70°C/W
120
140
V
CE
= 2 V
V
CE
= 3 V
V
CE
= 1 V
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
8
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-13
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 3 V
V
CE
= 4 V
80
T
A
= +85°C
V
DD
= 5 V
Rθ
JA
= 55°C/W
120
140
V
CE
= 1 V
V
CE
= 0.7 V
V
CE
= 2 V
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-12
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 2 V
V
CE
= 3 V
V
CE
= 4 V
80
T
A
= +85°C
V
DD
= 5 V
R
θ
JA
= 70°C/W
120
140
V
CE
= 1 V
V
CE
= 0.7 V
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
A6277xA A6277xLW
TYPICAL CHARACTERISTICS
0.5
Dwg. GP-063-1
1.0 2.0
1.5
V
CE
IN VOLTS
0
60
40
OUTPUT CURRENT IN mA/BIT
20
0
T
A
= +25°C
R
EXT
= 470 Ω
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
www.allegromicro.com
9
TERMINAL DESCRIPTION
Terminal No. Terminal Name Function
1 LOGIC GROUND Reference terminal for control logic.
2 SERIAL DATA IN Serial-data input to the shift-register.
3 CLOCK Clock input terminal for data shift on rising edge.
4 LATCH ENABLE Data strobe input terminal; serial data is latched with high-level input.
5 HIGH/LOW Logic low for 100% of programmed current level;
(CURRENT) logic high for 50% of programmed current level.
6 POWER GROUND Ground.
7-14 OUT0-7 The eight current-sinking output terminals.
15 POWER GROUND Ground.
16 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
17 SERIAL OUT2CMOS serial-data output (on clock falling edge).
18 SERIAL OUT1CMOS serial-data output (on clock rising edge)
to the following shift-registers.
19 REXT An external resistor at this terminal establishes the output current for all sink
drivers.
20 LOGIC SUPPLY (VDD) The logic supply voltage. Typically 5 V.
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
10
The load current per bit (IO) is set by the external resistor
(REXT) as shown in the figure below.
Package Power Dissipation (PD). The maximum allow-
able package power dissipation is determined as
PD(max) = (150 - TA)/RθJA.
The actual package power dissipation is
PD(act) = dc(VCE • IO • 8) + (VDD • IDD).
When the load supply voltage is greater than 3 V to 5 V,
considering the package power dissipating limits of these
devices, or if PD(act) > PD(max), an external voltage
reducer (VDROP) should be used.
Load Supply Voltage (VLED). These devices are de-
signed to operate with driver voltage drops (VCE) of 0.4 V
to 0.7 V with LED forward voltages (VF) of 1.2 V to
4.0 V. If higher voltages are dropped across the driver,
package power dissipation will be increased significantly.
To minimize package power dissipation, it is recom-
mended to use the lowest possible load supply voltage or
to set any series dropping voltage (VDROP) as
VDROP = VLED - VF - VCE
with VDROP = Io • RDROP for a single driver, or a Zener
diode (VZ), or a series string of diodes (approximately
0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
provide supply voltages as low as 3.3 V.
For reference, typical LED forward voltages are:
Blue 3.0 – 4.0 V
Green 1.8 – 2.2 V
Yellow 2.0 – 2.1 V
Amber 1.9 – 2.65 V
Red 1.6 – 2.25 V
Infrared 1.2 – 1.5 V
Pattern Layout. This device has separate logic-ground
and power-ground terminals. If ground pattern layout
contains large common-mode resistance, and the voltage
between the system ground and the LATCH ENABLE or
CLOCK terminals exceeds 2.5 V (because of switching
noise), these devices may not operate correctly.
Dwg. EP-064
VLED
VDROP
VF
VCE
Applications Information
300 500 700 1 k 2 k
CURRENT-CONTROL RESISTANCE, R
EXT
IN OHMS
100
0100
Dwg. GP-061-1
OUTPUT CURRENT IN mA/BIT
5 k
200 3 k
20
40
60
80
V
CE
= 0.7 V
120
140
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
www.allegromicro.com
11
A6277EA
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 18 devices.
0.014
0.008
0.300
BSC
Dwg. MA-001-20 in
0.430
MAX
20
110
0.280
0.240
0.210
MAX
0.070
0.045
0.015
MIN
0.022
0.014
0.100
BSC
0.005
MIN
0.150
0.115
11
1.060
0.980
0.355
0.204
7.62
BSC
Dwg. MA-001-20 mm
10.92
MAX
20
110
7.11
6.10
5.33
MAX
1.77
1.15
0.39
MIN
0.558
0.356
2.54
BSC
0.13
MIN
3.81
2.93
11
26.92
24.89
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
12
A6277ELW
Dimensions in Inches
(for reference only)
Dimensions in Millimeters
(controlling dimensions)
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 37 devices or add “TR” to part number for tape and reel.
0° TO 8°
1 2 3
0.020
0.013
0.0040 MIN.
0.0125
0.0091
0.050
0.016
Dwg. MA-008-20 in
0.050
BSC
20 11
0.2992
0.2914 0.419
0.394
0.5118
0.4961
0.0926
0.1043
0°
TO
8°
1
20
23
0.51
0.33
0.10
MIN.
Dwg. MA-008-20 mm
1.27
BSC
11 0.32
0.23
1.27
0.40
7.60
7.40 10.65
10.00
13.00
12.60
2.65
2.35
