AS1524-BTDR - Austriamicrosystems

AS1524/AS1525

150ksps, 12-Bit, 1-Channel Pseudo/True-Differential

and 2-Channel Single-Ended ADCs

www.austriamicrosystems.com Revision 1.02 1 - 22

Datasheet

1 General Description

The AS1524/AS1525 are low-power, 12-bit analog-to-

digital converters (ADCs) designed to operate with a sin-

gle +2.7V to +5.25V supply. Excelle nt dynamic perfor-

mance, low power consumption, and simplicity make

these devices perfect for portable battery-powered data-

acquisition applications.

The devices are available as the standard prod ucts

listed in Table 1.

The devices feature a successive-approximation regis-

ter (SAR), automatic shutdown, fast wakeup (1.4µs),

and low-power consumption at the maximum sampling

rate of 150ksps.

Automatic shutdown (0.2µA) between conversions

results in reduced power consumption (at slower

throughput rates).

Data access are made via an external clock through the

SPI-/QSPI-/MICROWIRE-compatible 3-wire high-speed

serial interface.

The AS1525/AS1524 are available in a 8-pin TDFN

(3x3mm) package.

Figure 1. AS1524/AS1525 - Block Diagram

2 Key Features

! Single-Supply Operation: +2.7V to +5.25V

! Automati c Shutdown Between Conversions

! Low Power Consumption

- 350µA @ 150ksps

- 245µA @ 100ksps

-24µA @ 10ksps

- 2.5µA @ 1ksps

- 200nA in Automatic Shutdown Mode

! T rue-Differential T rack/Hold, 150kHz Sampling Rate

Software-Configurable Unipolar/Bipolar Conversion

(AS1524)

! Input Common Mode Range from GND to VDD

! 3-Wire SPI-/QSPI-/MICROWIRE-Compatible Serial

Interface

! Internal Conversion Clock

! 8-pin TDFN (3x3mm) Package

3 Applications

The devices are ideal for remote sensors, data-acquisi-

tion, data logging devices, lab instruments, or for any

other space-limited A/D devices with low power con-

sumption and single-supply requirements.

Table 1. Standard Products

Model Input Type Input Voltage

AS1524 1-Channel, Pseudo /

True-Differential 0 to VREF /

-VREF/2 to VREF/2

AS1525 2-Channel, Single-

Ended 0 to VREF

AS1524/AS1525

Control

Logic

Input

Shift

Osc

Track/

Hold 6

DOUT

GND

VDD

CNVST

SCLK

REF

12-Bit

SAR

AIN1/AIN+

AIN2/AIN-

www.austriamicrosystems.com Revision 1.02 2 - 22

AS1524/AS1525

Datasheet

Contents

1 General Description ............................................................................................................................. 1

2 Key Features ........................................................................................................................................ 1

3 Applications .......................................................................................................................................... 1

4 Pinout ................................................................................................................................................... 3

Pin Assignment ........... ... ... .................................................................................................................................. 3

Pin Description ............................................................................................................ ... ...................................... 3

5 Absolute Maximum Ratings ................................................................................................................. 4

6 Electrical Characteristics ...................................................................................................................... 5

Timing Characteristics ......................................................................................................................................... 7

7 Typical Operating Characteristics ........................................................................................................ 8

8 Detailed Description ...................................................................................................................... ... .. 11

True Differential Analog Input Track/Hold .......................................................................................................... 11

Selecting AIN1 or AIN2 (AS1525) ......................................................................................................................11

Selecting Unipolar or Bipolar Conversions (AS1524) .........................................................................................12

Input Bandwidth ..................................................................................................................................................13

Analog Input Protection ......................................................................................................................................13

Internal Clock ........................................................................................ ... .. .........................................................13

Output Data Format ................ ... ................................................................................. ......... ...............................13

Transfer Function ................................................................................................................................................13

9 Application Information .......................................................................................................................15

Automatic Shutdown Mode .................................................................................................................................15

External Reference ............ .. ........................................................... ... ... ................... ... ... .....................................15

Performing a Conversion ................... ... ... ...................... ....................... ...................... ........................................15

Standar d Interface Connections ..........................................................................................................................15

SPI and Microwire Interface........................................................................................................................... 15

QSPI Interface ................................................................................................................................................16

PIC16 and SSP Module and PIC17 Interface ................................................................................................17

Layout and Grounding Considerations .............................................................................................................. 19

10 Package Drawings and Markings .................................................................................................... 20

11 Ordering Information ........................................................................................................................ 21

www.austriamicrosystems.com Revision 1.02 3 - 22

AS1524/AS1525

Datasheet - Pin o u t

4 Pinout

Pin Assignment

Figure 2. Pin Assignments (Top View)

Pin Description

Table 2. Pin Description

Pin Number Pin Name Description

1 VDD Positive Supply Voltage. +2.7V to +5.25V.

Note: Bypass with a 0.1µF capacitor to GND.

2AIN1/AIN+

Analog Input Channel 1 (AS1525) or Positive Analog Input (AS1524)

3AIN2/AIN-

Analog Input Channel 2 (AS1525) or Negative Analog Input (AS1524)

4GND

Ground

5REF

External Reference Voltage Input. Sets the analog voltage range.

Note: Bypass with a 4.7µF capacitor to GND.

6 CNVST

Conversion Start. A rising edge powers up the device and puts the track/

hold circuitry in track mode. At the falling edge of this pin, the device enters

hold mode and begins a conversion.

Note: This pin also selects the input channel (AS1525) or input polarity

(AS1524).

7DOUT

Serial Data Output. This pin transitions the falling edge of SCLK and go es

low at the start of a conversion and delivers the MSB at the completion of a

conversion.

Note: This pin goes high impedance once data has been fully clocked out.

8SCLK

Serial Clock Input. Clocks out data at DOUT with the MSB first.

AS1524/

AS1525

GND

3AIN2/AIN-

2AIN1/AIN+

VDD

5REF

7DOUT

8SCLK

6CNVST

www.austriamicrosystems.com Revision 1.02 4 - 22

AS1524/AS1525

Datasheet - Ab so lu te Ma xi mu m R at in gs

5 Absolute Maximum Ratings

Stresses beyo n d th o s e li st ed in Table 3 may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated in Electri cal Chara cter-

istics on page 5 is not implied. Exposure to absolute maximum rating conditions for extended pe riods may affect

device reliability.

Table 3. Absolute Maximum Ratings

Parameter Min Max Units Comments

VDD to GND -0.3 +6 V

CNVST, SCLK, DOUT, REF, AIN1/

AIN+, AIN2/AIN- to GND -0.3 VDD +

0.3 V

Current into Any Pin 50 mA

Continuous Power Dissipation 1491 mW TAMB = +70ºC; derate 19.5mW/ºC above +70ºC

Operating Temperature Range -40 +85 ºC

Storage Temperature Range -60 +150 ºC

Package Body Tempe ra ture +260 ºC

The reflow peak soldering temperature (body

temperature) specified is in accordance with

IPC/JEDEC J-STD-020D “Moisture/Reflow

Sensitiv ity Cl assification for Non-Hermetic Solid

State Surface Mount Devices”.

The lead finish for Pb-free leaded packages is

matte tin (100% Sn).

www.austriamicrosystems.com Revision 1.02 5 - 22

AS1524/AS1525

Datasheet - Ele c t r i c a l C h a r a c t e r i s t i c s

6 Electrical Characteristics

VDD = +2.7 to +5.25V, VREF = +2 .5V, 4.7µF Ca pacitor at REF; f SCLK = 8MHz (50% Duty Cycle); AIN- = GND (AS1524)

TAMB = TMIN to TMAX (unless otherwise specified). Typical Values at TAMB = +25ºC. Unipolar Mode (AS1524).

Table 4. Electrical Characteristics

Symbol Parameter Condition Min Typ Max Unit

DC Accuracy

Resolution 12 Bits

INL Relative Accuracy ±1.0 LSB

DNL Differential Non-Lineraity No Missing Codes Over Temp erature -0.99 +1.0 LSB

Offset Error ±1 ±4 LSB

Gain Error 1±1 ±4 LSB

Gain Temp Coefficient ±0.3 ppm/ºC

Offset Temp Coefficient ±0.3 ppm/ºC

Channel-to-Channel Offset

Match ±0.1 LSB

Channel-to-Channel Gain

Match ±0.1 LSB

Dynamic Specifications – (fIN (sinewave) = 10kHz, VIN = 2.5VP-P, 150ksps, fSCLK = 8MHz (50% duty cycle), AIN- =

GND (AS1524)

SINAD Signal-to-Noise Plus Distortion 72.5 dB

THD Total Harmonic Distortion (to

the 5th Harmonic) -79.5 dB

SFDR Spurious-Free Dynami c Range 84 dB

Full Power Bandwidth -3dB Point 20 MHz

Full Linear Bandwidth -0.1dB Point 400 kHz

Conversion Rate

tCONV Conversion Time Exclusive of tACQ 3.3 3.7 µs

tACQ Track/Hold Acquisition Time 1.4 µs

Aperture Delay 30 ns

fSCLK Max Serial Clock Frequency 8 MHz

Serial Clock Duty Cycle 30 70 %

Analog Input

VIN Range 2Unipolar 0 VREF V

Bipolar -VREF/2 VREF/2

Input Leakage Current No Channel Selected or Conversion

Halted ±0.01 ±1 µA

Input Capacit ance Track Mode 20 pF

Hold Mode 5 pF

External Reference Input

VREF VIN Range 1.0 VDD +

50mV V

IREF Input Current

VREF = +2.5V @ 150ksps 11 25

µAVREF = +4.096V @ 150ksps 19

Acquisition Between Conversions 0 +2 +5

www.austriamicrosystems.com Revision 1.02 6 - 22

AS1524/AS1525

Datasheet - Ele c t r i c a l C h a r a c t e r i s t i c s

Digital Input s/Output s (CNVST, SCLK, DOUT)

VIL Input Low Voltag e 0.3VDD V

VIH Input High Voltage 0.7VDD V

ILEAK Input Leakage Current ±0.01 ±1.0 µA

CIN Input Capacit ance 15 pF

VOL Output Low Voltage ISINK = 2mA 0.4 V

ISINK = 4mA 0.8

VOH Output High Voltage ISOURCE = 1.5mA 0.7VDD V

Tri-State Leakage Current CNVST = GND ±0.05 ±5 µA

Tri-State Output Capacitance CNVST = GND 15 pF

Power Requirements

VDD Positive Supply Voltage 2.7 5.25 V

IDD Positive Supply Current

VDD = +3V, fSAMPLE = 150ksps 350 425

µA

VDD = +3V, fSAMPLE = 100ksps 245

VDD = +3V, fSAMPLE = 10ksps 24

VDD = +3V, fSAMPLE = 1ksps 2.5

VDD = +5V, fSAMPLE = 150ksps 485 550

VDD = +5V, fSAMPLE = 100ksps 330

VDD = +5V, fSAMPLE = 10ksps 33

VDD = +5V, fSAMPLE = 1ksps 3.7

Automatic Shutdown Mode 0.2 1

PSR Power Supply Rejection VDD = +5V ±5%, Full Scale Input ±0.3 mV

VDD = +2.7V to 3.6V, Full Scale Input ±0.4

1. Offset nulled.

2. The absolute input voltage range for the analog inputs is from GND to VDD.

Table 4. Electrical Characteristics (Continued)

Symbol Parameter Condition Min Typ Max Unit

www.austriamicrosystems.com Revision 1.02 7 - 22

AS1524/AS1525

Datasheet - Ele c t r i c a l C h a r a c t e r i s t i c s

Timing Characteristics

VDD = +2.7 to +5.25V, VREF = +2 .5V, 4.7µF Ca pacitor at REF; f SCLK = 8MHz (50% Duty Cycle); AIN- = GND (AS1524)

TAMB = TMIN to TMAX (unless otherwise specified). Typical Values at TAMB = +25ºC.

Figure 3. DOUT Enable/Disable Time Load Circuits

Figure 4. Detailed Serial Interface Timing Diagram

Table 5. Timing Characteristics

Parameter Symbol Conditions Min Typ Max Units

SCLK Pulse Width High tCH 38 ns

SCLK Pulse Width Low tCL 38 ns

SCLK Falling-to-DOUT

Transition tDOT CLOAD = 30pF (see Figure 3, Figure 4,

Figure 19 on page 12, Figure 20 on

page 12)28 60 ns

SCLK Rising-to-DOUT1

Disable

1. Guaranteed by Design and Characterisation.

tDOD CLOAD = 30pF (see Figure 3, Figure 4,

Figure 19 on page 12, Figure 20 on

page 12)100 200 500 ns

CNVST Falling-to-MSB Vlid tCONV CLOAD = 30pF (see Figure 3, Figure 4,

Figure 19 on page 12, Figure 20 on

page 12)3.3 3.7 µs

CNVST Pulse Width tCSW 30 ns

CLOAD 6kΩ

GND

DOUT

High-impedance to VOH, VOL to VOH, and VOH to High-impedance

VDD

6kΩ

GND CLOAD

DOUT

SCLK

CNVST

tCL tCH

tDOT tDOD

tCSW

High Z

www.austriamicrosystems.com Revision 1.02 8 - 22

AS1524/AS1525

Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s

7 Typical Operating Characteristics

VDD = 5V; VREF = 2.5V, fSCLK = 8MHz(50% duty), CREF = 4.7µF, TAMB = +25ºC (unless othe rwise specified).

Figure 5. Integral Nonlinearity vs. Digital Output Code Figure 6. Differential Nonlinearity vs. Digital Output Code

Figure 7. Supply Current vs. Supply Voltage Figure 8. Supply Current vs. Temperature

Figure 9. Supply Current vs. Temperat ure , VDD = 3V Figure 10. Supply Current vs. Sampling Rate

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 1024 2048 3072 4096

Digit al Out put Code

DNL (LSB) .

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0 1024 2048 3072 4096

Digit al Out put Code

I NL (LSB) .

fSAMPLE = 150ksps

100

150

200

250

300

350

400

450

500

-45 -30 -15 0 15 30 45 60 75 90

Temperature (° C)

Supply Cur r ent ( µA ) .

150ksps

100ksps

10ksps

1ksps

100

200

300

400

500

600

2.7 3.2 3.7 4.2 4.7 5.2

Supply Volt age (V)

Supply Cur r ent ( µA ) .

fSAMPLE = 150ksps

120

160

200

240

280

320

360

-45 -30 -15 0 15 30 45 60 75 90

Temperature (° C)

Supply Cur r ent ( µA ) .

150ksps

100ksps

10ksps

1ksps 0.01

0.1

100

1000

0.01 0.1 1 10 100 1000

Sa mpl in g R a te (ksps)

Supply Cur r ent ( µA ) .

www.austriamicrosystems.com Revision 1.02 9 - 22

AS1524/AS1525

Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s

Figure 11. Shutdown Current vs. Supply Voltage Figure 12. Shutdown Current vs. Temperature

Figure 13. Offset Error vs. Supply Voltage Figure 14. Offset Error vs. Temperature

Figure 15. Gain Error vs. Supply Voltage Figure 16. Gain Error vs. Temperature

100

-45 -30 -15 0 15 30 45 60 75 90

Temperature (° C)

S hut down Cur r ent ( nA ) .

2.73.23.74.24.75.2

Supply Volt age ( V)

S hut down Cur r ent ( nA ) .

-2

-1

-45 -30 -15 0 15 30 45 60 75 90

T emperature ( °C)

O f f set Error (LSB) .

-2

-1

2.7 3.2 3.7 4.2 4.7 5.2

S upply Voltage (V)

O f f set Error (LSB) .

-2

-1

-45 -30 -15 0 15 30 45 60 75 90

T emperature ( °C)

G ain Error (LSB) .

-2

-1

2.7 3.2 3.7 4.2 4.7 5.2

Supply Volt age (V)

G ain Error (LSB) .

www.austriamicrosystems.com Revision 1.02 10 - 22

AS1524/AS1525

Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s

Figure 17. FFT @ 10kHz

-160

-140

-120

-100

-80

-60

-40

-20

0 1530456075

I nput Signal F r equenc y (k Hz)

FFT (dBC) .

fSAMPLE = 150ksps

NFFT = 32768

SNR=72.7dB

THD = -79.3dB

SFDR = 83.5dB

www.austriamicrosystems.com Revision 1.02 11 - 22

AS1524/AS1525

Datasheet - D et a i l e d De s c r i p t i o n

8 Detailed Description

The AS1524/AS1525 employ a successive approximation conversion (SAR) technique and integ r ated track/hold cir-

cuitry to convert analog signals into 12-bit digital output. The serial interface provides easy interfacing to microproces-

sors. Figure 18 shows the simplified internal structure for the AS1525 (2-channels, si ngle ended) and the AS1524

(1-channel, true differential).

True Differential Analog Input Track/Hold

The equivalent circuit of Figure 18 shows the device input architecture which is composed of tra ck/hold circuitry, input

multiplexer, comparator, and switched-capacitor DAC. The track/hold circuitry enters its tracking mode on the rising

edge of CNVST. The positive input capacitor is connected to AIN1 or AIN2 (AS1525) or AIN+ (AS1524). The negative

input capacitor is connected to GND (AS1525) or AIN- (AS1524).

Figure 18. Equivalent In put Circuit

The track/hold circuitry enters its hold mode on the falling edge of CNVST and the difference between the sampled

positive and negative input voltages is converted. The time required for the track/hold to acquire an input signal is

determined by how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisi-

tion time lengthens, and CNVST must be held high for a longer period of time. The acquisition time (tACQ) is the maxi-

mum time needed for the signal to be acqui red, plus the power-up time. tACQ is calculated by:

tACQ = 9 x (RS + RIN) x 20pF + tPWR (EQ 1)

Where:

RS is the source impedance of the input signal;

RIN = 1.5kΩ;

tPWR of 1µs is the power-up time of the device.

Note: tACQ is never less than 1.4µs and any source impedance below 300. does not significantly affect the AS1524/

AS1525 AC performance. A high-impedance source can be accommodated either by lengthening tACQ or by

placing a 1µF capacitor between the positive and negative analog inputs.

Selecting AIN1 or AIN2 (AS1525)

Select one of the AS1525 two positive input channe ls using the CNVST pin (see page 3). If AIN1 is selected (see Fig-

ure 19), drive CNVST high to power up the AS1525 and place the track/hold circuitry in track mode with AIN1 con-

nected to the positive input capacitor. Hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place

the track/hold circuitry in hold mode. The AS1525 then performs a conversion and shutdown automatically . The MSB is

available at DOUT after 3.7µs. Data can then be clocked out using SCLK. Clock out all 12 bits of data before driving

CNVST high for the next conversion. If all 12 bits of data are not clocked out before CNVST is driven high, AIN2 is

selected for the next conversion.

–

Comparator

Hold

12-Bit Capacitive DAC

Track

AIN2

AIN1/AIN+

VDD/2

RIN-

CIN+

REF

GND

GND/AIN-

CIN-

Hold

RIN+

www.austriamicrosystems.com Revision 1.02 12 - 22

AS1524/AS1525

Datasheet - D et a i l e d De s c r i p t i o n

Figure 19. Single Conversion – AIN1 vs. GND (AS1525), Unipolar Mode AIN+ vs. AIN- (AS1524)

If AIN2 is selected (see Figure 20), drive CNVST high for at least 30ns. Next, drive CNVST low for at least 30ns, and

then high again. This powers up the AS1525 and places the track/hold circuitry in track mode with AIN2 connected to

the positive input capacitor. Next hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the

track/hold circuitry in hold mode. The AS1525 then performs a conversion and shuts down automatically. The MSB is

available at DOUT after 3.7µs. Data can then be clocked out using SCLK.

Note: If all 12 bits of data are not clocked out before CNVST is driven high, AIN2 is selected for the next conversion .

Selecting Unipolar or Bipolar Conversions (AS1524)

True-differential conversion (with the AS1524 unipolar and bipolar modes) is selected using pin CNVST (see page 3).

AIN+ and AIN- are sampled at the falling edge of CNVST. In unipolar mode, AIN+ can exceed AIN- by up to VREF. The

output format is straight binary. In bipolar mode, either input can exceed the other by up to VREF/2. The output format is

two’s complement. In both modes, the input common mode range can go from GND to VDD.

Figure 20. Single Conversion – AIN2 vs. GND (AS1525), Bipolar Mode AIN+ vs. AIN- (AS1524)

Note: In unipolar and bipolar modes, AIN+ and AIN- must not exceed VDD by more than 50mV or be lower than GND

by more than 50mV.

If unipolar mode is selected (see Figure 19) , drive CNVST high to power up the AS1524 and place the track/hold cir-

cuitry in track mode with AIN+ and AIN- connected to the input capacitors. Hold CNVST high for tACQ to fully acquire

the signal. Drive CNVST low to place the track/hold circuitry in hold mode. The AS1524 then performs a conversion

and shutdown automatically. The MSB is available at DOUT after 3.7µs. Data can then be clocked out using SCLK.

Clock out all 12 bits of data before driving CNVST high for the next conversion. If all 12 bits of data are not clocked out

before CNVST is driven high, bipolar mode is selected for the next conversion.

If bipolar mode is selected (see Fi gure 20), drive CNVST high for at least 30ns. Next, drive CNVST low for at least

30ns and then high again. This places the track/hold circuitry in track mode with AIN+ and AIN- connected to the input

capacitors.

Next hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the track/hold circuitry in hold

mode. The AS1524 then performs a conversion and shuts down automatically. The MSB is available at DOUT after

3.7µs. Data can then be clocked out using SCLK.

Note: If all 12 bits of data are not clocked out before CNVST is driven high, bipolar mode is selected for the next con-

version.

SCLK

CNVST

Sampling Instant

tCONV

tACQ

1 4 8 12

DOUT B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

B11

MSB B0

LSB High ZHigh Z

DOUT

SCLK

CNVST

B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

B11

MSB B0

LSB

Sampling Instant

tCONV

tACQ

1 4 8 12

High ZHigh Z

www.austriamicrosystems.com Revision 1.02 13 - 22

AS1524/AS1525

Datasheet - D et a i l e d De s c r i p t i o n

Input Bandwidth

The AS1524/AS1525 input tracking circuitry has a 20MHz small signal bandwidth, so it is possible to digitize high-

speed transient events and measure periodic signals with bandwidths exceeding the AS1524/AS1525 sampling rate

by using undersampling tech niques.

Note: To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recom-

mended.

Analog Input Protection

Internal protection diodes that clamp the analog input to VDD and GND allow the analog input pins to swing from GND

- 0.3V to VDD + 0.3V without damage. Both inputs must not exceed VDD by more than 50mV or be lower than GND by

more than 50mV for accurate conversions.

Note: If an off-channel analog input voltage exceeds the supply voltages, the input current should be limited to 2mA.

Internal Clock

The AS1524/AS1525 operate from an internal clock, which is accurate within 5% of the 4MHz clock rate. This results in

a worst-case conversion time of 3.7µs. The internal clock releases th e system microprocessor from running the SAR

conversion clock and allows the conversi on results to be read back at the processor’s convenience, at any clock rate

from 0 to 8MHz.

Output Data Format

Figure 19 on page 12 and Figure 20 on page 12 illustrate the conversion timing for the AS1524/AS1525. The 12-bit

conversion result is output in MSB-first format. Data on DOUT transitions on the falling edge of SCLK. All 12 bits must

be clocked out before CNVST transitions again.

For the AS1524, data is straight binary for unipolar mode and two’s complement for bipolar mode. For the AS1525,

data is always straight binary.

Transfer Function

Figure 21 on page 13 shows th e unipolar transfer function fo r the AS1524/AS1525. Figure 22 on page 14 shows the

bipolar transfer function for the AS1524. Code transitions occur halfway between successive-integer LSB values.

Figure 21. AS1524/AS1525 Unipolar Transfer Functio n

11...111

11...110

11....101

00...011

00...010

00...001

00...000

Output Code

Input Voltage (LSB)

0 1 2 3 FS-3/2 LSB FS

Full-Scale

Transition

Full Scale = VREF

Zero Scale = GND

1 LSB = VREF/4096

www.austriamicrosystems.com Revision 1.02 14 - 22

AS1524/AS1525

Datasheet - D et a i l e d De s c r i p t i o n

Figure 22. AS1524 Bipolar Transfer Function

011...111

011...110

000...010

000...001

000...000

111...111

111...110

111...101

100...001

100...000

Output Code

Input Voltage (LSB)

-FS 0 +FS-1 LS B

VCOM ≥ VREF /2

VIN = AIN+ - AIN-

Full Scale = VREF/2

-Full Scale = -VREF/2

Zero Scale = 0

1 LSB = VREF/4096

www.austriamicrosystems.com Revision 1.02 15 - 22

AS1524/AS1525

Datasheet - App l i c a t i o n I n f o r m a t i o n

9 Application Information

Automatic Shutdown Mode

With CNVST low, the AS1524/AS1525 default to automatic shutdown (< 0.2µA) mode after power-up and between

conversions. After detecting a rising edge of CNVST, the AS1524/AS1525 powers up, sets DOUT low, and enters

track mode.

After detecting a falling edge of CNVST, the device enters hold mode and begins the conversion. A maximum of 3.7µs

later, the device completes conversion, enters shutdown, and MSB is available at DOUT.

External Reference

An external reference is required for the AS1524/AS1525. Use a 4.7µF bypass capacitor for best performance. The

reference input structure allows a voltage range of +1V to VDD + 50mV.

Performing a Conversion

1. Use a general-purpose I/O line on the CPU to hold CNVST low between conversions.

2. Drive CNVST high to acquire AIN1(AS1525) or unipolar mode (AS1524). To acquire AIN2 (AS1525) or bipolar

mode (AS1524), drive CNVST low and high again.

3. Hold CNVST high for 1.4µs.

4. Drive CNVST low and wait approximately 3.7µs for conversion to complete. After 3.7µs, the MSB is available

at DOUT.

5. Activate SCLK for a minimum of 12 rising clock edges. DOUT transitions on SCLK’s falling edge and is avail-

able in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Clock data into the µP on

SCLK’s rising edge.

Standard Interface Connections

The AS1524/AS1525 serial interface is fully compatible with SPI, QSPI, and MICROWIRE. If a serial interface is avail-

able, establish the processor’s serial interface as a master so that the CPU generates the serial clock for the AS1524/

AS1525 and select a clock frequency up to 8MHz.

SPI and Microwire Interface

When using an SPI (Figure 23) or Microwire interface (Figure 24), set CP O L = C P HA = 0. Two 8-bit readi n gs are nec-

essary to obtain the entire 12-bit result from the AS1524/AS1525. DOUT data transitions on the serial clock’s falling

edge and is clocked into th e processor on SCLK’s rising ed ge. The first 8-bit data stream contains the first 8-bits of

DOUT starting with the MSB. The second 8-bit data stream contains the remaini ng four result bits. DOUT th en goes

high impedance.

Figure 23. SPI Serial Interface Connections

AS1524/

AS1525

CPU

SSM

MISO

I/O

SCK

DOUT

CNVST

SCLK

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AS1524/AS1525

Datasheet - App l i c a t i o n I n f o r m a t i o n

Figure 24. Microwire Serial Interface Connections

Figure 25. SPI/Microwire Interface Timing Diagram (CPOL = CPHA = 0)

QSPI Interface

Using the high-speed QSPI interface ( Figure 26) with CPOL = 0 and CPHA = 0, the AS1524/AS1525 support a maxi-

mum fSCLK of 8MHz. One 12- to 16-bit reads are necessary to obtain the entire 12-bit result from the AS1524/AS1525.

DOUT data transitions on the serial clock’s falling edge and is clocked into the processor on SCLK’s rising edge. The

first 12 bits are the data. DOUT then goes high impedance (see Figure 24).

Figure 26. QSPI Serial Interface Connections

AS1524/

AS1525

CPU

I/O

DOUT

CNVST

SCLK

CNVST

Sampling Instant

1 4 8 12

DOUT B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

B11

MSB B0

LSB High Z

1st Byte Read 2nd Byte Read

AS1524/

AS1525

CPU

SSM

MISO

CSM

SCK

DOUT

CNVST

SCLK

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AS1524/AS1525

Datasheet - App l i c a t i o n I n f o r m a t i o n

Figure 27. QSPI Serial Interface Timing (CPOL = CPHA = 0)

PIC16 and SSP Module and PIC17 Interface

The AS1524/AS1525 are compatible with a PIC16/PIC17 controllers, using the synchronous serial port (SSP) module

To establish SPI communication, connect the PIC16/PIC17 controllers as shown in Figure 28 and configure the PIC16/

PIC17 as system master. This is done by initializing its synchronous serial port control register (SSPCON) and syn-

chronous serial port status register (SSPSTAT) to the bit patterns shown in Table 6 on page 18 and Tab le 7 on

page 18.

Figure 28. SPI Interface Connections for PIC16/PIC17 Controller

In SPI mode, the PIC16/PIC17 processor allow 8 bits of data to be synchronously transmitted and received simultane-

ously. T wo consecutive 8-bit readings (see Figure 29) are necessary to obtain the entire 12-bit result from the AS1524/

AS1525. DOUT data transitions on the serial clock’s falling edge and is clocked in to the processor on SCLK’s rising

edge.

The first 8-bit data stream contains the first 8 data bits starting with the MSB. The second data stream contains the

remaining bits, D3 through D0.

Figure 29. SPI Interface T iming with PIC16/PIC17 in Master Mode (CKE = 1. CKP = 0. SMP = 0, SSPM3:SSPM0

= 0001)

SCLK

CNVST

Sampling Instant

1 4 8 12

DOUT B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

B11

MSB B0

LSB High Z

AS1524/

AS1525

PIC16/

PIC17

DOUT

CNVST

SCLK

DOUT

CNVST

SCLK

CNVST

Sampling Instant

1 4 8 12

DOUT B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

B11

MSB B0

LSB High Z

1st Byte Read 2nd Byte Read

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AS1524/AS1525

Datasheet - App l i c a t i o n I n f o r m a t i o n

Table 6. SSPCON Register Settings

Control Bit AS1524/AS1525

Setting Synchronous Serial Port Control Register (SSPCON)

WCOL Bit 7 X Write Collision Detection Bit

SSPOV Bit 6 X Receive Overflow Detect Bit

SSPEN Bit 5 1

Synchronous Serial Port Enable

0: Disables serial port and configures these pi ns as I/O port pins.

1: Enables serial port and confi gures SCK, SDO, and SCI pins as serial port

pins.

CKP Bit 4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selecti o n.

SSPM3:1 Bit 3:1 0 Synchronous Serial Port Mode Select Bit. Sets SPI master mode and

selects FCLK = fOSC / 16.

SSPM0 Bit 0 1

Table 7. SSPSTAT Register Settings

Control Bit AS1524/AS1525

Setting Synchronous Seria l St at us Regi ste r (SSP STAT)

SMP Bit 7 0 SPI Data Input Sample Phase. Input data is sampled at the middle of the

data output time.

CKE Bit 6 1 SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the

serial clock.

D/A Bit 5 X Data Address Bit

PBit 4 X Stop Bit

SBit 3 X Start Bi t

R/W Bit 2 X Read/Write Bit Information

UA Bit 1 X Update Address

BF Bit 0 X Buffer Fu ll Status Bit

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AS1524/AS1525

Datasheet - App l i c a t i o n I n f o r m a t i o n

Layout and Grounding Considerations

The AS1524/AS1525 require proper layout and design procedures for optimum performance.

! Use printed circuit boards; wirewrap boards should not be used.

! Separate analog and digital traces from each other. Analog and digital traces should not run parallel to each other

(especially clock traces).

! Digital traces should not run beneath the AS1524/AS1525.

! Use a single-point analog ground at GND, separate from the digital ground (see Figure 30). Connect all other ana-

log grounds and DGND to this star ground point for further noise reduction. No other digital system ground should

be connected to this single-point analog ground. The ground return to the power supply for thi s gro und should be

low impedance and as short as possible for noise-free operation.

! High-frequency noise in the VDD power supply may affect the AS1524/AS1525 high-speed comparator. Bypass

this supply to the single-point analog ground with 0.1µF and 4.7µF bypass capacitors (see Figure 30). The bypass

capacitors should be placed as close to the device as possible for optimum power supply noise-rejection. If the

power supply is very noisy, a 10Ω resistor can be connected as a low-pass filter to attenuate supply noise

! Power components such as the inductor , converter IC, filter capacitors, and output diode should be placed as close

together as possible, and their traces should be kept short, direct, and wide.

! Keep the voltage feedback network very close to the device, within 5mm (0.2”) of the pin.

! Keep noisy traces, such as those from the pin LX, away from the voltage feedback network and guarded from

them using grounded copper traces.

Figure 30. Recommended Ground Design

AS1524/

AS1525

Power

Supplies

Digital

Circuitry

0.1µF

GND

+5 or +3V

VDD

GND

+5 or +3V

DGND

GND

5Ω

(Optional)

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AS1524/AS1525

Datasheet - Pa ck ag e D ra wi ng s a nd Marki ngs

10 Package Drawings and Markings

The devices are available in a 8-pin TDFN (3x3mm) package.

Figure 31. 8-pin TDFN (3x3mm) Packagee

Notes:

1. Figure 31 is shown for illustration only.

2. All dimensions are in millimeters; angles in degrees.

3. Dimensioning and tolerancing conform to ASME Y14.5 M-1994.

4. N is the total number of terminals.

5. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC 95-1, SPP-012. Det ails of ter-

minal #1 identifier are optional, but must be located with in the zone indicated. The terminal #1 identifier may be either

a mold or marked feature.

6. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.

7. ND refers to the maximum number of terminals on side D.

8. Unilateral coplanarity zone app lies to the exposed heat sink slug as well as the terminals

Symbol Min Typ Max Notes

A 0.70 0 .75 0.80 1, 2

A1 0.00 0.02 0.05 1, 2

A3 0.20 REF 1, 2

L1 0.15 1, 2

L2 0.13 1, 2

aaa0.151, 2

bbb0.101, 2

ccc 0.10 1, 2

ddd0.051, 2

eee0.081, 2

ggg0.101, 2

Symbol Min Typ Max Notes

D BSC 3.00 1, 2

E BSC 3.00 1, 2

D2 1.60 2.50 1, 2

E2 1.35 1 .75 1, 2

L 0.30 0.40 0.50 1, 2

θ0º 14º 1, 2

K0.20 1, 2

b 0.25 0.30 0.35 1, 2, 5

e0.65

N81, 2

ND 4 1, 2, 5

SEE

DETAIL B

PIN 1 INDEX AREA

(D/2 xE/2)

BTM VIEW

N-1N

ddd

D2/2

(D/2 xE/2)

TOP VIEW

aaa C

PIN 1 INDEX AREA

ccc C

SIDE VIEW

(ND-1) X e

0.08 C

EVEN T ERMINAL SIDE

Datum A or B

Terminal Tip

e/2

C A B

E2/2

SEATING

PLANE

DETAIL B

www.austriamicrosystems.com Revision 1.02 21 - 22

AS1524/AS1525

Datasheet - O r d e r i n g I n f o r m a t i o n

11 Ordering Information

The devices are available as the standard products shown in Table 8.

Note: All products are RoHS compliant and Pb-free.

Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect

For further information and requests, please contact us mailto:sales@austriamicrosystems.com

or find your local distributor at http://www.austriamicrosystems.com/distributor

Table 8. Ordering Information

Ordering Code Description Delivery Form Package

AS1524-BTDT 150ksps, 12-Bit, 1-Channel True-Differential ADC Tape & Reel 8-pin TDFN (3x3mm)

AS1524-BTDR 150ksps, 12-Bit, 1-Channel True-Differential ADC Tray 8-pin TDFN (3x3mm)

AS1525-BTDT 150ksps, 12-Bit, 2-Channel Single-Ended ADC Tape & Reel 8-pin TDFN (3x3mm)

AS1525-BTDR 150ksps, 12-Bit, 2-Channel Single-Ended ADC Tray 8-pin TDFN (3x3mm)

www.austriamicrosystems.com Revision 1.02 22 - 22

AS1524/AS1525

Datasheet

Copyrights

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All products and companies mentioned are trademarks or registered trademarks of their respective companies.

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in its Term of Sale. austriamicrosystems AG makes no warranty, express, st atutory, implied, or by description regarding

the information set forth herein or regarding th e fre e dom of the described devi c es from patent infringement.

austriamicrosystems AG reserves the right to change specific ations and prices at any time and without notice.

Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for

current information. This product is intended for use in normal commercial applications. Applic ations requiring

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austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show

deviations from the standard production flow, such as test flow or test location.

The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,

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austriamicrosystems AG rendering of technical or other services.

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