LTC4360ISC8-1#TRPBF - ANALOG DEVICES

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

TYPICAL APPLICATION

DESCRIPTION

Overvoltage Protection Controller

The LT C

4360 overvoltage protection controller safe-

guards 2.5V to 5.5V systems from power supply over-

voltage. It is designed for portable devices with multiple

power supply options including wall adaptors, car battery

adaptors and USB ports.

The LTC4360 controls an external N-channel MOSFET in

series with the input power supply. During overvoltage

transients, the LTC4360 turns off the MOSFET within 1µs,

isolating downstream components from the input supply.

Inductive cable transients are absorbed by the MOSFET

and load capacitance. In most applications, the LTC4360

provides protection from transients up to 80V without

requiring transient voltage suppressors or other external

components.

The LTC4360 has a delayed start-up and an adjustable

dV/dt ramp-up for inrush current limiting. A PWRGD pin

provides power good monitoring for V

. Following an

overvoltage condition, the LTC4360 automatically restarts

with a start-up delay. The LTC4360-1 features a soft shut-

down controlled by the ON pin, while the LTC4360-2 con-

trols an optional external P-channel MOSFET for negative

voltage protection.

Output Protected from Overvoltage at Input

FEATURES

APPLICATIONS

n 2.5V to 5.5V Operation

n Overvoltage Protection Up to 80V

n No Input Capacitor or TVS Required for Most

Applications

n 2% Accurate 5.8V Overvoltage Threshold

n <1µs Overvoltage Turn-Off, Gentle Shutdown

n Controls N-Channel MOSFET

n Adjustable Power-Up dV/dt Limits Inrush

n Reverse Voltage Protection (LTC4360-2)

n Power Good Output

n Low Current Shutdown (LTC4360-1)

n Available in a Tiny 8-Lead SC70 Package

n USB Protection

n Handheld Computers

n Cell/Smart Phones

n MP3/MP4 Players

n Digital Cameras

GATE

Si1470DH

436012 TA01a

OUT

1.5A

VIN

LTC4360-1

OUT

PWRGD

GND

COUT

Protection from Overvoltage

0.5µs/DIV 436012 TA01b

Si1470DH

COUT = 10µF

VOUT

VIN

VGATE

10V/DIV

VIN, VOUT

5V/DIV

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LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

Bias Supply Voltage (IN) ............................ –0.3V to 85V

Input Voltages

OUT, ON ................................................... –0.3V to 9V

Output Voltages

PWRGD .................................................... –0.3V to 9V

GATE (Note 3) ........................................ –0.3V to 15V

GATEP .................................................... –0.3V to 85V

IN to GATEP ........................................... –0.3V to 10V

(Notes 1, 2)

ORDER INFORMATION

Lead Free Finish

TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4360CSC8-1#TRMPBF LTC4360CSC8-1#TRPBF LDXN 8-Lead Plastic SC70 0°C to 70°C

LTC4360CSC8-2#TRMPBF LTC4360CSC8-2#TRPBF LDXP 8-Lead Plastic SC70 0°C to 70°C

LTC4360ISC8-1#TRMPBF LTC4360ISC8-1#TRPBF LDXN 8-Lead Plastic SC70 –40°C to 85°C

LTC4360ISC8-2#TRMPBF LTC4360ISC8-2#TRPBF LDXP 8-Lead Plastic SC70 –40°C to 85°C

TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.

Consult ADI Marketing for parts specified with wider operating temperature ranges.

Consult ADI Marketing for information on lead based finish parts.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

ABSOLUTE MAXIMUM RATINGS

LTC4360-1 LTC4360-2

IN 1

GND 2

GND 3

GND 4

8 GATE

7 OUT

6 ON

5 PWRGD

TOP VIEW

SC8 PACKAGE

8-LEAD PLASTIC SC70

TJMAX = 125°C, θJA = 270°C/W

IN 1

GND 2

GND 3

GND 4

8 GATEP

7 GATE

6 OUT

5 PWRGD

TOP VIEW

SC8 PACKAGE

8-LEAD PLASTIC SC70

TJMAX = 125°C, θJA = 270°C/W

PIN CONFIGURATION

Operating Temperature Range

LTC4360C ................................................ 0°C to 70°C

LTC4360I .............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ...................300°C

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to GND unless otherwise

specified.

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VON = 0V (LTC4360-1) unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supplies

VIN Input Voltage Range l2.5 80 V

VIN(UVL) Input Undervoltage Lockout VIN Rising l1.8 2.1 2.45 V

IIN Input Supply Current LTC4360-1 VON = 0V, LTC4360-2 l220 400 µA

LTC4360-1 VON = 2.5V l1.5 10 µA

Thresholds

VIN(OV) IN Pin Overvoltage Threshold VIN Rising l5.684 5.8 5.916 V

VIN(OVL) IN Pin Overvoltage Recovery Threshold VIN Falling l5.51 5.7 5.85 V

∆VOV Overvoltage Hysteresis l25 100 300 mV

External Gate Drive

∆VGATE External N-Channel MOSFET Gate Drive

(VGATE – VOUT)

2.5V ≤ VIN < 3V, IGATE = –1µA

3V ≤ VIN < 5.5V, IGATE = –1µA

3.5

4.5

7.9

VGATE(TH) GATE High Threshold for PWRGD Status VIN = 3.3V

VIN = 5V

5.7

6.7

6.3

7.2

6.8

7.8

IGATE(UP) GATE Pull-Up Current VGATE = 1V l–5 –10 –15 µA

VGATE(UP) GATE Ramp-Up VGATE = 1V to 7V l1.5 3 4.5 V/ms

IGATE(FST) GATE Fast Pull-Down Current Fast Turn-Off, VIN = 6V, VGATE = 9V l15 30 60 mA

IGATE(DN) GATE Pull-Down Current VON = 2.5V, VGATE = 9V (LTC4360-1) l10 40 80 µA

Input Pins

IOUT(IN) OUT Input Current VOUT = 5V, VON = 0V

VOUT = 5V, VON = 2.5V

5 10

±3

µA

VON(TH) ON Input Threshold (LTC4360-1) l0.4 1.5 V

ION ON Pull-Down Current VON = 2.5V (LTC4360-1) l2.5 5 10 µA

Output Pins

VGATEP(CLP) IN to GATEP Clamp Voltage VIN = 8V to 80V (LTC4360-2) l5 5.8 7.5 V

RGATEP GATEP Resistive Pull-down VGATEP = 3V (LTC4360-2) l0.8 2 3.2 MΩ

VPWRGD(OL) PWRGD Output Low Voltage VIN = 5V, IPWRGD = 3mA l0.23 0.4 V

RPWRGD PWRGD Pull-Up Resistance to OUT VIN = 6.5V, VPWRGD = 1V l250 500 800 kΩ

Delay

tON GATE On Delay VIN High to IGATE = –5µA l50 130 200 ms

tOFF GATE Off Propagation Delay VIN = Step 5V to 6.5V to PWRGD High l0.25 1 µs

tPWRGD PWRGD Delay VIN = Step 5V to 6.5V

VGATE > VGATE(TH) to PWRGD Low

0.25

100

µs

tON(OFF) ON High to GATE Off VON = Step 0V to 2.5V (LTC4360-1) l2 5 µs

Note 3: An internal clamp limits VGATE to a minimum of 4.5V above VOUT.

Driving this pin to voltages beyond this clamp may damage the device.

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

PWRGD Voltage

vs PWRGD Current

GATE Off Propagation Delay

vs Overdrive (VOVDRV)

Normal Start-Up Sequence GATE Slow Ramp-Up Entering Sleep Mode (LTC4360-1)

Input Supply Current

vs Input Voltage GATE Drive vs GATE Current

GATE Fast Pull-Down Current

vs Temperature

VIN

5V/DIV

VGATE

10V/DIV

VOUT

5V/DIV

ICABLE

0.5A/DIV

20ms/DIV 436012 G07

FIGURE 5 CIRCUIT

RIN = 150mΩ, LIN = 0.7µH

LOAD = 10Ω, COUT = 10µF

VIN

5V/DIV

VGATE

10V/DIV

VOUT

5V/DIV

ICABLE

0.5A/DIV

1ms/DIV 436012 G08

FIGURE 5 CIRCUIT

RIN = 150mΩ, LIN = 0.7µH

LOAD = 10Ω, COUT = 10µF

VON

5V/DIV

VGATE

10V/DIV

VOUT

5V/DIV

ICABLE

0.5A/DIV

50µs/DIV 436012 G09

FIGURE 5 CIRCUIT

RIN = 150mΩ, LIN = 0.7µH

LOAD = 10Ω, COUT = 10µF

VIN (V)

0.1

IIN (µA)

100

1000

436012 G01

100

VON = 2.5V

(LTC4360-1)

LTC4360-1 VON = 0V, LTC4360-2)

IGATE (µA)

VIN = 5V

VIN = 3V

VIN = 2.5V

∆V

GATE

(V)

2468

436012 G02

10 12

TEMPERATURE (°C)

–50

IGATE(FST) (mA)

–25 0 25 50

436012 G03

VIN = 6V

VGATE = 9V

100

IPWRGD (mA)

VPWRGD(OL) (mV)

200

100

300

400

500

1234

436012 G04

TA = 25°C, VIN = 5V, VON = 0V (LTC4360-1) unless otherwise noted.

GATE Voltage and GATE High

Threshold (for PWRGD Status)

vs Input Voltage

VIN (V)

2.5

GATE

GATE(TH)

(V)

3.53 4 4.5 5 5.5

436012 G06

VIN = VOUT

VGATE

VGATE(TH)

VOVDRV (V)

tOFF (µs)

0.5 1 1.5 2

436012 G05

2.5

VIN = STEP 5V TO (VIN(OV) + VOVDRV)

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

PIN FUNCTIONS

GATE: Gate Drive for External N-Channel MOSFET. An

internal charge pump provides a 10µA pull-up current

to charge the gate of the external N-channel MOSFET. An

additional ramp circuit limits the GATE ramp rate when

turning on to 3V/ms. For slower ramp rates, connect an

external capacitor from GATE to GND. An internal clamp

limits GATE to 6V above the OUT pin voltage. An internal

GATE high comparator controls the PWRGD pin.

GATEP (LTC4360-2): Gate Drive for External P-Channel

MOSFET. GATEP connects to the gate of an optional exter-

nal P-channel MOSFET to protect against negative volt-

ages at IN. This pin is internally clamped to 5.8V below

VIN. An internal 2M resistor connects this pin to ground.

Connect to IN if not used.

GND: Device Ground.

IN: Supply Voltage Input. Connect this pin to the input

power supply. This pin has an overvoltage threshold of

5.8V. After an overvoltage event, this pin must fall below

VIN(OV) – ∆VOV to release the overvoltage lockout. During

lockout, GATE is held low and the PWRGD pull-down

releases.

ON (LTC4360-1): On Control Input. A logic low at ON

enables the LTC4360-1. A logic high at ON activates a

low current pull-down at the GATE pin and causes the

LTC4360-1 to enter a low current sleep mode. An internal

5µA current pulls ON down to ground. Connect to ground

or leave open if unused.

OUT: Output Voltage Sense Input for Gate Clamp. Connect

to the source of the external N-channel MOSFET to sense

the output voltage for GATE to OUT clamp.

PWRGD: Power Good Status. Open-drain output with

internal 500k resistive pull-up to OUT. Pulls low 65ms

after GATE ramps above VGATE(TH).

BLOCK DIAGRAM

–

5.8V

5.7V

GND

436012 BD

10µA

5µA

(LTC4360-1)

OUT

PWRGD

5.8V

VGATE(TH)

500k

1.8M

200k 5.8V

GATEP

(LTC4360-2)

GATE

CONTROL

CHARGE

PUMP

OVERVOLTAGE

COMPARATOR

GATE HIGH

COMPARATOR

–

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

OPERATION

Mobile devices like cell phones and MP3/MP4 players have

highly integrated subsystems fabricated from deep submi-

cron CMOS processes. The small form factor is accompa-

nied by low absolute maximum voltage ratings. The sensi-

tive electronics are susceptible to damage from transient or

DC overvoltage conditions from the power supply.

Failures or faults in the power adaptor can cause an over-

voltage event. So can hot-plugging an AC adaptor into the

power input of the mobile device (see ADI Application

Note 88). Today’s mobile devices derive their power sup-

ply or recharge their internal batteries from multiple alter-

native inputs like AC wall adaptors, car battery adaptors

and USB ports. A user may unknowingly plug in the wrong

adaptor, damaging the device with a high or even a nega-

tive power supply voltage.

The LTC4360 protects low voltage electronics from these

overvoltage conditions by controlling a low cost exter-

nal N-channel MOSFET configured as a pass transistor.

At power-up (VIN > 2.1V), a start-up delay cycle begins.

Any overvoltage condition causes the delay cycle to con-

tinue until a safe voltage is present. When the delay cycle

completes, an internal high side switch driver slowly

ramps up the MOSFET gate, powering up the output at

a controlled rate and limiting the inrush current to the

output capacitor.

If the voltage at the IN pin exceeds 5.8V (VIN(OV)),

GATE is pulled low quickly to protect the load. The

incoming power supply must remain below 5.7V

(VIN(OV) – ∆VOV) for the duration of the start-up delay to

restart the GATE ramp-up.

The LTC4360-1 has a CMOS compatible ON input. When

driven low, the part is enabled. When driven high, the

external N-channel MOSFET is turned off and the supply

current of the LTC4360-1 drops to 1.5µA. The PWRGD

pull-down releases during this low current sleep mode,

UVLO or overvoltage and the subsequent 130ms start-up

delay. After the start-up delay, GATE starts its slow ramp-

up and ramps higher than V

GATE(TH)

to trigger a 65ms

delay cycle. When that completes, PWRGD pulls low.

The LTC4360-2 has a GATEP pin that drives an optional

external P-channel MOSFET to provide protection against

negative voltages at IN.

The typical LTC4360 application protects 2.5V to 5.5V

systems in portable devices from power supply overvolt-

age. The basic application circuit is shown in Figure1.

Device operation and external component selection is

discussed in detail in the following sections.

APPLICATIONS INFORMATION

GATE

COUT

10µF

Si1470DH

436012 F01

VOUT

1.5A

VIN

LTC4360-1

OUT

PWRGD

GND

Figure1. Protection from Input Overvoltage

Start-Up

When VIN is less than the undervoltage lockout level of

2.1V, the GATE driver is held low and the PWRGD pull-

down is high impedance. When VIN rises above 2.1V and

ON (LTC4360-1) is held low, a 130ms delay cycle starts.

Any undervoltage or overvoltage event at IN (VIN < 2.1V or

VIN > 5.7V) restarts the delay cycle. This delay allows the

N-channel MOSFET to isolate the output from any input

transients that occur at start-up. When the delay cycle

completes, GATE starts its slow ramp-up.

GATE Control

An internal charge pump provides a gate overdrive greater

than 3.5V when 2.5V ≤ VIN < 3V. If VIN ≥ 3V, the gate drive

is guaranteed to be greater than 4.5V. This allows the use

of logic-level N-channel MOSFETs. An internal 6V clamp

between GATE and OUT protects the MOSFET gate.

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

resistor from PWRGD to the I/O rail with a resistance

low enough to override the internal 500k pull-up to OUT.

Figure2 details PWRGD behavior for a LTC4360-1 with

1k pull-up to 5V at PWRGD.

APPLICATIONS INFORMATION

The GATE ramp rate is limited to 3V/ms. VOUT follows at

a similar rate which results in an inrush current into the

load capacitor COUT of:

IINRUSH =COUT •

GATE

=COUT • 3 mA/µF

[ ]

The servo loop is compensated by the parasitic capaci-

tance of the external MOSFET. No further compensation

components are normally required. In the case where the

parasitic capacitance is less than 100pF, a 100pF com-

pensation capacitor between GATE and ground may be

required.

An even slower GATE ramp and lower inrush current

can be achieved by connecting an external capacitor, CG,

from GATE to ground. The voltage at GATE then ramps

up with a slope equal to 10µA/CG [V/s]. Choose CG using

the formula:

CG=10µA

INRUSH

• COUT

Overvoltage

When power is first applied, VIN must remain below 5.7V

(VIN(OV) – ∆VOV) for more than 130ms before GATE is

ramped up to turn on the MOSFET. If VIN then rises above

5.8V (VIN(OV)), the overvoltage comparator activates the

30mA fast pull-down on GATE within 1µs. After an over-

voltage condition, the MOSFET is held off until VIN once

again remains below 5.7V for 130ms.

PWRGD Output

PWRGD is an active low output with a MOSFET pull-

down to ground and a 500k resistive pull-up to OUT. The

PWRGD pin pull-down releases during the low current

sleep mode (invoked by ON high), UVLO or overvoltage

and the subsequent 130ms start-up delay. After the start-

up delay, GATE starts its slow ramp-up and control of

the PWRGD pull-down passes on to the GATE high com-

parator. VGATE > VGATE(TH) for more than 65ms asserts

the PWRGD pull-down and VGATE < VGATE(TH) releases

the pull-down. The PWRGD pull-down is capable of sink-

ing up to 3mA of current allowing it to drive an optional

LED. To interface PWRGD to another I/O rail, connect a

Figure2. PWRGD Behavior

OUT

GATE

PWRGD

VGATE(TH) VGATE(TH)

VIN(UVL)

VIN(OV)–∆VOV

START-UP

FROM UVLO

RESTART

FROM OV

RESTART

FROM ON

130ms 65ms 130ms 65ms 130ms 65ms

VIN(OV)

VGATE(TH) VGATE(TH)

ON Input (LTC4360-1)

ON is a CMOS compatible, active low enable input. It

has a default 5µA pull-down to ground. Connect this

pin to ground or leave open to enable normal device

operation. If it is driven high while the external MOSFET

is turned on, GATE is pulled low with a weak pull-down

current (40µA) to turn off the external MOSFET gradu-

ally, minimizing input voltage transients. The LTC4360-1

then goes into a low current sleep mode, drawing only

1.5µA at IN. When ON goes back low, the part restarts

with a 130ms delay cycle.

GATEP Control (LTC4360-2)

GATEP has a 2M resistive pull-down to ground and a 5.8V

Zener clamp in series with a 200k resistor to IN. It con-

trols the gate of an optional external P-channel MOSFET

to provide negative voltage protection. The 2M resistive

pull-down turns on the MOSFET once VIN – VGATEP is

more than the MOSFET gate threshold voltage. The IN to

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

Figure3. MOSFET Configurations

GATEP

SUPPLY

OVERVOLTAGE, REVERSE

CURRENT PROTECTION

NEGATIVE

VOLTAGE

PROTECTION

GATE

OVERVOLTAGE, REVERSE

CURRENT PROTECTION

GATE

GATEP

436012 F03

OVERVOLTAGE

PROTECTION

OVERVOLTAGE

PROTECTION

NEGATIVE

VOLTAGE

PROTECTION

GATE

OUT

SUPPLY

IN OUT

SUPPLY

IN OUT

SUPPLY

IN OUT

M1 M3

M1M2

APPLICATIONS INFORMATION

GATEP Zener protects the MOSFET from gate overvoltage

by clamping its VGS to 5.8V when VIN goes high.

MOSFET Configurations and Selection

The LTC4360 can be used with various external MOSFET

configurations (see Figure3). The simplest configuration

is a single N-channel MOSFET. It has the lowest RDS(ON)

and voltage drop and is thus the most power efficient

solution. When GATE is pulled to ground, the MOSFET

can isolate OUT from a positive voltage at IN up to the

BVDSS of the MOSFET. However, reverse current can still

flow from OUT to IN via the parasitic body diode of the

MOSFET.

For near zero reverse leakage current protection when

GATE is pulled to ground, back-to-back N-channel

MOSFETs can be used. Adding an additional P-channel

MOSFET controlled by GATEP (LTC4360-2) provides neg-

ative input voltage protection down to the BVDSS of the

P-channel MOSFET. Another configuration consists of a

P-channel MOSFET controlled by GATEP and a N-channel

MOSFET controlled by GATE. This provides protection

against overvoltage and negative voltage but not reverse

current.

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

APPLICATIONS INFORMATION

Input Transients

Figure4 shows a typical set-up when an AC wall adap-

tor charges a mobile device. The inductor LIN represents

the lumped equivalent inductance of the cable and the

EMI filter found in some wall adaptors. RIN is the lumped

equivalent resistance of the cable, adaptor output capaci-

tor ESR and the connector contact resistance.

Figure4. 20V Hot-Plug into a 10µF Capacitor

LOAD

436012 F04a

MOBILE

DEVICE

WALL ADAPTOR

AC/DC

COUT

LIN

RIN

CABLE

ICABLE VIN

10V/DIV

ICABLE

20A/DIV

5µs/DIV 436012 F04b

RIN = 150mΩ, LIN = 0.7µH

LOAD = 10Ω, COUT = 10µF

LIN and RIN form an LC tank circuit with any capacitance

at IN. If the wall adaptor is powered up first, plugging the

wall adaptor output to IN does the equivalent of applying

a voltage step to this LC circuit. The resultant voltage

overshoot at IN can rise to twice the DC output voltage

of the wall adaptor as shown in Figure4. Figure5 shows

the 20V adaptor output applied to the LTC4360. Due to

the low capacitance at the IN pin, the plug-in transient has

been brought down to a manageable level.

Figure5. 20V Hot-Plug into the LTC4360

LOAD

LTC4360

Si1470DH

GND

GATE

436012 F04a

MOBILE

DEVICE

WALL ADAPTOR

AC/DC

COUT

IN OUT

LIN

RIN

CABLE

ICABLE

IN OUT

VIN

10V/DIV

VOUT

1V/DIV

ICABLE

20A/DIV

5µs/DIV 436012 F04b

RIN = 150mΩ, LIN = 0.7µH

LOAD = 10Ω, COUT = 10µF

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

LOAD

436012 F07

OUT

COUT

Si1470DH

20V

WALL

ADAPTER

USB

LTC4360

100k

B160

OUT

GND

GATE

–

ICABLE

APPLICATIONS INFORMATION

VADAPTOR/VOUT

5V/DIV

VIN

20V/DIV

ICABLE

5A/DIV

2µs/DIV 436012 F06

FIGURE 5 CIRCUIT

RIN = 150µΩ, LIN = 2µH

LOAD = 10Ω, COUT = 10µF

VADAPTOR

VOUT

As the IN pin can withstand up to 80V, a high voltage

N-channel MOSFET can be used to protect the system

against rugged abuse from high transient or DC voltages

up to the BVDSS of the MOSFET. Figure6 shows a 50V

input plugged into the LTC4360 controlling a 60V rated

MOSFET.

Input transients also occur when the current through the

cable inductance changes abruptly. This can happen when

the LTC4360 turns off the N-channel MOSFET rapidly in an

overvoltage event. Figure7 shows the effects of a voltage

transient at the wall adaptor output VADAPTOR. The cur-

rent in LIN will cause VIN to overshoot and avalanche the

N-channel MOSFET to COUT

. Typically, IN will be clamped

to a voltage of VOUT + 1.3•(BVDSS of Si1470DH) = 45V.

This is well below the 85V absolute maximum voltage

rating of the LTC4360. The single, nonrepetitive, pulse of

energy (EAS) absorbed by the MOSFET during this ava-

lanche breakdown with a peak current IAS is approximated

by the formula:

EAS = 0.5 • LIN • IAS2

For L

= 2µH and I

= 4A, then E

= 16µJ. This is within

the IAS and EAS capabilities of most MOSFET’s including

the Si1470DH. So in most instances, the LTC4360 can

ride through such transients without a bypass capacitor,

transient voltage suppressor or other external compo-

nents at IN.

Figure8 shows a particularly severe situation which can

occur in a mobile device with dual power inputs. A 20V

Figure6. 50V Hot-Plug into the LTC4360

VIN

20V/DIV

VOUT

1V/DIV

ICABLE

5A/DIV

5µs/DIV 436012 F05

FDC5612

RIN = 150mΩ, LIN = 0.7µH

LOAD = 10Ω, COUT = 10µF

Figure7. Input Transient After Overvoltage

Figure8. Set-Up for Testing 20V Plugged into 5V System

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

APPLICATIONS INFORMATION

LTC4360 to shut off the MOSFET before V

OUT

overshoots

to a dangerous voltage. A larger COUT also helps to lower

the ∆VOUT due to the discharge of the energy in LIN if the

MOSFET BVDSS is used as an input clamp.

Layout Considerations

Figure 10 shows example PCB layouts for the single

N-channel MOSFET (SC70 package) configuration and the

P-channel MOSFET/N-channel MOSFET (Complementary

P, N MOSFET in TSOP-6 package) configuration. Keep the

traces to the MOSFETs wide and short. The PCB traces

associated with the power path through the MOSFETs

should have low resistance.

Si3590DV

436012 F09

Si1470DH

SUPPLY/IN

SUPPLY

OUT

GND

LTC4360-2

LTC4360-1

Figure9. Overvoltage Protection Waveforms When 20V Plugged into 5V System

VIN

20V/DIV

VGATE

10V/DIV

VOUT

5V/DIV

ICABLE

10A/DIV

1µs/DIV 436012 F08

FIGURE 8 CIRCUIT

RIN = 150mΩ, LIN = 2µH

LOAD = 10Ω, COUT = 10µF (16V, SIZE 1210)

wall adaptor is mistakenly hot-plugged into the 5V device

with the USB input already live. As shown in Figure9, a

large current can build up in LIN to charge up COUT

. When

the N-channel MOSFET shuts off, the energy stored in L

is dumped into C

OUT

, causing a large 40V input transient

The LTC4360 limits this to a 1V rise in the output voltage.

If the voltage rise at VOUT due to the discharge of the

energy in LIN into COUT is not acceptable or the avalanche

capability of the MOSFET is exceeded, an additional exter-

nal clamp such as the SMAJ24A can be placed between

IN and GND. COUT is the decoupling capacitor of the pro-

tected circuits and its value will largely be determined by

their requirements. Using a larger COUT will work with

LIN to slow down the dV/dt at OUT, allowing time for the

Figure10. Recommended Layout for N-Channel MOSFET and P-/N-Channel MOSFET Configurations

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

PACKAGE DESCRIPTION

SC8 Package

8-Lead Plastic SC70

(Reference LTC DWG # 05-08-1639 Rev Ø)

1.15 – 1.35

(NOTE 4)

1.80 – 2.40

0.15 – 0.27

8 PLCS (NOTE 3)

SC8 SC70 0905 REV Ø

1.80 – 2.20

(NOTE 4)

0.50 BSC

PIN 1

PIN 8

0.80 – 1.00

1.00 MAX

0.00 – 0.10

REF

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL,

BUT MUST BE LOCATED WITHIN THE INDEX AREA

7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70 AND JEDEC MO-203 VARIATION BA

2.8 BSC

0.30

MAX

0.50

REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

1.8 REF

1.00 REF

INDEX AREA

(NOTE 6)

0.10 – 0.18

(NOTE 3)

0.26 – 0.46

GAUGE PLANE

0.15 BSC

0.10 – 0.40

SC8 Package

8-Lead Plastic SC70

(Reference LTC DWG # 05-08-1639 Rev Ø)

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 01/11 Revised Features 1

Revised conditions for VGATEP(CLP) and tOFF in Electrical Characteristics section 3

Revised GATE Control in Applications Information section 6

B 05/18 Changed ∆VOV maximum limit to 300mV 3

LTC4360-1/LTC4360-2

Rev B

For more information www.analog.com

D17015-0-5/18(B)

www.analog.com

 ANALOG DEVICES, INC. 2010-2018

RELATED PARTS

TYPICAL APPLICATION

5V System Protected from ±24V Power Supplies

GATE

VIO

COUT

10µF

LN1351CTR

Si3590DV

M2 M1

436012 TA02

VOUT

0.5A

VIN

LTC4360-2

GATEP

OUT

PWRGD

GND

PART NUMBER DESCRIPTION COMMENTS

LTC2935 Ultralow Power Supervisor with Eight Pin-Selectable

Thresholds

500nA Quiescent Current, 2mm × 2mm 8-Lead DFN and TSOT-23 Packages

3008 20mA, 45V, 3µA IQ Micropower LDO 280mV Dropout Voltage, Low IQ: 3µA, VIN = 2.0V to 45V, VOUT = 0.6V to 39.5V;

ThinSOT™ and 2mm × 2mm DFN-6 Packages

LT3009 20mA, 3µA IQ Micropower LDO 280mV Dropout Voltage, Low IQ: 3µA, VIN = 1.6V to 20V, VOUT = 0.6V to 19.5V;

ThinSOT and SC-70 Packages

LTC3576/

LTC3576-1

Switching USB Power Manager with USB OTG + Triple

Step-Down DC/DCs

Complete Multifunction PMIC: Bidirectional Switching Power Manager + 3

Bucks + LDO

LTC4090/

LTC4090-5

High Voltage USB Power Manager with Ideal Diode

Controller and High Efficiency Li-Ion Battery Charger

High Efficiency 1.2A Charger from 6V to 38V (60V Max) Input Charges Single

Cell Li-Ion Batteries Directly from a USB Port

LTC4098 USB-Compatible Switchmode Power Manager with

OVP

High VIN: 38V Operating, 60V Transient; 66V OVP. 1.5A Max Charge Current

from Wall, 600mA Charge Current from USB

LTC4210-1 Single Channel, Low Voltage Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6

LTC4213 No RSENSE™ Electronic Circuit Breaker Controls Load Voltages from 0V to 6V. 3 Selectable Circuit Breaker Thresholds.

Dual Level Overcurrent Fault Protection

LT4356-1 Surge Stopper Overvoltage/Overcurrent Protection

Regulator

Wide Operation Range: 4V to 80V. Reverse Input Protection to –60V.

Adjustable Output Clamp Voltage

LTC4411 SOT-23 Ideal Diode 2.6A Forward Current, 28mV Regulated Forward Voltage

LTC4412 2.5V to 28V, Low Loss PowerPath™ Controller in

ThinSOT

More Efficient than Diode-ORing, Automatic Switching Between DC Sources,

Simplified Load Sharing

LTC4413-1/

LTC4413-2

Dual 2.6A, 2.5V to 5.5V Fast Ideal Diodes in

3mm × 3mm DFN

130mΩ On Resistance, Low Reverse Leakage Current, 18mV Regulated

Forward Voltage (LTC4413-2 with Overvoltage Protection Sensor)

5V System Protected from ±24V Power

Supplies and Reverse Current

VIO

COUT

10µF

LN1351CTR

Si1471DH M1 M3

FDC6561AN

436012 TA03

VOUT

0.5A

VIN

GATE

LTC4360-2

GATEP

OUT

PWRGD

GND