2.5V LVDS 1:6 Clock Buffer
Terabuffer™ II IDT5T9306
DATA SHEET
IDT5T9306 REVISION C MAY 30, 2012 1©2012 Integrated Device Technology, Inc.
GL
G
PD
A1
A1
A2
A2
SEL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
Q2
Q2
Q1
Q1
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
1
0
DESCRIPTION:
The IDT5T9306 2.5V differential clock buffer is a user-selectable
differential input to six LVDS outputs. The fanout from a differential input
to six LVDS outputs reduces loading on the preceding driver and provides
an efficient clock distribution network. The IDT5T9306 can act as a
translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V
LVTTL input can also be used to translate to LVDS outputs. The redundant
input capability allows for an asynchronous change-over from a primary
clock source to a secondary clock source. Selectable reference inputs are
controlled by SEL.
The IDT5T9306 outputs can be asynchronously enabled/disabled. When
disabled, the outputs will drive to the value selected by the GL pin. Multiple
power and grounds reduce noise.
FEATURES:
• Guaranteed Low Skew < 40ps (max)
• Very low duty cycle distortion < 125ps (max)
• High speed propagation delay < 1.75ns (max)
• Additive phase jitter, RMS 0.159ps (typical) @ 125MHz
• Up to 1GHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML, or LVDS input interface
• Selectable differential inputs to six LVDS outputs
• Power-down mode
• 2.5V VDD
• Available in VFQFPN package
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
• Clock distribution
IDT5T9306 REVISION C MAY 30, 2012 2©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
PIN CONFIGURATION
18
21
20
19
17
16
15
PD
A2
Q4
Q4
VDD
A2
VDD
14
138910
11 12
Q
2
Q
2
Q
3
Q
3
V
DD
GL
V
DD
27 26 25 24 23 22
28
V
DD
SEL
Q
6
Q
6
Q
5
Q
5
NC
1
2
3
4
5
6
7
VDD
G
Q1
Q1
VDD
A1
A1
GND
VFQFPN
TOP VIEW
IDT5T9306 REVISION C MAY 30, 2012 3©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
Symbol Description Max Unit
VDD Power Supply Voltage –0.5 to +3.6 V
VIInput Voltage –0.5 to +3.6 V
VOOutput Voltage(2) –0.5 to VDD +0.5 V
TSTG Storage Temperature –65 to +150 °C
TJJunction Temperature 150 °C
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. Not to exceed 3.6V.
Symbol Parameter Min Typ. Max. Unit
CIN Input Capacitance —— 3pF
CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested
Symbol Description Min. Typ. Max. Unit
TAAmbient Operating Temperature –40 +25 +85 °C
VDD Internal Power Supply Voltage 2.3 2.5 2.7 V
RECOMMENDED OPERATING RANGE
PIN DESCRIPTION
Symbol I/O Type Description
A[1:2] I Adjustable(1,4) Clock input. A[1:2] is the "true" side of the differential clock input.
A[1:2] I Adjustable(1,4) Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For LVTTL single-ended operation, A[1:2] should be set
to the desired toggle voltage for A[1:2]:
3.3V LVTTL VREF = 1650mV
2.5V LVTTL VREF = 1250mV
GI LVTTL Gate control for differential outputs Q1 and Q1 through Q6 and Q6. When G is LOW, the differential outputs are active. When G
is HIGH, the differential outputs are asynchronously driven to the level designated by GL(2).
GL I LVTTL Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true"
outputs disable LOW and "complementary" outputs disable HIGH.
Qn O LVDS Clock outputs
Qn O LVDS Complementary clock outputs
SEL I LVTTL Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1.
PD I LVTTL Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled.
Both "true" and "complementary" outputs will pull to VDD. Set HIGH for normal operation.(3)
VDD PWR Power supply for the device core and inputs
GND PWR Power supply return for all power
NC No connect; recommended to connect to GND
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be
able to tolerate them in down stream circuitry.
3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after asserting
PD.
4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.
IDT5T9306 REVISION C MAY 30, 2012 4©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANG
Symbol Parameter Test Conditions Min. Typ.(2) Max Unit
Input Characteristics
IIH Input HIGH Current VDD = 2.7V — — ±5 μA
IIL Input LOW Current VDD = 2.7V — — ±5
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA — - 0.7 - 1.2 V
VIN DC Input Voltage - 0.3 — +3.6 V
VIH DC Input HIGH 1.7 — — V
VIL DC Input LOW — — 0.7 V
VTHI DC Input Threshold Crossing Voltage — VDD /2 — V
VREF Single-Ended Reference Voltage(3) 3.3V LVTTL — 1.65 — V
2.5V LVTTL — 1.25 —
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR
DIFFERENTIAL INPUTS(1)
Symbol Parameter Test Conditions Min. Typ.(2) Max Unit
Input Characteristics
IIH Input HIGH Current VDD = 2.7V — — ±5 μA
IIL Input LOW Current VDD = 2.7V — — ±5
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA — - 0.7 - 1.2 V
VIN DC Input Voltage - 0.3 — +3.6 V
VDIF DC Differential Voltage(3) 0.1 — — V
VCM DC Common Mode Input Voltage(4) 0.05 — VDD V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The DC differential voltage
must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2.
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
RANGE FOR LVDS(1)
Symbol Parameter Test Conditions Min. Typ.(2) Max Unit
Output Characteristics
VOT(+) Differential Output Voltage for the True Binary State 247 — 454 mV
VOT(-) Differential Output Voltage for the False Binary State 247 — 454 mV
ΔVOT Change in VOT Between Complementary Output States — — 50 mV
VOS Output Common Mode Voltage (Offset Voltage) 1.125 1.2 1.375 V
ΔVOS Change in VOS Between Complementary Output States — — 50 mV
IOS Outputs Short Circuit Current VOUT + and VOUT - = 0V — 12 24 mA
IOSD Differential Outputs Short Circuit Current VOUT + = VOUT -—612mA
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, TA = +25°C ambient.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVTTL(1)
IDT5T9306 REVISION C MAY 30, 2012 5©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 1V
VXDifferential Input Signal Crossing Point(2) 900 mV
DHDuty Cycle 50 %
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 2 V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification
under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual
use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 1V
VXDifferential Input Signal Crossing Point(2) 750 mV
DHDuty Cycle 50 %
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 2 V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification
under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual
use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL (2.5V) AND
LVPECL (3.3V)
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 732 mV
VXDifferential Input Signal Crossing Point(2) LVEPECL 1082 mV
LVPECL 1880
DHDuty Cycle 50 %
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 2 V/ns
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification
under actual use conditions.
2. 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point levels are specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This
device meets the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
IDT5T9306 REVISION C MAY 30, 2012 6©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVDS
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 400 mV
VXDifferential Input Signal Crossing Point(2) 1.2 V
DHDuty Cycle 50 %
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 2 V/ns
NOTES:
1. The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification
under actual use conditions.
2. A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use
conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
POWER SUPPLY CHARACTERISTICS FOR LVDS OUTPUTS(1)
Symbol Parameter Test Conditions Typ. Max Unit
IDDQ Quiescent VDD Power Supply Current VDD = Max., All Input Clocks = LOW(2) —240 mA
Outputs enabled
ITOT Total Power VDD Supply Current VDD = 2.7V., FREFERENCE CLOCK = 1GHz —250 mA
IPD Total Power Down Supply Current PD = LOW — 5 mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.
2. The true input is held LOW and the complementary input is held HIGH.
AC DIFFERENTIAL INPUT SPECIFICATIONS(1)
Symbol Parameter Min. Typ. Max Unit
VDIF AC Differential Voltage(2) 0.1 — 3.6 V
VIX Differential Input Crosspoint Voltage 0.05 — VDD V
VCM Common Mode Input Voltage Range(3) 0.05 — VDD V
VIN Input Voltage - 0.3 +3.6 V
NOTES:
1. The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has been met or exceeded.
2. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The AC differential voltage must be
achieved to guarantee switching to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2.
IDT5T9306 REVISION C MAY 30, 2012 7©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(1,5)
Symbol Parameter Min. Typ. Max Unit
Skew Parameters
tSK(O) Same Device Output Pin-to-Pin Skew(2) ——40 ps
tSK(P) Pulse Skew(3) ——125 ps
tSK(PP) Part-to-Part Skew(4) ——300 ps
Propagation Delay
tPLH Propagation Delay A, A Crosspoint to Qn, Qn Crosspoint —1.25 1.75 ns
tPHL
fOFrequency Range(6) ——1 GHz
Output Gate Enable/Disable Delay
tPGE Output Gate Enable Crossing VTHI to Qn/Qn Crosspoint ——3.5 ns
tPGD Output Gate Disable Crossing VTHI to Qn/Qn Crosspoint Driven to GL Designated Level ——3.5 ns
Power Down Timing
tPWRDN PD Crossing VTHI to Qn = VDD, Qn = VDD ——100 μS
tPWRUP Output Gate Disable Crossing VTHI to Qn/Qn Driven to GL Designated Level ——100 μS
RMS Additive Phase JitterRMS Additive Phase Jitter @ 25MHz (12kHz – 10MHz Integration Range) 0.541 ps
tJIT RMS Additive Phase Jitter @ 125MHz (12kHz – 20MHz Integration Range) 0.159 ps
RMS Additive Phase Jitter @ 156.25MHz (12kHz – 20MHz Integration Range) 0.185 ps
Output Rise/Fall Time
tR/tFOutput Rise/Fall Time(6), (20% - 80%) 125 600 ps
NOTES:
1. AC propagation measurements should not be taken within the first 100 cycles of startup.
2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
3. Skew measured is the difference between propagation delay times tPHL and tPLH of any differential output pair under identical input and output interfaces, transitions and load conditions on
any one device.
4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices, given identical transitions and load conditions at identical
VDD levels and temperature.
5. All parameters are tested with a 50% input duty cycle.
6. Guaranteed by design but not production tested.
IDT5T9306 REVISION C MAY 30, 2012 8©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
tPLH tPHL
tSK(O) tSK(O)
Qn - Qn
Qm - Qm
+ VDIF
VDIF = 0
- VDIF
+ VDIF
VDIF = 0
- VDIF
A[1:2] - A[1:2]
+ VDIF
VDIF = 0
- VDIF
1/fo
DIFFERENTIAL AC TIMING WAVEFORMS
Output Propagation and Skew Waveforms
NOTES:
1. Pulse skew is calculated using the following expression:
tSK(P) = | tPHL - tPLH |
Note that the tPHL and tPLH shown above are not valid measurements for this calculation because they are not taken from the same pulse.
2. AC propagation measurements should not be taken within the first 100 cycles of startup.
IDT5T9306 REVISION C MAY 30, 2012 9©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
Power Down Timing
NOTES:
1. It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after asserting
PD.
2. The POWER DOWN TIMING diagram assumes that GL is HIGH.
3. It should be noted that during power-down mode, the outputs are both pulled to VDD. In the POWER DOWN TIMING diagram this is shown when Qn-Qn goes to VDIF = 0.
A1 - A1
GVTHI
VIH
VIL
Qn - Qn
+VDIF
VDIF=0
-
V
DIF
+VDIF
VDIF=0
-VDIF
+VDIF
VDIF=0
-VDIF
PD
A2 - A2
VTHI
VIH
VIL
Differential Gate Disable/Enable Showing Runt Pulse Generation
NOTE:
1. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time the G signal to avoid this problem.
tPLH
GL
G
Qn - Qn
tPGD tPGE
VIH
VTHI
VIL
VIH
VTHI
VIL
+ VDIF
VDIF = 0
- VDIF
A[1:2] - A[1:2]
+ VDIF
VDIF = 0
- VDIF
IDT5T9306 REVISION C MAY 30, 2012 10 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
TEST CIRCUITS AND CONDITIONS
VDD/2
D.U.T.
A
A
Pulse
Generator
~50
Transmission Line
~50
Transmission Line
VIN
VIN
-VDD/2
Scope
50
50
Test Circuit for Differential Input
DIFFERENTIAL INPUT TEST CONDITIONS
Symbol VDD = 2.5V ± 0.2V Unit
VTHI Crossing of A and AV
IDT5T9306 REVISION C MAY 30, 2012 11 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
VDD
D.U.T.
A
A
Qn
Qn
Pulse
Generator RL
RL
VOS VOD
VDD/2
D.U.T.
A
A
Qn
Qn
Pulse
Generator 50
50
Z = 50
Z = 50
SCOPE
CL
-VDD/2
CL
Test Circuit for DC Outputs and Power Down Tests
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing
NOTES:
1. Specifications only apply to "Normal Operations" test condition. The TIA/EIA specification load is for reference only.
2. The scope inputs are assumed to have a 2pF load to ground. TIA/EIA - 644 specifies 5pF between the output pair. With CL = 8pF, this gives the test circuit appropriate 5pF equivalent load.
LVDS OUTPUT TEST CONDITION
Symbol VDD = 2.5V ± 0.2V Unit
CL0(1) pF
8(1,2)
RL50 Ω
IDT5T9306 REVISION C MAY 30, 2012 12 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
FIGURE 1. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
In order to maximize both the removal of heat from the package and the
electrical performance, a land pattern must be incorporated on the Printed
Circuit Board (PCB) within the footprint of the package corresponding to
the exposed metal pad or exposed heat slug on the package, as shown
in Figure 1. The solderable area on the PCB, as defined by the solder
mask, should be at least the same size/shape as the exposed pad/slug
area on the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the outer
edges of the land pattern and the inner edges of pad pattern for the
leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer and
electrical grounding from the package to the board through a solder joint,
thermal vias are necessary to effectively conduct from the surface of the
PCB to the ground plane(s). The land pattern must be connected to ground
through these vias. The vias act as “heat pipes”. The number of vias (i.e.
“heat pipes”) are application specific and dependent upon the package
power dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal and electrical
performance is achieved when an array of vias is incorporated in the
land pattern. It is recommended to use as many vias connected to ground
as possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the soldering
process which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to eliminate any
solder voids between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only. For further
information, refer to the Application Note on the Surface Mount Assembly
of Amkor’s Thermally/Electrically Enhance Leadframe Base Package,
Amkor Technology.
THERMAL VIA
LAND PATTERN
SOLDER PIN
SOLDER
PIN PADPIN PAD
PIN
GROUND PLANE
EXPOSED HEAT SLUG
(GROUND PAD)
VFQFPN EPAD THERMAL RELEASE PATH
IDT5T9306 REVISION C MAY 30, 2012 13 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
Figure 2 shows an example of IDT5T9306 schematic. In this
example, the device is operated at VDD = 2.5V. As with any high
speed analog circuitry, the power supply pins are vulnerable to
random noise. To achieve optimum jitter performance, power
supply isolation is required.
In order to achieve the best possible filtering, it is recommended
that the placement of the filter components be on the device side
of the PCB as close to the power pins as possible. If space is
limited, the 0.1μF capacitor in each power pin filter should be
placed on the device side of the PCB and the other components
can be placed on the opposite side.
Power supply filter recommendations are a general guideline to
be used for reducing external noise from coupling into the
SCHEMATIC LAYOUT
devices. The filter performance is designed for a wide range of
noise frequencies. This low-pass filter starts to attenuate noise
at approximately 10kHz. If a specific frequency noise component
is known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if
required, additional filtering be added. Additionally, good
general design practices for power plane voltage stability
suggests adding bulk capacitance in the local area of all devices.
The schematic example focuses on functional connections and
is not configuration specific. Refer to the pin description and
functional tables in the datasheet to ensure that the logic control
inputs are properly set.
Q1
VDD
VD D
Q1
A1
C6
0.1uF
Alternate
LVDS
Terminat ion
LVDS Termination
Zo = 50
/Q1
RD1
Not Install
C4
0. 1 uF
R4
50
/Q 6
Q5
C7
0. 1 uF
/Q6
C8
0.1uF
Q3
Zo_Diff = 100 Ohm
/Q2
C9
0.1uF
VD D
/Q1
R6
50
RU1
1K
Q4
VD D
+
-
SEL
C10
10uF
R8
100
A2
Zo = 50
Q6
2. 5 V LV P EC L D r iv e r
/G
VDD
R7
50
Z o_Diff = 100 Ohm
U1
1
2
3
4
5
6
7
8
9
11
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
27
29
/G
VDD
Q1
/Q1
VDD
A1
/A1
GL
VD D
/Q 2
Q2
Q3
/Q 3
VDD
/A2
A2
VD D
/Q 4
Q4
VD D
/PD
NC
/Q 5
Q5
/Q 6
Q6
SEL
VD D
GND
Logic Input Pin Examples
To L ogic
In put
pi ns
VD D
BL M1 8B B2 21 SN 1
Ferrite B ead
1 2
C3
0.1uF
LVDS Driv er
+
-
Q2
RD2
1K
C1
0.1uF
Q6
Zo_Di ff = 100 Ohm
/Q5/Q3
RU2
Not Install
VDD=2. 5V
VD D
To Logic
In put
pins
GL
C5
0.1uF
2.5V
C2
0. 1 uF
Set Logic
Input to
'1'
R2
18
/Q4
R1
100
VD D
/P D
/A2
VD D
Set Logic
Input to
'0'
/A1
R5
50
VDD
FIGURE 2. IDT5T3906 SCHEMATIC EXAMPLE
IDT5T9306 REVISION C MAY 30, 2012 14 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
RECOMMENDED LANDING PATTERN
NL 28 pin
NOTE: All dimensions are in millimeters.
IDT5T9306 REVISION C MAY 30, 2012 15 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
July 23, 2002 Datasheet creation
October 8, 2002 Page 1, entire page changed; page 2, both diagrams; page 3, Pin Description and notes; page 4, DC Cha. for LVPECL
and Differential Input tables; page 6, DC Cha. and Power Supply tables; page 7, entire page; page 9, added note 3; page
10, entire page; page 10, entire page; page 11, entire page; page 12, Ordering Info; added 3 new pages (10 thru 12) of
diagrams.
October 10, 2002 Page 1, entire page changed; page 2, both diagrams; page 3, Pin Description and notes; page 7, AC Cha. table; page
8, added new LVPECL table; page 10, removed Input Clock Switching diagram; page 11, deleted entire page; page
12, changed Power Down Timing; page 15, Ordering Info.
October 24, 2002 Page 2, added note 1 to TQFP TOP VIEW text; page3, aded note 4 to Pin Description; page 4, replaced "Compliant
devices must meet" with the text "This device meets" in four instances; page 5, Differential Input table, note 1, changed
1V to 732mV and replaced "Compliant devices must meet" with the text "This device meets"; page 6, DC Electrical table,
Vdif row, changed Min. value to 0.1, and under Differential Input table replaced "Compliant devices must meet" with
the text "This device meets" page 7, Power Supply table, replaced ((TBD)) with 800MHz, and under AC Electrical table,
replaced ((TBD)) with 500; page 8, completely altered AC DIfferential table; page 12, LVDS Output table, replaced
((TBD)) with 3.
November 1, 2002 Radical changes to entire document.
December 12, 2002 Radical changes to entire document, using 5T9316 as a base.
December 16, 2002 Throughout document, removed "Differential" from title; page 7, Power Supply table, changed Max values, changed
FREFERENCE value; page 10, note 1, changed Gx to G.
May 8, 2003 Page 2, corrected pinout diagram.
August 7, 2003 Page 1, Features text, 3rd bullet, changed 2ns to 1.75ns, 4th bullet, changed 800MHz to 1GHz, and 7th bullet, added
CML, on Description, 3rd line, added CML to list; page 4, Pin Descr., note 1, added "Differential CML levels", for
Description of PD row, replaced 2nd sentence with "Both 'true' and 'complementary' output will pull to Vdd"; page 5,
DC... for Differential Inputs table, removed note 5 and changed Vcm Max. from 3.5 to Vdd; page 7, Power Supply table,
changed 800MHz to 1GHz; page 8, AC Differential table, changed Vix and Vcm Max specs from 3.5V to Vdd, removed
notes 4 and 5, and placed entire table on page 7, for AC Elect. table, added notes 5 and 6, changed ((TBD)) to 300ps,
tplh Type to 1.25ns, and Max from 2ns to 1.75ns, and changed fo Max from 800MHz to 1GHz.
October 2, 2003 Page 1, Features, 7th bullet, added "3.3V / 2,5V LVTTL" to front, Description, added to 1st paragraph "A single-ended
3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs."; page 4, Pin Description table, added large block
of text to 2nd row, added "Single-ended 3.3V and 2.5V LVTTL levels" to note 1; page 5, DC for LVTTL table, added Vref
row and note 3, for DC for LVDS table, changed Ios ratings from 5 Typ, 7.5 Max to 12 Typ, 24 Max, and changed Iosd
ratings from 5 Typ, 7.5 Max to 6 Typ, 12 Max; page 7, Power Supply table, changed Ipd from 3 to 5.
March 26, 2004 Page 2, changed pin 22 to NC; page 3, changed pin 25 to NC; page 4, added NC row to Pin Description.
June 22, 2004 Removed TQFP package.
October 26, 2004 Inserted a page before Ordering Info and added Landing Pattern.
October 27, 2004 Added note to Landing Pattern.
October 29, 2004 Changed landing pattern diagram.
March 9, 2005 Page 6, switched Iddq and Itot values.
October 23, 2007 Page 7, added Additive Phase Jitter, RMS specs to the AC Electrical Characterisitcs Table.
April 15, 2008 Page 7, added Rise/Fall Time spec. to the AC Electrical Characteristics Table.
January 31, 2011 Page 12, added VFQFPN Thermal Release Path application note.
Updated to header/footer to new format.
March 13, 2012 Page 13, added schematic layout.
Page 16, corrected ordering information table.
May 30, 2012 Page 1, Features Section - changed Low Skew spec to <40ps (max) from <25ps.
Page 7, AC Charastics Table - tsk(o) Max from 25ps to 40ps.
REVISION HISTORY SHEET
IDT5T9306 REVISION C MAY 30, 2012 16 ©2012 Integrated Device Technology, Inc.
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
ORDERING INFORMATION
I
DT
XXXXX
Package
Device Type
5T9306 2.5V 1:6 LVDS Clock Buffer Terabuffer™
II
Thermally Enhanced Plastic Very Fine Pitc
h
Quad Flat No Lead Package - Green
NLG
I
XX
Process
X
-40 C to +85 C (Industrial)
IDT5T9306
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
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information in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the
described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided
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Copyright 2012. All rights reserved.
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