CY7C109D CY7C1009D PRELIMINARY 1-Mbit (128K x 8) Static RAM Features memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). * Pin- and function-compatible with CY7C109B/CY7C1009B * High speed -- tAA = 10 ns * Low active power Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. -- ICC = 60 mA @ 10 ns * Low CMOS standby power -- ISB2 = 1.2 mA (`L' Version only) * 2.0V Data Retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2, and OE options The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C109D is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009D is available in a 300-mil-wide SOJ Pb-Free package. The CY7C1009D and CY7C109D are functionally equivalent in all other respects. * Available in Pb-Free Packages Functional Description[1] The CY7C109D/CY7C1009D is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy Logic Block Diagram Pin Configurations I/O0 INPUT BUFFER I/O2 512 x 256 x 8 ARRAY SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O1 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP I Top View (not to scale) I/O3 I/O4 I/O5 COLUMN DECODER CE1 CE2 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 SOJ Top View NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 109D-2 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O7 A9 A 10 A 11 A 12 A 13 A14 A15 A16 OE I/O6 POWER DOWN 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Non-L Com'l / Ind'l Low Power Version CY7C109D-10 CY7C1009D-10 10 60 3 1.2 CY7C109D-12 CY7C1009D-12 12 50 3 1.2 Unit ns mA mA Note: 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05468 Rev. *C * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised January 10, 2005 CY7C109D CY7C1009D PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. -65C to +150C Latch-up Current..................................................... > 200 mA Ambient Temperature with Power Applied............................................. -55C to +125C Operating Range [2] Supply Voltage on VCC to Relative GND .... -0.5V to +7.0V Range DC Voltage Applied to Outputs in High-Z State[2] ....................................-0.5V to VCC + 0.5V Commercial Ambient Temperature VCC 0C to +70C 5V 10% -40C to +85C 5V 10% Industrial DC Input Voltage[2] .................................-0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range 7C109D-10 7C1009D-10 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage[2] IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VI < VCC, Output Disabled IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 ISB2 Min. Max. 2.4 7C109D-12 7C1009D-12 Min. Max. Unit 2.4 V 0.4 V 2.0 VCC + 0.3 0.4 2.0 VCC + 0.3 V -0.5 0.8 -0.5 0.8 V -1 +1 -1 +1 A -1 +1 -1 +1 A -300 -300 mA 60 50 mA Automatic CE Max. VCC, CE1 > VIH Power-Down Current or CE2 < VIL, VIN > VIH or --TTL Inputs VIN < VIL, f = fMAX 10 10 mA Max. VCC, Automatic CE Power-Down Current CE1 > VCC - 0.3V, --CMOS Inputs or CE2 < 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 3 3 mA 1.2 1.2 mA L Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. Unit 9 pF 8 pF Thermal Resistance[4] Parameter Description JA Thermal Resistance (Junction to Ambient)[4] JC Thermal Resistance (Junction to Case)[4] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board All-Packages Unit TBD C/W TBD C/W Notes: 2. VIL (min.) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05468 Rev. *C Page 2 of 9 CY7C109D CY7C1009D PRELIMINARY AC Test Loads and Waveforms 10-ns Device ALL INPUT PULSES Z = 50 3.0V OUTPUT 90% 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* GND 1.5V 90% 10% 10% 3 ns 3 ns (a) 12 -ns Devices THEVENIN EQUIVALENT 167 1.73V OUTPUT Equivalent to: R1 480 5V 10-ns Device OUTPUT R2 255 30 pF INCLUDING JIG AND SCOPE (b) R1 480 5V OUTPUT R2 255 5 pF INCLUDING JIG AND SCOPE (c) Switching Characteristics Over the Operating Range[7] 7C109D-10 7C1009D-10 Parameter Description Min. Max. 7C109D-12 7C1009D-12 Min. Max. Unit Read Cycle tpower[5] VCC(typical) to the first access 100 10 tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE OE HIGH to High 12 10 3 3 5 0 tLZCE CE1 LOW to Low Z, CE2 HIGH to Low tHZCE CE1 HIGH to High Z, CE2 LOW to High Z[8, 9] tPU CE1 LOW to Power-Up, CE2 HIGH to Power-Up tPD CE1 HIGH to Power-Down, CE2 LOW to Power-Down 3 12 ns 6 ns ns 6 3 5 0 ns ns 6 0 10 ns ns 0 5 Z[9] ns 12 10 Z[8, 9] s 100 ns ns 12 ns Write Cycle[10] tWC Write Cycle Time[11] 10 12 ns tSCE CE1 LOW to Write End, CE2 HIGH to Write End 8 10 ns tAW Address Set-Up to Write End 7 10 ns Notes: 5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed 6. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05468 Rev. *C Page 3 of 9 CY7C109D CY7C1009D PRELIMINARY Switching Characteristics Over the Operating Range[7] 7C109D-10 7C1009D-10 Parameter Description Min. Max. 7C109D-12 7C1009D-12 Min. Max. Unit tHA Address Hold from Write End 0 tSA Address Set-Up to Write Start tPWE WE Pulse Width tSD Data Set-Up to Write End tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low Z[9] 3 3 ns tHZWE WE LOW to High Z[8, 9] 0 ns 0 0 ns 7 10 ns 6 7 ns 6 6 ns Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR [4] Conditions Non-L, Com'l / Ind'l L-Version Only Min. Unit 3 mA 1.2 mA 2.0 VCC = VDR = 2.0V, CE1 > VCC - 0.3V or CE2 < 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Chip Deselect to Data Retention Time tR[6] Max Operation Recovery Time V 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 4.5V VDR > 2V 4.5V tR tCDR CE Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 12. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 13. WE is HIGH for read cycle. Document #: 38-05468 Rev. *C Page 4 of 9 CY7C109D CY7C1009D PRELIMINARY Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Write Cycle No. 1 (CE1 or CE2 Controlled)[15, 16] tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Notes: 14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 15. Data I/O is high impedance if OE = VIH. 16. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05468 Rev. *C Page 5 of 9 CY7C109D CY7C1009D PRELIMINARY Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[15, 16] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 17 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[16] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tHA tSA tPWE WE tSD NOTE 17 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE1 CE2 OE WE H X X X High Z I/O0-I/O7 Power-down Mode Standby (ISB) Power X L X X High Z Power-down Standby (ISB) L H L H Data Out Read Active (ICC) L H X L Data In Write Active (ICC) L H H H High Z Selected, Outputs Disabled Active (ICC) Note: 17. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05468 Rev. *C Page 6 of 9 CY7C109D CY7C1009D PRELIMINARY Ordering Information Speed (ns) 10 12 Package Name Package Type CY7C109D-10VXC V33 32-Lead (400-Mil) Molded SOJ (Pb-Free) CY7C1009D-10VXC V32 32-Lead (300-Mil) Molded SOJ (Pb-Free) CY7C109D-10ZXC Z32 32-Lead TSOP Type I (Pb-Free) CY7C109D-10VXI V33 32-Lead (400-Mil) Molded SOJ (Pb-Free) CY7C1009D-10VXI V32 32-Lead (300-Mil) Molded SOJ (Pb-Free) CY7C109D-10ZXI Z32 32-Lead TSOP Type I (Pb-Free) CY7C109D-12VXC V33 32-Lead (400-Mil) Molded SOJ (Pb-Free) CY7C1009D-12VXC V32 32-Lead (300-Mil) Molded SOJ (Pb-Free) CY7C109D-12ZXC Z32 32-Lead TSOP Type I (Pb-Free) CY7C109D-12VXI V33 32-Lead (400-Mil) Molded SOJ (Pb-Free) CY7C1009D-12VXI V32 32-Lead (300-Mil) Molded SOJ (Pb-Free) CY7C109D-12ZXI Z32 32-Lead TSOP Type I (Pb-Free) Ordering Code Operating Range Commercial Industrial Commercial Industrial Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Package Diagrams 32-Lead (300-Mil) Molded SOJ V32 51-85041-*A Document #: 38-05468 Rev. *C Page 7 of 9 PRELIMINARY CY7C109D CY7C1009D Package Diagrams (continued) 32-Lead (400-Mil) Molded SOJ V33 51-85033-*B 32-Lead Thin Small Outline Package Type I (8x20 mm) Z32 51-85056-*D All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05468 Rev. *C Page 8 of 9 (c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C109D CY7C1009D PRELIMINARY Document History Page Document Title: CY7C109D, CY7C1009D 1-Mbit (128K x 8) SRAM (Preliminary) Document Number: 38-05468 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 233722 See ECN RKF DC parameters are modified as per EROS (Spec # 01-2165) Pb-free offering in Ordering Information *B 262950 See ECN RKF Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information *C 307596 See ECN RKF Reduced Speed bins to -10 and -12 ns Document #: 38-05468 Rev. *C Page 9 of 9