AOD403/AOI403
30V P-Channel MOSFET
General Description Product Summary
V
DS
I
D
(at V
GS
= -20V) -70A
R
DS(ON)
(at V
GS
= -20V) < 6.2mΩ(< 6.7mΩ
∗
)
R
DS(ON)
(at V
GS
= -10V) < 8mΩ(< 8.5mΩ
∗
)
100% UIS Tested
100% R
g
Tested
Symbol
V
DS
V
GS
V
±2
5
Gate-Source Voltage
Drain-Source Voltage -30
The AOD403/AOI403 uses advanced trench technology to
provide excellent R
DS(ON)
, low gate charge and low gate
resistance. With the excellent thermal resistance of the
DPAK/IPAK package, this device is well suited for high
current load applications.
V
Maximum UnitsParameter
Absolute Maximum Ratings T
A
=25°C unless otherwise noted
-30V
TO252
DPAK
Top View
Bottom View
G
S
D
G
S
D
G
D
S
G
G
D
D
S
S
Top View
Bottom View
TO251A
IPAK
V
GS
I
DM
I
AS
, I
AR
E
AS
, E
AR
T
J
, T
STG
Symbol
t ≤ 10s
Steady-State
Steady-State
R
θJC
* package TO251A
Typ Max
T
C
=25°C
2.5
45
T
C
=100°C
Junction and Storage Temperature Range -55 to 175 °C
Thermal Characteristics Units
Maximum Junction-to-Ambient
A
°C/W
R
θJA
16
41 20
Parameter
V
±2
5
Gate-Source Voltage
Avalanche energy L=0.1mH
C
mJ
Avalanche Current
C
-12 A
A
T
A
=25°C I
DSM
A
T
A
=70°C
-200Pulsed Drain Current
C
Continuous Drain
Current
G
I
D
-70
-55
T
C
=25°C
T
C
=100°C
Power Dissipation
B
P
D
Continuous Drain
Current
125
-15
-50
W
Power Dissipation
A
P
DSM
W
T
A
=70°C
90
1.6
T
A
=25°C
Maximum Junction-to-Case °C/W
°C/W
Maximum Junction-to-Ambient
A D
0.9 50
1.6
Rev.9.0: July 2013
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of 6
AOD403/AOI403
Symbol Min Typ Max Units
BV
DSS
-30 V
V
DS
=-30V, V
GS
=0V -1
T
J
=55°C -5
I
GSS
±100 nA
V
GS(th)
Gate Threshold Voltage -1.5 -2.5 -3.5 V
I
D(ON)
-200 A
5.1 6.2
T
J
=125°C 7.6 9.2
g
FS
42 S
V
SD
-0.7 -1 V
I
S
-70 A
C
iss
2310 2890 3500 pF
C
oss
410 585 760 pF
C
rss
280 470 660 pF
R
g
1.9 3.8 5.7 Ω
Q
40
51
61
nC
R
DS(ON)
mΩ
mΩ
5.6 6.7
6.7 8.5
Reverse Transfer Capacitance
Maximum Body-Diode Continuous Current
G
Input Capacitance
Output Capacitance
DYNAMIC PARAMETERS
Gate resistance V
GS
=0V, V
DS
=0V, f=1MHz
Total Gate Charge
mΩ
TO252
6.2 8 mΩ
V
GS
=-20V, I
D
=-20A
TO251A
I
DSS
µA
V
DS
=V
GS
I
D
=-250µA
V
DS
=0V, V
GS
= ±25V
Zero Gate Voltage Drain Current
Gate-Body leakage current
V
GS
=-10V, V
DS
=-5V
V
GS
=-20V, I
D
=-20A
Forward Transconductance
Diode Forward Voltage
V
GS
=-10V, I
D
=-20A
TO252
I
S
=-1A,V
GS
=0V
V
DS
=-5V, I
D
=-20A
On state drain current
Static Drain-Source On-Resistance
VGS=-10V, ID=-20A
TO251A
V
GS
=0V, V
DS
=-15V, f=1MHz
SWITCHING PARAMETERS
Electrical Characteristics (T
J
=25°C unless otherwise noted)
STATIC PARAMETERS Parameter Conditions
Drain-Source Breakdown Voltage I
D
=-250µA, V
GS
=0V
Q
g
40
51
61
nC
Q
gs
10 12 14 nC
Q
gd
10 16 22 nC
t
D(on)
16 ns
t
r
12 ns
t
D(off)
45 ns
t
f
22 ns
t
rr
14 18 22 ns
Q
rr
911 13 nC
THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING
OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,
FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
Body Diode Reverse Recovery Charge I
F
=-20A, dI/dt=100A/µs
Turn-On DelayTime
Turn-On Rise Time
Turn-Off Fall Time
Total Gate Charge
V
GS
=-10V, V
DS
=-15V, I
D
=-20A
Gate Source Charge
Gate Drain Charge
V
GS
=-10V, V
DS
=-15V, R
L
=0.75Ω,
R
GEN
=3Ω
Turn-Off DelayTime
I
F
=-20A, dI/dt=100A/µs
Body Diode Reverse Recovery Time
A. The value of RθJA is measured with the device mounted on 1in2FR-4 board with 2oz. Copper, in a still air environment with TA=25°C. The
Power dissipation PDSM is based on R θJA and the maximum allowed junction temperature of 150°C. The value in any given application depends
on the user's specific board design, and the maximum temperature of 175°C may be used if the PCB allows it.
B. The power dissipation PDis based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper
dissipation limit for cases where additional heatsinking is used.
C. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=175°C. Ratings are based on low frequency and duty cycles to keep initial
TJ =25°C.
D. The RθJA is the sum of the thermal impedence from junction to case RθJC and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300µs pulses, duty cycle 0.5% max.
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming a
maximum junction temperature of TJ(MAX)=175°C. The SOA curve provides a single pulse rating.
G. The maximum current rating is package limited.
H. These tests are performed with the device mounted on 1 in2FR-4 board with 2oz. Copper, in a still air environment with TA=25°C.
Rev.9.0: July 2013 www.aosmd.com Page 2 of 6
AOD403/AOI403
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
17
5
2
10
0
18
0
20
40
60
80
100
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
-ID(A)
-VGS(Volts)
Figure 2: Transfer Characteristics (Note E)
2
4
6
8
10
0 5 10 15 20 25 30
RDS(ON) (mΩ
Ω
Ω
Ω)
-ID(A)
Figure 3: On-Resistance vs. Drain Current and
Gate Voltage (Note E)
0.8
1
1.2
1.4
1.6
1.8
0 25 50 75 100 125 150 175 200
Normalized On-Resistance
Temperature (°C)
Figure 4: On-Resistance vs. Junction Temperature
(Note E)
VGS=-10V
ID=-20A
VGS=-20V
ID=-20A
25°C
125°C
V
DS
=-5V
VGS=-10V
VGS=-20V
0
20
40
60
80
100
012345
-ID(A)
-VDS (Volts)
Fig 1: On-Region Characteristics (Note E)
V
GS
=-4V
-4.5V
-6V
-10V
-5V
18
40
Gate Voltage (Note E)
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E+00
1.0E+01
1.0E+02
0.0 0.2 0.4 0.6 0.8 1.0 1.2
-IS(A)
-VSD (Volts)
Figure 6: Body-Diode Characteristics (Note E)
25°C
125°C
(Note E)
0
5
10
15
20
0 5 10 15 20
RDS(ON) (mΩ
Ω
Ω
Ω)
-VGS (Volts)
Figure 5: On-Resistance vs. Gate-Source Voltage
(Note E)
ID=-20A
25°C
125°C
Rev.9.0: July 2013 www.aosmd.com Page 3 of 6
AOD403/AOI403
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
0
2
4
6
8
10
0 10 20 30 40 50 60
-VGS (Volts)
Qg(nC)
Figure 7: Gate-Charge Characteristics
0
1000
2000
3000
4000
5000
0 5 10 15 20 25 30
Capacitance (pF)
-VDS (Volts)
Figure 8: Capacitance Characteristics
Ciss
0
80
160
240
320
400
0.0001 0.001 0.01 0.1 1 10
Power (W)
Pulse Width (s)
Figure 10: Single Pulse Power Rating Junction
-
to
-
Coss
C
rss
VDS=-15V
ID=-20A
TJ(Max)=175°C
TC=25°C
10
µ
s
0.0
0.1
1.0
10.0
100.0
1000.0
0.01 0.1 1 10 100
-ID(Amps)
-VDS (Volts)
Figure 9: Maximum Forward Biased
10
µ
s
10ms
1ms
DC
RDS(ON)
limited
TJ(Max)=175°C
TC=25°C
100
µ
s
40
Figure 10: Single Pulse Power Rating Junction
-
to
-
Case (Note F)
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1 10
Zθ
θ
θ
θJC Normalized Transient
Thermal Resistance
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)
Single Pulse
D=Ton/T
TJ,PK=TC+PDM.ZθJC.RθJC
Ton T
P
D
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
Figure 9: Maximum Forward Biased
Safe Operating Area (Note F)
RθJC=1.6°C/W
Rev.9.0: July 2013 www.aosmd.com Page 4 of 6
AOD403/AOI403
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
0
18
0
30
60
90
120
150
0 25 50 75 100 125 150 175
Power Dissipation (W)
TCASE (°C)
Figure 13: Power De-rating (Note F)
0
10
20
30
40
50
60
70
80
0 25 50 75 100 125 150 175
Current rating ID(A)
T
CASE
(
°
°°
°
C)
1
10
100
1000
10000
0.00001 0.001 0.1 10 1000
Power (W)
Pulse Width (s)
Figure 15: Single Pulse Power Rating Junction
-
to
-
TA=25°C
10.0
100.0
1000.0
1 10 100 1000
-IAR (A) Peak Avalanche Current
Time in avalanche, tA (ms)
Figure 12: Single Pulse Avalanche capability
(Note C)
TA=25°C
TA=150°C
TA=100°C
TA=125°C
18
40
0.001
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
Zθ
θ
θ
θJA Normalized Transient
Thermal Resistance
Pulse Width (s)
Figure 16: Normalized Maximum Transient Thermal Impedance (Note H)
Single Pulse
D=Ton/T
TJ,PK=TA+PDM.ZθJA.RθJA
T
on
T
P
D
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
T
CASE
(
°
°°
°
C)
Figure 14: Current De-rating (Note F)
Figure 15: Single Pulse Power Rating Junction
-
to
-
Ambient (Note H)
RθJA=50°C/W
Rev.9.0: July 2013 www.aosmd.com Page 5 of 6
AOD403/AOI403
VDC
Ig
Vds
DUT
VDC
Vgs
Vgs Qg
Qgs Qgd
Charge
Gate Charge Test Circuit & Waveform
-
+
-
+
-10V
Id
Vds
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
Vds L
2
E = 1/2 LI
AR
AR
VDC
DUT Vdd
Vgs
Vds
Vgs
RL
Rg
Resistive Switching Test Circuit & Waveforms
-
+
Vgs
Vds
t t
t
tt
t
90%
10%
r
on
d(off)
f
off
d(on)
Vdd
Vgs
Id
Vgs
Rg
DUT
VDC
Vgs
Id
Vgs
-
+
BV
DSS
I
AR
Ig
Vgs
-
+
VDC
DUT
L
Vgs
Isd
Diode Recovery Test Circuit & Waveforms
Vds -
Vds +
dI/dt
RM
rr
Vdd
Vdd
Q = - Id t
t
rr
-Isd
-Vds
F
-I
-I
Rev.9.0: July 2013
www.aosmd.com
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