Isolated, Synchronous Forward Controller
with Active Clamp and iCoupler
Data Sheet ADP1074
Rev. D Document Feedback
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FEATURES
Current mode controller for active clamp forward topology
Integrated 5 kV (wide body SOIC package) or 3.0 kV (LGA
package) rated dielectric isolation voltage with Analog
Devices, Inc., patented iCoupler technology
Wide voltage supply range
Primary VIN: up to 60 V
Secondary VDD2: up to 36 V
Integrated 1 A primary side MOSFET driver for power switch
and active clamp reset switch
Integrated 1 A secondary side MOSFET drivers for
synchronous rectification
Integrated error amplifier and <1% accurate reference voltage
Programmable slope compensation
Programmable frequency range: 50 kHz to 600 kHz typical
Frequency synchronization
Programmable maximum duty cycle limit
Programmable soft start
Smooth soft start from precharged load
Programmable dead time
Power saving light load mode using MODE pin
Protection features such as short circuit, output overvoltage,
and overtemperature protection
Cycle-by-cycle input overcurrent protection
Precision enable UVLO with hysteresis
PGOOD pin for system flagging
Tracking function from secondary side
Remote (secondary side) shutdown/reset function
Safety and regulatory approvals (pending)
UL recognition
5000 V rms for 1 minute per UL 1577 (for wide body
SOIC package)
3000 V rms for 1 minute per UL 1577 (for LGA package)
CSA component acceptance notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 849 V peak (for wide body SOIC package)
VIORM = 560 V peak (for LGA package)
CQC certification per GB4943.1-2011
Available in 24-lead SOIC_W package and 24-terminal LGA
package
AEC-Q100 Qualified for Automotive Applications
APPLICATIONS
Isolated dc-to-dc power conversion
Intermediate bus voltage generation
Telecom, industrial
Base station and antenna RF power
Small cell
PoE powered device
Enterprise switches/routers
Core/edge/metro/optical routing
Power modules
SIMPLIFIED BLOCK DIAGRAM
ACTIVE CLAMP
FORWARD
BIAS
WDG
12V
DC
/
8
A
INPU
T
SYNCHRONOUS
RECTIFIER
OPTIONAL
START-UP
CIRCUITRY
ADP1074
15627-001
Figure 1.
ADP1074 Data Sheet
Rev. D | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Simplified Block Diagram ............................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications .................................................................................... 4
Insulation and Safety Related Specifications ............................ 7
Regulatory Information ............................................................... 8
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 9
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 10
Absolute Maximum Ratings ......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 14
Theory of Operation ...................................................................... 16
Detailed Block Diagram ............................................................ 17
Primary Side Supply, Input Voltage, and LDO.......................... 18
Secondary Side Supply and LDO ............................................. 18
Precision Enable ......................................................................... 18
Soft Start Procedure ................................................................... 18
Output Voltage Sensing and Feedback ................................... 19
Loop Compensation and Steady State Operation ................. 19
Slope Compensation .................................................................. 20
Input/Output Current-Limit Protection .................................... 20
Temperature Sensing ................................................................. 21
Frequency Setting (RT Pin) ...................................................... 21
Maximum Duty Cycle ............................................................... 21
Frequency Synchronization ...................................................... 21
Synchronous Rectifier (SR) Drivers ........................................ 22
Output Overvoltage Protection (OVP) ................................... 22
Active Clamp (PGATE) ............................................................ 22
Leading Edge Blanking .............................................................. 22
Gate Delay and SR Dead Time ................................................. 22
Light Load Mode (LLM) and SR Phase In .............................. 22
External Start-Up Circuit .......................................................... 23
Soft Stop ....................................................................................... 23
Power Good ................................................................................ 23
OCP/Feedback Recovery ........................................................... 24
Output Voltage Tracking .......................................................... 24
Remote System Reset ................................................................. 24
OCP Counter .............................................................................. 26
Insulation Lifetime ..................................................................... 26
Layout Guidelines ...................................................................... 27
Typical Application Circuits ......................................................... 28
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
6/2020—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 31
4/2020—Rev. B to Rev. C
Moved General Description Section .............................................. 3
Added Table 1; Renumbered Sequentially .................................... 3
8/2018—Rev. A to Rev. B
Changes to Table 1 ........................................................................... 3
Changes to Input/Output Current-Limit Protection Section .... 19
8/2018—Rev. 0 to Rev. A
Added CC-24-6 Package .............................................. Throughout
Changes to Features Section ........................................................... 1
Changes to Table 1 ........................................................................... 3
Changes to Table 2 ........................................................................... 6
Added Table 4; Renumbered Sequentially .................................... 7
Changes to Table 3 ............................................................................ 7
Added DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics Section, Table 5, and Figure 2; Renumbered
Sequentially ........................................................................................ 8
Added DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics Section, Table 6, and Figure 3 .............................. 9
Added Table 10 ............................................................................... 10
Changes to Table 8 and Table 9 ................................................... 10
Added Figure 5 ............................................................................... 11
Changes to Input/Output Current Limit Protection Section .. 19
Added Figure 15 ............................................................................. 20
Updated Outline Dimensions ...................................................... 30
Changes to Ordering Guide .......................................................... 30
10/2017—Revision 0: Initial Version
Data Sheet ADP1074
Rev. D | Page 3 of 32
GENERAL DESCRIPTION
The ADP1074 is a current mode, fixed frequency, active clamp,
synchronous forward controller designed for isolated dc to dc
power supplies. Analog Devices proprietary iCouplers® are
integrated in the ADP1074 to eliminate the bulky signal trans-
formers and optocouplers that transmit signals over the isolation
boundary. Integrating the iCouplers reduces system design
complexity, cost, and component count and improves overall
system reliability. With the integrated isolators and metal-oxide
semiconductor field effect transistor (MOSFET) drivers on both
the primary and the secondary side, the ADP1074 offers a compact
system level design and yields a higher efficiency than a non-
synchronous forward converter at heavy loads.
The primary side pins provide functions for programming the
switching frequency, maximum duty cycle, external frequency
synchronization, and slope compensation.
The secondary side pins provide functions for differential output
voltage sensing, overvoltage, power good, tracking, and
programmable light load mode setting.
The feedback signal and timing of synchronous rectifier pulse-
width modulations (PWMs) are transmitted from primary to
secondary or from secondary to primary sides through the
iCouplers using a proprietary transmission scheme.
The ADP1074 also offers features such as input current
protection, undervoltage lockout (UVLO), precision enable
with adjustable hysteresis, overtemperature protection (OTP),
and power saving light load mode (LLM).
Table 1. Related Products1
Lead Free Finish Tape and Reel2
Part
Marking Package Description
Temperature
Range3
LT8672EMS#WPBF LT8672EMS#WTRPBF LTGYT 10-lead plastic MSOP −40°C to +125°C
LT8672IMS#WPBF LT8672IMS#WTRPBF LTGYT 10-lead plastic MSOP −40°C to +125°C
LT8672JMS#WPBF LT8672JMS#WTRPBF LTGYT 10-lead plastic MSOP −40°C to +150°C
LT8672HMS#WPBF LT8672HMS#WTRPBF LTGYT 10-lead plastic MSOP −40°C to +150°C
LT8672EDDBM#WTRMPBF LT8672EDDBM#WTRPBF LHJR 10-lead, 3 mm × 2 mm, plastic side wettable
DFN package
−40°C to +125°C
LT8672IDDBM#WTRMPBF LT8672IDDBM#WTRPBF LHJR 10-lead, 3 mm × 2 mm, plastic side wettable
DFN package
−40°C to +125°C
LT8672JDDBM#WTRMPBF LT8672JDDBM#WTRPBF LHJR 10-lead, 3 mm × 2 mm, plastic side wettable
DFN package
−40°C to +150°C
1 Versions of these devices are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are
designated with a W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact a local Analog Devices account
representative for specific product ordering information and to obtain the specific automotive reliability reports for these models.
2 Some packages are available in 500 unit reels through designated sales channels. These versions feature the #TRMPBF suffix.
3 Contact the factory for devices specified with wider operating temperature ranges. The temperature grade is identified by a label on the shipping container.
ADP1074 Data Sheet
Rev. D | Page 4 of 32
SPECIFICATIONS
VIN = 24 V, VDD2 = 12 V, TJ = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY (PRIMARY)
Supply Voltage VIN 4.7 µF capacitor from VIN to PGND1,
1 µF capacitor from VREG1 to PGND1
4.7 24 60 V
Quiescent Supply Current IVIN VIN > VIN UVLO, NGATE and PGATE
unloaded
At 100 kHz 5.3 mA
At 300 kHz 5.8 mA
At 600 kHz 6.8 mA
VIN > VIN UVLO, NGATE and PGATE
loaded with 2.2 nF and 410 pF,
respectively
At 100 kHz 7.5 mA
At 300 kHz 12 mA
At 600 kHz 19.5 mA
VIN Shutdown Current EN pin voltage (VEN) < 1.2 V, VREG1 = 0 V,
VIN = 60 V
55 A
(VIN + VREG1) Start-Up Current IVIN_STARTUP VEN < 1.2 V, VREG1 = 12 V, VIN = 12 V 160 A
VIN UVLO VIN rising 4.7 V
VIN falling 4.0 V
UVLO Hysteresis 0.19 V
Time from EN High to PGATE
Output Switching
V
EN > 1.2 V, 1 µF capacitor on VREG1 1 ms
Time from EN Low to SR1/SR2
Output Stops Switching
V
EN < 1.0 V, 1 µF capacitor on VREG1 1 s
SUPPLY (SECONDARY)
Supply Voltage VDD2 4.7 µF capacitor from VDD2 to PGND2,
1 µF capacitor from VREG2 to PGND2
4.5 12 36 V
Quiescent Supply Current IDD2 SR1 and SR2 unloaded
At 100 kHz 6.5 mA
At 300 kHz 6.7 mA
At 600 kHz 7 mA
I
DD2 SR1 and SR2 loaded with 2.2 nF
At 100 kHz 8.3 mA
At 300 kHz 12 mA
At 600 kHz 18 mA
VDD2 UVLO Threshold VDD2 rising 3.55 V
VDD2 falling 3.0 V
UVLO Hysteresis 0.145 V
Secondary UVLO Hiccup Time 200 ms
OSCILLATOR
Switching Frequency (fS) RT resistance (RRT) = 480 kΩ (±1%) 50 − 10% 50 50 + 10% kHz
R
RT = 240 kΩ (±1%) 100 − 10% 100 100 + 10% kHz
R
RT = 120 kΩ (±1%) 200 − 10% 200 200 + 10% kHz
R
RT = 80 kΩ (±1%) 300 − 10% 300 300 + 10% kHz
R
RT = 60 kΩ (±1%) 400 − 10% 400 400 + 10% kHz
R
RT = 40 kΩ (±1%) 600 − 10% 600 600 + 10% kHz
VREG1 PIN
VREG1 Voltage Clamp VREG1 current (IVREG1) = 3 mA, VEN < 1.2 V 13.5 14.3 15.2 V
VREG1 Clamp Series Resistance VREG1 forced current of 5 mA and 15 mA 16 Ω
Data Sheet ADP1074
Rev. D | Page 5 of 32
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
GATE DRIVERS (PRIMARY)
NGATE and PGATE High
Voltage
I
VREG1 = 20 mA, VIN > 9 V 7.8 8 8.2 V
Gate Short-Circuit Peak
Current1
8 V on VREG1 1.0 A
Rise Time 10% to 90%
NGATE CNGATE = 2.2 nF 18 ns
PGATE CPGATE = 410 pF 8 ns
Fall Time 90% to 10%
NGATE CNGATE = 2.2 nF 16 ns
PGATE CPGATE = 410 pF 7 ns
Source Resistance RON_SOURCE Source 100 mA
NGATE 4 Ω
PGATE 6.5 Ω
Sink Resistance RON_SINK Sink 100 mA
NGATE 3 Ω
PGATE 3.5 Ω
NGATE Maximum Duty Cycle DMAX Divider bottom resistor (RBOT) = 0 Ω 45 50 55 %
Divider top resistor (RTOP) = RBOT,
1% resistors
75 %
NGATE Minimum On Time Includes propagation delay and CS
comparator blanking time
170 ns
SRx DRIVERS (SECONDARY)
SR1 and SR2 High Voltage IVREG2 = 15 mA, VDD2 > 5.5 V 4.9 5 5.1 V
Gate Short-Circuit Peak
Current1
5 V on VREG2 1.0 A
SRx Time CSRx = 2.2 nF
Rise 10% to 90% 14 ns
Fall 90% to 10% 11 ns
Minimum On Includes blanking time 230 ns
SRx Resistance
Source RON_SR_SOURCE Source 100 mA 3.5 Ω
Sink RON_SR_SINK Sink 100 mA 2 Ω
DELAYS
Gate Delay (SR1 Rising to
NGATE Rising)
35 ns
Delay Between NGATE Falling
Edge and SR1 Falling Edge iCoupler
delay
21 ns
SR DEAD TIME (PGATE RISING
TO SR2 FALLING)
Resistor (±5%) at NGATE
Dead time resistor (RDT) = 10 kΩ 154 ns
R
DT = 22 kΩ 109 ns
R
DT = 47 kΩ 72 ns
R
DT is open 42 ns
SR1 and SR2 Dead Time Dead time between SR1 and SR2 25 ns
CURRENT-LIMIT SENSE (PRIMARY)
CS Limit Threshold VCS_LIM Over current sense limit threshold 120 mV
CS Leading Edge Blanking Time 150 ns
Current Source di/dt for Slope
Compensation
Switching period (tS) = 1/fS 20 A per tS
ADP1074 Data Sheet
Rev. D | Page 6 of 32
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Overcurrent Protection (OCP)
Comparator Delay
40 ns
Time in OCP Before Entering
Hiccup Mode
1.5 ms
OCP Hiccup Time See Input/Output Current-Limit Protection
section
40 ms
FB PIN AND ERROR AMPLIFIER
Feedback Accuracy Voltage VFB T
J = −40°C to +85°C 1.2 − 0.85% +1.2 1.2 + 0.85% V
T
J = −40°C to +125°C 1.2 − 1.25% +1.2 1.2 + 1.25% V
Temperature Coefficient 76 ppm/°C
FB Input Bias Current −100 +1 +100 nA
Transconductance gm 230 250 270 µA/V
Output Current Clamp
Minimum −57 µA
Maximum 43 µA
COMP Clamp Voltage
Minimum 20 A sinking current from COMP pin 0.7 V
Maximum 20 A sourcing current to COMP pin 2.52 V
Open-Loop Gain 80 dB
Output Shunt Resistance 5 GΩ
Gain Bandwidth Product 1 MHz
PRECISION ENABLE THRESHOLD
EN Threshold VEN EN rising 1.14 1.2 1.26 V
EN Hysteresis VEN < 1.2 V 4 µA
V
EN > 1.2 V 1 µA
EN Hysteresis Current 3 µA
MODE PIN
Light Load Mode Current
Source
Connect a resistor from MODE to AGND2 6 6.5 7 µA
Hysteresis 24 40 60 mV
TEMPERATURE
Thermal Shutdown 155 °C
Hysteresis −15 °C
SOFT START SS1 AND SS2 PINS
Primary Side SS1 Current
Source
During soft start only 9.1 µA
Secondary Side SS2 Current
Source
During soft start only, post handover 20 µA
SS2 Discharging Current During a fault condition or soft stop 30 µA
SYNC PIN
Synchronization Range 100 600 kHz
Input Pulse Width 100 ns
Number of Cycles Before
Synchronization
7 Cycles
Input Voltage
Low 0.4 V
High 3 V
Leakage Current 1 A
iCOUPLER DELAY
COMP Signal Delay Through
iCoupler
600 ns
Data Sheet ADP1074
Rev. D | Page 7 of 32
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FB, OVP, AND PGOOD
THRESHOLDS
Overvoltage (OV) threshold for PGOOD
to toggle for FB and OVP pin
1.3 1.36 1.42 V
FB Pin OV Hysteresis 36 mV
OVP Pin Hysteresis 36 mV
FB Pin UV Threshold Undervoltage (UV) threshold for PGOOD
to toggle
1.04 1.11 1.16 V
FB Pin UV Hysteresis 36 mV
OVP Comparator Delay
(Includes iCoupler Delay)
320 ns
Time from Fault Condition to
PGOOD Toggling
OVP pin fault to PGOOD toggling 90 ns
FB pin OV/UV to PGOOD toggling 5 s
OVP Pin Leakage Current 1 A
PGOOD Pin Leakage Current 1 A
OVP Hiccup Time in OVP before entering OVP hiccup
mode
200 s
Hiccup time triggered by OVP event 200 ms
1 Short-circuit duration less than 1 s. Average power must conform to the limit shown in the Absolute Maximum Ratings section.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
WIDE BODY SOIC
iCoupler
Rated Dielectric Insulation
Voltage
1 minute duration 5 kV
Minimum External Air Gap
(Clearance)
Measured from input terminals to output terminals,
shortest distance through air
7.6 mm
Minimum External Air Gap
(Creepage)
Measured from input terminals to output terminals,
shortest distance path along body
7.6 mm
Minimum Internal Gap (Internal
Clearance)
Insulation distance through insulation 0.030 mm
Tracking Resistance
(Comparative Tracking Index)
CTI >400 V
Isolation Group Material Group II (DIN VDE 0110, 1/89, Table 1)
LAND GRID ARRAY (LGA)
iCoupler
Rated Dielectric Insulation
Voltage
1 minute duration 2.5 kV
Minimum External Air Gap
(Clearance)
Measured from input terminals to output terminals,
shortest distance through air
4 mm
Minimum External Air Gap
(Creepage)
Measured from input terminals to output terminals,
shortest distance path along body
4 mm
Minimum Internal Gap (Internal
Clearance)
Insulation distance through insulation 0.030 mm
Tracking Resistance
(Comparative Tracking Index)
CTI >400 V
Isolation Group Material Group I (DIN VDE 0110, 1/89, Table 1)
ADP1074 Data Sheet
Rev. D | Page 8 of 32
REGULATORY INFORMATION
See Table 4, Table 5, and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross
isolation waveforms and insulation levels.
Table 4. Regulatory Information for Wide Body SOIC Package
UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending)
Recognized Under UL 1577
Component Recognition
Program1
Approved under CSA Component
Acceptance Notice 5A
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Certified by
CQC11-471543-2012,
GB4943.1-2011:
Single Protection, 5000 V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and IEC 60950-1,
second edition, +A1+A2 and IEC62368:
Reinforced insulation,
maximum working
insulation voltage (VIORM) =
849 V peak,
highest allowable
overvoltage (VIOTM) =
8000 V peak
Basic insulation at 780 V rms
(1103 V peak)
Basic insulation at 780 V rms
(1103 V peak)
Reinforced insulation at 389 V rms
(552 V peak), tropical climate,
altitude ≤5000 meters
Reinforced insulation at 390 V rms
(552 V peak)
IEC 60601-1 Edition 3.1:
Basic insulation (1 means of patient
protection (1 MOPP)), 490 V rms
(686 V peak)
Reinforced insulation (2 MOPP),
238 V rms (325 V peak)
CSA 61010-1-12 and IEC 61010-1 third
edition:
Basic insulation at 300 V rms mains, 780 V
secondary (1103 V peak)
File (pending) File (pending) File (pending) File (pending)
1 In accordance with UL 1577, each product is proof tested by applying an insulation test voltage ≥6000 V rms for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each product is proof tested by applying an insulation test voltage ≥1592 V peak for 1 sec (partial discharge detection limit = 5 pC).
Note that the asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
Table 5. Regulatory Information for LGA Package
UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending)
Recognized Under UL 1577
Component Recognition
Program1
Approved under CSA Component
Acceptance Notice 5A
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
Certified by
CQC11-471543-2012,
GB4943.1-2011:
Single Protection, 3000V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and IEC 60950-1,
second edition, +A1+A2 and IEC62368:
Reinforced insulation,
VIORM = 565 V peak,
VIOTM = 4242 V peak
impulse voltage =
4242 V peak
Basic insulation at 400 V rms
(565 V peak)
Basic insulation at 400 V rms (565 V peak) Reinforced insulation at 200 V rms
(283 V peak), tropical climate,
altitude ≤5000 meters
Reinforced insulation at 200 V rms
(283 V peak)
IEC 60601-1 Edition 3.1:
Basic insulation (1 means of patient
protection (1 MOPP)), 250 V rms
(354 V peak)
CSA 61010-1-12 and IEC 61010-1 third
edition:
Basic insulation at 300 V rms mains, 400 V
secondary (565 V peak)
File (pending) File (pending) File (pending) File (pending)
1 In accordance with UL 1577, each product is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec.
2 In accordance with DIN V VDE V 0884-10, each product is proof tested by applying an insulation test voltage ≥1059 V peak for 1 sec (partial discharge detection limit = 5 pC).
Note that the asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
Data Sheet ADP1074
Rev. D | Page 9 of 32
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation within the safety limit data only. Maintenance of the safety data is ensured by protective
circuits. Note that the asterisk (*) marked on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 6. DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics for Wide Body SOIC Package
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 565 VPEAK
Input-to-Output Test Voltage, Method B1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VPR 1060 VPEAK
Input-to-Output Test Voltage, Method A VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR
After Environmental Tests Subgroup 1 905 VPEAK
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 679 VPEAK
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VIOTM 7071 VPEAK
Surge Isolation Voltage Reinforced VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 6000 VPEAK
Safety-Limiting Values Maximum value allowed in the event of a failure;
see Figure 2
Case Temperature TS 150 °C
Side 1 Current IS1 160 mA
Side 2 Current IS2 170 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω
15627-026
1.2
1.0
0.8
0.6
0.4
0.2
0
0 50 100 150 200
SAFE OPERATING P
VDDA
, P
VREG
POWER (W)
AMBIENT TEMPERATURE (°C)
Figure 2. Thermal Derative Curve, Dependence of Safety Limiting Values with Ambient Temperature per DINV VDE V 0884-10
ADP1074 Data Sheet
Rev. D | Page 10 of 32
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation within the safety limit data only. Maintenance of the safety data is ensured by protective
circuits. Note that the asterisk (*) marked on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 7. DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics for LGA Package
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 565 VPEAK
Input-to-Output Test Voltage, Method B1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VPR 1060 VPEAK
Input-to-Output Test Voltage, Method A VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR
After Environmental Tests Subgroup 1 905 VPEAK
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 679 VPEAK
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 4242 VPEAK
Surge Isolation Voltage Reinforced VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 6000 VPEAK
Safety-Limiting Values Maximum value allowed in the event of a failure;
see Figure 3
Case Temperature TS 150 °C
Side 1 Current IS1 160 mA
Side 2 Current IS2 170 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω
1.2
1.0
0.8
0.6
0.4
0.2
0
0 50 100 150 200
SAFE OPERATING P
VDDA
, P
VREG
POWER (W)
AMBIENT TEMPERATURE (°C)
15627-025
Figure 3. Thermal Derative Curve, Dependence of Safety Limiting Values with Ambient Temperature per DINV VDE V 0884-10
Data Sheet ADP1074
Rev. D | Page 11 of 32
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter Rating
VIN, EN −0.3 V to +66 V
VDD2 −0.3 V to +42 V
VREG1 −0.3 V to +16 V
VREG2 −0.3 V to +6 V
NGATE, PGATE −0.3 V to +16 V
RT, CS, SYNC, SS1, SS2, PGOOD, FB, COMP,
OVP, MODE, DMAX, SR1, SR2
−0.3 V to +6 V
AGND1, PGND1, AGND2, PGND2 ±0.3 V
Common-Mode Transients1 ±25 kV/µs
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec) 240°C
RoHS Compliant Assemblies
(20 sec to 40 sec)
260°C
Electrostatic Discharge (ESD)
Charged Device Model (CDM) ±1250 V
Human Body Model (HBM) ±2 kV
1 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum rating can cause latch-up
or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 9. Thermal Resistance1
Package Type θJA θ
JC Unit
RW-24 (Wide Body SOIC) 65.4 43.8 °C/W
CC-24-6 (LGA) 62.1 43 °C/W
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board. See JEDEC JESD-51.
Table 10. Maximum Continuous Working Voltage, Wide
Body SOIC1
Waveform
Maximum
Voltage (VPEAK) Constraint
AC Voltage
Bipolar 565 50-year minimum lifetime
Unipolar 1131 50-year minimum lifetime
DC Voltage 1131 50-year minimum lifetime
1 Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
Table 11. Maximum Continuous Working Voltage, LGA1
Waveform
Maximum
Voltage (VPEAK) Constraint
AC Voltage
Bipolar 565 50-year minimum lifetime
Unipolar 909 Limited by creepage
DC Voltage 565 Limited by creepage
1 Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
ESD CAUTION
ADP1074 Data Sheet
Rev. D | Page 12 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NGATE
1
PGATE
2
PGND1
3
AGND1
4
SR1
24
SR2
23
PGND2
22
AGND2
21
VREG1
5
VREG2
20
VIN
6
VDD2
19
EN
7
OVP
18
CS
8
FB
17
RT
9
COMP
16
SYNC
10
SS2
15
SS1
11
PGOOD
14
DMAX
12
MODE
13
15627-002
ADP1074
(Not to Scale)
TOP VIEW
Figure 4. 24-Lead SOIC_W Pin Configuration
15627-027
PGND2
SYNC
AGND1
COMP
4
VREG1 5
VIN 6
EN 7
CS 8
RT 9
SS1
DMAX
MODE
13
PGOOD
14
SS2
15
16
FB
17
OVP
18
VDD2
19
VREG2
20
A
GND2
21
22
SR2
23
SR1
24
NGATE
1
PGATE
2
PGND1
3
TOP VIEW
(TERMINAL SIDE DOWN)
Not to Scale
ADP1074
10 11 12
AGND1 AGND2
Figure 5. 24-Terminal LGA Pin Configuration
Table 12. Pin Function Descriptions
Pin No. Mnemonic Description
1 NGATE
Driver Output for the Main Power MOSFET on the Primary Side. Multiple function pin. Connect a resistor from
NGATE to PGND1 to set up the predetermined dead time between PGATE and SR2.
2 PGATE Driver for the Active Clamp MOSFET of the Forward Topology. This pin is referenced to PGND1.
3 PGND1 Power Ground on the Primary Side. Star connect this pin to AGND1.
4 AGND1
Analog Ground on the Primary Side. Star connect this pin to PGND1. Use this pin to differentially sense the
primary current sensed with the sense resistor between the CS and AGND1 pins.
5 VREG1
8 V Output for the MOSFET Drivers. Connect 1 F or greater at this pin. Do not put an external load on this pin.
Reference this pin to PGND1.
6 VIN
Input Voltage. Connect a 4.7 µF capacitor to this pin. The size of this capacitor can be reduced if the input
voltage to this pin is guaranteed stable. Reference this pin to PGND1.
7 EN Precision Enable Input. The controller is enabled when the voltage at the EN pin is above the EN threshold
voltage. Soft stop is enabled when EN drops below the EN threshold voltage. This pin also has a programmable
EN hysteresis. Reference this pin to AGND1.
8 CS Input Current Sensing. This pin senses the input pulse width modulated current. Place a current sense resistor
between the source terminal of the power MOSFET and PGND1. This current sense resistor sets up the input
current limit. This pin is also used for an external slope compensator. Connect a resistor from CS to the current
sense resistor to generate a voltage ramp for the slope compensation. Reference this pin to AGND1. Connect a
33 pF to 100 pF capacitor to this pin to act as a resistor capacitor (RC) filter along with the slope compensation
resistor in noisy environments.
9 RT Switching Period Resistor. Connect two resistors in series that sum up to the appropriate resistor from RT to
AGND1 to set the switching frequency. See the DMAX pin for more information. Also see the Frequency Setting
(RT Pin) section and the Maximum Duty Cycle section for the relevant equations.
10 SYNC
Frequency Synchronization. Connect an external clock to the SYNC pin to synchronize the internal oscillator to
this external clock frequency. Connect SYNC to AGND1 if this feature is not used. It is recommended that the
SYNC frequency be within 10% of the frequency set by the RT pin.
11 SS1 Soft Start 1. Connect a capacitor at this pin to set up the open-loop soft start time. Reference this pin to AGND1.
12 DMAX
Maximum Duty Cycle Control. Connect DMAX to the center tap of the resistive divider at the RT pin to set up the
maximum duty cycle. See the Frequency Setting (RT Pin) section and the Maximum Duty Cycle section for the
relevant equations.
13 MODE
Light Load Mode Setting. Connect MODE to AGND2 to disable discontinuous conduction mode (DCM)
operation, or to a high logic (2.5 V or higher, such as the VREG2 pin) to force LLM operation, or to a resistor to set
up a fixed LLM threshold voltage.
14 PGOOD Power Good Pin. Open-drain output. Connect a pull-up resistor from PGOOD to VREG2.
15 SS2 Soft Start on the Secondary Side. Connect a capacitor from SS2 to AGND2 to set up the soft start time on the
secondary side.
Data Sheet ADP1074
Rev. D | Page 13 of 32
Pin No. Mnemonic Description
16 COMP
Compensation Node on the Secondary Side. This pin is the output of the transconductance (gm) amplifier. This
pin is referenced to AGND2.
17 FB Feedback Node on the Secondary Side. Set up the resistive divider from the output voltage such that the
nominal voltage, when the power supply is in regulation, is 1.2 V. Reference this pin to AGND2.
18 OVP
Output Overvoltage Protection (OVP). The OVP threshold is set at 1.36 V. Connect a resistive divider from OVP to
the output and AGND2.
19 VDD2
Input Supply on the Secondary Side. Connect VDD2 to the output voltage of the power supply for a self driven
configuration. Connect a 4.7 µF capacitor from VDD2 to AGND2. The size of this capacitor can be reduced if the
input voltage to VDD2 is guaranteed stable.
20 VREG2
5 V Regulated Low Dropout (LDO) Output for Internal Bias and Powering of the Drivers of the Synchronous
Rectifiers. Do not use VREG2 as a reference or load. Connect a 1 µF capacitor from VREG2 to AGND2.
21 AGND2
Analog Ground on the Secondary Side. Star connect AGND2 to PGND2. Use AGND2 for differential sensing of the
output voltage between the FB pin and AGND2.
22 PGND2 Power Ground on the Secondary Side. Star connect PGND2 to AGND2.
23 SR2 MOSFET Driver Output 2 for the Synchronous Rectifier MOSFET. This PWM controls the freewheeling switch.
24 SR1 MOSFET Driver Output 1 for the Synchronous Rectifier MOSFET. This PWM is in phase with NGATE.
ADP1074 Data Sheet
Rev. D | Page 14 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
–25 –10 5 20 35 50 65 80 95 110 125
EN PIN RISING THRESHOLD (V)
–40
TEMPERATURE (°C)
MINIMUM
MEAN
MAXIMUM
15627-003
Figure 6. EN Pin Rising Threshold vs. Temperature
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
–25 –10 5 20 35 50 65 80 95 110 125
EN PIN FALLING THRESHOLD (V)
–40
TEMPERATURE (°C)
15627-004
MINIMUM
MEAN
MAXIMUM
Figure 7. EN Pin Falling Threshold vs. Temperature
1.185
1.190
1.195
1.200
1.205
1.210
–25 –10 5 20 35 50 65 80 95 110 125
FB PIN REFERENCE THRESHOLD (V)
–40
TEMPERATURE (°C)
15627-005
MINIMUM
MEAN
MAXIMUM
Figure 8. FB Pin Reference Threshold vs. Temperature
–25 –10 5 20 35 50 65 80 95 110 125
MODE PIN CURRENT (µA)
–40
TEMPERATURE (°C)
15627-006
6.0
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
MINIMUM
MEAN
MAXIMUM
Figure 9. MODE Pin Current vs. Temperature
Data Sheet ADP1074
Rev. D | Page 15 of 32
–25 –10 5 20 35 50 65 80 95 110 125
SR DEADTIME (ns)
SR1 FALLING TO SR2 RISING
–40
TEMPERATURE (°C)
15627-007
18
19
20
21
22
23
24
MINIMUM
MEAN
MAXIMUM
Figure 10. SR Dead Time (SR1 Falling to SR2 Rising) vs. Temperature
–25 –10 5 20 35 50 65 80 95 110 125
SR DEADTIME (ns)
SR2 FALLING TO SR1 RISING
–40
TEMPERATURE (°C)
15627-008
22
23
24
25
26
28
29
27
MINIMUM
MEAN
MAXIMUM
Figure 11. SR Dead Time (SR2 Falling to SR1 Rising) vs. Temperature
–25 –10 5 20 35 50 65 80 95 110 125
NGATE DELAY (ns)
SR1 RISING TO NGATE RISING
–40
TEMPERATURE (°C)
15627-009
25
27
29
31
33
35
37
39
41
43
MINIMUM
MEAN
MAXIMUM
Figure 12. NGATE Delay (SR1 Rising to NGATE Rising) vs. Temperature
ADP1074 Data Sheet
Rev. D | Page 16 of 32
THEORY OF OPERATION
The ADP1074 is a current mode, fixed frequency, active clamp,
synchronous forward controller designed for isolated dc to dc
power supplies. Analog Devices proprietary iCouplers are
integrated in the ADP1074 to eliminate the bulky signal trans-
formers and optocouplers that transmit signals over the isolation
boundary. Integrating the iCouplers reduces system design
complexity, cost, and component count and improves overall
system reliability. With the integrated isolators and MOSFET
drivers on both the primary and the secondary side, the ADP1074
offers a compact system level design and yields a higher efficiency
than a nonsynchronous forward converter at heavy loads.
Traditionally in a forward or flyback converter, a discrete opto-
coupler is used in the feedback path to transmit the signal from
the secondary to the primary side, and an external transformer
is used for transmitting the PWM signal from the primary to
the secondary side for synchronous rectification. However, the
current transfer ratio (CTR) of the optocouplers degrades over
time and over temperature and so the optocoupler must be
replaced every five to ten years, depending on the manufacturing
quality and optocoupler grade that determines the initial CTR. The
ADP1074 eliminates the use of optocouplers and signal
transformers, thus reducing system cost, PCB area, and
complexity while improving system reliability, without the
issue of CTR degradation of the optocouplers.
The ADP1074 controller offers a complete solution for an isolated
dc to dc power supply by integrating the 5 kV isolators and the
primary and secondary control circuitries in one package.
The PWM controls are performed on the primary side by
sensing the input peak current cycle by cycle with a sense resistor
at the source of the main switching MOSFET. The output of the
converter is sensed by the secondary circuitry, which sends the
feedback and PWM signals to the primary side via the 5 kV
integrated isolators for a complete control loop solution.
The primary circuitry in the ADP1074 includes an 8 V LDO,
input current sensing, bias circuit, and MOSFET drivers
including an active clamp reset driver, slope compensation,
external frequency synchronization, PWM generator, and a
programmable maximum duty cycle setting. The primary side
also has pins for differential sensing of the current sense signal.
The secondary circuitry includes the feedback compensation, a
5 V LDO regulator, an internal reference, two MOSFET drivers for
synchronous rectification, and a dedicated pin for overvoltage
protection. Additionally, the secondary side features differential
output voltage sensing and power good pins, and a program-
mable light load mode setting.
The integrated iCouplers carry out the communications
between the primary and secondary sides by transmitting the
feedback signal and the PWMs over the isolation barrier.
The feedback signal and timing of synchronous rectifier PWMs
are transmitted between the primary and the secondary sides,
or between the secondary and primary sides, through the
iCouplers using a proprietary transmission scheme.
The ADP1074 also offers features such as input current protection,
UVLO, precision enable with adjustable hysteresis, OTP, LLM,
and tracking.
Data Sheet ADP1074
Rev. D | Page 17 of 32
DETAILED BLOCK DIAGRAM
Figure 13 shows a detailed block diagram of the ADP1074.
VREG1
NGATE
VIN
CS
8V LDO
DRV
OSCILLATOR
RT
QS
R
LOGIC
AGND2
5V LDO
V
DD2
PGOOD
THERMAL
LIMIT
1.10V
LOGIC
OVP
VREF2
VREG2
VREF 1.2V
VREG
SR1
SR2
PWM
LOGIC
CONTROL
PGATE
DRV
LOGIC
AND
DEAD
TIME
CTRL
PGND2
PGND1
COMP
A
GND1
14V
DRV
VREG2
VREG2
VREG2
DRV
MODE
DMAX
SS1
OV
LLM
THRESHOLD
COMP
DC
1.36V
COMP
FB
gm
AMPLIFIER
1.2VREF
VREG2
CLAMP MAXIMUM
CLAMP MINIMUM
SS2
OCP RECOVERY
SLOPE RAMP
SYNC
fOSC
EN
1.2V
4µA1µA
Tx
VREG
OV
BIAS
OC THRESHOLD
DETECT SECONDARY
SIDE UVLO AND
HANDOVER CONTROL
FROM PRIMARY
HANDOVER TO
SECONDARY 1.36V
Rx
Tx Rx
OV DETECT
6µA
15627-010
Figure 13. Detailed Block Diagram
ADP1074 Data Sheet
Rev. D | Page 18 of 32
PRIMARY SIDE SUPPLY, INPUT VOLTAGE, AND LDO
Two pins on the primary side are supply pins: VIN and
VREG1. A high voltage LDO regulator connected to VIN has a
regulated output of 8 V at the VREG1 pin. This LDO regulator
provides power to the internal bias circuitry, primary side
iCouplers and housekeeping circuits, and the primary
MOSFET drivers at the NGATE and PGATE pins.
To reduce power consumption in the LDO for input voltages
higher than approximately 30 V, an auxiliary winding on the
transformer of the active clamp forward topology can be used
to power VREG1. This auxiliary supply voltage must be higher
than the regulated output at VREG1 so that the LDO shuts off
during normal operation. The recommended auxiliary voltage
is ≥8.5 V and ≤13 V because an internal 14 V Zener diode is
connected at VREG1.
For a high input voltage application to avoid losses in the LDO,
connect the VIN and VREG1 pins together and apply an auxiliary
voltage of 8 V to 10 V, which exceeds the VIN pin UVLO of
typically 4.5 V. Take care that this voltage does not exceed the
internal Zener clamp voltage of 14 V (typical). The typical value
is 10 V.
SECONDARY SIDE SUPPLY AND LDO
Two pins on the secondary side are supply pins: VDD2 and
VREG2.
The secondary side is typically powered by the output rail of the
converter by connecting it to the VDD2 pin. The UVLO for the
secondary side is typically 3.5 V, at which the secondary side
starts up. For output voltages less than the secondary UVLO
voltage, a third winding is required to generate an auxiliary voltage
to power the secondary circuitry. The internal 5 V LDO regulator
at the VREG2 pin powers the MOSFET drivers, secondary side
iCouplers, and housekeeping circuits. When VDD2 is less than
5 V, the LDO regulator operates in dropout mode.
For output voltages higher than 24 V, connecting the output
voltage directly to VDD2 can result in significant power
dissipation in the LDO. For instance, at 24 V and with the total
driver current at 10 mA, the power dissipated in the LDO is
0.19 W (10 mA × 19 V). It is recommended to power VDD2
with an auxiliary voltage in the 8 V to 12 V range.
PRECISION ENABLE
The enable threshold at the EN pin is precision voltage referenced
at 1.2 V. Assuming VIN is above the UVLO voltage (typically
4.5 V), the ADP1074 is enabled when the voltage at EN rises above
1.2 V. The crossing of the voltage, such that VEN > 1.2 V,
enables the internal 8 V LDO regulator on the VREG1 pin, and,
after the internal biasing is finished, a soft start procedure is
initiated.
Connect a resistive divider between EN and VIN to set up the
input start-up voltage (see Figure 14.) An internal current source
at EN allows the user to program the UVLO start-up voltage with
a desirable hysteresis. To calculate the start-up voltage with
hysteresis, use the superposition theorem or nodal analysis to
obtain the EN pin voltage, as follows:
(|| )
EN IN EN
R2
VV I R1R2RH
R1 R2
where:
VEN is the EN pin voltage.
IEN is the current source at the EN pin (1 A for turn on and
4 A for turn off).
The user can adjust the R1, R2, and RH resistors such that
VEN ≥ 1.2 V and obtain the desired hysteresis.
An internal 1 µA pull-down current is always on, and the 3 µA
current is active only when the VEN is below the EN threshold
and becomes inactive when VEN is above the EN threshold.
In general, a higher input voltage requires a larger hysteresis. It
is recommended to keep a capacitor on the EN pin to AGND1
to provide a low impedance path that prevents any noise, which
toggles the EN pin when the input voltage hovers at the threshold.
8V LDO
ADP1074
1µA 3µA
LOGIC
VREF
1.2V
R1
R2
RH
VIN
EN
HYSTERESIS
GENERATOR
15627-011
Figure 14. Precision EN with Adjustable Hysteresis
When the EN pin is less than the EN threshold, the system
enables the soft stop procedure. SR1 and SR2 take up to a
maximum of two switching periods to terminate. See the Soft
Start Procedure section for more details.
SOFT START PROCEDURE
The following procedure assumes that the VDD2 pin is powered
directly from the output voltage of the power supply.
To ensure a smooth output voltage ramp during startup, the
soft start sequence is controlled by two soft start control circuits,
one in the primary (for open-loop soft start, using the SS1 pin)
and the other in the secondary (for closed-loop soft start, using
the SS2 pin). Proper handshaking between the primary side and
the secondary side is needed prior to the secondary side taking
control.
The open-loop soft start time is determined by the capacitor on
the SS1 pin. This pin sources a 9.1 µA constant current that
builds up a voltage on the SS1 pin. The voltage on the SS1 pin is
proportional to the peak primary current limit where 0 V and
1.5 V correspond to a peak current of 0 A and 120 mV/RSENSE,
respectively. This rate is the open-loop soft start. During this
time, the ADP1074 starts firing the PWM pulses, and the
output voltage continues to build up slowly if the average
inductor current limit exceeds the load current. Because the
ADP1074 is a current mode controller, the output capacitor
Data Sheet ADP1074
Rev. D | Page 19 of 32
starts charging only when the primary current limit exceeds the
load current requirement.
The rate at which the SS1 pin voltage rises to the maximum
current limit is given by
dt = CSS1 × 1.5/(9.1 A)
The handshaking process is as follows.
When VDD2 reaches the UVLO of approximately 3.5 V, the
internal circuitry on the secondary side is activated and the
ADP1074 initiates the following process:
1. The ADP1074 makes the voltage on the SS2 pin equal to
the value on the FB pin, with an SS2 pin current, at ten
times the nominal current source of 20 µA on the SS2 pin.
2. Simultaneously, the current limit on the primary (which is
the voltage on SS1) is transferred over to the secondary
side, and the voltage on the COMP pin is made equal to
the instantaneous SS1 voltage ± 100 mV. There is a
timeout for this process, which is 1.5 ms after the VDD2
UVLO threshold is crossed.
When this process is satisfied, the transmission of the COMP
signal occurs from the secondary to the primary side. The
ADP1074 transmits the COMP signal by continuously sampling
the analog signal at the COMP pin. The sampled value is then
transmitted using a proprietary scheme to the primary side where
the instantaneous value of the CS pin is compared to the COMP
level to determine the falling edge of the NGATE pulse. The
COMP signal is, therefore, a representation of the primary
current limit.
After COMP transmission begins, the primary side receives the
signal and control is completely handed over to the secondary
side when either the received level of COMP on the primary side
is within ±100 mV, or up to 128 switching periods (typically 8)
have passed, starting from the first pulse being transmitted to
the primary side.
Then, the control is handed over to the secondary side and the
closed-loop soft start begins, where the SS2 capacitor is charged
at a nominal rate of 20 µA. The output voltage then rises to the
regulation voltage based on the SS2 pin voltage. The voltage on
the SS2 pin continues to rise to 1.2 V, that is, the steady state
voltage on the FB pin. At this stage, the power supply is in
regulation, and the output voltage is at its target value.
At the end of the soft start process, the voltage on the SS2 pin
continues to rise to approximately 1.4 V. The instant that the
handover takes place, SS1 is discharged to 0 V. In steady state,
the FB pin (that is, the reference voltage) is 1.2 V.
The SR1 and SR2 synchronous drivers begin to pulse after
VDD2 crosses the UVLO threshold.
If the voltage at the VDD2 pin is greater than the UVLO voltage,
such as a soft start from the precharged output, or if the VDD2 pin
is powered by an external supply, the secondary side assumes
control from the moment the EN pin is enabled, and only SS2 is
used for the soft start procedure.
When initiating a soft start from the precharged output, the SS2
pin tracks the FB pin and then initiates a soft start. This process
eliminates any glitches in the output voltage.
When soft starting into a precharged output, the SRx gates are
prevented from turning on until the SS2 voltage has reached
the precharged voltage at the FB pin. This soft start scheme
prevents the output from being discharged, and it prevents reverse
current.
Under abnormal situations, such as a shorted load or a
transient condition on the load during the soft start process, FB
may not be able to track SS2 accurately. If this occurs before the
VDD2 UVLO threshold is crossed, SS1 is in control. If it occurs
after the VDD2 UVLO threshold is crossed, SS2 tracks the FB
pin and then continues with the soft start process until the
regulation voltage is reached. In all conditions, control is
handed over to the secondary if FB ≥ 1.2 V.
When the secondary VDD2 is directly powered by the output
of the converter, the minimum output voltage required is
higher than the secondary UVLO voltage. For output voltages
less than the secondary UVLO voltage, a third winding is needed
to generate an auxiliary voltage to power the secondary side
circuitry. Alternately, in most cases, a diode resistor capacitor
combination from the switch node can provide the voltage to
VDD2.
OUTPUT VOLTAGE SENSING AND FEEDBACK
The output voltage of the converter is set by a resistive divider
to the FB pin. The resistive divider must be set in a manner
such that the voltage at the FB pin is 1.2 V in steady state. The
output voltage must be differentially sensed using the FB pin
and the AGND2 pin.
LOOP COMPENSATION AND STEADY STATE
OPERATION
The FB pin feeds into the negative terminal of a transconductance
amplifier (or gm amplifier) with a gain of approximately 250 A/V.
The positive input terminal of the gm amplifier is connected to SS2,
which provides the reference setpoint voltage. The output of
the gm amplifier is connected to the COMP pin. The voltage on
the COMP pin is representative of the current peak limit
required to sustain regulation. This pin is continuously
sampled, and the signal is transmitted to the primary side,
where it is compared to the sensed primary current using a
comparator. When the comparator trips, it causes NGATE to
terminate.
Typically, an RC network in series is connected between the
COMP pin and AGND2 for compensation. A high frequency pole
in the form of a capacitor can also be added in parallel to the RC
network.
The output of the gm amplifier is clamped to a minimum and
maximum current of approximately −57 A and +43 A,
respectively.
ADP1074 Data Sheet
Rev. D | Page 20 of 32
The COMP node is clamped to a lower and higher level of
approximately 0.7 V and 2.52 V, respectively. This is
representative of the CS range from 0 mV to 120 mV.
SLOPE COMPENSATION
For a peak current mode controller with duty cycle higher than
50%, slope compensation is necessary for a stable operation. To
set up an external compensation in the ADP1074, connect the
external RRAMP resistor (see Figure 25) between CS and the current
sense resistor, RSENSE, to set up the slope voltage ramp for the
control signal. It is important to sense the signal differentially.
See the Layout Guidelines section for more details.
An internal ramp current starts from 0 µA at the minimum duty
cycle (that is, the beginning of the switching period) and increases
linearly toward a maximum of 20 µA at the end of the switching
period. The slope of the voltage ramp is the ramp current times
RRAMP. RRAMP is sized using the following equation:
20 A
OUT SENSE
RAMP S
VN2R
Rk t
LN1
where:
k = 0.5 for nominal cases and k = 1 for deadbeat control.
VOUT is the desired output voltage.
L is the output inductor.
N1 and N2 are the primary and secondary turns of the
transformer.
tS is the switching period.
INPUT/OUTPUT CURRENT-LIMIT PROTECTION
There is no direct current-limit sensing circuit on the secondary;
the output current limit is indirectly limited by the cycle-by-cycle
primary side current limit of 120 mV on the CS pin.
The input peak current limit is set by connecting a sense
resistor, RSENSE, from the source of the main MOSFET to
PGND1 (see Figure 25), and the sensed voltage appears at the
CS pin. To generate the slope-comp ramp, insert the slope
compensation resistor, RRAMP, between CS and RSENSE.
The CS current limit, VCSLIM, is internally set to 120 mV. Calculate
the RSENSE value by
20 A
CSLIM RAMP
SENSE
PKPRI
VR
RI
where:
VCSLIM is the CS current limit.
IPKPRI is the primary peak current.
When the sensed input peak current is above the CS limit
threshold, the controller operates in the cycle-by-cycle constant
current-limit mode for 1.5 ms. Then the controller immediately
shuts down the primary and secondary drivers. The controller
then goes into hiccup mode for the next 40 ms and restarts the
soft start sequence after this timeout period.
The slope ramp can affect the accuracy of the current-limit
threshold because the voltage drop across RRAMP contributes to
the inaccuracy of the peak current limit. For instance, if the
added slope ramp voltage is 20% of the current-limit threshold,
the actual input peak current limit can be off by as much as
20% depending on where the peak current-limit threshold is
tripped during the on cycle. In the event of an output short
circuit, the controller treats this condition as an overcurrent
event and enters the 40 ms hiccup mode.
Under certain conditions, the ADP1074 exits OCP hiccup
mode. In these conditions, the COMP pin is at the maximum
clamp level, but the device does not enter hiccup mode.
However, it is guaranteed that the PWMs are terminated
whenever the CS maximum threshold is reached. The condition
under which the ADP1074 skips entering hiccup mode is when
VDD2 is powered through an auxiliary winding and an output
short circuit occurs that results in the FB pin having a voltage
that is <300 mV. This event is more prominent at high
temperatures (>85°C), and can be exacerbated at higher
temperatures.
The root cause of the device exiting hiccup mode is due to the
effect that the OCP hiccup mode feature has on the SS2 pin.
During OCP recovery, the SS2 pin tracks the FB pin and attempts
a soft start from the precharge sequence. During the time when
SS2 tracks the FB pin, the SS2 pin voltage can be less than the
FB pin for a short interval, which causes the COMP pin (output
of the gm amplifier) to momentarily dip below the maximum
COMP pin clamp level. This event means that the current limit
required for the next few switching periods is less than the maxi-
mum threshold and puts the device out of hiccup mode because
the ADP1074 fails to register 1.25 ms worth of consecutive
overcurrent cycles.
The following scenarios guarantee OCP hiccup mode based on
the configuration of the VDD2 power supply:
1. When VDD2 is powered directly from the output voltage,
if a short circuit occurs on the output terminals of the load
after steady state regulation is achieved, the voltage of the
VDD2 pin is less than the UVLO, and the device enters
hiccup mode for 200 ms, similar to the hiccup time described
in the Remote System Reset section.
2. When VDD2 is powered through auxiliary winding or
another configuration, when a short circuit occurs on the
output terminals, the auxiliary winding is not shorted and
maintains a positive voltage above the UVLO threshold of
the VDD2 pin. To enter hiccup mode, it is recommended to
use the circuit shown in Figure 15. The circuit operates as
follows: when the output voltage goes low due to a short
circuit, the D1 diode turns on, which pulls the base of the
bipolar junction transistor low, shutting off VDD2. The
system then enters hiccup mode, as described in the
Remote System Reset section.
Data Sheet ADP1074
Rev. D | Page 21 of 32
R3 is sized to bias the Zener diode and R4 is sized such that
(VZENER – 1)/R4 > IZENER, where VZENER is the voltage of the
diode and IZENER is the biasing current of the diode. This
sizing ensures that the impedance of the resistor is less
than the impedance of the diode, which causes the voltage
of the diode to drop, and allows VDD2 to enter UVLO.
If the output voltage is <5 V, the same procedure can be
used to size the R4 resistor. If a discrete LDO is not used, a
simple resistor and diode connector to the output voltage
is sufficient. In this case, the R4 resistor is sized to limit the
current through the D1 diode when the output voltage is
0 V during a short-circuit event. Because the bandwidth of
the system is high, the ADP1074 is able to maintain
voltage regulation at the proper voltage level, even if the
auxiliary winding voltage is higher than the output voltage.
The soft start and soft start from precharge conditions is
met with the addition of this circuit due to the bandwidth
of the overall system.
R3
500Ω
R4
100Ω
VDD2
VOUT
AGND2
~6.3V
ZENER
D1
D1
VOUT
R4
100Ω
ALTERNATE OPTION
FROM AUMILIARY
WINDING
~10V
15627-028
Figure 15. Recommended Circuit to Guarantee Hiccup Mode Showing
Typical Values
TEMPERATURE SENSING
The ADP1074 has an internal temperature sensor that shuts
down the controller when the internal temperature exceeds the
OTP limit. At this time, the primary and secondary MOSFET
drivers (PGATE, NGATE, SR1, and SR2) are held low. When the
temperature drops below the OTP hysteresis level, the ADP1074
restarts with a soft start sequence.
FREQUENCY SETTING (RT PIN)
The switching frequency can be programmed in a range of
50 kHz to 600 kHz by connecting a resistor from RT to AGND1.
A small current flows out of the RT pin and the voltage across it
sets up the internal oscillator frequency. The value of this pin is
approximately 1.224 V in steady state. Use the following equation
to determine the resistor (in ) for a particular switching
frequency (in kHz):
1000
1
)(1067.41
1
(kHz) 12
BOTTOP
SRR
f
where:
fS is the switching frequency.
RTOP is the top resistor of the divider.
RBOT is the bottom resistor of the divider.
MAXIMUM DUTY CYCLE
To prevent the transformer core from saturating in the event of
high current or extreme load transient and reduce voltage stress
on the MOSFETs, a maximum duty cycle clamp can be set by
connecting the DMAX pin to the center tap of the resistive
divider that is connected from RT to AGND1, as shown in
Figure 16.
R
TOP
R
BOT
DMAX
RT
ADP1074
PGND1
AGND1
15627-012
Figure 16. Setting the Maximum Duty Cycle, DMAX
The maximum duty cycle is calculated by the following:
%
)(
50
50
BOTTOP
BOT
MAX RR
R
D
where:
DMAX is 50% when RBOT is 0 Ω or when the DMAX pin is
connected to AGND1. For example, when RTOP is equal to RBOT,
DMAX is 75%. DMAX can reach 100% if RTOP is 0 or when RBOT
becomes open circuit.
RBOT is the bottom resistor of the divider.
RTOP is the top resistor of the divider.
As an added protection feature to prevent open-loop conditions,
the maximum duty cycle is also applicable during soft start. If the
controller reaches DMAX during soft start for three con-
secutive switching periods, the 40 ms hiccup timer is initiated.
FREQUENCY SYNCHRONIZATION
The switching frequency of the ADP1074 can be synchronized
to an external clock at the SYNC pin. When an external clock
rising edge is first detected, it takes approximately seven to ten
periods for the internal clock to lock in the SYNC clock frequency.
In between the time that the SYNC clock is detected and the
time that it is locked in, the controller continues to operate with
the internal oscillator frequency.
The SYNC frequency must be within ±10% of the internal
oscillator frequency set by the RT pin; otherwise, synchronization
does not take place.
A clock signal can be applied to SYNC on the fly or prior to the
soft start sequence. A dithered clock can also be applied to
SYNC to reduce the peak electromagnetic interference (EMI)
noise in the converter output and switch node. The internal
clock is able to lock onto the dithered clock cycle by cycle.
It is recommended to connect the SYNC pin to AGND1 if this
feature is not used.
ADP1074 Data Sheet
Rev. D | Page 22 of 32
SYNCHRONOUS RECTIFIER (SR) DRIVERS
There are two synchronous rectifier drivers on the secondary
side for driving the synchronous switches. SR1 is the forward
driver that is in phase with the primary side NGATE driver,
and SR2 is the freewheeling driver. VDD2 is the front end of
the LDO at VREG2. The 5 V internal LDO at VREG2 powers
the SRx drivers and all internal circuits on the secondary side.
The recommended power supply range at VDD2 is from 6 V to
36 V. However, at 36 V input to VDD2, the power dissipation
in the LDO can be significant. If VDD2 is less than 5 V, the
LDO operates in the dropout region, where VREG2 and the
driver output are less than 5 V. In this case, it is recommended
to supply VDD2 with an auxiliary power supply greater than 5 V.
VDD2 can be directly connected to the converter output or an
auxiliary power supply, which can be realized by using a third
winding of the main transformer. For additional drive strength,
SR1 and SR2 can be fed into an external MOSFET driver such
as the ADP3624 or the ADP3654.
OUTPUT OVERVOLTAGE PROTECTION (OVP)
When the output voltage exceeds the OVP threshold of 1.36 V,
the controller immediately shuts off the drivers (NGATE, PGATE,
SR1, and SR2) on both the primary and secondary side. When
the voltage at the OVP drops below the OV hysteresis level, the
controller resumes switching in the next switching period with
the primary drivers, followed by phasing in of the SR1 and SR2
PWMs. The OVP feature causes the system to enter hiccup for
200 ms if the voltage on the OVP pin exceeds 1.36 V for a
sustained period of 200 s.
ACTIVE CLAMP (PGATE)
In a forward converter, the magnetizing energy stored in the
transformer core during the on cycle must be demagnetized or
reset during the off cycle; otherwise, the transformer core
saturates in subsequent switching cycles. To reset the transformer
core, an active clamp switch is turned on during the off cycle,
which enables the reset of the transformer. This process reduces
power dissipation and increases overall efficiency. The active
clamp switch can be a high-side or a low-side switch using the
driver at the PGATE pin.
LEADING EDGE BLANKING
A leading edge blanking time is added after the rising edge of
the NGATE signal to avoid picking up any unwanted noise or
ringing at the CS pin at the start of the switching period.
GATE DELAY AND SR DEAD TIME
At high input voltages, the rise and fall times of the main MOSFET
on the primary side are larger than at lower input voltages. It is
important to have a programmable delay time between the PGATE
rising and the NGATE rising to account for different input
voltages, leakage inductances of the transformer, and MOSFET
output capacitances. Also, a sufficient gate delay between
PGATE and NGATE ensures zero volt switching (ZVS), which
is important for reducing switching losses in the main
MOSFET.
The total delay between the PGATE and NGATE rising edges
can be programmed with a resistor connected to the NGATE
pin. The resistor connected to NGATE is determined by the
ADP1074 prior to soft start. The programmable delay between
PGATE to NGATE has four discrete settings having typical
values of 30 ns, 60 ns, 100 ns, and 150 ns. See Figure 17 for
more details.
PGATE
FIXED
25ns
FIXED
25ns
30ns TO 150ns
SR DEAD TIME
(NGATE RESISTOR)
SR DEAD TIME
(NGATE RESISTOR)
SR2
SR1
NGATE GATE DELAY
35ns
iCOUPLER DELAY
15627-013
Figure 17. Gate Delay and SR Dead Time Settings
To maximize efficiency and avoid cross conduction between
the primary NGATE and SR2 (freewheeling switch), it is
necessary to have a delay time between SR2 and NGATE.
As shown in Figure 17, the NGATE falling edge and SR1 falling
edge turn off simultaneously with an iCoupler delay.
In addition, a dead time between SR1 and SR2 is internally
fixed to 25 ns (typical) to avoid shorting out the secondary
transformer winding.
LIGHT LOAD MODE (LLM) AND SR PHASE IN
Add a resistor at the MODE pin to enable the ADP1074 power
saving LLM feature. A current source from the MODE pin of
6.5 A into this resistor sets up the LLM threshold voltage, which
is compared to the COMP voltage. When the COMP voltage
rises above the LLM threshold (that is, the MODE pin voltage),
the SRx PWMs gradually increase (or phase in) from the duty
cycle at light load to the steady state duty cycle at the SRx phase
in rate. The SRx phase in rate moves the SRx edges every
1.5 ns per s. Without the phase in sequence, a dip in the output
voltage can occur if the SRx PWMs transition from zero to full
duty cycle instantaneously.
In a load dump situation, for example, when the load is stepped
from full load to light load, that is, from continuous conduction
mode (CCM) to discontinuous conduction mode (DCM) oper-
ation, the duty cycles of the SRx PWMs gradually phase out at
the SRx phase out rate, which has the same numerical value of
the SRx phase in rate. The phase out sequence of the SRx PWMs
prevents reverse current in the secondary, and at the same time,
optimizes the dynamic performance of the output response.
Note that the level of COMP is still above the minimum COMP
clamp level at this point, and the ADP1074 outputs duty cycles
with minimum on time.
Data Sheet ADP1074
Rev. D | Page 23 of 32
If the load is further reduced and the COMP pin voltage becomes
equal to the minimum COMP clamp level, the ADP1074 enters
pulse skip mode.
The NGATE delay time settings shown in Figure 17 remain
unchanged in LLM operation. Use the following formula to set
up the light load mode threshold:
MODE
GAINLLMPEAK
MODE I
CSI
R8.0
_
where:
IPEAK_LLM is the peak primary current at the light load condition.
CSGAIN = 12.5.
IMODE is the current flowing out of the MODE pin.
For a forced CCM operation, connect MODE to AGND2. In
this case, pulse skipping is disabled.
Note also that when the system enters light load mode, the
synchronous rectifiers terminate at the falling edge of SR1. This
termination facilitates the prevention of the PWM at a negative
current, which can cause a spike in voltage that can damage the
synchronous FET.
EXTERNAL START-UP CIRCUIT
For input voltages higher than 36 V, where the power
dissipation in the internal 8 V LDO can be significant, the use of
an external start-up circuit is recommended. (See Figure 18 for
an example.) In this case, the VIN and VREG1 pins are shorted
together and connect to the output of the start-up circuit.
Because the input pre-enable bias current, the (VIN + VREG1)
start-up current, is approximately 160 µA, the output of the start-
up circuit must be able to provide this level of current to
perform a soft start. The auxiliary winding then provides the
bias voltage, shutting off the start-up circuit after soft start
completes.
8V LDO
START-UP
CIRCUIT
ADP1074
1µA 4µA
LOGIC
VREF
1.2V
R1
R2
VIN
V
AUX1
VREG UVLO
VIN
VREG1
EN
HYSTERESIS
GENERATOR
15627-014
Figure 18. Precision EN Circuit Connection with an External Start-Up Circuit
A fast start-up circuit is shown in Figure 19. This circuit requires
two components: a Zener diode, which sets up the start-up
voltage at the VIN and VREG1 pin, and a negative-positive-
negative (NPN) transistor, which sets up a fast current path for
charging up the start-up capacitor, C1. The start-up current
through R1 must be more than 160 µA, which is the minimum
specified start-up current, and it is recommended that the start-
up voltage at VREG1 and VIN be approximately 8 V to 13 V.
The auxiliary winding then provides the bias voltage, shutting
off the NPN transistor after soft start completes.
ADP1074
LDO
R2
C1
2.2µF
D1
8.7V TO 11V
R1
V
IN
Q1
R3
VIN
14V
V
AUX
= 8V TO 13V
FROM
AUXILLIARY
WINDING
VREG1
EN
15627-015
Figure 19. Fast Start-Up Circuit
SOFT STOP
The ADP1074 employs a soft stop feature that brings the
output voltage gradually down to zero by using the SS2 pin as a
reference. During the soft stop procedure, the SS2 pin is discharged
to zero by a current sink of approximately 1.5 times the value
during closed-loop soft start.
When the voltage at EN drops below the EN threshold, the SR1
and SR2 secondary drivers shut off immediately, and the primary
NGATE pulse width gradually decreases the duty cycle from the
last known condition to the minimum pulse width and down to
zero, causing the output voltage to decrease. The soft stop feature
prevents any reverse current when the controller is shut down.
When the output voltage decreases below the VDD2 UVLO
threshold, there is no transmission of the COMP signal to the
primary side. Therefore, the output voltage continues to decrease
at the rate at which the load current discharges the output
capacitor.
When the load is at a minimum or at no load, the output voltage
does not discharge because any reduction in duty cycle or
current limit does not discharge the output voltage linearly.
POWER GOOD
The PGOOD pin is an open-drain N-channel metal-oxide
semiconductor (nMOS), which is off in fault conditions.
Connect a pull-up resistor between PGOOD and VREG2 or to
an external power supply less than 5.5 V.
To toggle PGOOD, the fault voltage on the FB pin and the OVP
pin must exceed the overvoltage threshold of 1.36 V. PGOOD
also toggles if the FB pin voltage drops 100 mV below the
nominal of 1.2 V, that is, to 1.1 V.
PGOOD toggles again after the output voltage crosses the
PGOOD hysteresis voltage of 36 mV. PGOOD becomes active
after a delay of 5 µs for an FB pin fault and after 90 ns for an
OVP pin fault.
ADP1074 Data Sheet
Rev. D | Page 24 of 32
OCP/FEEDBACK RECOVERY
During steady state, the FB pin is at 1.2 V. At this time, the SS2
pin voltage is 1.4 V. Under abnormal situations, such as an
overload condition, the output voltage can dip severely. In such
an event, the current limit is at the maximum level, and the
COMP pin voltage is at its clamp level. If the two conditions of
the COMP pin voltage being clamped and VFB < (1.2 V – 100 mV)
are satisfied, the controller discharges the SS2 pin using a fast
current sink (200 A) to make the SS2 pin equal to the FB pin.
The controller then attempts to perform a soft start from this
precharged condition, that is, from the last known value of the
output voltage. This process is how the OCP/feedback recovery
feature operates.
However, if at any time the voltage on the COMP pin is above
the maximum clamp voltage for a period greater than 1.5 ms,
the system enters hiccup mode.
During the soft start from precharge, the output voltage rises at
the same rate as determined by the capacitor on the SS2 pin. If,
however, there is a detrimental fault in the power stage that
prevents the rise of the output voltage, VFB does not track SS2,
and when SS2 > (VFB + 100 mV), the COMP pin voltage increases
to the clamp level, and the system again enters OCP/feedback
recovery mode.
OUTPUT VOLTAGE TRACKING
The ADP1074 offers a tracking feature. During steady state, the
FB pin is at 1.2 V. At this time, the SS2 pin voltage is at 1.4 V.
Using an external DAC, the voltage on the SS2 pin can
modulate the output voltage. It is recommended that the SS2
pin voltage be changed only after the VDD2 UVLO point is
crossed, and control is handed over to the secondary side, or
else the handover process does not occur smoothly, resulting in
glitches in the output voltage. Ideally, the PGOOD pin can be
used as a signal that indicates that regulation is achieved, to initiate
the tracking.
The SS2 voltage must be brought down from 1.4 V to 1.2 V, and
it must be brought down even further to effect any change in the
output voltage. The rate at which the output tracks the SS2 pin is
dependent upon the overall system bandwidth. Note that while
modulating the output voltage, if the FB pin voltage drops
below (1.2 V − 100 mV = 1.1 V), the PGOOD pin toggles.
REMOTE SYSTEM RESET
For a remote (secondary side) system shutdown, an open-drain
general-purpose input/output (GPIO) of an external micro-
controller can be used to force the SS2 pin to 0 V. This pull-down
causes the ADP1074 to regulate to 0 V, and the ADP1074
enters pulse skip mode or outputs a minimum duty cycle
because the SS2 pin offsets because of the finite resistance of the
GPIO.
When VDD2 is charged from the output bus, this setup is
equivalent to a system shutdown, because when VDD2 <
VDD2 UVLO, the ADP1074 enters a special hiccup mode of
200 ms (instead of the standard 40 ms hiccup).
When VDD2 is powered using auxiliary winding, the system
regulates to the voltage proportional to the voltage on the SS2 pin
and eventually enters the special hiccup mode previously
mentioned, after the auxiliary rail decays below the VDD2
UVLO threshold.
Therefore, the SS2 pin can achieve output tracking as well as a
secondary side shutdown, also known as remote system reset,
as shown in Figure 20.
Data Sheet ADP1074
Rev. D | Page 25 of 32
V
FB
(1.2V)
SS2 (1.4V)
VDD2 UVLO
(3.5V)
VDD2
200ms HICCUP COUNTER
SS2
CAPACITOR
SS1
CAPACITOR
DEPENDS ON VDD2
CAPACITOR AND I
DD2
CONSUMPTION
HANDOVER TIME FROM
PRIMARY TO SECONDARY
TIME
PWM SWITCHING
DEPENDS ON SYSTEM
BANDWIDTH
15627-016
Figure 20. Remote Software Reset with 200 ms Hiccup
ADP1074 Data Sheet
Rev. D | Page 26 of 32
V
FB
1.2V
SS2 = 1.4V
DEPENDS ON
LOOP BANDWIDTH
TIME
VDD2
DEPENDS ON
LOOP BANDWIDTH
15627-017
VDD2_UVLO
3.5V
Figure 21. Tracking with SS2 Pin
OCP COUNTER
During overload conditions, when the peak sensed currents
exceed the OCP threshold voltage of 120 mV on the CS pin, the
ADP1074 immediately terminates the remainder of the PWM
pulse. If the peak sense current continues to exceed the threshold
every switching period for 1.5 ms, the system enters hiccup mode,
by which it shuts down for approximately 40 ms and then soft
starts. During an exceeded overcurrent situation, such as a dead
short, it is likely that the programmed slope compensation is
not enough, and therefore, the system enters subharmonic
oscillation. If this is the case, the system cannot enter hiccup
mode because the OCP threshold is crossed every alternate
switching period, and the 1.5 ms hiccup counter resets.
To prevent this scenario, the ADP1074 latches the last known
state, whereby if an OCP condition registered as a 1 in one
switching period and as a 0 in the next switching period, it is
still counted as a 1. In this manner, the system can enter hiccup
mode even in subharmonic oscillation. Missing two OCP
thresholds consecutively resets the hiccup counter.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent upon the characteristics of
the voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADP1074.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accel-
eration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage.
The values shown in Table 10 summarize the peak voltage for
50 years of service life for a bipolar ac operating condition. In
many cases, the approved working voltage is higher than the
50 year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
The ADP1074 insulation lifetime depends on the voltage wave-
form type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates depending on
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 22,
Figure 23, and Figure 24 show these different isolation voltage
waveforms.
A bipolar ac voltage environment is the worst case for the iCoupler
products, yet meets the 50 year operating lifetime recommended
by Analog Devices for maximum working voltage. In the case
of unipolar ac or dc voltage, the stress on the insulation is
significantly lower. The low stress allows operation at higher
working voltages while still achieving a 50 year service life. Treat
any cross insulation voltage waveform that does not conform to
Figure 23 or Figure 24 as a bipolar ac waveform, and limit its peak
voltage to the 50 year lifetime voltage value listed in Table 10.
Note that the voltage presented in Figure 23 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage
cannot cross 0 V.
0V
RATED PEAK VOLTAGE
15627-018
Figure 22. Bipolar AC Waveform
0V
RATED PEAK VOLTAGE
15627-019
Figure 23. Unipolar AC Waveform
0V
RATED PEAK VOLTAGE
15627-020
Figure 24. DC Waveform
Data Sheet ADP1074
Rev. D | Page 27 of 32
LAYOUT GUIDELINES
The layout guidelines for the primary side are as follows:
1. Ground all the capacitors to their respective grounds. For
example, ground the SS1 capacitor to AGND1.
2. Use the CS pin and the AGND1 pin to differentially sense
the primary current measurement through the sense
resistor. Do not cross the CS and AGND1 traces for
current sensing across any switch nodes.
3. Place a capacitor (33 pF to 470 pF typical) close to the CS
pin, connected to AGND1.
4. Connect the ground plane on the primary side to PGND1.
5. Connect AGND1 to PGND1 using a 0 resistor.
6. Place resistors (1 to 5 typical) in series with NGATE
and the main power MOSFET. These resistors aid in
eliminating any ringing on the drive voltages.
The layout guidelines for the secondary side are as follows:
1. Ground all the capacitors to their respective grounds. For
example, ground the SS2 capacitor to AGND2.
2. Place resistors (1 to 5 ) in series with SRx and the
synchronous MOSFET. These resistors aid in eliminating
any ringing on the drive voltages.
3. Connect the ground plane on the secondary side to
PGND2. Connect the negative terminal of the output
voltage to the PGND2 plane.
4. Use the FB pin and the AGND2 pin to remotely
differentially sense the output voltage by connecting
AGND2 to the negative terminal of the output voltage
using a 0 resistor.
5. Use a 100 nF capacitor on the MODE pin if light load
mode is used in noisy environments.
ADP1074 Data Sheet
Rev. D | Page 28 of 32
TYPICAL APPLICATION CIRCUITS
VIN
VIN
ACTIVE
CLAMP
PMOS
NMOS
SR2
SR1
RRAMP
RSENSE
RDT
RTOP
RBOT
CSS1
VOUT
CS
EN
VREG1
NGATE
PGATE
SYNC
SS1
DMAX
RT
PGND1
AGND1
SR1
SR2
VDD2
VREG2
COMP
FB
OVP
SS2
PGOOD
MODE
PGND2
AGND2
15627-021
ADP1074
Figure 25. Typical Application Circuit for Active Clamp Forward Topology
Data Sheet ADP1074
Rev. D | Page 29 of 32
VIN
R1
14kΩ
114mW
AT 48V
C1
10µF
ZENER
V
IN
TO VREG1
V
BIAS
= 8V TO 13V
ACTIVE
CLAMP
PMOS
NMOS
SR2
SR1
R
RAMP
R
SENSE
R
DT
R
TOP
R
BOT
C
SS1
V
OUT
CS
EN
VREG1
NGATE
PGATE
SYNC
SS1
DMAX
RT
PGND1
AGND1
EXTERNAL START-UP CIRCUIT
SR1
SR2
VDD2
VREG2
COMP
FB
OVP
SS2
PGOOD
MODE
PGND2
AGND2
15627-022
ADP1074
Figure 26. Typical Application Circuit for Active Clamp Forward Topology with Simple Start-Up Circuit and Bias Winding
Data Sheet ADP1074
Rev. D | Page 31 of 32
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
15.60 (0.6142)
15.20 (0.5984)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75(0.0295)
0.25(0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
24 13
12
1
1.27 (0.0500)
BSC
12-09-2010-A
Figure 28. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
0
4-20-2017-
B
P
KG-005313
PIN 1
INDICATOR
SEATING
PLANE
8.10
8.00
7.90
4.10
4.00
3.90
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.25
0.20
0.15
0.35
0.30
0.25
0.75 REF
6.50 BSC
2.25
BSC
3.78 BSC2.825 BSC
1.15
2.50
BSC
2.80
1.775
BSC
0.50
BSC
0.25
BSC
0.28 REF
1.20
MAX
COPLANARITY
0.08
1
9
10
15
16
21
22 24 3
4
PIN 1 CORNER
INDICATOR
Figure 29. 24-Terminal Land Grid Array [LGA]
(CC-24-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADP1074WARWZ −40°C to +125°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24
ADP1074WARWZ-RL −40°C to +125°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24
ADP1074WARWZ-R7 −40°C to +125°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24
ADP1074ARWZ −40°C to +125°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24
ADP1074ARWZ-RL −40°C to +125°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24
ADP1074ARWZ-R7 −40°C to +125°C 24-Lead Standard Small Outline Package [SOIC_W] RW-24
ADP1074-EVALZ ADP1074 Evaluation Board with Wide Body IC
ADP1074ACCZ −40°C to +125°C 24-Terminal Land Grid Array [LGA] CC-24-6
ADP1074ACCZ-RL −40°C to +125°C 24-Terminal Land Grid Array [LGA] CC-24-6
ADP1074ACCZ-R7 −40°C to +125°C 24-Terminal Land Grid Array [LGA] CC-24-6
ADP1074LGA-EVALZ ADP1074 Evaluation Board with LGA IC
1 Z = RoHS-Compliant Part.
