LTC2066/LTC2067
1
Rev A
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TYPICAL APPLICATION
FEATURES DESCRIPTION
10µA Supply Current,
Low IB, Zero-Drift Operational Amplifier
The LTC
®
2066/LTC2067 are single and dual low power,
zero-drift, 100kHz amplifiers. The LTC2066/LTC2067
enable high resolution measurement at extremely low
power levels.
Typical supply current is 7.5µA per amplifier with a maxi-
mum of 10µA. The available shutdown mode has been
optimized to minimize power consumption in duty-cycled
applications and features low charge loss during power-
up, reducing total system power.
The LTC2066/LTC2067’s self-calibrating circuitry re-
sults in very low input offset (5µV max) and offset drift
(0.02µV/°C). The maximum input bias current is only
35pA and does not exceed 150pA over the full specified
temperature range. The extremely low input bias current
of the LTC2066/LTC2067 allows the use of high value
power-saving resistors in the feedback network.
With its ultralow quiescent current and outstanding
precision, the LTC2066/LTC2067 can serve as a signal
chain building block in portable, energy harvesting and
wireless sensor applications.
The LTC2066 is available in 6-lead SC70 and 5-lead TSOT-
23 packages. The LTC2067 is available in 8-lead MSOP
and 10-lead DFN packages. These devices are fully speci-
fied over the –40°C to 85°C and –40°C to 125°C tempera-
ture ranges.
Precision Micropower Low Side Current Sense
Output Voltage vs Sense Current
APPLICATIONS
n Low Supply Current: 10μA Maximum (per Amplifier)
n Offset Voltage: 5μV Maximum
n Offset Voltage Drift: 0.02μV/°C Maximum
n Input Bias Current:
n 5pA Typical
n 50pA Maximum, –40°C to 85°C
n 150pA Maximum, –40°C to 125°C
n Integrated EMI Filter (90dB Rejection at 1.8GHz)
n Shutdown Current: 170nA Maximum (per Amplifier)
n Rail-to-Rail Input and Output
n 1.7V to 5.25V Operating Supply Range
n AVOL: 140dB Typical
n Low-Charge Power-Up for Duty Cycled Applications
n Specified Temperature Ranges:
n –40°C to 85°C
n –40°C to 125°C
n SC70, TSOT-23, MS8 and DFN Packages
n Signal Conditioning in Wireless Mesh Networks
n Portable Instrumentation Systems
n Low-Power Sensor Conditioning
n Gas Detection
n Temperature Measurement
n Medical Instrumentation
n Energy Harvesting Applications
n Low Power Current Sensing All registered trademarks and trademarks are the property of their respective owners.
10k*
0.1%
1M
0.1%
VOUT = 10 • ISENSE
1mV TO 2.5V
VIN
*RESISTOR CANCELS OUT PARASITIC SEEBECK EFFECT VOLTAGE
–
+
3.3V
100mΩ
0.1%
ISENSE
100µA TO 250mA
LOAD
10k
0.1%
2066 TA01a
LTC2066
I
SENSE
(mA)
0.1
1
10
100
250
0.001
0.01
0.1
1
2.5
OUT
2066 TA01b
LTC2066/LTC2067
2
Rev A
For more information www.analog.com
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ to V–) ................................5.5V
Differential Input Current (+IN to –IN) (Note 2) .... ±10mA
Differential Input Voltage (+IN to –IN) ...................... 5.5V
Input Voltage
+IN, –IN, SHDN ...................(V–) – 0.3V to (V+) + 0.3V
Input Current
+IN, –IN, SHDN (Note 2) .................................. ±10mA
(Note 1)
ORDER INFORMATION
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2066ISC6#TRMPBF LTC2066ISC6#TRPBF LHDB 6-Lead Plastic SC70 –40°C to 85°C
LTC2066HSC6#TRMPBF LTC2066HSC6#TRPBF LHDB 6-Lead Plastic SC70 –40°C to 125°C
LTC2066IS5#TRMPBF LTC2066IS5#TRPBF LTHCZ 5-Lead Plastic TSOT-23 –40°C to 85°C
LTC2066HS5#TRMPBF LTC2066HS5#TRPBF LTHCZ 5-Lead Plastic TSOT-23 –40°C to 125°C
LTC2067IMS8#TRMPBF LTC2067IMS8#TRPBF LTHDC 8-Lead Plastic MSOP –40°C to 85°C
LTC2067HMS8#TRMPBF LTC2067HMS8#TRPBF LTHDC 8-Lead Plastic MSOP –40°C to 125°C
LTC2067IDD#TRMPBF LTC2067IDD#TRPBF LHDD 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2067HDD#TRMPBF LTC2067HDD#TRPBF LHDD 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Parts ending with PBF are RoHS and WEEE compliant.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Output Short-Circuit Duration
(Note 3) ..........................................Thermally Limited
Operating and Specified Temperature Range (Note 4)
LTC2066I/LTC2067I .............................–40°C to 85°C
LTC2066H/LTC2067H ........................ –40°C to 125°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range .................. –65°C to 150°C
LTC2066 LTC2066
+IN 1
V– 2
–IN 3
TOP VIEW
SC6 PACKAGE
6-LEAD PLASTIC SC70
θ
JA
= 265°C/W (Note 5)
+
–
6 V+
5 SHDN
4 OUT
OUT 1
V– 2
TOP VIEW
S5 PACKAGE
5-LEAD PLASTIC TSOT-23
θ
JA
= 215°C/W (Note 5)
+IN 3
5 V+
4 –IN
+
–
LTC2067 LTC2067
1
2
3
4
OUTA
–INA
+INA
V–
8
7
6
5
V+
OUTB
–INB
+INB
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
θJA
= 163°C/W, θ
JC = 40°C/W (Note 5)
A
B
TOP VIEW
11
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
θJA = 43°C/W, θJC = 5.5°C/W (Note 5)
EXPOSED PAD (PIN 11) IS CONNECTED TO V
–
(PIN 4) (PCB CONNECTION OPTIONAL)
10
9
6
7
8
4
5
3
2
1V+
OUTB
–INB
+INB
SHDN
OUTA
–INA
+INA
V–
NC
A
B
LTC2066/LTC2067
3
Rev A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 6) VS = 1.7V
l
1 ±5
±10
μV
μV
ΔVOS/ΔT Input Offset Voltage Drift (Note 6) –40°C to 85°C
–40°C to 125°C
l
l
±0.03
±0.05
μV/°C
µV/°C
IBInput Bias Current (Note 7) ±2 pA
IOS Input Offset Current (Note 7) ±4 pA
inInput Noise Current Spectral Density f ≤ 100Hz 35 fA/√Hz
enInput Noise Voltage Spectral Density f ≤ 100Hz 90 nV/√Hz
en P-P Input Noise Voltage DC to 10Hz 1.9 μVP–P
CIN Input Capacitance Differential
Common Mode
3.3
3.5
pF
pF
VCMR Input Voltage Range Guaranteed by CMRR l(V–) – 0.1 (V+) + 0.1 V
CMRR Common Mode Rejection Ratio (Note 8) VCM = (V–) – 0.1V to (V+) + 0.1V
RL = 499k
l
103
100
123 dB
dB
PSRR Power Supply Rejection Ratio VS = 1.7V to 5.25V
RL = 499k
l
108
106
126 dB
dB
AVOL Open Loop Gain VOUT = (V–) + 0.1V to (V+) – 0.1V, RL = 499k 135 dB
VOL Output Voltage Swing Low (VOUT – V–) RL = 499k 0.05 mV
RL = 10k
l
3 10
20
mV
mV
VOH Output Voltage Swing High (V+ – VOUT) RL = 499k 0.1 mV
RL = 10k
l
4.5 10
50
mV
mV
ISC Output Short Circuit Current Sourcing
l
5.8
4
7.5 mA
mA
Sinking
l
10.4
5
13 mA
mA
SR Slew Rate AV = +1 17.5 V/ms
GBW Gain Bandwidth Product RL = 499k 100 kHz
tON Power-Up Time 0.4 ms
fCInternal Chopping Frequency 25 kHz
VSSupply Voltage Range Guaranteed by PSRR l1.7 5.25 V
ISSupply Current per Amplifier No Load
–40°C to 85°C
–40°C to 125°C
l
l
7.4 10
12.5
20
μA
μA
µA
In Shutdown (SHDN = V–)
–40°C to 85°C
–40°C to 125°C
l
l
90 170
250
500
nA
nA
nA
VHSHDN Pin Threshold, Logic High (Referred to V–)l1.0 V
VLSHDN Pin Threshold, Logic Low (Referred to V–)l0.65 V
ISHDN SHDN Pin Current VSHDN = 0V l–150 –20 nA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VS = 1.8V, VCM = VOUT = VS/2, VSHDN = 1.8V,
RLtoVS/2.
LTC2066/LTC2067
4
Rev A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 6) VS = 5.25V
l
1 ±5
±10
μV
μV
ΔVOS/ΔT Input Offset Voltage Drift (Note 6) –40°C to 85°C
–40°C to 125°C
l
l
±0.02
±0.04
μV/°C
µV/°C
IBInput Bias Current
–40°C to 85°C
–40°C to 125°C
l
l
±5 ±35
±50
±150
pA
pA
pA
IOS Input Offset Current
–40°C to 85°C
–40°C to 125°C
l
l
±10 ±35
±50
±150
pA
pA
pA
inInput Noise Current Spectral Density f ≤ 100Hz 35 fA/√Hz
enInput Noise Voltage Spectral Density f ≤ 100Hz 80 nV/√Hz
en P–P Input Noise Voltage DC to 10Hz 1.7 μVP–P
CIN Input Capacitance Differential
Common Mode
3.3
3.5
pF
pF
VCMR Input Voltage Range Guaranteed by CMRR l(V–) – 0.1 (V+) + 0.1 V
CMRR Common Mode Rejection Ratio VCM = (V–) – 0.1V to (V+) + 0.1V
RL = 499k
l
111
108
134 dB
dB
PSRR Power Supply Rejection Ratio VS = 1.7V to 5.25V
RL = 499k
l
108
106
126 dB
dB
EMIRR EMI Rejection Ratio
VRF = 100mVPK
EMIRR = 20 • log(VRF/ΔVOS)
f = 400MHz
f = 900MHz
f = 1800MHz
f = 2400MHz
66
79
90
76
dB
dB
dB
dB
AVOL Open Loop Gain VOUT = (V–) + 0.1V to (V+) – 0.1V, RL = 499k
l
112
110
140 dB
dB
VOL Output Voltage Swing Low (VOUT – V–) RL = 499k 0.1 mV
RL = 10k
l
5.5 15
20
mV
mV
VOH Output Voltage Swing High (V+ – VOUT) RL = 499k 0.15 mV
RL = 10k
l
7 15
20
mV
mV
ISC Output Short Circuit Current Sourcing
l
30
16
51 mA
mA
Sinking
l
20
5
48 mA
mA
SR Slew Rate AV = +1 17.5 V/ms
GBW Gain Bandwidth Product RL = 499k 100 kHz
tON Power-Up Time 0.4 ms
fCInternal Chopping Frequency 25 kHz
VSSupply Voltage Range Guaranteed by PSRR l1.7 5.25 V
ISSupply Current per Amplifier No Load
–40°C to 85°C
–40°C to 125°C
l
l
7.5 10
12.5
20
μA
μA
µA
In Shutdown (SHDN = V–)
–40°C to 85°C
–40°C to 125°C
l
l
90 170
250
500
nA
nA
nA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VS = 5V, VCM = VOUT = VS/2, VSHDN = 5V,
RLtoVS/2.
LTC2066/LTC2067
5
Rev A
For more information www.analog.com
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VS = 5V, VCM = VOUT = VS/2, VSHDN = 5V,
RLtoVS/2.
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs are protected by two series connected ESD protection
diodes to each power supply. The input current should be limited to less than
10mA. The input voltage should not exceed 300mV beyond the power supply.
Note 3: A heat sink may be required to keep the junction temperature below
the absolute maximum rating when the output is shorted indefinitely.
Note 4: The LTC2066I/LTC2067I is guaranteed to meet specified
performance from –40°C to 85°C. The LTC2066H/LTC2067H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 5: Thermal resistance varies with the amount of PC board metal
connected to the package. The specified values are for short traces
connected to the leads.
Note 6: These parameters are guaranteed by design. Thermocouple effects
preclude measurements of these voltage levels during automated testing.
VOS is measured to a limit determined by test equipment capability.
Note 7: Input Bias Current, Input Offset Current and Open Loop Gain are
only production tested at 5V. Input Bias Current and Input Offset Current
at 1.8V are expected to meet 5V specifications.
Note 8: Minimum specifications for these parameters are limited by noise
and the capabilities of the automated test system.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VHSHDN Pin Threshold, Logic High (Referred to V–)l1.8 V
VLSHDN Pin Threshold, Logic Low (Referred to V–)l0.8 V
ISHDN SHDN Pin Current VSHDN = 0V l–150 –20 nA
LTC2066/LTC2067
6
Rev A
For more information www.analog.com
Input Offset Voltage vs
Input Common Mode Voltage
Input Offset Voltage vs
Input Common Mode Voltage
Input Offset Voltage vs
Supply Voltage
5 TYPICAL UNITS
V
S
= 5V
T
A
= 25°C
V
CM
(V)
–0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
–5
–4
–3
–2
–1
0
1
2
3
4
5
V
OS
(µV)
2066 G07
5 TYPICAL UNITS
V
S
= 1.8V
T
A
= 25°C
V
CM
(V)
–0.5
0
0.5
1
1.5
2
2.5
–5
–4
–3
–2
–1
0
1
2
3
4
5
V
OS
(µV)
2066 G08
5 TYPICAL UNITS
V
CM
= V
S
/2
T
A
= 25°C
V
S
(V)
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
–10
–8
–6
–4
–2
0
2
4
6
8
10
V
OS
(µV)
2066 G09
TYPICAL PERFORMANCE CHARACTERISTICS
Input Offset Voltage Drift
Distribution (H-Grade)
Input Offset Voltage Distribution Input Offset Voltage Distribution
Input Offset Voltage Drift
Distribution (H-Grade)
Input Offset Voltage Drift
Distribution (I-Grade)
Input Offset Voltage Drift
Distribution (I-Grade)
260 TYPICAL UNITS
V
S
= 5V
V
OS
(µV)
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
10
20
30
40
50
60
70
80
2066 G01
NUMBER OF AMPLIFIERS
260 TYPICAL UNITS
V
S
= 1.8V
V
OS
(µV)
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
10
20
30
40
50
60
70
2066 G02
NUMBER OF AMPLIFIERS
260 TYPICAL UNITS
V
S
= 5V
TA = –40°C TO 125°C
V
OS
TC (nV/°C)
0
5
10
15
20
25
30
35
40
45
50
0
10
20
30
40
50
60
70
80
90
100
2066 G03
NUMBER OF AMPLIFIERS
260 TYPICAL UNITS
V
S
= 1.8V
TA = –40°C TO 125°C
V
OS
TC (nV/°C)
0
5
10
15
20
25
30
35
40
45
50
0
20
40
60
80
100
120
2066 G04
NUMBER OF AMPLIFIERS
260 TYPICAL UNITS
V
S
= 5V
TA = –40°C TO 85°C
V
OS
TC (nV/°C)
0
5
10
15
20
25
30
35
40
45
50
0
20
40
60
80
100
120
140
2066 G05
NUMBER OF AMPLIFIERS
260 TYPICAL UNITS
V
S
= 1.8V
TA = –40°C TO 85°C
V
OS
TC (nV/°C)
0
5
10
15
20
25
30
35
40
45
50
0
20
40
60
80
100
120
NUMBER OF AMPLIFIERS
2066 G06
LTC2066/LTC2067
7
Rev A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Input Bias Current vs
Input Common Mode Voltage
Input Bias Current vs
Input Common Mode Voltage
Input Bias Current vs
Supply Voltage
Input Bias Current vs Temperature
6276 TYPICAL UNITS
V
S
= 5V
T
A
= 25°C
INPUT BIAS CURRENT (pA)
–20
–16
–12
–8
–4
0
4
8
12
16
20
0
250
500
750
1000
1250
1500
NUMBER OF AMPLIFIERS
2066 G10
6276 TYPICAL UNITS
V
S
= 1.8V
T
A
= 25°C
INPUT BIAS CURRENT (pA)
–10
–8
–6
–4
–2
0
2
4
6
8
10
0
250
500
750
1000
1250
1500
NUMBER OF AMPLIFIERS
2066 G11
V
S
= 5V
I
B
(+IN)
I
B
(–IN)
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–10
–5
0
5
10
15
20
25
I
B
(pA)
2066 G12
I
B
(+IN)
I
B
(–IN)
V
S
= 5V
T
A
= 25°C
V
CM
(V)
–0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
–20
–15
–10
–5
0
5
10
15
20
I
B
(pA)
2066 G13
I
B
(+IN)
I
B
(–IN)
V
S
= 1.8V
T
A
= 25°C
V
CM
(V)
–0.5
0
0.5
1
1.5
2
2.5
–10
–8
–6
–4
–2
0
2
4
6
8
10
I
B
(pA)
2066 G14
V
CM
= V
S
/2
T
A
= 25°C
I
B
(+IN)
I
B
(–IN)
V
S
(V)
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
–10
–8
–6
–4
–2
0
2
4
6
8
10
I
B
(pA)
2066 G15
Input Bias Current Distribution Input Bias Current Distribution
LTC2066/LTC2067
8
Rev A
For more information www.analog.com
Input Offset and Average Current
vs Input Common Mode Voltage
Input Offset and Average Current
vs Input Common Mode Voltage
TYPICAL PERFORMANCE CHARACTERISTICS
DC to 10Hz Voltage Noise
Input Referred Voltage Noise
Density
V
S
= 1.8V
T
A
= 25°C
I
AVG
I
OS
V
CM
(V)
–0.5
0
0.5
1
1.5
2
2.5
–5
–4
–3
–2
–1
0
1
2
3
4
5
I
B
(pA)
2066 G17
V
S
= ± 2.5V
TIME (1s/DIV)
INPUT REFERRED VOLTAGE NOISE (0.5µV/DIV)
2066 G18
Input Referred Current Noise
Density
Common Mode Rejection Ratio
vs Frequency
Power Supply Rejection Ratio
vs Frequency Closed Loop Gain vs Frequency
V
S
= ± 2.5V
V
S
= ± 0.9V
FREQUENCY (Hz)
0.1
1
10
100
1k
10k
100k
10
100
1k
10k
VOLTAGE NOISE DENSITY (nV/√
Hz
)
2066 G19
V
S
= 5V
T
A
= 25°C
I
AVG
I
OS
V
CM
(V)
–0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
–10
–8
–6
–4
–2
0
2
4
6
8
10
I
B
(pA)
2066 G16
V
IN
= 100mV
PK
EMIRR = 20log(100mV/∆V
OS
)
RF FREQUENCY (GHz)
0.05
0.1
1
4
20
40
60
80
100
120
EMIRR (dB)
2066 G21
A
V
= +1000
A
V
= +100
A
V
= +10
A
V
= –1
A
V
= +1
V
S
= 5V
R
L
= 499kΩ
R
F
= 1MΩ
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
–30
–20
–10
0
10
20
30
40
50
60
70
CLOSED LOOP GAIN (dB)
2066 G24
R
L
= 499kΩ
V
S
= 5V
V
S
= 1.8V
FREQUENCY (Hz)
0.1
1
10
100
1k
10k
100k
1M
10M
0
20
40
60
80
100
120
140
CMRR (dB)
2066 G22
EMI Rejection vs Frequency
V
S
= 5V
V
CM
= 2.5V
FREQUENCY (Hz)
0.1
1
10
100
1k
10k
100k
1M
10
100
1k
10k
CURRENT NOISE DENSITY (fA/√
Hz
)
2066 G20
V
S
= 5V
R
L
= 499kΩ
+PSRR
–PSRR
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
0
20
40
60
80
100
120
PSRR (dB)
2066 G23
LTC2066/LTC2067
9
Rev A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Open Loop Gain and Phase
vs Frequency
Open Loop Gain and Phase
vs Frequency
LTC2067 Crosstalk vs Frequency
V
S
= 5V
R
L
= 499kΩ
PHASE
GAIN
CL = 0pF
CL = 47pF
CL = 100pF
FREQUENCY (Hz)
1m
10m
100m
1
10
100
1k
10k
100k
1M
10M
–60
–40
–20
0
20
40
60
80
100
120
140
–450
–405
–360
–315
–270
–225
–180
–135
–90
–45
0
GAIN (dB)
PHASE (°)
2066 G25
V
S
= 1.8V
R
L
= 499kΩ
PHASE
GAIN
C
L
= 0pF
C
L
= 47pF
C
L
= 100pF
FREQUENCY (Hz)
1m
10m
100m
1
10
100
1k
10k
100k
1M
10M
–60
–40
–20
0
20
40
60
80
100
120
140
–270
–240
–210
–180
–150
–120
–90
–60
–30
0
GAIN (dB)
PHASE (°)
2066 G26
R
L
= 10k
B to A
A to B
FREQUENCY (Hz)
100
1k
10k
100k
1M
–140
–120
–100
–80
–60
–40
–20
0
CROSSTALK (dB)
2066 G66
Shutdown Transient with
Sinusoidal Input
Shutdown Transient with
Sinusoidal Input
Enable Transient with
Sinusoidal Input
Enable Transient with
Sinusoidal Input
V
S
= ±2.5V
A
V
= +1
400µs/DIV
V
SHDN
5V/DIV
V
OUT
, V
IN
0.1V/DIV
I
S
5µA/DIV
2066 G28
V
S
= ±0.9V
A
V
= +1
400µs/DIV
V
SHDN
2V/DIV
V
OUT
, V
IN
0.1V/DIV
I
S
5µA/DIV
2066 G29
V
S
= ±2.5V
A
V
= +1
400µs/DIV
V
SHDN
5V/DIV
V
OUT
, V
IN
1V/DIV
I
S
5µA/DIV
2066 G30
V
S
= ±0.9V
A
V
= +1
400µs/DIV
V
SHDN
2V/DIV
V
OUT
, V
IN
0.2V/DIV
I
S
5µA/DIV
2066 G31
Open Loop Gain vs Load
V
S
= 5V
R
LOAD
(kΩ)
1
10
100
500
120
125
130
135
140
145
150
OPEN LOOP GAIN (dB)
2066 G27
LTC2066/LTC2067
10
Rev A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Closed Loop Output Impedance
vs Frequency
Output Impedance in Shutdown
vs Frequency
V
S
= 5V
A
V
= +1
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
1k
10k
100k
1M
Z
OUT
(Ω)
2066 G32
V
S
= 5V
A
V
= +1
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
100M
1G
Z
OUT
(Ω)
2066 G33
Maximum Undistorted Output
Amplitude vs Frequency Supply Current vs Supply Voltage
Supply Current vs Temperature
THD vs Frequency
A
V
= +1
V
S
= ±2.5V
V
OUT
= ±2V
RL = 10k
RL = 499k
FREQUENCY (Hz)
20
100
1k
2k
–120
–100
–80
–60
–40
–20
TOTAL HARMONIC DISTORTION (dB)
2066 G34
A
V
= +1
V
S
= ±2.5V
THD
< –40dB
R
L
= 499k
FREQUENCY (Hz)
100
1k
10k
0
1
2
3
4
5
6
MAXIMUM UNDISTORTED OUTPUT VOLTAGE (V
P–P
)
2066 G35
V
S
(V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
2.5
5.0
7.5
10.0
12.5
IS PER AMPLIFIER (µA)
2066 G36
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
5
6
7
8
9
10
11
12
IS PER AMPLIFIER (µA)
2066 G37
VS = 1.8V
VS = 5V
Supply Current vs SHDN Pin
Voltage
Supply Current vs SHDN Pin
Voltage
V
S
= 5V
SHDN
PIN VOLTAGE (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
10
20
30
40
50
60
70
80
IS PER AMPLIFIER (µA)
2066 G38
125°C
85°C
25°C
–40°C
V
S
= 1.8V
SHDN
PIN VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
2
4
6
8
10
12
14
16
IS PER AMPLIFIER (µA)
2066 G39
125°C
85°C
25°C
–40°C
LTC2066/LTC2067
11
Rev A
For more information www.analog.com
Shutdown Supply Current vs
Supply Voltage
Shutdown Supply Current vs
Temperature
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage Swing High
vs Load Current
Output Voltage Swing High
vs Load Current
125°C
85°C
25°C
–40°C
V
S
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
50
100
150
200
250
300
350
400
IS PER AMPLIFIER (nA)
2066 G43
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
50
100
150
200
250
300
350
IS PER AMPLIFIER (nA)
2066 G44
VS = 1.8V
VS = 5V
V
S
= ± 2.5V
125°C
85°C
25°C
–40°C
I
SOURCE
(mA)
0.01
0.1
1
10
100
0.1
1
10
100
1000
4000
V
+
– V
OH
(mV)
2066 G45
V
S
= ± 0.9V
125°C
85°C
25°C
–40°C
I
SOURCE
(mA)
0.01
0.1
1
10
100
0.1
1
10
100
1000
V
+
– V
OH
(mV)
2066 G46
V
S
= ± 2.5V
125°C
85°C
25°C
–40°C
I
SINK
(mA)
0.01
0.1
1
10
100
0.1
1
10
100
1000
4000
V
OL
– V
-
(mV)
2066 G47
Output Voltage Swing Low
vs Load Current
Output Voltage Swing Low
vs Load Current
V
S
= ± 0.9V
125°C
85°C
25°C
–40°C
I
SINK
(mA)
0.01
0.1
1
10
100
0.1
1
10
100
1000
V
OL
– V
–
(mV)
2066 G48
V
S
= 5V
V
SHDN
(V)
–1
0
1
2
3
4
5
6
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
I
SHDN
(nA)
2066 G40
125°C
85°C
25°C
–40°C
V
S
= 1.8V
V
SHDN
(V)
–1
–0.5
0
0.5
1
1.5
2
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
I
SHDN
(nA)
2066 G41
125°C
85°C
25°C
–40°C
V
SHDN
= 0V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–80
–70
–60
–50
–40
–30
I
SHDN
(nA)
2066 G42
VS = 1.8V
VS = 5V
SHDN Pin Pull-Up Current vs
SHDN Pin Voltage
SHDN Pin Pull-Up Current vs
SHDN Pin Voltage SHDN Pin Current vs Temperature
LTC2066/LTC2067
12
Rev A
For more information www.analog.com
No Phase Reversal
Output Short Circuit Current
vs Temperature
Output Short Circuit Current
vs Temperature
A
V
= +1
V
S
= ±2.5V
V
IN
= 5.6V
P–P
1ms/DIV
VOLTAGE (1V/DIV)
2066 G49
VOUT
VIN
V
S
= ± 2.5V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0
10
20
30
40
50
60
70
80
90
I
SC
(mA)
2066 G50
SOURCING
SINKING
V
S
= ± 0.9V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0
5
10
15
20
I
SC
(mA)
2066 G51
SINKING
SOURCING
TYPICAL PERFORMANCE CHARACTERISTICS
Large Signal Response Large Signal Response
V
S
= ±2.5V
A
V
= +1
200µs/DIV
V
OUT
(1V/DIV)
2066 G52
V
S
= ±0.9V
A
V
= +1
200µs/DIV
V
OUT
(0.5V/DIV)
2066 G53
Small Signal Overshoot
vs Load Capacitance
V
S
= ±0.9V
V
IN
= 40mV
P–P
A
V
= +1
C
L
(pF)
1
10
100
1000
0
10
20
30
40
50
60
OVERSHOOT (%)
2066 G57
+OS
–OS
Small Signal Response
Small Signal Overshoot
vs Load Capacitance
Small Signal Response
V
S
= ±2.5V
V
IN
= 40mV
P–P
A
V
= +1
CL = 3.9pF
CL = 100pF
20µs/DIV
V
OUT
(10mV/DIV)
2066 G54
V
S
= ±0.9V
V
IN
= 40mV
P–P
A
V
= +1
CL = 3.9pF
CL = 100pF
20µs/DIV
V
OUT
(10mV/DIV)
2066 G55
V
S
= ±2.5V
V
IN
= 40mV
P–P
A
V
= +1
C
L
(pF)
1
10
100
1000
0
10
20
30
40
50
60
70
80
OVERSHOOT (%)
2066 G56
+OS
–OS
LTC2066/LTC2067
13
Rev A
For more information www.analog.com
Positive Output Overload
Recovery Positive Output Overload Recovery
Negative Output Overload
Recovery
Negative Output Overload
Recovery
TYPICAL PERFORMANCE CHARACTERISTICS
Negative Input Overload Recovery
Positive Input Overload Recovery Positive Input Overload Recovery
Negative Input Overload Recovery
V
S
= ±2.5V
A
V
= –100
200µs/DIV
V
IN
50mV/DIV
V
OUT
1V/DIV
2066 G58
V
S
= ±0.9V
A
V
= –100
400µs/DIV
V
IN
50mV/DIV
V
OUT
0.5V/DIV
2066 G59
V
S
= ±2.5V
A
V
= –100
200µs/DIV
V
IN
50mV/DIV
V
OUT
1V/DIV
2066 G60
V
S
= ±0.9V
A
V
= –100
400µs/DIV
V
IN
50mV/DIV
V
OUT
0.5V/DIV
2066 G61
V
S
= ±2.5V
A
V
= +1
100µs/DIV
V
IN
1V/DIV
V
OUT
1V/DIV
2066 G62
V
S
= ±0.9V
A
V
= +1
40µs/DIV
V
IN
0.5V/DIV
V
OUT
0.5V/DIV
2066 G63
V
S
= ±2.5V
A
V
= +1
100µs/DIV
V
IN
1V/DIV
V
OUT
1V/DIV
2066 G64
V
S
= ±0.9V
A
V
= +1
40µs/DIV
V
IN
0.5V/DIV
V
OUT
0.5V/DIV
2066 G65
LTC2066/LTC2067
14
Rev A
For more information www.analog.com
BLOCK DIAGRAM
PIN FUNCTIONS
OUT: Amplifier Output
–IN: Inverting Amplifier Input
+IN: Noninverting Amplifier Input
V+: Positive Power Supply. A bypass capacitor should be
used between supply pins and ground.
V
–
: Negative Power Supply. A bypass capacitor should be
used between supply pins and ground.
SHDN: Shutdown Control Pin. The SHDN pin threshold is
referenced to V–. If tied to V+, the part is enabled. If tied
to V–, the part is disabled and draws less than 170nA of
supply current per amplifier. It is recommended not to
float this pin.
Amplifier
–
+
V+
V–
V–
V+
V–
V
+
V–
V+
V–
OUT
+IN
–IN
2066 BDa
7k
7k
EMI
FILTER
Shutdown Circuit
V+
V+
V–
SHDN
10k
50nA
SHDN
2066 BDb
LTC2066/LTC2067
15
Rev A
For more information www.analog.com
Using the LTC2066/LTC2067
The LTC2066/LTC2067 are single and dual zero-drift op-
erational amplifiers with the open-loop voltage gain and
bandwidth characteristics of a conventional operational
amplifier. Advanced circuit techniques allow the LTC2066/
LTC2067 to operate continuously through its entire band-
width while self-calibrating unwanted errors.
Input Voltage Noise
Zero-drift amplifiers like the LTC2066/LTC2067 achieve
low input offset voltage and 1/f noise by heterodyning DC
and flicker noise to higher frequencies. In early zero-drift
amplifiers, this process resulted in idle tones at the self-
calibration frequency, often referred to as the chopping
frequency. These artifacts made early zero-drift amplifiers
difficult to use. The advanced circuit techniques used by
the LTC2066/LTC2067 suppress these spurious artifacts,
allowing for trouble-free use.
Input Current Noise
For applications with high source and feedback imped-
ances, input current noise can be a significant contributor
to total output noise. For this reason, it is important to
consider noise current interaction with circuit elements
placed at the amplifier’s inputs.
V
S
= 5V
V
CM
= 2.5V
FREQUENCY (Hz)
0.1
1
10
100
1k
10k
100k
1M
10
100
1k
10k
CURRENT NOISE DENSITY (fA/√
Hz
)
2066 F01
Figure1. Input Current Noise Spectrum
APPLICATIONS INFORMATION
The current noise spectrum of the LTC2066/LTC2067 is
shown in Figure1. Low input current noise is achieved
through the use of MOSFET input devices and self-calibra-
tion techniques to eliminate 1/f current noise. As with all
zero-drift amplifiers, there is an increase in current noise
at the offset-nulling frequency. This phenomenon is dis-
cussed in the Input Bias Current and Clock Feedthrough
section.
Input current noise also rises with frequency due to ca-
pacitive coupling of MOSFET channel thermal noise.
Input Bias Current and Clock Feedthrough
The input bias current of zero-drift amplifiers has differ-
ent characteristics than that of a traditional operational
amplifier. The specified input bias current is the DC aver-
age of transient currents which conduct due to the input
stage’s switching circuitry. In addition to this, junction
leakages can contribute additional input bias current at
elevated temperatures. Through careful design and the
use of an innovative boot-strap circuit the input bias cur-
rent of the LTC2066/LTC2067 does not exceed 35pA at
room and 150pA over the full temperature range. This
minimizes bias current induced errors even in high im-
pedance circuits.
Transient switching currents at the input interact with
source and feedback impedances producing error volt-
ages which are indistinguishable from a valid input signal.
The resulting error voltages are amplified by the ampli-
fier’s closed-loop gain, which acts as a filter, attenuating
frequency components above the circuit bandwidth. This
phenomenon is known as clock feedthrough and is pres-
ent in all zero-drift amplifiers. Understanding the cause
and effect of clock feedthrough is important when using
zero-drift amplifiers.
For zero-drift amplifiers, clock feedthrough is propor-
tional to source and feedback impedances, as well as the
magnitude of the transient currents. These transient cur-
rents have been minimized in the LTC2066/LTC2067 to
allow use with high source and feedback impedances.
Many circuit designs require high feedback impedances
LTC2066/LTC2067
16
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
to minimize power consumption and/or require a sensor
which is intrinsically high impedance. In these cases, a
capacitor can be used, either at the input or across the
feedback resistor, to limit the bandwidth of the closed-
loop system. Doing so will effectively filter out the clock
feedthrough signal.
Thermocouple Effects
In order to achieve accuracy on the microvolt level, ther-
mocouple effects must be considered. Any connection
of dissimilar metals forms a thermoelectric junction and
generates a small temperature-dependent voltage. Also
known as the Seebeck Effect, these thermal EMFs can be
the dominant error source in low-drift circuits.
Connectors, switches, relay contacts, sockets, resistors,
and solder are all candidates for significant thermal EMF
generation. Even junctions of copper wire from different
manufacturers can generate thermal EMFs of 200nV/°C,
which significantly exceeds the maximum drift specifica-
tion of the LTC2066/LTC2067. Figures2 and 3 illustrate
the potential magnitude of these voltages and their sen-
sitivity to temperature.
In order to minimize thermocouple-induced errors, atten-
tion must be given to circuit board layout and component
selection. It is good practice to minimize the number of
junctions in the amplifier’s input signal path and avoid con-
nectors, sockets, switches, and relays whenever possible. If
such components are required, they should be selected for
low thermal EMF characteristics. Furthermore, the number,
type, and layout of junctions should be matched for both in-
puts with respect to thermal gradients on the circuit board.
Doing so may involve deliberately introducing dummy junc-
tions to offset unavoidable junctions.
Air currents can also lead to thermal gradients and cause
significant noise in measurement systems. It is important
to prevent airflow across sensitive circuits. Doing so will
often reduce thermocouple noise substantially. A sum-
mary of techniques can be found in Figure4.
Leakage Effects
Leakage currents into high impedance signal nodes can
easily degrade measurement accuracy of sub-nanoamp
signals. High voltage and high temperature applications
are especially susceptible to these issues. Quality insula-
tion materials should be used, and insulating surfaces
should be cleaned to remove fluxes and other residues.
For humid environments, surface coating may be neces-
sary to provide a moisture barrier.
TEMPERATURE (°C)
25
MICROVOLTS REFERRED TO 25°C
1.8
2.4
3.0
2.8
2.6
2.0
2.2
1.4
1.6
0.8
1.0
0.2
0.4
30 40 45
2066 F02
1.2
0.6
035
Figure2. Thermal EMF Generated by Two Copper
Wires from Different Manufacturers
SOLDER-COPPER JUNCTION DIFFERENTIAL TEMPERATURE
SOURCE: NEW ELECTRONICS 02-06-77
0
THERMALLY PRODUCED VOLTAGE IN MICROVOLTS
0
50
40
2066 F03
–50
–100 10 20 30 50
100
SLOPE ≈ 1.5µV/°C
BELOW 25°C
SLOPE ≈ 160nV/°C
BELOW 25°C
64% SN/36% Pb
60% Cd/40% SN
Figure3. Solder-Copper Thermal EMFs
LTC2066/LTC2067
17
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
RG**
RF
RF§
RL§
NC
‡
2066 F04
HEAT SOURCE/
POWER DISSIPATOR
THERMAL
GRADIENT
MATCHING RELAY
RELAY
* CUT SLOTS IN PCB FOR THERMAL ISOLATION.
** INTRODUCE DUMMY JUNCTIONS AND COMPONENTS TO OFFSET UNAVOIDABLE JUNCTIONS OR CANCEL THERMAL EMFs.
† ALIGN INPUTS SYMMETRICALLY WITH RESPECT TO THERMAL GRADIENTS.
‡ INTRODUCE DUMMY TRACES AND COMPONENTS FOR SYMMETRICAL THERMAL HEAT SINKING.
§ LOADS AND FEEDBACK CAN DISSIPATE POWER AND GENERATE THERMAL GRADIENTS. BE AWARE OF THEIR THERMAL EFFECTS.
# COVER CIRCUIT TO PREVENT AIR CURRENTS FROM CREATING THERMAL GRADIENTS.
+
–
VIN
VTHERMAL
+
–
VTHERMAL
LTC2066
+IN OUT
–IN
RG
**
*#
#
†
Figure4. Techniques for Minimizing Thermocouple-Induced Errors
Figure5. Example Layout of Inverting Amplifier with Leakage Guard Ring
‡
RF
OUT VOUT
V–V–
+IN
V+
V+
–IN
GUARD
RING
HIGH-Z
SENSOR
NO SOLDER MASK
OVER GUARD RING
LEAKAGE
CURRENT
VBIAS
‡ NO LEAKAGE CURRENT, V–IN = V+IN
§ AVOID DISSIPATING SIGNIFICANT AMOUNTS OF POWER IN THIS RESISTOR.
IT WILL GENERATE THERMAL GRADIENTS WITH RESPECT TO THE INPUT
PINS AND LEAD TO THERMOCOUPLE-INDUCED ERROR. THERMALLY
ISOLATE OR ALIGN WITH INPUTS IF RESISTOR WILL CAUSE HEATING.
§
2066 F05
+
–
GUARD RING
LTC2066
LEAKAGE
CURRENT
LEAKAGE CURRENT IS ABSORBED BY GROUND INSTEAD OF
CAUSING A MEASUREMENT ERROR.
VOUT
V+
V–
HIGH-Z SENSOR
RF
VBIAS
+
–
VIN RIN
LTC2066/LTC2067
18
Rev A
For more information www.analog.com
rent available to take the system up to nominal voltages.
In other cases, this transient power-up current will lead
to added power loss in duty-cycled applications.
A way to quantify the transient current loss is to integrate
the supply current during power-up to examine the total
charge loss. If there were no additional transient current,
the integrated supply current would appear as a smooth,
straight line with a slope equal to the DC supply cur-
rent of the part. Any deviation from a straight line indi-
cates additional transient current that is drawn from the
supply. The LTC2066/LTC2067 have been designed to
minimize this charge loss during power-up so that power
can be conserved in duty-cycled applications. Figure6
shows the integrated supply current (i.e. charge) of the
LTC2066 during power-up. Likewise, Figure7 shows the
charge loss due to enabling and disabling the part via
the SHDN pin.
1V/µs V
–
EDGE RATE
V
+
= 5V
500µs/DIV
V
–
5V/DIV
V
OUT
2V/DIV
Q
V+
10nC/DIV
2066 F06
Figure6. LTC2066 Charge Loss During Power-Up
500µs/DIV
V
SHDN
5V/DIV
V
OUT
2V/DIV
Q
V+
10nC/DIV
2066 F07
Figure7. LTC2066 Charge Loss Due to
Enabling and Disabling via SHDN Pin
APPLICATIONS INFORMATION
Board leakage can be minimized by encircling the input
connections with a guard ring operated at a potential very
close to that of the inputs. The ring must be tied to a low
impedance node. For inverting configurations, the guard
ring should be tied to the potential of the positive input
(+IN). For noninverting configurations, the guard ring
should be tied to the potential of the negative input (–IN).
In order for this technique to be effective, the guard ring
must not be covered by solder mask. Ringing both sides
of the printed circuit board may be required. See Figure5
for an example of proper layout.
Shutdown Mode
The LTC2066 in the SC70 package and the LTC2067 in
the DFN package feature a shutdown mode for low-power
applications. In the OFF state, each amplifier draws less
than 170nA of supply current and the outputs present a
high impedance to external circuitry.
Shutdown operation is accomplished by tying SHDN
below VL. If the shutdown feature is not required, it is
recommended that SHDN be tied to V
+
. A current source
pulls the SHDN pin high to keep the amplifier in the ON
state when the pin is floated, however this may not be
reliable at elevated temperatures due to board leakage
(see SHDN Circuit Block Diagram, page 14). For opera-
tion in noisy environments, a capacitor between SHDN
and V+ is recommended to prevent noise from changing
the shutdown state. When there is a danger of SHDN
being pulled beyond the supply rails, resistance in series
with the SHDN pin is recommended to limit the resulting
current.
Start-Up Characteristics
Micropower op amps are often not micropower during
start-up, which can cause problems when used on low
current supplies. Large transient currents can conduct
during power-up until the internal bias nodes settle to
their final values. A large amount of current can be drawn
from the supplies during this transient, which can sustain
for several milliseconds in the case of a micropower part.
In the worst case, there may not be enough supply cur-
LTC2066/LTC2067
19
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
There are benefits when the SHDN pin is used to disable
and enable the part in duty-cycled applications, rather
than powering down the external supply voltage (V+).
Powering up and powering down the external supply will
tend to waste charge due to charging and discharging the
external decoupling capacitors. For these power-cycled
applications, a relay or MOS device can be located after
the decoupling capacitors to alleviate this; however there
are drawbacks to this approach. The LTC2066 draws an
initial charge of approximately 3nC when powered up.
This recurring charge loss is unavoidable in power-cycled
applications. Additionally, if the supply ramp rate exceeds
0.4V/µs, an internal transient ESD clamp will trigger, con-
ducting additional current from V+ to V–. This will waste
charge and can make insignificant any gain that may
have been expected by power-cycling the supply. Figure8
shows the charge loss at power-up.
The shutdown pin can be used to overcome these limita-
tions in duty-cycled applications. The typical charge loss
transitioning into and out of shutdown is only 2.3nC.
Since the supply is not transitioned, the external decou-
pling capacitors do not draw charge from the supply.
SUPPLY EDGE RATE (V/µs)
0.1
1
2
1
10
100
0.1% SETTLED POINT (nC)
CHARGE CONSUMED TO
2066 F08
Figure8. LTC2066 Power-Up Charge vs Supply Edge Rate
Gas Sensor
This low power precision gas sensor circuit operates in
an oxygen level range of 0% to 30%, with a nominal out-
put of 1V in normal atmospheric oxygen concentrations
(20.9%) when the gas sensor has been fully initialized.
Total active power consumption is less than 10.1μA on a
single rail supply.
Since this gas sensor produces 100μA in a normal oxygen
environment and requires a 100Ω load resistor, the result-
ing input signal is typically around 10mV. The LTC2066’s
rail-to-rail input means no additional DC level shifting is
necessary, all the way down to very low oxygen concen-
trations.
Due to the extremely low input offset voltage of the
LTC2066, which is 1μV typically and 5μV maximum, it is
possible to gain up the mV-scale input signal substantially
without introducing significant error. In the configuration
shown in Figure9, with a noninverting gain of 101V/V, the
worst-case input offset results in a maximum of 0.5mV
offset on the 1V output, or 0.05% error.
Although the 100kΩ resistor in series with the gas sen-
sor does not strictly have the same precision requirement
as the 10MΩ and 100kΩ resistors that set the gain, it is
important to use a similar resistor at both input terminals.
This helps to minimize additional offset voltage at the inputs
due to thermocouple effects and bias current, hence the
similar0.1% precision requirement.
Figure9. Micropower Precision Oxygen Sensor
100k*
0.1%
100Ω
0.1%
100k
0.1%
10M
0.1%
OXYGEN SENSOR
CITY TECHNOLOGY
40XV
VOUT = 1V IN AIR
ISUPPLY = 7.5µA (ENABLED)
90nA (SHUTDOWN)
www.citytech.com
VSHDN
*RESISTOR CANCELS OUT PARASITIC SEEBECK EFFECT VOLTAGE
2066 F09
–
+
1.8V
LTC2066
LTC2066/LTC2067
20
Rev A
For more information www.analog.com
OUT
2066 F10
–
+
RFB
1.58M
RTD
1k
100k
10k
10k
100k
LT5400-3
GND
LT6656-2.048
R2
11k
110k
0.1%
±2ppm/°C
C2
10µF
VOUT SCALE 10mV/°C
1V AT 25°C ROOM TEMP
ISUPPLY = 43µA
VISHAY PTS SERIES
1kΩ PtRTD, CLASS F0.3
PTS12061B1K00P100
www.vishay.com
C1
0.1µF
2.6V ≤ VSUPPLY ≤ 18V
+
–
OUTIN
LTC2066
131:1 VOLTAGE DIVIDER
Figure10. RTD Sensor
APPLICATIONS INFORMATION
RTD Sensor
This low power platinum resistance temperature detector
(RTD) sensor circuit draws only 43μA total supply cur-
rent on a minimum 2.6V rail, and is accurate to within
±1°C at room temperature, including all error intrinsic
to the Vishay PTS Class F0.3 Variant RTD. It covers the
temperature range from –40°C to 85°C in 10mV/°C incre-
ments and produces an output of 1V at nominal room
temperature of 25°C.
The LTC2066’s extremely low typical offset of 1μV and
typical input bias current of 5pA allows for the use of a
very low excitation current in the RTD. Thus, self-heating
is negligible, improving accuracy.
The LT5400-3, B-grade, is used to provide a ±0.025%
matched resistor network that is effectively a precision
131:1 voltage divider. This precision divider forms one
half of a bridge circuit, with the 0.1% 110kΩ and RTD in
the other branch. Note that the 110kΩ’s precision require-
ment is to ensure matching with the RTD. The 11kΩ R2
serves to provide a DC offset for the entire bridge so that
the output is 1V at room temperature. Since bridge imbal-
ances can lead to error, it is recommended to minimize
the length of the leads connecting the RTD to reduce ad-
ditional lead resistance.
The LT6656-2.048 reference helps create a known excita-
tion current in the RTD at each temperature of operation,
and also acts as a supply for the LTC2066, all while using
less than 1μA itself. The LT6656 can accept input voltages
anywhere between 2.6V and 18V, allowing for flexibility
in selection of supply voltage while maintaining a fixed
output range. The LT6656 reference can easily source
the 43μA required to run the entire circuit, thanks to the
LTC2066’s 10μA maximum supply current and ability to
handle microvolt signals produced by the RTD under low
excitation current.
Care should be taken to minimize thermocouple effects by
preventing significant thermal gradients between the two
op amp inputs. It is also important to choose feedback
and series resistors that are low-tempco to minimize error
due to drift over the entire temperature range.
LTC2066/LTC2067
21
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
High Side Current Sense
This micropower precision LTC2066 high side current
sense circuit measures currents from 100μA to 250mA
over a 4.5V to 90V input voltage range.
The output of this circuit is:
VOUT =RLOAD • RSENSE
R
IN
ISENSE =10 •ISENSE
The LTC2066’s low typical input offset voltage of 1μV and
low input bias current of 5pA contribute output errors
that are much smaller than the error due to precision
limitations of the resistors used. Thus, output accuracy
is mainly set by the accuracy of the resistors RSENSE, RIN,
and RLOAD. R1 helps cancel out parasitic Seebeck effect
voltages at –IN by balancing with an identical voltage
at+IN.
The LT1389-4.096 reference, along with the bootstrap
circuit composed of M2, R3, and D1, establishes a very
low power isolated 3V rail that protects the LTC2066 from
reaching its absolute maximum voltage of 5.5V while al-
lowing for much higher input voltages.
Since the LTC2066’s gain-bandwidth product is 100kHz,
it is recommended to use this circuit to measure currents
that do not change faster than 10kHz. Note that the output
filter as drawn will limit the frequency to 1.5Hz, which
optimizes for lowest noise.
VOUT = 10 • ISENSE
1mV TO 2.5V
VIN
4.5V TO 90V
2066 F11
–
+
R1
49.9Ω
0.1%
D1
1N4148
REF
LT1389-4.096
C1
3.3µF
R3
499k
RSENSE
0.1Ω
RLOAD
5k
0.1%
C4
22µF
C3
100nF
BSP322P
M1
RIN
49.9Ω
0.1%
C2*
10µF
BSP322P
M2
ISENSE
100µA to 250mA
LOAD
LTC2066
*C2 MUST WITHSTAND
VOLTAGES UP TO VIN
Figure11. High Side Current Sense
LTC2066/LTC2067
22
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
R6
909k 2066 F12
–
+
1/2 LTC2067
R2
909k
R1
100k
R5
100k
1.5V
–1.5V
1.5V
–1.5V
+
–
1/2 LTC2067
OUT
R3
100Ω
R4
100Ω
IN
Parallel LTC2067 Amplifiers to Reduce Noise by √2
Precision, Micropower Carbon Monoxide Detector
R5
35.7k
C4
100nF
2.5V
2.5V
OUT
INPUT RANGE:
0ppm TO 500ppm CO
TYPICAL GAIN:
2.5mV/ppm CO
OUTPUT:
1.7V (TYP)
2.0V (MAX) AT 500ppm CO
4CM CARBON MONOXIDE SENSOR
CITY TECHNOLOGY
70nA/ppm CO TYP
4CM COUNTER ELECTRODE (CE)
SELF-BIASES BELOW WE POTENTIAL
VWE – VCE = –0.3V TO –0.4V TYP
2066 F13
+
–
1/2 LTC2067 C5
10µF
R7
100k
R8
100k
C3
100nF
R6
402k
RBURDEN
5Ω
2.5V
R4
1M
J1
MMBFJ270
R3
35.7k
C2
100nF
2.5V
RECE
WE
+
–
1/2 LTC2067
R2
100k
C1
100nF
R1
402k
2.5V
4CM
LTC2066/LTC2067
23
Rev A
For more information www.analog.com
PACKAGE DESCRIPTION
1.15 – 1.35
(NOTE 4)
1.80 – 2.40
0.15 – 0.30
6 PLCS (NOTE 3)
SC6 SC70 1205 REV B
1.80 – 2.20
(NOTE 4)
0.65 BSC
PIN 1
0.80 – 1.00
1.00 MAX
0.00 – 0.10
REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE INDEX AREA
7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70
8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB
2.8 BSC
0.47
MAX
0.65
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.8 REF
1.00 REF
INDEX AREA
(NOTE 6)
0.10 – 0.18
(NOTE 3)
0.26 – 0.46
GAUGE PLANE
0.15 BSC
0.10 – 0.40
SC6 Package
6-Lead Plastic SC70
(Reference LTC DWG # 05-08-1638 Rev B)
LTC2066/LTC2067
24
Rev A
For more information www.analog.com
PACKAGE DESCRIPTION
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S5 TSOT-23 0302
PIN ONE
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
LTC2066/LTC2067
25
Rev A
For more information www.analog.com
PACKAGE DESCRIPTION
MSOP (MS8) 0213 REV G
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ±0.0508
(.004 ±.002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ±0.152
(.193 ±.006)
8765
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.52
(.0205)
REF
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ±.0015)
TYP
0.65
(.0256)
BSC
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev G)
LTC2066/LTC2067
26
Rev A
For more information www.analog.com
PACKAGE DESCRIPTION
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV C 0310
0.25 ±0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.70 ±0.05
3.55
±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
LTC2066/LTC2067
27
Rev A
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog De-
vices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications sub-
ject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 07/18 Adding LTC2067 to data sheet All Pages
LTC2066/LTC2067
28
Rev A
For more information www.analog.com
D16885-0-7/18(A)
www.analog.com
ANALOG DEVICES, INC. 2017-2018
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VOUT = VREF/2 ±ILOAD × RSENSE × GAIN
GAIN = 2M/14k
12V
2066 TA03
–
+
VREF
2M
14k
14k
2M2M 2M2M
RSENSE
10mΩ
LT6656-3
10µF
BAT
>3.1V
10µF
ILOAD CURRENT
TO BE MEASURED
(BI-DIRECTIONAL)
0.1% RESISTORS TO MAINTAIN OFFSET ACCURACY
LTC2066
IN OUT