EMIF09-SD01F3 9-line IPADTM, EMI filter and ESD protection Features 9-line EMI low-pass filter and ESD protection High efficiency in EMI filtering Lead-free package 400 m pitch Very low PCB space occupation: < 4 mm2 Very thin package: 0.6 mm High reliability offered by monolithic integration Reduction of parasitic elements thanks to CSP integration Flip Chip 24 bumps Figure 1. Pin layout (bump side) 5 4 3 2 1 Complies with the following standards A B IEC61000-4-2 level 4 on external pins: - 15 kV (air discharge) - 8 kV (contact discharge) C D IEC61000-4-2 level 2 on internal pins: - 2 kV (air discharge) - 2 kV (contact discharge) E MIL STD 883F - Method 3015.7 Class 3 Application Secure digital memory card in mobile phones and communication systems Description The EMIF09-SD01F3 is a highly integrated array designed to suppress EMI/RFI noise for secure digital memory cards. The EMIF09-SD01F3 is in a Flip Chip package to offer space saving and high RF performance. This low-pass filter includes ESD protection circuitry, which prevents damage to the protected device when subjected to ESD surges up 15 kV. This filter also has a low line capacitance to be compatible with high data rate signals. TM: IPAD is a trademark of STMicroelectronics. April 2008 Rev 4 1/9 www.st.com Characteristics 1 EMIF09-SD01F3 Characteristics Figure 2. Device configuration VSD R15 R14 R12 R13 R11 DAT3_PU CLK SDCLK R1 CMD SDCMD R2 DATA0 SDDATA0 R3 DATA1 SDDATA1 R4 DATA2 SDDATA2 R5 DATA3 SDDATA3 R6 CD SDCD R7 WP SDWP R8 WP+CD R21 DAT3_PD GND_H Table 1. SDWP+CD R9 GND_C Pin-signal attribution Pin Description Pin Description Pin Description Pin Description Pin Description A1 DATA2 B1 CD C1 DAT3_PD D1 WP+CD E1 DATA1 A2 DATA3 B2 CMD C2 WP D2 CLK E2 DATA0 A3 GND_H B3 C3 DAT3_PU D3 GND_C E3 GND_C A4 SDDATA2 B4 SDCD C4 SDWP D4 SDWP+CD E4 SDDATA1 A5 SDDATA3 B5 SDCMD C5 VSD D5 SDCLK E5 SDDATA0 Table 2. Absolute ratings (limiting values) Symbol Parameter VPP Internal pins (A1, B1, C1, D1, E1, A2, B2, C2, D2, E2, C3) ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge External pins (A4, B4, C4, D4, E4, A5, B5, C5, D5, E5) ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge 15 8 Junction temperature 125 C Tj Value 2 2 Unit kV Top Operating temperature range -30 to + 85 C Tstg Storage temperature range -55 to 150 C GND bumps (GND_H and GND_C - A3, D3 and E3) must be connected to ground on the printed circuit board for ESD testing and RF measurements. 2/9 EMIF09-SD01F3 Characteristics Table 3. Electrical characteristics (Tamb = 25 C) Symbol Parameters VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current RI/O Series resistance between input and output Cline Input capacitance per line Symbol Test conditions VBR IR = 1 mA IRM VRM = 5 V per line I IPP VCLVBR VRM IR IRM V IRM IR VRMVBR VCL IPP Min Typ 6 50 Max Unit 20 V 200 nA R1, R2, R3, R4, Tolerance 20% R5, R6, R7, R8, R9 40 R11, R12, Tolerance 30% R13, R14 50 k R15 Tolerance 30% 15 k R21 Tolerance 30% 470 k Cline Vline = 0 V, VOSC = 30 mV, F = 1 MHz (under zero light conditions) 20 pF 3/9 Characteristics Figure 3. EMIF09-SD01F3 S21(dB) all lines attenuation measurement Figure 4. dB Analog cross talk measurement dB 0.00 0.00 -10.00 -10.00 -20.00 -30.00 -20.00 -40.00 -30.00 -50.00 -60.00 -40.00 F (Hz) -50.00 100.0k 1.0M data0 data2 Figure 5. 10.0M F (Hz) -70.00 100.0M -80.00 100.0k 1.0G 1.0M data1 data3 10.0M 100.0M 1.0G data0_data1 Digital crosstalk measurement Figure 6. ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input (VIN) and on one output (VOUT) Output Line 2 200mV/d Vexternal=20V/d Input Line 1 1V/d Vinternal =10V/d 10ns/d 5Gs/s Figure 7. 100ns/d ESD response to IEC 61000-4-2 Figure 8. (-15 kV air discharge) on one input (VIN) and on one output (VOUT) Line capacitance versus applied voltage Cline (pF) 25 Vexternal=20V/d F = 1 MHz VOSC = 30 mV Tj = 25C 20 15 10 Vinternal =10V/d 100ns/d 5 Vline (V) 0 0 4/9 2 4 6 8 10 12 14 EMIF09-SD01F3 2 Application information Application information Figure 9. Aplac model data0 Lbump Rbump Rline MODEL = D1 Rbump Lbump sddata0 MODEL = D2 Rsub MODEL = D3 MODEL = D4 Rbump Rbump Rbump Lbump Lbump Lbump Rgnd Rgnd Rgnd Lgnd Lgnd Lgnd Figure 10. Aplac model variables Variables aplacvar Rline 40 aplacvar C_d1 14.5p aplacvar C_d2 6.5p aplacvar C_d3 303p aplacvar C_d4 14.5p aplacvar Lbump 43pH aplacvar Rbump 17m aplacvar Cbump 150f aplacvar Lgnd 150pH aplacvar Rgnd 10m aplacvar Rsub 5 Diode D1 BV=7 IBV=1m CJO=C_d1 M=0.28 RS=1.13 VJ=0.6 TT=100n Diode D2 BV=7 IBV=1m CJO=C_d2 M=0.28 RS=0.8 VJ=0.6 TT=100n Diode D3 BV=7 IBV=1m CJO=C_d3 M=0.28 RS=0.37 VJ=0.6 TT=100n Diode D4 BV=7 IBV=1m CJO=C_d4 M=0.28 RS=1.13 VJ=0.6 TT=100n 5/9 Ordering information scheme 3 EMIF09-SD01F3 Ordering information scheme Figure 11. Ordering information scheme EMIF yy - xx zz F3 EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10 (pF) or 2 letters = application 2 digits = version Package F = Flip Chip 3 = Lead-free, pitch = 400 m, bump = 255 m 4 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 12. Package dimensions 185 m 10 m 1.97 mm 30 m 6/9 1.97 mm 30 m 255 m 40 185 m 10 m 400 m 40 400 m 40 605 m 55 EMIF09-SD01F3 Ordering information Figure 13. Footprint Figure 14. Marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) Copper pad Diameter: 220 m recommended 260 m maximum E Solder mask opening: 300 m minimum x x z y ww Solder stencil opening : 220 m recommended Figure 15. Flip Chip tape and reel specifications Dot identifying Pin A1 location 1.75 0.1 O 1.5 0.1 4 0.1 3.5 0.1 2.11 ST E xxz yww 2.11 4 0.1 User direction of unreeling All dimensions in mm Note: ST E xxz yww ST E xxz yww 8 0.3 2.11 0.69 0.05 More information is available in the application note: AN2348: "STMicroelectronics 400 micro-metre Flip Chip: Package description and recommendation for use" AN1751: EMI Filters: Recommendations and measurements 5 Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF09-SD01F3 GZ Flip Chip 5.2 mg 5000 Tape and reel (7") 7/9 Revision history 6 EMIF09-SD01F3 Revision history Table 5. 8/9 Document revision history Date Revision Changes 19-Oct-2005 1 Initial release. 09-Feb-2006 2 Tape cavity dimensions added in Figure 13. Other graphics improved. 22-Mar-2006 3 Reformatted to current standard. Typical and maximum values updated for IRM in Electrical characteristics, page 3. 28-Apr-2008 4 Updated ECOPACK statement. Updated Figure 11, Figure 12 and Figure 15. Reformatted to current standards. EMIF09-SD01F3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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