Single-Channel, 1024-Position,
1% R-Tolerance Digital Potentiometer
AD5293
Rev. D
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FEATURES
Single-channel, 1024-position resolution
20 kΩ, 50 kΩ, and 100 kΩ nominal resistance
Calibrated 1% nominal resistor tolerance (resistor
performance mode)
Rheostat mode temperature coefficient: 35 ppm/°C
Voltage divider temperature coefficient: 5 ppm/°C
Single-supply operation: 9 V to 33 V
Dual-supply operation: ±9 V to ±16.5 V
SPI-compatible serial interface
Wiper setting readback
APPLICATIONS
Mechanical potentiometer replacement
Instrumentation: gain and offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, and time constants
Programmable power supply
Low resolution DAC replacements
Sensor calibration
FUNCTIONAL BLOCK DIAGRAM
A
W
B
RDAC
REGISTER
10
SERIAL
INTERFACE
SYNC
SCLK
DIN
POWER-ON
RESET
VLOGIC
SDO
EXT_CAP
V
DD
VSS GND
AD5293
RESET
RDY
07675-001
Figure 1.
GENERAL DESCRIPTION
The AD5293 is a single-channel, 1024-position digital
potentiometer1 with a <1% end-to-end resistor tolerance error.
The AD5293 performs the same electronic adjustment function as
a mechanical potentiometer with enhanced resolution, solid state
reliability, and superior low temperature coefficient performance.
This device is capable of operating at high voltages and supporting
both dual-supply operation at ±10.5 V to ±15 V and single-supply
operation at 21 V to 30 V.
The AD5293 offers guaranteed industry-leading low resistor
tolerance errors of ±1% with a nominal temperature coefficient
of 35 ppm/°C. The low resistor tolerance feature simplifies open-
loop applications as well as precision calibration and tolerance
matching applications.
The AD5293 is available in a compact 14-lead TSSOP package.
The part is guaranteed to operate over the extended industrial
temperature range of −40°C to +105°C.
1 In this data sheet, the terms digital potentiometer and RDAC are used
interchangeably.
AD5293
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Features ...............................................................................................1
Applications........................................................................................1
Functional Block Diagram ...............................................................1
General Description..........................................................................1
Revision History ................................................................................2
Specifications......................................................................................3
Electrical Characteristics—20 kΩ Versions...............................3
Resistor Performance Mode Code Range—20 kΩ Versions ...4
Electrical Characteristics—50 kΩ and 100 kΩ Versions..........5
Resistor Performance Mode Code Range—50 kΩ and 100 kΩ
Versions...........................................................................................6
Interface Timing Specifications...................................................7
Timing Diagrams...........................................................................8
Absolute Maximum Ratings.............................................................9
Thermal Resistance .......................................................................9
ESD Caution...................................................................................9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Test Circuits..................................................................................... 17
Theory of Operation ...................................................................... 18
Serial Data Interface................................................................... 18
Shift Register ............................................................................... 18
RDAC Register............................................................................ 18
Write Protection ......................................................................... 18
Basic Operation .......................................................................... 18
Shutdown Mode.......................................................................... 18
Reset ............................................................................................. 19
Resistor Performance Mode...................................................... 19
SDO Pin and Daisy-Chain Operation..................................... 19
RDAC Architecture.................................................................... 20
Programming the Variable Resistor......................................... 20
Programming the Potentiometer Divider ............................... 21
EXT_CAP Capacitor.................................................................. 21
Terminal Voltage Operating Range.......................................... 21
Applications Information .............................................................. 22
High Voltage DAC...................................................................... 22
Programmable Voltage Source with Boosted Output............ 22
High Accuracy DAC .................................................................. 22
Variable Gain Instrumentation Amplifier............................... 22
Audio Volume Control .............................................................. 23
Outline Dimensions ....................................................................... 24
Ordering Guide........................................................................... 24
REVISION HISTORY
3/11—Rev. C to Rev. D
Changes to Table 1, Endnote 2 ................................................................4
Changes to Table 3, Endnote 2........................................................ 6
9/10—Rev. B to Rev. C
Added CPOL = 0, CPHA = 1 to Figure 3 and Figure 4 Captions.....8
Changes to SDO Pin and Daisy-Chain Operation Section....... 19
3/10—Rev. A to Rev. B
Changes to Resistor Noise Density Conditions (Table 3) ........... 6
12/09—Rev. 0 to Rev. A
Added 50 kΩ and 100 kΩ Specifications.........................Universal
Changes to Features Section............................................................ 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Added Table 3; Renumbered Sequentially .................................... 5
Added Table 4.................................................................................... 6
Changes to Table 5............................................................................ 7
Changes to Table 6 and Note 1, Table 7......................................... 9
Changes to Typical Performance Characteristics Section......... 11
Changes to Programming the Variable Resistor Section .......... 20
Changes to Programming the Potentiometer
Divider Section ............................................................................... 21
Changes to Ordering Guide Section ............................................ 24
4/09—Revision 0: Initial Version
AD5293
Rev. D | Page 3 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—20 kΩ VERSIONS
VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS,
−40°C < TA < +105°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS,
RHEOSTAT MODE
Resolution N 10 Bits
Resistor Differential Nonlinearity2 R-DNL RWB −1 +1 LSB
Resistor Integral Nonlinearity2 R-INL |VDD − VSS | = 26 V to 33 V −2 +2 LSB
R-INL |VDD − VSS | = 21 V to 26 V −3 +3 LSB
Nominal Resistor Tolerance
(R-Perf Mode)3
∆RAB/RAB See Table 2 −1 ±0.5 +1 %
Nominal Resistor Tolerance
(Normal Mode)
∆RAB/RAB ±7 %
Resistance Temperature Coefficient4 (∆RAB/RAB)/∆T × 106 35 ppm/°C
Wiper Resistance RW 60 100 Ω
DC CHARACTERISTICS,
POTENTIOMETER DIVIDER MODE
Resolution N 10 Bits
Differential Nonlinearity5 DNL −1 +1 LSB
Integral Nonlinearity5 INL −1.5 +1.5 LSB
Voltage Divider Temperature
Coefficient4
(∆VW/VW)/∆T × 106 Code = half scale 5 ppm/°C
Full-Scale Error VWFSE Code = full scale −8 0 LSB
Zero-Scale Error VWZSE Code = zero scale 0 8 LSB
RESISTOR TERMINALS
Terminal Voltage Range6 V
A, VB, VW V
SS V
DD V
Capacitance A, Capacitance B4 C
A, CB f = 1 MHz, measured to GND,
code = half-scale
85 pF
Capacitance W4 C
W f = 1 MHz, measured to GND,
code = half-scale
65 pF
Common-Mode Leakage Current ICM V
A = VB = VW ±1 nA
DIGITAL INPUTS JEDEC compliant
Input Logic High VIH V
LOGIC = 2.7 V to 5.5 V 2.0 V
Input Logic Low VIL V
LOGIC = 2.7 V to 5.5 V 0.8 V
Input Current IIL V
IN = 0 V or VLOGIC ±1 μA
Input Capacitance4 C
IL 5 pF
DIGITAL OUTPUTS (SDO and RDY)
Output High Voltage VOH R
PULL_UP = 2.2 kΩ to VLOGIC V
LOGIC − 0.4 V
Output Low Voltage VOL R
PULL_UP = 2.2 kΩ to VLOGIC GND + 0.4 V
Tristate Leakage Current −1 +1 μA
Output Capacitance4 C
OL 5 pF
POWER SUPPLIES
Single-Supply Power Range VDD V
SS = 0 V 9 33 V
Dual-Supply Power Range VDD/VSS ±9 ±16.5 V
Positive Supply Current IDD V
DD/VSS = ±16.5 V 0.1 2 μA
Negative Supply Current ISS V
DD/VSS = ±16.5 V −2 −0.1 μA
Logic Supply Range VLOGIC 2.7 5.5 V
Logic Supply Current ILOGIC V
LOGIC = 5 V; VIH = 5 V or VIL = GND 1 10 μA
Power Dissipation7 P
DISS V
IH = 5 V or VIL = GND 8 110 μW
Power Supply Rejection Ratio4 PSSR ∆VDD/∆VSS = ±15 V ± 10% 0.103 %/%
AD5293
Rev. D | Page 4 of 24
Parameter Symbol Conditions Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS4, 8
Bandwidth BW −3 dB 520 kHz
Total Harmonic Distortion THDW V
A = 1 V rms, VB = 0 V, f = 1 kHz, −93 dB
VW Settling Time tS VA = 30 V, VB = 0 V, ±0.5 LSB error
band, initial code = zero scale
Code = full scale, R-normal mode 750 ns
Code = full scale, R-perf mode 2.5 μs
Code = half scale, R-normal mode 2.5 μs
Code = half scale, R-perf mode 5 μs
Resistor Noise Density eN_WB RWB = 10 kΩ, TA = 25°C,
0 kHz to 200 kHz
10 nV/√Hz
1 Typicals represent average readings at 25°C; VDD = +15 V, VSS = −15 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between RWB at Code 0x00B to Code 0x3FF or between RWA at Code 0x3F3 to
Code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode with
a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V.
3 The terms resistor performance mode and R-perf mode are used interchangeably.
4 Guaranteed by design; not subject to production test.
5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal
adjustment.
7 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC).
8 All dynamic characteristics use VDD = +15 V, VSS = −15 V, and VLOGIC = 5 V.
RESISTOR PERFORMANCE MODE CODE RANGE—20 kΩ VERSIONS
Table 2.
RAB = 20 kΩ
|VDD − VSS| = 30 V to 33 V |VDD − VSS| = 26 V to 30 V |VDD − VSS| = 22 V to 26 V |VDD − VSS| = 21 V to 22 V
Resistor
Tolerance
per Code RWB R
WA R
WB R
WA R
WB R
WA R
WB R
WA
1% R-Tolerance From 0x15E
to 0x3FF
From 0x000
to 0x2A1
From 0x1F4
to 0x3FF
From 0x000
to 0x20B
From 0x1F4
to 0x3FF
From 0x000
to 0x20B
N/A N/A
2% R-Tolerance From 0x8C
to 0x3FF
From 0x000
to 0x373
From 0xB4
to 0x3FF
From 0x000
to 0x34B
From 0xFA
to 0x3FF
From 0x000
to 0x305
From 0xFA
to 0x3FF
From 0x000
to 0x305
3% R-Tolerance From 0x5A
to 0x3FF
From 0x000
to 0x3A5
From 0x64
to 0x3FF
From 0x000
to 0x39B
From 0x78
to 0x3FF
From 0x000
to 0x387
From 0x78
to 0x3FF
From 0x000
to 0x387
AD5293
Rev. D | Page 5 of 24
ELECTRICAL CHARACTERISTICS—50 kΩ AND 100 kΩ VERSIONS
VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS,
−40°C < TA < +105°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS,
RHEOSTAT MODE
Resolution N 10 Bits
Resistor Differential Nonlinearity2 R-DNL RWB −1 +1 LSB
Resistor Integral Nonlinearity2 R-INL −2 +2 LSB
Nominal Resistor Tolerance
(R-Perf Mode)3
∆RAB/RAB See Table 4 −1 ±0.5 +1 %
Nominal Resistor Tolerance
(Normal Mode)
∆RAB/RAB ±20 %
Resistance Temperature Coefficient4 (∆RAB/RAB)/∆T × 106 35 ppm/°C
Wiper Resistance RW 60 100 Ω
DC CHARACTERISTICS,
POTENTIOMETER DIVIDER MODE
Resolution N 10 Bits
Differential Nonlinearity5 DNL −1 +1 LSB
Integral Nonlinearity5 INL −1.5 +1.5 LSB
Voltage Divider Temperature
Coefficient4
(∆VW/VW)/∆T × 106 Code = half scale 5 ppm/°C
Full-Scale Error VWFSE Code = full scale −8 +1 LSB
Zero-Scale Error VWZSE Code = zero scale 0 8 LSB
RESISTOR TERMINALS
Terminal Voltage Range6 V
A, VB, VW V
SS V
DD V
Capacitance A, Capacitance B4 C
A, CB f = 1 MHz, measured to GND,
code = half-scale
85 pF
Capacitance W4 C
W f = 1 MHz, measured to GND,
code = half-scale
65 pF
Common-Mode Leakage Current ICM V
A = VB = VW ±1 nA
DIGITAL INPUTS JEDEC compliant
Input Logic High VIH V
LOGIC = 2.7 V to 5.5 V 2.0 V
Input Logic Low VIL V
LOGIC = 2.7 V to 5.5 V 0.8 V
Input Current IIL V
IN = 0 V or VLOGIC ±1 μA
Input Capacitance4 C
IL 5 pF
DIGITAL OUTPUTS (SDO and RDY)
Output High Voltage VOH R
PULL_UP = 2.2 kΩ to VLOGIC V
LOGIC − 0.4 V
Output Low Voltage VOL R
PULL_UP = 2.2 kΩ to VLOGIC GND + 0.4 V
Tristate Leakage Current −1 +1 μA
Output Capacitance4 C
OL 5 pF
POWER SUPPLIES
Single-Supply Power Range VDD V
SS = 0 V 9 33 V
Dual-Supply Power Range VDD/VSS ±9 ±16.5 V
Positive Supply Current IDD V
DD/VSS = ±16.5 V 0.1 2 μA
Negative Supply Current ISS V
DD/VSS = ±16.5 V −2 −0.1 μA
Logic Supply Range VLOGIC 2.7 5.5 V
Logic Supply Current ILOGIC V
LOGIC = 5 V; VIH = 5 V or VIL = GND 1 10 μA
Power Dissipation7 P
DISS V
IH = 5 V or VIL = GND 8 110 μW
Power Supply Rejection Ratio4 PSSR ∆VDD/∆VSS = ±15 V ± 10%
R
AB = 50 kΩ 0.039 %/%
R
AB = 100 kΩ 0.021 %/%
AD5293
Rev. D | Page 6 of 24
Parameter Symbol Conditions Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS4, 8
Bandwidth BW −3 dB kHz
R
AB = 50 kΩ 210
R
AB = 100 kΩ 105
Total Harmonic Distortion THDW V
A = 1 V rms, VB = 0 V, f = 1 kHz
R
AB = 50 kΩ −101 dB
R
AB = 100 kΩ −106 dB
VW Settling Time tS VA = 30 V, VB = 0 V, ±0.5 LSB error
band, initial code = zero scale
Code = full scale, R-normal mode 750 ns
Code = full scale, R-perf mode 2.5 μs
Code = half scale, R-normal mode,
RAB = 50 kΩ
7 μs
Code = half scale, R-normal mode,
RAB = 100 kΩ
14 μs
Code = half scale, R-perf mode,
RAB = 50 kΩ
9 μs
Code = half scale, R-perf mode,
RAB = 100 kΩ
16 μs
Resistor Noise Density eN_WB Code = half scale, TA = 25°C,
0 kHz to 200 kHz,
R
AB = 50 kΩ 18 nV/√Hz
R
AB = 100 kΩ 27 nV/√Hz
1 Typicals represent average readings at 25°C; VDD = +15 V, VSS = −15 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between RWB at Code 0x00B to Code 0x3FF or between RWA at Code 0x3F3 to
Code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode with
a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V.
3 The terms resistor performance mode and R-perf mode are used interchangeably.
4 Guaranteed by design; not subject to production test.
5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal
adjustment.
7 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC).
8 All dynamic characteristics use VDD = +15 V, VSS = −15 V, and VLOGIC = 5 V.
RESISTOR PERFORMANCE MODE CODE RANGE—50 kΩ AND 100 kΩ VERSIONS
Table 4.
RAB = 50 kΩ RAB = 100 kΩ
|VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V |VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V
Resistor Tolerance
per Code RWB R
WA R
WB R
WA R
WB R
WA R
WB R
WA
1% R-Tolerance From 0x08C
to 0x3FF
From 0x000
to 0x35F
From 0x0B4
to 0x3FF
From 0x000
to 0x31E
From 0x04B
to 0x3FF
From 0x000
to 0x3B4
From 0x064
to 0x3FF
From 0x000
to 0x39B
2% R-Tolerance From 0X03C
to 0x3FF
From 0x000
to 0x3C3
From 0x050
to 0x3FF
From 0x000
to 0x3AF
From 0x028
to 0x3FF
From 0x000
to 0x3D7
From 0x028
to 0x3FF
From 0x000
to 0x3D7
3% R-Tolerance From 0X028
to 0x3FF
From 0x000
to 0x3D7
From 0x032
to 0x3FF
From 0x000
to 0x3CD
From 0x019
to 0x3FF
From 0x000
to 0x3E6
From 0x019
to 0x3FF
From 0x000
to 0x3E6
AD5293
Rev. D | Page 7 of 24
INTERFACE TIMING SPECIFICATIONS
VDD = VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, and −40°C < TA < +105°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter Limit1 Unit Test Conditions/Comments
t12 20 ns min SCLK cycle time
t2 10 ns min SCLK high time
t3 10 ns min SCLK low time
t4 10 ns min
SYNC to SCLK falling edge setup time
t5 5 ns min Data setup time
t6 5 ns min Data hold time
t7 1 ns min
SCLK falling edge to SYNC rising edge
t8 4003 ns min Minimum SYNC high time
t9 14 ns min
SYNC rising edge to next SCLK fall ignored
t104 1 ns min
RDY rise to SYNC falling edge
t114 40 ns max
SYNC rise to RDY fall time
t124 2.4 μs max RDY low time, RDAC register write command execute time (resistor performance mode)
t124 410 ns max RDY low time, RDAC register write command execute time (normal mode)
t124 1.5 ms max Software\hardware reset
t134 450 ns max RDY low time, RDAC register read command execute time
t144 450 ns max SCLK rising edge to SDO valid
tRESET 20 ns min
Minimum RESET pulse width (asynchronous)
tPOWER-UP5 2 ms max Power-on time to half scale
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency = 50 MHz.
3 Refer to t12 and t13 for RDAC register commands operations.
4 RPULL_UP = 2.2 kΩ to VLOGIC with a capacitance load of 168 pF.
5 Typical power supply voltage slew-rate of 2 V/ms.
DATA BITS
DB9 (MSB) DB0 (LSB)
D7 D6 D5 D4 D3 D2 D1 D0
CONTROL BITS
C0C1
C2 D9 D8
C3
00
07675-002
Figure 2. Shift Register Contents
AD5293
Rev. D | Page 8 of 24
TIMING DIAGRAMS
t
4
t
3
t
2
t
5
t
7
t
6
D0D1
X
SYNC
SCLK
t
9
t
1
t
8
DIN
SDO
D6
D7 D2
XC3 C2
RDY
t
12
t
10
t
11
07675-003
RESET
t
RESET
Figure 3. Write Timing Diagram, CPOL = 0, CPHA =1
D0D1
X
SYNC
SCLK
t
9
t
14
t
13
t
11
DIN
SDO
X
D0 X
XC3
RDY
D0
XX
C3
D0D1
C3
0
7675-004
Figure 4. Read Timing Diagram, CPOL = 0, CPHA =1
AD5293
Rev. D | Page 9 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to GND −0.3 V to +35 V
VSS to GND +0.3 V to −25 V
VLOGIC to GND −0.3 V to +7 V
VDD to VSS 35 V
VA, VB, VW to GND VSS − 0.3 V, VDD + 0.3 V
Digital Input and Output Voltage to GND −0.3 V to VLOGIC +0.3 V
EXT_CAP Voltage to GND −0.3 V to +7 V
IA, IB, IW
Continuous
RAB = 20 kΩ ±3 mA
RAB = 50 kΩ, 100 kΩ ±2 mA
Pulsed1
Frequency > 10 kHz MCC2/d3
Frequency ≤ 10 kHz MCC2/√d3
Operating Temperature Range −40°C to +105°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation (TJ max − TA)/θJA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type θJA θ
JC Unit
14-Lead TSSOP 931 20 °C/W
1 JEDEC 2S2P test board, still air (from 0 m/sec to 1 m/sec of air flow).
ESD CAUTION
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Maximum continuous current.
3 Pulse duty factor.
AD5293
Rev. D | Page 10 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESET
V
SS
A
W
RDY
SYNC
V
LOGIC
SCLK
B
V
DD
EXT_CAP
1
2
3
4
5
6
7
DIN
GND
14
13
12
11
10
9
8
AD5293
TOP VIEW
Not to Scale
SDO
07675-005
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 RESET Hardware Reset Pin. Sets the RDAC register to midscale. RESET is activated at the logic high transition. Tie RESET to
VLOGIC if not used.
2 VSS Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 μF ceramic
capacitors and 10 μF capacitors.
3 A Terminal A of RDAC. VSS ≤ VA ≤ VDD.
4 W Wiper Terminal W of RDAC. VSS ≤ VW ≤ VDD.
5 B Terminal B of RDAC. VSS ≤ VB ≤ VDD.
6 VDD Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
7 EXT_CAP Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V.
8 VLOGIC Logic Power Supply, 2.7 V to 5.5 V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
9 GND Ground Pin, Logic Ground Reference.
10 DIN Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
11 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be
transferred at rates up to 50 MHz.
12 SYNC Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes
low, it enables the shift register, and data is transferred in on the falling edges of the following clocks. The selected
register is updated on the rising edge of SYNC, following the 16th clock cycle. If SYNC is taken high before the
16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
13 SDO Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data
from the serial register in daisy-chain mode or in readback mode.
14 RDY Ready Pin. This active-high, open-drain output identifies the completion of a write or read operation to or from
the RDAC register.
AD5293
Rev. D | Page 11 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
+25°C
–40°C
+105°C
07675-106
R
AB
= 20k
Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature
0.6
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
DNL (LSB)
0 128 256 384 512 640 768 896 1023
CODE (Decimal)
+25°C
–40°C +105°C
707675-00
R
AB
= 20k
Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature
1.0
–0.2
0
0.2
0.4
0.6
0.8
INL (LSB)
–0.6
–0.4
0 128 256 384 512 640 768 896 1023
CODE (Decimal)
+25°C
–40°C +105°C
07675-010
R
AB
= 20k
Figure 8. R-INL in Normal Mode vs. Code vs. Temperature
07675-215
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 25°C
Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance
07675-211
0.6
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance
07675-216
1.0
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 25°C
Figure 11. R-INL in Normal Mode vs. Code vs. Nominal Resistance
AD5293
Rev. D | Page 12 of 24
0.15
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07675-011
R
AB
= 20k
Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07675-014
R
AB
= 20k
Figure 13. INL in R-Perf Mode vs. Code vs. Temperature
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.2
–0.1
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
+25°C
–40°C +105°C
07675-015
R
AB
= 20k
Figure 14. DNL in R-Perf Mode vs. Code vs. Temperature
07675-213
0.15
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 25°C
Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance
07675-207
0.8
–0.8
–0.6
–0.2
0
0.2
0.6
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 25°C
Figure 16. INL in R-Perf Mode vs. Code vs. Nominal Resistance
07675-203
0.6
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 2 5°C
Figure 17. DNL in R-Perf Mode vs. Code vs. Nominal Resistance
AD5293
Rev. D | Page 13 of 24
0.8
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
+25°C
–40°C
+105°C
07675-018
R
AB
= 20k
Figure 18. INL in Normal Mode vs. Code vs. Temperature
0.10
–0.20
–0.15
–0.10
–0.05
0
0.05
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
+25°C
–40°C
+105°C
07675-019
R
AB
= 20k
Figure 19. DNL in Normal Mode vs. Code vs. Temperature
07675-022
450
400
350
300
250
200
150
100
50
0
–50
SUPPLY CURRENT (nA)
TEMPERATURE (°C)
–40–30–20–100 102030405060708090100
I
LOGIC
V
DD
/V
SS
= ±15V
V
LOGIC
= +5V
I
DD
I
SS
Figure 20. Supply Current vs. Temperature
07675-209
0.8
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 25°C
Figure 21. DNL in Normal Mode vs. Code vs. Temperature
07675-205
0.08
–0.16
–0.12
–0.08
–0.04
0
0.04
0 128 256 384 512 640 768 896 1023
DNL (LSB)
CODE (Decimal)
20k
50k
100k
TEMPERATURE = 25°C
Figure 22. DNL in Normal Mode vs. Code vs. Temperature
07675-057
0.20
0.18
0.16
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY CURRENT I
LOGIC
(mA)
DIGITAL INPUT VOLTAGE (V)
V
DD
= ±15V
Figure 23. Supply Current, ILOGIC, vs. Digital Input Voltage.
AD5293
Rev. D | Page 14 of 24
700
600
500
400
300
200
100
0
RHEOSTAT MODE TEMPCO (ppm/°C)
07675-023
0 256 512 768 1023
CODE (Decimal)
50k
20k
100k
V
DD
= 30V,
V
SS
= 0V
Figure 24. Rheostat Mode Tempco ΔRWB/ΔT vs. Code
0
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
1M100k10k1k10010
07675-025
GAIN (dB)
FREQUENCY (Hz)
0x200
0x100
0x080
0x040
0x020
0x010
0x008
0x004
0x002 0x001
Figure 25. 20 kΩ Gain vs. Frequency vs. Code
–50
–40
–30
–10
0
10 1M100k10k1k100
GAIN (dB)
FREQUENCY (Hz)
0x200
0x080
0x020
0x010
0x004
0x002 0x001
–20
–60
07674-200
0x040
0x008
0x100
Figure 26. 50 kΩ Gain vs. Frequency vs. Code
700
600
500
400
300
200
100
0
POTENTIOMETER MODE TEMPCO (ppm/°C)
0
7675-024
0 256 512 768 1023
CODE (Decimal)
V
DD
= 30V
V
SS
= 0V
50k
20k
100k
Figure 27. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code
–60
–50
–40
–30
–10
0
10 1M100k10k1k100
GAIN (dB)
FREQUENCY (Hz)
0x200
0x100
0x080
0x040
0x020
0x010
0x008
0x004
0x002
0x001
–20
–70
07675-201
Figure 28. 100 kΩ Gain vs. Frequency vs. Code
–70
–60
–50
–40
–30
–20
–10
0
100 1k 10k
FREQUENCY (Hz)
100k 1M
100k
20k
50k
07675-026
PSRR (dB)
Figure 29. Power Supply Rejection Ratio (PSRR) vs. Frequency
AD5293
Rev. D | Page 15 of 24
07675-027
0
–120
–105
–90
–75
–60
–45
–30
–15
THD + N (dB)
FREQUENCY (Hz)
100 1k 10k 100k
VDD/VSS = ±15V
CODE = HALF SCALE
VIN = 1V rms
Noise BW = 22kHz
50k
20k
100k
Figure 30. Total Harmonic Distortion + Noise (THD + N) vs. Frequency
0
100,000
200,000
300,000
400,000
500,000
600,000
700,000
BANDWIDTH (Hz)
800,000
900,000
1,000,000
CODE (Decimal)
5120 128 2566432168
07675-222
20k – 0pF
20k – 75pF
20k – 150pF
20k – 250pF
50k – 0pF
50k – 75pF
50k – 150pF
50k – 250pF
100k – 0pF
100k – 75pF
100k – 150pF
100k – 250pF
Figure 31. Maximum Bandwidth vs. Code vs. Net Capacitance
07675-058
35
–5
0
5
10
15
20
25
30
VOLTAGE (V)
TIME (µs)
V
WB
, CODE: FULL SCALE,
NORMAL MODE
SYNC
–2
–1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
V
DD
/V
SS
= 30V/0V
V
LOGIC
= 5V
V
A
= V
DD
V
B
= V
SS
V
WB
, CODE: HALF-SCALE,
NORMAL MODE
V
WB
, CODE: HALF-SCALE,
R-PERF MODE
20k
50k
100k
20k
50k
100k
V
WB
, CODE: FULL SCALE,
R-PERF MODE
Figure 32. Large Signal Settling Time, Code from Zero Scale to Full Scale
–140
–120
–100
–80
–60
–40
–20
0
0.001 0.01 0.1 1 10
THD + N (dB)
AMPLITUDE (V rms)
07675-220
V
DD
/V
SS
= ±15V,
CODE = HALF SCALE
f
IN
= 1kHz
NOISE BW = 22kHz
50k
20k
100k
Figure 33. Total Harmonic Distortion + Noise (THD + N) vs. Amplitud
8
0
1
2
3
4
5
6
7
0 256 512 768 1023
THEORETICAL I
WB_MAX
(mA)
CODE (Decimal)
07675-029
V
DD
/V
SS
= 30V/0V
V
A
= V
DD
V
B
= V
SS
50k
20k
100k
Figure 34. Theoretical Maximum Current vs. Code
40
32
24
–40
–32
–24
–16
–8
0
8
16
–0.5 0 5 10 15 20 25 30 35 40 45
VOLTAGE (V)
TIME (µs)
V
DD
/V
SS
= ±15V
V
A
=V
DD
V
B
=V
SS
CODE = HALF CODE
07675-221
Figure 35. Digital Feedthrough
AD5293
Rev. D | Page 16 of 24
21 26 30 33
VOLTAGE V
DD
/V
SS
NUMBER OF CODES (AD5293)
80
0
10
20
30
40
50
60
70
07675-219
V
A
= V
DD
V
B
= V
SS
TEMPERATURE = 25°C
50k
20k
100k
07675-035
1.2
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
VOLTAGE (V)
TIME (µs)
–202 46 810121416
V
DD
/V
SS
= ±15V
V
LOGIC
= +5V
V
A
= V
DD
V
B
= V
SS
50k
20k
100k
Figure 38. Code Range > 1% R-Tolerance Error vs. Voltage
Figure 36. Maximum Transition Glitch
07675-056
300
250
200
150
100
50
0
NUMBER OF CODES (AD5293)
TEMPERATURE (°C)
–40–30–20–100 102030405060708090100
V
DD
/V
SS
= ±15V
50k
20k
100k
Figure 37. Code Range > 1% R-Tolerance Error vs. Temperature
AD5293
Rev. D | Page 17 of 24
TEST CIRCUITS
Figure 39 to Figure 44 define the test conditions used in the Specifications section.
A
W
B
NC
I
W
DUT
V
MS
NC = NO CONNECT
07675-030
Figure 39. Resistor Position Nonlinearity Error
(Rheostat Operation: R-INL, R-DNL)
A
W
B
DUT
V
MS
V+
V
+ = V
DD
1LSB = V+/2
N
07675-031
Figure 40. Potentiometer Divider Nonlinearity Error (INL, DNL)
+
–
DUT
CODE = 0x00
0.1V
V
SS
TO V
DD
R
WB
= 0.1
V
I
WB
R
W
= R
WB
2
I
WB
W
B
A = NC
0
7675-032
Figure 41. Wiper Resistance
AW
BV
MS
~
V
A
V
DD
V+
V+ = V
DD
± 10%
V
MS
%
V
DD
%
PSS (%/%) =
PSRR (dB) = 20 log V
MS
V
DD
07675-033
Figure 42. Power Supply Sensitivity (PSS, PSRR)
07675-036
OFFSET
GND
A
B
DUT
W
+15
V
V
IN
V
OUT
OP42
–15V
2.5V
Figure 43. Gain vs. Frequency
V
SS
I
CM
W
B
V
DD
DUT
GND
A
NC = NO CONNECT
NC
–15V
GND
+15V
NC
+15
V
+15V –15V
–15V
GND
GND
GND
07675-037
Figure 44. Common-Mode Leakage Current
AD5293
Rev. D | Page 18 of 24
THEORY OF OPERATION
The AD5293 digital potentiometer is designed to operate as
a true variable resistor for analog signals that remain within
the terminal voltage range of VSS < VTERM < VDD. The patented
±1% resistor tolerance feature helps to minimize the total RDAC
resistance error, which reduces the overall system error by
offering better absolute matching and improved open-loop
performance. The digital potentiometer wiper position is
determined by the RDAC register contents. The RDAC register
acts as a scratchpad register, allowing as many value changes
as necessary to place the potentiometer wiper in the correct
position. The RDAC register can be programmed with any
position setting via the standard serial peripheral interface (SPI)
by loading the 16-bit data-word.
SERIAL DATA INTERFACE
The AD5293 contains a serial interface (SYNC, SCLK, DIN, and
SDO) that is compatible with SPI standards, as well as most DSPs.
The device allows data to be written to every register via the SPI.
SHIFT REGISTER
The AD5293 shift register is 16 bits wide (see Figure 2). The 16-bit
data-word consists of two unused bits, which are set to 0, followed
by four control bits and 10 RDAC data bits. Data is loaded MSB
first (Bit 15). The four control bits determine the function of the
software command (see Table 11). Figure 3 shows a timing diagram
of a typical write sequence.
The write sequence begins by bringing the SYNC line low. The
SYNC pin must be held low until the complete data-word is loaded
from the DIN pin. When SYNC returns high, the serial data-word
is decoded according to the instructions in . The
command bits (Cx) control the operation of the digital
potentiometer. The data bits (Dx) are the values that are loaded
into the decoded register. The AD5293 has an internal counter
that counts a multiple of 16 bits (per frame) for proper operation.
For example, the AD5293 works with a 32-bit word, but it cannot
work properly with a 31- or 33-bit word. The AD5293 does not
require a continuous SCLK, when
Table 11
SYNC is high, and all interface
pins should be operated close to the supply rails to minimize
power consumption in the digital input buffers.
RDAC REGISTER
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with all zeros, the wiper is connected to Terminal B of the
variable resistor. The RDAC register is a standard logic register;
there is no restriction on the number of changes allowed. The RDY
pin can be used to monitor the completion of a write to or read
from the RDAC register. The AD5293 presets to midscale on
power-up.
WRITE PROTECTION
On power-up, the serial data input register write command for
the RDAC register is disabled. The RDAC write protect bit, C1
of the control register (see Table 12 and Table 13 ), is set to 0 by
default. This disables any change of the RDAC register content,
regardless of the software commands, except that the RDAC register
can be refreshed to midscale using the software reset command
(Command 3, see Tabl e 11) or through hardware, using the
RESET pin. To enable programming of the variable resistor wiper
position (programming the RDAC register), the write protect bit,
C1 of the control register, must first be programmed. This is
accomplished by loading the serial data input register with
Command 4 (see ). Table 11
BASIC OPERATION
The basic mode of setting the variable resistor wiper position
(programming the RDAC register) is accomplished by loading the
serial data input register with Command 1 (see Table 11) and the
desired wiper position data. The RDY pin can be used to monitor
the completion of this RDAC register write command. Command 2
can be used to read back the contents of the RDAC register (see
Table 11). After issuing the readback command, the RDY pin
can be monitored to indicate when the data is available to be
read out on SDO in the next SPI operation. Instead of monitoring
the RDY pin, a minimum delay can be implemented when
executing a write or read command (see Table 5). Table 9
provides an example listing of a sequence of serial data input
(DIN) words with the serial data output appearing at the SDO
pin in hexadecimal format for an RDAC write and read.
Table 9. RDAC Register Write and Read
DIN SDO Action
0x1802 0xXXXX1 Enable update of wiper position.
0x0500 0x1802 Write 0x100 to the RDAC register.
Wiper moves to ¼ full-scale position.
0x0800 0x0500 Prepare data read from RDAC register.
0x0000 0x0100 NOP (Instruction 0) sends a 16-bit word
out of SDO, where the last 10 bits contain
the contents of the RDAC register.
1 X = unknown.
SHUTDOWN MODE
The AD5293 can be placed in shutdown mode by executing the
software shutdown command (see Command 6 in Table 11), and
setting the LSB to 1. This feature places the RDAC in a special state
in which Terminal A is open-circuited and Wiper W is connected
to Terminal B. The contents of the RDAC register are unchanged
by entering shutdown mode. However, all commands listed in
Table 11 are supported while in shutdown mode.
AD5293
Rev. D | Page 19 of 24
RESET
A low-to-high transition of the hardware RESET pin loads the
RDAC register with midscale. The AD5293 can also be reset
through software by executing Command 3 (see ).
The control register is restored with default bits (see ).
Table 11
Tabl e 13
RESISTOR PERFORMANCE MODE
This mode activates a new, patented 1% end-to-end resistor
tolerance that ensures a ±1% resistor tolerance on each code,
that is, code = half scale, RWB =10 kΩ ± 100 Ω. See Table 2 and
Table 4 to verify which codes achieve ±1% resistor tolerance.
The resistor performance mode is activated by programming
Bit C2 of the control register (see Table 12 and Table 13). The
typical settling time is shown in Figure 32.
SDO PIN AND DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes: it can
be used to read the contents of the wiper setting and control
register using Command 2, and Command 5, respectively (see
Table 11) or the SDO pin can be used in daisy-chain mode.
Data is clocked out of SDO on the rising edge of SCLK. The
SDO pin contains an open-drain N-channel FET that requires
a pull-up resistor if this pin is used. To place the pin in high
impedance and minimize the power dissipation when the pin
is used, the 0x8001 data word followed by Command 0 should
be sent to the part. Tabl e 10 provides a sample listing for the
sequence of the serial data input (DIN). Daisy chaining mini-
mizes the number of port pins required from the controlling IC.
As shown in Figure 45, users need to tie the SDO pin of one
package to the DIN pin of the next package. Users may need to
increase the clock period, because the pull-up resistor and the
capacitive loading at the SDO-to-DIN interface may require
additional time delay between subsequent devices.
When two AD5293s are daisy-chained, 32 bits of data are required.
The first 16 bits go to U2, and the second 16 bits go to U1. The
SYNC pin should be held low until all 32 bits are clocked into
their respective serial registers. The SYNC pin is then pulled
high to complete the operation.
Keep the SYNC pin low until all 32 bits are clocked into their
respective serial registers. The SYNC pin is then pulled high to
complete the operation.
DIN SDO
SCLK SCLK
R
P
2.2k
DIN SDO
U1 U2
AD5293 AD5293
SYNC
V
LOGIC
MICRO-
CONTROLLER
SCLK SS
MOSI
SYNC
07675-039
Figure 45. Daisy-Chain Configuration Using SDO
Table 10. Minimize Power Dissipation at the SDO Pin
DIN SDO1 Action
0xXXXX 0xXXXX Last user command sent to the digipot
0x8001 0xXXXX Prepares the SDO pin to be placed in high impedance mode
0x0000 High impedance The SDO pin is placed in high impedance
1 X = don’t care.
Table 11. Command Operation Truth Table
Command Bits[B13:B10] Data Bits[B9:B0]1
Command C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0 0 0 0 0 X X X X X X X X X X NOP command. Do nothing.
1 0 0 0 1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register data
to RDAC.
2 0 0 1 0 X X X X X X X X X X Read RDAC wiper setting from SDO
output in the next frame.
3 0 1 0 0 X X X X X X X X X X Reset. Refresh RDAC with midscale code.
4 0 1 1 0 X X X X X X X D2 D1 X Write contents of serial register data
to control register.
5 0 1 1 1 X X X X X X X X X X Read control register from SDO output
in the next frame.
6 1 0 0 0 X X X X X X X X X D0 Software power-down.
D0 = 0 (normal mode).
D0 = 1 (device placed in shutdown
mode).
1 X = don’t care.
Table 12. Control Register Bit Map
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X1 X
1 X
1 X
1 X
1 X
1 X
1 C2 C1 X1
1 X = don’t care.
AD5293
Rev. D | Page 20 of 24
Table 13. Control Register Function
Register Name Bit Name Description
Control C2 Calibration enable.
0 = resistor performance mode (default).
1 = normal mode.
C1 RDAC register write protect.
0 = locks the wiper position through the digital interface (default).
1 = allows update of wiper position through digital interface.
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5293 employs a 3-stage
segmentation approach, as shown in Figure 46. The AD5293
wiper switch is designed with transmission gate CMOS topology
and with the gate voltage derived from VDD.
R
W
S
W
W
R
W
10-BIT
ADDRESS
DECODER
A
R
L
R
L
R
M
R
M
B
R
M
R
M
R
L
R
L
07675-040
Figure 46. Simplified RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—1% Resistor Tolerance
The AD5293 operates in rheostat mode when only two terminals
are used as a variable resistor. The unused terminal can be left
floating or it can be tied to the W terminal, as shown in Figure 47.
W
A
B
W
A
B
W
A
B
07675-041
Figure 47. Rheostat Mode Configuration
The nominal resistance betwe en Ter min al A and Ter min al B,
RAB, is available in 20 kΩ, 50 kΩ, and 100 kΩ and has 1024 tap
points that are accessed by the wiper terminal. The 10-bit data
in the RDAC latch is decoded to select one of the 1024 possible
wiper settings. The AD5293 contains an internal ±1% resistor
tolerance calibration feature that can be enabled or disabled,
enabled by default by programming Bit C2 of the control
register (see Table 12 and Ta ble 13 ).
The digitally programmed output resistance between the
W terminal and the A terminal, RWA , and the W terminal
and B terminal, RWB, is calibrated to give a maximum of ±1%
absolute resistance error over both the full supply and temperature
ranges. As a result, the general equation for determining the
digitally programmed output resistance between the W terminal
and B terminal is
AB
WB R
D
DR ×= 1024
)( (1)
where:
D is the decimal equivalent of the binary code loaded in the
10-bit RDAC register.
RAB is the end-to-end resistance.
Similar to the mechanical potentiometer, the resistance of the RDAC
between the W terminal and the A terminal also produces a digitally
controlled complementary resistance, RWA . RWA is also calibrated
to give a maximum of 1% absolute resistance error. RWA starts at
the maximum resistance value and decreases as the data loaded
into the latch increases. The general equation for this operation is
ABWA R
D
DR ×
−
=1024
1024
)( (2)
where:
D is the decimal equivalent of the binary code loaded in the
10-bit RDAC register.
RAB is the end-to-end resistance.
In the zero-scale condition, a finite total wiper resistance of 120 Ω
is present. Regardless of the setting in which the part is operating,
care should be taken to limit the current between the A terminal to
B terminal, the W terminal to the A terminal, and the W terminal
to the B terminal to the maximum continuous current of ±3 mA or
to the pulse current specified in Table 6. Otherwise, degradation,
or possible destruction of the internal switch contact, can occur.
AD5293
Rev. D | Page 21 of 24
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B terminal and wiper-to-A terminal that is proportional
to the input voltage at A to B, as shown in Figure 48. Unlike the
polarity of VDD to GND, which must be positive, voltage across
A to B, W to A, and W to B can be at either polarity.
07675-042
W
A
B
V
IN
V
OUT
Figure 48. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity,
connecting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B that
ranges from 0 V to 30 V − 1 LSB. Each LSB of voltage is equal to
the voltage applied across the A terminal and B terminal, divided
by the 1024 positions of the potentiometer divider. The general
equation defining the output voltage at VW, with respect to
ground for any valid input voltage applied to Terminal A and
Terminal B, is
B
A
WV
D
V
D
DV ×
−
+×= 1024
1024
1024
)( (3)
To optimize the wiper position update rate when in voltage
divider mode, it is recommended that the internal ±1% resistor
tolerance calibration feature be disabled by programming Bit C2
of the control register (see Table 11 ).
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
rheostat mode, the output voltage is dependent mainly on the ratio
of the internal resistors, RWA and RWB, and not on the absolute
values. Therefore, the temperature drift reduces to 5 ppm/°C.
EXT_CAP CAPACITOR
A 1 µF capacitor to GND must be connected to the EXT_CAP
pin (see Figure 49) on power-up and throughout the operation
of the AD5293. This capacitor must have a voltage rating of ≥7 V.
AD5293
GND
C1
1µF
EXT_CAP
07675-043
Figure 49. Hardware Setup for the EXT_CAP Pin
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the AD5293
define the boundary conditions for proper 3-terminal, digital
potentiometer operation. Supply signals present on the A, B,
and W terminals that exceed VDD or VSS are clamped by the
internal forward-biased diodes (see Figure 50).
V
SS
V
DD
A
W
B
07675-044
Figure 50. Maximum Terminal Voltages Set by VDD and VSS
The ground pin of the AD5293 is primarily used as a digital
ground reference. To minimize the digital ground bounce, the
AD5293 ground pin should be joined remotely to common ground.
The digital input control signals to the AD5293 must be referenced
to the device ground pin (GND) to satisfy the logic level defined
in the Specifications section.
Power-Up Sequence
Because there are diodes to limit the voltage compliance at the
A, B, and W terminals (see Figure 50), it is important to power
VDD and VSS first, before applying any voltage to the A, B, and W
terminals. Otherwise, the diode is forward-biased such that VDD
and VSS are powered up unintentionally. The ideal power-up
sequence is GND, VSS, VLOGIC, VDD, the digital inputs, and then
VA, VB, and VW. The order of powering up VA, VB, VW, and the
digital inputs is not important, as long as they are powered after
VDD, VSS, and VLOGIC.
Regardless of the power-up sequence and the ramp rates of the
power supplies, the power-on preset activates after VLOGIC is
powered, restoring midscale to the RDAC register.
AD5293
Rev. D | Page 22 of 24
APPLICATIONS INFORMATION
HIGH VOLTAGE DAC
The AD5293 can be configured as a high voltage DAC, with an
output voltage as high as 33 V. The circuit is shown in Figure 51.
The output is
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+××=
1
2
1V2.1
1024
)( R
RD
DVOUT (4)
where D is the decimal code from 0 to 1023.
AD5293
U2
AD8512
V+
V–
AD8512
V
OUT
V
DD
U1B
V
DD
R
BIAS
A
DR512
D1
R
2
R
1
B
20k
U1A
07675-153
Figure 51. High Voltage DAC
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
For applications that require high current adjustments, such as
a laser diode or turnable laser, a boosted voltage source can be
considered (see Figure 52).
W
SIGNAL
C
C
R
BIAS
LD
V
IN
A
B
V
OUT
U1
AD5293
U3 2N7002
U2 I
L
OP184
07675-155
Figure 52. Programmable Boosted Voltage Source
In this circuit, the inverting input of the op amp forces VOUT to
be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the N-channel
FET (U3). The N-channel FET power handling must be adequate
to dissipate (VIN − VOUT) × IL power. This circuit can source a
maximum of 100 mA with a 33 V supply.
HIGH ACCURACY DAC
It is possible to configure the AD5293 as a high accuracy DAC
by optimizing the resolution of the device over a specific reduced
voltage range. This is achieved by placing external resistors on
either side of the RDAC, as shown in Figure 53. The improved
±1% resistor tolerance specification greatly reduces error
associated with matching to discrete resistors.
3
1024
)1024(
1
1024
3
)(
)(
)( RRR
VRR
DV
AB
D
DD
AB
D
OUT +×+
×
+
=− (5)
AD5293
U1
V
OUT
B
R
2
20k
R
1
R
3
±1%
OP1177
V+
V–
V
DD
V
DD
U2
07675-154
Figure 53. Optimizing Resolution
VARIABLE GAIN INSTRUMENTATION AMPLIFIER
The AD8221 in conjunction with the AD5293 and the ADG1207,
as shown in Figure 54, make an excellent instrumentation
amplifier for use in data acquisition systems. The data acquisition
system is low distortion and low noise enable it to condition
signals in front of a variety of ADCs.
AD8221
AD5293
+V
IN1
V
DD
V
OUT
V
SS
A
DG1207
+V
IN4
–V
IN1
–V
IN4
07675-156
Figure 54. Data Acquisition System
The gain can be calculated by using Equation 6, as follows:
AB
RD
DG ×
+= )1024(
k4.49
1)( (6)
AD5293
Rev. D | Page 23 of 24
AUDIO VOLUME CONTROL
The excellent THD performance and high voltage capability
of the AD5293 make it ideal for digital volume control. The
AD5293 is used as an audio attenuator; it can be connected
directly to a gain amplifier. A large step change in the volume
level at any arbitrary time can lead to an abrupt discontinuity of
the audio signal, causing an audible zipper noise. To prevent this,
a zero-crossing window detector can be inserted to the CS line to
delay the device update until the audio signal crosses the window.
Because the input signal can operate on top of any dc level,
rather than absolute 0 V level, zero crossing in this case means
the signal is ac-coupled, and the dc offset level is the signal zero
reference point.
The configuration to reduce zipper noise is shown in Figure 56,
and the results of using this configuration are shown in Figure 55.
The input is ac-coupled by C1 and attenuated down before
feeding into the window comparator formed by U2, U3, and U4B.
U6 is used to establish the signal as zero reference. The upper
limit of the comparator is set above its offset and, therefore, the
output pulses high whenever the input falls between 2.502 V
and 2.497 V (or 0.005 V window) in this example. This output
is AND’ed with the chip select signal such that the AD5293
updates whenever the signal crosses the window. To avoid a
constant update of the device, the chip select signal should be
programmed as two pulses, rather than as one.
In Figure 55, the lower trace shows that the volume level changes
from a quarter-scale to full-scale when a signal change occurs
near the zero-crossing window.
CHANNEL 1
FREQ = 20.25kHz
1.03V p-p
1
2
0
7675-158
Figure 55. Zipper Noise Detector
R
1
100k
R
2
200
5V
V
IN
V+
V–
AD8541
5V
U6
R
3
100k
R
4
90k
R
5
10k
C1
1µF
V
DD
V
SS
SCLK
SDIN
V+
V–
AD5293
20k
+15V
–15V
C3
0.1µF
C2
0.1µF
A
B
W
GND
SDIN
SCLK
U1
V
CC
GND
V
CC
GND
ADCMP371
ADCMP371
+15V
–15V
+5V
+5V
U3
U2
V
OUT
U5
U4A
U4B
16
2
4
5
7408
7408 SYNC
SYNC
07675-157
Figure 56. Audio Volume Control with Zipper Noise Reduction.
AD5293
Rev. D | Page 24 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 57. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 R
AB (kΩ) Resolution Temperature Range Package Description Package Option
AD5293BRUZ-20 20 1,024 −40°C to +105°C 14-Lead TSSOP RU-14
AD5293BRUZ-20-RL7 20 1,024 −40°C to +105°C 14-Lead TSSOP RU-14
AD5293BRUZ-50 50 1,024 −40°C to +105°C 14-Lead TSSOP RU-14
AD5293BRUZ-50-RL7 50 1,024 −40°C to +105°C 14-Lead TSSOP RU-14
AD5293BRUZ-100 100 1,024 −40°C to +105°C 14-Lead TSSOP RU-14
AD5293BRUZ-100-RL7 100 1,024 −40°C to +105°C 14-Lead TSSOP RU-14
1 Z = RoHS Compliant Part.
©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07675-0-3/11(D)