NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM 240pin Registered DDR2 SDRAM MODULE Based on 64Mx8 & 128Mx4 DDR2 SDRAM Die A Features * 64Mx72 Registered DDR2 DIMM based on 64Mx8 DDR2 SDRAM * 128Mx72 & 256Mx72 Registered DDR2 DIMM based on 128Mx4 DDR2 SDRAM * JEDEC Standard 240-pin Dual In-Line Memory Module * Error Check Correction (ECC) Support * Phase-lock loop (PLL) clock driver to reduce loading * Registered inputs with one-clock delay * Performance: * Differential clock inputs * Data is read or written on both clock edges * Programmable Operation: - Device Latency: 3, 4, 5 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * On-Die Termination (ODT) * Off-Chip Driver (OCD) * 14/10/1 Addressing (row/column/rank) - 512MB * 14/11/1 Addressing (row/column/rank) - 1GB * 14/11/2 Addressing (row/column/rank) - 2GB * 7.8 s Max. Average Periodic Refresh Interval * Serial Presence Detect * Gold contacts * SDRAMs in 60-ball FBGA Package * RoHS compliance PC2-5300 Speed Sort DIMM Latency* f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency -3C Unit 5 333 MHz 3 ns 667 MHz * Intended for 333 MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = 1.8 0.1 Volt, VDDQ = 1.8 0.1 Volt * SDRAMs have 4 internal banks for concurrent operation Description NT512T72U89A0BV, NT1GT72U4PA0BV and NT2GT72U4NA2BV are Registered 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank 64Mx72 or128Mx72 and two-banks 256Mx72 high-speed memory array. The module uses nine 64Mx8 (NT512T72U89A0BV), eighteen 128Mx4 (NT1GT72U4PA0BV) or thirty-six 128Mx4 (NT2GT72U4NA2BV) DDR2 SDRAMs in FBGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 333 MHz clock speeds and achieves high-speed data transfer rates of up to 667 MHz. Prior to any access operation, the device latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A15 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.2 09/2006 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Ordering Information Part Number Speed Organization NT512T72U89A0BV-3C NT1GT72U4PA0BV-3C Leads Power Gold 1.8V 64Mx72 333 MHz (3ns @ CL = 5) PC2-5300 DDR2-667 NT2GT72U4NA2BV-3C 128Mx72 256Mx72 Pin Description CK0, CKE0, CKE1 Differential Clock Inputs DQ0-DQ63 Clock Enable CB0-CB7 Row Address Strobe DQS0-DQS8 Column Address Strobe , A0-A9, A11-A13 A10/AP BA0, BA1 ODT0, ODT1 NC RFU Par_In REV 1.2 09/2006 Data input/output ECC Check Bit Data Input/Output Bidirectional data strobes DM0-DM8/DQS9-17 Input Data Mask/High Data Strobes Write Enable - Chip Selects VDD Address Inputs VDDQ Column Address Input/Auto-precharge VREF SDRAM Bank Address Inputs VDDSPD Differential data strobes Core Power I/O Power Ref. Voltage for SSTL_18 inputs Serial EEPROM positive power supply Reset pin VSS Ground Active termination control lines SCL Serial Presence Detect Clock Input No Connect SDA Serial Presence Detect Data input/output Reserved for Future Use SA0-2 Serial Presence Detect Address Inputs Parity error found on the Address and Control bus Parity bit for the Address and Control bus 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Pinout Pin Front 1 VREF 2 VSS 3 DQ0 44 4 DQ1 45 5 VSS 46 47 DQS0 8 9 10 DQ3 11 VSS 12 13 14 Back Pin Back Pin Back 121 VSS 162 CB5 202 DM4/DQS13 122 DQ4 163 VSS 203 DQS4 123 DQ5 164 DM8/DQS17 204 VSS 85 VSS 124 VSS 165 205 DQ38 DQS8 86 DQ34 125 DM0, DQS9 166 VSS 206 DQ39 VSS 87 DQ35 126 167 CB6 207 VSS 48 CB2 88 VSS 127 VSS 168 CB7 208 DQ44 VSS 49 CB3 89 DQ40 128 DQ6 169 VSS 209 DQ45 DQ2 50 VSS 90 DQ41 129 DQ7 170 VDDQ 210 VSS 51 VDDQ 91 VSS 130 VSS 171 NC, CKE1 211 DM5/DQS14 52 CKE0 92 131 DQ12 172 VDD 212 DQ8 53 VDD 93 DQS5 132 DQ13 173 NC 213 VSS DQ9 54 NC 94 VSS 133 VSS 174 NC 214 DQ46 VSS 55 DM1/DQS10 DQ47 6 7 15 Pin Front Pin Front Pin 42 CB0 82 VSS 43 CB1 83 VSS 84 95 DQ42 134 56 VDDQ 96 DQ43 135 A11 97 VSS 136 NC, 175 VDDQ 215 176 A12 216 VSS VSS 177 A9 217 DQ52 16 DQS1 57 17 VSS 58 A7 98 DQ48 137 RFU 178 VDD 218 DQ53 59 VDD 99 DQ49 138 RFU 179 A8 219 VSS NC 18 19 NC 60 A5 100 VSS 139 VSS 180 A6 220 20 VSS 61 A4 101 SA2 140 DQ14 181 VDDQ 221 NC 21 DQ10 62 VDDQ 102 NC 141 DQ15 182 A3 222 VSS 22 DQ11 63 A2 103 VSS DM6/DQS15 23 VSS 64 VDD 104 24 DQ16 25 DQ17 65 26 VSS 27 KEY 142 VSS 183 A1 223 143 DQ20 184 VDD 224 105 DQS6 144 DQ21 VSS 106 VSS 145 VSS 185 KEY 66 VSS 107 DQ50 146 DM2/DQS11 186 67 VDD 108 DQ51 147 187 CK0 225 VSS 226 DQ54 227 DQ55 VDD 228 VSS 28 DQS2 68 Par_In 109 VSS 148 VSS 188 A0 229 DQ60 29 VSS 69 VDD 110 DQ56 149 DQ22 189 VDD 230 DQ61 30 DQ18 70 A10/AP 111 DQ57 150 DQ23 190 BA1 231 VSS 31 DQ19 71 BA0 112 VSS 151 VSS 191 VDDQ 232 DM7/DQS16 32 VSS 72 VDDQ 113 152 DQ28 192 33 DQ24 73 114 DQS7 153 DQ29 193 234 VSS 34 DQ25 74 115 VSS 154 VSS 194 VDDQ 235 DQ62 35 Vss 75 116 DQ58 155 DM3/DQS12 117 DQ59 156 36 VDDQ 76 233 195 ODT0 236 DQ63 196 A13 237 VSS 37 DQS3 77 ODT1 118 VSS 157 VSS 197 VDD 238 VDDSPD 38 Vss 78 VDDQ 119 SDA 158 DQ30 198 VSS 239 SA0 39 DQ26 79 Vss 120 SCL 159 DQ31 199 DQ36 240 SA1 40 DQ27 80 DQ32 160 VSS 200 DQ37 Vss 81 DQ33 161 CB4 201 VSS 41 and Par_In are optional functions to check address and command parity. REV 1.2 09/2006 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Input/Output Functional Description Symbol CK0 Type Polarity Function (SSTL) The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, operation to be executed by the SDRAM. , , , , define the VREF Supply Reference voltage for SSTL-18 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. A0 - A9 A10/AP A11-A13 (SSTL) - DQ0 - DQ63 CB0 - CB7 (SSTL) Active High VDD, VSS Supply DQS0 - DQS17 - DM0 - DM8 (SSTL) On-Die Termination control signals Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM configurations. Power and ground for the DDR SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Input Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Input Active Low The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and the registers will be set to low level. The PLL will remain synchronized with the input clock. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. V DDSPD Supply Par_In Input Out REV 1.2 09/2006 Serial EEPROM positive power supply. Parity bit for the Address and Control bus. (1 for Odd, 0 for Even) Parity error found in the Address and Control bus. 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Functional Block Diagram (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) REV 1.2 09/2006 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Functional Block Diagram (1GB, 1 Rank, 128Mx4 DDR2 SDRAMs) ! ! ! ! ! ! ! " " " " " " " " ! # " " ' " " " $ " & % % & & % # & # # # $ $ $ $ $ $ $ () $ *+ % ,, $$ ), +-- ), ./ 0)1. +) ( $. ( $. 23 23 " 23 % 4- $ % % % % 5 %!5 5 5 ( $. % $ % $ % ( $. REV 1.2 09/2006 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Functional Block Diagram (2GB, 2 Rank, 128Mx4 DDR2 SDRAMs) REV 1.2 09/2006 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (512MB) 64Mx72 1 RANK REGISTERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-667 -3C DDR2-667 -3C 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type DDR2-SDRAM 08 3 Number of Row Addresses on Assembly 14 0E 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Bank 1 60 6 Data Width of Assembly X72 48 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8 05 9 DDR2 SDRAM Device Cycle Time at CL=5 3ns 30 10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.45ns 45 11 DIMM Configuration Type parity 06 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width 14 Error Checking DDR2 SDRAM Device Width 15 Reserved 16 17 7.8s/SR 82 X8 08 X8 08 Undefined 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 3/4/5 38 19 DIMM Mechanical Characteristics <4.10mm 01 20 DDR2 SDRAM DIMM Type Information Reg. DIMM 01 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 24 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time from Clock at CL=3 27 28 Normal DIMM 00 Support weak driver 03 Minimum Clock Cycle at CL=5 3.75ns 3D Maximum Data Access Time from Clock at CL=5 0.5ns 50 5ns 50 0.6ns 60 Minimum Row Precharge Time (tRP) 15ns 3C Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 31 Module Bank Density 32 Address and Command Setup Time Before Clock (tIS) 33 34 512MB 80 0.2ns 20 Address and Command Hold Time After Clock (tIH) 0.275ns 27 Data Input Setup Time Before Clock (tDS) 0.10ns 10 35 Data Input Hold Time After Clock (tDH) 0.175ns 17 36 Write Recovery Time (tWR) 15ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Reserved Undefined 00 40 Extension of Byte 41 tRC and Byte 42 tRFC The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 41 Minimum Core Cycle Time (tRC) 60ns 3C REV 1.2 09/2006 Note 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (512MB) 64Mx72 1 RANK REGISTERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-667 -3C DDR2-667 -3C 105ns 69 8ns 80 18 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) 0.24ns 45 Read Data Hold Skew Factor (tQHS) 0.34ns 22 46 PLL Relock Time 15.0s 0F 47 Tcasemax 3 52 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 122 7A 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 20 53 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 58 2F 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 39 27 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 39 27 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 44 2C 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 28 1C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 38 4C 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 37 25 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 40 28 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit(DT Register Active/Mode Bit) 00 00 62 SPD Revision 63 Checksum Data 64-71 Manufacturer's JEDEC ID Code 72 Module Manufacturing Location 73-91 Module Part number 92-255 Module Revision Code Note: 1. NT512T72U89A0BV-3C REV 1.2 09/2006 1.2 12 Checksum Data 12 NANYA 7F7F7F0B00000000 Manufacturing code -- Module Part Number in ASCII -- Undefined -- Note 1 4E54353132543732553839413046552D354120 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (1GB) 128Mx72 1 RANK REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-667 -3C DDR2-667 -3C 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of DIMM Bank 6 Data Width of Assembly X72 48 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8 05 9 DDR2 SDRAM Device Cycle Time at CL=5 3ns 30 10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.45ns 45 11 DIMM Configuration Type parity 06 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width 14 Error Checking DDR2 SDRAM Device Width 15 Reserved 16 17 DDR2-SDRAM 08 14 0E 11 0B 1 rank, Height=30mm 60 7.8s/SR 82 X4 04 X4 04 Undefined 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 3/4/5 38 19 DIMM Mechanical Characteristics <4.10mm 01 20 DDR2 SDRAM DIMM Type Information Reg. DIMM 01 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 24 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time from Clock at CL=3 27 28 Normal DIMM 00 Support weak driver 03 Minimum Clock Cycle at CL=5 3.75ns 3D Maximum Data Access Time from Clock at CL=5 0.5ns 50 5ns 50 0.6ns 60 Minimum Row Precharge Time (tRP) 15ns 3C Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 31 Module Bank Density 1GB 01 32 Address and Command Setup Time Before Clock (tIS) 0.2ns 20 33 Address and Command Hold Time After Clock (tIH) 0.27ns 27 34 Data Input Setup Time Before Clock (tDS) 0.1ns 10 35 Data Input Hold Time After Clock (tDH) 0.175ns 17 36 Write Recovery Time (tWR) 15ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Reserved Undefined 00 40 Extension of Byte 41 tRC and Byte 42 tRFC The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 41 Minimum Core Cycle Time (tRC) 60ns 3C REV 1.2 09/2006 Note 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (1GB) 128Mx72 1 RANK REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-667 -3C DDR2-667 -3C 105ns 69 8ns 80 18 Description 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) 0.24ns 45 Read Data Hold Skew Factor (tQHS) 0.34ns 22 46 PLL Relock Time 15s 0F 47 Tcasemax 3 52 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 61C/W 7A 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 20 53 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 58 2F 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 39 27 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 39 27 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 44 2C 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 28 1C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 38 4C 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 37 25 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 40 28 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit(DT Register Active/Mode Bit) 00 00 62 SPD Revision 63 Checksum Data 1.2 12 Checksum Data 8C NANYA 7F7F7F0B00000000 64-71 Manufacturer's JEDEC ID Code 72 Module Manufacturing Location 73-91 Module Part number Manufacturing code -- Module Part Number in ASCII -- Undefined -- 92-255 Module Revision Code Note: 1.NT1GT72U4PA0BV-3C REV 1.2 09/2006 Note 1 4E543147543732553450413042562D33432020 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (2GB) 256Mx72 2 RANKS REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-667 -3C DDR2-667 -3C 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of DIMM Bank 6 Data Width of Assembly X72 48 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8 05 9 DDR2 SDRAM Device Cycle Time at CL=5 3ns 30 10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.45ns 45 11 DIMM Configuration Type parity 06 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width 14 Error Checking DDR2 SDRAM Device Width 15 Reserved 16 17 DDR2-SDRAM 08 14 0E 11 0B 2 rank, Height=30mm 61 7.8s/SR 82 X4 04 X4 04 Undefined 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 3/4/5 38 19 DIMM Mechanical Characteristics <4.10mm 01 20 DDR2 SDRAM DIMM Type Information Reg. DIMM 01 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 24 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time from Clock at CL=3 27 28 Normal DIMM 00 Support weak driver 03 Minimum Clock Cycle at CL=5 3.75ns 3D Maximum Data Access Time from Clock at CL=5 0.5ns 50 5ns 50 0.6ns 60 Minimum Row Precharge Time (tRP) 15ns 3C Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 31 Module Bank Density 1GB 01 32 Address and Command Setup Time Before Clock (tIS) 0.2ns 20 33 Address and Command Hold Time After Clock (tIH) 0.27ns 27 34 Data Input Setup Time Before Clock (tDS) 0.1ns 10 35 Data Input Hold Time After Clock (tDH) 0.175ns 17 36 Write Recovery Time (tWR) 15ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Reserved Undefined 00 40 Extension of Byte 41 tRC and Byte 42 tRFC The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 41 Minimum Core Cycle Time (tRC) 60ns 3C REV 1.2 09/2006 Note 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (2GB) 256Mx72 2 RANKS REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2-667 -3C DDR2-67 -3C 105ns 69 8ns 80 18 Description 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) 0.24ns 45 Read Data Hold Skew Factor (tQHS) 0.34ns 22 46 PLL Relock Time 15s 0F 47 Tcasemax 3 52 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 61C/W 7A 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 20 53 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 58 2F 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 39 27 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 39 27 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 44 2C 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 28 1C 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 38 4C 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 37 25 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 40 28 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit(DT Register Active/Mode Bit) 00 00 62 SPD Revision 63 Checksum Data 1.2 12 Checksum Data 8D NANYA 7F7F7F0B00000000 64-71 Manufacturer's JEDEC ID Code 72 Module Manufacturing Location 73-91 Module Part number Manufacturing code -- Module Part Number in ASCII -- Undefined -- 92-255 Module Revision Code Note: 1.NT2GT72U4NA0BV-3C REV 1.2 09/2006 Note 1 4E54324754373255344E413042562D33432020 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Absolute Maximum Ratings Symbol Rating Units Voltage on I/O pins relative to VSS -0.5 to 2.3 V Voltage on VDD supply relative to VSS -1.0 to 2.3 V VDDQ Voltage on VDDQ supply relative to VSS -0.5 to 2.3 V HSTG Storage Humidity (without condensation) 5 to 95 % VIN, VOUT VDD Parameter Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating conditions Symbol Parameter Rating Units Note 0 to 95 C 1,2,3 -55 to 100 C TCASE Operating Temperature (Ambient) TSTG Storage Temperature (Plastic) TOPR Module Operating Temperature Range (ambient) 0 to 55 C HOPR Operating Humidity (relative) 10 to 90 % Note: 1. 2. 3. Case temperature is measured at top and center side of any DRAMs. tCASE > 85C tREFI = 3.9 6s All DRAM specification only support 0C < tCASE < 85C DC Electrical Characteristics and Operating Conditions (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) Symbol VDD VDDQ VSS, VSSQ VREF Min Max Units Notes Supply Voltage Parameter 1.7 1.9 V 1 I/O Supply Voltage 1.7 1.9 V 1 Supply Voltage, I/O Supply Voltage 0 0 V 0.49VDDQ 0.51VDDQ V 1, 2 VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 -5 5 6A IL I/O Reference Voltage Input / Output Leakage Current Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VID is the magnitude of the difference between the input level on CK and the input level on . REV 1.2 09/2006 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) PC2-5300 (-3C) Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 790 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 1070 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 318 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 519 mA I DD2Q Precharge quiet standby current; All banks idle; tCK=tCK(IDD); CKE is HIGH; is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. 231 mA I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 401 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 319 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 521 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1165 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1134 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1296 mA I DD6 Self-Refresh Current: CKE 0.2V 305 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1703 mA Symbol Parameter/Condition Note: All IDD values are average values derived from measurements. REV 1.2 09/2006 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V (1GB, 1 Rank, 64Mx8 DDR2 SDRAMs) PC2-5300 (-3C) Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1340 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 1724 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 391 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 793 mA I DD2Q Precharge quiet standby current; All banks idle; tCK=tCK(IDD); CKE is HIGH; is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. 298 mA I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 559 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 392 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 798 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1823 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1585 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 2373 mA I DD6 Self-Refresh Current: CKE 0.2V 376 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 2870 mA Symbol Parameter/Condition Note: All IDD values are average values derived from measurements. REV 1.2 09/2006 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V (2GB, 2 Rank, 64Mx8 DDR2 SDRAMs) PC2-5300 (-3C) Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1960 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 2400 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 691 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 1400 mA I DD2Q Precharge quiet standby current; All banks idle; tCK=tCK(IDD); CKE is HIGH; is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. 1476 mA I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 862 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 697 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1402 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 2484 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 2225 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 2962 mA I DD6 Self-Refresh Current: CKE 0.2V 684 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 3549 mA Symbol Parameter/Condition Note: All IDD values are average values derived from measurements. REV 1.2 09/2006 17 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol Max. Unit -0.45 +0.45 ns DQS output access time from CK/ -0.4 +0.4 ns tCH CK high-level width 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCH or tCL - tCK tDQSCK tCK Clock Cycle Time 3 8 ns tDH DQ and DM input hold time 175 - ps tDS DQ and DM input setup time 100 - ps tIPW Input pulse width 0.6 - tCK DQ and DM input pulse width (each input) 0.35 - tCK - tAC max ns tAC max ns tAC min tAC max ns tDIPW tHZ Data-out high-impedance time from CK/ tLZ(DQ) Data-out low-impedance time from CK/ tLZ(DQS) DQS low-impedance time from CK/ 2tAC min DQS-DQ skew (DQS & associated DQ signals) - 0.24 ns tQHS Data hold Skew Factor - 0.34 ns tQH Data output hold time from DQS tHP tQHS - ns Write command to 1st DQS latching transition -0.25 0.25 tCK DQS input low (high) pulse width (write cycle) 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - tCK tMRD Mode register set command cycle time 2 - tCK tWPST Write postamble 0.40 0.60 tCK tWPRE Write preamble 0.35 - tCK tIH Address and control input hold time 275 - ps tIS Address and control input setup time 0.2 - ns tRPRE Read preamble 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 tCK tIS + tCK + tIH - ns tDQSQ tDQSS tDQSL,(H) 09/2006 Min. DQ output access time from CK/ tAC REV 1.2 -3C Parameter tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tRFC Refresh to active/Refresh command time 105 Notes ns 18 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol tREFI -3C Parameter Min. Unit Average Periodic Refresh Interval (85C < TCASE 7 95C) 3.9 6s Average Periodic Refresh Interval (0C 7 TCASE 7 85C) 7.8 6s tRRD Active bank A to Active bank B command 7.5 tFAW For Activate window 37.5 tCCD Max. to tWR Write recovery time WR Write recovery time with Auto-Precharge - ns 2 - tCK 15 - ns ns tWR/tCK ns tDAL Auto precharge write recovery + precharge time WR +tRP tWTR Internal write to read command delay 7.5 - ns tRTP Internal read to precharge command delay 7.5 - ns tXSNR Exit self refresh to a Non-read command tRFC +10 - ns tXSRD Exit self refresh to a Read command 200 - tCK 2 - tCK tXP Exit precharge power down to any Non- read command Notes - tCK tXARD Exit active power down to read command 2 - tCK tXARDS Exit active power down to read command 7-AL - tCK tCKE CKE minimum pulse width 3 - tCK tOIT OCD drive mode output delay 0 12 ns 2 2 tCK tAC(min) tAC(max) ns tAC(min) +2 2tCK + tAC(max)+1 ns 2.5 2.5 tCK tAC(min) tAC(max)+ 0.6 ns 2.5tCK + tAC(max)+1 ns ODT tAOND ODT turn-on delay tAON ODT turn-on tAONPD ODT turn-on (Power down mode) tAOFD ODT turn-off delay tAOF ODT turn-off +0.7 tAOFPD ODT turn-off (Power down mode) tAC(min) +2 tANPD ODT to power down entry latency 3 tCK tAXPD ODT power down exit latency 8 tCK Speed Grade Definition REV 1.2 09/2006 tRAS Row Active Time 45 70000 ns tRCD RAS to CAS delay 15 - ns tRC Row Cycle Time 60 - ns tRP Row Precharge Time 15 - ns 19 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Package Dimensions (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) 3& 8 8 8 8 !8 8 8 ! ( $. : ;< 8 8 8 8 8 8! 8 8 8 . " ! 8 . " 8 8 8! 8 8 8 8! 9 8 ,.4 8 9 8 ! 8 8 8 8 8 8 ,- )$ +)$ 9 9 9 8 9 8 8 8 . ?).$# 8 8 % 8 ! 3+. # " 8 8 . 8 8 .14 8 8 ./=1 > .4 .+ )1 $ +*9 8 : 8 < 0) $$ +.4 > $ $. . ,8 - . $ : )14 $< *Device position is only for reference. REV 1.2 09/2006 20 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Package Dimensions (1GB, 1 Rank, 128Mx4 DDR2 SDRAMs) 3& 8 8 8 8 !8 8 8 ! ( $. : ;< 8 8 8 8 8 8! 8 8 8 8 . " 8 8 8 . 8 " ! 8 % 8 9 8 9 8 8 8 ( $. 8 ! . 8 8 8! 9 8 ,.4 8 9 8 ! 8 8 8 8 8 8 3+. # ?).$# " 8 8 8! 8 . ,- )$ +)$ 9 9 .14 8 8 ./=1 > .4.+ )1 $ +*9 8 : 8 < 0) $$ +.4 > $ $. . ,8 - . $ : )14 $< *Device position is only for reference. REV 1.2 09/2006 21 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Package Dimensions (2GB, 2 Ranks, 128Mx4 DDR2 SDRAMs) 3& 8 8 8 8 !8 8 8 ! ( $. : ;< 8 8 8 8 8 8! 8 ( $. 8 8 8 . " 8 8 8 . 8 " ! 8 % 8 9 8 9 8 8 8 ( $. ( $. 8 ! . 8 8 8! 9 8 ,.4 8 9 8 ! 8 8 8 8 8 8 3+. # ?).$# " 8 8 8! 8 . ,- )$ +)$ 9 9 .14 8 8 ./=1 > .4.+ )1 $ +*9 8 : 8 < 0) $$ +.4 > $ $. . ,8 - . $ : )14 $< *Device position is only for reference. REV 1.2 09/2006 22 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV 512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72 Registered DDR2 SDRAM DIMM Revision Log Rev Date 0.1 12/2005 Preliminary Release. 0.2 12/2005 Update Block Diagram. 0.3 03/2006 Update Package Dimensions and IDD. 1.0 03/2006 Official release. 1.1 04/2006 Update 2GB Part Number. 1.2 09/2006 Update SPD content; functional Block Diagram; Features. REV 1.2 09/2006 Modification 23 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.