ISG2000DS - California Eastern Laboratories / NEC

ISG2000DS

FEATURES

• TWO WAY MCNS COMPLIANT:

91-860 MHz Downstream

5-42 MHz Upstream

• INTERFACES DIRECTLY WITH QAM DEMOD/MOD ICs

• BUILT IN RF TRANSMITTER:

50 dB AGC Driver

• LOW PHASE NOISE:

-85 dBc/Hz @ 10 KHz

• BUSINESS CARD SIZE:

3.4" x 2.0" x 0.5"

• RUGGED/NO MICROPHONICS:

All SMD Components, "Coiless"

• EUROPEAN AND US VERSIONS AVAILABLE

• LOW POWER CONSUMPTION:

RX: 1.2 Watts, TX: 0.6 Watts

5 V CATV MODEM RF TRANSCEIVER

DESCRIPTION AND APPLICATIONS

The ISG2000DS is a complete RF transceiver designed for

use in cable modem applications. The transceiver integrates

a diplex filter, double conversion receiver and transmit AGC

amplifier (see Figure 1). The diplex filter provides over 40 dB

of isolation between the TX band and the RX band. The

receiver converts QAM signals in the RX band down to the IF

sampling frequency and provides the necessary gain control

input power to the DSP. The RF transmitter section provides

40 dB gain control under all conditions, while maintaining

excellent linearity performance.

California Eastern Laboratories

ELECTRICAL CHARACTERISTICS (VCC = 5 V, VCC2 = 24 V, TA = 25°C)

Notes:

1. Optional Output 43.75 MHz Available

2. 110 Channels at +15 dBmV/tone

PART NUMBER ISG2000DS

SYMBOLS PARAMETERS UNITS MIN TYP MAX

RF Performance (RX)

fOP Operating Frequency Range MHz 91 860

Input Signal Level dBmV -20 15

Gain Range dB 25 75

VAGC Automatic Gain Control Voltage RF 0 3.3

VAGC Automatic Gain Control Voltage IF 0 3.3

NFMAX Noise Figure (Max Gain) dB 8 10

Phase Noise at 10 kHz Offset dBc/Hz -85 -83

LO Radiation at RF Input dBm -60

Resolution KHz 62.5

Lock Time µsec. 600

Input Impedance (Nominal) ohms 75

RLIN Input Return Loss dB 6

Channel Bandwidth USA MHz 6

Output Frequency1MHz 43.70 43.75 43.80

Passband Ripple dB 1 2

Image Rejection dB 50

Inband Group Delay ns 100

CSO2dBc 45

CTB2dBc 45

Frequency Offset KHz -50 +50

ABSOLUTE MAXIMUM RATINGS

(TC = 25 °C unless otherwise noted)

SYMBOLS PARAMETERS UNITS RATINGS

VIN RF Input Voltage dBmV 60

VCC1 (RX) Supply Voltage 1 (RX)V 6

VCC2 (RX) Supply Voltage 2 (RX)V35

VCC (TX) Supply Voltage (TX)V10

TOP Operating Temperature °C -10 to 60

TSTG Storage Temperature °C -55 to 150

TSOL Soldering Temperature °C 260

tSOL Soldering Time sec. 4

Note:

1. Operation in excess of any one of these parameters may result

in permanent damage.

ISG2000DS

ELECTRICAL CHARACTERISTICS (VCC = 5 V, VCC2 = 24 V, TA = 25°C)

PART NUMBER ISG2000DS

SYMBOLS PARAMETERS UNITS MIN TYP MAX

RF Performance (TX)

fOP Operating Frequency Range MHz 5 55

Gain (VAGC = 0 V) dB 35

Gain (VAGC = 3.3 V) dB -30

VAGC Automatic Gain Control Voltage V 0 3.3

2nd Harmonic Level (Single Tone, POUT = +58 dBmV) dBc -53 -56

3rd Harmonic Level (Single Tone, POUT = +58 dBmV) dBc -53 -56

RLOUT Output Return Loss dB 10 6

TX ON On/Off Setting Time µS12

TX OFF On/Off Setting Time µS5

Power Requirements

Supply Voltage V1 RXV 4.5 5 5.5

Supply Voltage V2 RXV 22 24 31.5

Supply Current

Supply Voltage V1 TXV 4.5 5 9

ICC1 (RX) Supply Current 1 (RX) mA 240 320

ICC2 (RX) Supply Current 2 (RX) mA 1.5 2

ICC1 (TX) Supply Current 1 (TX) mA 80 110

Physical Interface

To the CATV Network Female

F-Connector

To the Motherboard 16 Pin Header

Physical Dimensions

L x W x H 3.4 x 2.0 x 0.5"

Environmental Specs

TOP Operating Temperature °C-5 60

TSTG Storage Temperature °C -40 75

ISG2000DS

Pin No. Pin Name Description Equivalent Circuit

1RFAGC

2VCC (TX)

3 TXEN

4 TXIN-

5 TXIN+

6 TXAGC

7 VCC2 (RX)

8 VCC1 (RX)

9 IFAGC

10 GND

PIN FUNCTIONS

The RFAGC pin is used to adjust gain in the

dual conversion tuner. This pin has a

positive gain vs. AGC slope. 20 dB of gain

control is available by varying the voltage

from 0.5 V to 3.3 V.

The VCC (TX) pin powers the TX amplifier. A

5 V bias is required and nominal current is

125 mA.

The TXEN pin is used to enable/disable the

TX amplifier. When TXEN is set LOW, the

TX amplifier is disabled. In this state, a

standby current of 3 mA is required from

VCC (TX). When TXEN is set HIGH, the TX

amplifier is enabled. In this state, a

nomimal current of 125 mA is required from

VCC (TX).

TXIN- is the inverting input to the TX

amplifier. The input frequency range spans

covers 5-55 MHz.

TXIN+ is the non-inverting input to the TX

amplifier. The input frequency range spans

covers 5-55 MHz.

The TXAGC pin is used to adjust gain in the

TX amplifier. The pin has a positive gain vs.

AGC slope. 50 dB of gain control is

available by varying the voltage from 0.5 V

to 3.0 V.

The VCC2 (RX) pin powers the loop filter for

the first LO. A bias of 24 V - 30 V is

required and maximum current draw is

2 mA.

The VCC1 (RX) pin powers the entire RX

section. A bias of 5 V is required and

nominal current draw is

250 mA.

The IFAGC pin is used to adjust gain in the

final downconverter stage of the RX section.

The pin has a positive gain vs. AGC slope.

30 dB of gain control is available by varying

the voltage from 0.5 to 2.0 V.

Ground.

1 K

0.1 µF

10 K

4 5

1 K

1000 p

ISG2000DS

Note:

1. For programming information, refer to National LMX2336 data sheet (http://www.national.com)

Pin No. Pin Name Description Equivalent Circuit

111CK

121DATA

131 LE

14 GND

15 IFOUT-

16 IFOUT+

PIN FUNCTIONS

Clock pin for the dual PLL. High impedance

CMOS input. Data for the various latches is

clocked in on the rising edge into a 20-bit

shift register.

Serial data pin for the dual PLL. High

impedance CMOS input. MSB entered first.

The last two bits are the control bits.

Latch enable pin for the dual PLL. High

impedance CMOS input. When LE goes

HIGH, data stored in the shift registers is

loaded into one of the 4 latches determined

by the 2 control bits.

Ground.

Inverting final IF output.

Non-inverting final IF output.

FIGURE 1

240 5.6 µH

2405.6 µH

DUAL PLL

CABLE

IN/OUT

91-860 MHz 43.75 MHz

5-42 MHz

TX IN

RX OUT

CK DATA LE

OUTLINE DIMENSIONS (Units in mm [inches])

ISG2000

16 Pin Header Connections/Location

1: RFAGC

2: VCC (T

)

3: TXEN

4: TXIN+

5: TXIN-

6: TXAGC

7: VCC2(R

)

8: VCC1(R

)

9: IFAGC

10: GND

11: CK

12: DATA

13: LE

14: GND

15: IFOUT-

16: IFOUT+

2 3 4 5 6 7 8 9 10 11 1213 14 15 16

18.9 [.744] 6.4 [.252]

15.9 [.626]

5.6 [.220]

F Connector

.5 [.020]

54.8 [2.157]

Pin 1

26.6 [1.047] 90.5 [3.563]

2.54

[.100]

87.3 [3.437]

14.25 [5.61]

3.8 [.150]

4.1 [.161]

27.8 [1.094] 5.0 [.197] DIA

2.2 [.087]

50.2 [1.976]

ISG2000DS

Table 1. Programmable Modes

Table 2. Mode Select Truth Table

C1 C2 R16 R17 R18 R19 R20

0 0 RF2 Phase RF2 ICPO RF2 DO RF2 LD RF2 FO

Detector TRI-STATE

Polarity

0 1 RF1 Phase RF1 ICPO RF1DO RF1 LD RF1 FO

Detector TRI-STATE

Polarity

C1 C2 N19 N20

1 0 RF2 Prescaler Pwdn RF2

1 1 RF1 Prescaler Pwdn RF1

Phase DO TRI-ST ATE ICPO1 RF1 RF2 Pwdn2

Detector Prescaler Prescaler

Polarity3

0 Negative Normal LOW 64/65 64/65 pwrd up

Operation

1 Positive TRI-STA TE HIGH 128/129 128/129 pwrd dn

Notes:

1. The ICPO LOW Current State = 1/4 x ICPO HIGH

Current.

2. Activitation of the RF2 PLL or RF1 PLL powerdown

modes result in the disabling of the respective N counter

divider and debiasing of its respective fIN inputs (to a

high impedance state). The powerdown function is

gated by the charge pump to prevent unwanted

frequency jumps. Once the powerdown program mode

is loaded, the part will go into powerdown mode when

the charge pump reaches a TRI-STATE condition. The

R counter and Oscillator functionality does not become

disabled until both RF2 and RF1 powerdown bits are

activated. The OSCIN is connected to VCC through a 100

kΩ resistor and the OSCOUT goes HIGH when this con-

dition exists. The MICROWAVETM control register re-

mains active and capable of loading and latching data

during all the powerdown modes.

3. Phase Detector Polarity

Depending upon VCO characteristics, the R16 bits

should be set accordingly:

When VCO characteristics are positive like (1), R16

should be set HIGH, when VCO characteristics are

negative like (2), R16 should be set LOW.

ISG2000DS

(1)

(2)

VCO CHARACTERISTICS

VCO Input Voltage

VCO Output Frequency

RF1 R (19) RF2 R (19) RF1 R (20) RF2 R (20) FOLD

(RF1 LD) (RF2 LD) (RF1 FO) (RF2 FO) Output State

0 0 0 0 Disabled1

0 1 0 0 RF2 Lock

Detect2

1 0 0 0 RF1 Lock

Detect2

1 1 0 0 RF1/RF2

Lock Detect2

X 0 0 1 RF2 Reference

Divider Output

X 0 1 0 RF1 Reference

Divider Output

X 1 0 1 RF2

Programmable

Divider Output

X 1 1 0 RF1

Programmable

Divider Output

0 0 1 1 Fastlock3

0 1 1 1 For internal

use only

1 0 1 1 For internal

use only

1 1 1 1 Counter Reset4

X - Don’t care condition

Table 3. The FOLD Output Truth Table

Notes:

1. When the FOLD output is disabled, it is actively pulled to a

low logic state.

2. Lock detect output provided to indicate when the VCO fre-

quency is in “lock”. When the loop is locked and a lock

detect mode is selected, the pin's output is HIGH, with nar-

row pulses LOW. In the RF1/RF2 lock detect mode a locked

condition is indicated when RF2 and RF1 are both locked.

3. The Fastlock mode utilized the FOLD output pin to switch a

second loop filter damping resistor to ground during fastlock

operation. Activation of Fastlock occurs whenever the RF

loop’s Icpo magnitude bit #17 is selected HIGH (while the

#19 and #20 mode bits are set for Fastlock).

4. The Counter Reset mode bits R19 and R20 when activated

reset all counters. Upon removal of the Reset bits the N

counter resumes counting in “close” alignment with R

counter. (The maximum error is one prescaler cycle). If

the Reset bits are activated the R counter is also forced to

Reset, allowing smooth acquisition upon powering up.

Serial Data Input Timing

DATA N20: WSB

(R20: WSB) C1: LSB

(C1: LSB)

N19

(R19) N10

(R10) N9

(R9) (R8) C2

(C2)

OR LE

CLOCK tCWL

tCS tCH tEWtCWH tES

Notes:

1. Parenthesis data indicates programmable reference

divider data.

2. Data shifted into register on clock rising edge.

3. Data is shifted in MSB first.

Test Conditions:

The Serial Data Input Timing is tested using a symmetrical

waveform around VCC/2. The test waveform has an edge

rate of 0.6V/ns with amplitudes of 2.2 V @ VCC = 2.7 V and

2.6 V @ VCC = 5.5 V.

Phase Comparator and Internal Charge Pump Character-

istics.

DoHZL

f > f

rp f = f

rp f < f

Notes:

1. Phase difference detection range: -2π to +2π

2. The minimum width pump up and pump down current pulses

occur at the DO pin when the loop is locked.

CALIFORNIA EASTERN LABORATORIES • Headquarters • 4590 Patrick Henry Drive • Santa Clara, CA 95054-1817 • (408) 988-3500 • Telex 34-6393 • FAX (408) 988-0279

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PRINTED IN USA ON RECYCLED PAPER -10/98

DATA SUBJECT TO CHANGE WITHOUT NOTICE