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AOZ1252
2A EZBuck™ Synchronous
Buck Regulator
General Description
The AOZ1252 is a high efficiency, low quiescent
current and simple to use 2A synchronous buck
regulator. This device operates from 4.5V to 26V
input voltage range and provides up to 2A of
continuous output current with an adjustable output
voltage down to 0.6V.
The AOZ1252 is offered in the Exposed Pad SO-8
package which is rated over a -40°C to +85°C
ambient temperature range.
Features
4.5V to 26V input voltage operation range
High efficiency PFM mode light load
performance
Synchronous rectification: 150mΩ integrated
high-side switch and 50mΩ internal low-side
switch
Integrated bootstrap diode
External soft start control
Adjustable output voltage down to 0.6V
2A continuous output current
Fixed frequency of PWM 620kHz operation
Tailored for small profile inductor and ceramic
capacitors
Cycle-by-cycle current limit
Short-circuit protection
Thermal shutdown
Standard exposed pad SO-8 package
-40°C to 150°C operating j unction temperature
range
Applications
High performance point-of-load DC/DC
converters
Notebook/ultra mobile PCs/servers
PCIe graphics cards/set top boxes
Set top boxes
DVD drives and HDD
LCD-TV/displays
Typical Application
Not Recommended For New Designs
Not Recommended For New Designs
Replacement Part: AOZ3101DI
AOZ125
2
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Ordering Information
Part Number Temperature Range Package Environmental
AOZ1252PI -40°C to +85°C EPAD SO-8 Green
AOS Green Products use reduced levels of Haloge ns, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
EPAD SO-8
(Top View)
Pin Description
Part Number Pin Name Pin Function
1 PGND Power Ground connection.
2 VIN Input Voltage Supply Pin. When VIN rises abov e the UVLO threshold the device starts up.
Note: Connect close decoupling capacitor from VIN to PGND to minimize input switching
loop.
3 BST
Bootstrap Connection for High-side NFET Gate Drive Input. Connect 1 0n F capacitor from
BST to LX.
4 SS Soft Start Input. Connect a capacitor between SS to GND for soft start time control.
5 COMP External Loop Compensation Input.
6 AGND Signal Ground Input.
7 FB
The Feedback Voltage Input. It is used to determine the out put voltage via a resistor divider
between the output and AGND.
8 VDD Internal LDO Voltage Output. Connect a 1µF capacitor close to VDD to AGND.
Exposed Pad LX Output Connection to Inductor. Thermal connectio n for output stage.
VIN
BST Exposed Pad
LX
2
3
SS 4
PGND 1
FB
AGND
7
6
COMP
5
VDD
8
Not Recommended For New Designs
AOZ125
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Functional Block
Not Recommended For New Designs
AOZ125
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Absolute Maximum Ratings
Exceeding the Absolute Maximum Ratings may damage the
device.
Parameter Rating
Supply Voltage (VIN) 30V
LX to GND -0.7V to VIN+0.3V
SS to GND -0.3V to +6V
BST to LX -0.3V to +6V
FB to GND -0.3V to +6V
COMP to GND -0.3V to +6V
Junction Temperature (TJ) +150°C
Storage Temperature (TS) -65°C to +150°C
ESD Rating(1) 2kV
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Recommended Operating Ratings
This device is not guaranteed to operate beyond the
Recommended Operating Ratings.
Parameter Rating
Supply Voltage (VIN) 4.5V to 26V
Output Voltage (VOUT) 0.6V to VIN
Ambient Temperature (TA) -40°C to +85°C
Package Thermal Resistance
EPAD SO-8 (
JA) 50°C/W
Electrical Characteristics
TA = 25°C, VVIN = 12V, VSS = 2.5V, VOUT = 3.3V unless otherwise specified. Specifications in BOLD indicate an ambient
temperature range of -40°C to +85°C.
Symbol Parameter Conditions Min. Typ. Max Units
VVIN Supply Voltage 4.5 26 V
VUVLO Input Under-Voltage Lockout
Threshold VVIN rising
VVIN falling
3.3 4.1 V
IVIN Supply Current (Quiescent) IOUT = 0, VFB = 0.8V 0.9 1.5 mA
IOFF Shutdown Supply Current VSS = 0V 20 µA
VVDD LDO Voltage VVIN > 6V 5.2 V
VFB Feedback Voltage 591 600 609 mV
VFB_LOAD Load Regulation 0.8A < IOUT < 3.2A 0.5 %
VFB_LINE Line Regulation 6V < VVIN < 26V, Load = 1A 0.05 %/V
IFB Feedback Input Current VFB = 0.6V 100 nA
VSS_OFF Enable Threshold Off threshold
0.4 V
ISS SS Source Current VSS = 2.0V -30 2.5 30 µA
Modulator
Fs Frequency 500 620 740 kHz
DMAX Maximum Duty Cycle 87 %
TON_MIN Minimum On Time 80 ns
GMSYS System Loop Transconduct ance IOUT/VCOMP 5 A/V
GMEA Error Amplifier Transconductance 1 mA/V
Protection
ILIM Current Limit 3 3.5 A
TOTP_RISE Over-Temperature Shutdown
Limit Temperature rising 155 °C
TOTP_FALL Temperature falling 115 °C
Outputs
RDSON_HS High-Side Switch ON Resistance 150 190
mΩ
RDSON_LS Low-Side Switch ON Resistance 50 80
mΩ
Not Recommended For New Designs
AOZ125
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Typical Performance Characteristics
TA = 25°C, VIN = 12V, VOUT = 1.2V unless otherwise specified.
Not Recommended For New Designs
AOZ125
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Detailed Description
The AOZ1252 is a high efficiency current-mode buck
regulator with integrated both high-side and low-side
NMOS switches. It has a wide operating input voltage
range of 4.5V to 26V and can supply up to 2A of output
load current. AOZ1252’s key protection features include
input under voltage lockout, output over voltage
protection, cycle by cycle current limit, fault short
protection and thermal shut down. The AOZ1252 is
available in the exposed pad SO-8 package.
Soft Start
AOZ1252 starts a soft start that can be adjusted by an
external capacitor. The internal 2.5µA current source
starts to charge the external capacitor through the soft-
start pin. When soft-start voltage is higher than internal
enable threshold voltage, the IC starts to switch with
minimum on-time. With the soft-start voltage further
increasing, the IC starts to switch with wider on-time,
which drives the output (FB) following the soft-start
voltage until output reaches the pre-set value. The
output soft-start time can be calculated by:
SS
SS
SS I
C
T 6.0
Light Load and PWM Operation
Under low output current settings, AOZ1252 will
operate in light load mode to obtain high efficiency. The
two modes of operation, PFM and PWM are determined
by the peak inductor current level and the output
feedback voltage. For very low output current and
consequently low peak inductor current, AOZ1252 will
operate under critical inductor current mode if FB
voltage is lower than threshold of VH_PFM. VH_PFM is
10mV higher than normal voltage reference. If output is
higher than that value, IC will turn-off to keep high light
load efficiency. As the output current increases, the IC
will leave PFM mode and will enter PWM mode
operating in fixed frequency continuous conduction
mode (CCM). In CCM mode, AOZ1252 operates with
the low side MOSFET switching in synchronous
rectification to obtain high efficiency performance.
Error Amplifier
AOZ1252 uses an error amplifier that has a
transconductance of 1000µA/V. Closed loop stability is
realized through the frequency compensation network
connected between COMP to AGND. (Refer to Loop
Compensation)
Slope Compensation
A slope compensation ramp is also added in the control
loop design to prevent sub harmonic oscillations. There
is sufficient inductor current information to obtain stabile
current mode operation. The output voltage is divided
by the resistive voltage divider at the FB pin. The
internal transconductance error amplifier then amplifies
the difference between the voltages at FB with the
reference voltage. The error signal voltage is an input to
the COMP and is compared against the current signal
which consists of both the inductor current and slope
comp ramp at the PWM comparator input. If this current
signal is less than the error voltage the high side switch
will turn on.
Switching Frequency
The AOZ1252 has a fixed switching frequency under
PWM mode of operation through an internal oscillator.
Its nominal switching frequency is set to 600kHz.
Not Recommended For New Designs
AOZ125
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Output Voltage Setting
The output voltage is set by a resistor divider network of
R1 and R2, by feeding back the output to the FB pin.
The output setting is defined by:
2
1
16.0 R
R
VO
Below Table 1 lists popular regulated outputs and the
corresponding values of R1, R2.
VO (V) R1 (kΩ) R2 (kΩ)
0.6 Open
1.0 6.67 10
1.5 15 10
1.8 20 10
2.5 31.7 10
3.3 45 10
5.0 73.3 10
Table 1.Output Voltage Setting
with Resistor Divider
The combination of R1 and R2 should be large enough
to avoid drawing excessive current from the output that
contributes to power loss. Since the switch duty cycle
can be as high as 100%, the maximum output voltage
can be set as high as the input voltage minus the
voltage drop of the high side NMOS and inductor .
Over Current Protection (O CP)
The primary signal used in over current protection is the
peak inductor. By employing peak current mode control,
the COMP voltage is proportional to the peak inductor
current. This voltage falls between the range of 0.4V
and 2.5V, increasing with output load current. AOZ1252
utilizes cycle by cycle current limit and limits the peak
inductor current. A preset current limit voltage is used
as a reference trip point. When the output current
exceeds the current limit range, the high side switch will
stop switching.
Under fault conditions where the output maybe shorted
to ground, VOUT will drop rapidly and AOZ1252’s
protection circuit will force the inductor current to decay
once the OCP level is reached within several switching
cycles. This feature helps to prevent catastrophic failure
and recovery of the IC once the short is removed.
AOZ1252 will initiate a soft start once the over-current
condition is removed.
Thermal Protection
An internal temperature sensor monitors the junction
temperature of the controller. The internal control circuit
shuts down the high-side NMOS once the junction
temperature exceeds 150ºC. The regulator has a 50°
hysteresis and will automatically restart when the
junction temperature decreases to 100ºC.
Input capacitor
The input bypass capacitor must be connected very
closely to the VIN and PGND pins of AOZ1252. This
mainly to ensure that proper filtering is maintained to
filter out the pulsing input current inherent to buck
regulator switching. The voltage rating of input
capacitor is selected to be higher than maximum input
voltage plus the input ripple voltage.
The input ripple voltage can be approximated by
equation below:
IN
O
IN
O
IN
O
IN V
V
V
V
Cf I
V
1
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
one key concern when selecting the capacitor. For a
buck regulator, the RMS value of input capacitor current
can be calculated by:
IN
O
IN
O
ORMSCIN V
V
V
V
II 1
_
m equals the conversion ratio:
m
V
V
IN
O
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 1 below. It can be seen that when VO is
half of VIN, CIN is under the worst current stress. The
worst current stress on CIN is 0.5·IO.
Figure 1. ICIN vs. Voltage Conversion Ratio
Not Recommended For New Designs
AOZ125
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To ensure reliable operation, the input capacitors must
be selected to have a current rating higher than ICIN-RMS
at the worst operating conditions. Ceramic capacitors
are preferred for input capacitors because of their low
ESR and high current rating. Depending on the
application circuits, other low ESR tantalum capacitor
may also be used. When selecting ceramic capacitors,
X5R or X7R type dielectric ceramic capacitors should
be used for their better temperature and voltage
characteristics. Note that the ripple current rating from
capacitor manufactures is based on certain amount of
life time. Further de-rating may be necessary in
practical design.
Inductor
The inductor is used to supply constant current to
output when it is driven by a switching voltage. For
given input and output voltage, inductance and
switching frequency together decide the inductor ripple
current, which is:
IN
OO
LV
V
LfV
I1
The peak inductor current is:
2L
OLpeak I
II
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be 20% to
30% of output current.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor needs to be checked
for thermal and efficiency requirem ents.
Surface mount inductors in different shape and styles
are available from Coilcraft, Elytone and Murata.
Shielded inductors are small and radiate less EMI
noise. But they cost more than unshielded inductors.
The choice depends on EMI requirement, price and
size.
Output Capacitor
The output capacitor is selected based on the DC
output voltage rating, output ripple voltage specification
and ripple current rating. The selected output capacitor
must have a higher rated voltage specification than the
maximum desired output voltage including ripple. De-
rating needs to be considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
O
COLO Cf
ESRIV 81
where,
CO is output capacitor value and
ESRCO is the Equivalent Series Resistor of output
capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the
switching frequency dominates. Output ripple is mainly
caused by capacitor value and inductor ripple current.
The output ripple voltage calculation can be simplified
to:
O
LO Cf
IV
81
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The
output ripple voltage calculation can be further
simplified to:
COLO ESRIV
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric
type of ceramic, or other low ESR tantalum are
recommended to be used as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It
can be calculated by:
12
_L
RMSCO I
I
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the b uck inductor is select ed to be very sma l l and
inductor ripple current is high, output capacitor could be
overstressed.
Not Recommended For New Designs
AOZ125
2
Page 9 of 9 Rev. 1.1 March 2012 www.aosmd.com
Loop Compensation
The AOZ1252 employs peak current mode control for
ease-of-use and fast transient response. Peak current
mode control eliminates the double pole effect of the
output L&C filter. It greatly simplifies the compensation
loop design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
LO
pRC
f
21
1
The zero is an ESR zero due to output capacitor and
it’s ESR. It is can be calculated by:
COO
ZESRC
f
21
1
where,
CO is the output filter capacitor;
RL is load resistor value; and
ESRCO is the equivalent series resistance of output
capacitor.
The compensation design is actually to shape the
converter control loop transfer function to get desired
gain and phase. Several different types of
compensation network can be used for the AOZ1252.
For most cases, a series capacitor and resistor network
connected to the COMP pin sets the pole-zero and is
adequate for a stable high-bandwidth control loop.
In the AOZ1252, FB pin and COMP pin are the
inverting input and the output of internal error amplifier.
A series R and C compensation network connected to
COMP provides one pole and one zero. The pole is:
VEAC
EA
pGC
G
f
2
2
where,
GEA is the error amplifier transconductance, which is
1000·10-6 A/V;
GVEA is the error amplifier voltage gain, which is 500
V/V; and
CC is compensation capacitor in the Typical Application
schematic on the first page.
The zero given by the external compensation network,
capacitor CC and resistor RC is located at:
CC
ZRC
f
21
2
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The
system crossover frequency is where control loop has
unity gain. The crossover is the also called the
converter bandwidth. Generally a higher bandwidth
means faster response to load transient. However, the
bandwidth should not be too high because of system
stability concern. When designing the compensation
loop, converter stability under all line and load condition
must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. It is
recommended to choose a crossover frequency equal
or less than 60kHz.
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to
calculate RC:
CSEA
O
FB
O
CC GG C
V
V
fR
2
where,
fC is desired crossover frequency. For best
performance, fC is set to be about 1/10 of switching
frequency;
VFB is 0.6V;
GEA is the error amplifier transconductance, which is
1000·10-6 A/V; and
GCS is the current sense circuit transconductance,
which is 4 A/V.
The compensation capacitor CC and resistor RC
together make a zero. This zero is put somewhere
close to the dominate pole fp1 but lower than 1/5 of
selected crossov er fr equency. CC can is selected by:
1
25.1
pC
CFR
C
Equation above can also b e simplified to:
C
LO
CRRC
C
Not Recommended For New Designs
AOZ125
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PCB Layout Consideration
As with all high current switching buck regulators, circuit
board layout is the key in preventing inductive
overshoots and undershoots transient spikes. There are
essentially two high pulsing current loops in a
synchronous buck converter. The first switching loop is
formed when the high-side MOSFET is switched on.
The circulating current flows from the input capacitors,
to the filter inductor, to the output capacitors (load),
then returns to the input capacitor through power
ground. It is imperative that a low inductive ceramic
capacitor be placed directly across VIN (PIN2) and
PGND (PIN1) to reduce the switching loop during the
high side turn on transition.
The second loop is formed when the low-side MOSFET
is switched on during synchronous operation. This loop
is formed from the inductor, to the output capacitors
(load), then returns through the low-side MOSFET. The
PCB layout for the AOZ1252 is shown below. It can be
seen that the input bypassing capacitors are placed in
close proximity to VIN and PGND. Analog ground and
power grounds are separated to filter out noise from the
main power switching loops. The sensitive nodes that
require connection through analog ground (AGND) are
COMP, FB, and VSS.
PCB guideline that can be helpful :
1. The exposed (LX) node serves as the interconnect
of both high-side and low-side MOSFETs. It is
suggested that a large copper plane added
underneath the IC to improve thermal dissipation.
2. To improve high-side thermal dissipation, maximize
the copper area conne cted to the VIN pin.
3. The input capacitor should be connected in close
proximity to the VIN pin and the PGND pins.
4. A ground plane is strongly recommended. Separate
PGND from AGND and connect them at a single
point to avoid noise coupling.
5. Form a short wide trace from LX to the output
inductor and capacitors.
6. The LX switching node is the noisiest of all pins;
therefore, all sensitive nodes must be far away from
this pin.
Not Recommended For New Designs
AOZ125
2
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Package Dimensions, Exposed Pad SO-8
Not Recommended For New Designs
AOZ125
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Tape and Reel Dimensions, Exposed Pad SO-8
Not Recommended For New Designs
AOZ125
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Part Marking
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha and Omega Semiconductor reserves the right to make changes at any time without n otice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body or (b) support or su stain life, and (c)
whose failure to perform when prope rly used in
accordance with instructions for use p ro v ided in the
labeling, can be reasonabl y expected to result in a
significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failu re of the life suppo rt
device or system, or to affect its safety or effectiveness.
A
OZ1252PI
(EPAD SO-8)
Z1252PI
FA Part Number Code
Assembly Lot Code
Year & Week Code
LTYW
Fab & Assembly Location
Not Recommended For New Designs
