MR256A08BCSO35 - EVERSPIN TECHNOLOGIES

MR256A08B

MR256A08B Rev. 6.5 3/2018

32K x 8 MRAM

The MR256A08B is a 262,144-bit magnetoresistive random access

memory (MRAM) device organized as 32,768 words of 8 bits. The

MR256A08B oers SRAM compatible 35ns read/write timing with un-

limited endurance.

Data is always non-volatile for greater than 20-years. Data is automatically protected on

power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specication.

The MR256A08B is the ideal memory solution for applications that must permanently store

and retrieve critical data and programs quickly.

The MR256A08B is available in a small footprint 400-mil, 44-lead plastic small-outline TSOP

type-2 package, or an 8 mm x 8 mm, 48-pin ball grid array (BGA) package. (The 32-SOIC

package options is obsolete and no longer available for new orders.) All package footprints

are compatible with similar low-power SRAM products and other non-volatile RAM products.

The MR256A08B provides highly reliable data storage over a wide range of temperatures.

The product is oered with commercial temperature (0 to +70 °C) and industrial temperature

(-40 to +85 °C) range options.

FEATURES

BENEFITS

• One memory replaces FLASH, SRAM, EEPROM and MRAM

in system for simpler, more ecient design

• Improves reliability by replacing battery-backed SRAM

• 3.3 Volt power supply

• Fast 35 ns read/write cycle

• SRAM compatible timing

• Native non-volatility

• Unlimited read & write endurance

• Data always non-volatile for >20 years at temperature

• Commercial and industrial temperatures

• All products meet MSL-3 moisture sensitivity level

• RoHS-Compliant TSOP2 and BGA packages

INTRODUCTION

48-ball FBGA

44-pin TSOP2

RoHS

MR256A08B Rev. 6.5 3/2018

MR256A08B

TABLE OF CONTENTS

FEATURES .............................................................................................................................................1

BENEFITS ...............................................................................................................................................1

INTRODUCTION ...................................................................................................................................1

BLOCK DIAGRAM AND PIN ASSIGNMENTS .......................................................................................4

Figure 1 – MR256A08B Block Diagram.................................................................................................................. 4

Table 1 – MR256A08B Pin Functions...................................................................................................................... 4

Figure 2 – Pin Diagrams for Available Packages (Top View) 1 ...................................................................... 5

Table 2 – Operating Modes ....................................................................................................................................... 5

ELECTRICAL SPECIFICATIONS ............................................................................................................6

Absolute Maximum Ratings ...........................................................................................................6

Table 3 – Absolute Maximum Ratings ................................................................................................................... 6

OPERATING CONDITIONS ...................................................................................................................7

Table 4 – Operating Conditions ............................................................................................................................... 7

Power Up and Power Down Sequencing .......................................................................................8

Figure 3 – Power Up and Power Down Sequencing Timing Diagram ....................................................... 8

DC CHARACTERISTICS .........................................................................................................................9

Table 5 – DC Characteristics ...................................................................................................................................... 9

Table 6 – Power Supply Characteristics ..............................................................................................................10

TIMING SPECIFICATIONS ................................................................................................................. 11

Table 7 – Capacitance ...............................................................................................................................................11

Table 8 – AC Measurement Conditions ..............................................................................................................11

Figure 4 – Output Load Test Low and High ....................................................................................................... 11

Figure 5 – Output Load Test All Others ...............................................................................................................11

Read Mode .................................................................................................................................... 12

Table 9 – Read Cycle Timing ...................................................................................................................................12

MR256A08B

MR256A08B Rev. 6.5 3/2018

Figure 6 – Read Cycle 1 .............................................................................................................................................12

Figure 7 – Read Cycle 2 .............................................................................................................................................13

Write Mode .................................................................................................................................... 14

Table 10 – Write Cycle Timing 1 (W Controlled) ..............................................................................................14

Figure 8 – Write Cycle Timing 1 (W Controlled) ..............................................................................................15

Table 11 – Write Cycle Timing 2 (E Controlled) ................................................................................................16

Figure 9 – Write Cycle Timing 2 (E Controlled) ................................................................................................17

ORDERING INFORMATION ............................................................................................................... 18

Table 12 – Ordering Part Number System for Parallel I/O MRAM..............................................................18

Table 13 – MR256A08B Ordering Part Numbers 1 .......................................................................................... 19

PACKAGE OUTLINE DRAWINGS ....................................................................................................... 20

Figure 10 – 44-TSOP2 Package Outline...............................................................................................................20

Figure 11 – 48-BGA Package Outline ...................................................................................................................21

Figure 12 – 32-SOIC Package Outline 1 ..............................................................................................................22

REVISION HISTORY ........................................................................................................................... 23

HOW TO CONTACT US ....................................................................................................................... 24

TABLE OF CONTENTS CONT’D

MR256A08B Rev. 6.5 3/2018

MR256A08B

CHIP

ENABLE

BUFFER

OUTPUT

ENABLE

BUFFER

ADDRESS

BUFFER

WRITE

ENABLE

BUFFER

OUTPUT ENABLE

32K x 8 BIT

MEMORY

ARRAY

ROW

DECODER

COLUMN

DECODER

SENSE

AMPS

OUTPUT

BUFFER

WRITE

DRIVER

FINAL

WRITE

DRIVERS

WRITE ENABLE

A[14:0]

DQ[7:0]

Figure 1 – MR256A08B Block Diagram

Table 1 – MR256A08B Pin Functions

Signal

Name

Function

A Address Input

E Chip Enable

W Write Enable

G Output Enable

DQ Data I/O

VDD Power Supply

VSS Ground

DC Do Not Connect

NC No Connection - Pin 2, 40, 41,43 (TSOP2); Ball C2, C5, D3, F2, F5, G1, G2, G6, H1, H6 (BGA); Pin 9,

24, 31(SOIC) Reserved For Future Expansion

BLOCK DIAGRAM AND PIN ASSIGNMENTS

MR256A08B

MR256A08B Rev. 6.5 3/2018

123456

G A A A A

AAEB

DQ AA

DQ C

VSS

VDD D

VDD

VSS E

DQ F

NCNC

DCDC

DQ3

VSS

VDD

A14

Figure 2 – Pin Diagrams for Available Packages (Top View) 1

Table 2 – Operating Modes

E 1G 1W 1Mode VDD Current DQ[7:0] 2

H X X Not selected ISB1, ISB2 Hi-Z

L H H Output disabled IDDR Hi-Z

L L H Byte Read IDDR DOut

L X L Byte Write IDDW Din

Notes:

1. H = high, L = low, X = don’t care

2. Hi-Z = high impedance

48 Pin FBGA32 Pin SOIC 1

44 Pin TSOP2

VDD

VSS

DC 22

44 DC

VSS

VDD

NC NC

A14

A12

DQ0

DQ1

VDD

A13

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

VSS

Note:

1. The 32-SOIC package is obsolete and shown for legacy reference only. This package option is no longer

available for new orders.

MR256A08B Rev. 6.5 3/2018

MR256A08B

ELECTRICAL SPECIFICATIONS

This device contains circuitry to protect the inputs against damage caused by high static voltages or

electric elds; however, it is advised that normal precautions be taken to avoid application of any voltage

greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic elds. Precautions should be taken to avoid

application of any magnetic eld more intense than the maximum eld intensity specied in the maximum

ratings. 1

Parameter Symbol Value Unit

Supply voltage 2VDD -0.5 to 4.0 V

Voltage on an pin 2VIN -0.5 to VDD + 0.5 V

Output current per pin IOUT ±20 mA

Package power dissipation 3PD0.600 W

Temperature under bias

MR256A08B (Commercial)

MR256A08BC (Industrial) TBIAS

-10 to 85

-45 to 95

°C

Storage Temperature Tstg -55 to 150 °C

Lead temperature during solder (3 minute max) TLead 260 °C

Maximum magnetic eld during write Hmax_write 2000 A/m

Maximum magnetic eld during read or standby Hmax_read 8000 A/m

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional oper-

ation should be restricted to recommended operating conditions. Exposure to excessive voltages

or magnetic elds could aect device reliability.

2. All voltages are referenced to VSS.

3. Power dissipation capability depends on package characteristics and use environment.

Table 3 – Absolute Maximum Ratings

Absolute Maximum Ratings

MR256A08B

MR256A08B Rev. 6.5 3/2018

Parameter Symbol Min Typical Max Unit

Power supply voltage VDD 3.0 13.3 3.6 V

Write inhibit voltage VWI 2.5 2.7 3.0 1 V

Input high voltage VIH 2.2 - VDD + 0.3 2 V

Input low voltage VIL -0.5 3- 0.8 V

Temperature under bias

MR256A08B (Commercial)

MR256A08BC (Industrial)

TA0

-40

°C

Notes:

1. There is a 2 ms startup time once VDD exceeds VDD,(min). See “Power Up and Power Down Sequencing Timing Diagram”.

2. VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.

3. VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.

Table 4 – Operating Conditions

OPERATING CONDITIONS

MR256A08B Rev. 6.5 3/2018

MR256A08B

Figure 3 – Power Up and Power Down Sequencing Timing Diagram

BROWNOUT or POWER LOSS

NORMAL

OPERATION

VDD

READ/WRITE

INHIBITED

VWI

2 ms

READ/WRITE

INHIBITED

VIH

STARTUP

NORMAL

OPERATION

2 ms

RECOVER

VIH

The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min),

there is a startup time of 2 ms before read or write operations can start. This time allows memory power sup-

plies to stabilize.

The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain

high for the startup time. In most systems, this means that these signals should be pulled up with a resistor

so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should

hold the signals high with a power-on reset signal for longer than the startup time.

During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be

observed when power returns above VDD(min).

Power Up and Power Down Sequencing

MR256A08B

MR256A08B Rev. 6.5 3/2018

Parameter Symbol Min Typical Max Unit

Input leakage current Ilkg(I) - - ±1 μA

Output leakage current Ilkg(O) - - ±1 μA

Output low voltage

(IOL = + 4 mA)

(IOL = + 100 μA)

VOL - - 0.4

VSS + 0.2

Output high voltage

(IOL = - 4 mA)

(IOL = - 100 μA)

VOH 2.4

VDD - 0.2

- - V

Table 5 – DC Characteristics

DC CHARACTERISTICS

MR256A08B Rev. 6.5 3/2018

MR256A08B

Table 6 – Power Supply Characteristics

Parameter Symbol Typical Max Unit

AC active supply current - read modes 1

(IOUT= 0 mA, VDD= max) IDDR 25 30 mA

AC active supply current - write modes 1

(VDD= max)

MR256A08B (Commercial)

MR256A08BC (Industrial)

IDDW 55

AC standby current

(VDD= max, E = VIH)

no other restrictions on other inputs

MR256A08B (Commercial)

MR256A08BC (Industrial)

ISB1 6

8mA

CMOS standby current

(E ≥ VDD - 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD - 0.2 V)

(VDD = max, f = 0 MHz)

MR256A08B (Commercial)

MR256A08BC (Industrial)

ISB2 5

7mA

Notes:

1. All active current measurements are measured with one address transition per cycle and at minimum cycle time.

MR256A08B

MR256A08B Rev. 6.5 3/2018

TIMING SPECIFICATIONS

Table 7 – Capacitance

Parameter 1Symbol Typical Max Unit

Address input capacitance CIn - 6 pF

Control input capacitance CIn - 6 pF

Input/Output capacitance CI/O - 8 pF

Notes:

1. f = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.

Table 8 – AC Measurement Conditions

Figure 4 – Output Load Test Low and High

Figure 5 – Output Load Test All Others

Parameter Value Unit

Logic input timing measurement reference level 1.5 V

Logic output timing measurement reference level 1.5 V

Logic input pulse levels 0 or 3.0 V

Input rise/fall time 2 ns

Output load for low and high impedance parameters See Figure 4

Output load for all other timing parameters See Figure 5

Output

L= 1.5 V

RL= 50 Ω

ZD= 50 Ω

Output

435 Ω

590 Ω

5 pF

3.3 V

MR256A08B Rev. 6.5 3/2018

MR256A08B

Parameter 1Symbol Min Max Unit

Read cycle time tAVAV 35 - ns

Address access time tAVQV - 35 ns

Enable access time 2 tELQV - 35 ns

Output enable access time tGLQV - 15 ns

Output hold from address change tAXQX 3 - ns

Enable low to output active 3 tELQX 3 - ns

Output enable low to output active 3 tGLQX 0 - ns

Enable high to output Hi-Z 3 tEHQZ 0 15 ns

Output enable high to output Hi-Z 3 tGHQZ 0 10 ns

Notes:

1. W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be

minimized or eliminated during read or write cycles.

2. Addresses valid before or at the same time E goes low.

3. This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage.

Table 9 – Read Cycle Timing

Read Mode

Figure 6 – Read Cycle 1

A (ADDRESS)

Q (DATA OUT)

tAVAV

tAXQX

tAVQV

Previous Data Valid Data Valid

MR256A08B

MR256A08B Rev. 6.5 3/2018

Figure 7 – Read Cycle 2

A (ADDRESS)

E (CHIP ENABLE)

G (OUTPUT ENABLE)

Q (DATA OUT)

Data Valid

tAVAV

tAVQV

tELQV

tELQX

tGHQZ

tEHQZ

tGLQV

tGLQX

MR256A08B Rev. 6.5 3/2018

MR256A08B

Table 10 – Write Cycle Timing 1 (W Controlled)

Parameter 1Symbol Min Max Unit

Write cycle time 2 tAVAV 35 - ns

Address set-up time tAVWL 0 - ns

Address valid to end of write (G high) tAVWH 18 - ns

Address valid to end of write (G low) tAVWH 20 - ns

Write pulse width (G high)

tWLWH

tWLEH 15 - ns

Write pulse width (G low)

tWLWH

tWLEH 15 - ns

Data valid to end of write tDVWH 10 - ns

Data hold time tWHDX 0 - ns

Write low to data Hi-Z 3 tWLQZ 0 12 ns

Write high to output active 3 tWHQX 3 - ns

Write recovery time tWHAX 12 - ns

Notes:

1. All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or

after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must re-

main in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being

asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

2. All write cycle timings are referenced from the last valid address to the rst transition address.

3. This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any

given voltage or temperature, tWLQZ(max) < tWHQX(min)

Write Mode

MR256A08B

MR256A08B Rev. 6.5 3/2018

A (ADDRESS)

E (CHIP ENABLE)

W (WRITE ENABLE)

Q (DATA OUT)

D (DATA IN)

AVAV

AVWH

WHAX

WLEH

WHDX

DVWH

WHQX

AVWL

Hi-Z Hi-Z

WLQZ

WLWH

Data Valid

Figure 8 – Write Cycle Timing 1 (W Controlled)

MR256A08B Rev. 6.5 3/2018

MR256A08B

Table 11 – Write Cycle Timing 2 (E Controlled)

Parameter 1Symbol Min Max Unit

Write cycle time 2 tAVAV 35 - ns

Address set-up time tAVEL 0 - ns

Address valid to end of write (G high) tAVEH 18 - ns

Address valid to end of write (G low) tAVEH 20 - ns

Enable to end of write (G high)

tELEH

tELWH 15 - ns

Enable to end of write (G low) 3tELEH

tELWH 15 - ns

Data valid to end of write tDVEH 10 - ns

Data hold time tEHDX 0 - ns

Write recovery time tEHAX 12 - ns

Notes:

1. All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain

in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being as-

serted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

2. All write cycle timings are referenced from the last valid address to the rst transition address.

3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the

same time or before W goes high, the output will remain in a high-impedance state.

MR256A08B

MR256A08B Rev. 6.5 3/2018

Figure 9 – Write Cycle Timing 2 (E Controlled)

A (ADDRESS)

E (CHIP ENABLE)

W (WRITE ENABLE)

Q (DATA OUT)

D (DATA IN)

tAVAV

tAVEH tEHAX

tELEH

tEHDX

tDVEH

tAVEL

Hi-Z

tELWH

Data Valid

MR256A08B Rev. 6.5 3/2018

MR256A08B

ORDERING INFORMATION

Table 12 – Ordering Part Number System for Parallel I/O MRAM

Memory Density Type I/O Width Rev. Temp Package Speed Packing Grade

Example Ordering Part Number MR 256 A 08 B C MA 35 R

MRAM MR

256 Kb 256

1 Mb 0

4 Mb 2

16 Mb 4

Async 3.3v

Async 3.3v Vdd and 1.8v Vddq

Async 3.3v Vdd and 1.8v Vddq with 2.7v min. Vdd

8-bit 08

16-bit 16

Rev A A

Rev B B

Commercial 0 to 70°C Blank

Industrial -40 to 85°C C

Extended -40 to 105°C V

AEC Q-100 Grade 1 -40 to 125°C M

44-TSOP-2 YS

48-FBGA MA

16-SOIC SC

32-SOIC SO

35 ns 35

45 ns 45

Tray Blank

Tape and Reel R

Engineering Samples ES

Customer Samples Blank

Mass Producon Blank

MR256A08B

MR256A08B Rev. 6.5 3/2018

Table 13 – MR256A08B Ordering Part Numbers 1

Temp Grade Temp Package Shipping Ordering Part Number

Commercial 0 to +70 °C

44-TSOP2 Tray MR256A08BYS35

Tape and Reel MR256A08BYS35R

48-BGA Tray MR256A08BMA35

Tape and Reel MR256A08BMA35R

32-SOIC 1 Tray MR256A08BSO35 Obsolete

Tape and Reel MR256A08BSO35R Obsolete

Industrial -40 to +85 °C

44-TSOP2 Tray MR256A08BCYS35

Tape and Reel MR256A08BCYS35R

48-BGA Tray MR256A08BCMA35

Tape and Reel MR256A08BCMA35R

32-SOIC 1 Tray MR256A08BCSO35 Obsolete

Tape and Reel MR256A08BCSO35R Obsolete

1 The 32-SOIC package option is obsolete and no longer available. See PCN02895 here.

MR256A08B Rev. 6.5 3/2018

MR256A08B

Figure 10 – 44-TSOP2 Package Outline

PACKAGE OUTLINE DRAWINGS

Not To Scale

1. Dimensions and tolerances per ASME Y14.5M - 1994.

2. Dimensions in Millimeters.

3. Dimensions do not include mold protrusion.

4. Dimension does not include DAM bar protrusions.

5. DAM Bar protrusion shall not cause the lead width to

exceed 0.58.

MR256A08B

MR256A08B Rev. 6.5 3/2018

Figure 11 – 48-BGA Package Outline

TOP VIEW

BOTTOM VIEW SIDE VIEW

0.41

0.31 0.32

0.22

Not To Scale

1. Dimensions in Millimeters.

2. Dimensions and tolerances per ASME Y14.5M - 1994.

3. Maximum solder ball diameter measured parallel to DATUM A

4. DATUM A, the seating plane is determined by the spherical crowns

of the solder balls.

surface of package.

Obsolete

MR256A08B Rev. 6.5 3/2018

Figure 12 – 32-SOIC Package Outline 1

Unit A B C D E F G H I J K

mm - Min

- Max

20.574

20.878

1.00

1.50

0.355

0.508

0.66

0.81

0.101

0.254

2.286

2.540

Radius

0.101

0.533

1.041

0.152

0.304

7.416

7.594

10.287

10.642

inch - Min

- Max

0.810

0.822

0.04

0.06

0.14

0.02

0.026

0.032

0.004

0.010

0.09

0.10

Radius

0.0040

0.021

0.041

0.006

0.012

0.292

0.299

0.405

0.419

1 16

32 17

PIN 1 ID

E F

Reference JEDEC MO-119

Note:

1. The 32-SOIC package is obsolete and shown for legacy reference only. This package option is no longer

available for new orders.

MR256A08B

MR256A08B Rev. 6.5 3/2018

Revision Date Description of Change

0 Sept 12, 2008 Initial Advance Information Release

1 Mar 25, 2009 Add Industrial and Automotive Temperature Options

2 August 16, 2011 Removed Automotive temperature options. Included SOIC package.

Revised formatting

3 October 28, 2011

Changed TSOP-II to TSOP2. Changed logo to new EST Logo. Revisions to

Available Parts, Table 4.1: Added Industrial Temp Grade option in SOIC

package. Deleted Tape & Reel pack option for all SOIC packaged parts.

4 Dec 9, 2011

Figure 2.1 cosmetic update. Figure 5.2 BGA package outline drawing

revised for package ball size. Revisions to ISB1, ISB2 and IDDW for Indus-

trial Grade options in Table 2.4.

5 July 9, 2013 MR256A08BCSO35 removed Preliminary status. Now MP.

6 October 11, 2013 Added Tape and Reel shipping option for SOIC packaged products. Re-

formatted to current standards.

6.1 May 19, 2015 Revised Everspin contact information.

6.2 June 11, 2015 Corrected Japan Sales Oce telephone number.

6.3 July 20, 2015 32-SOIC package options Not Recommended for New Designs.

6.4 October 17, 2015 32-SOIC package options are obsolete and no longer available.

6.5 March 23, 2018 Updated the Contact Us table

REVISION HISTORY

MR256A08B Rev. 6.5 3/2018

MR256A08B

Everspin Technologies, Inc.

Information in this document is provided solely to enable system and

software implementers to use Everspin Technologies products. There

are no express or implied licenses granted hereunder to design or

fabricate any integrated circuit or circuits based on the information

in this document. Everspin Technologies reserves the right to make

changes without further notice to any products herein. Everspin makes

no warranty, representation or guarantee regarding the suitability of its

products for any particular purpose, nor does Everspin Technologies as-

sume any liability arising out of the application or use of any product or

circuit, and specically disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters,

which may be provided in Everspin Technologies data sheets and/

or specications can and do vary in dierent applications and actual

performance may vary over time. All operating parameters including

“Typicals” must be validated for each customer application by cus-

tomer’s technical experts. Everspin Technologies does not convey any

license under its patent rights nor the rights of others. Everspin Tech-

nologies products are not designed, intended, or authorized for use as

components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other

application in which the failure of the Everspin Technologies product

could create a situation where personal injury or death may occur.

Should Buyer purchase or use Everspin Technologies products for any

such unintended or unauthorized application, Buyer shall indemnify

and hold Everspin Technologies and its ocers, employees, subsidiar-

ies, aliates, and distributors harmless against all claims, costs, dam-

ages, and expenses, and reasonable attorney fees arising out of, directly

or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that Ever-

spin Technologies was negligent regarding the design or manufacture

of the part. Everspin™ and the Everspin logo are trademarks of Everspin

Technologies, Inc. All other product or service names are the property

of their respective owners.

HOW TO CONTACT US

How to Reach Us:

Home Page:

www.everspin.com

World Wide Information Request

WW Headquarters - Chandler, AZ

5670 W. Chandler Blvd., Suite 100

Chandler, Arizona 85226

Tel: +1-877-480-MRAM (6726)

Local Tel: +1-480-347-1111

Fax: +1-480-347-1175

support@everspin.com

orders@everspin.com

sales@everspin.com

Europe, Middle East and Africa

Everspin Europe Support

support.europe@everspin.com

Japan

Everspin Japan Support

support.japan@everspin.com

Asia Pacic

Everspin Asia Support

support.asia@everspin.com

Filename:

EST00355_MR256A08B_Datasheet_Rev6.5 032318