1
®
FN4115.4
HI1178
Triple 8-Bit, 40MSPS, RGB, 3-Channel D/A
Converter
The HI1178 is a triple 8-bit, high-speed, CMOS D/A
converter designed for video band use. It has three
separate, 8-bit, pixel inputs, one each for red, green, and
blue video data. A single 5.0V power supply and pixel clock
input is all that is required to make the device operational. A
bias voltage generator is internal. Each channel clock input
can be controlled individually, or connected together as one.
The HI1178 also has BLANK video control signal.
Pinout HI1178
(MQFP)
TOP VIEW
Features
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 8-Bit
• Maximum Conversion Speed. . . . . . . . . . . . . . . . . 40MHz
• RGB 3-Channel Input/Output
• Differential Linearity Error . . . . . . . . . . . . . . . . . +0.3 LSB
• Low Power Consumption. . . . . . . . . . . . . . . . . . . .240mW
(200Ω Load for 2VP-P Output)
• Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . .+5V
• Low Glitch Noise
• Direct Replacement for Sony CXD1178
Applications
• Digital TV
• Graphics Disp lay
• High Resolution Col or Graphics
• Video Reconstruction
• Instrumentation
• Image Processing
• I/Q Modulation
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mo unt Devices
(SMDs)”
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE PKG. NO.
HI1178JCQ -40 to 85 48 Ld MQFP Q48.12x12-S
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
2423222120191817
9
10
11
1213 14 15 16
33
34
35
36
373839404142434445464748 RO
IREF
VREF
AVSS
VB
DVSS
DVSS
BCK
GCK
RCK
CE
BLK
R0
R1
R2
R3
R4
R7
G0
G1
G2
G3
R5
R6
DVDD
DVDD
AVDD
AVDD
AVDD
VG
BO
BO
GO
GO
RO
AVDD
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
Data Sheet October 25, 2005
Pb-Free and RoHS Compliant
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Functional Block Diagram
(LSB) R0
R1
R2
R3
R4
R5
R6
R7
(LSB) B0
B1
B2
B3
B4
B5
B6
B7
BLK
CE
DVDD
DVDD
R0
R0
RCK
AVSS
DVSS
B0
B0
BCK
VG
VREF
IREF
BIAS VOLTAGE
+
-
GENERATOR
CURRENT CELLS
(FOR FULL SCALE)
CLOCK
GENERATOR
6 MSBs
CURRENT
CELLS
2 LSBs
CURRENT
CELLS
CLOCK
GENERATOR
6 MSBs
CURRENT
CELLS
2 LSBs
CURRENT
CELLS
LATCHES
LATCHES
DECODER
DECODER
DECODER
DECODER
VB
(LSB) G0
G1
G2
G3
G4
G5
G6
G7
AVDD
AVDD
G0
G0
GCK
AVSS
CLOCK
GENERATOR
6 MSBs
CURRENT
CELLS
2 LSBs
CURRENT
CELLS
LATCHES
DECODER
DECODER
1
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
25
26
9
10
11
12
13
14
15
16
47
48
36
37
27
43
30
40
41
29
42
34
35
32
44
45
38
39
28
33
AVDD
46
DVSS
31
HI1178
3
Pin Descriptions
PIN NO. SYMBOL EQUIVALENT CIRCUIT DESCRIPTION
1 to 8 R0 to R7 Digital input.
9 to 16 G0 to G7
17 to 24 B0 to B7
25 BLK Blanking pin. No signal at “H” (Output
0V). Output condition at “L”.
32 VBConnect a capacitor of about 0.1µF.
27 RCK Clock pin. Moreover all input pins are
TTL-CMOS compatible.
28 CLK
29 BCK
30, 31 DVSS Digital GND.
33 AVSS Analog GND.
26 CE Chip enable pin. No signal (Output 0V) at
“H” and minimizes power consumption.
1
24
DVDD
DVSS
25
DVDD
DVSS
32
DVSS
DVDD
DVDD
+
-
28
29
DVSS
DVDD
27
26
DVSS
DVDD
HI1178
4
35 IREF Connect a resistance 16 times “16R” that
of output resistance value “R”.
34 VREF Set full scale output value.
42 VGConnect a capacitor of about 0.1µF.
43 to 46 AVDD Analog VDD.
37 RO Current output pin. Voltage output can be
obtained by connecting a resistance.
39 GO
41 BO
36 RO Inverted current output pin. Normally
dropped to analog GND.
38 GO
40 BO
47, 48 DVDD Digital VDD.
Pin Descriptions (Continued)
PIN NO. SYMBOL EQUIVALENT CIRCUIT DESCRIPTION
34
AVSS
AVDD
AVDD
35
42
AVDD
AVDD
AVSS
AVSS
+
-
39
AVSS
AVDD
38
AVSS
AVDD
41
40
37
36
HI1178
5
Absolute Maximum Ratings TA = 25oCThermal Information
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Input Voltage (VIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS
Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS
Digital Input Voltage (CLK) . . . . . . . . . . . . . . . . . . . . . 0mA to 15mA
(Every Each Channel)
Operating Conditions
Temperature Range (TOPR) . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Supply Voltage
AVDD, AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V
DVDD, DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V
Reference Input Voltage (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . .2V
Clock Pulse Width
tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.5ns (Min)
tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.5ns (Min)
Thermal Resistance (Typical, Note 1) θJA (oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(MQFP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications fCLK = 40MHz, VDD = 5V, ROUT = 200Ω, VREF = 2.0V, TA = 25oC
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Resolution n-8-bit
Maximum Conversion Speed fMAX 40 - - MSPS
Linearity Error EL-2.5 - 2.5 LSB
Differential Linearity Error ED-0.3 - 0.3 LSB
Full Scale Output Voltage VFS 1.8 2.0 2.2 V
Full Scale Output Ratio (Note 1) FSR 01.53 %
Full Scale Output Current IFS -1015mA
Offset Output Voltage VOS --1mV
Power Supply Current IDD 14.3MHz, at Color Bar Data Input - - 48 mA
Digital Input
Current H Level IIH --5µA
L Level IIL -5 - - µA
Set Up Time tS5--ns
Hold Time tH10 - - ns
Propagation Delay Time tPD -10- ns
Glitch Energy GE ROUT = 75Ω-30-pV/s
Crosstalk CT 1MHz Sine Wave Output - 57 - dB
NOTE:
1. Full scale output ratio = x 100(%)
Full Scale Voltage of Channel
Average of the Full Scale Voltage of the Channels
------------------------------------------------------------------------------------------------------------------------------------ 1–
HI1178
6
I/O Chart (When Full Scale Output Voltage at 2.00V)
INPUT CODE OUTPUT CODE
MSB LSB
11111111 2.0V
•
•
•
10000000 1.0V
•
•
•
00000000 0V
Timing Diagram
FIGURE 1.
CLK
DATA
D/AOUT
100%
50%
0%
tPW1 tPW0
tS
tHL
tStS
tPD
tPD tPD
tHL tHL
Test Circuits
FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT
42
34
35
25
26
32
28
29
R0 ~ R7
8-BIT
COUNTER
WITH
LATCH
1 ~ 8
B0 ~ B7
17 ~ 24
BLK
CE
VB
RCK
BCK
DVSS
0.1µ
CLK
40MHz
SQUARE
WAVE IREF
VREF
VG
B0
OSCILLOSCOPE
200
AVSS AVDD
AVSS
0.1µ
3.3K
1K
G0
200
AVSS
R0
200
AVSS
G0 ~ G7
9 ~ 18
GCK
27
41
39
37
HI1178
HI1178
7
FIGURE 3. SETUP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT
FIGURE 4. CROSSTALK TEST CIRCUIT
Test Circuits (Continued)
41
R0 ~ R7
8-BIT
COUNTER
WITH
LATCH
1 ~ 8
G0 ~ G7
9 ~ 18
BLK
CE
VB
RCK
GCK
DVSS
0.1µ
CLK
1MHz
SQUARE
WAVE IREF
VREF
VG
G0
R0
75
AVSS OSCILLOSCOPE
75
AVSS
AVDD
AVSS
0.1µ
1.2K
1K
DELAY
CONTROLLER
29
28
27
32
26
25
39
37
DELAY
CONTROLLER
B0 ~ B7
17 ~ 24
BCK
75
AVSS
B0
42
34
35
HI1178
26
25
28
27 42
34
32
R0 ~ R7
DIGITAL
WAVEFORM
GENERATOR
1 ~ 8
G0 ~ G7
9 ~ 16
BLK
CE
VB
RCK
BCK
DVSS
0.1µ
CLK
40MHz
SQUARE
WAVE IREF
VREF
VG
G0
R0
AVSS SPECTRUM
AVSS
AVDD
AVSS
0.1µ
1K
ANALYZER
ALL “1”
29 35
GCK
B0 ~ B7
17 ~ 24
AVSS
B0
37
39
41
HI1178
HI1178
8
FIGURE 5. DC CHARACTERISTICS TEST CIRCUIT
FIGURE 6. PROPAGATION DELAY TIME TEST CIRCUIT
Test Circuits (Continued)
39
37
42
34
35
CONTROLLER
BLK
CE
VB
RCK
GCK
DVSS
0.1µ
CLK
40MHz
SQUARE
WAVE IREF
VREF
VG
200
AVSS
AVDD
AVSS
0.1µ
3.3K
1K
R0 ~ R7
1 ~ 8
G0 ~ G7
9 ~ 16
B0 ~ B7
17 ~ 24
BCK
200
AVSS
200
AVSS
41B0
G0
R0
25
26
32
27
28
29
DVM
HI1178
29
42
34
35
FREQUENCY
BLK
CE
VB
DVSS
0.1µ
CLK
10MHz
SQUARE
WAVE IREF
VREF
VG
200
AVSS
OSCILLOSCOPE
AVDD
AVSS
0.1µ
3.3K
1K
DEMULTIPLIER
200
AVSS
200
AVSS
41
39
37
B0
G0
R0
R0 ~ R7
1 ~ 8
G0 ~ G7
9 ~ 16
B0 ~ B7
17 ~ 24
28
27
32
26
25
RCK
GCK
BCK
HI1178
HI1178
9
Typical Performance Curves
FIGURE 7. OUTPUT FULL SCALE VOLTAGE vs REFERENCE
VOLTAGE FIGURE 8. GLITCH ENERGY vs OUTPUT RESISTANCE
FIGURE 9. OUTPUT FULL SCALE VOLTAGE vs AMBIENT
TEMPERATURE FIGURE 10. CROSSTALK vs OUTPUT FREQUENCY
VDD = 5.0V
R = 200Ω
16R = 3.3kΩ
TA = 25oC
VFS, OUTPUT FULL SCALE VOLTAGE (V)
2.0
1.0
1.0 2.0
VREF, REFERENCE VOLTAGE (V)
200
100
100 200
OUTPUT RESISTANCE (Ω)
VDD = 5.0V
VREF = 2.0V
R = 200Ω
16R = 3.3kΩ
2.0
1.9
0-25 2505075
AMBIENT TEMPERATURE (oC)
OUTPUT FULL SCALE VOLTAGE (V)
100
60
50
40
100K 10M1M
OUTPUT FREQUENCY (Hz)
CROSSTALK (dB)
HI1178
10
Notes On Operation
• How to select the outpu t resi st an ce
The HI1178 is a current-output D/A converter. To obtain
the output voltage, connect the resistance to IO pin (RO,
GO, BO). For specifications we have :
Calculate the output resistance value from the relation of
VFS = IFS X R. Also, 16 times resistance of the output
resistance is connected to reference current pin IREF. In
some cases, however, this turns out to be a value that
does not actually exist. In such a case a value close to it
can be used as a substitute. Here please note that VFS
becomes VFS =V
REF X 16R/R'. R is the resistance con-
nected to IO while R' is con nected to IREF. Increasing the
resistance value can curb power consumption. On the
other hand glitch energy and data settling time will
inversely increase. Set the most suitable value according
to the desired application.
• Phase Relation Between Data and Clock
To obtain the expected performan ce as a D/A converter, it
is necessary to set properly the phase relation between
data and clock applied from the exterior. Be sure to satisfy
the provisions of the set up time (tS) and hol d time (tH) as
stipulated in the Electrical Characteristics.
•V
DD, VSS
To reduce noise effects separate analog and digital
systems in the device periphery. For VDD pin s, both di gita l
and analog, bypass respective GNDs by using a ceramic
capacitor of 0.1µF, as close as possible to the pin.
Application Circuit
FIGURE 11.
DVDD AVDD
36
242322212019181713 14 15 16
1
2
3
4
5
6
7
8
9
10
11
12
38394041424344454647 3748
35
DVSS
CLOCK IN
DVSS
0.1µ
AVSS
AVSS
(BCK)
(GCK)
(RCK)
(MSB)
(LSB)
1K
AVSS
3.3K
2V
(LSB)
(MSB)
(MSB)
G(GREEN)IN
R(RED)IN
B(BLUE)IN
AVSS
AVDD
200
R(RED)OUT
G(GREEN)OUT
200
AVSS
200
B(BLUE)OUT
0.1µ
(LSB)
34
31
30
29
28
27
26
25
33
32
HI1178
Output Full Scale Voltage VFS = less than 2.0 [V]
Output Full Scale Current IFS = less than 15 [mA]
HI1178
11
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semicon duc to r prod ucts are sold by descr ip tion on ly. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is grant ed by impl icati on or ot herwise under any patent or patent rights of Intersil or its subsi diaries.
For information re garding Intersil Corporation and its products, see web site www.intersil.com
HI1178
Metric Plastic Quad Flatpack Packages (MQFP/PQFP)
D
D1
EE1
PIN 1
A1
A
0.15
0.006
0o-10o
L
PLANE
B
SEATING
e
M
0.24
0.10/0.25
0.004/0.010
-C-
-H-
Q48.12x12-S
48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.081 0.100 2.05 2.55 -
A1 0.000 0.011 0.00 0.30 -
B 0.008 0.017 0.20 0.45 5
D 0.587 0.618 14.90 15.70 2
D1 0.469 0.488 11.90 12.40 3, 4
E 0.587 0.618 14.90 15.70 2
E1 0.469 0.488 11.90 12.40 3, 4
L 0.028 0.043 0.70 1.10 -
N48 486
e 0.032 BSC 0.80 BSC -
Rev. 0 2/96
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
2. Dimensions D and E to be determined at seating plane .
3. Dimensions D1 and E1 to be determined at datum plane .
4. Dimensions D1 and E1 do not include mold protrusion.
5. Dimension B does not include dambar protrusion.
6. “N” is the number of terminal positions.
-C-
-H-
