19-4117; Rev 1; 4/09 KIT ATION EVALU E L B A AVAIL Hi-Speed USB-to-SD Card Readers with Bypass Features USB 2.0 Hi-Speed and Full-Speed Compliant SDHC Card Support Internal Hi-Speed USB SD Card Reader Eases Host P Overhead On-Chip Termination and Pullup Resistors Internal SD Switches Allow For Multiplexing Two SD Cards on a Single-Microprocessor SD Port Accommodates Clock Input Frequencies 26MHz, 19.2MHz, 13MHz, and 12MHz Internal Clock Squarer for Low-Amplitude TCXO Signals No Power-Supply Sequencing Required Compatible with +1.8V to +3.3V I/O Host Microprocessor Simple Control Mode Requires Only a Single GPIO I2C Control Provides Multiple Configuration Options I2C Control Required for Two SD Cards On-Chip Power-On Reset/Brown-Out Reset Ordering Information/ Selector Guide PART INPUT SD FREQUENCY CARDS (MHz) PINPACKAGE MAX14500ETL+* 12 1 40 TQFN-EP** MAX14500AEWN+* 12 2 56 WLP MAX14501ETL+* 13 1 40 TQFN-EP** MAX14501AEWN+* 13 2 56 WLP Cell Phones MAX14502AETL+ 19.2 1 40 TQFN-EP** PDAs MAX14502AEWN+* Applications MP3 Players Digital Still Cameras GPS 19.2 2 56 WLP MAX14503ETL+* 26 1 40 TQFN-EP** MAX14503AEWN+* 26 2 56 WLP Note: All devices are specified over the -40C to +85C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *Future product--contact factory for availability. **EP = Exposed pad. SD is a trademark of the SD Card Association. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX14500-MAX14503 General Description The MAX14500-MAX14503 USB-to-SDTM card readers provide a means for portable devices that support fullspeed USB communication (12Mbps) with one or two SD card slots, upgrading the USB SD card reader function to USB Hi-Speed (480Mbps) operation. The MAX14500-MAX14503 have two modes of operation: Pass Thru and Card Reader. In pass thru, the SD and USB signals pass through the MAX14500-MAX14503 without modification, appearing like the device is not present. The host microprocessor firmware does not need modification, as there is no change from the host microprocessor's perspective. In Card Reader mode, the MAX14500-MAX14503 implement a Hi-Speed USB card reader that operates independently of the host microprocessor. All the capabilities of the full-speed USB port and SD card slot are preserved with the additional feature that allows a faster way for a PC to read or write to the SD card. The MAX14500-MAX14503 support SD high capacity SDHC cards. The 40-pin TQFN version supports one SD card, while the 56-bump WLP version supports two SD cards. The MAX14500-MAX14503 feature advanced powersaving modes to reduce power consumption in portable applications. The low-power Sleep modes allow the ability to disable internal circuit blocks, providing power-saving operating modes. The default clock input for each part number is specified in the ordering information. The MAX14500-MAX14503 feature the option to change the default values using the I2C interface. The MAX14500-MAX14503 are available in 5mm x 5mm, 40-pin TQFN, and 3.23mm x 3.5mm, 56-bump WLP packages. These devices operate over a wide supply voltage range and are specified over the -40C to +85C extended temperature range. MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) VCC ...........................................................................-0.3V to +4V VSD ...........................................................................-0.3V to +4V VIO ............................................................................-0.3V to +4V VTM ...........................................................................-0.3V to +4V KVBUS......................................................................-0.3V to +4V CLDO........................................................................-0.3V to +2V CDAT1_[3:0], HDAT1_[3:0], CCMD1, HCMD1, CCLK1, HCLK1, CCRD_PRST, HCRD_PRST, CDAT2_[3:0], HDAT2_[3:0], CCMD2, HCMD2, CCLK2, HCLK2 .........-0.3V to (VSD + 0.3V) BUSY, BERR/INT, MODE, SCL, SDA, I2C_SEL, ADD, RST.................................................-0.3V to (VIO + 0.3V) CD+, CD-, HD+, HD-, RREF, FREF ............-0.3V to (VTM + 0.3V) Continuous Power Dissipation (TA = +70C) 40-Pin TQFN (derate 35.7mW/C above +70C) ........2857mW Junction-to-Case Thermal Resistance (JC) (Note 1) 40-Pin TQFN ................................................................1.7C/W Junction-to-Ambient Thermal Resistance (JA) (Note 1) 40-Pin TQFN .................................................................28C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +2.4V to +3.6V, VSD = +2.4V to +3.6V, VIO = +1.5V to +3.6V, VTM = +2.91V to +3.4V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS Pass thru VCC Supply Voltage VSD Supply Voltage VCC VSD 2.1 3.6 Card reader active, fCCLK_ 26MHz 2.1 3.6 Card reader active, fCCLK_ > 26MHz 2.4 3.6 Pass thru 2.0 3.6 Card reader active, fCCLK_ 26MHz 2.0 3.6 Card reader active, fCCLK_ > 26MHz 2.4 3.6 V V Logic Interface Supply Voltage VIO 1.5 3.6 V USB Supply Voltage VTM 2.91 3.4 V Digital Core LDO Regulator Output Voltage VCLDO VCC Supply Current ICC VSD Supply Current ISD VIO Supply Current VTM Supply Current IIO ITM CCLDO = 1.0F 1.8 V Pass thru 5 15 A Card reader active 35 50 mA Pass thru 17 40 A Card reader active 3 Pass thru 2 Card reader active 0.2 Pass thru 13 Card reader active 25 mA 10 A mA 50 A mA VSD Comparator Threshold VSDCT 1.0 1.5 1.9 V VTM Comparator Threshold VTMCT 2.0 2.5 2.9 V MODE, I2C_SEL, ADD, RST Input-Voltage Low VIL 0.4 V 2 _______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass (VCC = +2.4V to +3.6V, VSD = +2.4V to +3.6V, VIO = +1.5V to +3.6V, VTM = +2.91V to +3.4V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MODE, I2C_SEL, ADD, RST Input-Voltage High VIH BUSY, BERR/INT Output-Voltage Low VOL ILOAD = 1mA BUSY, BERR/INT Output-Voltage High VOH ILOAD = -1mA I2C_SEL, ADD, RST Input Leakage Current MODE Input Resistance to GND MIN RMODE 150 FREF Full-Swing Input-Voltage High VIH 1.3 FREF Full-Swing Input-Voltage Low VIL FREF Low-Amplitude InputVoltage Low VIL FREF Input Leakage Current IILF VTH KVBUS Comparator Hysteresis VHYS KVBUS Comparator Input Impedance VIL_I2C SDA/SCL Input High Voltage VIH_I2C SDA Output Logic-Low SDA/SCL Input Leakage Current VOL_I2C A 500 k V V mV -10 +10 1 1.0 1.25 A M 1.5 20 V mV 10 RIN SDA/SCL Input Low Voltage 300 +1 200 Low-Amplitude input mode V V 0.4 Full-Swing mode UNITS V VIO 0.4 -1 KVBUS Comparator Threshold MAX 0.4 IIL FREF Input Resistance TYP 2/3 x VIO M 0.3 x VIO 0.7 x VIO V V VIO > +2V, 3mA sink current 0 0.4 VIO +2V, 3mA sink current 0 0.2 x VIO V -10 +10 A +1 A IIN_I2C SD CARD INTERFACE On-Resistance RON VTEST = 0 or VSD, ITEST = 10mA (Note 3) Off-Leakage Current IILSD VTEST = 0 or VSD (Note 3) 10 -1 Off-Capacitance CSD_OFF (Note 4) 5 pF On-Capacitance CSD_ON (Note 5) 10 pF Pullup Resistance RPU CCMD1, CCMD2, CDAT1_[3:0], CDAT2_[3:0] Output High Voltage VOH IOH = -100A Output Low Voltage VOL IOL = 100A 50 75 100 0.75 x VSD k V 0.125 x VSD V _______________________________________________________________________________________ 3 MAX14500-MAX14503 ELECTRICAL CHARACTERISTICS (continued) MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass ELECTRICAL CHARACTERISTICS (continued) (VCC = +2.4V to +3.6V, VSD = +2.4V to +3.6V, VIO = +1.5V to +3.6V, VTM = +2.91V to +3.4V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA = +25C.) (Note 2) PARAMETER Input High Voltage Input Low Voltage SYMBOL CONDITIONS MIN VSD < 2.4V 0.8 x VSD VSD 2.4V 0.625 x VSD VIH TYP MAX UNITS V VSD < 2.4V 0.2 x VSD VSD 2.4V 0.25 x VSD VIL V USB INTERFACE RON VCD_ = 0 or VTM, switch closed 5 On-Resistance Flatness RONFLAT VCD_ = 0 to 3.3V, VTM = +3.3V 2 On-Capacitance CON_USB Switch closed, measured from CD+ and CD- 12 pF Off-Capacitance COFF_USB Switch open, measured from CD+, CD-, HD+, HD- 6 pF On-Resistance AC CHARACTERISTICS (Note 6) SD CARD CLOCK TIMING (CCLK_), DEFAULT SPEED (Figure 5a) Clock Low Time tWL CL = 10pF 19 Clock High Time tWH CL = 10pF 19 ns Clock Rise Time tTLH CL = 10pF 10 ns Clock Fall Time tTHL CL = 10pF 10 ns ns SD CARD CLOCK TIMING (CCLK_), HI-SPEED (Figure 5b) Clock Low Time tWL CL = 40pF 7 Clock High Time tWH CL = 40pF 7 Clock Rise Time tTLH CL = 40pF ns ns 3 ns 3 ns Clock Fall Time tTHL CL = 40pF SD CARD COMMAND TIMING (CCMD1, CCMD2) (Figure 5b) Input Setup Time tISU 5 ns Input Hold Time 2 ns Output Delay Time During Data Transfer Mode Output Hold Time tIH 14 tODLY tOH 2.5 ns ns I2C CHARACTERISTICS SCL Clock Frequency fSCL SDA, SCL Capacitance CIO_I2C SDA Output Fall Time tOF_I2C Hold Time After Repeated START tHD,STA 4 400 5 pF 250 0.6 _______________________________________________________________________________________ kHz ns s Hi-Speed USB-to-SD Card Readers with Bypass (VCC = +2.4V to +3.6V, VSD = +2.4V to +3.6V, VIO = +1.5V to +3.6V, VTM = +2.91V to +3.4V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Clock Low Period tLOW_I2C 1.3 s Clock High Period tHIGH_I2C 0.6 s Setup Time for Repeated START tSU,STA 0.6 Hold Time for Data tHD,DAT Setup Time for Data tSU,DAT s 0 0.9 100 s ns SDA/SCL Input Fall Time tF_I2C 300 SDA/SCL Rise Time tR_I2C 300 Setup Time for STOP tSU,STO 0.6 s tBUF 1.3 s Bus Free Time Between STOP and START ns ns USB HI-SPEED SOURCE ELECTRICAL CHARACTERISTICS (VCC = +2.4V to +3.6V, VSD = +2.4V to +3.6V, VIO = +1.5V to +3.6V, VTM = +2.91V to +3.4V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 100 150 mV -50 +500 mV DC CHARACTERISTICS Hi-Speed Squelch Detection Threshold (Diff Signal Amplitude) Hi-Speed Differential Input Signaling Levels Hi-Speed Data Signaling Common-Mode Voltage Range VHSSQ VIL SCM (Note 6) Specified by Hi-Speed receive eye diagram (Note 6) Hi-Speed Idle Level VHSOI -10 +10 mV Hi-Speed Data Signaling High VHSOH 360 440 mV Hi-Speed Data Signaling Low VHSOL -10 +10 mV Chirp J Level (Differential Voltage) VCHIRPJ 700 1100 mV Chirp K Level (Differential Voltage) VCHIRPK -900 -500 mV Termination Voltage (Hi-Speed) VHSTERM -10 +10 mV AC CHARACTERISTICS Rise Time tHSR (Note 6) 500 ps Fall Time tHSF (Note 6) 500 ps Driver Waveform Requirements Driver-Output Resistance Source Jitter Total (Including Frequency Tolerance) Specified by Hi-Speed transmit eye diagram See the Typical Operating Characteristics section Specified by Hi-Speed transmit eye diagram See the Typical Operating Characteristics section ZHSDRV 40.5 49.5 _______________________________________________________________________________________ 5 MAX14500-MAX14503 ELECTRICAL CHARACTERISTICS (continued) MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass USB FULL-SPEED SOURCE ELECTRICAL CHARACTERISTICS (VCC = +2.4V to +3.6V, VSD = +2.4V to +3.6V, VIO = +1.5V to +3.6V, VTM = +2.91V to +3.4V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC CHARACTERISTICS SE Receiver Input High VIH SE Receiver Input Low VIL 2.0 V 0.8 V 2.0 V Differential Common-Mode Voltage VCM 0.8 Receiver Differential Input Sensitivity VDI 0.2 Transmitter High VOH RL = 15k connected to GND 2.8 3.6 V Transmitter Low VOL RL = 1.5k connected to 3.3V 0 0.3 V 1.3 2.0 V V Transmitter Output Signal Crossover Voltage VCRS Bus Pullup Resistor on Upstream Facing Port (Idle Bus) RPUI 0.900 1.25 1.575 k Bus Pullup Resistor on Upstream Facing Port (Upstream Port Receiving) RPUA 1.425 2.5 3.090 k Input Impedance ZINP 300 Termination Voltage for Upstream Facing Port Pullup (RPU) (Note 6) VTERM k VTM V AC CHARACTERISTICS Rise Time tFR 4 20 ns Fall Time tFF 4 20 ns 90 111.11 % 11.994 12.030 Mbps Differential Rise and Fall Time Matching Full-Speed Data Rate tFRFM tFDRATHS (Note 6) Note 2: All parameters are tested at TA = +25C. Specifications over temperature are guaranteed by design. Note 3: On-resistance is measured by applying voltage and current on the SD card interface (CCLK1, CCMD1, CDAT1_[3:0], CCLK2, CCMD2, CDAT2_[3:0]). Note 4: Off-capacitance measured with SD switch open (CCLK1, HCLK1, CCMD1, HCMD1, CDAT1_[3:0], HDAT1_[3:0], CCLK2, HCLK2, CCMD2, HCMD2, CDAT2_[3:0], HDAT2_[3:0]). Note 5: On-capacitance measured on SD card side (CCLK1, CCMD1, CDAT1_[3:0], CCLK2, CCMD2, CDAT2_[3:0]). Note 6: Specifications guaranteed by design. 6 _______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass HI-SPEED EYE DIAGRAM FOR CARD READER MODE MAX14500 toc01 10 MAX14500 toc02 USB ON-RESISTANCE vs. USB COMMON VOLTAGE (VCD_) VTM = 3.3V RON () DIFFERENTIAL VOLTAGE 8 6 4 2 0 0.9 UNIT TIME INTERVAL 2.5 2.9 3.3 20 15 10 NO CLOCK 5 SUPPLY CURRENT (A) 25 MAX14500 toc04 6 4 3 2 1 5 0 0 0.5 1.0 1.5 2.0 2.0 2.5 2.4 2.8 3.2 VCC SUPPLY VOLTAGE (V) PASS THRU VIO SUPPLY CURRENT vs. SUPPLY VOLTAGE PASS THRU VSD SUPPLY CURRENT vs. SUPPLY VOLTAGE NO CLOCK 30 2 1 NO CLOCK 25 SUPPLY CURRENT (A) 3 3.6 MAX14500 toc06 SD CHANNEL COMMON VOLTAGE (V) MAX14500 toc05 0 SUPPLY CURRENT (A) 2.1 PASS THRU VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX14500 toc03 SD CHANNEL ON-RESISTANCE () VSD = +3V 30 4 1.7 VCD_ COMMON VOLTAGE (V) SD CHANNEL ON-RESISTANCE vs. SD CHANNEL COMMON VOLTAGE 35 1.3 20 15 10 5 0 0 1.5 1.8 2.1 2.4 2.7 VIO SUPPLY VOLTAGE (V) 3.0 3.3 1.8 2.1 2.4 2.7 3.0 3.3 VSD SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 7 MAX14500-MAX14503 Typical Operating Characteristics (VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA = +25C, unless otherwise noted.) SUPPLY CURRENT (mA) 8 6 4 2 DEVICE ENUMERATED DATA RATE = 0Mbps 23 DEVICE ENUMERATED DATA RATE = 0Mbps 22 32 SUPPLY CURRENT (mA) NO CLOCK MAX14500 toc009 33 MAX14500 toc07 10 CARD READER VTM SUPPLY CURRENT vs. SUPPLY VOLTAGE CARD READER VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX14500 toc08 PASS THRU VCC SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (A) 31 30 21 20 19 18 0 17 29 -40 -15 10 35 60 2.0 85 2.4 2.8 3.2 3.6 2.9 3.0 VCC SUPPLY VOLTAGE (V) TEMPERATURE (C) 0 MAX14500 toc11 -4 3.2 PASS THRU SD CHANNEL OFF-ISOLATION MAX14500 toc10 0 -2 3.1 VTM SUPPLY VOLTAGE (V) PASS THRU USB CHANNEL FREQUENCY RESPONSE -20 OFF-ISOLATION (dB) -6 ON-LOSS (dB) MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass -8 -10 -12 -14 -40 -60 -16 -18 -20 -80 0.1 1 10 FREQUENCY (MHz) 8 100 1000 0.1 1 10 100 FREQUENCY (MHz) _______________________________________________________________________________________ 1000 3.3 3.4 Hi-Speed USB-to-SD Card Readers with Bypass PIN TQFN WLP NAME FUNCTION INPUTS/OUTPUTS I2C Select Input. I2C_SEL must be connected to VIO or GND at power-up. Drive I2C_SEL low to disable I2C control and drive I2C_SEL high to enable I2C control. 1 C4 I2C_SEL 2 A2 SCL I2C Serial-Clock Input. SCL is +3.6V tolerant and the high threshold is set by VIO. If the I2C interface is not used, connect SCL to GND. 3 B4 SDA I2C Serial-Data I/O. SDA is +3.6V tolerant and the high threshold is set by VIO. If the I2C interface is not used, connect SDA to GND. 4 A3 ADD I2C Address Selection Input. Connect ADD to VIO or GND to select between two I2C slave addresses: (GND = 1110 000Xb and VIO = 1110 001Xb). 6 B6 BERR/INT Card Reader Error/Interrupt Output. BERR/INT becomes BERR for simple control and INT for I2C control. BERR/INT goes low to indicate an error in Card Reader mode during simple control and asserts for enabled interrupts during I2C control. 7 A7 BUSY Busy Output. BUSY asserts low to indicate device is in Card Reader mode. 8 C6 MODE Card Reader/Pass Thru Mode Select Input. MODE is only active during simple control. Drive MODE low to enable Pass Thru mode and drive MODE high to enable Card Reader mode. For I2C control, MODE must be connected to GND. 9 B7 RST Reset Input. Drive RST low to reset the internal registers to default values and put all outputs in high impedance. Connect RST to VIO for normal operation. 25 E6 FREF Frequency Input. FREF is the clock input (12MHz/13MHz/19.2MHz/26MHz) for the internal logic and USB PHY. FREF can accept a square-wave or sine-wave clock. An internal clock squaring circuit can be enabled or disabled through I2C. In simple control, the internal clock squarer is enabled by default. 27 F5 RREF Reference Resistor. Connect a Bias Resistor 6.19k 1% from RREF to GND. 22 G7 CD+ USB Analog Switch/Hi-Speed USB Transceiver. CD+ connects to D+ on the USB connector. 21 F7 CD- USB Analog Switch/Hi-Speed USB Transceiver. CD- connects to D- on the USB connector. 20 G8 HD+ USB Analog Switch. HD+ connects to D+ on the host side. 19 F8 HD- USB Analog Switch. HD- connects to D- on the host side. 28 E5 KVBUS USB Bus Power-Supply Detection Input. Connect a resistor-divider between USB VBUS, KVBUS, and GND. USB INTERFACE SD CARD INTERFACE 13 C8 CDAT1_0 SD Card 1 Data Bus Analog Switch/Card Reader Interface. CDAT1_0 connects to DAT0 on the SD card. 12 B8 CDAT1_1 SD Data Card 1 Bus Analog Switch/Card Reader Interface. CDAT1_1 connects to DAT1 on the SD card. 11 C7 CDAT1_2 SD Data Card 1 Bus Analog Switch/Card Reader Interface. CDAT1_2 connects to DAT2 on the SD card. _______________________________________________________________________________________ 9 MAX14500-MAX14503 Pin Description Hi-Speed USB-to-SD Card Readers with Bypass MAX14500-MAX14503 Pin Description (continued) PIN 10 NAME FUNCTION TQFN WLP 10 A8 CDAT1_3 SD Card 1 Data Bus Analog Switch/Card Reader Interface. CDAT1_3 connects to DAT3 on the SD card. 34 E2 CCMD1 SD Card 1 Command Analog Switch/Card Reader Interface. CCMD1 connects to CMD on the SD card. 32 E3 CCLK1 SD Card 1 Clock Analog Switch/Card Reader Interface. CCLK1 connects to CLK on the SD card. 33 F1 CCRD_PRST SD Card 1 Analog Switch for Card Present Detection. CCRD_PRST is the card detection line to the SD socket. When in Pass Thru mode, CCRD_PRST is connected to HCRD_PRST. 17 D7 HDAT1_0 SD Card 1 Data Bus Analog Switch. HDAT1_0 connects to DAT0 on the SD port of the host P. 16 D8 HDAT1_1 SD Card 1 Data Bus Analog Switch. HDAT1_1 connects to DAT1 on the SD port of the host P. 15 D6 HDAT1_2 SD Card 1 Data Bus Analog Switch. HDAT1_2 connects to DAT2 on the SD port of the host P. 14 D5 HDAT1_3 SD Card 1 Data Bus Analog Switch. HDAT1_3 connects to DAT3 on the SD port of the host P. 31 G1 HCMD1 SD Card 1 Command Analog Switch. HCMD1 connects to CMD on the SD port of the host P. 29 G2 HCLK1 SD Card 1 Clock Analog Switch. HCLK1 connects to CLK on the SD port of the host P. 30 F2 HCRD_PRST SD Card 1 Analog Switch for Card Present Detection. HCRD_PRST is connected to CCRD_PRST in Pass Thru mode. -- D2 CDAT2_0 SD Card 2 Data Bus Analog Switch/Card Reader Interface. CDAT2_0 connects to DAT0 on the SD card. -- D1 CDAT2_1 SD Card 2 Data Bus Analog Switch/Card Reader Interface. CDAT2_1 connects to DAT1 on the SD card. -- B5 CDAT2_2 SD Card 2 Data Bus Analog Switch/Card Reader Interface. CDAT2_2 connects to DAT2 on the SD card. -- A5 CDAT2_3 SD Card 2 Data Bus Analog Switch/Card Reader Interface. CDAT2_3 connects to DAT3 on the SD card. -- F4 CCMD2 SD Card 2 Command Analog Switch/Card Reader Interface. CCMD2 connects to CMD on the SD card. -- F3 CCLK2 SD Card 2 Clock Analog Switch/Card Reader Interface. CCLK2 connects to CLK on the SD card. -- D3 HDAT2_0 SD Card 2 Data Bus Analog Switch. HDAT2_0 connects to DAT0 on the SD port of the host P. -- E1 HDAT2_1 SD Card 2 Data Bus Analog Switch. HDAT2_1 connects to DAT1 on the SD port of the host P. ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass PIN NAME FUNCTION TQFN WLP -- C5 HDAT2_2 SD Card 2 Data Bus Analog Switch. HDAT2_2 connects to DAT2 on the SD port of the host P. -- A4 HDAT2_3 SD Card 2 Data Bus Analog Switch. HDAT2_3 connects to DAT3 on the SD port of the host P. -- G4 HCMD2 SD Card 2 Command Analog Switch. HCMD2 connects to CMD on the SD port of the host P. -- G3 POWER SUPPLY HCLK2 SD Card 2 Clock Analog Switch. HCLK2 connects to CLK on the SD port of the host P. 5 A6 VIO I/O Logic-Level Translator Voltage. Bypass VIO to GND with a 0.1F ceramic capacitor. VIO powers the logic inputs/outputs and I2C block. 23 F6 VTM USB Analog Switch and Transceiver Power Supply. Bypass VTM to GND with a 0.1F ceramic capacitor. 38 B1, B2 CLDO 39 B3, C3 VCC Digital Supply Voltage. Bypass VCC to GND with a 1F ceramic capacitor (X7R, X5R, or better). 40 A1 VSD SD Card Voltage. Bypass VSD to GND with a 1F ceramic capacitor (X7R, X5R, or better). 18, 24, 26, 37 C1, C2, E7, E8, G5, G6 GND Ground N.C. No Connection. Connect N.C. to GND. NO CONNECTION 35, 36 D4, E4 Bypass Capacitor for Internal +1.8V LDO. Connect a 1F ceramic capacitor (X7R, X5R, or better) from CLDO to GND. CLDO must not be used to power external circuitry. EXPOSED PAD -- -- EP Exposed Pad. Connect EP to GND. Do not use EP as the sole GND connection. ______________________________________________________________________________________ 11 MAX14500-MAX14503 Pin Description (continued) MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass SIMPLE CONTROL SD PORT 1 SWITCHES CCRD_PRST SD SLOT 4 HCRD_PRST CCLK1 HCLK1 CCMD1 HCMD1 CDAT1_[3:0] HDAT1_[3:0] SD PORT 4 VIO VIO VSD VSD SD CARD INTERFACE MODE BUSY VCC USB HS CARD READER CLDO BERR I2C_SEL ADD SCL SDA RREF VTM KVBUS USB TRANSCEIVER MAX14500- MAX14503 VTM FREF VBUS USB CONNECTOR D+ CD+ HD+ D- CD- HD- GND HOST I/O I/O LEVEL TRANSLATORS VCC USB USB SWITCHES Figure 1. Typical Application Circuit for Simple Control Mode with One SD Card 12 ______________________________________________________________________________________ HOST PROCESSOR Hi-Speed USB-to-SD Card Readers with Bypass MAX14500-MAX14503 I2C CONTROL SD PORT 1 SWITCHES CCRD_PRST SD SLOT 4 HCRD_PRST CCLK1 HCLK1 CCMD1 HCMD1 CDAT1_[3:0] SD PORT 4 HDAT1_[3:0] VIO VIO VSD VSD SD CARD INTERFACE BUSY OPTIONAL MODE VCC CLDO INT I2C_SEL SCL VTM KVBUS USB TRANSCEIVER MAX14500- MAX14503 VTM FREF VBUS D+ CD+ HD+ D- CD- HD- GND HOST PROCESSOR SDA RREF USB CONNECTOR VIO ADD HOST I/O USB HS CARD READER I/O LEVEL TRANSLATORS VCC USB USB SWITCHES Figure 2. Typical Application Circuit for I2C Control Mode with One SD Card ______________________________________________________________________________________ 13 I2C CONTROL SD PORT 2 SWITCHES SD SLOT2 4 CCLK2 HCLK2 CCMD2 HCMD2 HDAT2_[3:0] CDAT2_[3:0] SD PORT2 4 SD PORT 1 SWITCHES CCRD_PRST SD SLOT1 4 HCRD_PRST CCLK1 HCLK1 CCMD1 HCMD1 SD PORT1 HDAT1_[3:0] CDAT1_[3:0] 4 VIO VIO VSD VSD SD CARD INTERFACE BUSY OPTIONAL MODE VCC USB HS CARD READER CLDO SDA VTM KVBUS VTM USB TRANCEIVER MAX14500- MAX14503 VBUS D+ D- VIO SCL RREF USB CONNECTOR INT I2C_SEL ADD FREF CD+ HD+ CD- HD- GND USB SWITCHES Figure 3. Typical Application Circuit for I2C Control Mode with Two SD Cards 14 HOST I/O VCC I/O LEVEL TRANSLATORS MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass ______________________________________________________________________________________ USB HOST PROCESSOR Hi-Speed USB-to-SD Card Readers with Bypass SD PORT 2 SWITCHES SD SLOT2 4 CCLK2 HCLK2 CCMD2 HCMD2 HDAT2_[3:0] CDAT2_[3:0] SD PORT 1 SWITCHES CCRD_PRST SD SLOT1 4 HCRD_PRST CCLK1 HCLK1 CCMD1 HCMD1 SD PORT HDAT1_[3:0] CDAT1_[3:0] 4 VIO VIO VSD VSD SD CARD INTERFACE BUSY MODE VCC CLDO VTM VTM USB TRANCEIVER MAX14500- MAX14503 VBUS D- VIO SDA KVBUS D+ ADD HOST PROCESSOR SCL RREF USB CONNECTOR INT I2C_SEL HOST I/O USB HS CARD READER I/O LEVEL TRANSLATORS VCC OPTIONAL FREF CD+ HD+ CD- HD- USB GND USB SWITCHES Figure 4. Typical Application Circuit for I2C Control Mode with One SD Port and Two SD Cards ______________________________________________________________________________________ 15 MAX14500-MAX14503 I2C CONTROL Hi-Speed USB-to-SD Card Readers with Bypass MAX14500-MAX14503 Timing Diagrams fPP tWH tWL VIH CLOCK VIL tTLH tTHL tISU tIH VIH INPUT VIL VOH OUTPUT VOL tODLY (max) tODLY (min) SHADED AREAS ARE NOT VALID Figure 5a. SD Card Default Timing Diagram 16 ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass VOH VIH VIL VOL fPP tWH tWL VIH CCLK1 CCLK2 VIL tTHL tTLH tISU tIH VIH CDAT1 _[3:0], CDAT2_[3:0], CCMD1, CCMD2 (READ) VIL VOH CDAT1 _[3:0], CDAT2_[3:0], CCMD1, CCMD2 (WRITE) VOL tODLY tOH Figure 5b. SD Card Hi-Speed Timing Diagram ______________________________________________________________________________________ 17 MAX14500-MAX14503 Timing Diagrams (continued) MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass Timing Diagrams (continued) tR_I2C tF_I2C SDA tSU,DAT tLOW_I2C tSU,STA tBUF tHD,STA tSU,STO tHD,DAT tHIGH_I2C SCL tHD,STA tR_I2C tF_I2C START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 6. I2C Timing Diagram Detailed Description The MAX14500-MAX14503 can be added to devices that have an SD card slot and a USB full-speed port (12Mbps) to provide a Hi-Speed USB path to an SD card bypassing the host microprocessor (P), allowing for faster SD card transfers (Figures 1-4). Without the MAX14500-MAX14503, a host P with a full-speed USB port moves data between an SD card and a host PC at 12Mbps when transferring data from an SD card through USB. The host P has additional overhead because it has to accept data from the SD cards, process the data by putting it in USB format, and then transfer the data through the USB port. The MAX14500- MAX14503 create an alternate path from the SD card to USB, providing USB Hi-Speed capability. By bypassing the host P using the MAX14500-MAX14503, SD card read and write operations are not limited by host P overhead and USB full-speed data rates. The MAX14500-MAX14503 operate in Pass Thru and Card Reader mode. In Pass Thru mode, the MAX14500- MAX14503 are transparent to the host P. All read and write operations pass from the host P SD port to the SD card without modification. All of the features of the original device are intact and there is no need to change firmware in the host P. In Card Reader mode, the SD card is connected to the PC with the internal USB Hi-Speed card reader, bypassing the host P. 18 The MAX14500-MAX14503 can be controlled in two ways. The simple control method uses a single output from a P or ASIC to select Pass Thru or Card Reader mode. Only one SD card can be used as a Hi-Speed USB card reader in simple control. I2C control allows more configuration options and provides status information along with error conditions and additional interrupts. Two SD cards can be connected and each set of SD port switches can be controlled independently (two SD port version under I2C control). The state of I2C_SEL must not change after VIO is applied. With I2C control, the I2C bus is used to read and write to internal registers for configuration, error checking, control, and status reporting. The control and configuration registers have various functions including wakeup, SD card selection, interrupt enable, and SD switch settings. The status registers give the status of errors, SD card detection, power supplies, and interrupts. Putting the MAX14500-MAX14503 to sleep puts the device into Pass Thru mode. The state of SD port switches for card 1 and card 2 can be changed while in Pass Thru. Some I2C commands are executed upon waking up or entering Card Reader mode. For register settings that involve Card Reader mode, (when in Sleep mode), programming the I 2C registers changes the values, but the actions do not execute until the internal logic wakes up or Card Reader mode is entered. The register map indicates when register bit changes take effect. ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass MAX14500-MAX14503 Table 1. Power-Up Default Mini Register Map for Configuration Registers REGISTER NAME Control Register (CONTROL) REGISTER ADDRESS (hex) 0x00 POWER-UP VALUE (hex) POWER-UP DEFAULT SETTINGS 0x18 SD2SW = 1, SD switch 2 is closed SD1SW = 1, SD switch 1 is closed MODE[1:0] = 00, Card Reader mode is not active WAKEUP = 0, shutdown Configuration Register 1 (CONFIG1) 0x01 0x00 SD2ONEBIT = 0, SD2 bus in 4-bit data mode SD1ONEBIT = 0, SD1 bus in 4-bit data mode INTPULSE = 0, INT stays asserted until status register is read INTACTHI = 0, INT asserts active low Configuration Register 2 (CONFIG2) 0x02 0x00 CLKSOURCE = 00000, default clock input FORCEFS = 0, USB Hi-Speed Configuration Register 3 (CONFIG3) 0x03 0x00 SD2MAXCLK = 0000, default clock (base SD clock) SD1MAXCLK = 0000, default clock (base SD clock) Interrupt Enable Register 1 (IE1) 0x04 0x00 USBFS = 0, disable INT for full-speed status change USBSR = 0, disable INT for suspend/resume status change VTM = 0, disable INT for VTM status change VSD = 0, disable INT for VSD status change KVBUS = 0, disable INT for VBUS status change BSY = 0, disable INT for BUSY status change SDSTAT = 0, disable INT for SD card status change Interrupt Enable Register 2 (IE2) 0x05 0x00 FWUPD = 0, disable INT for firmware update status change USB Vendor ID High Byte (USBVIDH) 0x06 0x00 If VID = 0x0000, 0x06BA is used during USB enumeration, VID high byte = 0x06 USB Vendor ID Low Byte (USBVIDL) 0x07 0x00 If VID = 0x0000, 0x06BA is used during USB enumeration, VID low byte = 0xBA USB Product ID High Byte (USBPIDH) 0x08 0x00 If PID = 0x0000, 0x38A4 is used during USB enumeration, PID high byte = 0x38 USB Product ID Low Byte (USBPIDL) 0x09 0x00 If PID = 0x0000, 0x38A4 is used during USB enumeration. PID low byte = 0xA4 ______________________________________________________________________________________ 19 MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass SD PORT 2 SWITCHES CCLK2 HCLK2 CCMD2 SD SLOT2 4 HCMD2 CDAT2_[3:0] HDAT2_[3:0] 4 SD PORT2 SD PORT 1 SWITCHES HCRD_PRST CCRD_PRST SD SLOT1 4 CCLK1 HCLK1 CCMD1 HCMD1 CDAT1_[3:0] HDAT1_[3:0] SD CARD INTERFACE SD PORT1 4 HOST PROCESSOR I/O LEVEL TRANSLATORS USB HS CARD READER HOST I/O USB TRANSCEIVER MAX14500- MAX14503 USB CONNECTOR D+ CD+ HD+ D- CD- HD- USB USB SWITCHES Figure 7. Default Startup (Pass Thru Mode) Default Power-Up (Pass Thru Mode) In the default Pass Thru mode, the MAX14500- MAX14503 are transparent and the existing host functions (access to SD cards and USB) are preserved (Figure 7). The host P reads and writes data to the SD card from the SD port, and can communicate to a PC through its existing full-speed USB port. All of the features of the original chipset are intact. The MAX14500- MAX14503 sleep when in Pass Thru mode (WAKEUP = 0), when the MODE input is low, or when the MODE bits [2:1] in control register (0x00) are set to Card Reader mode, not active. In Sleep mode, the internal microcontroller is turned off and current consumption is mini20 mized. The settings for SD port switches for card 1 and card 2 are controlled by SD port switch bits [4:3] in the control register. Card Reader Mode In Card Reader mode, the PC communicates with the SD card through USB with an internal Hi-Speed SD card reader, bypassing the host P. Figure 8 shows card reader mode with SD card 1 connected to the PC with the internal card reader. The 40-pin TQFN can connect to a single SD card in Card Reader mode. With the 56-bump WLP operating under I2C control, either SD card can be selected for Card Reader mode. ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass MAX14500-MAX14503 SD PORT 2 SWITCHES SD SLOT2 4 CCLK2 HCLK2 CCMD2 HCMD2 CDAT2_[3:0] HDAT2_[3:0] 4 SD PORT2 SD PORT 1 SWITCHES HCRD_PRST CCRD_PRST SD SLOT1 4 CCLK1 HCLK1 CCMD1 HCMD1 CDAT1_[3:0] HDAT1_[3:0] SD CARD INTERFACE SD PORT1 4 HOST PROCESSOR I/O LEVEL TRANSLATORS USB HS CARD READER HOST I/O USB TRANSCEIVER MAX14500- MAX14503 USB CONNECTOR D+ CD+ HD+ D- CD- HD- USB USB SWITCHES Figure 8. Card Reader Mode. The USB port is connected to SD card 1. In the 2 port version, a second SD card (SD slot 2) can be independently connected and disconnected to the host P. When the card reader is initiated in the control register, the internal USB switch disconnects from the host P USB port and connects to the internal USB Hi-Speed SD card reader unit. When the MAX14500-MAX14503 disconnect from the host to implement a stand-alone high-speed card reader, it simulates a disconnect on the host USB and SD ports to maintain data coherence. The SD connections are restored to the host P by closing the analog switch connecting CCRD_PRST to HCRD_PRST. Certain registers execute actions when entering Card Reader mode. These actions are only valid for Card Reader mode. Writing to these registers in Sleep mode, or when awake, updates the registers, but the action is carried out when Card Reader mode is activated for one of the SD cards (see the Register Map section). When Card Reader mode is initially entered, the internal microcontroller enumerates with the PC to establish a high-speed USB mass storage device. No actions by the host P are required for enumeration other than entering Card Reader mode. Once the USB-SD card connection is established, PC to SD card data transfer begins and various interrupts monitor the status the of Card Reader mode if enabled. The BSY flag is represented externally by the BUSY output and can be read serially through I2C. The BUSY output is always active. If the host P requests Sleep mode in the middle of the data transfer, the MAX14500-MAX14503 do not complete the transfer, exit Card Reader mode, reconnect USB switches, and ______________________________________________________________________________________ 21 MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass PASS THRU CARD READER (TRANSFER DATA) IF ASLEEP SD COMMAND IN PROGRESS REQUEST TO ENTER CARD READER REQUEST TO SLEEP OR PASS THRU IF AWAKE NO SD COMMAND IN PROGRESS * DISCONNECT SD SWITCHES FOR CARD READER * ENUMERATE SD CARD * OPEN USB SWITCHES * ASSERT BUSY * SET BUSY FLAG * ENUMERATE PC * DEENUMERATE PC * CLOSE USB SWITCHES * DEENUMERATE SD CARD * RESTORE SD SWITCHES TO I2C SETTINGS * DEASSERT BUSY * CLEAR BUSY FLAG Figure 9. Card Reader Flow Chart go to sleep. Because the BUSY output (BSY bit in I2C) indicates Card Reader mode, the host P may monitor this output after commanding a mode change to determine when the change takes place (Figure 9). If the host requests the other SD card to enter Card Reader mode, the busy flag deasserts and reasserts to let the host know that the change took place. Simple Control (I2C_SEL = Low) The MAX14500-MAX14503 feature a very simple control scheme for entering Card Reader mode that requires a single logic (GPIO) from the host P. The simple control may only be used with the single SD port versions. When I2C_SEL is connected low at startup, the MODE input controls whether the device is in Pass Thru or Card Reader mode. Driving MODE low enables Pass Thru mode (Figure 10), and the host P has a direct connection to the SD card and USB connector through internal analog switches. Driving MODE high enables Card Reader mode between SD card 1 and the PC through the USB connector (Figure 11). BERR/INT functions as the bridge error output BERR that asserts for card reader errors. Interrupts are not enabled, the clock source is set to the default as 22 defined by the part number, and the BERR and BUSY outputs are active. Upon MODE transitioning high, SD card 1 connects to the USB connector in Card Reader mode and BUSY asserts low. The BUSY output indicates that the device is in Card Reader mode. BUSY may be important to the host P, as the time to complete enumeration/de-enumeration may take a long time (> 100ms). I2C Control (I2C_SEL = High) The MAX14500-MAX14503 feature I 2 C control that allows access to internal registers for complete control over configuration, SD port analog switches, interrupts, clock configuration, advanced power-on states, and error status. I2C control uses I2C to serially program the MAX14500-MAX14503 to be in Card Reader or Pass Thru mode, and allows either SD card to be connected in Card Reader mode. While a SD card is connected in Card Reader mode, the other SD port analog switches can be independently controlled serially through I2C. Using the I2C bus to put the device to sleep minimizes the supply current while maintaining control over the SD port switches. ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass MAX14500-MAX14503 SD PORT 1 SWITCHES HCRD_PRST CCRD_PRST SD SLOT 1 4 CCLK1 HCLK1 CCMD1 HCMD1 SD PORT1 HDAT1_[3:0] CDAT1_[3:0] 4 HOST PROCESSOR SD CARD INTERFACE BUSY I/O LEVEL TRANSLATORS USB HS CARD READER USB TRANSCEIVER USB CONNECTOR BERR MODE = LOW HOST I/O I2C_SEL = LOW MAX14500- MAX14503 D+ CD+ HD+ D- CD- HD- USB USB SWITCHES Figure 10. I2C_SEL Connected Low to Enable Simple Control and MODE = 0 to Enable Pass Thru Control Register (0x00) Configuration Registers The control register controls the settings of SD port analog switches, Card Reader mode, and sleep (Table 2.) The state of the SD port analog switches can be changed when the device is in Sleep mode or in Card Reader mode, and actions are executed immediately. If SD card 1 is connected to the PC through USB in Card Reader mode, the state of the SD port 1 switches are ignored, but the SD port 2 switches can still be controlled through the Control register. Likewise, if SD card 2 is connected to the USB connector in Card Reader mode, the state of the SD port 2 switches are ignored, but the SD port 1 switches can still be controlled through the Control register. Changing the card reader bits in Sleep mode does not cause the device to enter Card Reader mode. Under this condition, the MAX14500-MAX14503 enter Card Reader mode upon waking up. The MAX14500-MAX14503 have three configuration registers (CONFIG1 = 0x01, CONFIG2 = 0x02, CONFIG3 = 0x03). The configuration registers control the SD bus bit data mode, interrupt polarity, interrupt clearance, clock configuration, SD clock, and USB speed for Card Reader mode. The default settings are shown in the Register Map section. Interrupts (INT) All interrupts are masked in the default reset state. There are two interrupt enable registers (IE1 = 0x04, IE2 = 0x05) and two interrupt request registers (IRQ1 = 0x10, IRQ2 = 0x11). The BERR/INT output functions as the bridge error output BERR in simple control and functions as an interrupt INT in I2C control. The polarity of INT and how INT is asserted can be programmed in CONFIG1. The INT output asserts for enabled interrupts and errors in Card Reader mode. The polarity of INT can be active-high or active-low, and INT can be pro- ______________________________________________________________________________________ 23 MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass Table 2. Control Register (0x00) BIT [7:5] DESCRIPTION VALUE 000 RESERVED SD PORT 2 ANALOG SWITCHES SD Port 2 is a set of six analog switches connecting the SD port to the SD card. This set contains: clock (CCLK2), command (CCMD2), and four data lines (CDAT2_[3:0]). The card-present line is not available for this port. This setting is ignored when Card Reader mode is enabled for this port. SD PORT 1 ANALOG SWITCHES SD Port 1 is a set of seven analog switches connecting the SD port to the SD card. This set contains: card-present (CCRD_PRST), clock (CCLK1), command (CCMD1), and four data lines (CDAT1_[3:0]). The difference between Port 1 and Port 2 is the card-present line. This setting is ignored when Card Reader mode is enabled for this port. 4 3 0 1 0 1 00, 11 [2:1] CARD READER MODE Changing these bits in Sleep mode does not execute the action until the host P wakes up the MAX14500-MAX14503. 01 10 0 WAKEUP In Sleep mode, the MAX14500-MAX14503 are in Pass Thru mode. SD port switches are controlled by their respective bits. Entering Sleep mode reduces the supply current by turning off the internal logic. Request to shut down may be delayed due to USB and deenumeration. grammed to stay asserted until the status register is read, or stay asserted for 10ms. If INT is programmed to stay asserted, a read to the status register is required to clear INT. INT can be programmed to be active-high or active-low when I2C_SEL is high (I2C control). INT is high impedance in Sleep mode (WAKEUP = 0), regardless of the INT polarity programmed in the I2C registers. Use a pullup or pulldown resistor for the desired inactive INT polarity state during Sleep mode. Interrupt Masking All interrupts are masked at power-up. While masked interrupts do not assert the INT output, they do register as changes in the interrupt request registers (IRQ1 and IRQ2). The status register (STATUS1 = 0x12) indicates the current state of the interrupt bits. If interrupts are masked, polling IRQ1 and IRQ2 indicate the fields with changes, and STATUS1 gives the current state. Reading the IRQ registers resets the interrupt request bits. If polling is used to read the device status, it is required to read both the status register and the interrupt request registers to check for state changes. 24 0 FUNCTION Set these bits to 0. Analog switches are open, disconnecting the SD port from the SD card. Analog switches are closed, connecting the SD port to the SD card. Analog switches are open, disconnecting the SD port from the SD card. Analog switches are closed, connecting the SD port to the SD card. Card Reader mode not active. Card Reader mode active: Connects to SD card 1. Card Reader mode active: Connects to SD card 2. DEFAULT 000 1 1 00 Request internal logic to shut down. 0 1 Wake up internal logic. USB Interrupts When enabled, the INT output asserts an interrupt for changes in the USB connection and if the operating system suspends the USB connection. VBUS is detected at the KVBUS input and changes in VBUS voltage can assert an interrupt when enabled. Power-Supply Interrupts The MAX14500-MAX14503 feature many advanced power-saving modes. VCC, VSD, and VTM do not need to be applied for I2C communication. Changes in VSD and VTM can assert an interrupt when enabled to indicate different power-saving modes (see the Power-Supply Modes section). Busy Interrupt When enabled, changes in the BSY bit can assert an interrupt (see the Busy Indication (BSY) section). SD Status Interrupt When enabled, the SDSTAT bit asserts an interrupt for card detection and removal upon entering Card Reader mode for the SD card socket configured as the card reader. The SDSTAT bit is not active during Pass Thru mode and does not change states in the IRQ registers upon card insertion and removal during Pass Thru mode. ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass MAX14500-MAX14503 SD PORT 1 SWITCHES HCRD_PRST CCRD_PRST SD SLOT 1 4 CCLK1 HCLK1 CCMD1 HCMD1 HDAT1_[3:0] CDAT1_[3:0] SD PORT1 4 HOST PROCESSOR SD CARD INTERFACE BUSY I/O LEVEL TRANSLATORS USB HS CARD READER BERR MODE = HIGH HOST I/O I2C_SEL = LOW USB TRANSCEIVER MAX14500- MAX14503 USB CONNECTOR D+ CD+ HD+ D- CD- HD- USB USB SWITCHES Figure 11. I2C_SEL is connected low to enable simple control and MODE = 1 to enable Card Reader mode for SD card 1. Error Checking In simple control, the BERR/INT output functions as BERR and indicates if an error occurs during Card Reader mode. If BERR asserts low to indicate an error, the MAX14500-MAX14503 stay in Card Reader mode. If the error clears, data transfer begins. BERR asserts if KVBUS, VTM, or VSD are not present. It is recommended that MODE be pulled low when BERR indicates an error to return the MAX14500-MAX14503 to Pass Thru mode for the host P to clear the error. In I2C control, BERR/INT functions as an interrupt output (INT) and asserts for errors encountered in Card Reader mode when interrupts are not masked. To find the source of the interrupt, read the interrupt request registers and status register. Busy Indication (BSY) The BUSY output is used in simple control and I2C control to indicate when Card Reader mode is active. In simple control, transitioning MODE high to low requests the internal microcontroller to enable Pass Thru mode. BUSY asserts low while in Card Reader mode and deasserts high in Pass Thru mode. The BSY bit in STATUS1 (0x12) behaves similarly with I2C control. The BUSY output is represented by the BSY bit. Requests to put the device to sleep or bypass (Pass Thru mode) while in Card Reader mode can be verified by checking the state of the BUSY signal or BSY bit. The BUSY output indicates the status of the BUSY flag in STATUS1. The BSY bit is 1 when the BUSY output asserts low. When enabled, changes in the busy flag cause an interrupt. In I2C control, either the BSY bit or the BUSY output give the status of the busy state. ______________________________________________________________________________________ 25 MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass RUNTIME NO NO INTERRUPT ACTIVITY OCCURS HAS INTERRUPT STATUS CHANGED? INTERRUPT REQUEST REGISTERS READ? NO YES NO IS INT ENABLED? YES * INTERRUPT STATUS REGISTER BIT UPDATED * INTERRUPT REQUEST REGISTER BIT SET YES CLEAR INT IS INTERRUPT MASK BIT ENABLED? YES INT ENABLED-BASED ON INTPULSE AND INTACTHI FIELD SETTINGS NOTE: THIS IS VALID FOR I2C CONTROL ONLY Figure 12. Typical Interrupt Servicing Flowchart Reset (RST) Drive RST low to reset all the registers to the default value and minimize the supply current. Sleep The MAX14500-MAX14503 can be put to sleep by programming the WAKEUP bit to 0 in the control register with I2C control, or by driving the MODE input low in simple control. This turns off the internal microcontroller to minimize current. Reads and writes to the I2C are still functional, and registers can be updated with new values. Most register actions do not take effect until the internal microcontroller wakes up or when Card Reader mode is enabled. The SD port analog switches can 26 change states while the internal microcontroller is in Sleep mode. The Register Map section shows which registers are enabled in Sleep mode, at power-up, and upon entering Card Reader mode. Clock Configuration The MAX14500-MAX14503 come preprogrammed to accept a 12MHz, 13MHz, 19.2MHz, or 26MHz default clock input with the clock squarer enabled for lowamplitude TCXO signals (see the Ordering Information/Selector Guide). This clock is used for the USB and SD subsystems and is not required for operation of the I2C interface. This allows the clock frequency to be changed in the system. The PLL subsystem con- ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass Table 3. Clock Source Bit Values CLKSOURCE SOURCE (MHz) NOTES 00000b See Ordering Information/ Selector Guide 00001b 19.2 Rail-to-rail square wave 00010b 19.2 Low-amplitude sine wave 00101b 13.0 Rail-to-rail square wave 00110b 13.0 Low-amplitude sine wave 01001b 12.0 Rail-to-rail square wave 01010b 12.0 Low-amplitude sine wave 01101b 26.0 Rail-to-rail square wave 01110b 26.0 Low-amplitude sine wave Default low-amplitude clock I2C Serial Interface Serial Addressing The MAX14500-MAX14503 operate as I2C slave devices that send and receive data through an I2C-compatible 2-wire interface. The interface uses a serial-data line (SDA) and a serial-clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master initiates all data transfers to and from the MAX14500-MAX14503, and generates the SCL clock that synchronizes the data transfer. The SDA line operates as both an input and an open-drain output requiring a pullup resistor on SDA. The SCL line operates only as an input. A pullup resistor is required on SCL if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output. Each transmission consists of a START (S) condition by a master, followed by the MAX14500-MAX14503's 7-bit slave address, plus a R/W bit, a register address byte, one or more data bytes, and finally a STOP (P) condition. START and STOP Conditions Both SCL and SDA remain high when the interface is idle. A master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high (Figure 13). When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. SDA SCL S P START CONDITION STOP CONDITION Figure 13. START and STOP Conditions ______________________________________________________________________________________ 27 MAX14500-MAX14503 sists of two blocks: a clock squarer input (enabled by default), which accepts low-signal amplitude TCXO signals (down to 200mV), and a PLL with fixed dividers. The PLL sub system can be configured using the I2C interface. The complete list of PLL subsystem combinations are listed in Table 3. MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass SDA SCL DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED Figure 14. Bit Transfer START CONDITION CLOCK PULSE FOR ACKNOWLEDGE 1 SCL 2 8 9 SDA BY TRANSMITTER SDA BY RECEIVER S Figure 15. Acknowledge SDA 1 1 1 0 0 0 ADD ACK R/W MSB LSB SCL Figure 16. Slave Address Bit Transfer One data bit is transferred during each clock pulse (Figure 14). The data on SDA must remain stable while SCL is high. Acknowledge The acknowledge bit is a clocked 9th bit (Figure 15), which the recipient uses to handshake receipt of each byte of data. Each byte transferred effectively requires nine bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse. The SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX14500-MAX14503, the MAX14500-MAX14503 generate the acknowledge bit because the MAX14500-MAX14503 are the recipients. When the MAX14500-MAX14503 are transmitting to the master, the master generates the acknowledge bit because the master is the recipient. 28 Slave Addresses The MAX14500-MAX14503 have a 7-bit long slave address. The bit following the 7-bit slave address is the R/W bit, which is low for a write command and high for a read command. The address bit ADD is externally driven high or low by the ADD input to select between two slave addresses to avoid conflict with other I2C addresses (Figure 16). Table 4 shows the binary values for reads and writes. Table 4. Slave Addresses ADD FUNCTION DEVICE ADDRESS High Read 1 1 1 0 0 0 1 1 High Write 1 1 1 0 0 0 1 0 GND Read 1 1 1 0 0 0 0 1 GND Write 1 1 1 0 0 0 0 0 ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass MAX14500-MAX14503 0 = WRITE ADDRESS = 0xE0 S 1 1 1 0 REGISTER ADDRESS = 0x01 0 0 0 0 A 0 REGISTER 0x01 WRITE DATA D7 D6 D5 D4 D3 D2 D1 D0 A/A 0 0 0 0 0 0 1 A S = START BIT P = STOP BIT A = ACK A = NACK D_ = DATA BIT P Figure 17. Format for I2C Write. In this example the register 0x01 is written. 0 = WRITE ADDRESS = 0xE0 S 1 1 1 0 0 REGISTER ADDRESS = 0x01 0 0 0 A 0 0 D6 D5 D4 D3 D2 0 0 0 0 1 A D1 D0 A/A REGISTER 0x02 WRITE DATA REGISTER 0x01 WRITE DATA D7 0 D1 D0 A D7 D6 D5 D4 D3 D2 P Figure 18. Format for Writing to Multiple Registers. In this example, registers 0x01 and 0x02 are written in sequence. Format for Writing A write to the MAX14500-MAX14503 comprises the transmission of the slave address with the R/W bit set to zero, followed by at least 1 byte of information. The first byte of information is the register address or command byte. The register address determines which register of the MAX14500-MAX14503 is to be written by the next byte if received. If a STOP condition is detected after the register address is received, then the MAX14500- MAX14503 take no further action beyond storing the register address (Figure 17). Any bytes received after the register address are data bytes. The first data byte goes into the register selected by the register address and subsequent data bytes go into subsequent registers (Figure 18). If multiple data bytes are transmitted before a STOP condition, these bytes are stored in subsequent registers because the register address autoincrements. Format for Reading The MAX14500-MAX14503 are read using the internally stored register address as an address pointer, the same way the stored register address is used as an address pointer for a write. The pointer autoincrements after each data byte is read using the same rules used for a write. Thus, a read is initiated by first configuring the register address by performing a write (Figure 19). The master can now read consecutive bytes from the MAX14500-MAX14503, with the first data byte being read from the register addressed pointed by the previously written register address (Figure 20). Once the master sends a NACK, the MAX14500-MAX14503 stop sending valid data. Applications Information SD Ports The MAX14500-MAX14503 support one or two SD cards or SD interface NAND flash memory. SD Ports Configuration There are three operational configurations: * 40-pin TQFN version, containing one host port and one SD card (Figures 1, 2) * 56-bump WLP version, containing two SD host ports and two SD cards. There are two SD hosts and two SD memory cards. Use this mode if the host has two SD ports (Figure 3). ______________________________________________________________________________________ 29 MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass 0 = WRITE ADDRESS = 0xE0 S 1 1 1 0 0 REGISTER ADDRESS = 0x01 0 0 0 0 A 0 0 0 0 0 0 1 A P D1 D0 A/A P 0 0 A P D1 D0 A D1 D0 A 1 = READ ADDRESS = 0xE1 S 1 1 1 0 0 REGISTER 0x01 READ DATA 0 0 1 A D7 D6 D5 D4 D3 D2 Figure 19. Format for Reading 0 = WRITE ADDRESS = 0xE0 S 1 1 1 0 0 REGISTER ADDRESS = 0x00 0 0 0 0 A 0 0 0 0 0 1 = READ ADDRESS = 0xE1 S 1 1 1 1 0 REGISTER 0x00 READ DATA 0 0 1 A D7 D6 REGISTER 0x01 READ DATA D7 D6 D5 D4 D3 D2 D5 D4 D3 D2 REGISTER 0x02 READ DATA D1 D0 A D1 D0 A D7 D6 D5 D4 D3 D2 REGISTER 0x03 READ DATA D7 D6 D5 D4 D3 D2 P Figure 20. Format for Reading Multiple Registers * 56-bump WLP version, containing one port and two SD cards. The host SD ports 1 and 2 are connected together at the host. This configuration allows two SD cards connected to one host, but only one SD card is connected to the host at a time. The host uses the MAX14500-MAX14503's internal SD port switches to multiplex between the cards. This configuration can also be used to limit the bus capacitive loading of having two cards connected at the same time to the bus (Figure 4). SD Card Clock Frequency The SD card clock frequency is the lower of the maximum the card can support as read from the SD card and base SD clock (base SD clock is determined from values shown in Table 5). The MAX14500-MAX14503 30 internally read the max frequency directly from the SD card. In I2C control, the maximum clock frequency is programmable to values lower than the maximum allowed by the SD card, helping with issues such as excessive bus capacitance causing data errors. Table 5. Maximum SD Card Clock Frequency INPUT FREQUENCY (MHz) BASE SD CLOCK (MHz) 12 48 13 52 19.2 48 26 52 ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass MAX14500-MAX14503 VSD MAX14500-MAX14503 SD PORT1 SWITCH MECHANICAL CARD DETECT SWITCH CCRD_PRST HCRD_PRST CARD PRESENT INPUT CCMD1 HCMD1 CCLK1 HCLK1 CDAT1_[3:0] HDAT1_[3:0] HOST SD PORT SD CARD VSD MAX14500-MAX14503 SD PORT2 SWITCH MECHANICAL CARD DETECT SWITCH CARD PRESENT INPUT CCMD2 HCMD2 CCLK2 HCLK2 CDAT2_[3:0] HDAT2_[3:0] HOST SD PORT SD CARD Figure 21. Host Card Detection Schemes SD Port Switches The SD port analog switches change states immediately whether the MAX14500-MAX14503 are in Sleep mode (WAKEUP = 0) or awake. If the internal USB Hi-Speed SD card reader is in operation, the SD card switches for the selected path are opened automatically. Any writes to the SD port switch bits for that path are ignored. The SD port analog switches for the path not being used for the card reader are controllable by the host P, and any writes to these bits affect state changes immediately. Card Detection The MAX14500-MAX14503 provide an analog switch to pass the card present signal on SD card slot 1. This allows the host P to continue using the SD slot card present switch (see Figure 21). The internal analog switch can be bypassed if an alternate algorithm is used to detect card data change. The second SD card path does not provide this analog switch so if this path is used for another SD card socket, an alternate carddetection mechanism for the host P may be needed. If the second SD card path is used for an SD interface NAND chip, no card detection is required. The MAX14500-MAX14503 do not use the SD card slot switch to detect insertion and removals. Instead, a pro- tocol-based detection mechanism is used that polls for the presence or absence of an SD card. This allows both path 1 and path 2 to support an SD card slot with removable SD cards without a connection between the MAX14500-MAX14503 and the SD socket card present switch. The pullup voltage for the card slot detection may be any voltage equal to or less than VSD. Enumeration The MAX14500-MAX14503 enumerate to the USB mass storage class and appear as a USB mass storage device on most operating systems. USB Hi-Speed vs. Full-Speed The MAX14500-MAX14503 support USB Hi-Speed and full-speed operation. The MAX14500-MAX14503 operate at 480Mbps when plugged into a Hi-Speed USB host, and at 12Mbps when plugged into a full-speed host. USB VID/PID Using I2C, the MAX14500-MAX14503 have dedicated I2C registers for vendor identification (VID) and product identification (PID). The programmed 16-bit default values are shown in the Register Map section. The factory default values can be replaced with your company's VID and PID. ______________________________________________________________________________________ 31 MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass Power-Supply Modes The MAX14500-MAX14503 have four power-supply inputs (Table 6). Bypass VCC, VIO, VSD, and VTM with high-frequency, surface-mount ceramic capacitors as close as possible to the supply pins. Table 6. Power-Supply Inputs SUPPLY FUNCTION RANGE (V) VTM USB transceiver and USB switch power +2.91 to +3.4 VCC Digital core 1.8V LDO +2.1 to +3.6 VSD SD card level translator and SD switches +2.0 to +3.6 VIO Host microprocessor level translator +1.5 to +3.6 Power-supply inputs: 1) VTM USB Transceiver Power. This supply powers the USB analog switches, PLL subsystem, and the USB 2.0 transceiver. This regulator can be internal to a power-management IC, or it can be discrete and is recommended to be powered from USB VBUS. This supply must be present when the MAX14500- MAX14503 are used in Card Reader mode to pass USB signals in Pass Thru mode. 2) VCC Digital Logic Power. This supply powers the digital logic/internal microcontroller/flash memory. There is an internal +1.8V LDO (CLDO) with shutdown controlled by the state of the MODE input and internal logic. 3) VSD SD Card Power. This supply powers the SD card level translator and SD card switches. V SD needs to be present to pass SD signals in Pass Thru mode. Power modes: 1) Idle. Only VIO is required to be present. I2C registers can be updated, but no operation is possible. 2) Pass Thru Mode. VIO needs to be present so the voltage level at MODE can be detected. To allow USB pass thru, the VTM supply needs to be present. To allow SD pass thru, VSD supply needs to be present. Each supply is independent from the others and no power-supply sequencing is required. 3) Card Reader Mode. All supplies are needed. When the card reader is actively transferring data, this mode draws the most current, mainly from VCC and VTM. Layout Considerations The MAX14500-MAX14503 support Hi-Speed USB and requires careful PCB layout. Use controlled-impedance matched traces of equal lengths to the USB connector with no discontinuities and a minimum number of feedthroughs. All SD traces (CLK, CMD, DAT_) should be of equal lengths and as short as possible. Choosing Pullup Resistors I2C requires pullup resistors to provide a logic-high level to data and clock lines. There are tradeoffs between power dissipation and speed, and a compromise must be made in choosing pullup resistor values. Every device connected to the bus introduces some capacitance, even when the device is not in operation. I2C specifies 300ns rise time to go from low to high (30% to 70%) for fast mode, which is defined for data rates up to 400kbps. To meet the rise time requirement, choose pullup resistors so the rise time (tR) is less than 300ns where tR 0.85 x RPULLUP x CBUS. If the transition time becomes too slow, the setup and hold times may not be met and waveforms may not be recognized. 4) VIO Host Interface Power. This supply powers the digital I/O and I2C interface. 32 ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass FIELD NAME READ WRITE BITS RESET DESCRIPTION VALID WHEN CONTROL: Control Register (0x00) RFU R/W [7:5] 000 Reserved for future use SD2SW R/W 4 1 Setting of SD port 2 switches: 0 = open 1 = closed Powered SD1SW R/W 3 1 Setting of SD port 1 switches: 0 = open 1 = closed Powered MODE R/W [2:1] 00 Activates PC USB Hi-Speed SD card reader: 00 = not active 01 = card reader active for SD port 1 10 = card reader active for SD port 2 11 = not active WAKEUP R/W 0 0 Wakes the internal C: 0 = requests C to shut down 1 = wakes C -- WAKEUP = 1 Powered CONFIG1: Configuration Register 1 (0x01) SD2ONEBIT R/W 7 0 Force the SD port 2 bus to 1 bit mode: 0 = SD bus 4-bit data mode 1 = SD bus 1-bit data mode Enter Card Reader mode SD1ONEBIT R/W 6 0 Force the SD port 1 bus to 1 bit mode: 0 = SD bus 4-bit data mode 1 = SD bus 1-bit data mode Enter Card Reader mode INTPULSE R/W 5 0 INT assertion method: 0 = INT stays asserted until STATUS register is read 1 = INT asserts for 10ms pulse WAKEUP = 1 INTACTHI R/W 4 0 INT pin active level: 0 = active-low 1 = active-high WAKEUP = 1 RFU R/W [3:0] 0000 Reserved for future use -- Reserved for future use -- CONFIG2: Configuration Register 2 (0x02) RFU CLKSOURCE R/W R/W 7 [6:2] 0 00000 Sets the configuration for the clock input: 00000 = default 00001 = 19.2MHz rail-to-rail square wave 00010 = 19.2MHz low-amplitude AC-coupled sine wave 00101 = 13MHz rail-to-rail square wave 00110 = 13MHz low-amplitude AC-coupled sine wave 01001 = 12MHz rail-to-rail square wave 01010 = 12MHz low-amplitude AC-coupled sine wave 01101 = 26MHz rail-to-rail square wave 01110 = 26MHz low-amplitude AC-coupled sine wave All other values = default Enter Card Reader mode ______________________________________________________________________________________ 33 MAX14500-MAX14503 Register Map MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass Register Map (continued) READ WRITE BITS RESET FORCEFS R/W 1 0 Sets the maximum USB speed: 0 = Hi-Speed 1 = full speed RFU R/W 0 0 Reserved for future use FIELD NAME DESCRIPTION VALID WHEN Enter Card Reader mode -- CONFIG3: Configuration Register 3 (0x03) SD2MAXCLK SD1MAXCLK R/W R/W [7:4] [3:0] 0000 Limits the max clock for SD card 2. The SD clock will be the minimum of either this register or the SD card max speed register. 0111 = base SD clock/64 0110 = base SD clock/32 0101 = base SD clock/16 0100 = base SD clock/8 0011 = base SD clock/4 0010 = base SD clock/2 0001 = base SD clock 0000 = default (base SD clock) Enter Card Reader mode 0000 Limits the max clock for SD card 1. The SD clock will be the minimum of either this register or the SD card max speed register. 0111 = base SD clock/64 0110 = base SD clock/32 0101 = base SD clock/16 0100 = base SD clock/8 0011 = base SD clock/4 0010 = base SD clock/2 0001 = base SD clock 0000 = default (base SD clock) Enter Card Reader mode IE1: Interrupt Enable Register 1 (0x04) RFU R/W 7 0 Reserved for future use -- Powered USBFS R/W 6 0 Full-speed status change: 0 = disable contribution to INT 1 = enable contribution to INT USBSR R/W 5 0 USB suspend-resume status change: 0 = disable contribution to INT 1 = enable contribution to INT Powered VTM R/W 4 0 VTM voltage-detector change: 0 = disable contribution to INT 1 = enable contribution to INT Powered VSD R/W 3 0 VSD voltage-detector change: 0 = disable contribution to INT 1 = enable contribution to INT Powered KVBUS R/W 2 0 VBUS voltage-detector change: 0 = disable contribution to INT 1 = enable contribution to INT Powered 34 ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass FIELD NAME BUSY SDSTAT READ WRITE BITS RESET R/W 1 0 BUSY state change: 0 = disable contribution to INT 1 = enable contribution to INT Powered 0 0 SD card status change: 0 = disable contribution to INT 1 = enable contribution to INT Note: Reflects currently selected card in Card Reader mode Powered 0 Firmware update status change: 0 = disable contribution to INT 1 = enable contribution to INT Powered R/W DESCRIPTION VALID WHEN IE2: Interrupt Enable Register 2 (0x05) FWUPD R/W 7 RFU R/W [6:0] 0000000 Reserved for future use -- USBVIDH: USB Vendor ID High Byte (0x06) VID 1 R/W [7:0] 0x00 Bits 15-8 of USB vendor ID reported during card reader enumeration. If this register is written, the written value is used for USB enumeration, otherwise a default VID of 0x06BA (Maxim Integrated Products) is used. Enter Card Reader mode 0x00 Bits 7-0 of USB vendor ID reported during card reader enumeration. If this register is written, the written value is used for USB enumeration, otherwise a default VID of 0x06BA (Maxim Integrated Products) is used. Enter Card Reader mode 0x00 Bits 15-8 of USB product ID reported during card reader enumeration. If this register is written, the written value is used for USB enumeration, otherwise a default PID of 0x38A4 is used. Enter Card Reader mode Enter Card Reader mode USBVIDL: USB Vendor ID Low Byte (0x07) VID 2 R/W [7:0] USBPIDH: USB Product ID High Byte (0x08) PID 1 R/W [7:0] USBPIDL: USB Product ID Low Byte (0x09) PID 2 R/W [7:0] 0x00 Bits 7-0 of USB product ID reported during card reader enumeration. If this register is written, the written value is used for USB enumeration, otherwise if zero, a default PID of 0x38A4 is used. R/W -- 0x00 Do not write to this register -- R/W -- 0x00 Do not write to this register -- R/W -- 0x00 Do not write to this register -- R/W -- 0x00 Do not write to this register -- Test Register (0x0A) Test Register Test Register (0x0B) Test Register Test Register (0x0C) Test Register Test Register (0x0D) Test Register ______________________________________________________________________________________ 35 MAX14500-MAX14503 Register Map (continued) MAX14500-MAX14503 Hi-Speed USB-to-SD Card Readers with Bypass Register Map (continued) FIELD NAME READ WRITE BITS RESET R/W -- 0x00 Do not write to this register -- [7:0] 0x00 Contact factory. Do not write to this register. -- DESCRIPTION VALID WHEN Test Register (0x0E) Test Register FWP: Firmware Portal (0x0F) Firmware Portal R/W IRQ1: Interrupt Request Register 1 (0x10) RFU R 7 Reserved for future use Enter Card Reader mode -- USBFS R 6 0 = no change in USB full-speed mode status 1 = change in USB full-speed mode status USBSR R 5 0 = no change in USB suspend/resume status 1 = change in USB suspend/resume status Enter Card Reader mode VTM R 4 0 = no change in VTM detector status 1 = change in VTM detector status WAKEUP = 1 VSD R 3 0 = no change in VSD detector status 1 = change in VSD detector status WAKEUP = 1 VBUS R 2 0 = no change in VBUS detector status 1 = change in VBUS detector status WAKEUP = 1 BSY R 1 0 = no change in BUSY status 1 = change in BUSY status WAKEUP = 1 SDSTAT R 0 0 = no change in SD card present status 1 = change in SD card present status Enter Card Reader mode IRQ2: Interrupt Request Register 2 (0x11) Contact factory Code download Firmware Update R 7 RFU R [6:0] Reserved for future use -- -- STATUS1: Status Register 1 (0x12) RFU R 7 Reserved for future use USBFS R 6 0 = no connection or Hi-Speed connection 1 = full-speed connection Enter Card Reader mode USBSR R 5 0 = USB resume 1 = USB suspend Enter Card Reader mode VTM R 4 0 = no voltage 1 = VTM supply present WAKEUP = 1 VSD R 3 0 = no voltage 1 = VSD supply present WAKEUP = 1 VBUS R 2 0 = no voltage 1 = VBUS supply present WAKEUP = 1 BSY R 1 0 = not busy 1 = busy WAKEUP = 1 36 ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass READ WRITE FIELD NAME SDSTAT BITS R 0 RESET DESCRIPTION The insert/removal status is only valid for the card currently set to Card Reader mode (Reg 0x00 bits 1-2) 0 = no card 1 = card present VALID WHEN Enter Card Reader mode STATUS2: Status Register 2 (0x13) RFU R [7:0] Reserved for future use -- FWUGRRH: Firmware Upgrade Response Data High Byte (0x14) High Byte of Response Data R [7:0] Contact factory Code download FWUPGRL: Firmware Upgrade Response Data Low Byte (0x15) Low Byte of Response Data Code download R [7:0] Contact factory R [7:0] Reserved for future use -- R [7:0] Reserved for future use -- R [7:0] Reserved for future use -- R [7:0] Reserved for future use -- R [7:0] Reserved for future use -- RFU Register (0x16) RFU RFU Register (0x17) RFU RFU Register (0x18) RFU RFU Register (0x19) RFU RFU Register (0x1A) RFU Firmware Incremental Revision (0x1B) Firmware Incremental Revision [7:0] Firmware incremental revision WAKEUP = 1 [7:0] Firmware minor revision WAKEUP = 1 R [7:0] Firmware major revision WAKEUP = 1 R [7:0] Chip revision WAKEUP = 1 R [7:0] 0x00 = 40-lead TQFN 0x05 = 56-bump WLP 0xFF = unknown WAKEUP = 1 R Firmware Minor Revision (0x1C) Firmware Minor Revision R Firmware Major Revision (0x1D) Firmware Major Revision Chip Revision (0x1E) Chip Revision Package Type (0x1F) Package Type ______________________________________________________________________________________ 37 MAX14500-MAX14503 Register Map (continued) Hi-Speed USB-to-SD Card Readers with Bypass MAX14500-MAX14503 Functional Diagram VSD VIO 0.1F 1F VIO VSD SD SLOT CCMD2 DAT 0 DAT 1 HCLK2 CLK HCMD2 CMD CDAT 2_0 HDAT 2_0 DAT 0 CDAT 2_1 HDAT 2_1 DAT 1 DAT 2 CDAT 2_2 HDAT 2_2 DAT 2 DAT 3 CDAT 2_3 HDAT 2_3 DAT 3 SD_DETECT CCRD_PRST HCRD_PRST SD_DETECT CLK CCLK 1 HCLK1 CLK CMD CCMD 1 HCMD1 CMD DAT 0 CDAT 1_0 HDAT 1_0 DAT 0 DAT 1 CDAT 1_1 HDAT 1_1 DAT 1 DAT 2 CDAT 1_2 HDAT 1_2 DAT 2 DAT 3 CDAT 1_3 HDAT 1_3 DAT 3 SD PORT 1 SWITCHES SD PORT1 SD CARD CCLK2 CMD SD PORT2 SD INTERFACE NAND FLASH CLK SD PORT 2 SWITCHES SD CARD INTERFACE LEVEL TRANSLATORS VCC CLDO 1F MODE 1.8V LDO MICROCONTROLLER FLASH KVBUS 6.19k 1% VTM (+2.91V TO +3.4V) RREF VBUS DET USB SIE USB 2.0 TRANSCEIVER SRAM ROM OSC BUSY BERR/INT HOST INTERFACE 0.1F I/O LEVEL TRANSLATORS VCC SCL SDA RST VIO ADD I2C_SEL HOST PROCESSOR VTM 1F 1.5k 48/52MHz PLL SQR FREF TCXO CD+ HD+ D+ D- CD- HD- D- USB CONNECTOR USB SWITCHES MAX14500-MAX14503 VBUS 38 ______________________________________________________________________________________ USB D+ Hi-Speed USB-to-SD Card Readers with Bypass CD- CD+ KVBUS RREF GND FREF GND VTM HCRD_PRST HCLK1 TOP VIEW 30 29 28 27 26 25 24 23 22 21 20 19 18 17 31 32 33 34 MAX14500 MAX14501 MAX14502 MAX14503 35 36 37 38 39 VSD 40 1 2 3 I2C_SEL SCL SDA + *EP 4 5 6 7 HD+ HDGND HDAT1_0 HDAT1_1 13 12 HDAT1_2 HDAT1_3 CDAT1_0 CDAT1_1 11 CDAT1_2 8 9 10 CDAT1_3 VCC 16 15 14 BUSY MODE RST CCLK1 CCRD_PRST CCMD1 N.C. N.C. GND CLDO ADD VIO BERR/INT HCMD1 TQFN *CONNECT EXPOSED PAD TO GND. ______________________________________________________________________________________ 39 MAX14500-MAX14503 Pin Configurations Hi-Speed USB-to-SD Card Readers with Bypass MAX14500-MAX14503 Pin Configurations (continued) TOP VIEW (BUMPS ON BOTTOM) 8 7 6 5 4 3 2 1 MAX14500-MAX14503 A CDAT1_3 BUSY VIO CDAT2_3 HDAT2_3 ADD SCL VSD B CDAT1_1 RST BERR/INT CDAT2_2 VCC SDA CLDO CLDO C CDAT1_0 CDAT1_2 MODE I2C_SEL HDAT2_2 VCC GND GND D HDAT1_1 HDAT1_0 HDAT1_2 HDAT1_3 HDAT2_0 N.C. CDAT2_0 CDAT2_1 E GND GND FREF KVBUS CCLK1 N.C. CCMD1 HDAT2_1 F HD- CD- VTM RREF CCMD2 CCLK2 HCRD_PRST CCRD_PRST G HD+ CD+ GND GND HCMD2 HCLK2 HCLK1 HCMD1 WLP Package Information Chip Information PROCESS: CMOS 40 For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 40 TQFN-EP T4055-1 21-0140 56 WLP W563B3+1 21-0090 ______________________________________________________________________________________ Hi-Speed USB-to-SD Card Readers with Bypass REVISION NUMBER REVISION DATE 0 4/08 Initial release 4/09 Fixed data sheet to reflect new rev material including EC table, Pin Description, Applications Information, Functional Diagram, and Pin Configurations 1 DESCRIPTION PAGES CHANGED -- 1-41 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 41 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX14500-MAX14503 Revision History