General Description
The MAX14500–MAX14503 USB-to-SD™ card readers
provide a means for portable devices that support full-
speed USB communication (12Mbps) with one or two
SD card slots, upgrading the USB SD card reader func-
tion to USB Hi-Speed (480Mbps) operation. The
MAX14500–MAX14503 have two modes of operation:
Pass Thru and Card Reader. In pass thru, the SD and
USB signals pass through the MAX14500–MAX14503
without modification, appearing like the device is not
present. The host microprocessor firmware does not
need modification, as there is no change from the host
microprocessor’s perspective. In Card Reader mode,
the MAX14500–MAX14503 implement a Hi-Speed USB
card reader that operates independently of the host
microprocessor. All the capabilities of the full-speed
USB port and SD card slot are preserved with the addi-
tional feature that allows a faster way for a PC to read or
write to the SD card. The MAX14500–MAX14503 sup-
port SD high capacity SDHC cards. The 40-pin TQFN
version supports one SD card, while the 56-bump WLP
version supports two SD cards.
The MAX14500–MAX14503 feature advanced power-
saving modes to reduce power consumption in
portable applications. The low-power Sleep modes
allow the ability to disable internal circuit blocks, pro-
viding power-saving operating modes. The default
clock input for each part number is specified in the
ordering information. The MAX14500–MAX14503 fea-
ture the option to change the default values using the
I2C interface.
The MAX14500–MAX14503 are available in 5mm x
5mm, 40-pin TQFN, and 3.23mm x 3.5mm, 56-bump
WLP packages. These devices operate over a wide
supply voltage range and are specified over the -40°C
to +85°C extended temperature range.
Features
♦USB 2.0 Hi-Speed and Full-Speed Compliant
♦SDHC Card Support
♦Internal Hi-Speed USB SD Card Reader Eases
Host µP Overhead
♦On-Chip Termination and Pullup Resistors
♦Internal SD Switches Allow For Multiplexing Two
SD Cards on a Single-Microprocessor SD Port
♦Accommodates Clock Input Frequencies
26MHz, 19.2MHz, 13MHz, and 12MHz
♦Internal Clock Squarer for Low-Amplitude TCXO
Signals
♦No Power-Supply Sequencing Required
♦Compatible with +1.8V to +3.3V I/O Host
Microprocessor
♦Simple Control Mode Requires Only a Single
GPIO
♦I2C Control Provides Multiple Configuration
Options
♦I2C Control Required for Two SD Cards
♦On-Chip Power-On Reset/Brown-Out Reset
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
________________________________________________________________
Maxim Integrated Products
1
Ordering Information/
Selector Guide
19-4117; Rev 1; 4/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART
INPUT
FREQUENCY
(MHz)
SD
CARDS
PIN-
PACKAGE
MAX14500ETL+* 12 1 40 TQFN-EP**
MAX14500AEWN+* 12 2 56 WLP
MAX14501ETL+* 13 1 40 TQFN-EP**
MAX14501AEWN+* 13 2 56 WLP
MAX14502AETL+ 19.2 1 40 TQFN-EP**
MAX14502AEWN+* 19.2 2 56 WLP
MAX14503ETL+* 26 1 40 TQFN-EP**
MAX14503AEWN+* 26 2 56 WLP
Applications
Cell Phones
PDAs
MP3 Players
Digital Still Cameras
GPS
Note: All devices are specified over the -40°C to +85°C oper-
ating temperature range.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
Future product—contact factory for availability.
**
EP = Exposed pad.
SD is a trademark of the SD Card Association.
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
2 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS
(VCC = +2.4V to +3.6V, VSD = +2.4V to +3.6V, VIO = +1.5V to +3.6V, VTM = +2.91V to +3.4V, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC CHARACTERISTICS
Pass thru 2.1 3.6
Card reader active, fCCLK_ ≤ 26MHz 2.1 3.6VCC Supply Voltage VCC
Card reader active, fCCLK_ > 26MHz 2.4 3.6
V
Pass thru 2.0 3.6
Card reader active, fCCLK_ ≤ 26MHz 2.0 3.6VSD Supply Voltage VSD
Card reader active, fCCLK_ > 26MHz 2.4 3.6
V
Logic Interface Supply Voltage VIO 1.5 3.6 V
USB Supply Voltage VTM 2.91 3.4 V
Digital Core LDO Regulator
Output Voltage VCLDO CCLDO = 1.0µF 1.8 V
Pass thru 5 15 µA
VCC Supply Current ICC Card reader active 35 50 mA
Pass thru 17 40 µA
VSD Supply Current ISD Card reader active 3 mA
Pass thru 2 10 µA
VIO Supply Current IIO Card reader active 0.2 mA
Pass thru 13 50 µA
VTM Supply Current ITM Card reader active 25 mA
VSD Comparator Threshold VSDCT 1.0 1.5 1.9 V
VTM Comparator Threshold VTMCT 2.0 2.5 2.9 V
MODE, I2C_SEL, ADD, RST
Input-Voltage Low VIL 0.4 V
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
VCC ...........................................................................-0.3V to +4V
VSD ...........................................................................-0.3V to +4V
VIO ............................................................................-0.3V to +4V
VTM ...........................................................................-0.3V to +4V
KVBUS......................................................................-0.3V to +4V
CLDO........................................................................-0.3V to +2V
CDAT1_[3:0], HDAT1_[3:0], CCMD1, HCMD1, CCLK1, HCLK1,
CCRD_PRST, HCRD_PRST, CDAT2_[3:0], HDAT2_[3:0],
CCMD2, HCMD2, CCLK2, HCLK2 .........-0.3V to (VSD + 0.3V)
BUSY, BERR/INT, MODE, SCL, SDA, I2C_SEL,
ADD, RST.................................................-0.3V to (VIO + 0.3V)
CD+, CD-, HD+, HD-, RREF, FREF ............-0.3V to (VTM + 0.3V)
Continuous Power Dissipation (TA= +70°C)
40-Pin TQFN (derate 35.7mW/°C above +70°C) ........2857mW
Junction-to-Case Thermal Resistance (θJC) (Note 1)
40-Pin TQFN ................................................................1.7°C/W
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
40-Pin TQFN .................................................................28°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MODE, I2C_SEL, ADD, RST
Input-Voltage High VIH 2/3 x
VIO V
BUSY, BERR/INT
Output-Voltage Low VOL ILOAD = 1mA 0.4 V
BUSY, BERR/INT
Output-Voltage High VOH ILOAD = -1mA VIO -
0.4 V
I2C_SEL, ADD, RST Input
Leakage Current IIL -1 +1 µA
MODE Input Resistance to GND RMODE 150 300 500 kΩ
FREF Full-Swing Input-Voltage
High VIH 1.3 V
FREF Full-Swing Input-Voltage
Low VIL 0.4 V
FREF Low-Amplitude Input-
Voltage Low VIL 200 mV
FREF Input Leakage Current IILF Full-Swing mode -10 +10 µA
FREF Input Resistance Low-Amplitude input mode 1 MΩ
KVBUS Comparator Threshold VTH 1.0 1.25 1.5 V
KVBUS Comparator Hysteresis VHYS 20 mV
KVBUS Comparator Input
Impedance RIN 10 MΩ
SDA/SCL Input Low Voltage VIL_I2C 0.3 x
VIO V
SDA/SCL Input High Voltage VIH_I2C 0.7 x
VIO V
VIO > +2V, 3mA sink current 0 0.4
SDA Output Logic-Low VOL_I2C VIO ≤ +2V, 3mA sink current 0 0.2 x
VIO
V
SDA/SCL Input Leakage Current IIN_I2C -10 +10 µA
SD CARD INTERFACE
On-Resistance RON VTEST = 0 or VSD, ITEST = 10mA (Note 3) 10 Ω
Off-Leakage Current IILSD VTEST = 0 or VSD (Note 3) -1 +1 µA
Off-Capacitance CSD_OFF (Note 4) 5 pF
On-Capacitance CSD_ON (Note 5) 10 pF
Pullup Resistance RPU CCMD1, CCMD2, CDAT1_[3:0],
CDAT2_[3:0] 50 75 100 kΩ
Output High Voltage VOH IOH = -100µA 0.75 x
VSD V
Output Low Voltage VOL IOL = 100µA 0.125 x
VSD V
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.4V to +3.6V, VSD = +2.4V to +3.6V, VIO = +1.5V to +3.6V, VTM = +2.91V to +3.4V, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA= +25°C.) (Note 2)
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
4 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VSD < 2.4V 0.8 x
VSD
Input High Voltage VIH
VSD ≥ 2.4V 0.625 x
VSD
V
VSD < 2.4V 0.2 x
VSD
Input Low Voltage VIL
VSD ≥ 2.4V 0.25 x
VSD
V
USB INTERFACE
On-Resistance RON VCD_ = 0 or VTM, switch closed 5 Ω
On-Resistance Flatness RONFLAT VCD_ = 0 to 3.3V, VTM = +3.3V 2 Ω
On-Capacitance CON_USB Switch closed, measured from CD+ and
CD- 12 pF
Off-Capacitance COFF_USB Switch open, measured from CD+, CD-,
HD+, HD- 6pF
AC CHARACTERISTICS (Note 6)
SD CARD CLOCK TIMING (CCLK_), DEFAULT SPEED (Figure 5a)
Clock Low Time tWL CL = 10pF 19 ns
Clock High Time tWH CL = 10pF 19 ns
Clock Rise Time tTLH CL = 10pF 10 ns
Clock Fall Time tTHL CL = 10pF 10 ns
SD CARD CLOCK TIMING (CCLK_), HI-SPEED (Figure 5b)
Clock Low Time tWL CL = 40pF 7 ns
Clock High Time tWH CL = 40pF 7 ns
Clock Rise Time tTLH CL = 40pF 3 ns
Clock Fall Time tTHL CL = 40pF 3 ns
SD CARD COMMAND TIMING (CCMD1, CCMD2) (Figure 5b)
Input Setup Time tISU 5ns
Input Hold Time tIH 2ns
Output Delay Time During Data
Transfer Mode tODLY 14 ns
Output Hold Time tOH 2.5 ns
I2C CHARACTERISTICS
SCL Clock Frequency fSCL 400 kHz
SDA, SCL Capacitance CIO_I2C 5pF
SDA Output Fall Time tOF_I2C 250 ns
Hold Time After Repeated START tHD,STA 0.6 µs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.4V to +3.6V, VSD = +2.4V to +3.6V, VIO = +1.5V to +3.6V, VTM = +2.91V to +3.4V, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA= +25°C.) (Note 2)
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Clock Low Period tLOW_I2C 1.3 µs
Clock High Period tHIGH_I2C 0.6 µs
Setup Time for Repeated START tSU,STA 0.6 µs
Hold Time for Data tHD,DAT 0 0.9 µs
Setup Time for Data tSU,DAT 100 ns
SDA/SCL Input Fall Time tF_I2C 300 ns
SDA/SCL Rise Time tR_I2C 300 ns
Setup Time for STOP tSU,STO 0.6 µs
Bus Free Time Between STOP
and START tBUF 1.3 µs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.4V to +3.6V, VSD = +2.4V to +3.6V, VIO = +1.5V to +3.6V, VTM = +2.91V to +3.4V, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC CHARACTERISTICS
Hi-Speed Squelch Detection
Threshold (Diff Signal Amplitude) VHSSQ (Note 6) 100 150 mV
Hi-Speed Differential Input
Signaling Levels VIL Specified by Hi-Speed receive eye diagram
Hi-Speed Data Signaling
Common-Mode Voltage Range SCM (Note 6) -50 +500 mV
Hi-Speed Idle Level VHSOI -10 +10 mV
Hi-Speed Data Signaling High VHSOH 360 440 mV
Hi-Speed Data Signaling Low VHSOL -10 +10 mV
Chirp J Level (Differential
Voltage) VCHIRPJ 700 1100 mV
Chirp K Level (Differential
Voltage) VCHIRPK -900 -500 mV
Ter m i nati on V ol tag e ( Hi-Speed) VHSTERM -10 +10 mV
AC CHARACTERISTICS
Rise Time tHSR (Note 6) 500 ps
Fall Time tHSF (Note 6) 500 ps
Driver Waveform Requirements S p eci fi ed b y H i - S p eed tr ansm i t eye d i ag r am See the Typical Operating
Characteristics section
Driver-Output Resistance ZHSDRV 40.5 49.5 Ω
Source Jitter Total (Including
Frequency Tolerance) S p eci fi ed b y H i - S p eed tr ansm i t eye d i ag r am See the Typical Operating
Characteristics section
USB HI-SPEED SOURCE ELECTRICAL CHARACTERISTICS
(VCC = +2.4V to +3.6V, VSD = +2.4V to +3.6V, VIO = +1.5V to +3.6V, VTM = +2.91V to +3.4V, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA= +25°C.) (Note 2)
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
6 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC CHARACTERISTICS
SE Receiver Input High VIH 2.0 V
SE Receiver Input Low VIL 0.8 V
Differential Common-Mode
Voltage VCM 0.8 2.0 V
Receiver Differential Input
Sensitivity VDI 0.2 V
Transmitter High VOH RL = 15kΩ connected to GND 2.8 3.6 V
Transmitter Low VOL RL = 1.5kΩ connected to 3.3V 0 0.3 V
Transmitter Output Signal
Crossover Voltage VCRS (Note 6) 1.3 2.0 V
Bus Pullup Resistor on Upstream
Facing Port (Idle Bus) RPUI 0.900 1.25 1.575 kΩ
Bus Pullup Resistor on Upstream
Facing Port (Upstream Port
Receiving)
RPUA 1.425 2.5 3.090 kΩ
Input Impedance ZINP 300 kΩ
Termination Voltage for Upstream
Facing Port Pullup (RPU)VTERM VTM V
AC CHARACTERISTICS
Rise Time tFR 420ns
Fall Time tFF 420ns
Differential Rise and Fall Time
Matching tFRFM (Note 6) 90 111.11 %
Full-Speed Data Rate tFDRATHS 11.994 12.030 Mbps
USB FULL-SPEED SOURCE ELECTRICAL CHARACTERISTICS
(VCC = +2.4V to +3.6V, VSD = +2.4V to +3.6V, VIO = +1.5V to +3.6V, VTM = +2.91V to +3.4V, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA= +25°C.) (Note 2)
Note 2: All parameters are tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 3: On-resistance is measured by applying voltage and current on the SD card interface (CCLK1, CCMD1, CDAT1_[3:0],
CCLK2, CCMD2, CDAT2_[3:0]).
Note 4: Off-capacitance measured with SD switch open (CCLK1, HCLK1, CCMD1, HCMD1, CDAT1_[3:0], HDAT1_[3:0], CCLK2,
HCLK2, CCMD2, HCMD2, CDAT2_[3:0], HDAT2_[3:0]).
Note 5: On-capacitance measured on SD card side (CCLK1, CCMD1, CDAT1_[3:0], CCLK2, CCMD2, CDAT2_[3:0]).
Note 6: Specifications guaranteed by design.
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
_______________________________________________________________________________________
7
HI-SPEED EYE DIAGRAM
FOR CARD READER MODE
MAX14500 toc01
UNIT TIME INTERVAL
DIFFERENTIAL VOLTAGE
0
2
6
4
8
10
0.9 1.71.3 2.1 2.5 2.9 3.3
USB ON-RESISTANCE
vs. USB COMMON VOLTAGE (VCD_)
MAX14500 toc02
VCD_ COMMON VOLTAGE (V)
RON (Ω)
VTM = 3.3V
0
10
5
20
15
30
25
35
0 1.00.5 1.5 2.0 2.5
SD CHANNEL ON-RESISTANCE
vs. SD CHANNEL COMMON VOLTAGE
MAX14500 toc03
SD CHANNEL COMMON VOLTAGE (V)
SD CHANNEL ON-RESISTANCE (Ω)
VSD = +3V
0
2
1
4
3
5
6
2.0 2.82.4 3.2 3.6
PASS THRU VCC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX14500 toc04
VCC SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
NO CLOCK
4
3
2
1
0
1.5 2.41.8 2.1 2.7 3.0 3.3
PASS THRU VIO SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX14500 toc05
VIO SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
NO CLOCK
0
10
5
20
15
25
30
1.8 3.3
PASS THRU VSD SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX14500 toc06
VSD SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
2.42.1 2.7 3.0
NO CLOCK
Typical Operating Characteristics
(VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA= +25°C, unless otherwise noted.)
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VCC = +3.3V, VIO = +2.5V, VSD = +2.5V, VTM = +3.3V, TA= +25°C, unless otherwise noted.)
0
-20
0.1 1 10 100 1000
PASS THRU USB CHANNEL
FREQUENCY RESPONSE
-16
MAX14500 toc10
FREQUENCY (MHz)
ON-LOSS (dB)
-12
-8
-4
-6
-10
-14
-18
-2
0.1 1 10 100 1000
PASS THRU SD CHANNEL
OFF-ISOLATION
MAX14500 toc11
FREQUENCY (MHz)
OFF-ISOLATION (dB)
0
-80
-60
-40
-20
0
2
6
4
8
10
-40 10-15 35 60 85
PASS THRU VCC SUPPLY CURRENT
vs. TEMPERATURE
MAX14500 toc07
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
NO CLOCK 33
32
31
30
29
2.0 2.82.4 3.2 3.6
CARD READER VCC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX14500 toc08
VCC SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
DEVICE ENUMERATED
DATA RATE = 0Mbps
17
19
18
21
20
22
23
2.9 3.4
CARD READER VTM SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX14500 toc009
VTM SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.13.0 3.2 3.3
DEVICE ENUMERATED
DATA RATE = 0Mbps
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
_______________________________________________________________________________________ 9
Pin Description
PIN
TQFN WLP NAME FUNCTION
INPUTS/OUTPUTS
1 C4 I2C_SEL I2C Select Input. I2C_SEL must be connected to VIO or GND at power-up. Drive
I2C_SEL low to disable I2C control and drive I2C_SEL high to enable I2C control.
2 A2 SCL I2C Serial-Clock Input. SCL is +3.6V tolerant and the high threshold is set by VIO. If
the I2C interface is not used, connect SCL to GND.
3 B4 SDA I2C Serial-Data I/O. SDA is +3.6V tolerant and the high threshold is set by VIO. If the
I2C interface is not used, connect SDA to GND.
4 A3 ADD I2C Address Selection Input. Connect ADD to VIO or GND to select between two I2C
slave addresses: (GND = 1110 000Xb and VIO = 1110 001Xb).
6B6BERR/INT
Card Reader Error/Interrupt Output. BERR/INT becomes BERR for simple control and
INT for I2C control. BERR/INT goes low to indicate an error in Card Reader mode
during simple control and asserts for enabled interrupts during I2C control.
7A7BUSY Busy Output. BUSY asserts low to indicate device is in Card Reader mode.
8 C6 MODE
Card Reader/Pass Thru Mode Select Input. MODE is only active during simple
control. Drive MODE low to enable Pass Thru mode and drive MODE high to enable
Card Reader mode. For I2C control, MODE must be connected to GND.
9B7RST Reset Input. Drive RST low to reset the internal registers to default values and put all
outputs in high impedance. Connect RST to VIO for normal operation.
25 E6 FREF
Frequency Input. FREF is the clock input (12MHz/13MHz/19.2MHz/26MHz) for the
internal logic and USB PHY. FREF can accept a square-wave or sine-wave clock. An
internal clock squaring circuit can be enabled or disabled through I2C. In simple
control, the internal clock squarer is enabled by default.
27 F5 RREF Reference Resistor. Connect a Bias Resistor 6.19kΩ ±1% from RREF to GND.
USB INTERFACE
22 G7 CD+ USB Analog Switch/Hi-Speed USB Transceiver. CD+ connects to D+ on the USB
connector.
21 F7 CD- USB Analog Switch/Hi-Speed USB Transceiver. CD- connects to D- on the USB
connector.
20 G8 HD+ USB Analog Switch. HD+ connects to D+ on the host side.
19 F8 HD- USB Analog Switch. HD- connects to D- on the host side.
28 E5 KVBUS USB Bus Power-Supply Detection Input. Connect a resistor-divider between USB
VBUS, KVBUS, and GND.
SD CARD INTERFACE
13 C8 CDAT1_0 SD Card 1 Data Bus Analog Switch/Card Reader Interface. CDAT1_0 connects to
DAT0 on the SD card.
12 B8 CDAT1_1 SD Data Card 1 Bus Analog Switch/Card Reader Interface. CDAT1_1 connects to
DAT1 on the SD card.
11 C7 CDAT1_2 SD Data Card 1 Bus Analog Switch/Card Reader Interface. CDAT1_2 connects to
DAT2 on the SD card.
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
10 ______________________________________________________________________________________
Pin Description (continued)
PIN
TQFN WLP NAME FUNCTION
10 A8 CDAT1_3 SD Card 1 Data Bus Analog Switch/Card Reader Interface. CDAT1_3 connects to
DAT3 on the SD card.
34 E2 CCMD1 SD Card 1 Command Analog Switch/Card Reader Interface. CCMD1 connects to
CMD on the SD card.
32 E3 CCLK1 SD Card 1 Clock Analog Switch/Card Reader Interface. CCLK1 connects to CLK on
the SD card.
33 F1 CCRD_PRST
SD Card 1 Analog Switch for Card Present Detection. CCRD_PRST is the card
detection line to the SD socket. When in Pass Thru mode, CCRD_PRST is connected
to HCRD_PRST.
17 D7 HDAT1_0 SD Card 1 Data Bus Analog Switch. HDAT1_0 connects to DAT0 on the SD port of
the host µP.
16 D8 HDAT1_1 SD Card 1 Data Bus Analog Switch. HDAT1_1 connects to DAT1 on the SD port of
the host µP.
15 D6 HDAT1_2 SD Card 1 Data Bus Analog Switch. HDAT1_2 connects to DAT2 on the SD port of
the host µP.
14 D5 HDAT1_3 SD Card 1 Data Bus Analog Switch. HDAT1_3 connects to DAT3 on the SD port of
the host µP.
31 G1 HCMD1 SD Card 1 Command Analog Switch. HCMD1 connects to CMD on the SD port of the
host µP.
29 G2 HCLK1 S D C ar d 1 C l ock Anal og S w i tch. H C LK1 connects to C LK on the S D p or t of the host µP .
30 F2 HCRD_PRST SD Card 1 Analog Switch for Card Present Detection. HCRD_PRST is connected to
CCRD_PRST in Pass Thru mode.
— D2 CDAT2_0 SD Card 2 Data Bus Analog Switch/Card Reader Interface. CDAT2_0 connects to
DAT0 on the SD card.
— D1 CDAT2_1 SD Card 2 Data Bus Analog Switch/Card Reader Interface. CDAT2_1 connects to
DAT1 on the SD card.
— B5 CDAT2_2 SD Card 2 Data Bus Analog Switch/Card Reader Interface. CDAT2_2 connects to
DAT2 on the SD card.
— A5 CDAT2_3 SD Card 2 Data Bus Analog Switch/Card Reader Interface. CDAT2_3 connects to
DAT3 on the SD card.
— F4 CCMD2 SD Card 2 Command Analog Switch/Card Reader Interface. CCMD2 connects to
CMD on the SD card.
— F3 CCLK2 SD Card 2 Clock Analog Switch/Card Reader Interface. CCLK2 connects to CLK on
the SD card.
— D3 HDAT2_0 SD Card 2 Data Bus Analog Switch. HDAT2_0 connects to DAT0 on the SD port of
the host µP.
— E1 HDAT2_1 SD Card 2 Data Bus Analog Switch. HDAT2_1 connects to DAT1 on the SD port of
the host µP.
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 11
Pin Description (continued)
PIN
TQFN WLP NAME FUNCTION
— C5 HDAT2_2 SD Card 2 Data Bus Analog Switch. HDAT2_2 connects to DAT2 on the SD port of
the host µP.
— A4 HDAT2_3 SD Card 2 Data Bus Analog Switch. HDAT2_3 connects to DAT3 on the SD port of
the host µP.
— G4 HCMD2 SD Card 2 Command Analog Switch. HCMD2 connects to CMD on the SD port of the
host µP.
— G3 HCLK2 S D C ar d 2 C l ock Anal og S w i tch. H C LK2 connects to C LK on the S D p or t of the host µP .
POWER SUPPLY
5A6V
IO I/O Logic-Level Translator Voltage. Bypass VIO to GND with a 0.1µF ceramic
capacitor. VIO powers the logic inputs/outputs and I2C block.
23 F6 VTM USB Analog Switch and Transceiver Power Supply. Bypass VTM to GND with a 0.1µF
ceramic capacitor.
38 B1, B2 CLDO
Bypass Capacitor for Internal +1.8V LDO. Connect a 1µF ceramic capacitor (X7R,
X5R, or better) from CLDO to GND. CLDO must not be used to power external
circuitry.
39 B3, C3 VCC Digital Supply Voltage. Bypass VCC to GND with a 1µF ceramic capacitor (X7R, X5R,
or better).
40 A1 VSD SD Card Voltage. Bypass VSD to GND with a 1µF ceramic capacitor (X7R, X5R, or
better).
18, 24, 26,
37
C1, C2, E7,
E8, G5, G6 GND Ground
NO CONNECTION
35, 36 D4, E4 N.C. No Connection. Connect N.C. to GND.
EXPOSED PAD
— — EP Exposed Pad. Connect EP to GND. Do not use EP as the sole GND connection.
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
12 ______________________________________________________________________________________
USB
USB
CONNECTOR
D+
D-
SD SLOT
SIMPLE CONTROL
VIO
FREF
VBUS
SD CARD
INTERFACE
VSD
VCC
MODE
I2C_SEL
ADD
SDA
SCL
USB HS
CARD READER
VSD
44
GND
HCRD_PRST
HCLK1
HCMD1
HDAT1_[3:0]
CCRD_PRST
CCLK1
CCMD1
CDAT1_[3:0]
CLDO
KVBUS
CD+
CD-
HD+
HD-
USB
TRANSCEIVER
VCC BERR
BUSY
VTM
USB SWITCHES
VTM
SD PORT 1 SWITCHES
RREF
I/O LEVEL
TRANSLATORS
VIO
HOST I/O
HOST
PROCESSOR
SD
PORT
MAX14500–
MAX14503
Figure 1. Typical Application Circuit for Simple Control Mode with One SD Card
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 13
USB
CONNECTOR
D+
D-
SD SLOT
VIO
FREF
VBUS
SD CARD
INTERFACE
VSD
VCC MODE
I2C_SEL
ADD
SDA
SCL
USB HS
CARD READER
VSD
44
GND
HCRD_PRST
HCLK1
HCMD1
HDAT1_[3:0]
CCRD_PRST
CCLK1
CCMD1
CDAT1_[3:0]
CLDO
KVBUS
CD+
CD-
HD+
HD-
USB
TRANSCEIVER
VCC INT
BUSY
VTM
USB SWITCHES
VTM
SD PORT 1 SWITCHES
RREF
I/O LEVEL
TRANSLATORS
VIO
HOST I/O
HOST
PROCESSOR
SD
PORT
OPTIONAL
VIO
USB
MAX14500–
MAX14503
I2C CONTROL
Figure 2. Typical Application Circuit for I2C Control Mode with One SD Card
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
14 ______________________________________________________________________________________
USB
CONNECTOR
D+
D-
VBUS
GND
USB
HOST I/O
HOST
PROCESSOR
SD
PORT1
VIO
VTM
SD SLOT1
FREF
SD CARD
INTERFACE
VSD
VCC MODE
INT
I2C_SEL
SDA
SCL
USB HS
CARD READER
44
HCRD_PRST
HCLK1
HCMD1
HDAT1_[3:0]
CCRD_PRST
CCLK1
CCMD1
CDAT1_[3:0]
CLDO
CD+
CD-
HD+
HD-
USB
TRANCEIVER
SD SLOT2
4
HCLK2
HCMD2
HDAT2_[3:0]
CCLK2
CCMD2
CDAT2_[3:0]
BUSY
VIO
ADD
VIO
OPTIONAL
RREF
KVBUS
SD PORT 2 SWITCHES
SD PORT 1 SWITCHES
VCC
VSD
I/O LEVEL
TRANSLATORS
VTM
USB SWITCHES
SD
PORT2
4
MAX14500–
MAX14503
I2C CONTROL
Figure 3. Typical Application Circuit for I2C Control Mode with Two SD Cards
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 15
USB
CONNECTOR
D+
D-
VBUS
GND
USB
HOST I/O
HOST
PROCESSOR
SD
PORT
VIO
VTM
SD SLOT1
FREF
SD CARD
INTERFACE
VSD
VCC MODE
INT
I2C_SEL
SDA
SCL
USB HS
CARD READER
44
HCRD_PRST
HCLK1
HCMD1
HDAT1_[3:0]
CCRD_PRST
CCLK1
CCMD1
CDAT1_[3:0]
CLDO
CD+
CD-
HD+
HD-
USB
TRANCEIVER
SD SLOT2
4
HCLK2
HCMD2
HDAT2_[3:0]
CCLK2
CCMD2
CDAT2_[3:0]
BUSY
VIO
ADD
VIO
OPTIONAL
RREF
KVBUS
SD PORT 2 SWITCHES
SD PORT 1 SWITCHES
VCC
VSD
I/O LEVEL
TRANSLATORS
VTM
USB SWITCHES
MAX14500–
MAX14503
I2C CONTROL
Figure 4. Typical Application Circuit for I2C Control Mode with One SD Port and Two SD Cards
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
16 ______________________________________________________________________________________
fPP
tWL tWH
tTLH
tIH
tODLY
(min)
SHADED AREAS ARE NOT VALID
tTHL
tISU
tODLY (max)
VIH
VIL
VIH
VIL
VOH
VOL
CLOCK
INPUT
OUTPUT
Figure 5a. SD Card Default Timing Diagram
Timing Diagrams
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 17
fPP
tWL tWH
tTLH
tIH
tTHL
tISU
tODLY tOH
VIH
VIL
VIH
VIL
VOH
VOL
CCLK1
CCLK2
CDAT1 _[3:0],
CDAT2_[3:0],
CCMD1, CCMD2
(READ)
VOH
CDAT1 _[3:0],
CDAT2_[3:0],
CCMD1, CCMD2
(WRITE)
VIH
VIL
VOL
Figure 5b. SD Card Hi-Speed Timing Diagram
Timing Diagrams (continued)
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
18 ______________________________________________________________________________________
Detailed Description
The MAX14500–MAX14503 can be added to devices
that have an SD card slot and a USB full-speed port
(12Mbps) to provide a Hi-Speed USB path to an SD
card bypassing the host microprocessor (µP), allowing
for faster SD card transfers (Figures 1–4). Without the
MAX14500–MAX14503, a host µP with a full-speed USB
port moves data between an SD card and a host PC at
12Mbps when transferring data from an SD card
through USB. The host µP has additional overhead
because it has to accept data from the SD cards,
process the data by putting it in USB format, and then
transfer the data through the USB port. The MAX14500–
MAX14503 create an alternate path from the SD card to
USB, providing USB Hi-Speed capability. By bypassing
the host µP using the MAX14500–MAX14503, SD card
read and write operations are not limited by host µP
overhead and USB full-speed data rates.
The MAX14500–MAX14503 operate in Pass Thru and
Card Reader mode. In Pass Thru mode, the MAX14500–
MAX14503 are transparent to the host µP. All read and
write operations pass from the host µP SD port to the SD
card without modification. All of the features of the original
device are intact and there is no need to change firmware
in the host µP. In Card Reader mode, the SD card is con-
nected to the PC with the internal USB Hi-Speed card
reader, bypassing the host µP.
The MAX14500–MAX14503 can be controlled in two
ways. The simple control method uses a single output
from a µP or ASIC to select Pass Thru or Card Reader
mode. Only one SD card can be used as a Hi-Speed
USB card reader in simple control. I2C control allows
more configuration options and provides status informa-
tion along with error conditions and additional interrupts.
Two SD cards can be connected and each set of SD
port switches can be controlled independently (two SD
port version under I2C control). The state of I2C_SEL
must not change after VIO is applied.
With I2C control, the I2C bus is used to read and write to
internal registers for configuration, error checking, con-
trol, and status reporting. The control and configuration
registers have various functions including wakeup, SD
card selection, interrupt enable, and SD switch settings.
The status registers give the status of errors, SD card
detection, power supplies, and interrupts. Putting the
MAX14500–MAX14503 to sleep puts the device into
Pass Thru mode. The state of SD port switches for card 1
and card 2 can be changed while in Pass Thru. Some
I2C commands are executed upon waking up or entering
Card Reader mode. For register settings that involve
Card Reader mode, (when in Sleep mode), program-
ming the I2C registers changes the values, but the
actions do not execute until the internal logic wakes up
or Card Reader mode is entered. The register map indi-
cates when register bit changes take effect.
SDA
SCL
tHD,STA
tLOW_I2C
tHIGH_I2C
tR_I2C tF_I2C
tSU,DAT tSU,STA
tSU,STO
tBUF
tHD,STA
tHD,DAT
START
CONDITION
STOP
CONDITION
START
CONDITION
REPEATED
START CONDITION
tF_I2C
tR_I2C
Figure 6. I2C Timing Diagram
Timing Diagrams (continued)
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 19
REGISTER NAME
REGISTER
ADDRESS
(hex)
POWER-UP VALUE
(hex) POWER-UP DEFAULT SETTINGS
Control Register
(CONTROL) 0x00 0x18
SD2SW = 1, SD switch 2 is closed
SD1SW = 1, SD switch 1 is closed
MODE[1:0] = 00, Card Reader mode is not active
WAKEUP = 0, shutdown
Configuration
Register 1
(CONFIG1)
0x01 0x00
SD2ONEBIT = 0, SD2 bus in 4-bit data mode
SD1ONEBIT = 0, SD1 bus in 4-bit data mode
INTPULSE = 0, INT stays asserted until status register is read
INTACTHI = 0, INT asserts active low
Configuration
Register 2
(CONFIG2)
0x02 0x00 CLKSOURCE = 00000, default clock input
FORCEFS = 0, USB Hi-Speed
Configuration
Register 3
(CONFIG3)
0x03 0x00 SD2MAXCLK = 0000, default clock (base SD clock)
SD1MAXCLK = 0000, default clock (base SD clock)
Interrupt Enable
Register 1
(IE1)
0x04 0x00
USBFS = 0, disable INT for full-speed status change
USBSR = 0, disable INT for suspend/resume status change
VTM = 0, disable INT for VTM status change
VSD = 0, disable INT for VSD status change
KVBUS = 0, disable INT for VBUS status change
BSY = 0, disable INT for BUSY status change
SDSTAT = 0, disable INT for SD card status change
Interrupt Enable
Register 2
(IE2)
0x05 0x00 FWUPD = 0, disable INT for firmware update status change
USB Vendor ID
High Byte
(USBVIDH)
0x06 0x00 If VID = 0x0000, 0x06BA is used during USB enumeration,
VID high byte = 0x06
USB Vendor ID
Low Byte
(USBVIDL)
0x07 0x00 If VID = 0x0000, 0x06BA is used during USB enumeration,
VID low byte = 0xBA
USB Product ID
High Byte
(USBPIDH)
0x08 0x00 If PID = 0x0000, 0x38A4 is used during USB enumeration,
PID high byte = 0x38
USB Product ID
Low Byte
(USBPIDL)
0x09 0x00 If PID = 0x0000, 0x38A4 is used during USB enumeration.
PID low byte = 0xA4
Table 1. Power-Up Default Mini Register Map for Configuration Registers
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
20 ______________________________________________________________________________________
Default Power-Up (Pass Thru Mode)
In the default Pass Thru mode, the MAX14500–
MAX14503 are transparent and the existing host func-
tions (access to SD cards and USB) are preserved
(Figure 7). The host µP reads and writes data to the SD
card from the SD port, and can communicate to a PC
through its existing full-speed USB port. All of the fea-
tures of the original chipset are intact. The MAX14500–
MAX14503 sleep when in Pass Thru mode (WAKEUP =
0), when the MODE input is low, or when the MODE bits
[2:1] in control register (0x00) are set to Card Reader
mode, not active. In Sleep mode, the internal microcon-
troller is turned off and current consumption is mini-
mized. The settings for SD port switches for card 1 and
card 2 are controlled by SD port switch bits [4:3] in the
control register.
Card Reader Mode
In Card Reader mode, the PC communicates with the
SD card through USB with an internal Hi-Speed SD
card reader, bypassing the host µP. Figure 8 shows
card reader mode with SD card 1 connected to the PC
with the internal card reader. The 40-pin TQFN can
connect to a single SD card in Card Reader mode. With
the 56-bump WLP operating under I2C control, either
SD card can be selected for Card Reader mode.
CCLK2
CCMD2
CDAT2_[3:0]
HCLK2
HCMD2
HDAT2_[3:0] 4
4
SD
PORT2
SD
SLOT2
CD+
SD PORT 2 SWITCHES
HOST PROCESSOR
USB SWITCHES
CD-
D+
D-
HD+
HD-
USB
USB
CONNECTOR
SD CARD INTERFACE
USB HS
CARD READER
CCRD_PRST
SD PORT 1 SWITCHES
CCLK1
CCMD1
HCRD_PRST
HCLK1
HCMD1
4
4 CDAT1_[3:0] HDAT1_[3:0]
SD
PORT1
I/O LEVEL
TRANSLATORS
HOST
I/O
SD
SLOT1
USB
TRANSCEIVER
MAX14500–
MAX14503
Figure 7. Default Startup (Pass Thru Mode)
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 21
When the card reader is initiated in the control register,
the internal USB switch disconnects from the host µP
USB port and connects to the internal USB Hi-Speed
SD card reader unit. When the MAX14500–MAX14503
disconnect from the host to implement a stand-alone
high-speed card reader, it simulates a disconnect on
the host USB and SD ports to maintain data coherence.
The SD connections are restored to the host µP by clos-
ing the analog switch connecting CCRD_PRST to
HCRD_PRST.
Certain registers execute actions when entering Card
Reader mode. These actions are only valid for Card
Reader mode. Writing to these registers in Sleep mode,
or when awake, updates the registers, but the action is
carried out when Card Reader mode is activated for
one of the SD cards (see the
Register Map
section).
When Card Reader mode is initially entered, the internal
microcontroller enumerates with the PC to establish a
high-speed USB mass storage device. No actions by the
host µP are required for enumeration other than entering
Card Reader mode. Once the USB-SD card connection
is established, PC to SD card data transfer begins and
various interrupts monitor the status the of Card Reader
mode if enabled. The BSY flag is represented externally
by the BUSY output and can be read serially through
I2C. The BUSY output is always active. If the host µP
requests Sleep mode in the middle of the data transfer,
the MAX14500–MAX14503 do not complete the transfer,
exit Card Reader mode, reconnect USB switches, and
CCLK2
CCMD2
CDAT2_[3:0]
HCLK2
HCMD2
HDAT2_[3:0] 4
4
SD
PORT2
SD
SLOT2
CD+
SD PORT 2 SWITCHES
HOST PROCESSOR
USB SWITCHES
CD-
D+
D-
HD+
HD-
USB
USB
CONNECTOR
SD CARD INTERFACE
USB HS
CARD READER
CCRD_PRST
SD PORT 1 SWITCHES
CCLK1
CCMD1
HCRD_PRST
HCLK1
HCMD1
4
4 CDAT1_[3:0] HDAT1_[3:0]
SD
PORT1
I/O LEVEL
TRANSLATORS
HOST
I/O
SD
SLOT1
USB
TRANSCEIVER
MAX14500–
MAX14503
Figure 8. Card Reader Mode. The USB port is connected to SD card 1. In the 2 port version, a second SD card (SD slot 2) can be
independently connected and disconnected to the host µP.
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
22 ______________________________________________________________________________________
go to sleep. Because the BUSY output (BSY bit in I2C)
indicates Card Reader mode, the host µP may monitor
this output after commanding a mode change to deter-
mine when the change takes place (Figure 9). If the host
requests the other SD card to enter Card Reader mode,
the busy flag deasserts and reasserts to let the host
know that the change took place.
Simple Control (I2C_SEL = Low)
The MAX14500–MAX14503 feature a very simple con-
trol scheme for entering Card Reader mode that
requires a single logic (GPIO) from the host µP. The
simple control may only be used with the single SD port
versions. When I2C_SEL is connected low at startup,
the MODE input controls whether the device is in Pass
Thru or Card Reader mode. Driving MODE low enables
Pass Thru mode (Figure 10), and the host µP has a
direct connection to the SD card and USB connector
through internal analog switches. Driving MODE high
enables Card Reader mode between SD card 1 and
the PC through the USB connector (Figure 11).
BERR/INT functions as the bridge error output BERR
that asserts for card reader errors. Interrupts are not
enabled, the clock source is set to the default as
defined by the part number, and the BERR and BUSY
outputs are active. Upon MODE transitioning high, SD
card 1 connects to the USB connector in Card Reader
mode and BUSY asserts low. The BUSY output indi-
cates that the device is in Card Reader mode. BUSY
may be important to the host µP, as the time to com-
plete enumeration/de-enumeration may take a long
time (> 100ms).
I2C Control (I2C_SEL = High)
The MAX14500–MAX14503 feature I2C control that
allows access to internal registers for complete control
over configuration, SD port analog switches, interrupts,
clock configuration, advanced power-on states, and
error status. I2C control uses I2C to serially program the
MAX14500–MAX14503 to be in Card Reader or Pass
Thru mode, and allows either SD card to be connected
in Card Reader mode. While a SD card is connected in
Card Reader mode, the other SD port analog switches
can be independently controlled serially through I2C.
Using the I2C bus to put the device to sleep minimizes
the supply current while maintaining control over the
SD port switches.
PASS THRU
REQUEST
TO ENTER CARD
READER
REQUEST
TO SLEEP OR
PASS THRU
IF AWAKE
IF ASLEEP
NO SD COMMAND IN PROGRESS
SD COMMAND
IN PROGRESS
• DISCONNECT SD
SWITCHES FOR CARD READER
• ENUMERATE SD CARD
• OPEN USB SWITCHES
CARD READER
(TRANSFER DATA)
• DEENUMERATE PC
• CLOSE USB SWITCHES
• DEENUMERATE SD CARD
• RESTORE SD SWITCHES TO I2C SETTINGS
• DEASSERT BUSY
• CLEAR BUSY FLAG
• ASSERT BUSY
• SET BUSY FLAG
• ENUMERATE PC
Figure 9. Card Reader Flow Chart
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 23
Control Register (0x00)
The control register controls the settings of SD port
analog switches, Card Reader mode, and sleep (Table
2.) The state of the SD port analog switches can be
changed when the device is in Sleep mode or in Card
Reader mode, and actions are executed immediately. If
SD card 1 is connected to the PC through USB in Card
Reader mode, the state of the SD port 1 switches are
ignored, but the SD port 2 switches can still be con-
trolled through the Control register. Likewise, if SD card
2 is connected to the USB connector in Card Reader
mode, the state of the SD port 2 switches are ignored,
but the SD port 1 switches can still be controlled
through the Control register. Changing the card reader
bits in Sleep mode does not cause the device to enter
Card Reader mode. Under this condition, the
MAX14500–MAX14503 enter Card Reader mode upon
waking up.
Configuration Registers
The MAX14500–MAX14503 have three configuration reg-
isters (CONFIG1 = 0x01, CONFIG2 = 0x02, CONFIG3 =
0x03). The configuration registers control the SD bus
bit data mode, interrupt polarity, interrupt clearance,
clock configuration, SD clock, and USB speed for Card
Reader mode. The default settings are shown in the
Register Map
section.
Interrupts (INT)
All interrupts are masked in the default reset state.
There are two interrupt enable registers (IE1 = 0x04, IE2
= 0x05) and two interrupt request registers (IRQ1 =
0x10, IRQ2 = 0x11). The BERR/INT output functions as
the bridge error output BERR in simple control and func-
tions as an interrupt INT in I2C control. The polarity of
INT and how INT is asserted can be programmed in
CONFIG1. The INT output asserts for enabled interrupts
and errors in Card Reader mode. The polarity of INT can
be active-high or active-low, and INT can be pro-
HCRD_PRST
HCLK1
HCMD1
HDAT1_[3:0]
CD+
HOST PROCESSOR
USB SWITCHES
CD-
D+
D-
HD+
HD-
USB
USB
CONNECTOR
SD CARD INTERFACE
USB HS
CARD READER
CCRD_PRST
SD PORT 1 SWITCHES
CCLK1
CCMD1
BUSY
BERR
MODE = LOW
4
4 CDAT1_[3:0]
I2C_SEL = LOW
SD
PORT1
I/O LEVEL
TRANSLATORS
HOST
I/O
SD
SLOT 1
USB
TRANSCEIVER
MAX14500–
MAX14503
Figure 10. I2C_SEL Connected Low to Enable Simple Control and MODE = 0 to Enable Pass Thru
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
24 ______________________________________________________________________________________
grammed to stay asserted until the status register is
read, or stay asserted for 10ms. If INT is programmed to
stay asserted, a read to the status register is required to
clear INT. INT can be programmed to be active-high or
active-low when I2C_SEL is high (I2C control). INT is
high impedance in Sleep mode (WAKEUP = 0), regard-
less of the INT polarity programmed in the I2C registers.
Use a pullup or pulldown resistor for the desired inactive
INT polarity state during Sleep mode.
Interrupt Masking
All interrupts are masked at power-up. While masked
interrupts do not assert the INT output, they do register
as changes in the interrupt request registers (IRQ1 and
IRQ2). The status register (STATUS1 = 0x12) indicates
the current state of the interrupt bits. If interrupts are
masked, polling IRQ1 and IRQ2 indicate the fields with
changes, and STATUS1 gives the current state.
Reading the IRQ registers resets the interrupt request
bits. If polling is used to read the device status, it is
required to read both the status register and the inter-
rupt request registers to check for state changes.
USB Interrupts
When enabled, the INT output asserts an interrupt for
changes in the USB connection and if the operating
system suspends the USB connection. VBUS is detect-
ed at the KVBUS input and changes in VBUS voltage
can assert an interrupt when enabled.
Power-Supply Interrupts
The MAX14500–MAX14503 feature many advanced
power-saving modes. VCC, VSD, and VTM do not need to
be applied for I2C communication. Changes in VSD and
VTM can assert an interrupt when enabled to indicate dif-
ferent power-saving modes (see the
Power-Supply
Modes
section).
Busy Interrupt
When enabled, changes in the BSY bit can assert an
interrupt (see the
Busy Indication (BSY)
section).
SD Status Interrupt
When enabled, the SDSTAT bit asserts an interrupt for
card detection and removal upon entering Card Reader
mode for the SD card socket configured as the card
reader. The SDSTAT bit is not active during Pass Thru
mode and does not change states in the IRQ registers
upon card insertion and removal during Pass Thru mode.
BIT DESCRIPTION VALUE FUNCTION DEFAULT
[7:5] RESERVED 000 Set these bits to 0. 000
0
Analog switches are open,
disconnecting the SD port
from the SD card.
4
SD PORT 2 ANALOG SWITCHES
SD Port 2 is a set of six analog switches connecting the SD port to the
SD card. This set contains: clock (CCLK2), command (CCMD2), and
four data lines (CDAT2_[3:0]). The card-present line is not available
for this port. This setting is ignored when Card Reader mode is
enabled for this port.
1
Analog switches are
closed, connecting the SD
port to the SD card.
1
0
Analog switches are open,
disconnecting the SD port
from the SD card.
3
SD PORT 1 ANALOG SWITCHES
SD Port 1 is a set of seven analog switches connecting the SD port to
the SD card. This set contains: card-present (CCRD_PRST), clock
(CCLK1), command (CCMD1), and four data lines (CDAT1_[3:0]). The
difference between Port 1 and Port 2 is the card-present line. This
setting is ignored when Card Reader mode is enabled for this port.
1
Analog switches are
closed, connecting the SD
port to the SD card.
1
00, 11 Card Reader mode not
active.
01 Card Reader mode active:
Connects to SD card 1.
[2:1]
CARD READER MODE
Changing these bits in Sleep mode does not execute the action until
the host µP wakes up the MAX14500–MAX14503.
10 Card Reader mode active:
Connects to SD card 2.
00
0Request internal logic to
shut down.
0
WAKEUP
In Sleep mode, the MAX14500–MAX14503 are in Pass Thru mode. SD
port switches are controlled by their respective bits. Entering Sleep
mode reduces the supply current by turning off the internal logic.
Request to shut down may be delayed due to USB and de-
enumeration. 1 Wake up internal logic.
0
Table 2. Control Register (0x00)
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 25
Error Checking
In simple control, the BERR/INT output functions as
BERR and indicates if an error occurs during Card
Reader mode. If BERR asserts low to indicate an error,
the MAX14500–MAX14503 stay in Card Reader mode.
If the error clears, data transfer begins. BERR asserts if
KVBUS, VTM, or VSD are not present. It is recommend-
ed that MODE be pulled low when BERR indicates an
error to return the MAX14500–MAX14503 to Pass Thru
mode for the host µP to clear the error.
In I2C control, BERR/INT functions as an interrupt out-
put (INT) and asserts for errors encountered in Card
Reader mode when interrupts are not masked. To find
the source of the interrupt, read the interrupt request
registers and status register.
Busy Indication (BSY)
The BUSY output is used in simple control and I2C con-
trol to indicate when Card Reader mode is active. In
simple control, transitioning MODE high to low requests
the internal microcontroller to enable Pass Thru mode.
BUSY asserts low while in Card Reader mode and
deasserts high in Pass Thru mode.
The BSY bit in STATUS1 (0x12) behaves similarly with
I2C control. The BUSY output is represented by the BSY
bit. Requests to put the device to sleep or bypass
(Pass Thru mode) while in Card Reader mode can be
verified by checking the state of the BUSY signal or
BSY bit. The BUSY output indicates the status of the
BUSY flag in STATUS1. The BSY bit is 1 when the
BUSY output asserts low. When enabled, changes in
the busy flag cause an interrupt. In I2C control, either
the BSY bit or the BUSY output give the status of the
busy state.
HCRD_PRST
HCLK1
HCMD1
HDAT1_[3:0]
CD+
HOST PROCESSOR
USB SWITCHES
CD-
D+
D-
HD+
HD-
USB
USB
CONNECTOR
SD CARD INTERFACE
USB HS
CARD READER
CCRD_PRST
SD PORT 1 SWITCHES
CCLK1
CCMD1
BUSY
BERR
MODE = HIGH
4
4 CDAT1_[3:0]
I2C_SEL = LOW
SD
PORT1
I/O LEVEL
TRANSLATORS
HOST
I/O
SD
SLOT 1
USB
TRANSCEIVER
MAX14500–
MAX14503
Figure 11. I2C_SEL is connected low to enable simple control and MODE = 1 to enable Card Reader mode for SD card 1.
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
26 ______________________________________________________________________________________
Reset (
RST
)
Drive RST low to reset all the registers to the default
value and minimize the supply current.
Sleep
The MAX14500–MAX14503 can be put to sleep by pro-
gramming the WAKEUP bit to 0 in the control register
with I2C control, or by driving the MODE input low in
simple control. This turns off the internal microcontroller
to minimize current. Reads and writes to the I2C are still
functional, and registers can be updated with new val-
ues. Most register actions do not take effect until the
internal microcontroller wakes up or when Card Reader
mode is enabled. The SD port analog switches can
change states while the internal microcontroller is in
Sleep mode. The
Register Map
section shows which
registers are enabled in Sleep mode, at power-up, and
upon entering Card Reader mode.
Clock Configuration
The MAX14500–MAX14503 come preprogrammed to
accept a 12MHz, 13MHz, 19.2MHz, or 26MHz default
clock input with the clock squarer enabled for low-
amplitude TCXO signals (see the
Ordering
Information/Selector Guide
). This clock is used for the
USB and SD subsystems and is not required for opera-
tion of the I2C interface. This allows the clock frequency
to be changed in the system. The PLL subsystem con-
RUNTIME
NOTE: THIS IS VALID FOR I2C CONTROL ONLY
INTERRUPT
REQUEST REGISTERS
READ?
IS
INT ENABLED?
HAS
INTERRUPT STATUS
CHANGED?
IS INTERRUPT
MASK BIT
ENABLED?
YES
YES
YES
YES
• INTERRUPT STATUS
REGISTER BIT UPDATED
• INTERRUPT REQUEST
REGISTER BIT SET
CLEAR INT
INT ENABLED-BASED
ON INTPULSE AND
INTACTHI FIELD SETTINGS
INTERRUPT ACTIVITY
OCCURS
NO
NO
NO
NO
Figure 12. Typical Interrupt Servicing Flowchart
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 27
sists of two blocks: a clock squarer input (enabled by
default), which accepts low-signal amplitude TCXO sig-
nals (down to 200mV), and a PLL with fixed dividers.
The PLL sub system can be configured using the I2C
interface. The complete list of PLL subsystem combina-
tions are listed in Table 3.
I
2
C Serial Interface
Serial Addressing
The MAX14500–MAX14503 operate as I2C slave devices
that send and receive data through an I2C-compatible
2-wire interface. The interface uses a serial-data line
(SDA) and a serial-clock line (SCL) to achieve bidirec-
tional communication between master(s) and slave(s). A
master initiates all data transfers to and from the
MAX14500–MAX14503, and generates the SCL clock
that synchronizes the data transfer. The SDA line oper-
ates as both an input and an open-drain output requiring
a pullup resistor on SDA. The SCL line operates only as
an input. A pullup resistor is required on SCL if there are
multiple masters on the 2-wire interface, or if the master
in a single-master system has an open-drain SCL output.
Each transmission consists of a START (S) condition by
a master, followed by the MAX14500–MAX14503’s 7-bit
slave address, plus a R/Wbit, a register address byte,
one or more data bytes, and finally a STOP (P) condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is
idle. A master signals the beginning of a transmission
with a START condition by transitioning SDA from high
to low while SCL is high (Figure 13). When the master
has finished communicating with the slave, it issues a
STOP condition by transitioning SDA from low to high
while SCL is high. The bus is then free for another
transmission.
CLKSOURCE SOURCE (MHz) NOTES
00000b
See Ordering
Information/
Selector Guide
Default low-amplitude
clock
00001b 19.2 Rail-to-rail square wave
00010b 19.2 Low-amplitude sine
wave
00101b 13.0 Rail-to-rail square wave
00110b 13.0 Low-amplitude sine
wave
01001b 12.0 Rail-to-rail square wave
01010b 12.0 Low-amplitude sine
wave
01101b 26.0 Rail-to-rail square wave
01110b 26.0 Low-amplitude sine
wave
Table 3. Clock Source Bit Values
SDA
SCL
START
CONDITION
STOP
CONDITION
S P
Figure 13. START and STOP Conditions
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
28 ______________________________________________________________________________________
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 14). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 15),
which the recipient uses to handshake receipt of each
byte of data. Each byte transferred effectively requires
nine bits. The master generates the 9th clock pulse,
and the recipient pulls down SDA during the acknow-
ledge clock pulse. The SDA line is stable low during the
high period of the clock pulse. When the master is
transmitting to the MAX14500–MAX14503, the
MAX14500–MAX14503 generate the acknowledge bit
because the MAX14500–MAX14503 are the recipients.
When the MAX14500–MAX14503 are transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Slave Addresses
The MAX14500–MAX14503 have a 7-bit long slave
address. The bit following the 7-bit slave address is the
R/Wbit, which is low for a write command and high for
a read command. The address bit ADD is externally
driven high or low by the ADD input to select between
two slave addresses to avoid conflict with other I2C
addresses (Figure 16). Table 4 shows the binary values
for reads and writes.
SCL
SDA
BY
TRANSMITTER
CLOCK PULSE FOR
ACKNOWLEDGE
START
CONDITION
SDA
BY
RECEIVER
1 2 8 9
S
Figure 15. Acknowledge
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 14. Bit Transfer
SDA 1 ACK
SCL
MSB LSB
1 0 R/W1 0 0 ADD
Figure 16. Slave Address
ADD FUNCTION DEVICE ADDRESS
High Read 11100011
High Write 11100010
GND Read 11100001
GND Write 11100000
Table 4. Slave Addresses
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 29
Format for Writing
A write to the MAX14500–MAX14503 comprises the
transmission of the slave address with the R/Wbit set to
zero, followed by at least 1 byte of information. The first
byte of information is the register address or command
byte. The register address determines which register of
the MAX14500–MAX14503 is to be written by the next
byte if received. If a STOP condition is detected after
the register address is received, then the MAX14500–
MAX14503 take no further action beyond storing the
register address (Figure 17).
Any bytes received after the register address are data
bytes. The first data byte goes into the register selected
by the register address and subsequent data bytes go
into subsequent registers (Figure 18). If multiple data
bytes are transmitted before a STOP condition, these
bytes are stored in subsequent registers because the
register address autoincrements.
Format for Reading
The MAX14500–MAX14503 are read using the internal-
ly stored register address as an address pointer, the
same way the stored register address is used as an
address pointer for a write. The pointer autoincrements
after each data byte is read using the same rules used
for a write. Thus, a read is initiated by first configuring
the register address by performing a write (Figure 19).
The master can now read consecutive bytes from the
MAX14500–MAX14503, with the first data byte being
read from the register addressed pointed by the previ-
ously written register address (Figure 20). Once the
master sends a NACK, the MAX14500–MAX14503 stop
sending valid data.
Applications Information
SD Ports
The MAX14500–MAX14503 support one or two SD
cards or SD interface NAND flash memory.
SD Ports Configuration
There are three operational configurations:
• 40-pin TQFN version, containing one host port and
one SD card (Figures 1, 2)
• 56-bump WLP version, containing two SD host ports
and two SD cards. There are two SD hosts and two
SD memory cards. Use this mode if the host has two
SD ports (Figure 3).
1110 000
ADDRESS = 0xE0
REGISTER 0x01 WRITE DATA
S
D7 D6 D5 D4 D2 D1D3
0 = WRITE
0000 0010
REGISTER ADDRESS = 0x01
0A A
PD0 A/A
S = START BIT
P = STOP BIT
A = ACK
A = NACK
D_ = DATA BIT
Figure 17. Format for I
2
C Write. In this example the register 0x01 is written.
1110 000
ADDRESS = 0xE0
REGISTER 0x01 WRITE DATA
S
D7 D6 D5 D4 D2 D1D3
0 = WRITE
0000 0010
REGISTER ADDRESS = 0x01
0A A
D0 A
REGISTER 0x02 WRITE DATA
D7 D6 D5 D4 D2 D1D3 PD0 A/A
Figure 18. Format for Writing to Multiple Registers. In this example, registers 0x01 and 0x02 are written in sequence.
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
30 ______________________________________________________________________________________
• 56-bump WLP version, containing one port and two
SD cards. The host SD ports 1 and 2 are connected
together at the host. This configuration allows two
SD cards connected to one host, but only one SD
card is connected to the host at a time. The host
uses the MAX14500–MAX14503’s internal SD port
switches to multiplex between the cards. This con-
figuration can also be used to limit the bus capaci-
tive loading of having two cards connected at the
same time to the bus (Figure 4).
SD Card Clock Frequency
The SD card clock frequency is the lower of the maxi-
mum the card can support as read from the SD card
and base SD clock (base SD clock is determined from
values shown in Table 5). The MAX14500–MAX14503
internally read the max frequency directly from the SD
card. In I2C control, the maximum clock frequency is
programmable to values lower than the maximum
allowed by the SD card, helping with issues such as
excessive bus capacitance causing data errors.
1110 000
ADDRESS = 0xE0
S
0 = WRITE
0000 0010
REGISTER ADDRESS = 0x01
0
1110 000
ADDRESS = 0xE1
S
1 = READ
1
A
A
REGISTER 0x01 READ DATA
D7 D6 D5 D4 D2 D1D3 PD0 A/A
PA
Figure 19. Format for Reading
1110 000
ADDRESS = 0xE0
S
0 = WRITE
0000 0000
REGISTER ADDRESS = 0x00
0
1111 000
ADDRESS = 0xE1
S
1 = READ
1
A
A
REGISTER 0x00 READ DATA
D7 D6 D5 D4 D2 D1D3 D0 A
REGISTER 0x02 READ DATA
D7 D6 D5 D4 D2 D1D3 D0 A
REGISTER 0x01 READ DATA
D7 D6 D5 D4 D2 D1D3 D0 A
P
REGISTER 0x03 READ DATA
D7 D6 D5 D4 D2 D1D3 D0 A P
A
Figure 20. Format for Reading Multiple Registers
INPUT FREQUENCY (MHz) BASE SD CLOCK (MHz)
12 48
13 52
19.2 48
26 52
Table 5. Maximum SD Card Clock Frequency
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 31
SD Port Switches
The SD port analog switches change states immediately
whether the MAX14500–MAX14503 are in Sleep mode
(WAKEUP = 0) or awake. If the internal USB Hi-Speed
SD card reader is in operation, the SD card switches for
the selected path are opened automatically. Any writes
to the SD port switch bits for that path are ignored. The
SD port analog switches for the path not being used for
the card reader are controllable by the host µP, and any
writes to these bits affect state changes immediately.
Card Detection
The MAX14500–MAX14503 provide an analog switch to
pass the card present signal on SD card slot 1. This
allows the host µP to continue using the SD slot card
present switch (see Figure 21). The internal analog
switch can be bypassed if an alternate algorithm is
used to detect card data change. The second SD card
path does not provide this analog switch so if this path
is used for another SD card socket, an alternate card-
detection mechanism for the host µP may be needed. If
the second SD card path is used for an SD interface
NAND chip, no card detection is required.
The MAX14500–MAX14503 do not use the SD card slot
switch to detect insertion and removals. Instead, a pro-
tocol-based detection mechanism is used that polls for
the presence or absence of an SD card. This allows
both path 1 and path 2 to support an SD card slot with
removable SD cards without a connection between
the MAX14500–MAX14503 and the SD socket card pre-
sent switch. The pullup voltage for the card slot detec-
tion may be any voltage equal to or less than VSD.
Enumeration
The MAX14500–MAX14503 enumerate to the USB
mass storage class and appear as a USB mass stor-
age device on most operating systems.
USB Hi-Speed vs. Full-Speed
The MAX14500–MAX14503 support USB Hi-Speed and
full-speed operation. The MAX14500–MAX14503 operate
at 480Mbps when plugged into a Hi-Speed USB host,
and at 12Mbps when plugged into a full-speed host.
USB VID/PID
Using I2C, the MAX14500–MAX14503 have dedicated
I2C registers for vendor identification (VID) and product
identification (PID). The programmed 16-bit default val-
ues are shown in the
Register Map
section. The factory
default values can be replaced with your company’s VID
and PID.
CCRD_PRST
MECHANICAL CARD
DETECT SWITCH
MAX14500–MAX14503 SD
PORT1 SWITCH
CCMD1
CCLK1
HCRD_PRST
≤ VSD
HCMD1
HCLK1
CDAT1_[3:0] HDAT1_[3:0]
HOST SD PORT
CARD PRESENT INPUT
SD CARD
≤ VSD
MECHANICAL CARD
DETECT SWITCH
MAX14500–MAX14503 SD
PORT2 SWITCH
CCMD2
CCLK2
HCMD2
HCLK2
CDAT2_[3:0] HDAT2_[3:0]
HOST SD PORT
CARD PRESENT INPUT
SD CARD
Figure 21. Host Card Detection Schemes
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
32 ______________________________________________________________________________________
Power-Supply Modes
The MAX14500–MAX14503 have four power-supply
inputs (Table 6). Bypass VCC, VIO, VSD, and VTM with
high-frequency, surface-mount ceramic capacitors as
close as possible to the supply pins.
Power-supply inputs:
1) VTM USB Transceiver Power. This supply powers the
USB analog switches, PLL subsystem, and the USB
2.0 transceiver. This regulator can be internal to a
power-management IC, or it can be discrete and is
recommended to be powered from USB VBUS. This
supply must be present when the MAX14500–
MAX14503 are used in Card Reader mode to pass
USB signals in Pass Thru mode.
2) VCC Digital Logic Power. This supply powers the
digital logic/internal microcontroller/flash memory.
There is an internal +1.8V LDO (CLDO) with shut-
down controlled by the state of the MODE input and
internal logic.
3) VSD SD Card Power. This supply powers the SD
card level translator and SD card switches. VSD
needs to be present to pass SD signals in Pass Thru
mode.
4) VIO Host Interface Power. This supply powers the
digital I/O and I2C interface.
Power modes:
1) Idle. Only VIO is required to be present. I2C registers
can be updated, but no operation is possible.
2) Pass Thru Mode. VIO needs to be present so the
voltage level at MODE can be detected. To allow
USB pass thru, the VTM supply needs to be present.
To allow SD pass thru, VSD supply needs to be pre-
sent. Each supply is independent from the others
and no power-supply sequencing is required.
3) Card Reader Mode. All supplies are needed. When
the card reader is actively transferring data, this mode
draws the most current, mainly from VCC and VTM.
Layout Considerations
The MAX14500–MAX14503 support Hi-Speed USB and
requires careful PCB layout. Use controlled-impedance
matched traces of equal lengths to the USB connector
with no discontinuities and a minimum number of
feedthroughs. All SD traces (CLK, CMD, DAT_) should
be of equal lengths and as short as possible.
Choosing Pullup Resistors
I2C requires pullup resistors to provide a logic-high level
to data and clock lines. There are tradeoffs between
power dissipation and speed, and a compromise must
be made in choosing pullup resistor values. Every
device connected to the bus introduces some capaci-
tance, even when the device is not in operation. I2C
specifies 300ns rise time to go from low to high (30% to
70%) for fast mode, which is defined for data rates up to
400kbps. To meet the rise time requirement, choose
pullup resistors so the rise time (tR) is less than 300ns
where tR≈0.85 x RPULLUP x CBUS. If the transition time
becomes too slow, the setup and hold times may not be
met and waveforms may not be recognized.
SUPPLY FUNCTION RANGE (V)
VTM USB transceiver and USB
switch power +2.91 to +3.4
VCC Digital core 1.8V LDO +2.1 to +3.6
VSD SD card level translator and SD
switches +2.0 to +3.6
VIO Host microprocessor level
translator +1.5 to +3.6
Table 6. Power-Supply Inputs
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 33
FIELD NAME READ
WRITE BITS RESET DESCRIPTION VALID
WHEN
CONTROL: Control Register (0x00)
RFU R/W [7:5] 000 Reserved for future use —
SD2SW R/W 4 1
Setting of SD port 2 switches:
0 = open
1 = closed
Powered
SD1SW R/W 3 1
Setting of SD port 1 switches:
0 = open
1 = closed
Powered
MODE R/W [2:1] 00
Activates PC USB Hi-Speed SD card reader:
00 = not active
01 = card reader active for SD port 1
10 = card reader active for SD port 2
11 = not active
WAKEUP = 1
WAKEUP R/W 0 0
Wakes the internal µC:
0 = requests µC to shut down
1 = wakes µC
Powered
CONFIG1: Configuration Register 1 (0x01)
SD2ONEBIT R/W 7 0
Force the SD port 2 bus to 1 bit mode:
0 = SD bus 4-bit data mode
1 = SD bus 1-bit data mode
Enter Card
Reader mode
SD1ONEBIT R/W 6 0
Force the SD port 1 bus to 1 bit mode:
0 = SD bus 4-bit data mode
1 = SD bus 1-bit data mode
Enter Card
Reader mode
INTPULSE R/W 5 0
INT assertion method:
0 = INT stays asserted until STATUS register is read
1 = INT asserts for 10ms pulse
WAKEUP = 1
INTACTHI R/W 4 0
INT pin active level:
0 = active-low
1 = active-high
WAKEUP = 1
RFU R/W [3:0] 0000 Reserved for future use —
CONFIG2: Configuration Register 2 (0x02)
RFU R/W 7 0 Reserved for future use —
CLKSOURCE R/W [6:2] 00000
S ets the confi g ur ati on for the cl ock i np ut:
00000 = d efaul t
00001 = 19.2M H z r ai l - to- r ai l sq uar e w ave
00010 = 19.2M H z l ow - am p l i tud e AC - coup l ed si ne w ave
00101 = 13M H z r ai l - to- r ai l sq uar e w ave
00110 = 13M H z l ow - am p l i tud e AC - coup l ed si ne w ave
01001 = 12M H z r ai l - to- r ai l sq uar e w ave
01010 = 12M H
z l ow - am p l i tud e AC - coup l ed si ne w ave
01101 = 26M H z r ai l - to- r ai l sq uar e w ave
01110 = 26M H z l ow - am p l i tud e AC - coup l ed si ne w ave
Al l other val ues = d efaul t
Enter Card
Reader mode
Register Map
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
34 ______________________________________________________________________________________
Register Map (continued)
FIELD NAME READ
WRITE
BITS
RESET
DESCRIPTION VALID
WHEN
FORCEFS R/W 1 0
Sets the maximum USB speed:
0 = Hi-Speed
1 = full speed
Enter Card
Reader mode
RFU R/W 0 0 Reserved for future use —
CONFIG3: Configuration Register 3 (0x03)
SD2MAXCLK R/W [7:4] 0000
Limits the max clock for SD card 2. The SD clock will
be the minimum of either this register or the SD card
max speed register.
0111 = base SD clock/64
0110 = base SD clock/32
0101 = base SD clock/16
0100 = base SD clock/8
0011 = base SD clock/4
0010 = base SD clock/2
0001 = base SD clock
0000 = default (base SD clock)
Enter Card
Reader mode
SD1MAXCLK R/W [3:0] 0000
Limits the max clock for SD card 1. The SD clock will
be the minimum of either this register or the SD card
max speed register.
0111 = base SD clock/64
0110 = base SD clock/32
0101 = base SD clock/16
0100 = base SD clock/8
0011 = base SD clock/4
0010 = base SD clock/2
0001 = base SD clock
0000 = default (base SD clock)
Enter Card
Reader mode
IE1: Interrupt Enable Register 1 (0x04)
RFU R/W 7 0 Reserved for future use —
USBFS R/W 6 0
Full-speed status change:
0 = disable contribution to INT
1 = enable contribution to INT
Powered
USBSR R/W 5 0
USB suspend-resume status change:
0 = disable contribution to INT
1 = enable contribution to INT
Powered
VTM R/W 4 0
VTM voltage-detector change:
0 = disable contribution to INT
1 = enable contribution to INT
Powered
VSD R/W 3 0
VSD voltage-detector change:
0 = disable contribution to INT
1 = enable contribution to INT
Powered
KVBUS R/W 2 0
VBUS voltage-detector change:
0 = disable contribution to INT
1 = enable contribution to INT
Powered
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 35
FIELD NAME READ
WRITE BITS RESET DESCRIPTION VALID
WHEN
BUSY R/W 1 0
BUSY state change:
0 = disable contribution to INT
1 = enable contribution to INT
Powered
SDSTAT R/W 0 0
SD card status change:
0 = disable contribution to INT
1 = enable contribution to INT
Note: Reflects currently selected card in Card Reader
mode
Powered
IE2: Interrupt Enable Register 2 (0x05)
FWUPD R/W 7 0
Firmware update status change:
0 = disable contribution to INT
1 = enable contribution to INT
Powered
RFU R/W [6:0] 0000000 Reserved for future use —
USBVIDH: USB Vendor ID High Byte (0x06)
VID 1 R/W [7:0] 0x00
Bits 15–8 of USB vendor ID reported during card
reader enumeration. If this register is written, the written
value is used for USB enumeration, otherwise a default
VID of 0x06BA (Maxim Integrated Products) is used.
Enter Card
Reader mode
USBVIDL: USB Vendor ID Low Byte (0x07)
VID 2 R/W [7:0] 0x00
Bits 7–0 of USB vendor ID reported during card reader
enumeration. If this register is written, the written value
is used for USB enumeration, otherwise a default VID of
0x06BA (Maxim Integrated Products) is used.
Enter Card
Reader mode
USBPIDH: USB Product ID High Byte (0x08)
PID 1 R/W [7:0] 0x00
Bits 15–8 of USB product ID reported during card
reader enumeration. If this register is written, the written
value is used for USB enumeration, otherwise a default
PID of 0x38A4 is used.
Enter Card
Reader mode
USBPIDL: USB Product ID Low Byte (0x09)
PID 2 R/W [7:0] 0x00
Bits 7–0 of USB product ID reported during card reader
enumeration. If this register is written, the written value
is used for USB enumeration, otherwise if zero, a
default PID of 0x38A4 is used.
Enter Card
Reader mode
Test Register (0x0A)
Test Register R/W — 0x00 Do not write to this register —
Test Register (0x0B)
Test Register R/W — 0x00 Do not write to this register —
Test Register (0x0C)
Test Register R/W — 0x00 Do not write to this register —
Test Register (0x0D)
Test Register R/W — 0x00 Do not write to this register —
Register Map (continued)
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
36 ______________________________________________________________________________________
Register Map (continued)
FIELD NAME READ
WRITE
BITS
RESET
DESCRIPTION VALID
WHEN
Test Register (0x0E)
Test Register R/W — 0x00 Do not write to this register —
FWP: Firmware Portal (0x0F)
Firmware Portal R/W [7:0] 0x00 Contact factory. Do not write to this register. —
IRQ1: Interrupt Request Register 1 (0x10)
RFU R 7 Reserved for future use —
USBFS R 6 0 = no change in USB full-speed mode status
1 = change in USB full-speed mode status
Enter Card
Reader mode
USBSR R 5 0 = no change in USB suspend/resume status
1 = change in USB suspend/resume status
Enter Card
Reader mode
VTM R 4 0 = no change in VTM detector status
1 = change in VTM detector status
WAKEUP = 1
VSD R 3 0 = no change in VSD detector status
1 = change in VSD detector status
WAKEUP = 1
VBUS R 2 0 = no change in VBUS detector status
1 = change in VBUS detector status
WAKEUP = 1
BSY R 1 0 = no change in BUSY status
1 = change in BUSY status
WAKEUP = 1
SDSTAT R 0 0 = no change in SD card present status
1 = change in SD card present status
Enter Card
Reader mode
IRQ2: Interrupt Request Register 2 (0x11)
Firmware Update R 7 Contact factory Code
download
RFU R [6:0] Reserved for future use —
STATUS1: Status Register 1 (0x12)
RFU R 7 Reserved for future use —
USBFS R 6 0 = no connection or Hi-Speed connection
1 = full-speed connection
Enter Card
Reader mode
USBSR R 5 0 = USB resume
1 = USB suspend
Enter Card
Reader mode
VTM R 4 0 = no voltage
1 = VTM supply present
WAKEUP = 1
VSD R 3 0 = no voltage
1 = VSD supply present
WAKEUP = 1
VBUS R 2 0 = no voltage
1 = VBUS supply present
WAKEUP = 1
BSY R 1 0 = not busy
1 = busy
WAKEUP = 1
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 37
Register Map (continued)
FIELD NAME READ
WRITE
BITS
RESET
DESCRIPTION VALID
WHEN
SDSTAT R 0
The insert/removal status is only valid for the card
currently set to Card Reader mode (Reg 0x00 bits 1-2)
0 = no card
1 = card present
Enter Card
Reader mode
STATUS2: Status Register 2 (0x13)
RFU R [7:0] Reserved for future use —
FWUGRRH: Firmware Upgrade Response Data High Byte (0x14)
High Byte of Response
Data R [7:0] Contact factory Code
download
FWUPGRL: Firmware Upgrade Response Data Low Byte (0x15)
Low Byte of Response
Data R [7:0] Contact factory Code
download
RFU Register (0x16)
RFU R [7:0] Reserved for future use —
RFU Register (0x17)
RFU R [7:0] Reserved for future use —
RFU Register (0x18)
RFU R [7:0] Reserved for future use —
RFU Register (0x19)
RFU R [7:0] Reserved for future use —
RFU Register (0x1A)
RFU R [7:0] Reserved for future use —
Firmware Incremental Revision (0x1B)
Firmware Incremental
Revision R [7:0] Firmware incremental revision
WAKEUP = 1
Firmware Minor Revision (0x1C)
Firmware Minor Revision
R [7:0] Firmware minor revision
WAKEUP = 1
Firmware Major Revision (0x1D)
Firmware Major Revision
R [7:0] Firmware major revision
WAKEUP = 1
Chip Revision (0x1E)
Chip Revision R [7:0] Chip revision
WAKEUP = 1
Package Type (0x1F)
Package Type R [7:0]
0x00 = 40-lead TQFN
0x05 = 56-bump WLP
0xFF = unknown
WAKEUP = 1
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
38 ______________________________________________________________________________________
CCLK2
VSD VIO
CCMD2
CDAT 2_0
HCLK2
HCMD2
HDAT 2_0
CDAT 2_1
CDAT 2_2
CDAT 2_3
CLK
CMD
DAT 0
DAT 1
DAT 2
DAT 3
HDAT 2_1
HDAT 2_2
HDAT 2_3
CLK
CMD
DAT 0
DAT 1
DAT 2
DAT 3
SD PORT2
SD INTERFACE
NAND FLASH
CD+
SD PORT 2 SWITCHES
HOST PROCESSOR
USB SWITCHES
CD-
D+
D-
VBUS
HD+
HD-
D+
D-
USB
CONNECTOR
SD CARD INTERFACE LEVEL TRANSLATORS
1.8V
LDO
VBUS
DET
MICROCONTROLLER
FLASH
PLL
48/52MHz SQR TCXO
SRAM
USB SIE
OSC
ROM
I/O LEVEL TRANSLATORS
HOST INTERFACE
USB 2.0
TRANSCEIVER
CCRD_PRST
CCLK 1
CCMD 1
HCRD_PRST
HCLK1
HCMD1
CDAT 1_0
CDAT 1_1
CDAT 1_2
SD_DETECT
CLK
CMD
DAT 0
DAT 1
DAT 2
HDAT 1_0
HDAT 1_1
HDAT 1_2
SD_DETECT
CLK
CMD
DAT 0
DAT 1
DAT 2
SD PORT1
SD SLOT
SD CARD
SD PORT 1 SWITCHES
CDAT 1_3
CLDO
VCC
DAT 3 HDAT 1_3
MODE
BUSY
BERR/INT
USB
SCL
SDA
RST
ADD
I2C_SEL
FREF
DAT 3
1μF
0.1μF
VSD
VCC
VTM
(+2.91V TO +3.4V)
VIO
VIO
MAX14500–MAX14503
KVBUS
RREF
1μF
0.1μF
1μF
6.19kΩ
1%
1.5kΩ
VTM
Functional Diagram
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
______________________________________________________________________________________ 39
HCRD_PRST
HCLK1
RREF
GND
VTM
CD+
CD-
FREF
GND
KVBUS
SDA
ADD
VIO
BUSY
MODE
RST
CDAT1_3
SCL
I2C_SEL
HDAT1_2
HDAT1_1
HDAT1_0
HD-
HD+
HDAT1_3
CDAT1_0
CDAT1_1
CDAT1_2
VCC
CLDO
GND
N.C.
N.C.
CCMD1
CCRD_PRST
CCLK1
HCMD1
VSD
TQFN
MAX14500
MAX14501
MAX14502
MAX14503
TOP VIEW
BERR/INT
GND
1 2 3 4 5 6 7 8 9 10
40
39
38
37
36
35
34
33
32
31
11
*EP
12
13
14
15
16
17
18
19
20
30 29 28 27 26 25 24 23 22 21
+
*CONNECT EXPOSED PAD TO GND.
Pin Configurations
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
40 ______________________________________________________________________________________
TOP VIEW
(BUMPS ON BOTTOM)
MAX14500–MAX14503
CDAT1_3 VIO
CDAT1_1
876
HDAT1_0
CDAT1_0 CDAT1_2 MODE
HDAT1_2
HDAT1_1
CD-
GND GND FREF
VTM
GND
HD-
HD+ CD+
SDA
CDAT2_3 HDAT2_3 ADD
VCC
CDAT2_2
543
N.C.
N.C.
HDAT2_2 I2C_SEL VCC
HDAT2_0
HDAT1_3
CCMD2
KVBUS CCLK1
CCLK2
HCLK2
RREF
GND HCMD2
SCL VSD
CLDOCLDO
21
GND GND
CDAT2_1CDAT2_0
CCMD1 HDAT2_1
CCRD_PRSTHCRD_PRST
HCLK1 HCMD1
A
B
C
D
E
F
G
WLP
BUSY
RST BERR/INT
Pin Configurations (continued)
Chip Information
PROCESS: CMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
40 TQFN-EP T4055-1 21-0140
56 WLP W563B3+1 21-0090
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
41
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 4/08 Initial release —
1 4/09
Fixed data sheet to reflect new rev material including EC table,Pin Description,
Applications Information,Functional Diagram, and Pin Configurations 1–41
