Kinetis K02 64 KB/128 KB Flash
100 MHz ARM® Cortex®-M4 Based Microcontroller with FPU
Ideal for low-power applications that require processing
efficiency and high peripheral integration. These devices share
the comprehensive enablement and scalability of the Kinetis
family.
This product offers:
• Run power consumption down to 117.5 µA/MHz and static
power consumption down to 2.8 µA with full state retention
and 5.7 µs wakeup. Lowest static mode down to 70 nA.
• Excellent processing efficiency, 100 MHz ARM® Cortex®-
M4-based device with floating-point unit in a tiny form factor
Performance
• 100 MHz ARM Cortex-M4 core with DSP instructions
delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
• Up to 128 KB of embedded flash and 16 KB of RAM
• Preprogrammed Kinetis flashloader for one-time, in-
system factory programming
System peripherals
• Flexible low-power modes, multiple wake up sources
• 4-channel DMA controller
• Independent External and Software Watchdog monitor
Clocks
• Crystal oscillator: 32-40 kHz or 3-32 MHz
• Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz
• Multi-purpose clock generator with FLL
Security and integrity modules
• Hardware CRC module
• 128-bit unique identification (ID) number per chip
• Flash access control to protect proprietary software
Human-machine interface
• Up to 46 general-purpose I/O (GPIO)
Analog modules
• One 16-bit SAR ADC (1.2 MS/s in 12bit mode)
• One 12-bit DAC
• Two analog comparators (CMP) with 6- bit DAC
• Accurate internal voltage reference (not available in
32-pin QFN package)
Communication interfaces
• One SPI module
• Two UART modules
• One I2C: Support for up to 1 Mbps operation
Timers
• One 6-channel general-purpose/PWM timer
• Two 2-channel general-purpose timers with
quadrature decoder functionality (FTM2 does not
have external pins on the 32-pin QFN or the 48-pin
LQFP package)
• Periodic interrupt timers
• 16-bit low-power timer
• Programmable delay block
Operating Characteristics
• Voltage range (including flash writes): 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
MK02FN128VLH10
MK02FN128VLF10
MK02FN128VFM10
MK02FN64VLH10
MK02FN64VLF10
MK02FN64VFM10
64 LQFP (LH)
10 x 10 x 1.4 Pitch 0.5
mm
48 LQFP (LF)
7 x 7 x 1.4 Pitch 0.5
mm
32 QFN (FM)
5 x 5 x 1 Pitch 0.5 mm
NXP Semiconductors K02P64M100SFA
Data Sheet: Technical Data Rev. 4, 08/2016
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information
Part Number Memory Number of GPIOs
Flash (KB) SRAM (KB)
MK02FN128VLH10 128 16 46
MK02FN128VLF10 128 16 35
MK02FN128VFM10 128 16 26
MK02FN64VLH10 64 16 46
MK02FN64VLF10 64 16 35
MK02FN64VFM10 64 16 26
Device Revision Number
Device Mask Set Number SIM_SDID[REVID] JTAG ID Register[PRN]
0N36M 0000 0000
Related Resources
Type Description Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
KINETISKMCUSELGD
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K02P64M100SFARM
Data Sheet The Data Sheet includes electrical characteristics and signal
connections.
This document.
Chip Errata The chip mask set Errata provides additional or corrective information for
a particular device mask set.
Kinetis_K_0N36M
Package
drawing
Package dimensions are provided by the part number:
• MK02FN64VFM10
• MK02FN128VFM10
• MK02FN64VLF10
• MK02FN128VLF10
• MK02FN64VLH10
• MK02FN128VLH10
•98ARE10566D
•98ARE10566D
•98ASH00962A
•98ASH00962A
•98ASS23234W
•98ASS23234W
Figure 1 shows the functional modules in the chip.
2Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
NXP Semiconductors
Memories and Memory Interfaces
Program
(Up to 128 KB)
RAM
CRC
Programmable
Analog Timers Communication InterfacesSecurity
and Integrity
Clocks
Frequency-
Core
Debug
interfaces DSP
Interrupt
controller
Comparator
x2
16-bit
timer
Human-Machine
Interface (HMI)
Up to
System
DMA (4 ch)
Low-leakage
wakeup
locked loop
reference
Internal
clocks
delay block
timers
interrupt
Periodic
oscillators
Low/high
frequency
UART
x2
®
Cortex™-M4ARM
FPU
voltage ref
x1
IC
2
Timers
x1 (6ch)
SAR ADC x1
SPI
x1
High
performance
Flash access
control
low-power
46 GPIOs
(16 KB)
flash
Internal
watchdogs
and external
with 6-bit DAC
12-bit DAC
x1
x2 (2ch)
16-bit
Figure 1. Functional block diagram
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 3
NXP Semiconductors
Table of Contents
1 Ratings....................................................................................5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 6
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors.....16
2.2.7 Designing with radiated emissions in mind..........17
2.2.8 Capacitance attributes.........................................17
2.3 Switching specifications...................................................17
2.3.1 Device clock specifications..................................17
2.3.2 General switching specifications......................... 18
2.4 Thermal specifications.....................................................18
2.4.1 Thermal operating requirements......................... 18
2.4.2 Thermal attributes................................................19
3 Peripheral operating requirements and behaviors.................. 20
3.1 Core modules.................................................................. 20
3.1.1 SWD electricals .................................................. 20
3.1.2 JTAG electricals.................................................. 21
3.2 System modules.............................................................. 24
3.3 Clock modules................................................................. 24
3.3.1 MCG specifications..............................................24
3.3.2 IRC48M specifications.........................................26
3.3.3 Oscillator electrical specifications........................26
3.4 Memories and memory interfaces................................... 29
3.4.1 Flash electrical specifications..............................29
3.5 Security and integrity modules........................................ 30
3.6 Analog............................................................................. 30
3.6.1 ADC electrical specifications............................... 30
3.6.2 CMP and 6-bit DAC electrical specifications....... 34
3.6.3 12-bit DAC electrical characteristics....................37
3.6.4 Voltage reference electrical specifications.......... 40
3.7 Timers..............................................................................41
3.8 Communication interfaces............................................... 41
3.8.1 DSPI switching specifications (limited voltage
range).................................................................. 42
3.8.2 DSPI switching specifications (full voltage
range).................................................................. 43
3.8.3 Inter-Integrated Circuit Interface (I2C) timing...... 45
3.8.4 UART switching specifications............................ 47
4 Dimensions............................................................................. 47
4.1 Obtaining package dimensions....................................... 47
5 Pinout......................................................................................47
5.1 K02F Signal Multiplexing and Pin Assignments.............. 47
5.2 Recommended connection for unused analog and
digital pins........................................................................50
5.3 K02F Pinouts................................................................... 51
6 Part identification.....................................................................54
6.1 Description.......................................................................54
6.2 Format............................................................................. 54
6.3 Fields............................................................................... 55
6.4 Example...........................................................................55
6.5 48-pin LQFP part marking............................................... 56
6.6 32-pin QFN part marking................................................. 56
7 Terminology and guidelines.................................................... 56
7.1 Definitions........................................................................56
7.2 Examples.........................................................................57
7.3 Typical-value conditions.................................................. 57
7.4 Relationship between ratings and operating
requirements....................................................................58
7.5 Guidelines for ratings and operating requirements..........58
8 Revision History...................................................................... 58
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NXP Semiconductors
1 Ratings
1.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
-500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Ratings
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 5
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Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current — 145 mA
VDIO Digital input voltage –0.3 VDD + 0.3 V
VAIO Analog1–0.3 VDD + 0.3 V
IDMaximum current single pin limit (applies to all digital pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
Table continues on the next page...
General
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Table 1. Voltage and current operating requirements (continued)
Symbol Description Min. Max. Unit Notes
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VIH Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
VIL Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD — V
IICIO Analog and I/O pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection) -3 — mA
1
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection -25 — mA
VODPU Open drain pullup voltage level VDD VDD V2
VRAM VDD voltage required to retain RAM 1.2 — V
1. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or
greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VIO_MIN-VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
Table continues on the next page...
General
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Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— 80 — mV
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— 60 — mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
VOH Output high voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA VDD – 0.5 — — V 1
1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA VDD – 0.5 — — V
VOH Output high voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA VDD – 0.5 — — V 1
1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA VDD – 0.5 — — V
IOHT Output high current total for all ports — — 100 mA
VOL Output low voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — — 0.5 V 1
1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA — — 0.5 V
VOL Output low voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA — — 0.5 V 1
1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA — — 0.5 V
VOL Output low voltage — RESET_B
Table continues on the next page...
General
8Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
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Table 3. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA — — 0.5 V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA — — 0.5 V
IOLT Output low current total for all ports — — 100 mA
IIN Input leakage current (per pin) for full
temperature range
All pins other than high drive port pins — 0.002 0.5 μA 1, 2
High drive port pins — 0.004 0.5 μA
IIN Input leakage current (total all pins) for full
temperature range
— — 1.0 μA 2
RPU Internal pullup resistors 20 — 50 kΩ 3
RPD Internal pulldown resistors 20 — 50 kΩ 4
1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability
selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD=3.6V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
4. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 72 MHz
• Bus clock = 36 MHz
• Flash clock = 24 MHz
• MCG mode: FEI
Table 4. Power mode transition operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
tPOR After a POR event, amount of time from the
point VDD reaches 1.71 V to execution of the
first instruction across the operating
temperature range of the chip.
— — 300 μs 1
• VLLS0 → RUN
—
—
135
μs
• VLLS1 → RUN
—
—
135
μs
• VLLS2 → RUN
—
—
75
μs
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General
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Table 4. Power mode transition operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• VLLS3 → RUN
—
—
75
μs
• VLPS → RUN
—
—
5.7
μs
• STOP → RUN
—
—
5.7
μs
1. Normal boot (FTFA_OPT[LPBOOT]=1)
2.2.5 Power consumption operating behaviors
The current parameters in the table below are derived from code executing a while(1)
loop from flash, unless otherwise noted.
The IDD typical values represent the statistical mean at 25°C, and the IDD maximum
values for RUN, WAIT, VLPR, and VLPW represent data collected at 125°C junction
temperature unless otherwise noted. The maximum values represent characterized
results equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 5. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current — — See note mA 1
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, CoreMark benchmark code
executing from flash
@ 1.8V — 18.70 19.37 mA 2, 3, 4
@ 3.0V — 18.71 19.38 mA
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, code executing from flash
@ 1.8V — 18.13 18.80 mA 4
@ 3.0V — 18.19 18.86 mA
IDD_HSRUN High Speed Run mode current — all peripheral
clocks enabled, code executing from flash
@ 1.8V — 22.2 22.87 mA 5
@ 3.0V — 22.4 23.07 mA
IDD_RUN Run mode current in Compute operation —
CoreMark benchmark code executing from flash
@ 1.8V — 12.74 13.41 mA 2, 3, 6
@ 3.0V — 12.82 13.49 mA
Table continues on the next page...
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10 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
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Table 5. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_RUN Run mode current in Compute operation —
code executing from flash
@ 1.8V — 12.10 13.10 mA 6
@ 3.0V — 12.20 13.37 mA
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
@ 1.8V — 12.8 13.47 mA 7
@ 3.0V — 12.9 13.57 mA
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V — 14.8 15.47 mA 8
@ 3.0V
• @ 25°C — 14.9 15.57 mA
• @ 70°C — 14.9 15.57 mA
• @ 85°C — 14.9 15.57 mA
• @ 105°C — 15.5 16.20 mA
IDD_RUN Run mode current — Compute operation, code
executing from flash
@ 1.8V — 12.1 12.77 mA 9
@ 3.0V
• @ 25°C — 12.2 12.87 mA
• @ 70°C — 12.2 12.87 mA
• @ 85°C — 12.2 12.87 mA
• @ 105°C — 12.7 13.37 mA
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
— 5.5 6.17 mA 7
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
— 3.5 4.17 mA 10
IDD_VLPR Very-low-power run mode current in Compute
operation — CoreMark benchmark code
executing from flash
@ 1.8V — 0.58 0.86 mA 2, 11, 3
@ 3.0V — 0.59 0.87 mA
IDD_VLPR Very-low-power run mode current in Compute
operation, code executing from flash
@ 1.8V — 0.47 0.75 mA 11
@ 3.0V — 0.47 0.75 mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
— 0.62 0.90 mA 12
Table continues on the next page...
General
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Table 5. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
— 0.76 1.04 mA 13
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
— 0.28 0.56 mA 14
IDD_STOP Stop mode current at 3.0 V
@ -40°C to 25°C — 0.26 0.33 mA
@ 70°C — 0.30 0.47 mA
@ 85°C — 0.35 0.52 mA
@ 105°C — 0.43 0.60 mA
IDD_VLPS Very-low-power stop mode current at 3.0 V
@ -40°C to 25°C — 2.80 8.30 µA
@ 70°C — 13.30 29.90 µA
@ 85°C — 26.90 46.45 µA
@ 105°C — 56.80 67.05 µA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
@ -40°C to 25°C — 1.3 1.71 µA
@ 70°C — 3.8 5.35 µA
@ 85°C — 7.6 8.50 µA
@ 105°C — 15.1 19.05 µA
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ -40°C to 25°C — 1.3 1.55 µA
@ 70°C — 3.1 4.05 µA
@ 85°C — 7.2 8.60 µA
@ 105°C — 12.0 14.10 µA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ -40°C to 25°C — 0.63 0.87 µA
@ 70°C — 1.70 2.35 µA
@ 85°C — 2.8 3.40 µA
@ 105°C — 7.6 8.80 µA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
@ -40°C to 25°C — 0.35 0.46 µA
@ 70°C — 1.38 1.94 µA
@ 85°C — 2.4 2.95 µA
@ 105°C — 7.3 8.45 µA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
@ -40°C to 25°C — 0.07 0.16 µA
@ 70°C — 1.05 1.78 µA
@ 85°C — 2.1 2.80 µA
Table continues on the next page...
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12 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
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Table 5. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
@ 105°C — 6.9 8.25 µA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. Cache on and prefetch on, low compiler optimization
3. CoreMark benchmark compiled using IAR 7.2 with optimization level low
4. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled.
5. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled.
6. 72 MHz core and system clock, 36 MHz bus clock and 24 MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled. Compute operation.
7. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEI mode. All
peripheral clocks disabled.
8. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled.
9. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. Compute
operation.
10. 25 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode.
11. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. Compute operation.
Code executing from flash.
12. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
13. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled, but peripherals are not in active operation. Code executing from flash.
14. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
Table 6. Low power mode peripheral adders—typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56 56 56 56 56 56 µA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52 52 52 52 52 52 µA
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206 228 237 245 251 258 uA
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
VLLS1
VLLS3
LLS
440
440
490
490
490
490
540
540
540
560
560
560
570
570
570
580
580
680
nA
Table continues on the next page...
General
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Table 6. Low power mode peripheral adders—typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
VLPS
STOP
510
510
560
560
560
560
560
560
610
610
680
680
I48MIRC 48 Mhz internal reference clock 350 350 350 350 350 350 µA
ICMP CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and
a single external input for compare.
Includes 6-bit DAC power
consumption.
22 22 22 22 22 22 µA
IUART UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
MCGIRCLK (4 MHz internal reference
clock)
>OSCERCLK (4 MHz external crystal)
66
214
66
237
66
246
66
254
66
260
66
268
µA
IBG Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42 42 42 42 42 42 µA
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at
frequencies between 50 MHz and 100MHz.
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
General
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Figure 3. Run mode supply current vs. core frequency
General
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Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 64 LQFP package
Parame
ter
Conditions Clocks Frequency range Level
(Typ.)
Unit Notes
VEME Device configuration, test
conditions and EM
testing per standard IEC
61967-2.
Supply voltage: VDD =
3.3 V
Temp = 25°C
FSYS = 100 MHz
FBUS = 50 MHz
External crystal = 10 MHz
150 kHz–50 MHz 11 dBuV 1, 2, 3
50 MHz–150 MHz 12
150 MHz–500 MHz 11
500 MHz–1000 MHz 8
IEC level N 4
1. Measurements were made per IEC 61967-2 while the device was running typical application code.
2. Measurements were performed on a similar 64LQFP device.
3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
General
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4. IEC Level Maximums: N ≤ 12dBmV, M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV .
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
• Go to nxp.com
• Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins — 7 pF
CIN_D Input capacitance: digital pins — 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol Description Min. Max. Unit Notes
High Speed run mode
fSYS System and core clock — 100 MHz
fBUS Bus clock — 50 MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS System and core clock — 72 MHz
fBUS Bus clock — 50 MHz
fFLASH Flash clock — 25 MHz
fLPTMR LPTMR clock — 25 MHz
VLPR mode1
fSYS System and core clock — 4 MHz
fBUS Bus clock — 4 MHz
fFLASH Flash clock — 1 MHz
fERCLK External reference clock — 16 MHz
fLPTMR_pin LPTMR clock — 25 MHz
Table continues on the next page...
General
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NXP Semiconductors
Table 9. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
fLPTMR_ERCLK LPTMR external reference clock — 16 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 10. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100 — ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous
path
50 — ns 4
Port rise and fall time
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
10
5
30
16
ns
ns
ns
ns
5
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can
be recognized in that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
5. 25 pF load
2.4 Thermal specifications
General
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2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol Description Min. Max. Unit Notes
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C 1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
2.4.2 Thermal attributes
Board type Symbol Descriptio
n64 LQFP 48 LQFP 32 QFN Unit Notes
Single-layer
(1s)
RθJA Thermal
resistance,
junction to
ambient
(natural
convection)
66 79 97 °C/W 1
Four-layer
(2s2p)
RθJA Thermal
resistance,
junction to
ambient
(natural
convection)
48 55 33 °C/W 1
Single-layer
(1s)
RθJMA Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
54 67 81 °C/W 1
Four-layer
(2s2p)
RθJMA Thermal
resistance,
junction to
ambient (200
ft./min. air
speed)
41 49 28 °C/W 1
— RθJB Thermal
resistance,
junction to
board
30 33 13 °C/W 2
— RθJC Thermal
resistance,
junction to
case
17 23 2.0 °C/W 3
—ΨJT Thermal
characterizati
3 5 6 °C/W 4
General
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NXP Semiconductors
Board type Symbol Descriptio
n64 LQFP 48 LQFP 32 QFN Unit Notes
on
parameter,
junction to
package top
outside
center
(natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 12. SWD full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 SWD_CLK frequency of operation
• Serial wire debug
0
33
MHz
S2 SWD_CLK cycle period 1/S1 — ns
S3 SWD_CLK clock pulse width
• Serial wire debug
15
—
ns
S4 SWD_CLK rise and fall times — 3 ns
S9 SWD_DIO input data setup time to SWD_CLK rise 8 — ns
S10 SWD_DIO input data hold time after SWD_CLK rise 1.4 — ns
S11 SWD_CLK high to SWD_DIO data valid — 25 ns
S12 SWD_CLK high to SWD_DIO high-Z 5 — ns
Peripheral operating requirements and behaviors
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S2
S3 S3
S4 S4
SWD_CLK (input)
Figure 5. Serial wire clock input timing
S11
S12
S11
S9 S10
Input data valid
Output data valid
Output data valid
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
Figure 6. Serial wire data timing
3.1.2 JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 2.7 3.6 V
J1 TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
0
0
10
20
MHz
J2 TCLK cycle period 1/J1 — ns
J3 TCLK clock pulse width
50
—
ns
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 13. JTAG limited voltage range electricals (continued)
Symbol Description Min. Max. Unit
• Boundary Scan
• JTAG and CJTAG
25 — ns
J4 TCLK rise and fall times — 3 ns
J5 Boundary scan input data setup time to TCLK rise 20 — ns
J6 Boundary scan input data hold time after TCLK rise 1 — ns
J7 TCLK low to boundary scan output data valid — 25 ns
J8 TCLK low to boundary scan output high-Z — 25 ns
J9 TMS, TDI input data setup time to TCLK rise 8 — ns
J10 TMS, TDI input data hold time after TCLK rise 1 — ns
J11 TCLK low to TDO data valid — 19 ns
J12 TCLK low to TDO high-Z — 19 ns
J13 TRST assert time 100 — ns
J14 TRST setup time (negation) to TCLK high 8 — ns
Table 14. JTAG full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
0
0
10
15
MHz
J2 TCLK cycle period 1/J1 — ns
J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
50
33
—
—
ns
ns
J4 TCLK rise and fall times — 3 ns
J5 Boundary scan input data setup time to TCLK rise 20 — ns
J6 Boundary scan input data hold time after TCLK rise 1.4 — ns
J7 TCLK low to boundary scan output data valid — 27 ns
J8 TCLK low to boundary scan output high-Z — 27 ns
J9 TMS, TDI input data setup time to TCLK rise 8 — ns
J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns
J11 TCLK low to TDO data valid — 26.2 ns
J12 TCLK low to TDO high-Z — 26.2 ns
J13 TRST assert time 100 — ns
J14 TRST setup time (negation) to TCLK high 8 — ns
Peripheral operating requirements and behaviors
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J2
J3 J3
J4 J4
TCLK (input)
Figure 7. Test clock input timing
J7
J8
J7
J5 J6
Input data valid
Output data valid
Output data valid
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
Figure 8. Boundary scan (JTAG) timing
Peripheral operating requirements and behaviors
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J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
TCLK
TDI/TMS
TDO
TDO
TDO
Figure 9. Test Access Port timing
J14
J13
TCLK
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
Peripheral operating requirements and behaviors
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NXP Semiconductors
3.3.1 MCG specifications
Table 15. MCG specifications
Symbol Description Min. Typ. Max. Unit Notes
fints_ft Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
— 32.768 — kHz
Δfints_t Total deviation of internal reference frequency
(slow clock) over voltage and temperature
— +0.5/-0.7 ± 2 %
fints_t Internal reference frequency (slow clock) —
user trimmed
31.25 — 39.0625 kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
— ± 0.3 ± 0.6 %fdco 1
Δfdco_t Total deviation of trimmed average DCO output
frequency over voltage and temperature
— +0.5/-0.7 ± 2 %fdco 1, 2
Δfdco_t Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
— ± 0.3 ± 1.5 %fdco 1
fintf_ft Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
— 4 — MHz
Δfintf_ft Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
— +1/-2 ± 5 %fintf_ft
fintf_t Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3 — 5 MHz
floc_low Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
— — kHz
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
— — kHz
FLL
ffll_ref FLL reference frequency range 31.25 — 39.0625 kHz
fdco DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20 20.97 25 MHz 3, 4
Mid range (DRS=01)
1280 × ffll_ref
40 41.94 50 MHz
Mid-high range (DRS=10)
1920 × ffll_ref
60 62.91 75 MHz
High range (DRS=11)
2560 × ffll_ref
80 83.89 100 MHz
fdco_t_DMX3
2
DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
— 23.99 — MHz 5, 6
Mid range (DRS=01)
1464 × ffll_ref
— 47.97 — MHz
Mid-high range (DRS=10) — 71.99 — MHz
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 15. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
— 95.98 — MHz
Jcyc_fll FLL period jitter
• fVCO = 48 MHz
• fVCO = 98 MHz
—
—
—
180
150
—
—
ps
tfll_acquire FLL target frequency acquisition time — — 1 ms 7
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2.0 V <= VDD <= 3.6 V.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
3.3.2 IRC48M specifications
Table 16. IRC48M specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 — 3.6 V
IDD48M Supply current — 400 500 μA
firc48m Internal reference frequency — 48 — MHz
Δfirc48m_hv Total deviation of IRC48M frequency at high voltage
(VDD=1.89V-3.6V) over full temperature
— ± 0.5 ± 1.5 %firc48m
Δfirc48m_hv Total deviation of IRC48M frequency at high voltage
(VDD=1.89V-3.6V) over -40°C to 85°C
— ± 0.5 ± 1.0 %firc48m
Δfirc48m_lv Total deviation of IRC48M frequency at low voltage
(VDD=1.71V-1.89V) over full temperature
— ± 0.5 ± 2.0 %firc48m
Jcyc_irc48m Period Jitter (RMS) — 35 150 ps
tirc48mst Startup time — 2 3 μs 1
1. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by one of the following settings:
• MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10 or MCG_C5[PLLCLKEN0]=1, or
• SIM_SOPT2[PLLFLLSEL]=11
Peripheral operating requirements and behaviors
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3.3.3 Oscillator electrical specifications
3.3.3.1 Oscillator DC electrical specifications
Table 17. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 — 3.6 V
IDDOSC Supply current — low-power mode (HGO=0)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
500
200
300
950
1.2
1.5
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
1
IDDOSC Supply current — high-gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
25
400
500
2.5
3
4
—
—
—
—
—
—
μA
μA
μA
mA
mA
mA
1
CxEXTAL load capacitance — — — 2, 3
CyXTAL load capacitance — — — 2, 3
RFFeedback resistor — low-frequency, low-power
mode (HGO=0)
— — — MΩ 2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
— 10 — MΩ
Feedback resistor — high-frequency, low-
power mode (HGO=0)
— — — MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
— 1 — MΩ
RSSeries resistor — low-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
— 200 — kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
0
—
kΩ
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 17. Oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
Vpp5Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
— VDD — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
— VDD — V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. When low-power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other device.
3.3.3.2 Oscillator frequency specifications
Table 18. Oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
32 — 40 kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
(MCG_C2[RANGE]=01)
3 — 8 MHz
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8 — 32 MHz
fec_extal Input clock frequency (external clock mode) — — 50 MHz 1, 2
tdc_extal Input clock duty cycle (external clock mode) 40 50 60 %
tcst Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
— 750 — ms 3, 4
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
— 250 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
— 0.6 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
— 1 — ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
Peripheral operating requirements and behaviors
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2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 19. NVM program/erase timing specifications
Symbol Description Min. Typ. Max. Unit Notes
thvpgm4 Longword Program high-voltage time — 7.5 18 μs —
thversscr Sector Erase high-voltage time — 13 113 ms 1
thversall Erase All high-voltage time — 104 904 ms 1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 20. Flash command timing specifications
Symbol Description Min. Typ. Max. Unit Notes
trd1sec2k Read 1s Section execution time (flash sector) — — 60 μs 1
tpgmchk Program Check execution time — — 45 μs 1
trdrsrc Read Resource execution time — — 30 μs 1
tpgm4 Program Longword execution time — 65 145 μs —
tersscr Erase Flash Sector execution time — 14 114 ms 2
trd1all Read 1s All Blocks execution time — — 0.9 ms 1
trdonce Read Once execution time — — 30 μs 1
tpgmonce Program Once execution time — 100 — μs —
tersall Erase All Blocks execution time — 140 1150 ms 2
tvfykey Verify Backdoor Access Key execution time — — 30 μs 1
1. Assumes 25 MHz flash clock frequency.
Peripheral operating requirements and behaviors
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2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 21. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current adder during high voltage
flash programming operation
— 2.5 6.0 mA
IDD_ERS Average current adder during high voltage
flash erase operation
— 1.5 4.0 mA
3.4.1.4 Reliability specifications
Table 22. NVM reliability specifications
Symbol Description Min. Typ.1Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 5 50 — years —
tnvmretp1k Data retention after up to 1 K cycles 20 100 — years —
nnvmcycp Cycling endurance 10 K 50 K — cycles 2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the
differential pins ADCx_DPx, ADCx_DMx.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
Peripheral operating requirements and behaviors
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3.6.1.1 16-bit ADC operating conditions
Table 23. 16-bit ADC operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 — 3.6 V
ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2
ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2
VREFH ADC reference
voltage high
1.13 VDDA VDDA V
VREFL ADC reference
voltage low
VSSA VSSA VSSA V
VADIN Input voltage • 16-bit differential mode
• All other modes
VREFL
VREFL
—
—
31/32 *
VREFH
VREFH
V
CADIN Input
capacitance
• 16-bit mode
• 8-bit / 10-bit / 12-bit
modes
—
—
8
4
10
5
pF
RADIN Input series
resistance
— 2 5 kΩ
RAS Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
3
fADCK ADC conversion
clock frequency
≤ 13-bit mode 1.0 — 24.0 MHz 4
fADCK ADC conversion
clock frequency
16-bit mode 2.0 — 12.0 MHz 4
Crate ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20
—
1200
Ksps
5
Crate ADC conversion
rate
16-bit mode
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
37
—
461
Ksps
5
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
Peripheral operating requirements and behaviors
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RAS
VAS CAS
ZAS
VADIN
ZADIN
RADIN
RADIN
RADIN
RADIN
CADIN
Pad
leakage
due to
input
protection
INPUT PIN
INPUT PIN
INPUT PIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
Figure 11. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
IDDA_ADC Supply current 0.215 — 1.7 mA 3
fADACK
ADC asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
Sample Time See Reference Manual chapter for sample times
TUE Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
±4
±1.4
±6.8
±2.1
LSB45
DNL Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±0.7
±0.2
–1.1 to
+1.9
–0.3 to
0.5
LSB45
INL Integral non-linearity • 12-bit modes — ±1.0 –2.7 to
+1.9
LSB45
Table continues on the next page...
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Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
• <12-bit modes — ±0.5 –0.7 to
+0.5
EFS Full-scale error • 12-bit modes
• <12-bit modes
—
—
–4
–1.4
–5.4
–1.8
LSB4VADIN = VDDA5
EQQuantization error • 16-bit modes
• ≤13-bit modes
—
—
–1 to 0
—
—
±0.5
LSB4
ENOB Effective number of
bits
16-bit differential mode
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
• Avg = 4
12.8
11.9
12.2
11.4
14.5
13.8
13.9
13.1
—
—
—
—
bits
bits
bits
bits
6
SINAD Signal-to-noise plus
distortion
See ENOB 6.02 × ENOB + 1.76 dB
THD Total harmonic
distortion
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
—
—
-94
-85
—
—
dB
dB
7
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
82
78
95
90
—
—
dB
dB
7
EIL Input leakage error IIn × RAS mV IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55 1.62 1.69 mV/°C 8
VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
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4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
12.30
12.00
1 2 3 4 5 6 7 8 9 10 1211
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
Figure 12. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
14.00
13.75
13.25
13.00
12.75
12.50
12.00
11.75
11.50
11.25
11.00
1 2 3 4 5 6 7 8 9 10 1211
Averaging of 4 samples
Averaging of 32 samples
13.50
12.25
Figure 13. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
Peripheral operating requirements and behaviors
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3.6.2 CMP and 6-bit DAC electrical specifications
Table 25. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 1.71 — 3.6 V
IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA
IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA
VAIN Analog input voltage VSS – 0.3 — VDD V
VAIO Analog input offset voltage — — 20 mV
VHAnalog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
10
20
30
—
—
—
—
mV
mV
mV
mV
VCMPOh Output high VDD – 0.5 — — V
VCMPOl Output low — — 0.5 V
tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns
tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns
Analog comparator initialization delay2— — 40 μs
IDAC6b 6-bit DAC current adder (enabled) — 7 — μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
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00
01
10
HYSTCTR
Setting
0.1
10
11
Vin level (V)
CMP Hystereris (V)
3.12.82.5
2.2
1.91.61.3
1
0.70.4
0.05
0
0.01
0.02
0.03
0.08
0.07
0.06
0.04
Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1 12-bit DAC operating requirements
Table 26. 12-bit DAC operating requirements
Symbol Desciption Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
VDACR Reference voltage 1.13 3.6 V 1
CLOutput load capacitance — 100 pF 2
ILOutput load current — 1 mA
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
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3.6.3.2 12-bit DAC operating behaviors
Table 27. 12-bit DAC operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA_DACL
P
Supply current — low-power mode — — 330 μA
IDDA_DACH
P
Supply current — high-speed mode — — 1200 μA
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
— 100 200 μs 1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
— 15 30 μs 1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
— 0.7 1 μs 1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
— — 100 mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
— VDACR mV
INL Integral non-linearity error — high speed
mode
— — ±8 LSB 2
DNL Differential non-linearity error — VDACR > 2
V
— — ±1 LSB 3
DNL Differential non-linearity error — VDACR =
VREF_OUT
— — ±1 LSB 4
VOFFSET Offset error — ±0.4 ±0.8 %FSR 5
EGGain error — ±0.1 ±0.6 %FSR 5
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB
TCO Temperature coefficient offset voltage — 3.7 — μV/C 6
TGE Temperature coefficient gain error — 0.000421 — %FSR/C
Rop Output resistance (load = 3 kΩ) — — 250 Ω
SR Slew rate -80h→ F7Fh→ 80h
• High power (SPHP)
• Low power (SPLP)
1.2
0.05
1.7
0.12
—
—
V/μs
BW 3dB bandwidth
• High power (SPHP)
• Low power (SPLP)
550
40
—
—
—
—
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
Peripheral operating requirements and behaviors
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Digital Code
DAC12 INL (LSB)
0
500 1000 1500 2000 2500 3000 3500 4000
2
4
6
8
-2
-4
-6
-8
0
Figure 16. Typical INL error vs. digital code
Peripheral operating requirements and behaviors
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Temperature °C
DAC12 Mid Level Code Voltage
25 55 85 105 125
1.499
-40
1.4985
1.498
1.4975
1.497
1.4965
1.496
Figure 17. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 28. VREF full-range operating requirements
Symbol Description Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
TATemperature Operating temperature
range of the device
°C
CLOutput load capacitance 100 nF 1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range
of the device.
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Table 29. VREF full-range operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
Vout Voltage reference output with factory trim at
nominal VDDA and temperature=25°C
1.1920 1.1950 1.1980 V 1
Vout Voltage reference output with user trim at
nominal VDDA and temperature=25°C
1.1945 1.1950 1.1955 V 1
Vstep Voltage reference trim step — 0.5 — mV 1
Vtdrift Temperature drift (Vmax -Vmin across the full
temperature range)
— — 15 mV 1
Ibg Bandgap only current — — 80 µA
Ilp Low-power buffer current — — 360 uA 1
Ihp High-power buffer current — — 1 mA 1
ΔVLOAD Load regulation
• current = ± 1.0 mA
—
200
—
µV 1, 2
Tstup Buffer startup time — — 100 µs
Tchop_osc_st
up
Internal bandgap start-up delay with chop
oscillator enabled
— — 35 ms
Vvdrift Voltage drift (Vmax -Vmin across the full
voltage range)
— 2 — mV 1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 30. VREF limited-range operating requirements
Symbol Description Min. Max. Unit Notes
TATemperature 0 70 °C
Table 31. VREF limited-range operating behaviors
Symbol Description Min. Max. Unit Notes
Vtdrift Temperature drift (Vmax -Vmin across the limited
temperature range)
— 10 mV
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
Peripheral operating requirements and behaviors
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3.8.1 DSPI switching specifications (limited voltage range)
The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to
the SPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 32. Master mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation — 25 MHz
DS1 DSPI_SCK output cycle time 2 x tBUS — ns
DS2 DSPI_SCK output high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −
2
— ns 1
DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −
2
— ns 2
DS5 DSPI_SCK to DSPI_SOUT valid — 8.5 ns
DS6 DSPI_SCK to DSPI_SOUT invalid -2 — ns
DS7 DSPI_SIN to DSPI_SCK input setup 16.2 — ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 18. DSPI classic SPI timing — master mode
Peripheral operating requirements and behaviors
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Table 33. Slave mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation — 12.5 MHz 1
DS9 DSPI_SCK input cycle time 4 x tBUS — ns
DS10 DSPI_SCK input high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 21.4 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 2.6 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 17 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 17 ns
1. The maximum operating frequency is measured with noncontinuous CS and SCK. When DSPI is configured with
continuous CS and SCK, the SPI clock must not be greater than 1/6 of the bus clock. For example, when the bus
clock is 60 MHz, the SPI clock must not be greater than 10 MHz.
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 19. DSPI classic SPI timing — slave mode
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3.8.2 DSPI switching specifications (full voltage range)
The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the SPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 34. Master mode DSPI timing (full voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 1.71 3.6 V 1
Frequency of operation — 12.5 MHz
DS1 DSPI_SCK output cycle time 4 x tBUS — ns
DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −
4
— ns 2
DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −
4
— ns 3
DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns
DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 — ns
DS7 DSPI_SIN to DSPI_SCK input setup 24.6 — ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 20. DSPI classic SPI timing — master mode
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Table 35. Slave mode DSPI timing (full voltage range)
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
Frequency of operation — 6.25 MHz
DS9 DSPI_SCK input cycle time 8 x tBUS — ns
DS10 DSPI_SCK input high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 29.5 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 3.2 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 25 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 25 ns
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 21. DSPI classic SPI timing — slave mode
3.8.3 Inter-Integrated Circuit Interface (I2C) timing
Table 36. I 2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency fSCL 0 100 0 4001kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA 4 — 0.6 — µs
LOW period of the SCL clock tLOW 4.7 — 1.25 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START
condition
tSU; STA 4.7 — 0.6 — µs
Table continues on the next page...
Peripheral operating requirements and behaviors
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NXP Semiconductors
Table 36. I 2C timing (continued)
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
Data hold time for I2C bus devices tHD; DAT 023.453040.92µs
Data set-up time tSU; DAT 2505— 1003, 6— ns
Rise time of SDA and SCL signals tr— 1000 20 +0.1Cb7300 ns
Fall time of SDA and SCL signals tf— 300 20 +0.1Cb6300 ns
Set-up time for STOP condition tSU; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
tBUF 4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
tSP N/A N/A 0 50 ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the
High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
Table 37. I 2C 1 Mbps timing
Characteristic Symbol Minimum Maximum Unit
SCL Clock Frequency fSCL 0 11MHz
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA 0.26 — µs
LOW period of the SCL clock tLOW 0.5 — µs
HIGH period of the SCL clock tHIGH 0.26 — µs
Set-up time for a repeated START condition tSU; STA 0.26 — µs
Data hold time for I2C bus devices tHD; DAT 0 — µs
Data set-up time tSU; DAT 50 — ns
Rise time of SDA and SCL signals tr20 +0.1Cb, 2120 ns
Fall time of SDA and SCL signals tf20 +0.1Cb2120 ns
Set-up time for STOP condition tSU; STO 0.26 — µs
Bus free time between STOP and START condition tBUF 0.5 — µs
Pulse width of spikes that must be suppressed by
the input filter
tSP 0 50 ns
1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins across
the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
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SDA
HD; STA tHD; DAT
tLOW
tSU; DAT
tHIGH
tSU; STA SR PS
S
tHD; STA tSP
tSU; STO
tBUF
tftr
tftr
SCL
Figure 22. Timing definition for devices on the I2C bus
3.8.4 UART switching specifications
See General switching specifications.
4Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package Then use this document number
32-pin QFN 98ARE10566D
48-pin LQFP 98ASH00962A
64-pin LQFP 98ASS23234W
5 Pinout
5.1 K02F Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
Dimensions
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 47
NXP Semiconductors
64
LQFP
48
LQFP
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
1 — — PTE0/
CLKOUT32K
DISABLED PTE0/
CLKOUT32K
UART1_TX
2 — — PTE1/
LLWU_P0
DISABLED PTE1/
LLWU_P0
UART1_RX
3 1 1 VDD VDD VDD
4 2 2 VSS VSS VSS
5 3 3 PTE16 ADC0_SE4a/
ADC0_DP1
ADC0_SE4a/
ADC0_DP1
PTE16 SPI0_PCS0 UART1_TX FTM_CLKIN0 FTM0_FLT3
6 4 4 PTE17 ADC0_SE5a/
ADC0_DM1
ADC0_SE5a/
ADC0_DM1
PTE17 SPI0_SCK UART1_RX FTM_CLKIN1 LPTMR0_
ALT3
7 5 5 PTE18 ADC0_SE6a/
ADC0_DP2
ADC0_SE6a/
ADC0_DP2
PTE18 SPI0_SOUT UART1_CTS_
b
I2C0_SDA
8 6 6 PTE19 ADC0_SE7a/
ADC0_DM2
ADC0_SE7a/
ADC0_DM2
PTE19 SPI0_SIN UART1_RTS_
b
I2C0_SCL
9 7 — ADC0_DP0 ADC0_DP0 ADC0_DP0
10 8 — ADC0_DM0 ADC0_DM0 ADC0_DM0
11 — — ADC0_DP3 ADC0_DP3 ADC0_DP3
12 — — ADC0_DM3 ADC0_DM3 ADC0_DM3
13 9 7 VDDA VDDA VDDA
14 10 7 VREFH VREFH VREFH
15 11 8 VREFL VREFL VREFL
16 12 8 VSSA VSSA VSSA
17 13 — VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
18 14 9 DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
19 — — CMP0_IN4 CMP0_IN4 CMP0_IN4
20 15 10 PTE24 ADC0_SE17 ADC0_SE17 PTE24 I2C0_SCL EWM_OUT_b
21 16 11 PTE25 ADC0_SE18 ADC0_SE18 PTE25 I2C0_SDA EWM_IN
22 17 12 PTA0 JTAG_TCLK/
SWD_CLK
PTA0 UART0_CTS_
b
FTM0_CH5 JTAG_TCLK/
SWD_CLK
23 18 13 PTA1 JTAG_TDI PTA1 UART0_RX JTAG_TDI
24 19 14 PTA2 JTAG_TDO/
TRACE_SWO
PTA2 UART0_TX JTAG_TDO/
TRACE_SWO
25 20 15 PTA3 JTAG_TMS/
SWD_DIO
PTA3 UART0_RTS_
b
FTM0_CH0 JTAG_TMS/
SWD_DIO
26 21 16 PTA4/
LLWU_P3
NMI_b PTA4/
LLWU_P3
FTM0_CH1 NMI_b
27 — — PTA5 DISABLED PTA5 FTM0_CH2 JTAG_TRST_
b
28 — — PTA12 DISABLED PTA12 FTM1_CH0 FTM1_QD_
PHA
Pinout
48 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
NXP Semiconductors
64
LQFP
48
LQFP
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
29 — — PTA13/
LLWU_P4
DISABLED PTA13/
LLWU_P4
FTM1_CH1 FTM1_QD_
PHB
30 22 — VDD VDD VDD
31 23 — VSS VSS VSS
32 24 17 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0
33 25 18 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 LPTMR0_
ALT1
34 26 19 RESET_b RESET_b RESET_b
35 27 20 PTB0/
LLWU_P5
ADC0_SE8 ADC0_SE8 PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 FTM1_QD_
PHA
36 28 21 PTB1 ADC0_SE9 ADC0_SE9 PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_
PHB
37 29 — PTB2 ADC0_SE12 ADC0_SE12 PTB2 I2C0_SCL UART0_RTS_
b
FTM0_FLT3
38 30 — PTB3 ADC0_SE13 ADC0_SE13 PTB3 I2C0_SDA UART0_CTS_
b
FTM0_FLT0
39 31 — PTB16 DISABLED PTB16 UART0_RX FTM_CLKIN0 EWM_IN
40 32 — PTB17 DISABLED PTB17 UART0_TX FTM_CLKIN1 EWM_OUT_b
41 — — PTB18 DISABLED PTB18 FTM2_CH0 FTM2_QD_
PHA
42 — — PTB19 DISABLED PTB19 FTM2_CH1 FTM2_QD_
PHB
43 33 — PTC0 ADC0_SE14 ADC0_SE14 PTC0 SPI0_PCS4 PDB0_
EXTRG
44 34 22 PTC1/
LLWU_P6
ADC0_SE15 ADC0_SE15 PTC1/
LLWU_P6
SPI0_PCS3 UART1_RTS_
b
FTM0_CH0
45 35 23 PTC2 ADC0_SE4b/
CMP1_IN0
ADC0_SE4b/
CMP1_IN0
PTC2 SPI0_PCS2 UART1_CTS_
b
FTM0_CH1
46 36 24 PTC3/
LLWU_P7
CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT
47 — — VSS VSS VSS
48 — — VDD VDD VDD
49 37 25 PTC4/
LLWU_P8
DISABLED PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX FTM0_CH3 CMP1_OUT
50 38 26 PTC5/
LLWU_P9
DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_
ALT2
CMP0_OUT FTM0_CH2
51 39 27 PTC6/
LLWU_P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_SOUT PDB0_
EXTRG
52 40 28 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN
53 — — PTC8 CMP0_IN2 CMP0_IN2 PTC8
54 — — PTC9 CMP0_IN3 CMP0_IN3 PTC9 FTM2_FLT0
55 — — PTC10 DISABLED PTC10
56 — — PTC11/
LLWU_P11
DISABLED PTC11/
LLWU_P11
Pinout
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 49
NXP Semiconductors
64
LQFP
48
LQFP
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
57 41 — PTD0/
LLWU_P12
DISABLED PTD0/
LLWU_P12
SPI0_PCS0
58 42 — PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK
59 43 — PTD2/
LLWU_P13
DISABLED PTD2/
LLWU_P13
SPI0_SOUT I2C0_SCL
60 44 — PTD3 DISABLED PTD3 SPI0_SIN I2C0_SDA
61 45 29 PTD4/
LLWU_P14
DISABLED PTD4/
LLWU_P14
SPI0_PCS1 UART0_RTS_
b
FTM0_CH4 EWM_IN
62 46 30 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_
b
FTM0_CH5 EWM_OUT_b
63 47 31 PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX FTM0_CH0 FTM0_FLT0
64 48 32 PTD7 DISABLED PTD7 UART0_TX FTM0_CH1 FTM0_FLT1
5.2 Recommended connection for unused analog and digital
pins
The following table shows the recommended connections for analog interface pins if
those analog interfaces are not used in the customer's application.
Table 38. Recommended connection for unused analog interfaces
Pin Type Short recommendation Detailed recommendation
Analog/non GPIO PGAx/ADCx Float Analog input - Float
Analog/non GPIO ADCx/CMPx Float Analog input - Float
Analog/non GPIO VREF_OUT Float Analog output - Float
Analog/non GPIO DACx_OUT Float Analog output - Float
Analog/non GPIO RTC_WAKEUP_B Float Analog output - Float
Analog/non GPIO XTAL32 Float Analog output - Float
Analog/non GPIO EXTAL32 Float Analog input - Float
GPIO/Analog PTA18/EXTAL0 Float Analog input - Float
GPIO/Analog PTA19/XTAL0 Float Analog output - Float
GPIO/Analog PTx/ADCx Float Float (default is analog input)
GPIO/Analog PTx/CMPx Float Float (default is analog input)
GPIO/Digital PTA0/JTAG_TCLK Float Float (default is JTAG with
pulldown)
GPIO/Digital PTA1/JTAG_TDI Float Float (default is JTAG with
pullup)
GPIO/Digital PTA2/JTAG_TDO Float Float (default is JTAG with
pullup)
GPIO/Digital PTA3/JTAG_TMS Float Float (default is JTAG with
pullup)
Table continues on the next page...
Pinout
50 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
NXP Semiconductors
Table 38. Recommended connection for unused analog interfaces (continued)
Pin Type Short recommendation Detailed recommendation
GPIO/Digital PTA4/NMI_b 10kΩ pullup or disable and
float
Pull high or disable in PCR &
FOPT and float
GPIO/Digital PTx Float Float (default is disabled)
VDDA VDDA Always connect to VDD
potential
Always connect to VDD
potential
VREFH VREFH Always connect to VDD
potential
Always connect to VDD
potential
VREFL VREFL Always connect to VSS
potential
Always connect to VSS
potential
VSSA VSSA Always connect to VSS
potential
Always connect to VSS
potential
5.3 K02F Pinouts
The below figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous section.
Pinout
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 51
NXP Semiconductors
PTE24
CMP0_IN4
DAC0_OUT/CMP1_IN3/ADC0_SE23
VREF_OUT/CMP1_IN5/CMP0_IN5
VSSA
VREFL
VREFH
VDDA
ADC0_DM3
ADC0_DP3
ADC0_DM0
ADC0_DP0
PTE19
PTE18
PTE17
PTE16
VSS
VDD
PTE1/LLWU_P0
PTE0/CLKOUT32K
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
64
63
62
61
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2/LLWU_P13
PTD1
PTD0/LLWU_P12
PTC11/LLWU_P11
PTC10
PTC9
PTC8
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
VDD
VSS
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6
PTC0
PTB19
PTB18
PTB17
PTB16
PTB3
PTB2
PTB1
PTB0/LLWU_P5
RESET_b
PTA19
PTA18
VSS
VDD
PTA13/LLWU_P4
PTA12
PTA5
PTA4/LLWU_P3
PTA3
PTA2
PTA1
PTA0
PTE25
Figure 23. K02F 64 LQFP pinout diagram (top view)
Pinout
52 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
NXP Semiconductors
VSSA
VREFL
VREFH
VDDA
ADC0_DM0
ADC0_DP0
PTE19
PTE18
PTE17
PTE16
VSS
VDD
12
11
10
9
8
7
6
5
4
3
2
1
48
47
46
45
44
43
42
41
40
39
38
37
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2/LLWU_P13
PTD1
PTD0/LLWU_P12
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
36
35
34
33
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6
PTC0
32
31
30
29
28
27
26
25
PTB17
PTB16
PTB3
PTB2
PTB1
PTB0/LLWU_P5
RESET_b
PTA19
PTA3
PTA2
PTA1
PTA0
24
23
22
21
20
19
18
17
PTE25
PTE24
DAC0_OUT/CMP1_IN3/ADC0_SE23
VREF_OUT/CMP1_IN5/CMP0_IN5
16
15
14
13
PTA18
VSS
VDD
PTA4/LLWU_P3
Figure 24. K02F 48 LQFP pinout diagram
Pinout
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 53
NXP Semiconductors
32
31
30
29
28
27
26
25
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
PTA0
PTE25
PTE24
DAC0_OUT/CMP1_IN3/ADC0_SE23
12
11
10
9
PTA4/LLWU_P3
PTA3
PTA2
PTA1
16
15
14
13
PTB0/LLWU_P5
RESET_b
PTA19
PTA18
24
23
22
21
20
19
18
17
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6
PTB1
VREFL VSSA
VDDA VREFH
PTE19
PTE18
PTE17
PTE16
VSS
VDD
8
7
6
5
4
3
2
1
Figure 25. K02F 32 QFN pinout diagram
6Part identification
6.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
Part identification
54 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
NXP Semiconductors
6.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
6.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field Description Values
Q Qualification status • M = Fully qualified, general market flow, full
reel
• P = Prequalification
• K = Fully qualified, general market flow, 100
piece reel
K## Kinetis family • K02
A Key attribute • D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory
FFF Program flash memory size • 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
R Silicon revision • Z = Initial
• (Blank) = Main
• A = Revision after main
T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
PP Package identifier • FM = 32 QFN (5 mm x 5 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
CC Maximum CPU frequency (MHz) • 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
N Packaging type • R = Tape and reel
6.4 Example
This is an example part number:
Part identification
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NXP Semiconductors
MK02FN128VLH10
6.5 48-pin LQFP part marking
The 48-pin LQFP package parts follow the part-marking scheme in the following table.
Table 39. 48-pin LQFP part marking
MK Partnumber MK Part Marking
MK02FN128VLF10 M02J7V
MK02FN64VLF10 M02J6V
6.6 32-pin QFN part marking
The 32-pin QFN package parts follow the part-marking scheme in the following table.
Table 40. 32-pin QFN part marking
MK Part number MK Part Marking
MK02FN128VFM10 M02J7V
MK02FN64VFM10 M02J6V
7 Terminology and guidelines
7.1 Definitions
Key terms are defined in the following table:
Term Definition
Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
•Operating ratings apply during operation of the chip.
•Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Table continues on the next page...
Terminology and guidelines
56 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
NXP Semiconductors
Term Definition
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
7.2 Examples
Operating rating:
Operating requirement:
Operating behavior that includes a typical value:
EXAMPLE
EXAMPLEEXAMPLE
EXAMPLE
7.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Terminology and guidelines
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 57
NXP Semiconductors
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD Supply voltage 3.3 V
7.4 Relationship between ratings and operating requirements
–∞
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
–∞
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
7.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8Revision History
The following table provides a revision history for this document.
Revision History
58 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
NXP Semiconductors
Table 41. Revision History
Rev. No. Date Substantial Changes
4 08/2016 • In "Power consumption operating behaviors" table, added "Low power mode
peripheral adders—typical value" table
• In "Thermal operating requirements" table, in footnote, corrected "TJ = TA + ΘJA" to
"TJ = TA + RΘJA""
• In "Slave mode DSPI timing (limited voltage range)" table, added footnote regarding
maximum frequency of operation
• Added new section, "Recommended connections for unused analog and digital
pins"
• Updated "NVM program/erase timing specifications" table; updated values for
thversall (Erase All high-voltage time)
• Added Terminology and Guidelines section
• Updated Thermal Attributes value for 48LQFP
• Added Device Revision Number table in front matter
34/2015 • Throughout: Modified notes related to 48-pin LQFP to say, "The 48-pin LQFP
package for this product is not yet available; however, it is included in a Package
Your Way program for Kinetis MCUs. Please visit www.Freescale.com/KPYW for
more details."
• On page 1:
• In first bullet of introduction, updated power consumption data to align with the
data in the "Power consumption operating behaviors" table
• Under "Clocks," corrected second and third bullets—moved "with FLL" from
"internal oscillators" to "multipurpose clock generator" bullet
• Under "Communication interfaces," updated I2C bullet to indicate support for
up to 1 Mbps operation
• Under "Operating characteristics," specified that voltage range includes flash
writes
• In "Voltage and current operating requirements" table:
• Removed content related to positive injection
• Updated footnote 1 to say that all analog and I/O pins are internally clamped
to VSS only (not VSS and VDD)through ESD protection diodes.
• In "Power mode transition operating behaviors" table, removed rows for LLS2 and
LLS3
• In "Power consumption operating behaviors" table:
• Provided additional temperature data
• Added Max IDD values based on characterization results equivalent to mean
+ 3 sigma
• Removed rows for LLS2 and LLS3
• Updated "EMC radiated emissions operating behaviors" table
• In "Thermal operating requirements" table, added the following footnote for ambient
temperature: "Maximum TA can be exceeded only if the user ensures that TJ does
not exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + ΘJA x
chip power dissipation"
• Updated "IRC48M Specifications":
• Updated maximum values for Δfirc48m_lv and Δfirc48m_hv (full temperature)
• Added specifications for Δfirc48m_hv (-40°C to 85°C)
• In "I2C timing" table,
• Added the following footnote on maximum Fast mode value for SCL Clock
Frequency: "The maximum SCL Clock Frequency in Fast mode with
maximum bus loading can only be achieved when using the High drive pins
across the full voltage range and when using the Normal drive pins and VDD
≥ 2.7 V."
• Updated minimum Fast mode value for LOW period of the SCL clock to 1.25 µ
• Added "I2C 1 Mbps timing" table
Table continues on the next page...
Revision History
Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016 59
NXP Semiconductors
Table 41. Revision History (continued)
Rev. No. Date Substantial Changes
• Removed Section 6, "Ordering parts."
• Added "48-pin LQFP part marking" section
• Added "32-pin QFN part marking" section
2 8/2014 • On p. 1, under "Memories and memory interfaces," added bullet, "Preprogrammed
Kinetis flashloader for one-time, in-system factory programming"
• On p. 1, added parenthetical element to the following bullet under "Analog
modules":Accurate internal voltage reference (not available for 32-pin QFN
package)
• On p. 1, added parenthetical element to the following bullet under "Timers":Two 2-
channel motor-control general-purpose timers with quadrature decoder
functionality (FTM2 does not have external pins on the 32-pin QFN or the 48-pin
LQFP package)
• In "Voltage and current operating ratings" section, updated digital supply current
maximum value
• In "Voltage and current operating behaviors" section, updated input leakage
information
• In "Power consumption operating behaviors table":
• Updated existing typical and maximum power measurements
• Added new typical power measurements for the following:
• IDD_HSRUN (High Speed Run mode, all peripheral clocks disabled,
current executing CoreMark code)
• IDD_HSRUN (High Speed Run mode, all peripheral clocks disabled,
current executing while(1) loop)
• IDD_RUN (Run mode current in Compute operation, all peripheral
clocks disabled, executing CoreMark code)
• IDD_RUN (Run mode current in Compute operation, all peripheral
clocks disabled, executing while(1) loop)
• IDD_VLPR (Very Low Power mode current in Compute operation, all
peripheral clocks disabled, executing CoreMark code)
• IDD_VLPR (Very Low Power Run mode current in Compute operation,
all peripheral clocks disabled, executing while(1) loop)
• Updated section, "EMC radiated emissions operating behaviors for 64 LQFP
package"
• In "Thermal attributes" section, added 64-pin LQFP and 32-pin QFN package values
• Updated "MCG specifications" table
• Updated "VREF full-range operating behaviors" table
• In the "Part identification" section, added "Format" and "Fields" subsections
13/2014 Initial public release
Revision History
60 Kinetis K02 64 KB/128 KB Flash, Rev. 4, 08/2016
NXP Semiconductors
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damages. “Typical” parameters that may be provided in NXP data sheets and/or
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may vary over time. All operating parameters, including “typicals,” must be
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Document Number K02P64M100SFA
Revision 4, 08/2016