....................................................................................................................................................................................................... SLES235 – JULY 2008

DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE

– Single 3.3-V Power SupplyOutput into 16 , 100 pF

– Integrated Regulators– 100-Pin TQFP (PZP) Package

Figure 1 shows the functional structure of the TAS3218.

Degradation in analog performance is to be expected depending on the quality of MCLKIN.

The hardware architecture of the S/PDIF Encoder can is shown in Figure 13 .

The SPDIF encoder performs the multiplexing of audio, channel status, user, and validity flag. It also performsbi-phase mark encoding of the multiplexed data stream. Audio data for both left and right channels from the DAPare latched at the rising edge of the internal LRCLK, which marks the beginning of next sample cycle. The SPDIFencoder then multiplexes these samples with internally generated preambles, channel status, user data, validityflag, and parity. The channel status and validity flag are generated based on the settings in the SPDIF controlregisters while the user data is fixed to all zero. The bi-phase mark encoded signal is then output starting at thenext rising edge of the internal LRCLK. The generated SPDIF stream is fixed to consumer mode linear audioPCM format.

Specifcation coverage details can be found in Table 3 .

Yes, with restriction 0101010L (Digital Sound Processor), but user data isByte1 (category)

The microcontroller has its own data RAM for storing intermediate values and queuing I

The 256 bytes of Internal Data Memory address space is accessible using indirect addressing instructions(including stack operations). However, only the lower 128 bytes are accessible using direct addressing. Theupper 128 bytes of direct address Data Memory space are used to access ESFRs.