© 2010–2011 Freescale Semiconductor, Inc.
Freescale Semiconductor
Data Sheet Documen t Nu mber: MSC8158E
Rev. 0, 11/2011
MSC8158E
FC-PBGA–783
29 mm ×29 mm
• Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP
core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,
unified 512 Kbyte L2 cache confi gurable as M2 memory in
64 Kbyte increments, memory management unit (MMU),
extended programmable interrupt controller (EPIC), two
general-purpose 32-bit tim e rs, debug and profiling support,
low-power Wait, Stop, and power-down processing modes, and
ECC/EDC support.
• Chip -leve l arbitra tio n and swi tc hing syste m (CLASS) that
provides full fabric non-blocking arbitration between the cores
and other ini tia tors and the M2 memory, share d M3 memory,
DDR SRAM controller, device configuration control and status
register s, MAPLE-B, and other targets.
• 307 2 Kbyt e 128- bit wid e M3 memo ry, 2048 Kbyte s of wh ich can
be turned off to save power.
• 96 Kbyte boot ROM.
• Three input clocks (one global and two differential) .
• Six PLLs (three global, two Serial RapidIO, one DDR PLLs).
• Secon d genera tion Multi-Ac celerato r Platform Engine for
Baseband (MAPLE-B2) with a second generation programmable
system interface (PSIF2); Turbo encoding and decoding; Viterbi
decoding; FFT/iFFT and DFT/iDFT processing; downlink chip
rate processing; CRC processing and insertion; uplink batch and
fast processing. Some MAPLE-B2 pro cessors can be disabl ed
when not required to reduce overall power consumption.
• Security Engine (SEC) optimized to process all the algorithms
associated with IPSec, IKE, SSL/TLS , 3GPP, and LTE using 4
crypto-channels with multi-command descriptor chains,
integrated controller for assignment of the eight execution units
(PKEU, DEU, AESU, AFEU, MDEU, KEU, SNOW, and the
random number generator (RNG), and XOR engine to accelerate
parity checking for RAID storage applications.
• One DDR controllers with up to a 667 MHz clock (1333 MHz
data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in
up to four banks (two per controller) and support for DDR3.
• DMA con trol l er with 32 unidirec tio na l cha nn els sup por tin g 16
memory-to-memory channels with up to 1024 buffer descriptors
per channe l, and program mable priority, bu ffer , a nd multiplexin g
configuration. It is optimized for DDR SDRAM.
• High-speed serial interface wi t h an 8-lane SerDes PHY that
suppor ts two Se rial Rapi dIO interfa ces, six C PR I lanes, and two
SGMII interfaces (multiplexed). Serial RapidIO controller 1
supports x1/x2/x4 op eration and serial RapidIO controller 2
supports x1/x2 operation, bot h up to 5 Gbaud with an enhanced
messaging unit (eMSG) and two DMA units. The six CPRI
controllers can support six lanes up to 6.144 Gbaud
• QUICC E ngine technology subsyst em with dual R ISC
processors, 48 Kbyte multi-master RAM, 48 Kbyte instructi on
RAM, supportin g two commun ication controllers fo r two Gigabit
Ethernet interfaces (RGMII or SGMII), to offload scheduling
tasks from the DSP cores, and an SPI.
• I/O Interrupt Concentrator consolidates all chip maskable
interrupt and non-maskable interrupt sources and routes then to
INT_OUT/CP_TX_INT, NMI_OUT/CP_RX_INT, and the cores.
• UART that permits full-duplex operation with a bit rate of up to
6.25 Mbps.
• T wo general-pu rpose 32-bit timers for R T OS support per SC3850
core, four timer modules with four 16-bit fully programmable
timers, two timer modules with four 32-bit fully programmable
timers; and eight software watchdog timers (SWT).
• Eight programmable hard war e semaphores.
• Up to 32 virtual interrupts and a virtual NMI asserted by simple
write access.
•I
2C interface.
• Up to 32 GPIO ports, sixteen of which can be configured as
external interrupts.
• Boot interface options include Ethernet, Serial RapidIO interface,
I2C, and SPI.
• Supports IEEE Std. 1149.6 JTAG interface
• Low power CMOS design , with low-power standby and
powe r-dow n modes, a nd opt imized po wer- managem ent circu itry .
• 45 nm SOI CMOS technology.
Six-Core Digital Signal
Processor wi th Security
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freesca le Sem ico nd uctor2
Table of Contents
1 Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 FC-PBGA Ba ll La yout Diagram. . . . . . . . . . . . . . . . . . . .3
1.2 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2 Ele c t r i c a l C h a ra c t e r i s t i c s . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.1 Max imum Ra ting s . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .40
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
2.4 CLKIN/MCLKIN Requirements . . . . . . . . . . . . . . . . . . .41
2.5 DC Electrical Chara c te ristics . . . . . . . . . . . . . . . . . . . .41
2.6 AC Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . .51
3 Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . . 68
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6 Pro duct D o c u menta ti o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
List of Figures
Figure 1. MSC8158E Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. MSC8158E FC-PB GA Pac kage, Top View. . . . . . . . . . . 3
Figure 3. Differential Voltage Definitions for Transmitter/Receiver 43
Figure 4. Receiver of SerDes Reference Clocks . . . . . . . . . . . . . 44
Figure 5. SerDes Transmitter and Receiver Reference Circuits . 45
Figure 6. Differential Reference Clock Input DC Requirements
(Ex te rnal D C - C o uple d ) . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7. Differential Reference Clock Input DC Requirements
(External AC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 8. Single-Ended Reference Clock Input DC Requirements47
Figure 9. DDR3 SDRAM Interface Input Timing Diagram . . . . . . 52
Figure 10.MCK to MDQS Timing. . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 11.DDR SDRAM Output Timing . . . . . . . . . . . . . . . . . . . . . 54
Figure 12.DDR3 Controller Bus AC Test Load . . . . . . . . . . . . . . . 55
Figure 13.DDR3 SDRAM Differential Timing Specifications . . . . . 55
Figure 14.Differential Measurement Points for Rise and Fall Time 56
Figure 15.Single-Ended Measurement Points for Rise and Fall Time
Matchi n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 16.Single Frequency Sinusoidal Jitter Limits for Data Rates for
3.125 Gbps and Below . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 17.Single Frequency Sinusoidal Jitter Limit s for Dat a Rate 5.0
Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 18.SGMII AC Test/Measurement Load. . . . . . . . . . . . . . . . 61
Figure 19.Single Frequency Sinusoidal Jitter Limit s for Baud Rate for
<3.125 Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 20.Single Frequency Sinus oidal Jitter Limits for Baud Rate
3.125 Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 21.Timer AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 22.MII Management Interface Timing. . . . . . . . . . . . . . . . . 64
Figure 23.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . . 64
Figure 24.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 25.SP I AC Timing in Slave Mode (External Clock). . . . . . . 65
Figure 26.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 66
Figure 27.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 28.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 67
Figure 29.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 30.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 31.MS C8158E Mechanical Information, 783-ball FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 1. MSC8158E Block Diagram
JTAG IEEE 1149.6
Note: The arrow direction indicates master or slave.
DMA 32 ch
I/O-Interrupt
Concentrator
UART
Clocks
Timers
Reset
Semaphores
Other
CLASS
Modules
Boot ROM
I2C
Virtual
Interrupts
SEC
MAPLE-B2
Six DSP Cores at 1 GHz
M3 Memory
3072 Kbyte
SC3850
DSP Core
512 Kbyte
32 Kbyte 32 Kbyte
L1
ICache L1
DCache
L2 Cache / M2 Memory
DDR Interface 64/32-bit
DDR
Controller
High-Speed
QUICC
SPI
Tw o SGMII
Two RGMII
Subsystem
Engine™ Serial
Interface
1333 MHz data rate
Two Serial RapidIO (1 = x1/x2/x4; 2 = x1/x2) up to 5 Gbaud
Two SGMII
Six lanes CPRI v4.1 up to 6.144 Gbaud
CLASS1
CPRI data WR
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 3
1 Pin Assignment
This section includes a MSC 8158E package ball grid array layout and table listing the sig nal allocation by ball location.
1.1 FC-PBGA Ball Layout Diagram
The top view of the FC-PBGA package is shown in Figure 2 with the bal l locati on index numbers. Only the first multiplexed
signal is shown. See Table 1 for a complete signal li st by ball location.
Note: See Figure 31 as a reference for correct ball grid layout.
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A VSS MDQ57 GVDD VSS MDQ63 GVDD NC NC NC NC NC CLKOUT EE0 VSS MCLKIN
(optional) VSS CLKIN VSS GPIO29 GPIO31 GE1_TX_
CTL GE1_GTX
_CLK GE1_TD0GE1_TX_
CLK GE1_TD2GE1_TD1GE1_TD3 A
BMDQ60 MDQ59 MDQS7 MDQS7 MDQ62 MDQ58 MDQ56 NC VSS NC VSS NC VSS TDO TMS VSS VSS VSS VSS GE2_TX_
CLK VSS VSS VSS GPIO25 VSS GE_MDC VSS GPIO18 B
CVSS GVDD MDQ61 VSS GVDD MDM7 VSS NC NC NC NC NC NC EE1 NC DFT_TESTPORESET VSS GPIO15 GE2_TD2GE2_GTX
_CLK GE2_TX_
CTL GE2_TD1GE2_TD0 GPIO30 GPIO20 GE_MDIO GPIO21 C
DMDQ49 MDQ48 MDQS6 MDQS6 MDQ50 MDQ51 MDQ52 NC VSS NC VSS NC VSS NC NMI VSS HRESET_
IN VSS VSS GPIO13 NVDD GE2_TD3 VSS GPIO5 NVDD GPIO16 VSS GPIO10 D
EMDQ53 VSS MDQ55 GVDD VSS MDQ54 GVDD VSS NC NC NC NC NC NC
INT_
OUT HRESET TCK VSS NVDD GE2_RD3 VSS VSS NVDD GPIO27 VSS GPIO0 GPIO17 GPIO1 E
FMDQ40 MDQ41 MDQS5 MDQS5 MDQ43 MDQ47 MDM6 VDD VSS VDD NC NC VSS NC
NMI_
OUT VSS TDI VSS GE2_RD2GE2_RX_
CTL GE2_RD0GE2_RX_
CLK GE2_RD1 GPIO26 GPIO6 GPIO22 GPIO23 GPIO8 F
GVSS GVDD MDM5 VSS GVDD MDQ46 VDD VSS VDD VSS NC NC NC NC QVDD STOP_BS TRST VSS GPIO28 GE1_RD3GE1_RD2GE1_RX_
CLK VSS GE1_RX_
CTL NVDD GPIO19 VSS GPIO11 G
HMDQ38 MDQS4 MDQS4 MDQ44 MDQ45 MDQ42 VSS VDD VSS VDD VSS VSS NC QVDD VSS VDD VSS VDD VSS NVDD VSS GE1_RD0 NVDD GE1_RD1 VSS GPIO14 NVDD GPIO12 H
JMDQ37 VSS MDQ35 GVDD MDQ33 MDQ36 VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NVDD GPIO24 GPIO9 RCW_
LSEL0 RCW_
LSEL3 RCW_
LSEL2 RC21 GPIO3 J
KMCAS MCS0 MCS1 MDQ39 MDQ32 MDQ34 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS GPIO4 VSS RCW_
LSEL1 NVDD GPIO7 VSS GPIO2 K
LVSS GVDD NC VSS GVDD MDM4 VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NVDD NC NC VSS VSS VSS SXCVSS SXCVDD L
MMCK0 MCK0 MA13 MWE NC NC VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC NC NC SXPVDD SXPVSS SXCVSS SXCVSS M
NMRAS VSS NC GVDD VSS MODT1 CRPEVDD VSS CRPEVDD VSS CRPEVDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC NC SXPVDD SXPVSS NC NC SXCVSS SXCVDD N
PMCK2 MA10 NC MA4 NC MODT0 VSS CRPEVDD VSS CRPEVDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC SD_IMP_
CAL_RX NC NC SXPVDD SXPVSS SXCVSS SXCVSS P
RMCK2 GVDD MA0 VSS GVDD MBA0 GVDD VSS VDD VSS CRPEVDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC NC NC NC SD_C_
TX SD_C_
TX SXCVSS SXCVDD R
TVSS VSS MCK1 MA1 MA3 MAPAR_
OUT VSS GVDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC NC NC SXPVDD SXPVSS SD_C_
RX SD_C_
RX T
UMAVDD VSS MCK1 GVDD VSS MBA1 GVDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC NC NC NC SD_D_
TX SD_D_
TX SXCVSS SXCVDD U
VMVREF VSS MA8 MA2 MA6 MCKE1 VSS GVDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC NC NC NC NC SD_D_
RX SD_D_
RX V
WVSS VSS MA5 VSS GVDD MMDIC1 GVDD VSS VDD VSS M3VDD VSS M3VDD VSS M3VDD VSS CPRIVDD VSS VDD VSS NC NC NC SD_PLL1
_AVDD SD_PLL1
_AGND NC SXCVSS SXCVDD W
YMA11 MA9 MA12 MA7 NC MMDIC0 VSS GVDD VSS VDD VSS M3VDD VSS M3VDD VSS CPRIVDD VSS CPRIVDD VSS VDD NC NC NC NC NC NC SD_REF_
CLK1 SD_REF_
CLK1 Y
AA MDQS8 VSS MA14 GVDD VSS MA15 MCKE0 VSS GVDD VSS M3VDD VSS M3VDD VSS CPRIVDD VSS CPRIVDD VSS CPRIVDD NC SD_IMP_
CAL_TX NC NC NC SD_E_
TX SD_E_
TX SXCVSS SXCVDD AA
AB MDQS8 MDM8 MECC2 MECC1 NC MAPAR_
IN MBA2 MDQ2 MDQ1 MDQ0 VSS M3VDD VSS M3VDD VSS CPRIVDD VSS CPRIVDD NC NC NC NC NC NC SXPVDD SXPVSS SD_E_
RX SD_E_
RX AB
AC VSS GVDD MECC4 VSS GVDD MDQ25 VSS GVDD MDQ3 VSS GVDD VSS M3VDD VSS CPRIVDD VSS NC NC NC NC NC NC NC NC SD_F_
TX SD_F_
TX SXCVSS SXCVDD AC
AD MECC7 MECC6 MECC0 MECC5 MECC3 MDQ24 MDM0 MDQS0 MDQS0 MDQ4 MDQ6 VSS VSS VSS VSS VSS NC SD_PLL2
_AVDD NC NC NC NC NC NC SXPVDD SXPVSS SD_F_
RX SD_F_
RX AD
AE MDQS2 VSS MDQ18 GVDD VSS MDQ29 GVDD VSS MDQ5 GVDD VSS MDQ9 VSS VSS VSS VSS NC SD_PLL2
_AGND NC SD_J_TX SXPVDD SD_I_ TX SX PVD D NC SD_G_
TX SD_G_
TX SXCVSS SXCVDD AE
AF MDQS2 MDQ17 MDQ21 MDQ16 MDQ30 MDQ27 MDQ28 MDQ7 MDQ14 MDQ11 MDQ8 MDQ10 VSS VSS VSS VSS NC NC NC SD_J_TX SXPVSS SD_I_
TX SXPVSS NC SXPVDD SXPVSS SD_G_
RX SD_G_
RX AF
AG VSS GVDD MDQ22 VSS GVDD MDQ26 VSS GVDD MDQ13 VSS GVDD MDQ12 VSS VSS VSS VSS NC SXCVSS SD_REF_
CLK2 SXCVSS SD_J_
RX SXCVSS SD_I_
RX SXCVSS SD_H_
TX SD_H_
TX SXCVSS SXCVDD AG
AH MDQ20 MDQ19 MDQ23 MDM2 MDQS3 MDQS3 MDM3 MDQ31 MDQS1 MDQS1 MDQ15 MDM1 VSS PLL0_
AVDD PLL1_
AVDD PLL2_
AVDD NC SXCVDD SD_REF_
CLK2 SXCVDD SD_J_
RX SXCVDD SD_I_RX SXCVDD SXPVDD SXPVSS SD_H_
RX SD_H_
RX AH
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Figure 2. MSC8158E FC-PBGA Package, Top View
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor4
1.2 Signal Lists
Table 1 presents the signal list sorted by ball number. Table 2 presents the sig nal list by signal name. When designing a boar d,
make sure that the power rail for each signal is appropriately considered. The specified power rail must be tied to the voltage
level specified in this document if any of the related signal functions are used (active)
Note: The information in Table 1 distinguishes among three concepts. First, the power pins are the balls of the device
package used to supply specific power levels for different device subsystems (as opposed to signals). Second, the
power rails are the electrical lines on the board that tran sfer power from the voltage regulator s to the device. They are
indicated here as the reference power rails for signal lines; therefore, the actual power inputs are listed as N/A with
regard to the power rails. Third, symb ols used in these tables are the names for th e voltage levels (absolute,
recommended, and so on) and not the power supplies themselves.
Table 1. Signal List by Ball Number
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
A2 VSS Ground N/A
A3 MDQ57 I/O GVDD
A4 GVDD Power N/A
A5 VSS Ground N/A
A6 MDQ63 I/O GVDD
A7 GVDD Power N/A
A8 NC Non-user N/A
A9 NC Non-user N/A
A10 NC Non-user N/A
A11 NC Non-user N/A
A12 NC Non-user N/A
A13 CLKOUT OQVDD
A14 EE0 IQVDD
A15 VSS Ground N/A
A16 MCLKIN (optional) I QVDD
A17 VSS Ground N/A
A18 CLKIN IQVDD
A19 VSS Ground N/A
A20 GPIO29/UART_TXD/CP_LOS2 I/O NVDD
A21 GPIO31/I2C_SDA I/O NVDD
A22 GE1_TX_CTL ONVDD
A23 GE1_GTX_CLK ONVDD
A24 GE1_TD0 ONVDD
A25 GE1_TX_CLK INVDD
A26 GE1_TD2 ONVDD
A27 GE1_TD1 ONVDD
A28 GE1_TD3 ONVDD
B1 MDQ60 I/O GVDD
B2 MDQ59 I/O GVDD
B3 MDQS7 I/O GVDD
B4 MDQS7 I/O GVDD
B5 MDQ62 I/O GVDD
B6 MDQ58 I/O GVDD
B7 MDQ56 I/O GVDD
B8 NC Non-user N/A
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 5
B9 VSS Ground N/A
B10 NC Non-user N/A
B11 VSS Ground N/A
B12 NC Non-user N/A
B13 VSS Ground N/A
B14 TDO OQVDD
B15 TMS IQVDD
B16 VSS Ground N/A
B17 VSS Ground N/A
B18 VSS Ground N/A
B19 VSS Ground N/A
B20 GE2_TX_CLK INVDD
B21 VSS Ground N/A
B22 NVDD Power N/A
B23 VSS Ground N/A
B24 GPIO25/TMR2/RCW_SRC1 I/O NVDD
B25 VSS Ground N/A
B26 GE_MDC ONVDD
B27 VSS Ground N/A
B28 GPIO18/SPI_MOSI/CP_LOS4 I/O NVDD
C1 VSS Ground N/A
C2 GVDD Power N/A
C3 MDQ61 I/O GVDD
C4 VSS Ground N/A
C5 GVDD Power N/A
C6 MDM7 OGVDD
C7 VSS Ground N/A
C8 NC Non-user N/A
C9 NC Non-user N/A
C10 NC Non-user N/A
C11 NC Non-user N/A
C12 NC Non-user N/A
C13 NC Non-user N/A
C14 EE1 OQVDD
C15 NC Non-user N/A
C16 DFT_TEST IQVDD
C17 PORESET IQVDD
C18 VSS Ground N/A
C19 GPIO15/DDN0/IRQ15/RC15 I/O NVDD
C20 GE2_TD2/CP_LOS3 I/O NVDD
C21 GE2_GTX_CLK/CP_LOS4 I/O NVDD
C22 GE2_TX_CTL ONVDD
C23 GE2_TD1 ONVDD
C24 GE2_TD0 ONVDD
C25 GPIO30/I2C_SCL I/O NVDD
C26 GPIO20/SPI_SL/CP_LOS6 I/O NVDD
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor6
C27 GE_MDIO I/O NVDD
C28 GPIO21/TMR6 I/O NVDD
D1 MDQ49 I/O GVDD
D2 MDQ48 I/O GVDD
D3 MDQS6I/O GVDD
D4 MDQS6 I/O GVDD
D5 MDQ50 I/O GVDD
D6 MDQ51 I/O GVDD
D7 MDQ52 I/O GVDD
D8 NC Non-user N/A
D9 VSS Ground N/A
D10 NC Non-user N/A
D11 VSS Ground N/A
D12 NC Non-user N/A
D13 VSS Ground N/A
D14 NC Non-user N/A
D15 NMI IQVDD
D16 VSS Ground N/A
D17 HRESET_IN IQVDD
D18 VSS Ground N/A
D19 VSS Non-user N/A
D20 GPIO13/IRQ13/RC13 I/O NVDD
D21 NVDD Power N/A
D22 GE2_TD3/CP_LOS5 I/O NVDD
D23 VSS Ground N/A
D24 GPIO5/IRQ5/RC5/CP_SYNC4 I/O NVDD
D25 NVDD Power N/A
D26 GPIO16/TMR5/RC16 I/O NVDD
D27 VSS‘ Ground N/A
D28 GPIO10/IRQ10/RC10 I/O NVDD
E1 MDQ53 I/O GVDD
E2 VSS Ground N/A
E3 MDQ55 I/O GVDD
E4 GVDD Power N/A
E5 VSS Ground N/A
E6 MDQ54 I/O GVDD
E7 GVDD Power N/A
E8 VSS Ground N/A
E9 NC Non-user N/A
E10 NC Non-user N/A
E11 NC Non-user N/A
E12 NC Non-user N/A
E13 NC Non-user N/A
E14 NC Non-user N/A
E15 INT_OUT/CP_TX_INT OQVDD
E16 HRESET I/O QVDD
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 7
E17 TCK IQVDD
E18 VSS Ground N/A
E19 NVDD Power N/A
E20 GE2_RD3/CP_LOS2 I NVDD
E21 VSS Ground N/A
E22 VSS Non-user N/A
E23 NVDD Power N/A
E24 GPIO27/TMR4/RCW_SRC0 I/O NVDD
E25 VSS Ground N/A
E26 GPIO0/IRQ0/RC0/CP_SYNC1 I/O NVDD
E27 GPIO17/SPI_SCK/CP_LOS3 I/O NVDD
E28 GPIO1/IRQ1/RC1/CP_SYNC2 I/O NVDD
F1 MDQ40 I/O GVDD
F2 MDQ41 I/O GVDD
F3 MDQS5I/O GVDD
F4 MDQS5 I/O GVDD
F5 MDQ43 I/O GVDD
F6 MDQ47 I/O GVDD
F7 MDM6 OGVDD
F8 VDD Power N/A
F9 VSS Ground N/A
F10 VDD Power N/A
F11 NC Non-user N/A
F12 NC Non-user N/A
F13 VSS Ground N/A
F14 NC Non-user N/A
F15 NMI_OUT/CP_RX_INT OQVDD
F16 VSS Ground N/A
F17 TDI IQVDD
F18 VSS Ground N/A
F19 GE2_RD2/CP_LOS1 I NVDD
F20 GE2_RX_CTL INVDD
F21 GE2_RD0/CP_LOS6 I NVDD
F22 GE2_RX_CLK INVDD
F23 GE2_RD1 INVDD
F24 GPIO26/TMR3 I/O NVDD
F25 GPIO6/IRQ6/RC6/CP_SYNC5 I/O NVDD
F26 GPIO22 I/O NVDD
F27 GPIO23/TMR0/BOOT_SPI_SL I/O NVDD
F28 GPIO8/IRQ8/RC8 I/O NVDD
G1 VSS Ground N/A
G2 GVDD Power N/A
G3 MDM5 OGVDD
G4 VSS Ground N/A
G5 GVDD Power N/A
G6 MDQ46 I/O GVDD
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor8
G7 VDD Power N/A
G8 VSS Ground N/A
G9 VDD Power N/A
G10 VSS Ground N/A
G11 NC Non-user N/A
G12 NC Non-user N/A
G13 NC Non-user N/A
G14 NC Non-user N/A
G15 QVDD Power N/A
G16 STOP_BS IQVDD
G17 TRST IQVDD
G18 VSS Ground N/A
G19 GPIO28/UART_RXD/CP_LOS1 I/O NVDD
G20 GE1_RD3 INVDD
G21 GE1_RD2 INVDD
G22 GE1_RX_CLK INVDD
G23 VSS Ground N/A
G24 GE1_RX_CTL INVDD
G25 NVDD Power N/A
G26 GPIO19/SPI_MISO/CP_LOS5 I/O NVDD
G27 VSS Ground N/A
G28 GPIO11/IRQ11/RC11 I/O NVDD
H1 MDQ38 I/O GVDD
H2 MDQS4 I/O GVDD
H3 MDQS4 I/O GVDD
H4 MDQ44 I/O GVDD
H5 MDQ45 I/O GVDD
H6 MDQ42 I/O GVDD
H7 VSS Ground N/A
H8 VDD Power N/A
H9 VSS Ground N/A
H10 VDD Power N/A
H11 VSS Ground N/A
H12 VSS Non-user N/A
H13 NC Non-user N/A
H14 QVDD Power N/A
H15 VSS Ground N/A
H16 VDD Power N/A
H17 VSS Ground N/A
H18 VDD Power N/A
H19 VSS Ground N/A
H20 NVDD Power N/A
H21 VSS Ground N/A
H22 GE1_RD0 INVDD
H23 NVDD Power N/A
H24 GE1_RD1 INVDD
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 9
H25 VSS Ground N/A
H26 GPIO14/DRQ0/IRQ14/RC14 I/O NVDD
H27 NVDD Power N/A
H28 GPIO12/IRQ12/RC12 I/O NVDD
J1 MDQ37 I/O GVDD
J2 VSS Ground N/A
J3 MDQ35 I/O GVDD
J4 GVDD Power N/A
J5 MDQ33 I/O GVDD
J6 MDQ36 I/O GVDD
J7 VDD Power N/A
J8 VSS Ground N/A
J9 VDD Power N/A
J10 VSS Ground N/A
J11 VDD Power N/A
J12 VSS Ground N/A
J13 VDD Power N/A
J14 VSS Ground N/A
J15 VDD Power N/A
J16 VSS Ground N/A
J17 VDD Power N/A
J18 VSS Ground N/A
J19 VDD Power N/A
J20 VSS Ground N/A
J21 NVDD Power N/A
J22 GPIO24/TMR1/RCW_SRC2 I/O NVDD
J23 GPIO9/IRQ9/RC9 I/O NVDD
J24 RCW_LSEL0/RC17 I/O NVDD
J25 RCW_LSEL3/RC20 I/O NVDD
J26 RCW_LSEL2/RC19 I/O NVDD
J27 RC21 INVDD
J28 GPIO3/DRQ1/IRQ3/RC3 I/O NVDD
K1 MCAS OGVDD
K2 MCS0 OGVDD
K3 MCS1 OGVDD
K4 MDQ39 I/O GVDD
K5 MDQ32 I/O GVDD
K6 MDQ34 I/O GVDD
K7 VSS Ground N/A
K8 VDD Power N/A
K9 VSS Ground N/A
K10 VDD Power N/A
K11 VSS Ground N/A
K12 VDD Power N/A
K13 VSS Ground N/A
K14 VDD Power N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor10
K15 VSS Ground N/A
K16 VDD Power N/A
K17 VSS Ground N/A
K18 VDD Power N/A
K19 VSS Ground N/A
K20 VDD Power N/A
K21 VSS Ground N/A
K22 GPIO4/DDN1/IRQ4/RC4 I/O NVDD
K23 VSS Ground N/A
K24 RCW_LSEL1/RC18 I/O NVDD
K25 NVDD Power N/A
K26 GPIO7/IRQ7/RC7/CP_SYNC6 I/O NVDD
K27 VSS Ground N/A
K28 GPIO2/IRQ2/RC2/CP_SYNC3 I/O NVDD
L1 VSS Ground N/A
L2 GVDD Power N/A
L3 NC Non-user N/A
L4 VSS Ground N/A
L5 GVDD Power N/A
L6 MDM4 OGVDD
L7 VDD Power N/A
L8 VSS Ground N/A
L9 VDD Power N/A
L10 VSS Ground N/A
L11 VDD Power N/A
L12 VSS Ground N/A
L13 VDD Power N/A
L14 VSS Ground N/A
L15 VDD Power N/A
L16 VSS Ground N/A
L17 VDD Power N/A
L18 VSS Ground N/A
L19 VDD Power N/A
L20 VSS Ground N/A
L21 NVDD Power N/A
L22 NC NC N/A
L23 NC NC N/A
L24 VSS Non-user N/A
L25 VSS Non-user N/A
L26 VSS Non-user N/A
L27 SXCVSS Ground N/A
L28 SXCVDD Power N/A
M1 MCK0 OGVDD
M2 MCK0 OGVDD
M3 MA13 OGVDD
M4 MWE OGVDD
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 11
M5 NC Non-user N/A
M6 NC Non-user N/A
M7 VSS Ground N/A
M8 VDD Power N/A
M9 VSS Ground N/A
M10 VDD Power N/A
M11 VSS Ground N/A
M12 VDD Power N/A
M13 VSS Ground N/A
M14 VDD Power N/A
M15 VSS Ground N/A
M16 VDD Power N/A
M17 VSS Ground N/A
M18 VDD Power N/A
M19 VSS Ground N/A
M20 VDD Power N/A
M21 NC NC N/A
M22 NC NC N/A
M23 NC Non-user N/A
M24 NC Non-user N/A
M25 SXPVDD Power N/A
M26 SXPVSS Ground N/A
M27 SXCVSS (not a ground pin) Non-user N/A
M28 SXCVSS (not a ground pin) Non-user N/A
N1 MRAS OGVDD
N2 VSS Ground N/A
N3 NC Non-user N/A
N4 GVDD Power N/A
N5 VSS Ground N/A
N6 MODT1 OGVDD
N7 CRPEVDD Power N/A
N8 VSS Ground N/A
N9 CRPEVDD Power N/A
N10 VSS Ground N/A
N11 CRPEVDD Power N/A
N12 VSS Ground N/A
N13 VDD Power N/A
N14 VSS Ground N/A
N15 VDD Power N/A
N16 VSS Ground N/A
N17 VDD Power N/A
N18 VSS Ground N/A
N19 VDD Power N/A
N20 VSS Ground N/A
N21 NC NC N/A
N22 NC NC N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor12
N23 SXPVDD Power N/A
N24 SXPVSS Ground N/A
N25 NC Non-user N/A
N26 NC Non-user N/A
N27 SXCVSS Ground N/A
N28 SXCVDD Power N/A
P1 MCK2 OGVDD
P2 MA10 OGVDD
P3 NC Non-user N/A
P4 MA4 OGVDD
P5 NC Non-user N/A
P6 MODT0 OGVDD
P7 VSS Ground N/A
P8 CRPEVDD Power N/A
P9 VSS Ground N/A
P10 CRPEVDD Power N/A
P11 VSS Ground N/A
P12 VDD Power N/A
P13 VSS Ground N/A
P14 VDD Power N/A
P15 VSS Ground N/A
P16 VDD Power N/A
P17 VSS Ground N/A
P18 VDD Power N/A
P19 VSS Ground N/A
P20 VDD Power N/A
P21 NC NC N/A
P22 SD_IMP_CAL_RX I SXCVDD
P23 NC NC N/A
P24 NC NC N/A
P25 SXPVDD Power N/A
P26 SXPVSS Ground N/A
P27 SXCVSS (not a ground pin) Non-user N/A
P28 SXCVSS (not a ground pin) Non-user N/A
R1 MCK2 OGVDD
R2 GVDD Power N/A
R3 MA0 OGVDD
R4 VSS Ground N/A
R5 GVDD Power N/A
R6 MBA0 OGVDD
R7 GVDD Power N/A
R8 VSS Ground N/A
R9 VDD Power N/A
R10 VSS Ground N/A
R11 CRPEVDD Power N/A
R12 VSS Ground N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 13
R13 VDD Power N/A
R14 VSS Ground N/A
R15 VDD Power N/A
R16 VSS Ground N/A
R17 VDD Power N/A
R18 VSS Ground N/A
R19 VDD Power N/A
R20 VSS Ground N/A
R21 NC NC N/A
R22 NC NC N/A
R23 NC NC N/A
R24 NC NC N/A
R25 SD_C_TX O SXPVDD
R26 SD_C_TX O SXPVDD
R27 SXCVSS Ground N/A
R28 SXCVDD Power N/A
T1 VSS Ground N/A
T2 VSS Ground N/A
T3 MCK1 OGVDD
T4 MA1 OGVDD
T5 MA3 OGVDD
T6 MAPAR_OUT OGVDD
T7 VSS Ground N/A
T8 GVDD Power N/A
T9 VSS Ground N/A
T10 VDD Power N/A
T11 VSS Ground N/A
T12 VDD Power N/A
T13 VSS Ground N/A
T14 VDD Power N/A
T15 VSS Ground N/A
T16 VDD Power N/A
T17 VSS Ground N/A
T18 VDD Power N/A
T19 VSS Ground N/A
T20 VDD Power N/A
T21 NC NC N/A
T22 NC Non-user N/A
T23 NC Non-user N/A
T24 NC NC N/A
T25 SXPVDD Power N/A
T26 SXPVSS Ground N/A
T27 SD_C_RX ISXCVDD
T28 SD_C_RX ISXCVDD
U1 MAVDD Power N/A
U2 VSS Ground N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor14
U3 MCK1 OGVDD
U4 GVDD Power N/A
U5 VSS Ground N/A
U6 MBA1 OGVDD
U7 GVDD Power N/A
U8 VSS Ground N/A
U9 VDD Power N/A
U10 VSS Ground N/A
U11 VDD Power N/A
U12 VSS Ground N/A
U13 VDD Power N/A
U14 VSS Ground N/A
U15 VDD Power N/A
U16 VSS Ground N/A
U17 VDD Power N/A
U18 VSS Ground N/A
U19 VDD Power N/A
U20 VSS Ground N/A
U21 NC NC N/A
U22 NC NC N/A
U23 NC NC N/A
U24 NC NC N/A
U25 SD_D_TX O SXPVDD
U26 SD_D_TX O SXPVDD
U27 SXCVSS Ground N/A
U28 SXCVDD Power N/A
V1 MVREF Power N/A
V2 VSS Ground N/A
V3 MA8 OGVDD
V4 MA2 OGVDD
V5 MA6 OGVDD
V6 MCKE1 OGVDD
V7 VSS Ground N/A
V8 GVDD Power N/A
V9 VSS Ground N/A
V10 VDD Power N/A
V11 VSS Ground N/A
V12 VDD Power N/A
V13 VSS Ground N/A
V14 VDD Power N/A
V15 VSS Ground N/A
V16 VDD Power N/A
V17 VSS Ground N/A
V18 VDD Power N/A
V19 VSS Ground N/A
V20 VDD Power N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 15
V21 NC NC N/A
V22 NC NC N/A
V23 NC NC N/A
V24 NC NC N/A
V25 NC NC N/A
V26 NC NC N/A
V27 SD_D_RX ISXCVDD
V28 SD_D_RX ISXCVDD
W1 VSS Ground N/A
W2 VSS Ground N/A
W3 MA5 OGVDD
W4 VSS Ground N/A
W5 GVDD Power N/A
W6 MMDIC1 I/O GVDD
W7 GVDD Power N/A
W8 VSS Ground N/A
W9 VDD Power N/A
W10 VSS Ground N/A
W11 M3VDD Power N/A
W12 VSS Ground N/A
W13 M3VDD Power N/A
W14 VSS Ground N/A
W15 M3VDD Power N/A
W16 VSS Ground N/A
W17 CPRIVDD Power N/A
W18 VSS Ground N/A
W19 VDD Power N/A
W20 VSS Ground N/A
W21 NC NC N/A
W22 NC NC N/A
W23 NC NC N/A
W24 SD_PLL1_AVDD Power N/A
W25 SD_PLL1_AGND Ground N/A
W26 NC NC N/A
W27 SXCVSS Ground N/A
W28 SXCVDD Power N/A
Y1 MA11 OGVDD
Y2 MA9 OGVDD
Y3 MA12 OGVDD
Y4 MA7 OGVDD
Y5 NC Non-user N/A
Y6 MMDIC0 I/O GVDD
Y7 VSS Ground N/A
Y8 GVDD Power N/A
Y9 VSS Ground N/A
Y10 VDD Power N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor16
Y11 VSS Ground N/A
Y12 M3VDD Power N/A
Y13 VSS Ground N/A
Y14 M3VDD Power N/A
Y15 VSS Ground N/A
Y16 CPRIVDD Power N/A
Y17 VSS Ground N/A
Y18 CPRIVDD Power N/A
Y19 VSS Ground N/A
Y20 VDD Power N/A
Y21 NC NC N/A
Y22 NC NC N/A
Y23 NC NC N/A
Y24 NC NC N/A
Y25 NC NC N/A
Y26 NC NC N/A
Y27 SD_REF_CLK1 ISXCVDD
Y28 SD_REF_CLK1 ISXCVDD
AA1 MDQS8 I/O GVDD
AA2 VSS Ground N/A
AA3 MA14 OGVDD
AA4 GVDD Power N/A
AA5 VSS Ground N/A
AA6 MA15 OGVDD
AA7 MCKE0 OGVDD
AA8 VSS Ground N/A
AA9 GVDD Power N/A
AA10 VSS Ground N/A
AA11 M3VDD Power N/A
AA12 VSS Ground N/A
AA13 M3VDD Power N/A
AA14 VSS Ground N/A
AA15 CPRIVDD Power N/A
AA16 VSS Ground N/A
AA17 CPRIVDD Power N/A
AA18 VSS Ground N/A
AA19 CPRIVDD Power N/A
AA20 NC NC N/A
AA21 SD_IMP_CAL_TX I SXPVDD
AA22 NC NC N/A
AA23 NC NC N/A
AA24 NC NC N/A
AA25 SD_E_TX O SXPVDD
AA26 SD_E_TX O SXPVDD
AA27 SXCVSS Ground N/A
AA28 SXCVDD Power N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 17
AB1 MDQS8 I/O GVDD
AB2 MDM8 OGVDD
AB3 MECC2 I/O GVDD
AB4 MECC1 I/O GVDD
AB5 NC Non-user N/A
AB6 MAPAR_IN IGVDD
AB7 MBA2 OGVDD
AB8 MDQ2 I/O GVDD
AB9 MDQ1 I/O GVDD
AB10 MDQ0 I/O GVDD
AB11 VSS Ground N/A
AB12 M3VDD Power N/A
AB13 VSS Ground N/A
AB14 M3VDD Power N/A
AB15 VSS Ground N/A
AB16 CPRIVDD Power N/A
AB17 VSS Ground N/A
AB18 CPRIVDD Power N/A
AB19 NC NC N/A
AB20 NC Non-user N/A
AB21 NC NC N/A
AB22 NC NC N/A
AB23 NC NC N/A
AB24 NC NC N/A
AB25 SXPVDD Power N/A
AB26 SXPVSS Ground N/A
AB27 SD_E_RX ISXCVDD
AB28 SD_E_RX ISXCVDD
AC1 VSS Ground N/A
AC2 GVDD Power N/A
AC3 MECC4 I/O GVDD
AC4 VSS Ground N/A
AC5 GVDD Power N/A
AC6 MDQ25 I/O GVDD
AC7 VSS Ground N/A
AC8 GVDD Power N/A
AC9 MDQ3 I/O GVDD
AC10 VSS Ground N/A
AC11 GVDD Power N/A
AC12 VSS Ground N/A
AC13 M3VDD Power N/A
AC14 VSS Ground N/A
AC15 CPRIVDD Power N/A
AC16 VSS Ground N/A
AC17 NC NC N/A
AC18 NC NC N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor18
AC19 NC NC N/A
AC20 NC Non-user N/A
AC21 NC NC N/A
AC22 NC NC N/A
AC23 NC NC N/A
AC24 NC NC N/A
AC25 SD_F_TX O SXPVDD
AC26 SD_F_TX O SXPVDD
AC27 SXCVSS Ground N/A
AC28 SXCVDD Power N/A
AD1 MECC7 I/O GVDD
AD2 MECC6 I/O GVDD
AD3 MECC0 I/O GVDD
AD4 MECC5 I/O GVDD
AD5 MECC3 I/O GVDD
AD6 MDQ24 I/O GVDD
AD7 MDM0 OGVDD
AD8 MDQS0 I/O GVDD
AD9 MDQS0 I/O GVDD
AD10 MDQ4 I/O GVDD
AD11 MDQ6 I/O GVDD
AD12 VSS Non-user N/A
AD13 VSS Non-user N/A
AD14 VSS Non-user N/A
AD15 VSS Ground N/A
AD16 VSS Ground N/A
AD17 NC NC N/A
AD18 SD_PLL2_AVDD Power N/A
AD19 NC NC N/A
AD20 NC NC N/A
AD21 NC NC N/A
AD22 NC NC N/A
AD23 NC NC N/A
AD24 NC NC N/A
AD25 SXPVDD Power N/A
AD26 SXPVSS Ground N/A
AD27 SD_F_RX ISXCVDD
AD28 SD_F_RX ISXCVDD
AE1 MDQS2 I/O GVDD
AE2 VSS Ground N/A
AE3 MDQ18 I/O GVDD
AE4 GVDD Power N/A
AE5 VSS Ground N/A
AE6 MDQ29 I/O GVDD
AE7 GVDD Power N/A
AE8 VSS Ground N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 19
AE9 MDQ5 I/O GVDD
AE10 GVDD Power N/A
AE11 VSS Ground N/A
AE12 MDQ9 I/O GVDD
AE13 VSS Non-user N/A
AE14 VSS Ground N/A
AE15 VSS Ground N/A
AE16 VSS Ground N/A
AE17 NC NC N/A
AE18 SD_PLL2_AGND Ground N/A
AE19 NC NC N/A
AE20 SD_J_TX O SXPVDD
AE21 SXPVDD Power N/A
AE22 SD_I_TX O SXPVDD
AE23 SXPVDD Power N/A
AE24 NC NC N/A
AE25 SD_G_TX O SXPVDD
AE26 SD_G_TX O SXPVDD
AE27 SXCVSS Ground N/A
AE28 SXCVDD Power N/A
AF1 MDQS2 I/O GVDD
AF2 MDQ17 I/O GVDD
AF3 MDQ21 I/O GVDD
AF4 MDQ16 I/O GVDD
AF5 MDQ30 I/O GVDD
AF6 MDQ27 I/O GVDD
AF7 MDQ28 I/O GVDD
AF8 MDQ7 I/O GVDD
AF9 MDQ14 I/O GVDD
AF10 MDQ11 I/O GVDD
AF11 MDQ8 I/O GVDD
AF12 MDQ10 I/O GVDD
AF13 VSS Non-user N/A
AF14 VSS Ground N/A
AF15 VSS Ground N/A
AF16 VSS Ground N/A
AF17 NC NC N/A
AF18 NC NC N/A
AF19 NC NC N/A
AF20 SD_J_TX O SXPVDD
AF21 SXPVSS Ground N/A
AF22 SD_I_TX O SXPVDD
AF23 SXPVSS Ground N/A
AF24 NC NC N/A
AF25 SXPVDD Power N/A
AF26 SXPVSS Ground N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor20
AF27 SD_G_RX ISXCVDD
AF28 SD_G_RX ISXCVDD
AG1 VSS Ground N/A
AG2 GVDD Power N/A
AG3 MDQ22 I/O GVDD
AG4 VSS Ground N/A
AG5 GVDD Power N/A
AG6 MDQ26 I/O GVDD
AG7 VSS Ground N/A
AG8 GVDD Power N/A
AG9 MDQ13 I/O GVDD
AG10 VSS Ground N/A
AG11 GVDD Power N/A
AG12 MDQ12 I/O GVDD
AG13 VSS Ground N/A
AG14 VSS Ground N/A
AG15 VSS Ground N/A
AG16 VSS Ground N/A
AG17 NC NC N/A
AG18 SXCVSS Ground N/A
AG19 SD_REF_CLK2 ISXCVDD
AG20 SXCVSS Ground N/A
AG21 SD_J_RX ISXCVDD
AG22 SXCVSS Ground N/A
AG23 SD_I_RX ISXCVDD
AG24 SXCVSS Ground N/A
AG25 SD_H_TX O SXPVDD
AG26 SD_H_TX O SXPVDD
AG27 SXCVSS Ground N/A
AG28 SXCVDD Power N/A
AH1 MDQ20 I/O GVDD
AH2 MDQ19 I/O GVDD
AH3 MDQ23 I/O GVDD
AH4 MDM2 OGVDD
AH5 MDQS3 I/O GVDD
AH6 MDQS3 I/O GVDD
AH7 MDM3 OGVDD
AH8 MDQ31 I/O GVDD
AH9 MDQS1 I/O GVDD
AH10 MDQS1 I/O GVDD
AH11 MDQ15 I/O GVDD
AH12 MDM1 OGVDD
AH13 VSS Ground N/A
AH14 PLL0_AVDD Power N/A
AH15 PLL1_AVDD Power N/A
AH16 PLL2_AVDD Power N/A
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 21
AH17 NC NC N/A
AH18 SXCVDD Power N/A
AH19 SD_REF_CLK2 ISXCVDD
AH20 SXCVDD Power N/A
AH21 SD_J_RX ISXCVDD
AH22 SXCVDD Power N/A
AH23 SD_I_RX ISXCVDD
AH24 SXCVDD Power N/A
AH25 SXPVDD Power N/A
AH26 SXPVSS Ground N/A
AH27 SD_H_RX ISXCVDD
AH28 SD_H_RX ISXCVDD
Notes: 1. Signal function during power-on reset is determined by the RCW source type. Selection of RapidIO, CPRI, and SGMII
functionality during normal operation is confi gured by the RCW bit values. Selection of the GPIO function and other functions
is done by GPIO register setup. For signals with GPIO functionality, the open-drain and internal 20 KΩ pull-up resistor can be
configured by GPIO register programming. For configuration details, see the GPIO chapter in the MSC8158E Reference
Manual.
2. NC signals should be disconnected for compatibility with future rev isions of the device. Non-user signals are reserved for
manufacturing and test purposes only. The assigned signal nam e is used to indicate whether the signal must be
unconnected (Reserved), pulled down (VSS or SXCVSS), or pulled up (VDD).
3. Pin types are: Ground = all VSS connections; Power = all VDD connections; I = Input; O = Output; I/O = Input/Output; NC =
not connected; non-user = connect as specified under Signal Name.
4. Connect power inputs to the power supplies via external filters. See the MSC8157 Design Checklist (AN4110) for details.
Table 2. Signal List by Primary Signal Name
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
A18 CLKIN IQVDD
A13 CLKOUT OQVDD
AA15 CPRIVDD Power N/A
AA17 CPRIVDD Power N/A
AA19 CPRIVDD Power N/A
AB16 CPRIVDD Power N/A
AB18 CPRIVDD Power N/A
AC15 CPRIVDD Power N/A
W17 CPRIVDD Power N/A
Y16 CPRIVDD Power N/A
Y18 CPRIVDD Power N/A
N11 CRPEVDD Power N/A
N7 CRPEVDD Power N/A
N9 CRPEVDD Power N/A
P10 CRPEVDD Power N/A
P8 CRPEVDD Power N/A
R11 CRPEVDD Power N/A
C16 DFT_TEST IQVDD
A14 EE0 IQVDD
C14 EE1 OQVDD
Table 1. Signal List by Ball Number (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor22
B26 GE_MDC ONVDD
C27 GE_MDIO I/O NVDD
A23 GE1_GTX_CLK ONVDD
H22 GE1_RD0 INVDD
H24 GE1_RD1 INVDD
G21 GE1_RD2 INVDD
G20 GE1_RD3 INVDD
G22 GE1_RX_CLK INVDD
G24 GE1_RX_CTL INVDD
A24 GE1_TD0 ONVDD
A27 GE1_TD1 ONVDD
A26 GE1_TD2 ONVDD
A28 GE1_TD3 ONVDD
A25 GE1_TX_CLK INVDD
A22 GE1_TX_CTL ONVDD
C21 GE2_GTX_CLK/CP_LOS4 I/O NVDD
F21 GE2_RD0/CP_LOS6 I NVDD
F23 GE2_RD1 INVDD
F19 GE2_RD2/CP_LOS1 I NVDD
E20 GE2_RD3/CP_LOS2 I NVDD
F22 GE2_RX_CLK INVDD
F20 GE2_RX_CTL INVDD
C24 GE2_TD0 ONVDD
C23 GE2_TD1 ONVDD
C20 GE2_TD2/CP_LOS3 I/O NVDD
D22 GE2_TD3/CP_LOS5 I/O NVDD
B20 GE2_TX_CLK INVDD
C22 GE2_TX_CTL ONVDD
E26 GPIO0/IRQ0/RC0/CP_SYNC1 I/O NVDD
E28 GPIO1/IRQ1/RC1/CP_SYNC2 I/O NVDD
D28 GPIO10/IRQ10/RC10 I/O NVDD
G28 GPIO11/IRQ11/RC11 I/O NVDD
H28 GPIO12/IRQ12/RC12 I/O NVDD
D20 GPIO13/IRQ13/RC13 I/O NVDD
H26 GPIO14/DRQ0/IRQ14/RC14 I/O NVDD
C19 GPIO15/DDN0/IRQ15/RC15 I/O NVDD
D26 GPIO16/TMR5/RC16 I/O NVDD
E27 GPIO17/SPI_SCK/CP_LOS3 I/O NVDD
B28 GPIO18/SPI_MOSI/CP_LOS4 I/O NVDD
G26 GPIO19/SPI_MISO/CP_LOS5 I/O NVDD
K28 GPIO2/IRQ2/RC2/CP_SYNC3 I/O NVDD
C26 GPIO20/SPI_SL/CP_LOS6 I/O NVDD
C28 GPIO21/TMR6 I/O NVDD
F26 GPIO22 I/O NVDD
F27 GPIO23/TMR0/BOOT_SPI_SL I/O NVDD
J22 GPIO24/TMR1/RCW_SRC2 I/O NVDD
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 23
B24 GPIO25/TMR2/RCW_SRC1 I/O NVDD
F24 GPIO26/TMR3 I/O NVDD
E24 GPIO27/TMR4/RCW_SRC0 I/O NVDD
G19 GPIO28/UART_RXD/CP_LOS1 I/O NVDD
A20 GPIO29/UART_TXD/CP_LOS2 I/O NVDD
J28 GPIO3/DRQ1/IRQ3/RC3 I/O NVDD
C25 GPIO30/I2C_SCL I/O NVDD
A21 GPIO31/I2C_SDA I/O NVDD
K22 GPIO4/DDN1/IRQ4/RC4 I/O NVDD
D24 GPIO5/IRQ5/RC5/CP_SYNC4 I/O NVDD
F25 GPIO6/IRQ6/RC6/CP_SYNC5 I/O NVDD
K26 GPIO7/IRQ7/RC7/CP_SYNC6 I/O NVDD
F28 GPIO8/IRQ8/RC8 I/O NVDD
J23 GPIO9/IRQ9/RC9 I/O NVDD
A4 GVDD Power N/A
A7 GVDD Power N/A
AA4 GVDD Power N/A
AA9 GVDD Power N/A
AC11 GVDD Power N/A
AC2 GVDD Power N/A
AC5 GVDD Power N/A
AC8 GVDD Power N/A
AE10 GVDD Power N/A
AE4 GVDD Power N/A
AE7 GVDD Power N/A
AG11 GVDD Power N/A
AG2 GVDD Power N/A
AG5 GVDD Power N/A
AG8 GVDD Power N/A
C2 GVDD Power N/A
C5 GVDD Power N/A
E4 GVDD Power N/A
E7 GVDD Power N/A
G2 GVDD Power N/A
G5 GVDD Power N/A
J4 GVDD Power N/A
L2 GVDD Power N/A
L5 GVDD Power N/A
N4 GVDD Power N/A
R2 GVDD Power N/A
R5 GVDD Power N/A
R7 GVDD Power N/A
T8 GVDD Power N/A
U4 GVDD Power N/A
U7 GVDD Power N/A
V8 GVDD Power N/A
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor24
W5 GVDD Power N/A
W7 GVDD Power N/A
Y8 GVDD Power N/A
E16 HRESET I/O QVDD
D17 HRESET_IN IQVDD
E15 INT_OUT/CP_TX_INT OQVDD
AA11 M3VDD Power N/A
AA13 M3VDD Power N/A
AB12 M3VDD Power N/A
AB14 M3VDD Power N/A
AC13 M3VDD Power N/A
W11 M3VDD Power N/A
W13 M3VDD Power N/A
W15 M3VDD Power N/A
Y12 M3VDD Power N/A
Y14 M3VDD Power N/A
R3 MA0 OGVDD
T4 MA1 OGVDD
P2 MA10 OGVDD
Y1 MA11 OGVDD
Y3 MA12 OGVDD
M3 MA13 OGVDD
AA3 MA14 OGVDD
AA6 MA15 OGVDD
V4 MA2 OGVDD
T5 MA3 OGVDD
P4 MA4 OGVDD
W3 MA5 OGVDD
V5 MA6 OGVDD
Y4 MA7 OGVDD
V3 MA8 OGVDD
Y2 MA9 OGVDD
AB6 MAPAR_IN IGVDD
T6 MAPAR_OUT OGVDD
U1 MAVDD Power N/A
R6 MBA0 OGVDD
U6 MBA1 OGVDD
AB7 MBA2 OGVDD
K1 MCAS OGVDD
M1 MCK0 OGVDD
M2 MCK0 OGVDD
T3 MCK1 OGVDD
U3 MCK1 OGVDD
P1 MCK2 OGVDD
R1 MCK2 OGVDD
AA7 MCKE0 OGVDD
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 25
V6 MCKE1 OGVDD
A16 MCLKIN (optional) I QVDD
K2 MCS0 OGVDD
K3 MCS1 OGVDD
AD7 MDM0 OGVDD
AH12 MDM1 OGVDD
AH4 MDM2 OGVDD
AH7 MDM3 OGVDD
L6 MDM4 OGVDD
G3 MDM5 OGVDD
F7 MDM6 OGVDD
C6 MDM7 OGVDD
AB2 MDM8 OGVDD
AB10 MDQ0 I/O GVDD
AB9 MDQ1 I/O GVDD
AF12 MDQ10 I/O GVDD
AF10 MDQ11 I/O GVDD
AG12 MDQ12 I/O GVDD
AG9 MDQ13 I/O GVDD
AF9 MDQ14 I/O GVDD
AH11 MDQ15 I/O GVDD
AF4 MDQ16 I/O GVDD
AF2 MDQ17 I/O GVDD
AE3 MDQ18 I/O GVDD
AH2 MDQ19 I/O GVDD
AB8 MDQ2 I/O GVDD
AH1 MDQ20 I/O GVDD
AF3 MDQ21 I/O GVDD
AG3 MDQ22 I/O GVDD
AH3 MDQ23 I/O GVDD
AD6 MDQ24 I/O GVDD
AC6 MDQ25 I/O GVDD
AG6 MDQ26 I/O GVDD
AF6 MDQ27 I/O GVDD
AF7 MDQ28 I/O GVDD
AE6 MDQ29 I/O GVDD
AC9 MDQ3 I/O GVDD
AF5 MDQ30 I/O GVDD
AH8 MDQ31 I/O GVDD
K5 MDQ32 I/O GVDD
J5 MDQ33 I/O GVDD
K6 MDQ34 I/O GVDD
J3 MDQ35 I/O GVDD
J6 MDQ36 I/O GVDD
J1 MDQ37 I/O GVDD
H1 MDQ38 I/O GVDD
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor26
K4 MDQ39 I/O GVDD
AD10 MDQ4 I/O GVDD
F1 MDQ40 I/O GVDD
F2 MDQ41 I/O GVDD
H6 MDQ42 I/O GVDD
F5 MDQ43 I/O GVDD
H4 MDQ44 I/O GVDD
H5 MDQ45 I/O GVDD
G6 MDQ46 I/O GVDD
F6 MDQ47 I/O GVDD
D2 MDQ48 I/O GVDD
D1 MDQ49 I/O GVDD
AE9 MDQ5 I/O GVDD
D5 MDQ50 I/O GVDD
D6 MDQ51 I/O GVDD
D7 MDQ52 I/O GVDD
E1 MDQ53 I/O GVDD
E6 MDQ54 I/O GVDD
E3 MDQ55 I/O GVDD
B7 MDQ56 I/O GVDD
A3 MDQ57 I/O GVDD
B6 MDQ58 I/O GVDD
B2 MDQ59 I/O GVDD
AD11 MDQ6 I/O GVDD
B1 MDQ60 I/O GVDD
C3 MDQ61 I/O GVDD
B5 MDQ62 I/O GVDD
A6 MDQ63 I/O GVDD
AF8 MDQ7 I/O GVDD
AF11 MDQ8 I/O GVDD
AE12 MDQ9 I/O GVDD
AD8 MDQS0 I/O GVDD
AD9 MDQS0 I/O GVDD
AH10 MDQS1 I/O GVDD
AH9 MDQS1 I/O GVDD
AE1 MDQS2 I/O GVDD
AF1 MDQS2 I/O GVDD
AH5 MDQS3 I/O GVDD
AH6 MDQS3 I/O GVDD
H2 MDQS4 I/O GVDD
H3 MDQS4 I/O GVDD
F3 MDQS5 I/O GVDD
F4 MDQS5 I/O GVDD
D3 MDQS6 I/O GVDD
D4 MDQS6 I/O GVDD
B3 MDQS7 I/O GVDD
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 27
B4 MDQS7 I/O GVDD
AA1 MDQS8 I/O GVDD
AB1 MDQS8 I/O GVDD
AD3 MECC0 I/O GVDD
AB4 MECC1 I/O GVDD
AB3 MECC2 I/O GVDD
AD5 MECC3 I/O GVDD
AC3 MECC4 I/O GVDD
AD4 MECC5 I/O GVDD
AD2 MECC6 I/O GVDD
AD1 MECC7 I/O GVDD
Y6 MMDIC0 I/O GVDD
W6 MMDIC1 I/O GVDD
P6 MODT0 OGVDD
N6 MODT1 OGVDD
N1 MRAS OGVDD
V1 MVREF Power N/A
M4 MWE OGVDD
A10 NC Non-user N/A
A11 NC Non-user N/A
A12 NC Non-user N/A
A8 NC Non-user N/A
A9 NC Non-user N/A
AA20 NC NC N/A
AA22 NC NC N/A
AA23 NC NC N/A
AA24 NC NC N/A
AB19 NC NC N/A
AB20 NC Non-user N/A
AB21 NC NC N/A
AB22 NC NC N/A
AB23 NC NC N/A
AB24 NC NC N/A
AB5 NC Non-user N/A
AC17 NC NC N/A
AC18 NC NC N/A
AC19 NC NC N/A
AC20 NC Non-user N/A
AC21 NC NC N/A
AC22 NC NC N/A
AC23 NC NC N/A
AC24 NC NC N/A
AD17 NC NC N/A
AD19 NC NC N/A
AD20 NC NC N/A
AD21 NC NC N/A
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor28
AD22 NC NC N/A
AD23 NC NC N/A
AD24 NC NC N/A
AE17 NC NC N/A
AE19 NC NC N/A
AE24 NC NC N/A
AF17 NC NC N/A
AF18 NC NC N/A
AF19 NC NC N/A
AF24 NC NC N/A
AG17 NC NC N/A
AH17 NC NC N/A
B10 NC Non-user N/A
B12 NC Non-user N/A
B8 NC Non-user N/A
C10 NC Non-user N/A
C11 NC Non-user N/A
C12 NC Non-user N/A
C13 NC Non-user N/A
C15 NC Non-user N/A
C8 NC Non-user N/A
C9 NC Non-user N/A
D10 NC Non-user N/A
D12 NC Non-user N/A
D14 NC Non-user N/A
D8 NC Non-user N/A
E10 NC Non-user N/A
E11 NC Non-user N/A
E12 NC Non-user N/A
E13 NC Non-user N/A
E14 NC Non-user N/A
E9 NC Non-user N/A
F11 NC Non-user N/A
F12 NC Non-user N/A
F14 NC Non-user N/A
G11 NC Non-user N/A
G12 NC Non-user N/A
G13 NC Non-user N/A
G14 NC Non-user N/A
H13 NC Non-user N/A
L22 NC NC N/A
L23 NC NC N/A
L3 NC Non-user N/A
M21 NC NC N/A
M22 NC NC N/A
M23 NC Non-user N/A
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 29
M24 NC Non-user N/A
M5 NC Non-user N/A
M6 NC Non-user N/A
N21 NC NC N/A
N22 NC NC N/A
N25 NC Non-user N/A
N26 NC Non-user N/A
N3 NC Non-user N/A
P21 NC NC N/A
P23 NC NC N/A
P24 NC NC N/A
P3 NC Non-user N/A
P5 NC Non-user N/A
R21 NC NC N/A
R22 NC NC N/A
R23 NC NC N/A
R24 NC NC N/A
T21 NC NC N/A
T22 NC Non-user N/A
T23 NC Non-user N/A
T24 NC NC N/A
U21 NC NC N/A
U22 NC NC N/A
U23 NC NC N/A
U24 NC NC N/A
V21 NC NC N/A
V22 NC NC N/A
V23 NC NC N/A
V24 NC NC N/A
V25 NC NC N/A
V26 NC NC N/A
W21 NC NC N/A
W22 NC NC N/A
W23 NC NC N/A
W26 NC NC N/A
Y21 NC NC N/A
Y22 NC NC N/A
Y23 NC NC N/A
Y24 NC NC N/A
Y25 NC NC N/A
Y26 NC NC N/A
Y5 NC Non-user N/A
D15 NMI IQVDD
F15 NMI_OUT/CP_RX_INT OQVDD
B22 NVDD Power N/A
D21 NVDD Power N/A
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor30
D25 NVDD Power N/A
E19 NVDD Power N/A
E23 NVDD Power N/A
G25 NVDD Power N/A
H20 NVDD Power N/A
H23 NVDD Power N/A
H27 NVDD Power N/A
J21 NVDD Power N/A
K25 NVDD Power N/A
L21 NVDD Power N/A
AH14 PLL0_AVDD Power N/A
AH15 PLL1_AVDD Power N/A
AH16 PLL2_AVDD Power N/A
C17 PORESET IQVDD
G15 QVDD Power N/A
H14 QVDD Power N/A
J27 RC21 INVDD
J24 RCW_LSEL0/RC17 I/O NVDD
K24 RCW_LSEL1/RC18 I/O NVDD
J26 RCW_LSEL2/RC19 I/O NVDD
J25 RCW_LSEL3/RC20 I/O NVDD
T27 SD_C_RX ISXCVDD
T28 SD_C_RX ISXCVDD
R25 SD_C_TX O SXPVDD
R26 SD_C_TX O SXPVDD
V27 SD_D_RX ISXCVDD
V28 SD_D_RX ISXCVDD
U25 SD_D_TX O SXPVDD
U26 SD_D_TX O SXPVDD
AB27 SD_E_RX ISXCVDD
AB28 SD_E_RX ISXCVDD
AA25 SD_E_TX O SXPVDD
AA26 SD_E_TX O SXPVDD
AD27 SD_F_RX ISXCVDD
AD28 SD_F_RX ISXCVDD
AC25 SD_F_TX O SXPVDD
AC26 SD_F_TX O SXPVDD
AF27 SD_G_RX ISXCVDD
AF28 SD_G_RX ISXCVDD
AE25 SD_G_TX O SXPVDD
AE26 SD_G_TX O SXPVDD
AH27 SD_H_RX ISXCVDD
AH28 SD_H_RX ISXCVDD
AG25 SD_H_TX O SXPVDD
AG26 SD_H_TX O SXPVDD
AG23 SD_I_RX ISXCVDD
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 31
AH23 SD_I_RX ISXCVDD
AE22 SD_I_TX O SXPVDD
AF22 SD_I_TX O SXPVDD
P22 SD_IMP_CAL_RX I SXCVDD
AA21 SD_IMP_CAL_TX I SXPVDD
AG21 SD_J_RX ISXCVDD
AH21 SD_J_RX ISXCVDD
AE20 SD_J_TX O SXPVDD
AF20 SD_J_TX O SXPVDD
W25 SD_PLL1_AGND Ground N/A
W24 SD_PLL1_AVDD Power N/A
AE18 SD_PLL2_AGND Ground N/A
AD18 SD_PLL2_AVDD Power N/A
Y27 SD_REF_CLK1 ISXCVDD
Y28 SD_REF_CLK1 ISXCVDD
AG19 SD_REF_CLK2 ISXCVDD
AH19 SD_REF_CLK2 ISXCVDD
G16 STOP_BS IQVDD
AA28 SXCVDD Power N/A
AC28 SXCVDD Power N/A
AE28 SXCVDD Power N/A
AG28 SXCVDD Power N/A
AH18 SXCVDD Power N/A
AH20 SXCVDD Power N/A
AH22 SXCVDD Power N/A
AH24 SXCVDD Power N/A
L28 SXCVDD Power N/A
N28 SXCVDD Power N/A
R28 SXCVDD Power N/A
U28 SXCVDD Power N/A
W28 SXCVDD Power N/A
AA27 SXCVSS Ground N/A
AC27 SXCVSS Ground N/A
AE27 SXCVSS Ground N/A
AG18 SXCVSS Ground N/A
AG20 SXCVSS Ground N/A
AG22 SXCVSS Ground N/A
AG24 SXCVSS Ground N/A
AG27 SXCVSS Ground N/A
L27 SXCVSS Ground N/A
N27 SXCVSS Ground N/A
R27 SXCVSS Ground N/A
U27 SXCVSS Ground N/A
W27 SXCVSS Ground N/A
M27 SXCVSS (not a ground pin) Non-user N/A
M28 SXCVSS (not a ground pin) Non-user N/A
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor32
P27 SXCVSS (not a ground pin) Non-user N/A
P28 SXCVSS (not a ground pin) Non-user N/A
AB25 SXPVDD Power N/A
AD25 SXPVDD Power N/A
AE21 SXPVDD Power N/A
AE23 SXPVDD Power N/A
AF25 SXPVDD Power N/A
AH25 SXPVDD Power N/A
M25 SXPVDD Power N/A
N23 SXPVDD Power N/A
P25 SXPVDD Power N/A
T25 SXPVDD Power N/A
AB26 SXPVSS Ground N/A
AD26 SXPVSS Ground N/A
AF21 SXPVSS Ground N/A
AF23 SXPVSS Ground N/A
AF26 SXPVSS Ground N/A
AH26 SXPVSS Ground N/A
M26 SXPVSS Ground N/A
N24 SXPVSS Ground N/A
P26 SXPVSS Ground N/A
T26 SXPVSS Ground N/A
E17 TCK IQVDD
F17 TDI IQVDD
B14 TDO OQVDD
B15 TMS IQVDD
G17 TRST IQVDD
F10 VDD Power N/A
F8 VDD Power N/A
G7 VDD Power N/A
G9 VDD Power N/A
H10 VDD Power N/A
H16 VDD Power N/A
H18 VDD Power N/A
H8 VDD Power N/A
J11 VDD Power N/A
J13 VDD Power N/A
J15 VDD Power N/A
J17 VDD Power N/A
J19 VDD Power N/A
J7 VDD Power N/A
J9 VDD Power N/A
K10 VDD Power N/A
K12 VDD Power N/A
K14 VDD Power N/A
K16 VDD Power N/A
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 33
K18 VDD Power N/A
K20 VDD Power N/A
K8 VDD Power N/A
L11 VDD Power N/A
L13 VDD Power N/A
L15 VDD Power N/A
L17 VDD Power N/A
L19 VDD Power N/A
L7 VDD Power N/A
L9 VDD Power N/A
M10 VDD Power N/A
M12 VDD Power N/A
M14 VDD Power N/A
M16 VDD Power N/A
M18 VDD Power N/A
M20 VDD Power N/A
M8 VDD Power N/A
N13 VDD Power N/A
N15 VDD Power N/A
N17 VDD Power N/A
N19 VDD Power N/A
P12 VDD Power N/A
P14 VDD Power N/A
P16 VDD Power N/A
P18 VDD Power N/A
P20 VDD Power N/A
R13 VDD Power N/A
R15 VDD Power N/A
R17 VDD Power N/A
R19 VDD Power N/A
R9 VDD Power N/A
T10 VDD Power N/A
T12 VDD Power N/A
T14 VDD Power N/A
T16 VDD Power N/A
T18 VDD Power N/A
T20 VDD Power N/A
U11 VDD Power N/A
U13 VDD Power N/A
U15 VDD Power N/A
U17 VDD Power N/A
U19 VDD Power N/A
U9 VDD Power N/A
V10 VDD Power N/A
V12 VDD Power N/A
V14 VDD Power N/A
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor34
V16 VDD Power N/A
V18 VDD Power N/A
V20 VDD Power N/A
W19 VDD Power N/A
W9 VDD Power N/A
Y10 VDD Power N/A
Y20 VDD Power N/A
A15 VSS Ground N/A
A17 VSS Ground N/A
A19 VSS Ground N/A
A2 VSS Ground N/A
A5 VSS Ground N/A
AA10 VSS Ground N/A
AA12 VSS Ground N/A
AA14 VSS Ground N/A
AA16 VSS Ground N/A
AA18 VSS Ground N/A
AA2 VSS Ground N/A
AA5 VSS Ground N/A
AA8 VSS Ground N/A
AB11 VSS Ground N/A
AB13 VSS Ground N/A
AB15 VSS Ground N/A
AB17 VSS Ground N/A
AC1 VSS Ground N/A
AC10 VSS Ground N/A
AC12 VSS Ground N/A
AC14 VSS Ground N/A
AC16 VSS Ground N/A
AC4 VSS Ground N/A
AC7 VSS Ground N/A
AD12 VSS Non-user N/A
AD13 VSS Non-user N/A
AD14 VSS Non-user N/A
AD15 VSS Ground N/A
AD16 VSS Ground N/A
AE11 VSS Ground N/A
AE13 VSS Non-user N/A
AE14 VSS Ground N/A
AE15 VSS Ground N/A
AE16 VSS Ground N/A
AE2 VSS Ground N/A
AE5 VSS Ground N/A
AE8 VSS Ground N/A
AF13 VSS Non-user N/A
AF14 VSS Ground N/A
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 35
AF15 VSS Ground N/A
AF16 VSS Ground N/A
AG1 VSS Ground N/A
AG10 VSS Ground N/A
AG13 VSS Ground N/A
AG14 VSS Ground N/A
AG15 VSS Ground N/A
AG16 VSS Ground N/A
AG4 VSS Ground N/A
AG7 VSS Ground N/A
AH13 VSS Ground N/A
B11 VSS Ground N/A
B13 VSS Ground N/A
B16 VSS Ground N/A
B17 VSS Ground N/A
B18 VSS Ground N/A
B19 VSS Ground N/A
B21 VSS Ground N/A
B23 VSS Ground N/A
B25 VSS Ground N/A
B27 VSS Ground N/A
B9 VSS Ground N/A
C1 VSS Ground N/A
C18 VSS Ground N/A
C4 VSS Ground N/A
C7 VSS Ground N/A
D11 VSS Ground N/A
D13 VSS Ground N/A
D16 VSS Ground N/A
D18 VSS Ground N/A
D19 VSS Non-user N/A
D23 VSS Ground N/A
D9 VSS Ground N/A
E18 VSS Ground N/A
E2 VSS Ground N/A
E21 VSS Ground N/A
E22 VSS Non-user N/A
E25 VSS Ground N/A
E5 VSS Ground N/A
E8 VSS Ground N/A
F13 VSS Ground N/A
F16 VSS Ground N/A
F18 VSS Ground N/A
F9 VSS Ground N/A
G1 VSS Ground N/A
G10 VSS Ground N/A
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor36
G18 VSS Ground N/A
G23 VSS Ground N/A
G27 VSS Ground N/A
G4 VSS Ground N/A
G8 VSS Ground N/A
H11 VSS Ground N/A
H12 VSS Non-user N/A
H15 VSS Ground N/A
H17 VSS Ground N/A
H19 VSS Ground N/A
H21 VSS Ground N/A
H25 VSS Ground N/A
H7 VSS Ground N/A
H9 VSS Ground N/A
J10 VSS Ground N/A
J12 VSS Ground N/A
J14 VSS Ground N/A
J16 VSS Ground N/A
J18 VSS Ground N/A
J2 VSS Ground N/A
J20 VSS Ground N/A
J8 VSS Ground N/A
K11 VSS Ground N/A
K13 VSS Ground N/A
K15 VSS Ground N/A
K17 VSS Ground N/A
K19 VSS Ground N/A
K21 VSS Ground N/A
K23 VSS Ground N/A
K27 VSS Ground N/A
K7 VSS Ground N/A
K9 VSS Ground N/A
L1 VSS Ground N/A
L10 VSS Ground N/A
L12 VSS Ground N/A
L14 VSS Ground N/A
L16 VSS Ground N/A
L18 VSS Ground N/A
L20 VSS Ground N/A
L24 VSS Non-user N/A
L25 VSS Non-user N/A
L26 VSS Non-user N/A
L4 VSS Ground N/A
L8 VSS Ground N/A
M11 VSS Ground N/A
M13 VSS Ground N/A
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Pin Assignment
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 37
M15 VSS Ground N/A
M17 VSS Ground N/A
M19 VSS Ground N/A
M7 VSS Ground N/A
M9 VSS Ground N/A
N10 VSS Ground N/A
N12 VSS Ground N/A
N14 VSS Ground N/A
N16 VSS Ground N/A
N18 VSS Ground N/A
N2 VSS Ground N/A
N20 VSS Ground N/A
N5 VSS Ground N/A
N8 VSS Ground N/A
P11 VSS Ground N/A
P13 VSS Ground N/A
P15 VSS Ground N/A
P17 VSS Ground N/A
P19 VSS Ground N/A
P7 VSS Ground N/A
P9 VSS Ground N/A
R10 VSS Ground N/A
R12 VSS Ground N/A
R14 VSS Ground N/A
R16 VSS Ground N/A
R18 VSS Ground N/A
R20 VSS Ground N/A
R4 VSS Ground N/A
R8 VSS Ground N/A
T1 VSS Ground N/A
T11 VSS Ground N/A
T13 VSS Ground N/A
T15 VSS Ground N/A
T17 VSS Ground N/A
T19 VSS Ground N/A
T2 VSS Ground N/A
T7 VSS Ground N/A
T9 VSS Ground N/A
U10 VSS Ground N/A
U12 VSS Ground N/A
U14 VSS Ground N/A
U16 VSS Ground N/A
U18 VSS Ground N/A
U2 VSS Ground N/A
U20 VSS Ground N/A
U5 VSS Ground N/A
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Pin Assignment
Freesca le Sem ico nd uctor38
U8 VSS Ground N/A
V11 VSS Ground N/A
V13 VSS Ground N/A
V15 VSS Ground N/A
V17 VSS Ground N/A
V19 VSS Ground N/A
V2 VSS Ground N/A
V7 VSS Ground N/A
V9 VSS Ground N/A
W1 VSS Ground N/A
W10 VSS Ground N/A
W12 VSS Ground N/A
W14 VSS Ground N/A
W16 VSS Ground N/A
W18 VSS Ground N/A
W2 VSS Ground N/A
W20 VSS Ground N/A
W4 VSS Ground N/A
W8 VSS Ground N/A
Y11 VSS Ground N/A
Y13 VSS Ground N/A
Y15 VSS Ground N/A
Y17 VSS Ground N/A
Y19 VSS Ground N/A
Y7 VSS Ground N/A
Y9 VSS Ground N/A
D27 VSS‘ Ground N/A
Notes: 1. Signal function during power-on reset is determined by the RCW source type. Selection of RapidIO, CPRI, and SGMII
functionality during normal operation is confi gured by the RCW bit values. Selection of the GPIO function and other functions
is done by GPIO register setup. For signals with GPIO functionality, the open-drain and internal 20 KΩ pull-up resistor can be
configured by GPIO register programming. For configuration details, see the GPIO chapter in the MSC8158E Reference
Manual.
2. NC signals should be disconnected for compatibility with future rev isions of the device. Non-user signals are reserved for
manufacturing and test purposes only. The assigned signal nam e is used to indicate whether the signal must be
unconnected (Reserved), pulled down (VSS or SXCVSS), or pulled up (VDD).
3. Pin types are: Ground = all VSS connections; Power = all VDD connections; I = Input; O = Output; I/O = Input/Output; NC =
not connected; non-user = connect as specified under Signal Name.
4. Connect power inputs to the power supplies via external filters. See the MSC8157 Design Checklist (AN4110) for details.
Table 2. Signal List by Primary Signal Name (continued)
Ball Number Signal Name1,2 Pin Type3Power Rail
Name
Electrical Characteri stics
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 39
2 Electrica l Characteristics
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications. For additional information, see the MSC8158E Reference Manual.
2.1 Maximum Ra tings
In calculat ing timi ng requir ements, adding a maximu m value o f one specification to a minimu m value of anoth er specification
does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values
in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction.
Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another
specification; adding a maximum to a minimum represents a condition that can never exist.
Table 3 describes the maximum electrical ratings for the MSC8158E.
Table 3. Absolute Maximum Ratings
Rating Power Rail Name Symbol Value Unit
Core supply voltage
• Cores 0–5
PLL supply voltage3
CRPE supply voltage
CPRI supply voltage
VDD
PLL0_AVDD
PLL1_AVDD
PLL2_AVDD
MAVDD
SD_PLL1_AVDD
SD_PLL2_AVDD
CRPEVDD
CPRIVDD
VDD
VDDPLL0
VDDPLL1
VDDPLL2
VDDPLLM
VDDPLL
VDDPLL
VDDCRPE
VDDCPRI
–0 .3 to 1 .1
–0 .3 to 1 .1
–0 .3 to 1 .1
–0 .3 to 1 .1
–0 .3 to 1 .1
–0 .3 to 1 .1
–0 .3 to 1 .1
–0 .3 to 1 .1
–0 .3 to 1 .1
V
V
V
V
V
V
V
V
V
M3 memory supply voltage M3VDD VDDM3 –0.3 to 1 .1 V
DDR memory supply voltage
DDR reference voltage
Input DDR voltage
GVDD
MVREF
VDDDDR
MVREF
VINDDR
–0.3 to 1.65
–0.3 to 0.51 × VDDDDR
–0.3 to VDDDDR + 0.3
V
V
V
I/O voltage excluding DDR and RapidIO lines
Input I/O voltage
NVDD, QVDD VDDIO
VINIO
–0.3 to 2.625
–0 .3 to VDDIO + 0.3
V
V
SerDes pad voltage SXPVDD VDDSXP –0.3 to 1.66 V
SerDes core voltage
SerDes PLL voltage3
Input SerDes I/O voltage
SXCVDD VDDSXC
VDDRIOPLL
VINRIO
–0.3 to 1.21
–0.3 to 1.21
–0.4 to VDDSXC + 0.3
V
V
V
Operating temperature TJ–40 to 105 °C
Storage temperature range TSTG –55 to +150 °C
Notes: 1. F unctional operating conditions are given in Table 4.
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the listed limits may affect device reliability or cause permanent damage.
3. PLL supply voltage is specified at input of the filter and not at pin of the MSC8158E (see the MSC8157 Design Checklist
(AN4110))
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Electrical Characteristics
Freesca le Sem ico nd uctor40
2.2 Recommended Operating Conditions
Table 4 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 4. Recommended Operating Conditions
Rating Supply Min Nominal Max Unit
Core supply voltage1VDD 0.97 1.0 1.05 V
PLL supply voltage1,3 PLL0_AVDD
PLL1_AVDD
PLL2_AVDD
MAVDD
SD_PLL1_AVDD
SD_PLL2_AVDD
0.97 1.0 1.05 V
CRPE supply voltage1CRPEVDD 0.97 1.0 1.05 V
CPRI supply voltage1CPRIVDD 0.97 1.0 1.05 V
Switchable M3 memory
supply voltage1M3VDD 0.97 1.0 1.05 V
DDR memory supply
voltage
DDR reference voltage
GVDD
MVREF
1.425
0.49 × GVDD (nom)
1.5
0.5 × GVDD (nom)
1.575
0.51 × GVDD (nom)
V
V
RGMII Ethernet and GPIO
supply voltage2 NVDD 2.375 2.5 2.625 V
Input/output clocks, reset
signal, and JTAG supply
voltage2
QVDD 2.375 2.5 2.625 V
SerDes pad supply voltage SXPVDD 1.425 1.5 1.575 V
SerDes core supply
voltage1SXCVDD 0.97 1.0 1.05 V
Operating temperature
range:
• Standard
• Extended TJ
TA
TJ
0
–40
—
105
—
105
°C
°C
°C
Notes: 1. Designates supplies that use the same 1.0 V nominal voltage level.
2. Designates supplies that use the same 2.5 V nominal voltage level.
3. PLL supply voltage is specified at the input of the filter and not at the MSC8158E pin for the supply.
Electrical Characteri stics
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 41
2.3 Thermal Characteristics
Table 5 describes thermal characteristics of the MSC8158E for the FC-PBGA packages.
2.4 CLKIN/MCLKIN Requirements
Table 6 summarizes the required characteristics for the CLKIN/MCLKIN signal.
2.5 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC8158E.
2.5.1 DDR SDRAM Electrical Characteristics
This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8 158E. Table 7 provides the
recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3 SDRAM.
Note: At recommended operating conditions (see Table 4) with GVDD =1.5V.
Table 5. Thermal Characteristics for the MSC8158E
Characteristic Symbol
FC-PBGA
29 × 29 mm2Unit
Natural
Convection 200 ft/min
(1 m/s) airflow
Junction-to-ambient1, 2 RθJA 18 12 °C/W
Junction-to-ambient , four-layer board1, 2 RθJA 13 9 °C/W
Junction-to-board (bottom)3RθJB 4°C/W
Junction-to-case4RθJC 0.4 °C/W
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESDC51-6. Thermal test board meets JEDEC
specification for the specified package.
3. Junction-to-board thermal resistance determined per JEDEC JESD 51-8. Thermal test board meets JEDEC specif ication for
the specified package.
4. Junction-to-case at the top of the package determined using MIL- STD-883 Method 1012.1. The cold plate temperature is used
for the case temperature. Reported value includes the thermal resistance of the interface layer
Table 6. CLKIN/MCLKIN Requirements
Parameter/Condition1Symbol Min Typ Max Unit Notes
CLKIN/MCLKIN duty cycle — 40 — 60 % 2
CLKIN/MCLKIN slew rate — 1 — 4 V/ns 3
CLKIN/MCLKIN peak period jitter — — — ±150 ps —
CLKIN/MCLKIN jitter phase noise at –56 dBc — — — 500 KHz 4
AC input swing limits ΔVAC 1.5 — — V —
Input capacitance CIN ——15pf 5
Notes: 1. For clock frequencies, see the Clock chapter in the MSC8158E Reference Manual.
2. Measured at the rising edge and/or the falling edge at VDDIO/2.
3. Slew rate as measured from ±20% to 80% of voltage swing at clock input.
4. Phase noise is calculated as FFT of TIE jitter.
5. The specified capacitance is not an exte rnal requireme nt. It represents the internal capacitance specification.
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Electrical Characteristics
Freesca le Sem ico nd uctor42
.
Table 8 provides the DDR controller interface capacitance for DDR3 memory.
Note: At recommended operating conditions (see Table 4) with VDDDDR =1.5V.
Table 9 lists the current draw characteristics for MVREF.
Note: Values when used at recommended operating conditions (see Table 4).
2.5.2 High-Speed Serial Interface (HSSI) DC Electrical Characteristics
The MSC8158E features an HSSI that includes one 8-channel SerDes port (lanes C through J) used for high-speed serial
interface applications (Serial RapidIO interfaces, CPRI, and SGMII). This section and its subsections describe the common
portion of the SerDes DC, including the DC requirements for the SerDes reference clocks and the SerDes data lane transmitter
(Tx) and receiver (Rx) reference circui ts. The data lane circuit specifications are specific for each suppo rted interface, and they
have individual subsections by protocol. The sel ection of individual data channel functionality is d one via the Reset
Configuration Word High Register (RCWHR) SerDes Protocol selection fields (S1P and S2P). Specific AC electrical
characteristics are defined in Section 2.6.2, “HSSI AC Timing Specifications.”
Table 7. DDR3 SDRAM Interface DC Electrical Characteristics
Parameter/Condition Symbol Min Max Unit Notes
I/O reference voltage MVREF 0.49 × VDDDDR 0.51 × VDDDDR V2,3,4
Input high voltage VIH MVREF + 0.100 VDDDDR V5
Input low voltage VIL GND MVREF – 0.100 V 5
Output high current (VOUT = 0.7125 V) IOH — –25.9 m A 6, 7
Output low current (VOUT = 0.7125 V) IOL 25.9 — mA 6, 7
I/O leakage current IOZ –50 50 μA8
Notes: 1. VDDDDR is expected to be within 50 mV of the DRAM VDD at all times. The DRAM and memory controller can use the same or
different sources.
2. MVREF is expected to be equal to 0.5 × VDDDDR and to track VDDDDR DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed 1% of the VDDDDR DC value (that is, 15 mV).
3. VTT is not applied directly to the device. It is the supply to which the far end signal termination is made and is expected to be
equal to MVREF with a minimum value of MVREF – 0.04 and a maximum value of MVREF + 0.04 V. VTT should track variations
in the DC-level of MVREF.
4. The voltage regulator for MVREF meet the specifications stated in Table 9.
5. Input capacitance load for DQ, DQS, and DQS signals are available in the IBIS models.
6. IOH and IOL are measured at VDDDDR = 1.425 V.
7. Refer to the IBIS model for the complete output IV curve characteristics.
8. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR.
Table 8. DDR3 SDRAM Capacitance
Parameter Symbol Min Max Unit
I/O capacitance: DQ, DQS, DQS CIO 68pF
Delta I/O capacitance: DQ, DQS, DQS CDIO —0.5pF
Note: Guaranteed by FAB process and micro-const ruction.
Table 9. Current Draw Characteristics for MVREF
Parameter / Condition Symbol Min Max Unit
Current draw for MVREF IMVREFn — 1250 μA
Electrical Characteri stics
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 43
2.5.2.1 Signal Term Definitions
The SerDes interface uses differential signaling to transfer data across the serial link. This section defines terms used in the
descrip tion and speci fication of dif ferent ial sign als. Figure 3 shows ho w the signals are defined. Figure 3 shows the wavef orm
for either a transmitter output (SD_[C–J]_TX and SD_[C–J]_TX) or a receiver input (SD_[C–J]_RX and SD_[C–J]_RX). Each
signal swings between X volts and Y volts where X > Y.
Using this waveform, the definitions are listed in Table 10. To simplify the illustration, the definitions assume that the SerDes
transmitter and receiver operate in a fully symmetrical differential signaling environment.
Figure 3. Differential Voltage Definitions for Transmitter/Receiver
Table 10. Differential Signal Definitions
Term Definition
Sing le -Ended Swing The transmitter output signals and the receiver input signals SD[C–J]_TX, SD_[C–J]_TX,
SD_[C–J]_RX and SD_[C–J]_RX each have a peak-to-peak swing of X – Y volts. This is also referred
to as each signal wire’s single-ended swing.
Diff e r e ntia l Ou t p ut Voltage, V OD (or
Diff er e ntial Outpu t Sw ing): The diff erential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the
two complimentary output voltages: VSD_[C–J]_TX – VSD[C–J]_TX. The VOD value can be either positive
or negative.
Differential Input Voltage, VID (or
Differential Input Swing)The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two
complimentary input voltages: VSD_[C–J]_RX – VSD_[C–J]_RX. The VID value can be either positive or
negative.
Differential Peak Voltage, VDIFFp The peak value of the differential transmitter output signal or the differential receiver input signal is
defined as the differential peak voltage, VDIFFp = |X– Y| volts.
Differential Peak-to-Peak, VDIFFp-p Since the differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter output
signal or the differential receiver input signal is defined as differential peak-to-peak voltage,
VDIFFp-p =2×VDIFFp = 2 ×|(A – B)| volts, which is twice the differential swing in amplitude, or twice
of the differential peak. For example, the output differential peak-peak volt age can also be calculated
as VTX-DIFFp-p = 2 ×|VOD|.
Differential Swing, VID or VOD = X – Y
X Volts
Y Volts
Differential Peak Voltage, VDIFFp = |X – Y|
Differential Peak-Peak Voltage, VDIFFpp = 2 ×VDIFFp (not shown)
SD_[C–J]_TX or
SD_[C–J]_RX
SD_[C–J]_TX or
SD_[C–J]_RX
Vcm = (X + Y)/2
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Electrical Characteristics
Freesca le Sem ico nd uctor44
To illustrate these definitions usin g real val ues, consid er the example of a current mode logic (CML) transmitter that has a
common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing fro m 2.0 V to 2.5 V, the peak-to-peak
voltage swing of each signal (TD o r TD) is 50 0 mV p-p, which is referr ed to as the sin gle-ended swing fo r each sign al. Because
the differential signaling environment is fully symmetrical in this example, the transmitter output differential swing (VOD) has
the same amplitude as each sig nal single-ended swing. Th e diff erential output sig nal ranges between 500 mV and –500 mV. In
other word s, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV.
The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
2.5.2.2 SerDes Reference Clock Receiver Characteristics
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clock inputs are SD_REF_CLK1/SD_REF_CLK1 or SD_REF_CLK2/SD_REF_CLK2.
Figure 4 shows a receiver reference diagram of the SerDes reference clocks.
The characteristics of the clock signals are as follows:
• The supply voltage requirements for VDDSXC are as specified in Table 4.
• The SerDes reference clock receiver reference circuit structure is as follows:
—The SD_REF_C LK [1– 2] and SD_R EF _CL K[ 1–2] are internally AC-coupled differential inputs as shown in
Figure 4. Each differential clock input (SD_REF_CLK[1–2] or SD_REF_CLK[1–2] has on-c hip 50-Ω
termination to SXCVSS followed by on-c hip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and
single-ended mode descriptions below for detailed requirements.
• The maximum average current requirement also determines the comm on mode voltag e rang e.
Differential Waveform The differential waveform is constructed by subtracting the inverting signal (SD_[C–J]_TX, fo r
example) from the non-inverting signal (SD_[C–J]_TX, for example) within a differential pair . There is
only one signal trace curve in a differential waveform. The voltage represented in the differential
waveform is not referenced to ground. Refer to Figure 3 as an example for differential waveform.
Common Mode Voltage, Vcm The common mode voltage is equal to half of the sum of the voltages between each conductor of a
balanced interchange circuit and ground. In this example, for SerDes output,
Vcm_out =(V
SD_[C–J]_TX +V
SD_[C–J]_TX) ÷2 = (A + B) ÷2, which is the arithmetic mean of the two
complimentary output voltages within a diff erential pair. In a system, the common mode voltage may
often differ from one component’s output to the other’s input. It may be different between the receiver
input and driver output circuits within the same component. It is also referred to as the DC offset on
some occasion s.
Figure 4. Receiver of SerDes Reference Clocks
Table 10. Differential Signal Definitions (continued)
Term Definition
Input
Amp
50
Ω
50
Ω
SD_REF_CLK[1–2]
SD_REF_CLK[1–2]
Electrical Characteri stics
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 45
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mo de input voltage
is not critical as long as it is within the range allowed by the maximum average curr ent of 8 mA because the input
is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V /50 = 8 mA)
while the minimum common mode input level is 0.1 V above GNDSXC. For example, a clock with a 50/50 duty
cycle can be p rodu ced by a clock driver with o utpu t driv en b y its cur rent s ource f rom 0 mA to 1 6 mA (0–0 .8 V),
such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode
voltage a t 400 mV.
— If the device driving the SD_REF_CLK[1–2] and SD_REF_CLK[1–2] inputs cannot drive 50 Ω to GNDSXC DC
or the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be
AC-coupled externally.
• The input amplitude req uirem ent is described in detail in the following sectio ns.
2.5.2.3 SerDes Transmitter and Receiver Reference Circuits
Figure 5 shows the reference circuits for SerDes data lane transmitter and receiver.
2.5.2.4 Equalization
With the use of high-speed serial links, the interconnect media causes degradation of the signal at the receiver and produces
effects such as inter -symbol interference (ISI) or data-dependent jitter . This loss can b e large enough to degrade the eye opening
at the receiver beyond that allowed by the specification. To offset a portion of these effects, equalization can be used. The
following is a list of the most commonly used equalization techniques:
• Pre-emphasis on the transmitter.
• A passive high-pass filter network placed at the receiver, often referred to as passive equalization.
• The use of active circuits in the receiver, often referred to as adaptive equalization.
2.5.3 DC-Level Requirements for SerDes Interfaces
The following subsections define the DC-level requiremen ts for the SerDes reference clocks, the Serial RapidIO data lines, the
CPRI data lines, and the SGMII data lines.
2.5.3.1 DC-Level Requirements for SerDes Reference Clocks
The DC-level requirement for the SerDes reference clock inputs is different depending on t he sign al ing mode used to connect
the clock driver chip and SerDes reference clock inputs, as described below:
Figure 5. SerDes Transmitter and Receiver Reference Circuits
50 Ω
50 Ω
50 Ω
50 Ω
Transmitter Receiver
SD_[C–J]_TX SD_[C–J]_RX
SD_[C–J]_TX SD_[C–J]_RX
Note: The [C–J] indicates the specific SerDes lane. Each lane can be assigned to a specific
for details). External AC coupling capacitors are required for all protocols for all lanes.
protocol by the RCW assignments at reset (see Chapter 5, Reset in the reference manual
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• Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV d ifferential peak-peak (or
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing of less than 800 mV and greater than 200 mV. This requir ement is the same for both external
DC-coupled or AC-coupled connection.
— For an external DC-coupled connection, the maximum average current requirements sets the requirement for
average voltage (common mode voltage) as between 100 mV and 400 mV. Figure 6 shows the SerDes reference
clock input requirement for DC-coupled connection scheme.
— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.
Because the external AC-coupling capacitor blocks the DC-level, th e clock driver and th e SerDes reference clock
receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection
schem e ha s its common mode voltage set to GNDSXC. Each signal wire of the differential inputs is allowed to
swing below and above the command mode voltage GNDSXC. Figure 7 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
• Single-Ended Mode
— The reference clock can also be single-ended. The SD_REF_CLK[1–2] input amplitude (single-ended swing)
must be between 400 mV and 800 m V peak-peak (from VMIN to VMAX) with SD_REF_CLK[1–2] either left
unconnected or tied to gr ound.
— The SD_REF_CLK[1–2] input average voltage must be between 200 and 400 mV. Figure 8 shows the SerDes
reference clock input requirement for single-ended signaling mode.
Figure 6. Differential Reference Clock Input DC Requirements (External DC-Coupled)
Figure 7. Differential Reference Clock Input DC Requirements (External AC-Coupled)
SD_REF_CLK[1–2]
SD_REF_CLK[1–2]
Vmax < 800 mV
Vmin > 0V
100 mV < Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLK[1–2]
SD_REF_CLK[1–2]
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax < Vcm + 400 mV
Vmin > Vcm – 400 mV
Electrical Characteri stics
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— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled
externally. For the best no ise performance, the reference of the clock coul d be DC- or AC-co upled into th e unused
phase (SD_REF_CLK[1–2]) through t he same source impedance as t he clock input (SD_REF_C LK[1–2]) in use.
2.5.3.2 DC Level Requirements for Serial RapidIO Configurations
Note: Specifications are valid at the recommended operating conditions listed in Table 4.
Figure 8. Single-Ended Reference Clock Input DC Requirements
Table 11. Seri al RapidIO Transmi tter DC Specificat ions for Transfer Rates ≤ 3.125 Gbaud
Parameter Symbol Min Nom Max Units Condition
Output voltage VO–0.40 —2.30 V
Long run differential output voltage VDIFFPP 800 — 1600 mVp-p L[C–J]TECR0[AMP _RED] = 0b000000
Short run differential output voltage VDIFFPP 500 — 1000 mV p-p L[C–J]TE CR0[AMP _RED] = 0b001000
DC differential TX impedance ZTX-DIFF-DC 80 100 120 Ω
Note: Voltage relative to COMMON of either signal comprising a differential pair.
Table 12. Serial RapidIO Receiver DC Specifications for Transfer Rates ≤ 3.125 Gbaud
Parameter Symbol Min Nom Max Units
Differential input voltage VIN 200 — 1600 mVp-p
DC differential RX impedance ZRX-DIFF-DC 80 100 120 Ω
Notes: 1. Voltage relative to COMMON of either signal comprising a differential pair.
2. Specifications are for Long and Short Run.
Table 13. Serial RapidIO Transmitter DC Specifications for Short Run at 5 Gbaud
Parameter Symbol Min Nom Max Units Condition
Output differential voltage
(into floating load Rload = 100 Ω)T_Vdiff 400 —750 mV Amplitude setting
L[C–J]TECR0[AMP_RED] = 0b001101
Differential resist ance T_Rd 80 100 120 Ω
Table 14. Serial RapidIO Receiver DC Specifications for Short Run at 5 Gbaud
Parameter Symbol Min Nom Max Units
Input differential voltage R_Vdiff 125 —1200 mV
Diff erential resistance R_Rdin 80 120 Ω
SD_REF_CLK[1–2]
SD_REF_CLK[1–2]
400 mV < SD_REF_CLK[1–2] Input Amplitude < 800 mV
0V
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2.5.3.3 DC-Level Requirements for CPRI Configurations
This section provide various DC-level requirements for CPRI Configurations.
Note: Specifications are valid at the recommended operating conditions listed in Table 4.
Table 15. Serial RapidIO Transmitter DC Specifications for Long Run at 5 Gbaud
Parameter Symbol Min Nom Max Units Conditions
Output differential voltage
(into floating load Rload = 100 Ω)T_Vdiff 800 — 1200 mV Amplitude setting
L[C–J]TECR0[AMP_RED] = 0b000000
(with de-emphasis disabled)
De-emphasized differential output
voltage T_VTX-DE-RATIO-3.5dB 3 3.5 4 dB • p(n)_(y)_tx_eq_type[1:0] = 01
• p(n)_(y)_tx_ratio_post1q[3:0] = 1110
Tx De-emphasized level T_VTX-DE-RATIO-6.0dB 5.5 6 6. 5 dB • p(n)_(y)_tx_eq_type[1:0] = 01
• p(n)_(y)_tx_ratio_post1q[3:0] = 1100
Differential resistance T_Rd 80 100 120 Ω
Table 16. Serial RapidIO Receiver DC Specifications for Long Run at 5 Gbaud
Parameter Symbol Min Nom Max Units Condition
Input differential
voltage R_Vdif f N/A — 1200 mV It is assumed that for the R_Vdiff
min specification, that the eye
can be closed at the receiver
after passing the signal through a
CEI/SRIO Level II LR compliant
channel.
Diff erential resistance R_Rdin 80 — 120 Ω
Table 17. CPRI Transmitter DC Specifications (LV: 1.2288, 2.4576 and 3.072 Gbps)
Parameter Symbol Min Nom Max Units Condition
Output voltage VO–0.40 — 2.30 V Voltage relative to COMMON of either signal
comprising a differential pair.
Differential output voltage VDIFFPP 800 — 1600 mVp-p L[C–J]TECR0[AMP_RED] = 0b000000.
Differential resistance T_Rd 80 100 120 Ω
Note: LV is XAUI-based.
Table 18. CPRI Transmitter DC Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
Parameter Symbol Min Nom Max Units Condition
Output differential vol tage (into floating
load Rload = 100 Ω)T _Vdiff 800 — 1200 mV L[C –J]TECR0[AMP _RED] = 0x000000
Differential resistance T_Rd 80 100 120 Ω
Note: LV-II is CEI-6G-LR-based.
Table 19. CPRI Receiver DC Specifications (LV: 1.2288, 2.4576 and 3.072 Gbps)
Parameter Symbol Min Nom Max Units Condition
Differential input voltage VIN 200 — 1600 mVp-p Measured at receiver.
Difference resistance R_Rdin 80 — 120 Ω
Note: LV is XAUI-based.
Electrical Characteri stics
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2.5.3.4 DC-Level Requirements for SGMII Configurations
Note: Specifications are valid at the recommended operating conditions listed in Table 4.
Table 21 describes the SGMII SerDes transm itter AC-coupled DC electrical characteristics .
Table 20. CPRI Receiver DC Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
Parameter Symbol Min Nom Max Units Condition
Input differential voltage R_Vdif f N/A — 1200 mV It is assumed that for the R_Vdiff
min specification, that the eye
can be closed at the receiver
after passing the signal through a
CEI/CPRI Level II LR compliant
channel.
Differential resistance R_Rdin 80 — 120 Ω
Note: LV-II is CEI-6G-LR-based.
Table 21. SGMII DC Transmitter Electrical Characteristics
Parameter Symbol Min Nom Max Unit Conditions
Output differential
voltage |VOD| 0.64 × Nom 500 1.45 × Nom mV 1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0 V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[C–J]TECR0[AMD_RED] = 0b000000
Output differential
voltage |VOD| 0.64 × Nom 459 1.45 × Nom mV 1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[C–J]TECR0[AMD_RED] = 0b000010
Output differential
voltage |VOD| 0.64 × Nom 417 1.45 × Nom mV 1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[C–J]TECR0[AMD_RED] = 0b000101
Output differential
voltage |VOD| 0.64 × Nom 376 1.45 × Nom mV 1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[C–J]TECR0[AMD_RED] = 0b001000
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Table 22 describes the SGMII SerDes receiver AC-coupled DC electrical characteristics.
Output differential
voltage |VOD| 0.64 × Nom 333 1.45 × Nom mV 1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[C–J]TECR0[AMD_RED] = 0b001100
Output differential
voltage |VOD| 0.64 × Nom 292 1.45 × Nom mV 1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[C–J]TECR0[AMD_RED] = 0b001111
Output differential
voltage |VOD| 0.64 × Nom 250 1.45 × Nom mV 1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[C–J]TECR0[AMD_RED] = 0b010011
Output impedance
(single-ended) RO40 50 60 Ω—
Output high
voltage VOH — — 1.5 × |VOD, max| mV —
Output low voltage VOL |VOD|, min/2 — — mV —
Table 22. SGMII DC Receiver Electrical Characteristics1,2
Parameter Symbol Min Nom Max Unit Condition
Input differential voltage3VRX_DIFFp-p 100 — 1200 mV L[C–J]GCR1 [RECTL_ SIGD] = 0b001
175 — 1200 mV L[C–J]GCR1 [RECTL_ SIGD] = 0b100
Loss of signal threshold4VLOS 30 — 100 mV L[C–J]GCR1[RE CTL_ SIGD] = 0b001
65 — 175 mV L[C–J]GCR1 [RECTL_ SIGD] = 0b100
Receiver differential input
impedance ZRX_DIFF 80 — 120 Ω—
Notes: 1. The supply voltage is 1.0 V.
2. Input must be externally AC-coupled.
3. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
4. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in the PCI Express interface.
Refer to the PCI Express Differential Receiver (RX) Input Specifications section of the PCI Express Specification document.
for details.
Table 21. SGMII DC Transmitter Electrical Characteristics (continued)
Parameter Symbol Min Nom Max Unit Conditions
Electrical Characteri stics
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2.5.4 RGMII and Other Interface DC Electrical Characteristics
Table 23 describes the DC electrical characteristics for the following interfaces:
•RGMII Ethernet
• SPI
•GPIO
• UART
•TIMER
•EE
•I
2C
• Interru pt s (IR Qn , NMI_OUT/CP_RX_INT, INT_OUT/CP_TX_INT)
• Clock and resets (CLKIN/MCLKIN, PORESET, HRESET, H RESET_IN)
• DMA External Request
•JTAG signals
2.6 AC Timing Characteristics
This section describes the AC timing characteristics for the MSC8158E.
2.6.1 DDR SDRAM AC Timing Specifications
This section describes the AC electrical characteristics for the DDR SDRAM interface.
2.6.1.1 DDR SDRAM Input AC Timing Specifications
Table 24 provides the input AC timing specifications for the DDR SDRAM when VDDDDR (typ) = 1.5 V.
Table 23. 2.5 V I/O DC Electrical Characteristics
Characteristic Symbol Min Max Unit Notes
Input high voltage VIH 1.7 — V 1
Input low voltage VIL —0.7V1
Input high current (VIN = VDDIO)I
IN —30μA2
Input low current (VIN = GND) IINL –30 — μA2
Output high voltage (VDDIO = min, IOH = –1.0 mA) VOH 2.0 VDDIO + 0.3 V 1
Output low voltage (VDDIO = min, IOL= 1.0 mA) VOL GND – 0.3 0.40 V 1
Notes: 1. The min VIL and max VIH values are based on the respective min and max VIN values listed in Table 4.
2. The symbol VIN represents the input voltage of the supply. It is referenced in Table 4.
Table 24. DDR3 SDRAM Input AC Timing Specifications for 1.5 V Interface
Parameter Symbol Min Max Unit
AC input low voltage
• > 1200 MHz data rate
•≤ 1200 MHz data rate
VILAC —MVREF – 0.150
MVREF – 0.175
V
AC input high voltage
• > 1200 MHz data rate
•≤ 1200 MHz data rate
VIHAC MVREF + 0.150
MVREF + 0.175
—V
Note: At recommended operating conditions with VDDDDR of 1.5 ± 5%.
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Table 25 provides the input AC timing specifications for the DDR SDRAM interface.
Figure 9 shows the DDR3 SDRAM interface input timing diagram.
2.6.1.2 DDR SDRAM Output AC Timing Specifications
Table 26 provides the output AC timing specifications for the DDR SDRAM interface.
Table 25. DDR SDRAM Input AC Timing Specifications
Parameter Symbol Min Max Unit Notes
Controller Skew for MDQS—MDQ/MECC
• 13 33 MHz data rate
• 12 00 MHz data rate
• 10 66 MHz data rate
• 80 0 MHz data rate
• 66 7 MHz data rate
tCISKEW –125
–142
–170
–200
–240
125
142
170
200
240
ps
ps
ps
ps
ps
1, 2, 4
Tolerated Skew for MDQS—MDQ/MECC
• 13 33 MHz data rate
• 12 00 MHz data rate
• 10 66 MHz data rate
• 80 0 MHz data rate
• 66 7 MHz data rate
tDISKEW –250
–275
–300
–425
–510
250
275
300
425
510
ps
ps
ps
ps
ps
2, 3
Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. Subtract this value from the total timing budget.
2. At recommended operating conditions with VDDDDR (1.5 V) ± 5%
3. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW =±(T÷4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
4. The tCISKEW test coverage is derived from the tDISKEW parameters.
Figure 9. DDR3 SDRAM Interface Input Timing Diagram
Table 26. DDR SDRAM Output AC Timing Specifications
Parameter Symbol 1Min Max Unit Notes
MCK[n ] cyc le tim e tMCK 1.5 3 ns 2
MCK[n]
MCK[n] tMCK
MDQ[n]
MDQS[n]
tDISKEW
D1D0
tDISKEW
tDISKEW
Electrical Characteri stics
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ADDR/CMD output setup with respect to MCK
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHAS 0.606
0.675
0.744
0.917
1.10
—
—
—
—
—
ns
ns
ns
ns
ns
3
ADDR/CMD output hold with respect to MCK
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHAX 0.606
0.675
0.744
0.917
1.10
—
—
—
—
—
ns
ns
ns
ns
ns
3
MCSn output setup with respect to MCK
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHCS 0.606
0.675
0.744
0.917
1.10
—
—
—
—
—
ns
ns
ns
ns
ns
3
MCSn output hold with respect to MCK
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHCX 0.606
0.675
0.744
0.917
1.10
—
—
—
—
—
ns
ns
ns
ns
ns
3
MCK to MDQS Skew
• > 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHMH –0.245
–0.375
–0.6
0.245
0.375
0.6
ns
ns
ns
4
MDQ/MECC/MDM output setup with respect to MDQS
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHDS,
tDDKLDS 250
275
300
375
450
—
—
—
—
—
ps
ps
ps
ps
ps
5, 6
MDQ/MECC/MDM output hold with respect to MDQS
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHDX,
tDDKLDX 250
275
300
375
450
—
—
—
—
—
ps
ps
ps
ps
ps
5
MDQS preamble tDDKHMP 0.9 × tMCK —ns—
MDQS postamble tDDKHME 0.4 × tMCK 0.6 × tMCK ns —
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output vali d time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K)
goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MC S, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of
the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table ass ume that these two parameters have been set to the same
adjustment value. See the MSC8158E Reference Manual for a description and understanding of the timing modifications
enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MSC8158E.
6. At recommended operating conditions with VDDDDR (1.5 V) ± 5%.
Table 26. DDR SDRAM Output AC T iming Specifications (continued)
Parameter Symbol 1Min Max Unit Notes
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Note: For the ADDR/CMD setup and hold specificati ons in Table 26, it is assumed that the clock control register is set to
adjust the memory clocks by ½ applied cycle.
Figure 10 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
Figure 11 shows the DDR SDRAM output timing diagram.
Figure 10. MCK to MDQS Timing
Figure 11. DDR SDRAM Output Timing
MDQS
MCK[n]
MCK[n] tMCK
tDDKHMHmax) = 0.6 ns or 0.375 ns
tDDKHMH( m in) = –0.6 ns or –0.375 ns
MDQS
ADDR/CMD
tDDKHAS, tDDKHCS
tDDKHMH
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK[n]
MCK[n] tMCK
tDDKLDX
tDDKHDX
D1D0
tDDKHAX, tDDKHCX
Write A0 NOOP
tDDKHME
tDDKHMP
Electrical Characteri stics
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Figure 12 provides the AC test load for the DDR3 controller bus.
2.6.1.3 DDR3 SDRAM Differential Timing Specifications
This section describes the DC and AC di f f erential timing specif ications for the DDR3 SDRAM controller interface. Figure 13
shows the differential timing specification.
Note: VTR specifies the true input signal (such as MCK or MDQS) and VCP is the complementary input signal (such as
MCK or MDQS).
Table 27 provides the DDR3 differential specifications for the differential signals MDQS/MDQS and MCK/MCK.
2.6.2 HSSI AC Timing Specifications
The following subsections define the AC timing requirements for the SerDes reference clocks, the Serial RapidIO data lines,
the CPRI data lanes, and the SGMII data lines.
2.6.2.1 AC Requirements for SerDes Reference Clock
Table 28 lists AC requirements for the SerDes reference clocks.
Note: Specifications are valid at the recommended operating conditions listed in Table 4.
Figure 12. DDR3 Controller Bus AC Test Load
Figure 13. DDR3 SDRAM Differential Timing Specifications
Table 27. DDR3 SDRAM Differential Electrical Characteristics
Parameter Symbol Min Max Unit
Input AC differential cross-point voltage VIXAC 0.5 × VDDDDR – 0.150 0.5 × VDDDDR + 0.150 V
Output AC differential cross-point voltage VOXAC 0.5 × VDDDDR – 0.115 0.5 × VDDDDR + 0.115 V
Note: I/O drivers are calibrated before making measurements.
Table 28. S D_R EF _C LK[1 –2] and SD_REF_CLK[ 1– 2] Input Clock Requirements
Parameter Symbol Min Nom Max Units Notes
SD_REF_CLK[1–2]/SD_REF_CLK[1–2] frequency
range tCLK_REF — 100/125
CPRI: 122.88 —MHz 1
Output Z0 = 50 ΩRL = 50 Ω
VDDDDR/2
VTR
VCP
GND
GVDD
V
OX
or V
IX
GV
DD
/2
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SD_REF_CLK[1–2]/SD_REF_CLK[1–2] clock
frequency tolerance
• Serial RapidIO, CPRI, SGMII
• PCI Express interface
tCLK_TOL
–100
–300 —
—100
300 ppm
ppm
—
SD_REF_CLK[1–2]/SD_REF_CLK[1–2] reference
clock duty cycle tCLK_DUTY 40 50 60 % 4
SD_REF_CLK[1–2]/SD_REF_CLK[1–2]max
deterministic peak-peak jitter at 10-6 BER tCLK_DJ ——42ps—
SD_REF_CLK[1–2]/SD_REF_CLK[1–2] total
reference clock jitter at 10-6 BER (peak-to-peak jitter
at ref_clk input)
tCLK_TJ ——86ps2
SD_REF_CLK/SD_REF_CLK rising/falling edge rate tCLKRR/tCLKFR 1—4V/ns3
Differential input high voltage VIH 200 — — mV 4
Differential input low voltage VIL — — –200 mV 4
Rising edge rate (SD_REF_CLKn to falling edge rate) Rise-Fall — — 20 % 5, 6
Notes: 1. Only 100, 122.88, and 125 MHz have been tested. CPRI uses 122.88 MHz. The other interfaces use 100 or 125 MHz. Other
values will not work correctly with the rest of the system.
2. Limits are from PCI Express CEM Rev 2.0.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 14.
4. Measurement taken from differential waveform.
5. Measurement taken from single-ended wavef orm.
6. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV
window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross
point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rising edge rate
of SD_RF_CLKn should be compared to the falling edge rate of S D_REF_CLKn; the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 15.
7. REF_CLK jitter must be less than 0.05 UI when measured against a Golden PLL reference. The Golden PLL must have a
maximum baud rate bandwidth greater than 1667, with a maximum 20 dB/dec rolloff down to a baud rate of 16.67 with no
peaking around the corner frequency.
Figure 14. Differential Measurement Points for Rise and Fall Time
Table 28. SD_REF_CLK[1–2] and SD_REF_CLK[1–2] Input Clock Requirements (continued)
Parameter Symbol Min Nom Max Units Notes
VIH = +200 mV
VIL = –200 mV
0.0 V
SD_REF_CLKn –
SD_REF_CLKn
Fall Edge RateRise Edge Rate
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2.6.2.2 Spread Spectrum Clock
SD_REF_CLK[1–2] and SD_REF_CLK[1–2] were designed to work with a spread spectrum clock (+0 to 0.5% spreading at
30–33 KH z rate is allowed) , assuming b oth ends have t he same reference cl ock and the indu stry pro tocol support s it. For bet ter
results, use a source without s ignif ican t unintended modulation.
2.6.2.3 Serial RapidIO AC Timing Specifications
Note: Specifications are valid at the recommended operating conditions listed in Table 4.
Table 29 defines the transmitter AC specifications for the Serial RapidIO interface at frequencies up to 3.125 Gbaud. The AC
timing specifications do not include REF_CLK jitter.
Table 30 defines the Receiver AC specifications for the Serial RapidIO interface at frequencies up to 3.125 Gbaud. The AC
timing specifications do not include REF_CLK jitter.
Table 31 defines the short run transmitter AC specifications for the Serial RapidIO interface at 5 Gbaud. The AC timing
specifications do not include REF_CLK jitter.
Figure 15. Single-Ended Measurement Points for Rise and Fall Time Matching
Table 29. Serial RapidIO Transmitter AC Timing Specifications Up to 3.125 Gbaud
Characteristic Symbol Min Nom Max Unit
Deterministi c Ji tter JD— — 0.17 UI p-p
Total Jitter JT— — 0.35 UI p-p
Unit Interval: 1.25 GBaud UI 800 – 100ppm 800 800 + 100ppm ps
Unit Interval: 2.5 GBaud UI 400 – 100ppm 400 400 + 100ppm ps
Unit Interval: 3.125 GBaud UI 320 – 100ppm 320 320 + 100ppm ps
Table 30. Serial RapidIO Receiver AC Timing Specifications Up to 3.125 Gbaud
Characteristic Symbol Min Nom Max Unit Notes
Deterministic Jitter Tolerance JD— — 0.37 UI p-p 1
Combined Deterministic and Random Jitter
Tolerance JDR — — 0.55 UI p-p 1
Total Jitter Tolerance JT— — 0.65 UI p-p 1, 2
Bit Error Rate BER — — 10–12 ——
Unit Interval: 1.25 GBaud UI 800 – 100ppm 800 800 + 100ppm ps —
Unit Interval: 2.5 GBaud UI 400 – 100ppm 400 400 + 100ppm ps —
Unit Interval: 3.125 GBaud UI 320 – 100ppm 320 320 + 100ppm ps —
Notes: 1. M easured at rec eiver.
2. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 16. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
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Table 32 defines the short run Receiver AC specifications for the Serial RapidIO interface at 5 Gbaud. The AC timing
specifications do not include REF_CLK jitter.
Table 33 defines the Tran smitter AC specifications for long run Serial RapidIO interfaces using a transfer rate of 5 Gbps. The
AC timing specifications do not include REF_CLK jitter.
Table 34 defines the Receiver AC specifications for long run Serial RapidIO interfaces using a transfer rate of 5 Gbps. The AC
timing specifications do not include REF_CLK jitter.
Table 31. Seri al RapidIO Short Run Transmitter AC Timing Specifications at 5.0 Gbaud
Characteristic Symbol Min Nom Max Unit
Uncorrelated High Probability Jitter T_UHPJ — — 0.15 UI p-p
Total Jitter T_TJ — — 0.30 UI p-p
Baud Rate UI 5.000 – 100ppm 5.000 5.000 + 100ppm Gbaud
Table 32. Serial RapidIO Short Run Receiver AC Timing Specifications at 5 Gbaud
Characteristic Symbol Min Nom Max Unit
Rx Baud Rate R_Baud 5.000 – 100ppm 5.000 5. 000 + 100ppm Gbaud
Uncorrelated Bounded High Probability Jitter R_UBHPJ — — 0.15 UIp-p
Correlated Bounded High Probability Jitter R_CBHPJ — — 0.3 UIp-p
Bounded High Probability Jitter R_BHPJ — — 0.45 UIp-p
Sinusoidal Jitter maximum R_SJ-max — — 5 UIp-p
Sinusoidal Jitter, H igh Frequency R_SJ- hf — — 0.05 U Ip-p
Total jitter (without sinusoidal jitter) R_Tj — — 0.6 UIp-p
Note: The AC specifications do not include REF_CLK jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded
region in Figure 17. The ISI jitter (R_CBHPJ) and amplitude have to be correlated, for example, by a PCB trace.
Table 33. Serial RapidIO Transmitter Long Run AC Timing for Transfer Rate of 5 Gbps
Characteristic Symbol Min Nom Max Unit Conditions
Tx Baud Rate T_Baud 5.000 – 100 ppm 5.000 5.000 + 100 ppm Gbps ± 100 ppm
Uncorrelated high probability jitter T_UHPJ 0.15 UI p-p W ith de-emphasis
disabled.
Total Jitter T_TJ — — 0.30 UI p-p With de-emphasis
disabled.
Table 34. Serial RapidIO Receiver Long Run AC Ti ming for Transfer Rate of 5 Gbps
Characteristic Symbol Min Nom Max Unit Condition
Rx Baud Rate R_Baud 5.000 – 100 ppm 5.000 5.000 + 100 ppm Gbps
Gaussian R_GJ 0.275 UI p-p Informative jitter budget
@Rx input
Uncorrelated bounded high
probability jitter (DJ)R_UBHPJ 0.15 UI p-p Informative jitter budget
@Rx input
Correlated bounded high
probability jitter (ISI) R_CBHPJ 0.525 UI p-p Informative jitter budget
@Rx input
Bounded high probability jitter
(DJ + ISI) R_BHPJ 0.675 UI p-p Informative jitter budget
@Rx input
Sinusoidal jitter, maximum R_S J-m a x 5 UI p-p Inform ative jitter budget
@Rx input
Sinusoidal jitter, high frequency R _SJ-hf 0.05 UI p-p Informative jitter budget
@Rx input
Electrical Characteri stics
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Total Jitter (does not include
sinusoidal jitter). R_TJ 0.95 UI p-p Informative jitter budget
@Rx input
Note: The AC specifications do not include REF_CLK jitter. The sinusoidal jitter in the total jitter tolerance may have any amplitude and
frequency in the unshaded region of Figure 17. The ISl jitter (R_CBHPJ) and amplitude have to be correlated, for example, by a PC
trace.
Figure 16. Single Frequency Sinusoidal Jitter Limits for Data Rates for 3.125 Gbps and Below
Figure 17. Single Frequency Sinusoidal Jitter Limits for Data Rate 5.0 Gbps
Table 34. Serial RapidIO Receiver Long Run AC Ti ming for Transfer Rate of 5 Gbps (continued)
Characteristic Symbol Min Nom Max Unit Condition
8.5 UI p-p
0.10 UI p-p
Sinusoidal
Jitter
Amplitude
baud/14200 baud/1667 20 MHzFrequency
20dB/dec
Pass
5 UI p-p
0.05 UI p-p
Sinusoidal
Jitter
Amplitude
22.1 kHz 2.999 MHz 20 MHzFrequency
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2.6.2.4 CPRI AC Timing Specifications
Note: Specifications are valid at the recommended operating conditions listed in Table 4.
Table 35 defines the transmitter AC specif ications for the CPRI LV lanes. The AC timing specifications do not include
REF_CLK jitter.
Table 36 defines the transmitter AC specif ications for the CPRI LV-II lanes. The AC timing specifications do not include
REF_CLK jitter.
Table 37 defines the Receiver AC specifications for CPRI LV. The AC timing specifications do not include REF_CLK jitter.
Table 38 defines the Receiver AC specifications for CPRI LV-II. The AC timing specifications do not include REF_CLK jitter.
Table 35. CPRI Transmitter AC Timing Specifications (LV-I: 1.2288, 2.4576, and 3.072 Gbps)
Characteristic Symbol Min Nom Max Unit
Deterministi c Jitter JD — — 0.17 UI p-p
Total Jitter JT — — 0.35 UI p-p
Unit Interval: 1.2288 GBaud UI 1/1228.8 – 100ppm 1/1228.8 1/1228.8 + 100ppm µs
Unit Interval: 2.4576 GBaud UI 1/2457.6 – 100ppm 1/2457.6 1/2457.6 + 100ppm µs
Unit Interval: 3.072 GBaud UI 1/3072.0 – 100ppm 1/3072.0 1/3072.0 + 100ppm µs
Table 36. CPRI Transmitter AC Timing Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
Characteristic Symbol Min Nom Max Unit
Uncorrelated High Probability Jitter T_UHPJ — — 0.15 UI p-p
Total Jitter T_TJ — — 0.30 UI p-p
Unit Interval: 1.2288 GBaud UI 1/1228.8 – 100ppm 1/1228.8 1/1228.8 + 100ppm µs
Unit Interval: 2.4576 GBaud UI 1/2457.6 – 100ppm 1/2457.6 1/2457.6 + 100ppm µs
Unit Interval: 3.072 GBaud UI 1/3072.0 – 100ppm 1/3072.0 1/3072.0 + 100ppm µs
Unit Interval: 4.9152 GBaud UI 1/4915.2 – 100ppm 1/4915.2.8 1/4915.2 + 100ppm µs
Unit Interval: 6.144 GBaud UI 1/6144.0 – 100ppm 1/6144.0 1/6144.0 + 100ppm µs
Table 37. CPRI Receiver AC Timing Specifications (LV-I: 1.2288, 2.4576, and 3.072 Gbps)
Characteristic Symbol Min Nom Max Unit
Deterministic jitter tolerance JD — — 0.37 UI p-p
Combined deterministic and random
jitter tolerance JDR — — 0.55 UI p-p
Total Jitter toleranc e JT — — 0.65 UI p-p
Unit Interval: 1.2288 GBaud UI 1/1228.8 – 100ppm 1/1228.8 1/1228.8 + 100ppm ps
Unit Interval: 2.4576 GBaud UI 1/2457.6 – 100ppm 1/2457.6 1/2457.6 + 100ppm ps
Unit Interval: 3.072 GBaud UI 1/3072.0 – 100ppm 1/3072.0 1/3072.0 + 100ppm ps
Bit error ratio BER — — 10–12 —
Table 38. CPRI Receiver AC Timing Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
Characteristic Symbol Min Nom Max Unit
Gaussian R_GJ — — 0.275 UI p-p
Uncorrelated bounded high probability
jitter R_UBHPJ — — 0.150 UI p-p
Correlated bounded high probability
jitter R_CBHPJ — — 0.525 UI p-p
Bounded high probability jitter R_BHPJ — — 0.675 UI p-p
Sinusoidal jitter, maximum R_SJ-max — — 5.000 UI p-p
Sinusoidal jitter, high frequency R_SJ-hf — — 0.050 UI p-p
Total Jitter (does not include sinusoidal
jitter). R_TJ — — 0.950 UI p-p
Electrical Characteri stics
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Note: The intended application is a point-to-point interface up to two conn ectors. Th e maximum allowed total los s (channel
+ interconnects + other loss) is 20.4 dB @ 6.144 Gbps.
2.6.2.5 SGMII AC Timing Specifications
Note: Specifications are valid at the recommended operating conditions listed in Table 4.
Transmitter and receiver AC characteristics are measured at the transmitter outputs (SD_[C–J]_TX and SD_[C–J]_TX) or at
the receiver inputs (SD_[C–J]_RX and SD_[C–J]_RX) as depicted in Figure 18, respectively.
Table 39 provides the SGMII transmit AC timing specifications. The AC timing specifications do not include REF_CLK jitter .
Table 40 provides the SGMII receiver AC timing specifications. The AC timing specifications do not include REF_CLK jitter .
Unit Interval: 1.2288 GBaud UI 1/1228.8 – 100ppm 1/1228.8 1/1228.8 + 100ppm µs
Unit Interval: 2.4576 GBaud UI 1/2457.6 – 100ppm 1/2457.6 1/2457.6 + 100ppm µs
Unit Interval: 3.072 GBaud UI 1/3072.0 – 100ppm 1/3072.0 1/3072.0 + 100ppm µs
Unit Interval: 4.9152 GBaud UI 1/4915.2 – 100ppm 1/4915.2.8 1/4915.2 + 100ppm µs
Unit Interval: 6.144 GBaud UI 1/6144.0 – 100ppm 1/6144.0 1/6144.0 + 100ppm µs
Note: The AC specifications do not include REF_CLK jitter. The sinusoidal jitter in the total jitter tolerance may have any amplitude and
frequency in the unshaded region of Figure 17. The ISl jitter (R_CBHPJ) and amplitude have to be correlated, for example, by a PC
trace.
Figure 18. SGMII AC Test/Measurement Load
Table 39. SGMII Transmit AC Timing Specifications
Parameter Symbol Min Nom Max Unit Condition
Unit interval UI 800 – 100ppm 800 800 + 100ppm pS ± 100ppm
Deterministi c jit ter JD — — 0.17 UI p-p —
Total jitter JT — — 0.35 UI p-p —
AC coupling capacitor CTX 75 — 200 nF All transmitters must be
AC-coupled
Note: The AC specifications do not include REF_CLK jitter.
Table 38. CPRI Receiver AC Timing Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
Characteristic Symbol Min Nom Max Unit
TX
Silicon
+ Package
D+ Package
Pin
D– Package
Pin
C = CTX
C = CTX
R = 50 ΩR = 50 Ω
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Table 40. SGMII Receive AC Timing Specifications
Parameter Symbol Min Nom Max Unit Condition
Unit interval UI 800 – 100ppm 800 800 + 100ppm pS ± 100ppm
Deterministic jitter tolerance JD — — 0.37 UI p-p Measured at receiver.
Combined deterministic and random
jitter tolerance JDR — — 0.55 UI p-p Measured at receive r
Total jitter tolerance JT — — 0.65 UI p-p Measured at receiver
Bit error ratio BER — — 10–12 ——
Note: The AC specifications do not include REF_CLK jitter. The sinusoidal jitter in the total jitter tolerance may have any amplitude and
frequency in the unshaded region shown in Figure 19 or Figure 20.
Figure 19. Single Frequency Sinusoidal Jitter Limits for Baud Rate for <3.125 Gbps
Figure 20. Single Frequency Sinusoidal Jitter Limits for Baud Rate 3.125 Gbps
8.5 UI
p-p
0.10 UI
p-p
Sinusoidal
Jitter
Amplitude
baud/14200 baud/1667 20 MHzFrequency
20 dB/dec
8.5 UI
p-p
0.10 UI
p-p
Sinusoidal
Jitter
Amplitude
22.1 kHz 1.875 MHz 20 MHzFrequency
Electrical Characteri stics
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2.6.3 Timers and Timers_32b AC Ti ming Specifications
Table 41 lists the timer input AC timing specifications.
Note: For recommended operating conditions, see Table 4.
Figure 21 sh ows the AC te st loa d for the timers.
2.6.4 Ethernet Timing
This section describes the AC electrical characteristics for the Ethernet interface.
There are three general configuration registers used to configure t he timing : GCR4, UCC1_DELAY_HR, and
UCC3_DELAY_HR. These registers configure the programmab le delay units (PDU) that should be programmed differently f or
each Interface to meet timing requirements. For additional information, see the MSC8158E Reference Manual.
2.6.4.1 Management Interface Timing
Table 41. Timers Input AC Timing Spec ifications
Characteristics Symbol Minimum Unit Notes
Timers inputs—minimum pulse width TTIWID 8ns1, 2
Notes: 1. The ma ximum allowed frequency of timer outputs is 125 MHz. Configure the timer modules appropriately.
2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any
external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation.
Figure 21. Timer AC Test Load
Table 42. Ethernet Controller Management Interface Timing
Characteristics Symbol Min Max Unit
GE_MDC frequency fMDC —2.5MHz
GE_MDC period tMDC 400 — ns
GE_MDC clock pulse width high tMDC_H 160 — ns
GE_MDC clock pulse width low tMDC_L 160 — ns
GE_MDC to GE_MDIO delay tMDKHDX 10 70 ns
GE_MDIO to GE_MDC rising edge setup time tMDDVKH 20 — ns
GE_MDC rising edge to GE_MDIO hold time tMDDXKH 0—ns
Output Z0 = 50 ΩVDDIO/2
RL = 50 Ω
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2.6.4.2 RGMII AC Timing Specifications
Table 43 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.
Figure 23 shows the RGMII AC timing and multiplexing diagrams.
Figure 22. MII Management Interface Timing
Table 43. RGMII at 1 Gbps with On-Board Delay2 AC Timing Specifications1
Parameter/Condition Symbol Min Typ Max Unit
Data to clock output skew (at transmitter)3tSKEWT –0.5 — 0.5 ns
Data to clock input skew (at receiver)3tSKEWR 1—2.6ns
Notes: 1. At recommended operating conditions with VDDIO of 2.5 V ± 5%.
2. Program GCR4 as 0x00000000, UCC1_DELAY_HR as 0x00000000, and UCC3_DELAY_HR as 0x00000000.
3. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and
less than 2.0 ns is added to the associated clock signal.
Figure 23. RGMII AC Timing and Multiplexing
GE_MDC
GE_MDIO
GE_MDIO
(Input)
(Output)
t
MDC
tMDDXKH
tMDDVKH
tMDKHDX
tMDC_H tMDC_L
GTX_CLK
tSKEWT
TX_CTL
txd[7:4]
txd[3:0]
(At Transmitte r)
TXD[3:0]
RX_CTL
rxd[8:5]
rxd[3:0]RXD[3:0]
RX_CLK
(At Receiver)
tSKEWR
Electrical Characteri stics
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2.6.5 SPI Timing
Table 44 lists the SPI input and output AC timing s pecifications.
Figure 24 provides the AC test load for the SPI.
Figure 24. SPI AC Test Load
Figure 25 and Figure 26 represent the AC timings from Table 44. Note that although the s pecifications g enerally reference the
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 25 shows the SPI timings in slave mode (external clock).
Figure 25. SPI AC Timing in Slave Mode (External Clock)
Figure 26 shows the SPI timings in master mode (internal clock).
Table 44. SPI AC Timing Specifications
Parameter Symbol
1Min Max Unit Note
SPI outputs valid—Master mode (internal clock) delay tNIKHOV —6ns2
SPI outputs hold—Master mode (internal clock) delay tNIKHOX 0.5 — ns 2
SPI outputs valid—Slave mode (external clock) delay tNEKHOV —12ns2
SPI outputs hold—Slave mode (external clock) delay tNEKHOX 2—ns2
SPI inputs—Master mode (internal clock) input setup time tNIIVKH 12 — ns —
SPI inputs—Master mode (internal clock) input hold time tNIIXKH 0—ns—
SPI inputs—Slave mode (external clock) input setup time tNEIVKH 4—ns—
SPI inputs—Slave mode (external clock) input hold time tNEIXKH 2—ns—
Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of func tional bloc k)(signal) ( s tat e)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tNIKHOX symbol iz es t he i nte rnal tim in g (NI) fo r the tim e SPI CLK cl oc k re fere nc e (K) go es to th e h igh state (H) u nti l
outputs (O) are invalid (X).
2. Output s pecifica tions are mea sured from the 50% level of the rising edge of SPICLK to the 50% level of the signal.
Timings are measured at the pin.
Output Z0 = 50 ΩVDDIO/2
RL = 50 Ω
SPICLK (input)
tNEIXKH
tNEKHOV
Input Signals:
SPIMOSI
(See note)
Output Signals:
SPIMISO
(See note)
tNEIVKH
tNEKHOX
N
ote: measured with SPMODE[CI] = 0, SPMODE[CP] = 0
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Figure 26. SPI AC Timing in Master Mode (Internal Clock)
2.6.6 Asynchronous Si gnal Timing
Table 45 lists the asynchronous signal timing specifications.
The following interfaces use the specified asynchronous signals:
•GPIO. Signals GPIO[31–0], when used as GPIO signals, that is, when the alternate multiplexed special functions are
not selected.
Note: When used as a general purpose input (GPI), the input signal should be driven until it is acknowledged by the
MSC8158E device, that is, when the expected input value is read from the GPIO data register.
•EE port. Signals EE0, EE1.
•Boot function. Signal STOP_BS.
•I2C interface. Signals I2C_SCL and I2C_SDA.
•Interru pt inputs. Signals IRQ[15–0] and NMI.
•Interr upt outputs. Signals INT_OUT/CP_TX_INT an d NMI_OUT/CP_RX_INT (minimum pulse width is 32 ns).
Table 45. Signal Timing
Characteristics Symbol Type Min
Input tIN Asynchron ous One CLKIN/MCLK IN cycle
Output tOUT Asynchronous Application dependent
Note: Input value relevant for EE0, IRQ[15–0], and NMI only.
SPICLK (output)
tNIIXKH
tNIKHOV
Input Signals:
SPIMISO
(See note)
Output Signals:
SPIMOSI
(See note)
tNIIVKH
tNIKHOX
N
ote: measured with SPMODE[CI] = 0, SPMODE[CP] = 0
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2.6.7 JTAG Signals
Figure 27 shows the Test Clock Input Timing Diagram.
Figure 28 shows the boundary scan (JTAG) timing diagram.
Table 46. JTAG Timing
Characteristics Symbol All frequencies Unit
Min Max
TCK cycle time tTCKX 36.0 — ns
TCK clock high phase measured at VM = VDDIO/2 tTCKH 15.0 — ns
Boundary scan input data setup time tBSVKH 0.0 — ns
Boundary scan input data hold time tBSXKH 15.0 — ns
TCK fall to output data valid tTCKHOV — 20.0 ns
TCK fall to output high impedance tTCKHOZ — 24.0 ns
TMS, TDI data setup time tTDIVKH 5.0 — ns
TMS, TDI data hold time tTDIXKH 5.0 — ns
TCK fall to TDO dat a valid tTDOHOV — 10.0 ns
TCK fall to TDO high impedance tTDOHOZ — 12.0 ns
TRST assert time tTRST 100.0 — ns
Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.
Figure 27. Test Clock Input Timing
Figure 28. Boundary Scan (JTAG) Timing
TCK
(Input)
VMVM
t
TCKX
tTCKH
tTCKR
tTCKR
TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
Input Data Valid
Output Data Valid
tBSXKH
tBSVKH
tTCKHOV
tTCKHOZ
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Figure 29 shows the test access port timing diagram
Figure 30 shows the TRST timing diagram.
3 Hardware Design Considerations
For detailed information ab out how to des ign this device into an application, see the MSC8157 Design Checklist (AN411 0).
4 Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Figure 29. Test Access Port Timing
Figure 30. TRST Timing
Part Package Type Spheres Core
Voltage Operating
Temperature
Core
Frequency
(MHz) Order Number
MSC8158E Flip Chip Plastic Ball Grid Array (FC-PBGA) Lead-free 1.0 V 0° C to 105°C 1000 MSC8158ESVT1000A
–40° to 105°C 1000 MSC8158ETVT1000A
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
Input Data Valid
Output Data Va lid
TMS
tTDIVKH tTDIXKH
tTDOHOV
tTDOHOZ
TRST
(Input) tTRST
Package Information
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5 Package Information
NOTES:
1. ALL DIMENSIONS IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURE PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
6. ALL DIMENSIONS ARE SYMMETRIC ACROSS THE PACKAGE CENTER LINES, UNLESS DIMENSIONED
OTHERWISE.
7. 29.2MM MAXIMUM PACKAGE ASS EMBLY (LID + LAMINATE) X AND Y.
Figure 31. MSC8158E Mechanical Information, 783-ball FC-PBGA Package
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
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6 Product Documentation
Following is a general list of supporting doc umentation:
•MSC8158E Technical Data Sheet (MSC8158E). Details the signals, AC/DC characteristics, clock signal
characteristics, package and pinout, and electrical design considerations of the MSC8158E device.
•MSC8158E Reference Manual (MS C81 58E RM). Incl ud es fun ctio nal descriptions of the extended cores and all the
internal subsystems including configuration and programming information.
•Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8158E device.
•QUICC Engine Block Reference Manual with Protocol Interworking (QEIWRM). Provides detailed information
regarding the QUICC Engine technology including functional description, registers, and programming information.
•SC3850 DS P Cor e Refer ence Manual. Covers the SC3850 core architecture, control registers, clock registers, program
control, and in st ru ctio n set.
•MSC8156SC3850 DSP Core Subsystem Reference Manual. Covers core subsystem architecture, functionality, and
registers.
Product Documentation
MSC8158E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
Freescale Semicond uc tor 71
Document Number: MSC8158E
Rev. 0
11/2011
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