PD - 95872 IRF2907Z IRF2907ZS IRF2907ZL AUTOMOTIVE MOSFET HEXFET(R) Power MOSFET Features l l l l l Advanced Process Technology Ultra Low On-Resistance 175C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax D VDSS = 75V RDS(on) = 4.5m G Description ID = 75A S Specifically designed for Automotive applications, this HEXFET(R) Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. D2Pak IRF2907ZS TO-220AB IRF2907Z TO-262 IRF2907ZL Absolute Maximum Ratings Parameter Max. Units ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Silicon Limited) 170 A ID @ TC = 100C Continuous Drain Current, VGS @ 10V (See Fig. 9) 120 ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Package Limited) 75 IDM Pulsed Drain Current 680 PD @TC = 25C Maximum Power Dissipation 330 W Linear Derating Factor VGS EAS Gate-to-Source Voltage 2.2 20 W/C V 300 mJ EAS (tested) Single Pulse Avalanche Energy Tested Value c Single Pulse Avalanche Energy (Thermally Limited) c IAR Avalanche Current EAR Repetitive Avalanche Energy TJ Operating Junction and TSTG Storage Temperature Range i d h -55 to + 175 A C 300 (1.6mm from case ) Mounting torque, 6-32 or M3 screw 10 lbf*in (1.1N*m) Thermal Resistance Parameter RJC Junction-to-Case RCS Case-to-Sink, Flat, Greased Surface RJA Junction-to-Ambient RJA Junction-to-Ambient (PCB Mount, steady state) k See Fig.12a,12b,15,16 mJ Soldering Temperature, for 10 seconds k 690 jk Typ. Max. Units --- 0.45 C/W 0.50 --- --- 62 --- 40 HEXFET(R) is a registered trademark of International Rectifier. www.irf.com 1 06/17/04 http://store.iiic.cc/ IRF2907Z/S/L Static @ TJ = 25C (unless otherwise specified) Parameter V(BR)DSS VDSS/TJ RDS(on) VGS(th) Min. Typ. Max. Units Qg Qgs Qgd td(on) tr td(off) tf LD Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance 75 --- --- 2.0 180 --- --- --- --- --- --- --- --- --- --- --- --- --- 0.069 3.5 --- --- --- --- --- --- 180 46 65 19 140 97 100 5.0 --- --- 4.5 4.0 --- 20 250 200 -200 270 --- --- --- --- --- --- --- LS Internal Source Inductance --- 13 --- Ciss Coss Crss Coss Coss Coss eff. Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance --- --- --- --- --- --- 7500 970 510 3640 650 1020 --- --- --- --- --- --- gfs IDSS IGSS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current f f f 6mm (0.25in.) from package pF Diode Characteristics Parameter Min. Typ. Max. Units IS Continuous Source Current --- --- 75 ISM (Body Diode) Pulsed Source Current --- --- 680 VSD trr Qrr ton (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time --- --- --- --- 41 59 1.3 61 89 G S and center of die contact VGS = 0V VDS = 25V = 1.0MHz, See Fig. 5 VGS = 0V, VDS = 1.0V, = 1.0MHz VGS = 0V, VDS = 60V, = 1.0MHz VGS = 0V, VDS = 0V to 60V Conditions MOSFET symbol A c Conditions V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 1mA m VGS = 10V, ID = 75A V VDS = VGS, ID = 250A S VDS = 25V, ID = 75A A VDS = 75V, VGS = 0V VDS = 75V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V ID = 75A nC VDS = 60V VGS = 10V ns VDD = 38V ID = 75A RG = 2.5 VGS = 10V D nH Between lead, V ns nC D showing the integral reverse G p-n junction diode. TJ = 25C, IS = 75A, VGS = 0V TJ = 25C, IF = 75A, VDD = 38V di/dt = 100A/s f S f Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Limited by TJmax, starting TJ = 25C, L=0.11mH, RG = 25, IAS = 75A, VGS =10V. Part not recommended for use above this value. ISD 75A, di/dt 340A/s, VDD V(BR)DSS, TJ 175C. Pulse width 1.0ms; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Limited by T Jmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. This value determined from sample failure population. 100% tested to this value in production. This is applied to D 2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. R is measured at TJ of approximately 90C. 2 www.irf.com http://store.iiic.cc/ IRF2907Z/S/L 1000 10000 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 1000 BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP BOTTOM VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 100 100 4.5V 10 4.5V 60s PULSE WIDTH 60s PULSE WIDTH Tj = 175C Tj = 25C 1 0.1 1 10 10 0.1 100 Fig 1. Typical Output Characteristics 10 100 Fig 2. Typical Output Characteristics 1000 200 Gfs, Forward Transconductance (S) ID, Drain-to-Source Current () 1 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) T J = 175C 100 10 T J = 25C 1 VDS = 25V 60s PULSE WIDTH T J = 25C 150 T J = 175C 100 50 V DS = 10V 380s PULSE WIDTH 0.1 0 2 4 6 8 10 0 25 50 75 100 125 150 ID,Drain-to-Source Current (A) VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance vs. Drain Current www.irf.com 3 http://store.iiic.cc/ IRF2907Z/S/L 100000 12.0 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd ID= 90A 10000 Ciss Coss Crss 1000 VDS= 60V VDS= 38V 10.0 VGS, Gate-to-Source Voltage (V) C, Capacitance(pF) C oss = C ds + C gd VDS= 15V 8.0 6.0 4.0 2.0 100 0.0 1 10 100 0 VDS, Drain-to-Source Voltage (V) 100 150 200 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage Fig 5. Typical Capacitance vs. Drain-to-Source Voltage 10000 ID, Drain-to-Source Current (A) 1000 ISD, Reverse Drain Current (A) 50 1000 T J = 175C 100 TJ = 25C 10 OPERATION IN THIS AREA LIMITED BY R DS(on) 100 100sec 10 1msec 1 10msec Tc = 25C Tj = 175C Single Pulse VGS = 0V 0.1 1 0.0 0.5 1.0 1.5 2.0 1 2.5 100 1000 VDS, Drain-to-Source Voltage (V) VSD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 10 Fig 8. Maximum Safe Operating Area 4 www.irf.com http://store.iiic.cc/ IRF2907Z/S/L 180 160 RDS(on) , Drain-to-Source On Resistance (Normalized) 2.5 Limited By Package ID, Drain Current (A) 140 120 100 80 60 40 20 0 ID = 90A VGS = 10V 2.0 1.5 1.0 0.5 25 50 75 100 125 150 -60 -40 -20 0 175 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (C) T C , Case Temperature (C) Fig 10. Normalized On-Resistance vs. Temperature Fig 9. Maximum Drain Current vs. Case Temperature 1 Thermal Response ( Z thJC ) D = 0.50 0.20 0.10 0.1 0.05 0.02 0.01 0.01 J R1 R1 J 1 C 1 2 2 Ri (C/W) i (sec) 0.251 0.000457 0.199 0.003019 Ci= i/Ri Ci i/Ri SINGLE PULSE ( THERMAL RESPONSE ) 0.001 R2 R2 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 http://store.iiic.cc/ IRF2907Z/S/L DRIVER L VDS D.U.T RG VGS 20V + V - DD IAS tp A 0.01 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS EAS , Single Pulse Avalanche Energy (mJ) 1200 15V ID TOP 10A 14A BOTTOM 75A 1000 800 600 400 200 tp 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) I AS Fig 12c. Maximum Avalanche Energy vs. Drain Current Fig 12b. Unclamped Inductive Waveforms QG 10 V QGS QGD 4.0 Charge Fig 13a. Basic Gate Charge Waveform L DUT 0 VCC VGS(th) Gate threshold Voltage (V) VG 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 1K Fig 13b. Gate Charge Test Circuit ID = 250A 0 25 50 75 100 125 150 175 200 T J , Temperature ( C ) Fig 14. Threshold Voltage vs. Temperature 6 www.irf.com http://store.iiic.cc/ IRF2907Z/S/L 100 Duty Cycle = Single Pulse Avalanche Current (A) 0.01 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses 0.05 10 0.10 1 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 15. Typical Avalanche Current Vs.Pulsewidth 350 TOP Single Pulse BOTTOM 1% Duty Cycle ID = 75A EAR , Avalanche Energy (mJ) 300 250 200 150 100 50 0 25 50 75 100 125 150 Starting T J , Junction Temperature (C) 175 Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asT jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 15, 16). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav ) = Transient thermal resistance, see figure 11) Fig 16. Maximum Avalanche Energy vs. Temperature www.irf.com PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav 7 http://store.iiic.cc/ IRF2907Z/S/L D.U.T Driver Gate Drive + - P.W. + D.U.T. ISD Waveform Reverse Recovery Current + V DD * dv/dt controlled by RG * Driver same type as D.U.T. * I SD controlled by Duty Factor "D" * D.U.T. - Device Under Test P.W. Period * RG D= VGS=10V Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer - Period + Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage - Body Diode VDD Forward Drop Inductor Curent ISD Ripple 5% * VGS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs V DS V GS RG RD D.U.T. + -V DD 10V Pulse Width 1 s Duty Factor 0.1 % Fig 18a. Switching Time Test Circuit VDS 90% 10% VGS td(on) tr t d(off) tf Fig 18b. Switching Time Waveforms 8 www.irf.com http://store.iiic.cc/ IRF2907Z/S/L TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) -B- 3.78 (.149) 3.54 (.139) 4.69 (.185) 4.20 (.165) -A- 1.32 (.052) 1.22 (.048) 6.47 (.255) 6.10 (.240) 4 15.24 (.600) 14.84 (.584) LEAD ASSIGNMENTS 1.15 (.045) MIN 1 2 3 14.09 (.555) 13.47 (.530) IGBTs, CoPACK 2 - DRAIN 1- GATE 3 - SOURCE 2- DRAIN 3- SOURCE 4 - DRAIN 4- DRAIN 1- GATE 2- COLLECTOR 3- EMITTER 4- COLLECTOR 4.06 (.160) 3.55 (.140) 3X 1.40 (.055) 3X 1.15 (.045) LEAD ASSIGNMENTS HEXFET 1 - GATE 0.93 (.037) 0.69 (.027) 0.36 (.014) 3X M B A M 2.92 (.115) 2.64 (.104) 2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH 0.55 (.022) 0.46 (.018) 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information (;$03/( 7+,6,6$1,5) /27&2'( $66(0%/('21:: ,17+($66(0%/