IS62LV12816L/LL 128K x 16 CMOS STATIC RAM FEATURES * High-speed access time: 55, 70, 100 ns * CMOS low power operation 120 mW (typical) operating 6 LW (typical) CMOS standby * TTL compatible interface levels * Single 3V + 10% Vcc power supply Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial temperature available * Available in the 44-pin TSOP (Type II) and 48-pin mini BGA FUNCTIONAL BLOCK DIAGRAM ISST ADVANCE INFORMATION MARCH 1999 DESCRIPTION The /SS/IS62LV12816L and IS62LV12816LL are high-speed, 2,097,152-bit static RAMs organized as 131,072 words by 16 bits. They are fabricated using [SI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CEis HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62LV12816L and IS62LV12816LL are packaged in the JEDECstandard 44-pin TSOP (Type Il) and 48-pin mini BGA. AO-A16 VCC > GND -> 1/00-1/O7 Lower Byte /08-1/015 Upper Byte Bl Sl all 2 DECODER 0 DATA CIRCUIT CONTROL CIRCUIT 128K x 16 MEMORY ARRAY COLUMN I/O The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 1999, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR002-0D 03/02/99IS62LV12816L/LL [SST PIN CONFIGURATIONS 44-Pin TSOP (Type Il) 48-Pin mini BGA 1 2 3 4 5 6 A4 (11 44|-] A5 A3 [2 43{_] A6 A243 42|_] A7 Ai [4 41{-] OE AO Cy 5 oe UB CE 6 39|-] LB voo C7 381 vO15 A @QOO@e WH vo1 C18 37] vo14 voz ()9 36{_] 013 B @OO 03 [J 10 35[-] vo12 Cc Vec [11 34[7] GND end E22 331] Vee D }) &) vo4 (4 13 32(7] vo11 vOo5 (4 14 31{-] O10 E OoOOOOL Hee 4 ee F VO7 16 29|_] 08 WE [[] 17 28{_] NC G CE & & Ai6 [] 18 27|-] As A15 (119 26{] AQ 0 OOOOO Ai4 [20 25{-] A10 A13 (21 24[[] A114 A12 22 23[] NC PIN DESCRIPTIONS A0-A16 Address Inputs LB Lower-byte Control (I/O0-I/07) 00-015 Data Inputs/Outputs UB Upper-byte Control (I/08-1/015) CE Chip Enable Input NC No Connection OE Output Enable Input Vcc Power WE Write Enable Input GND Ground TRUTH TABLE 1/O PIN Mode WE CE OE LB UB 00-07 1/08-I/015 Vcc Current Not Selected Xx H Xx Xx Xx High-Z High-Z IsB1, IsB2 Output Disabled H L H x x High-Z High-Z Icc Xx L Xx H H High-Z High-Z Read H L L L H DoutT High-Z Icc H L L H L High-Z Dout H L L L L Dout Dout Write L L Xx L H DIN High-Z Ico L L Xx H L High-Z DIN L L X L L DIN DIN Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR002-0D 03/02/99IS62LV12816L/LL ISS. OPERATING RANGE Range Ambient Temperature Vcc Commercial 0C to +70C 3.0V + 10% Industrial 40C to +85C 3.0V + 10% ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND 0.5 to Vec+0.5 Vv TBIAS Temperature Under Bias 40 to +85 C Vcc Vcc Related to GND 0.3 to +4.0 Vv TsTG Storage Temperature 65 to +150 C PT Power Dissipation 1.0 WwW Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VoH Output HIGH Voltage Vcc = Min., loH = 1 mA 2.0 _ Vv VoL Output LOW Voltage Vcc = Min., lo. = 2.1 mA _ 0.4 Vv VIH Input HIGH Voltage 2.2 Veco + 0.2 Vv vii) Input LOW Voltage -0.2 0.4 Vv Iu Input Leakage GND < Vin s Vec 1 1 LA ILo Output Leakage GND < Vout < Vcc, Outputs Disabled 1 1 LA Notes: 1. Vit (min.) = -2.0V for pulse width less than 10 ns. CAPACITANCE Symbol Parameter Conditions Max. Unit CIN Input Capacitance Vin = OV 6 pF Cout Input/Output Capacitance Vout = OV 8 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. Integrated Silicon Solution, Inc. 1-800-379-4774 3 ADVANCE INFORMATION SR002-0D 03/02/99[SST IS62LV12816L/LL AC TEST CONDITIONS Parameter Unit Input Pulse Level 0.4V to 2.2V Input Rise and Fall Times 5ns Input and Output Timing 1.5V and Reference Level Output Load See Figures 1 and 2 AC TEST LOADS 2.8V OUTPUT 3070 3150 3070 2.8V OUTPUT 100 pF 5 pF 3150 Including L Including jig and jig and scope = = scope = = Figure 1 Figure 2 IS62LV12816L POWER SUPPLY CHARACTERISTICS" (Over Operating Range) -55 -70 -100 Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit Icc Vec Dynamic Operating Vcc = Max., Com. 40 30 20 mA Supply Current lout = 0 mA, f = fiuax Ind. 60 50 40 IsB1 TTL Standby Current Vcc = Max., Com. 04 04 04 mA (TTL Inputs) Vin = ViH or VIL Ind. 1.0 1.0 1.0 CE2>Vi,f=0 IsB2 CMOS Standby Vcc = Max., Com. 16 16 16 LA Current (CMOS Inputs) CE > Vcc -0.2V, Ind. 25 2 2 Vin = Voc 0.2V, or Vin <0.2V, f=0 Note: 1. At f =fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. IS62LV12816LL POWER SUPPLY CHARACTERISTICS (Over Operating Range) -55 -70 -100 Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit Icc Vec Dynamic Operating Vcc = Max., Com. 40 30 20 mA Supply Current lout = 0 mA, f = fiuax Ind. 60 50 40 IsB1 TTL Standby Current Vcc = Max., Com. 04 04 04 mA (TTL Inputs) Vin = ViH or VIL Ind. 1.0 1.0 1.0 CE2>Vi,f=0 IsB2 CMOS Standby Vcc = Max., Com. 5 5 5 LA Current (CMOS Inputs) CE > Vcc -0.2V, Ind. 10 10 10 Vin = Voc 0.2V, or Vin <0.2V, f=0 Note: 1. At f =fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR002-0D 03/02/89ISSP IS62LV12816L/LL READ CYCLE SWITCHING CHARACTERISTICS" (Over Operating Range) -55 -70 -100 Symbol Parameter Min. Max Min. Max. Min. Max. Unit tac Read Cycle Time 55 70 100 ns TAA Address Access Time _ 55 _ 70 100 ns TOHA Output Hold Time 10 10 15 ns tace CE Access Time 55 70 100 ns toe OE Access Time 30 35 50 ns tyzoe OE to High-Z Output 20 25 30 ns t.zoe OE to Low-Z Output 5 ns tuzce CE to High-Z Output 0 20 25 30 ns tizce CE to Low-Z Output 10 10 10 ns tea LB, UB Access Time 20 35 50 ns tuze LB, UB to High-Z Output 0 25 25 35 ns tizB LB, UB to Low-Z Output 0 0 0 ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4 to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured +500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 12) (Address Controlled) (CE = OE = Vit, UB or LB = Vi) <a tRC | ADDRESS x Lad tAA tOHA }t TOHA DOUT PREVIOUS DATA VALID DATA VALID Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR002-0D 03/02/99IS62LV12816L/LL ISS? AC WAVEFORMS READ CYCLE NO. 2") ADDRESS DOUT DATA VALID Notes: 1. WE is HIGH for a Read Cycle. ee 2. The device is continuously selected. OE, CE, UB, or LB = Vi. 3. Address is valid prior to or coincident with CE LOW transition. WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -55 -70 -100 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit twe Write Cycle Time 55 70 100 ns tsce CE to Write End 45 65 80 ns taw Address Setup Time to Write End 45 _ 65 _ 80 _ ns THA Address Hold from Write End 0 _ 0 _ 0 ns tsa Address Setup Time 0 0 0 ns tewe LB, UB Valid to End of Write 50 60 80 ns tewe WE Pulse Width 50 60 80 ns tsp Data Setup to Write End 25 30 40 ns THD Data Hold from Write End 0 0 0 ns tuzwe) = WE LOW to High-Z Output 30 30 40 ns tzwe = WEHIGH to Low-Z Output 5 5 5 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. __ _ __ 2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured +500 mV from steady-state voltage. Not 100% tested. 6 Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR002-0D 03/02/89IS62LV12816L/LL ISSP AC WAVEFORMS WRITE CYCLE NO. 1?) (WE Controlled) ADDRESS twc - tSCE | a wt tHA / tPWB tAW v a LB, UB Tk nn WRITE) 7 |< tS A_ ~ tPWE a {sD r 1 ip DIN K tHZWE <> DOUT 4 _ UNDEFINED , HIGH-Z <<__ {LZWE UNDEFINED Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit Vor Vcc for Data Retention See Data Retention Waveform 1.5 3.3 V IDR Data Retention Current Vec = 2.0V, CE> Vec -0.2V 15 LA tspR Data Retention Setup Time See Data Retention Waveform 0 _ ns tRoR Recovery Time See Data Retention Waveform trc ns DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode | tRDR Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR002-0D 03/02/99IS62LV12816L/LL [SST ORDERING INFORMATION Commercial Range: 0C to +70C Industrial Range: 40C to +85C Speed (ns) Order Part No. Package 55 IS62LV12816L-55T TSOP (Type II) IS62LV12816L-55B = Mini BGA 70 IS62LV12816L-70T TSOP (Type II) IS62LV12816L-70B Mini BGA 100 IS62LV12816L-100T TSOP (Type II) IS62LV12816L-100B Mini BGA Speed (ns) Order Part No. Package 55 IS62LV12816L-55TI TSOP (Type II) IS62LV12816L-55BI Mini BGA 70 IS62LV12816L-70TI| TSOP (Type II) IS62LV12816L-70BI Mini BGA 100 IS62LV12816L-100TI TSOP (Type II) IS62LV12816L-100BI Mini BGA ORDERING INFORMATION Commercial Range: 0C to +70C Speed (ns) Order Part No. Package 55 IS62LV12816LL-55T TSOP (Type II) IS62LV12816LL-55B Mini BGA 70 IS62LV12816LL-70T TSOP (Type II) IS62LV12816LL-70B Mini BGA 100 IS62LV12816LL-100T TSOP (Type II) IS62LV12816LL-100B Mini BGA Industrial Range: 40C to +85C Speed (ns) Order Part No. Package 55 IS62LV12816LL-55TI| TSOP (Type Il) IS62LV12816LL-55BI Mini BGA 70 IS62LV12816LL-70TI| TSOP (Type Il) IS62LV12816LL-70BI Mini BGA 100 1S62LV12816LL-100Tl TSOP (Type II) IS62LV12816LL-100BI Mini BGA ISST Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com Integrated Silicon Solution, Inc. 1-800-379-4774 ADVANCE INFORMATION SR002-0D 03/02/99