March 2011 I
© 2010 Microsemi Corporation
SmartFusion Intelligent Mixed Signal FPGAs
Microcontroller Subsystem (MSS)
• Hard 100 MHz 32-Bit ARM® Cortex™-M3
– 1.25 DMIPS/MHz Throughput from Zero Wait State
Memory
– Memory Protection Unit (MPU)
– Single Cycle Multiplication, Hardware Divide
– JTAG Debug (4 wires), Serial Wire Debug (SWD, 2
wires), and Single Wire Viewer (SWV) Interfaces
• Internal Memory
– Embedded Nonvolatile Flash Memory (eNVM), 128
Kbytes to 512 Kbytes
– Embedded High-Speed SRAM (eSRAM), 16 Kbytes
to 64 Kbytes, Implemented in 2 Physical Blocks to
Enable Simultaneous Access from 2 Different
Masters
• Multi-Layer AHB Communications Matrix
– Provides up to 16 Gbps of On-Chip Memory
Bandwidth,1 Allowing Multi-Master Schemes
• 10/100 Ethernet MAC with RMII Interface2
• Programmable External Memory Controller, Which
Supports:
– Asynchronous Memories
– NOR Flash, SRAM, PSRAM
– Synchronous SRAMs
•Two I
2C Peripherals
• Two 16550 Compatible UARTs
• Two SPI Peripherals
• Two 32-Bit Timers
• 32-Bit Watchdog Timer
• 8-Channel DMA Controller to Offload the Cortex-M3
from Data Transactions
• Clock Sources
– 32 KHz to 20 MHz Main Oscillator
– Battery-Backed 32 KHz Low Power Oscillator with
Real-Time Counter (RTC)
– 100 MHz Embedded RC Oscillator; 1% Accurate
– Embedded Analog PLL with 4 Output Phases (0, 90,
180, 270)
High-Performance FPGA
• Based on proven ProASIC®3 FPGA Fabric
• Low Power, Firm-Error Immune 130-nm, 7-Layer Metal,
Flash-Based CMOS Process
• Nonvolatile, Live at Power-Up, Retains Program When
Powered Off
• 350 MHz System Performance
• Embedded SRAMs and FIFOs
– Variable Aspect Ratio 4,608-Bit SRAM Blocks
– x1, x2, x4, x9, and x18 Organizations
– True Dual-Port SRAM (excluding x18)
– Programmable Embedded FIFO Control Logic
• Secure ISP with 128-Bit AES via JTAG
• FlashLock® to Secure FPGA Contents
• Five Clock Conditioning Circuits (CCCs) with up to 2
Integrated Analog PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
– Frequency: Input 1.5–350 MHz, Output 0.75 to
350 MHz
Programmable Analog
Analog Front-End (AFE)
• Up to Three 12-Bit SAR ADCs
– 500 Ksps in 12-Bit Mode
– 550 Ksps in 10-Bit Mode
– 600 Ksps in 8-Bit Mode
• Internal 2.56 V Reference or Optional External
Reference
• One First-Order ΣΔ DAC (sigma-delta) per ADC
– 12-Bit 500 Ksps Update Rate
• Up to 5 High-Performance Analog Signal Conditioning
Blocks (SCB) per Device, Each Including:
– Two High-Voltage Bipolar Voltage Monitors (with 4
input ranges from ±2.5 V to –11.5/+14 V) with 1%
Accuracy
– High Gain Current Monitor, Differential Gain = 50, up
to 14 V Common Mode
– Temperature Monitor (Resolution = ¼°C in 12-Bit
Mode; Accurate from –55°C to 150°C)
• Up to Ten High-Speed Voltage Comparators
(tpd =15ns)
Analog Compute Engine (ACE)
• Offloads Cortex-M3–Based MSS from Analog
Initialization and Processing of ADC, DAC, and SCBs
• Sample Sequence Engine for ADC and DAC Parameter
Set-Up
• Post-Processing Engine for Functions such as Low-
Pass Filtering and Linear Transformation
• Easily Configured via GUI in Libero® Integrated Design
(IDE) Software
I/Os and Operating Voltage
• FPGA I/Os
– LVDS, PCI, PCI-X, up to 24 mA IOH/IOL
– Up to 350 MHz
• MSS I/Os
– Schmitt Trigger, up to 6 mA IOH, 8 mA IOL
– Up to 180 MHz
• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
• External 1.5 V Is Allowed by Bypassing Regulator
(digital VCC = 1.5 V for FPGA and MSS, analog VCC =
3.3 V and 1.5 V)
1 Theoretical maximum
2 A2F200 and larger devices
Revision 6
SmartFusion Intelligent Mixed Signal FPGAs
II Revision 6
SmartFusion Family Product Table
SmartFusion Devic e A2F0601A2F200 A2F500
FPGA Fabric System Gates 60,000 200,000 500,000
Tiles (D-flip-flops) 1,536 4,608 11,520
RAM Blocks (4,608 bits) 8 8 24
Microcontroller
Subsystem (MSS)
Flash (Kbytes) 128 256 512
SRAM (Kbytes) 16 64 64
Cortex-M3 with memory protection unit (MPU) Yes
10/100 Ethernet MAC No Yes
External Memory Controller (EMC) 24-bit address,16-bit data
DMA 8 Ch
I2C 2
SPI 2
16550 UART 2
32-Bit Timer 2
PLL 1 1 23
32 KHz Low Power Oscillator 1
100 MHz On-Chip RC Oscillator 1
Main Oscillator (32 KHz to 20 MHz) 1
Programmable
Analog
ADCs (8-/10-/12-bit SAR) 1 2 34
DACs (12-bit sigma-delta) 1 2 34
Signal Conditioning Blocks (SCBs) 1 4 54
Comparators2 28 10
4
Current Monitors2 14 5
4
Temperature Monitors214 5
4
Bipolar High Voltage Monitors228 10
4
Notes:
1. Under definition; subject to change.
2. These functions share I/O pins and ma y not all be available at the same time. See the "Analog Front-End Overvie w" secti on in
the SmartFusion Prog ra mma b l e An al o g Us er’s Guide for details.
3. Two PLLs are available in CS288 and FG484 (one PLL in FG256 and PQ208).
4. Available on FG484 only. PQ2 08, FG256, and CS288 packages offer the same programmable analog capabilities as A2F200.
SmartFusion Intelligent Mixe d Si gn a l FPG As
Revisi o n 6 III
Package I/Os: MSS + FPGA I/Os
SmartFusion Device Status
Device A2F060 A2F200 A2F500
Package CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484
Direct Analog Inputs 6 6 8 8 8 8 8 8 8 12
Shared Analog Inputs14 4 16 16 16 16 16 16 16 20
Total Analog Inputs 10 10 24 24 24 24 24 24 24 32
Total Analog Outputs 1 1 1 2 2 2 1 2 2 3
MSS I/Os2,3 28425422 31 25 41 22 31 25 41
FPGA I/Os 68 66 66 78 66 94 66 78 66 128
Total I/Os 107 102 113 135 117 161 113 135 117 204
Notes:
1. These pins are shared between direct analog inp uts to the ADCs and voltage/current/temperatu r e monitors.
2. 16 MSS I/Os are multip lexed and can be u sed as FPGA I/Os, if not needed for MSS. These I/Os support Schmitt triggers and
support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V) standards.
3. 9 MSS I/Os are primarily for 10/100 Ethernet MAC and are a lso multiplexed and can be used as FPGA I/Os if Ethernet MAC is
not used in a design. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V
standards.
4. 10/100 Ethernet MAC is not available on A2F060.
Device Status
A2F060 Advance
A2F200 Production: FG256, FG484
Preliminary: CS288
Advance: PQ208
A2F500 Production: FG256, FG484
Preliminary: CS288
Advance: PQ208
SmartFusion Intelligent Mixed Signal FPGAs
IV Revision 6
SmartFusion Block Diagram
Legend:
SDD – Sigma-delta DAC
SCB – Signal conditioning block
PDMA – Peripheral DMA
IAP – In-application programming
ABPS – Active bipolar prescaler
WDT – Watchdog Timer
SWD – Serial Wire Debug
Microcontroller Subsystem
Programmable Analog
FPGA Fabric
SRAM SRAM SRAM SRAM SRAM SRAM
SysReg
ENVM
10/100
EMAC
ESRAM
Timer2
Timer1
APB
I2C 2
UART 2
SPI 2
DAC
(SDD)
DAC
(SDD)
PPB
........
........
............
VersaTiles
3 V
I2C 1
UART 1
SPI 1
IAP PDMA APB EMC
AHB Bus Matrix
EFROM
APB
Sample Sequencing
Engine
Post Processing
Engine
ADC
Analog Compute
Engine
PLL
Supervisor
WDT
OSC
32 KHz
RC
+
–
RTC
JTAG
Cortex™
-M3
SWD
NVIC SysTick
MPU
SD I
Volt Mon.
(ABPS)
Temp.
Mon.
SCB
Curr.
Mon. Comparator
ADC
Volt Mon.
(ABPS)
Temp.
Mon.
SCB
Curr.
Mon. Comparator
3
V
............
....
SmartFusion Intelligent Mixe d Si gn a l FPG As
Revisi o n 6 V
SmartFusion System Architecture
Note: Architecture for A2F500
Bank 4 Bank 5
Bank 0
Bank 3
Bank 1 Bank 2
PLL/CCC MSS FPGA Analog
ISP AES Decryption Charge Pumps
Embedded NVM
(eNVM)
Cortex-M3 Microcontroller Subsystem (MSS)
Embedded SRAM
(eSRAM)
Embedded FlashROM
(eFROM)
SCB SCB ADC and DAC ADC and DAC SCB SCB
Osc. CCC
SmartFusion Intelligent Mixed Signal FPGAs
VI Revision 6
Product Ordering Codes
Temperature Grade Offerings
Note: *Most devices in the SmartFusion family can be ordered with the Y suffix. Devices with a package size greater or equal to 5x5
mm are supported. Contact your local Microsemi SoC Products Group sales represe ntative for more information.
SmartFusion Devic es A2F060 A2F200 A2F500
PQ208 – C, I C, I
CS288 C, I C, I C, I
FG256 C, I C, I C, I
FG484 – C, I C, I
Notes:
1. C = Commercial Temperature Range: 0°C to 85°C Junction
2. I = Industrial Temperature Range: –40°C to 100°C Junction
A2F200 FG
_
Part Number
SmartFusion Devices
Speed Grade
–1 = 100 MHz MSS Speed; FPGA Fabric 15% Faster than Standard
= 80 MHz MSS Speed; FPGA Fabric at Standard Speed
CPU Type
M3
M3 = Cortex-M3
Package Type
484 IG
Package Lead Count
256
208
288
484
Application (junction temperature range)
Y
Security Feature*
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Commercial (0 to +85°C)
I = Industrial (–40 to +100°C)
ES = Engineering Silicon (room temperature only)
200,000 System Gates
A2F200 =
60,000 System Gates
A2F060 =
500,000 System Gates
A2F500 =
PQ =Plastic Quad Flat Pack (0.5 mm pitch)
FG =Fine Pitch Ball Grid Array (1.0 mm pitch)
CS =Chip Scale Package (0.5 mm pitch)
F
eNVM Size
A= 8 Kbytes
B=16 Kbytes
C=32 Kbytes
D=64 Kbytes
E=128 Kbytes
F=256 Kbytes
G=512 Kbytes
Lead-Free Packaging Options
H = Halogen-Free Packaging
G = RoHS-Compliant (green) Packaging
Blank = Standard Packaging
1
Blank
SmartFusion Intelligent Mixed Signal FPGAs
Revisi o n 5
Table of Content s
SmartFusion Device Family Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SmartFusion DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61
Main and Lower Power Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
FPGA Fabric SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
Embedded Nonvolatile Memory Block (eNVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73
Embedded FlashROM (eFROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-74
Programmable Analog Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75
Serial Peripheral Interface (SPI) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86
Inter-Integrated Circuit (I2C) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88
SmartFusion Development Tools
SmartFusion Ecosystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Software Integrated Design Environment (IDE) Choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Operating System and Middleware Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
SmartFusion Programming
In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
In-Application Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Typical Programming and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Pin Descriptions
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Microcontroller Subsystem (MSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Analog Front-End (AFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Analog Front-End Pin-Level Function Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
288-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
Table of Contents
Revision 5
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Microsemi SoC Products Group Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . 6-8
Revision 6 1-1
1 – SmartFusion Device Family Overview
Introduction
The SmartFusion family of intelligent mixed signal FPGAs builds on the technology first introduced with
the Fusion mixed signal FPGAs. SmartFusion devices are made possible by integrating FPGA
technology with programmable high-performance analog and hardened ARM® Cortex™-M3
microcontroller blocks on a flash semiconductor process. The SmartFusion family takes its name from
the fact that these three discrete technologies are integrated on a single chip, enabling the lowest cost of
ownership and smallest footprint solution to you.
General Description
Microcontroller Subsystem (MSS)
The MSS is composed of a 100 MHz Cortex-M3 processor and integrated peripherals, which are
interconnected via a multi-layer AHB bus matrix (ABM). This matrix allows the Cortex-M3 processor,
FPGA fabric master, Ethernet message authentication controller (MAC), when available, and peripheral
DMA (PDMA) controller to act as masters to the integrated peripherals, FPGA fabric, embedded
nonvolatile memory (eNVM), embedded synchronous RAM (eSRAM), external memory controller
(EMC), and analog compute engine (ACE) blocks.
SmartFusion devices of different densities offer various sets of integrated peripherals. Available
peripherals include SPI, I2C, and UART serial ports, embedded FlashROM (EFROM), 10/100 Ethernet
MAC, timers, phase-locked loops (PLLs), oscillators, real-time counters (RTC), and peripheral DMA
controller (PDMA).
Programmable Analog
Analog Front-End (AFE)
SmartFusion devices offer an enhanced analog front-end compared to Fusion devices. The successive
approximation register analog-to-digital converters (SAR ADC) are similar to those found on Fusion
devices. SmartFusion also adds first order sigma-delta digital-to-analog converters (SDD DAC).
SmartFusion can handle multiple analog signals simultaneously with its signal conditioning blocks
(SCBs). SCBs are made of a combination of active bipolar prescalers (ABPS), comparators, current
monitors and temperature monitors. ABPS modules allow larger bipolar voltages to be fed to the ADC.
Current monitors take the voltage across an external sense resistor and convert it to a voltage suitable
for the ADC input range. Similarly, the temperature monitor reads the current through an external PN-
junction (diode or transistor) and converts it internally for the ADC. The SCB also includes comparators
to monitor fast signal thresholds without using the ADC. The output of the comparators can be fed to the
analog compute engine or the ADC.
Analog Compute Engine (ACE)
The mixed signal blocks found in SmartFusion are controlled and connected to the rest of the system via
a dedicated processor called the analog compute engine (ACE). The role of the ACE is to offload control
of the analog blocks from the Cortex-M3, thus offering faster throughput or better power consumption
compared to a system where the main processor is in charge of monitoring the analog resources. The
ACE is built to handle sampling, sequencing, and post-processing of the ADCs, DACs, and SCBs.
SmartFusion Device Family Overview
1-2 Revision 6
ProASIC3 FPGA Fabric
The SmartFusion family, based on the proven, low power, firm-error immune ProASIC®3 flash FPGA
architecture, benefits from the advantages only flash-based devices offer:
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flash-
based SmartFusion devices are live at power-up and do not need to be loaded from an external boot
PROM at each power-up. On-board security mechanisms prevent access to the programming
information and enable secure remote updates of the FPGA logic. Designers can perform secure remote
in-system programming (ISP) to support future design iterations and critical field upgrades, with
confidence that valuable IP cannot be compromised or copied. Secure ISP can be performed using the
industry standard AES algorithm with MAC data authentication on the device.
Low Power
Flash-based SmartFusion devices exhibit power characteristics similar to those of an ASIC, making them
an ideal choice for power-sensitive applications. With SmartFusion devices, there is no power-on current
and no high current transition, both of which are common with SRAM-based FPGAs.
SmartFusion devices also have low dynamic power consumption and support very low power time-
keeping mode, offering further power savings.
Security
As the nonvolatile, flash-based SmartFusion family requires no boot PROM, there is no vulnerable
external bitstream. SmartFusion devices incorporate FlashLock®, which provides a unique combination
of reprogrammability and design security without external overhead, advantages that only an FPGA with
nonvolatile flash programming can offer.
SmartFusion devices utilize a 128-bit flash-based key lock and a separate AES key to secure
programmed IP and configuration data. The FlashROM data in Fusion devices can also be encrypted
prior to loading. Additionally, the flash memory blocks can be programmed during runtime using the AES-
128 block cipher encryption standard (FIPS Publication 192).
SmartFusion devices with AES-based security allow for secure remote field updates over public
networks, such as the Internet, and ensure that valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves. As an additional security measure, the FPGA configuration
data of a programmed Fusion device cannot be read back, although secure design verification is
possible. During design, the user controls and defines both internal and external access to the flash
memory blocks.
Security, built into the FPGA fabric, is an inherent component of the SmartFusion family. The flash cells
are located beneath seven metal layers, and many device design and layout techniques have been used
to make invasive attacks extremely difficult. SmartFusion with FlashLock and AES security is unique in
being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected, making
secure remote ISP possible. A SmartFusion device provides the most impenetrable security for
programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based SmartFusion
FPGAs do not require system configuration components such as electrically erasable programmable
read-only memories (EEPROMs) or microcontrollers to load device configuration data during power-up.
This reduces bill-of-materials costs and PCB area, and increases system security and reliability.
Live at Power-Up
Flash-based SmartFusion devices are live at power-up (LAPU). LAPU SmartFusion devices greatly
simplify total system design and reduce total system cost by eliminating the need for complex
programmable logic devices (CPLDs). SmartFusion LAPU clocking (PLLs) replaces off-chip clocking
resources. In addition, glitches and brownouts in system power will not corrupt the SmartFusion device
flash configuration. Unlike SRAM-based FPGAs, the device will not have to be reloaded when system
power is restored. This enables reduction or complete removal of expensive voltage monitor and
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 1-3
brownout detection devices from the PCB design. Flash-based SmartFusion devices simplify total
system design and reduce cost and design risk, while increasing system reliability.
Immunity to Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the atmosphere, strike a
configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O configuration behavior in an unpredictable
way.
Another source of radiation-induced firm errors is alpha particles. For alpha radiation to cause a soft or
firm error, its source must be in very close proximity to the affected circuit. The alpha source must be in
the package molding compound or in the die itself. While low-alpha molding compounds are being used
increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors.
Firm errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not occur in SmartFusion flash-based FPGAs. Once it is
programmed, the flash cell configuration element of SmartFusion FPGAs cannot be altered by high
energy neutrons and is therefore immune to errors from them. Recoverable (or soft) errors occur in the
user data SRAMs of all FPGA devices. These can easily be mitigated by using error detection and
correction (EDAC) circuitry built into the FPGA fabric.
Revision 6 2-1
2 – SmartFusion DC and Switching Characteristics
General Specifications
Operating Conditions
Stresses beyond the operating conditions listed in Table 2-1 may cause permanent damage to the
device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in
Table 2-3 on page 2-3 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol Parameter Limits Units
VCC DC core supply voltage –0.3 to 1.65 V
VJTAG JTAG DC voltage –0.3 to 3.75 V
VPP Programming voltage –0.3 to 3.75 V
VCCPLLx Analog power supply (PLL) –0.3 to 1.65 V
VCCFPGAIOBx DC FPGA I/O buffer supply voltage –0.3 to 3.75 V
VCCMSSIOBx DC MSS I/O buffer supply voltage –0.3 to 3.75 V
VI I/O input voltage –0.3 V to 3.6 V
(when I/O hot insertion mode is enabled)
–0.3 V to (VCCxxxxIOBx + 1 V) or 3.6 V,
whichever voltage is lower (when I/O hot-
insertion mode is disabled)
V
VCC33A Analog clean 3.3 V supply to the analog
circuitry
–0.3 to 3.75 V
VCC33ADCx Analog 3.3 V supply to ADC –0.3 to 3.75 V
VCC33AP Analog clean 3.3 V supply to the charge pump –0.3 to 3.75 V
VCC33SDDx Analog 3.3 V supply to the sigma-delta DAC –0.3 to 3.75 V
VAREFx Voltage reference for ADC 1.0 to 3.75 V
VCCRCOSC Analog supply to the integrated RC oscillator –0.3 to 3.75 V
VDDBAT External battery supply –0.3 to 3.75 V
VCCMAINXTAL Analog supply to the main crystal oscillator –0.3 to 3.75 V
VCCLPXTAL Analog supply to the low power 32 kHz crystal
oscillator
–0.3 to 3.75 V
VCCENVM Embedded nonvolatile memory supply –0.3 to 1.65 V
VCCESRAM Embedded SRAM supply –0.3 to 1.65 V
VCC15A Analog 1.5 V supply to the analog circuitry –0.3 to 1.65 V
VCC15ADCx Analog 1.5 V supply to the ADC –0.3 to 1.65 V
Note: The device should be operated within the limits specified by the datasheet. During transitions, the input signal
may undershoot or overshoot according to the limits shown in Table 2-5 on page 2-4.
SmartFusion DC and Switching Characteristics
2-2 Revision 6
Table 2-2 • Analog Maximum Ratings
Parameter Conditions Min. Max. Units
ABPS[n] pad voltage (relative to ground) GDEC[1:0] = 00 (±15.36 V range)
Absolute maximum –11.5 14.4 V
Recommended –11 14 V
GDEC[1:0] = 01 (±10.24 V range) –11.5 12 V
GDEC[1:0] = 10 (±5.12 V range) –6 6 V
GDEC[1:0] = 11 (±2.56 V range) –3 3 V
CM[n] pad voltage relative to ground) CMB_DI_ON = 0 (ADC isolated)
COMP_EN = 0 (comparator off, for the
associated even-numbered comparator)
Absolute maximum –0.3 14.4 V
Recommended –0.3 14 V
CMB_DI_ON = 0 (ADC isolated)
COMP_EN = 1 (comparator on)
–0.3 3 V
TMB_DI_ON = 1 (direct ADC in) –0.3 3 V
TM[n] pad voltage (relative to ground) TMB_DI_ON = 0 (ADC isolated)
COMP_EN = 1(comparator on)
–0.3 3 V
TMB_DI_ON = 1 (direct ADC in) –0.3 3 V
ADC[n] pad voltage (relative to ground) –0.3 3.6 V
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-3
Table 2-3 • Recommended Op eratin g Co nditions
Symbol Parameter1Commercial Industrial Units
TJJunction temperature 0 to +85 –40 to +100 °C
VCC 21.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V
VJTAG JTAG DC voltage 1.425 to 3.6 1.425 to 3.6 V
VPP Programming voltage Programming mode 3.15 to 3.45 3.15 to 3.45 V
Operation3 0 to 3.6 0 to 3.6 V
VCCPLLx Analog power supply (PLL) 1.425 to 1.575 1.425 to 1.575 V
VCCFPGAIOBx/
VCCMSSIOBx4
1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V
1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V
2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V
3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V
LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V
LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V
VCC33A5Analog clean 3.3 V supply to the analog circuitry 3.15 to 3.45 3.15 to 3.45 V
VCC33ADCx5Analog 3.3 V supply to ADC 3.15 to 3.45 3.15 to 3.45 V
VCC33AP5Analog clean 3.3 V supply to the charge pump 3.15 to 3.45 3.15 to 3.45 V
VCC33SDDx5Analog 3.3 V supply to sigma-delta DAC 3.15 to 3.45 3.15 to 3.45 V
VAREFx Voltage reference for ADC 2.527 to 3.3 2.527 to 3.3 V
VCCRCOSC Analog supply to the integrated RC oscillator 3.15 to 3.45 3.15 to 3.45 V
VDDBAT External battery supply 2.7 to 3.63 2.7 to 3.63 V
VCCMAINXTAL5Analog supply to the main crystal oscillator 3.15 to 3.45 3.15 to 3.45 V
VCCLPXTAL5Analog supply to the low power 32 KHz crystal
oscillator
3.15 to 3.45 3.15 to 3.45 V
VCCENVM Embedded nonvolatile memory supply 1.425 to 1.575 1.425 to 1.575 V
VCCESRAM Embedded SRAM supply 1.425 to 1.575 1.425 to 1.575 V
VCC15A2Analog 1.5 V supply to the analog circuitry 1.425 to 1.575 1.425 to 1.575 V
VCC15ADCx2 Analog 1.5 V supply to the ADC 1.425 to 1.575 1.425 to 1.575 V
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,
VCC15A, and VCC15ADCx.
3. VPP can be left floating during operation (not programming mode).
4. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-18 on page 2-23. VCCxxxxIOBx should be at the same voltage within a given I/O bank.
5. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,
VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.
SmartFusion DC and Switching Characteristics
2-4 Revision 6
Power Supply Sequencing Requirement
SmartFusion devices have an on-chip 1.5 V regulator, but usage of an external 1.5 V supply is also
allowed while the on-chip regulator is disabled. In that case, the 3.3 V supplies (VCC33A, etc.) should be
powered before 1.5 V (VCC, etc.) supplies. The 1.5 V supplies should be enabled only after 3.3 V
supplies reach a value higher than 2.7 V.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every SmartFusion® device. These
circuits ensure easy transition from the powered-off state to the powered-up state of the device. The
many different supplies can power up in any sequence with minimized current spikes or surges. In
addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in
Figure 2-1 on page 2-6.
There are five regions to consider during power-up.
SmartFusion I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCxxxxIOBx are above the minimum specified trip points (Figure 2-1 on page 2-6).
2. VCCxxxxIOBx > VCC – 0.75 V (typical)
Table 2-4 • FPGA and Embedded Flash Programming, Storage and Operating Limits
Product Grade Storag e Tempera ture Element Grade Programming
Cycles Retention
Commercial Min. TJ = 0°C FPGA/FlashROM 500 20 years
Min. TJ = 85°C Embedded Flash < 1,000 20 years
< 10,000 10 years
< 15,000 5 years
Industrial Min. TJ = –40°C FPGA/FlashROM 500 20 years
Min. TJ = 100°C Embedded Flash < 1,000 20 years
< 10,000 10 years
< 15,000 5 years
Table 2-5 • Overshoot and Undershoot Limits 1
VCCxxxxIOBx Average VCCxxxxIOBx–GND Overshoot or Undershoot
Duration as a Percentage of Clock Cycle2Maximum Overshoot/
Undershoot2
2.7 V or less 10% 1.4 V
5% 1.49 V
3 V 10% 1.1 V
5% 1.19 V
3.3 V 10% 0.79 V
5% 0.88 V
3.6 V 10% 0.45 V
5% 0.54 V
Notes:
1. Based on reliability requiremen ts at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
3. This table does not provide PCI overshoot/undershoot limits.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-5
3. Chip is in the SoC Mode.
VCCxxxxIOBx Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCxxxxIOBx ramp-up trip points are about 100 mV higher than ramp-down trip points. This
specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the
following:
• During programming, I/Os become tristated and weakly pulled up to VCCxxxxIOBx.
• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
PLL Behavior at Brownout Condition
The Microsemi SoC Products Group recommends using monotonic power supplies or voltage regulators
to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and
VCCPLLx exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case
(see Figure 2-1 on page 2-6 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down
Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for
information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
Output buffers, after 200 ns delay from input buffer activation
SmartFusion DC and Switching Characteristics
2-6 Revision 6
Figure 2-1 • I/O State as a Function of VCCxxxxIOBx and VCC Voltage Levels
VCCxxxxIOBx
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCxxxxIOBx
/ V
CC
are
below specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Min VCCxxxxIOBx datasheet specification
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
VCC
VCC = 1.425 V
Region 1: I/O Buffers are OFF
Activation trip point:
V
a
= 0.85 V ± 0.25 V
Deactivation trip point:
V
d
= 0.75 V ± 0.25 V
Activation trip point:
V
a
= 0.9 V ± 0.3 V
Deactivation trip point:
V
d
= 0.8 V ± 0.3 V
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL , VOH / VOL , etc.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential
but slower because
below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCCxxxxIOBx
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
VCC = VCCxxxxIOBx + VT
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-7
Thermal Characteristics
Introduction
The temperature variable in the SoC Products Group Designer software refers to the junction
temperature, not the ambient, case, or board temperatures. This is an important distinction because
dynamic and static power consumption will cause the chip's junction temperature to be higher than the
ambient, case, or board temperatures. EQ 1 through EQ 3 give the relationship between thermal
resistance, temperature gradient, and power.
EQ 1
EQ 2
EQ 3
where
θJA = Junction-to-air thermal resistance
θJB = Junction-to-board thermal resistance
θJC = Junction-to-case thermal resistance
TJ= Junction temperature
TA= Ambient temperature
TB= Board temperature (measured 1.0 mm away from the
package edge)
TC= Case temperature
P = Total power dissipated by the device
Table 2-6 • Package Thermal Resistance
Product
Die Size θJA
θJC θJB Units(mm) Still Air 1.0 m/s 2.5 m/s
A2F200M3F-FG256 X = 4.0; Y = 5.6 33.7 30.0 28.3 9.3 24.8 °C/W
A2F200M3F-FG484 X = 5.10; Y = 7.3 21.8 18.2 16.7 7.7 16.8 °C/W
θJA
TJθA
–
P
------------------=
θJB
TJTB
–
P
-------------------=
θJC
TJTC
–
P
-------------------=
SmartFusion DC and Switching Characteristics
2-8 Revision 6
Theta-JA
Junction-to-ambient thermal resistance (θJA) is determined under standard conditions specified by
JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with
caution but is useful for comparing the thermal performance of one package to another.
A sample calculation showing the maximum power dissipation allowed for the A2F200-FG484 package
under forced convection of 1.0 m/s and 75°C ambient temperature is as follows:
EQ 4
where
EQ 5
The power consumption of a device can be calculated using the Microsemi SoC Products Group power
calculator. The device's power consumption must be lower than the calculated maximum power
dissipation by the package. If the power consumption is higher than the device's maximum allowable
power dissipation, a heat sink can be attached on top of the case, or the airflow inside the system must
be increased.
Theta-JB
Junction-to-board thermal resistance (θJB) measures the ability of the package to dissipate heat from the
surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance
from junction to board uses an isothermal ring cold plate zone concept. The ring cold plate is simply a
means to generate an isothermal boundary condition at the perimeter. The cold plate is mounted on a
JEDEC standard board with a minimum distance of 5.0 mm away from the package edge.
Theta-JC
Junction-to-case thermal resistance (θJC) measures the ability of a device to dissipate heat from the
surface of the chip to the top or bottom surface of the package. It is applicable for packages used with
external heat sinks. Constant temperature is applied to the surface in consideration and acts as a
boundary condition. This only applies to situations where all or nearly all of the heat is dissipated through
the surface in consideration.
Calculation for Heat Sink
For example, in a design implemented in an A2F200-FG484 package with 2.5 m/s airflow, the power
consumption value using the power calculator is 3.00 W. The user-dependent Ta and Tj are given as
follows:
From the datasheet:
θJA = 19.00°C/W (taken from Table 2-6 on page 2-7).
TA= 75.00°C
TJ= 100.00°C
TA= 70.00°C
θJA = 17.00°C/W
θJC = 8.28°C/W
Maximum Power Allowed TJ(MAX) TA(MAX)
–
θJA
---------------------------------------------=
Maximum Power Allowed 100.00°C 75.00°C–
19.00°C/W
---------------------------------------------------- 1.3 W==
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-9
EQ 6
The 1.76 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the
airflow where the device is mounted should be increased. The design's total junction-to-air thermal
resistance requirement can be estimated by EQ 7:
EQ 7
Determining the heat sink's thermal performance proceeds as follows:
EQ 8
where
EQ 9
A heat sink with a thermal resistance of 5.01°C/W or better should be used. Thermal resistance of heat
sinks is a function of airflow. The heat sink performance can be significantly improved with increased
airflow.
Carefully estimating thermal resistance is important in the long-term reliability of an FPGA. Design
engineers should always correlate the power consumption of the device with the maximum allowable
power dissipation of the package selected for that device.
Note: The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard
(JESD-51) and assumptions made in building the model. It may not be realized in actual
application and therefore should be used with a degree of caution. Junction-to-case thermal
resistance assumes that all power is dissipated through the case.
Temperature and Voltage Derating Factors
θJA = 0.37°C/W
= Thermal resistance of the interface material between
the case and the heat sink, usually provided by the
thermal interface manufacturer
θSA = Thermal resistance of the heat sink in °C/W
Table 2-7 • Temperature and Voltage Derating Factors for Timi ng Delays
(normalized to TJ = 85°C, worst-case VCC = 1.425 V)
Array
Voltage
VCC (V)
Junction Temperature (°C)
–40°C 0°C 25°C 70°C 85°C 100°C
1.425 0.86 0.91 0.93 0.98 1.00 1.02
1.500 0.81 0.86 0.88 0.93 0.95 0.96
1.575 0.78 0.83 0.85 0.90 0.91 0.93
PTJTA
–
θJA
-------------------100°C 70°C–
17.00 W
------------------------------------1.76 W== =
θJA(total)
TJTA
–
P
-------------------100°C 70°C–
3.00 W
------------------------------------10.00°C/W== =
θJA(TOTAL) θJC θCS θSA
++=
θSA θJA(TOTAL) θJC
–θCS
–=
θSA 13.33°C/W 8.28°C/W–0.37°C/W–5.01°C/W==
SmartFusion DC and Switching Characteristics
2-10 Revision 6
Calculating Power Dissipation
Quiescent Supply Current
Power per I/O Pin
Table 2-8 • Quiescent Supply Current Characteristics
Power Supplies Configuration
Modes and Power
Supplies
VCCxxxxIOBx
VCCFPGAIOBx
VCCMSSIOBx
VCC33A / VCC33ADCx
VCC33AP / VCC33SDDx
VCCMAINXTAL / VCCLPXTAL
VCC / VCC15A / VCC15ADCx
VCCPLLx / VCOMPLAx
VCCENVM / VCCESRAM
VDDBAT
VCCRCOSC
VJTAG
VPP
eNVM (reset/off)
LPXTAL (enable/disable)
MAINXTAL (enable/ di sa ble)
Time Keeping mode 0 V 0 V 0 V 3.3 V 0 V 0 V 0 V Off Enable Disable
Standby mode On* 3.3 V 1.5 V N/A 3.3 V N/A N/A Reset Enable Disable
Parameter Modes A2F200 A2F500
1.5 V Domain 3.3 V Domain 1.5 V Domain 3.3 V Domain
IDC1 Time Keeping mode N/A 10 µA N/A 10 µA
IDC2 Standby mode 3 mA 1 mA TBD 1 mA
Note: *On means proper voltage is applie d. Refer to Table 2-3 on page 2-3 for recommended operating conditio ns.
Table 2-9 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
VCCFPGAIOBx (V) Static Power
PDC7 (mW) Dynamic Power PAC9
(µW/MHz)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 17.55
2.5 V LVCMOS 2.5 – 5.97
1.8 V LVCMOS 1.8 – 2.88
1.5 V LVCMOS (JESD8-11) 1.5 – 2.33
3.3 V PCI 3.3 – 19.21
3.3 V PCI-X 3.3 – 19.21
Differential
LVDS 2.5 2.26 0.82
LVPECL 3.3 5.72 1.16
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-11
Table 2-10 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to MSS I/O Banks
VCCMSSIOBx (V) Static Power
PDC7 (mW) Dynamic Power
PAC9 (µW/MHz)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 17.21
3.3 V LVCMOS / 3.3 V LVCMOS – Schmitt trigger 3.3 – 20.00
2.5 V LVCMOS 2.5 – 5.55
2.5 V LVCMOS – Schmitt trigger 2.5 – 7.03
1.8 V LVCMOS 1.8 – 2.61
1.8 V LVCMOS – Schmitt trigger 1.8 – 2.72
1.5 V LVCMOS (JESD8-11) 1.5 – 1.98
1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 1.93
Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings*
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
CLOAD (pF) VCCFPGAIOBx
(V) Static Power
PDC8 (mW) Dynamic Power
PAC10 (µW/MHz)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 475.66
2.5 V LVCMOS 35 2.5 – 270.50
1.8 V LVCMOS 35 1.8 – 152.17
1.5 V LVCMOS (JESD8-11) 35 1.5 – 104.44
3.3 V PCI 10 3.3 – 202.69
3.3 V PCI-X 10 3.3 – 202.69
Differential
LVDS – 2.5 7.74 88.26
LVPECL – 3.3 19.54 164.99
Note: *Dynamic power consumpti on is given for standard load an d software default drive strength and outpu t slew.
Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
Applicable to MSS I/O Banks
CLOAD (pF) VCCMSSIOBx (V) Static Power
PDC8 (mW)2Dynamic Power
PAC10 (µW/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 10 3.3 – 155.65
2.5 V LVCMOS 10 2.5 – 88.23
1.8 V LVCMOS 10 1.8 – 45.03
1.5 V LVCMOS (JESD8-11) 10 1.5 – 31.01
SmartFusion DC and Switching Characteristics
2-12 Revision 6
Power Consumption of Various Internal Resources
Table 2-13 • Differe nt Components Contributing to Dynamic Power Consumption in Smar tFusion Devic es
Parameter Definition
Power Supply Device
UnitsName Domain A2F500 A2F200
PAC1 Clock contribution of a Global Rib VCC 1.5 V 5.0 9.3 µW/MHz
PAC2 Clock contribution of a Global Spine VCC 1.5 V 2.5 0.8 µW/MHz
PAC3 Clock contribution of a VersaTile row VCC 1.5 V 1.1 0.81 µW/MHz
PAC4 Clock contribution of a VersaTile used as a
sequential module
VCC 1.5 V 0.1 0.11 µW/MHz
PAC5 First contribution of a VersaTile used as a
sequential module
VCC 1.5 V 0.07 µW/MHz
PAC6 Second contribution of a VersaTile used as
a sequential module
VCC 1.5 V 0.29 µW/MHz
PAC7 Contribution of a VersaTile used as a
combinatorial module
VCC 1.5 V 0.29 µW/MHz
PAC8 Average contribution of a routing net VCC 1.5 V 0.70 µW/MHz
PAC9 Contribution of an I/O input pin (standard
dependent)
VCCxxxxIOBx/VCC See Ta b le 2 - 9 and Table 2-10 on
page 2-11
PAC10 Contribution of an I/O output pin (standard
dependent)
VCCxxxxIOBx/VCC See Tab le 2 -11 and Table 2-12 on
page 2-11
PAC11 Average contribution of a RAM block
during a read operation
VCC 1.5 V 25.00 µW/MHz
PAC12 Average contribution of a RAM block
during a write operation
VCC 1.5 V 30.00 µW/MHz
PAC13 Dynamic Contribution for PLL VCC 1.5 V 2.60 µW/MHz
PAC15 Contribution of NVM block during a read
operation (F < 33MHz)
VCC 1.5 V 358.00 µW/MHz
PAC16 1st contribution of NVM block during a
read operation (F > 33MHz)
VCC 1.5 V 12.88 mW
PAC17 2nd contribution of NVM block during a
read operation (F > 33MHz)
VCC 1.5 V 4.80 µW/MHz
PAC18 Main Crystal Oscillator contribution VCCMAINXTAL 3.3 V 1.98 mW
PAC19a RC Oscillator contribution VCCRCOSC 3.3 V 3.30 mW
PAC19b RC Oscillator contribution VCC 1.5 V 3.00 mW
PAC20a Analog Block Dynamic Power Contribution
of the ADC
VCC33ADCx 3.3 V 8.25 mW
PAC20b Analog Block Dynamic Power Contribution
of the ADC
VCC15ADCx 1.5 V 3.00 mW
PAC21 Low Power Crystal Oscillator contribution VCCLPXTAL 3.3 V 33.00 µW
PAC22 MSS Dynamic Power Contribution –
Running Drysthone at 100MHz1
VCC 1.5 V 67.50 mW
PAC23 Temperature Monitor Power Contribution See Table 2-92 on
page 2-76
–1.23mW
PAC24 Current Monitor Power Contribution See Table 2-91 on
page 2-75
–1.03mW
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-13
PAC25 ABPS Power Contribution See Table 2-94 on
page 2-79
–0.70mW
PAC26 Sigma-Delta DAC Power Contribution2See Table 2-96 on
page 2-82
–0.58mW
PAC27 Comparator Power Contribution See Table 2-95 on
page 2-81
–0.96mW
PAC28 Voltage Regulator Power Contribution3See Table 2-97 on
page 2-84
– 36.30 mW
Notes:
1. For a different use of MSS peripherals and resources, refer to SmartPower.
2. Assumes Input = Half Scale Operati on mode.
3. Assumes 100 mA load on 1.5 V domain.
Table 2-14 • Differe nt Components Contribu ting to the Static Power Consumption in SmartFusion Dev ices
Parameter Definition
Power Supply Device
UnitsName Domain A2F500 A2F200
PDC1 Core static power contribution VCC 1.5 V 4.5 1.50 mW
PDC2 Device static power contribution in
Standby Mode
See Table 2-8 on
page 2-10
–4.51.50mW
PDC3 Device static power contribution in
Time Keeping mode
See Table 2-8 on
page 2-10
3.3 V 0.00 mW
PDC4 eNVM static power contribution See Table 2-8 on
page 2-10
1.5 V 1.19 mW
PDC7 Static contribution per input pin
(standard dependent contribution)
VCCxxxxIOBx/VCC See Ta b l e 2 - 9 and Table 2-10 on
page 2-11.
PDC8 Static contribution per input pin
(standard dependent contribution)
VCCxxxxIOBx/VCC See Ta b le 2- 11 and Table 2-12 on
page 2-11.
PDC9 Static contribution per PLL VCC 1.5 V 2.55 mW
Table 2-15 • eNVM Dyn amic Power Consumption
Parameter Description Condition Min. Typ. Max. Units
eNVM System
eNVM array operating power
Idle 795 µA
Read operation See Table 2-13 on page 2-12.
Erase 900 µA
Write 900 µA
PNVMCTRL eNVM controller operating power 20 µW/MHz
Table 2-13 • Differe nt Components Contributing to Dynamic Power Consumption in Smar tFusion Devic es
Parameter Definition
Power Supply Device
UnitsName Domain A2F500 A2F200
SmartFusion DC and Switching Characteristics
2-14 Revision 6
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software.
The power calculation methodology described below uses the following variables:
• The number of PLLs/CCCs as well as the number and the frequency of each output clock
generated
• The number of combinatorial and sequential cells used in the design
• The internal clock frequencies
• The number and the standard of I/O pins used in the design
• The number of RAM blocks used in the design
• The number of eNVM blocks used in the design
• The analog block used in the design, including the temperature monitor, current monitor, ABPS,
sigma-delta DAC, comparator, low power crystal oscillator, RC oscillator and the main crystal
oscillator
• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on
page 2-18.
• Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on
page 2-18.
• Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-17 on page 2-18.
• Read rate to the eNVM blocks
The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power Consumption—PTOTAL
SoC Mode, Standby Mode, and Time Keeping Mode.
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—PSTAT
SoC Mode
PSTAT = PDC1 + (NeNVM-BLOCKS * PDC4) + (NINPUTS * PDC7) + (NOUTPUTS * PDC8) + (NPLLS * PDC9)
NeNVM-BLOCKS is the number of eNVM blocks available in the device.
NINPUTS is the number of I/O input buffers used in the design.
NOUTPUTS is the number of I/O output buffers used in the design.
NPLLS is the number of PLLs available in the device.
Standby Mode
PSTAT = PDC2
Time Keeping Mode
PSTAT = PDC3
Total Dynamic Power Consumption—PDYN
SoC Mode
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PeNVM +
PXTL-OSC + PRC-OSC + PAB + PLPXTAL-OSC + PMSS
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-15
Standby Mode
PDYN = PRC-OSC + PLPXTAL-OSC
Time Keeping Mode
PDYN = PLPXTAL-OSC
Global Clock Dynamic Contribution—PCLOCK
SoC Mode
PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in
Table 2-16 on page 2-18.
NROW is the number of VersaTile rows used in the design—guidelines are provided in Table 2-16
on page 2-18.
FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
Standby Mode and Time Keeping Mode
PCLOCK = 0 W
Sequential Cells Dynamic Contribution—PS-CELL
SoC Mode
PS-CELL = NS-CELL * (PAC5 + (α1 / 2) * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile
sequential cell is used, it should be accounted for as 1.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-18.
FCLK is the global clock signal frequency.
Standby Mode and Time Keeping Mode
PS-CELL = 0 W
Combinatorial Cells Dynamic Contribution—PC-CELL
SoC Mode
PC-CELL = NC-CELL* (α1 / 2) * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-18.
FCLK is the global clock signal frequency.
Standby Mode and Time Keeping Mode
PC-CELL = 0 W
Routing Net Dynamic Contribution—PNET
SoC Mode
PNET = (NS-CELL + NC-CELL) * (α1 / 2) * PAC8 * FCLK
NS-CELL is the number VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-18.
FCLK is the frequency of the clock driving the logic including these nets.
SmartFusion DC and Switching Characteristics
2-16 Revision 6
Standby Mode and Time Keeping Mode
PNET = 0 W
I/O Input Buffer Dynamic Contribution—PINPUTS
SoC Mode
PINPUTS = NINPUTS * (α2 / 2) * PAC9 * FCLK
Where:
NINPUTS is the number of I/O input buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-18.
FCLK is the global clock signal frequency.
Standby Mode and Time Keeping Mode
PINPUTS = 0 W
I/O Output Buffer Dynamic Contribution—POUTPUTS
SoC Mode
POUTPUTS = NOUTPUTS * (α2 / 2) * β1 * PAC10 * FCLK
Where:
NOUTPUTS is the number of I/O output buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-18.
β1 is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-18.
FCLK is the global clock signal frequency.
Standby Mode and Time Keeping Mode
POUTPUTS = 0 W
FPGA Fabric SRAM Dynamic Contribution—PMEMORY
SoC Mode
PMEMORY = (NBLOCKS * PAC11 * β2 * FREAD-CLOCK) + (NBLOCKS * PAC12 * β3 * FWRITE-CLOCK)
Where:
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
β2 is the RAM enable rate for read operations—guidelines are provided in Table 2-17 on
page 2-18.
β3 the RAM enable rate for write operations—guidelines are provided in Table 2-17 on
page 2-18.
FWRITE-CLOCK is the memory write clock frequency.
Standby Mode and Time Keeping Mode
PMEMORY = 0 W
PLL/CCC Dynamic Contribution—PPLL
SoC Mode
PPLL = PAC13 * FCLKOUT
FCLKIN is the input clock frequency.
FCLKOUT is the output clock frequency.1
1.The PLL dynamic contribution depends on the input clock fr equency, the number of output clock sign als generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula output clock by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL
contribution.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-17
Standby Mode and Time Keeping Mode
PPLL = 0 W
Embedded Nonvolatile Memory Dynamic Contribution—PeNVM
SoC Mode
The eNVM dynamic power consumption is a piecewise linear function of frequency.
PeNVM = NeNVM-BLOCKS * β4 * PAC15 * FREAD-eNVM when FREAD-eNVM ≤ 33 MHz,
PeNVM = NeNVM-BLOCKS * β4 *(PAC16 + PAC17 * FREAD-eNVM) when FREAD-eNVM > 33 MHz
Where:
NeNVM-BLOCKS is the number of eNVM blocks used in the design.
β4 is the eNVM enable rate for read operations. Default is 0 (eNVM mainly in idle state).
FREAD-eNVM is the eNVM read clock frequency.
Standby Mode and Time Keeping Mode
PeNVM = 0 W
Main Crystal Oscillator Dynamic Contribution—PXTL-OSC
SoC Mode
PXTL-OSC = PAC18
Standby Mode
PXTL-OSC = 0 W
Time Keeping Mode
PXTL-OSC = 0 W
Low Power Oscillator Crystal Dynamic Contribution—PLPXTAL-OSC
Operating, Standby, and Time Keeping Mode
PLPXTAL-OSC = PAC21
RC Oscillator Dynamic Contribution—PRC-OSC
SoC Mode
PRC-OSC = PAC19A + PAC19B
Standby Mode and Time Keeping Mode
PRC-OSC = 0 W
Analog System Dynamic Contribution—PAB
SoC Mode
PAB = PAC23 * NTM + PAC24 * NCM + PAC25 * NABPS + PAC26 * NSDD + PAC27 * NCOMP + PADC * NADC
+ PVR
Where:
NCM is the number of current monitor blocks
NTM is the number of temperature monitor blocks
NSDD is the number of sigma-delta DAC blocks
NABPS is the number of ABPS blocks
NADC is the number of ADC blocks
NCOMP is the number of comparator blocks
PVR= PAC28
PADC= PAC20A + PAC20B
SmartFusion DC and Switching Characteristics
2-18 Revision 6
Microcontroller Subsystem Dynamic Contribution—PMSS
SoC Mode
PMSS = PAC22
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some
examples:
• The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the
clock frequency.
• The average toggle rate of an 8-bit counter is 25%:
– Bit 0 (LSB) = 100%
– Bit 1 = 50%
– Bit 2 = 25%
–…
– Bit 7 (MSB) = 0.78125%
– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
non-tristate output buffers are used, the enable rate should be 100%.
Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation
Component Definition Guideline
α1 Toggle rate of VersaTile outputs 10%
α2 I/O buffer toggle rate 10%
Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation
Component Definition Guideline
β1 I/O output buffer enable rate Toggle rate of the logic driving the
output buffer
β2 FPGA fabric SRAM enable rate for read
operations
12.5%
β3FPGA fabric SRAM enable rate for write
operations
12.5%
β4 eNVM enable rate for read operations < 5%
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-19
User I/O Characteristics
Timing Model
Figure 2-2 • Timi ng Model
Operating Conditions: –1 Speed, Commercial Temperature Range (TJ = 85°C),
Worst Case VCC = 1.425 V
DQ
Y
Y
DQ
DQ DQ
Y
Combinational Cell
Combinational Cell
Combinational Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
Register Cell Register Cell
I/O Module
(Registered)
I/O Module
(Non-Registered)
LVPECL (applicable to
FPGA /O bank, EMC pin)
LVPECL
(Applicable
to FPGA
I/O Bank,
EMC pin)
LVDS,
BLVDS,
M-LVDS
(Applicable for
FPGA I/O Bank,
EMC pin)
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
Y
Combinational Cell
Y
Combinational Cell
Y
Combinational Cell
I/O Module
(Non-Registered)
LVTTLOutput drive strength = 8 mA
High slew rate
I/O Module
(Non-Registered)
LVCMOS 1.5 V Output drive strength = 4 mA
High slew rate
LVTTLOutput drive strength = 12 mA
High slew rate
I/O Module
(Non-Registered)
Input LVTTL
Clock
Input LVTTL
Clock
Input LVTTL
Clock
t
PD
= 0.57 ns t
PD
= 0.49 ns
t
DP
= 1.53 ns
t
PD
= 0.89 ns t
DP
= 2.81 ns (FPGA I/O Bank, EMC pin)
t
PD
= 0.51 ns
t
DP
= 3.87 ns (FPGA I/O Bank, EMC pin)
t
PD
= 0.48 ns t
DP
= 4.13 ns (FPGA I/O Bank, EMC pin)
t
PD
= 0.48 ns
t
PY
= 0.81 ns
(FPGA I/O Bank, EMC pin)
t
CLKQ
= 0.56 ns t
OCLKQ
= 0.60 ns
t
SUD
= 0.44 ns t
OSUD
= 0.32 ns
t
DP
= 2.81 ns
(FPGA I/O Bank, EMC pin)
t
PY
= 0.81 ns (FPGA I/O Bank, EMC pin)
t
PY
= 1.55 ns
t
CLKQ
= 0.56 ns
t
SUD
= 0.44 ns
t
PY
= 0.81 ns
(FPGA I/O Bank, EMC pin)
t
ICLKQ
= 0.24 ns
t
ISUD
= 0.27 ns
t
PY
= 1.46 ns
SmartFusion DC and Switching Characteristics
2-20 Revision 6
Figure 2-3 • Input Buffer Timing Model and Delays (example)
t
PY
(R)
PAD
Y
V
trip
GND t
PY
(F)
V
trip
50%
50%
VIH
VCC
VIL
t
DOUT
(R)
DIN
GND t
DOUT
(F)
50%50%
VCC
PAD Y
t
PY
D
CLK
Q
I/O Interface
DIN
t
DIN
To Array
t
PY
= MAX(t
PY
(R), t
PY
(F))
t
DIN
= MAX(t
DIN
(R), t
DIN
(F))
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-21
Figure 2-4 • Output Buffer Model and Delays (example)
tDP
(R)
PAD VOL
tDP
(F)
Vtrip
Vtrip
VOH
VCC
D50% 50%
VCC
0 V
DOUT 50% 50% 0 V
tDOUT
(R)
tDOUT
(F)
From Array
PAD
tDP
Std
Load
D
CLK
Q
I/O Interface
DOUT
D
tDOUT
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
SmartFusion DC and Switching Characteristics
2-22 Revision 6
Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)
D
CLK
Q
D
CLK
Q
10% VCCxxxxIOBx
tZL
Vtrip
50%
tHZ
90% VCCxxxxIOBx
tZH
Vtrip
50% 50% tLZ
50%
EOUT
PAD
D
E50%
tEOUT (R)
50%tEOUT (F)
PAD
DOUT
EOUT
D
I/O Interface
E
tEOUT
tZLS
Vtrip
50%
tZHS
Vtrip
50%
EOUT
PAD
D
E50% 50%
tEOUT (R) tEOUT (F)
50%
VCC
VCC
VCC
VCCxxxxIOBx
VCC
VCC
VCC
VOH
VOL
VOL
tZL, tZH, tHZ, tLZ, tZLS, tZHS
tEOUT = MAX(tEOUT(r), tEOUT(f))
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-23
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial
Conditions—Software De fault Settings
Applicable to FPGA I/O Banks
I/O Standard Drive
Strgth. Slew
Rate
VIL VIH VOL VOH IOL1IOH1
Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
3.3VLVTTL/
3.3 V LVCMOS
12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12
2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12
1.8 V LVCMOS 12 mA High –0.3 0.35 *
VCCxxxxIOBx
0.65*
VCCxxxxIOBx
3.6 0.45 VCCxxxxIOBx
– 0.45
12 12
1.5 V LVCMOS 12 mA High –0.3 0.35 *
VCCxxxxIOBx
0.65*
VCCxxxxIOBx
3.6 0.25 *
VCCxxxxIOBx
0.75*
VCCxxxxIOBx
12 12
3.3 V PCI Per PCI specifications
3.3 V PCI-X Per PCI-X specifications
Notes:
1. Currents are measured at 85°C juncti on temperature.
2. Output slew rate can be extracted by the IBIS Models.
Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial
Conditions—Software De fault Settings
Applicable to MSS I/O Banks
I/O Standard Drive
Strgth. Slew
Rate
VIL VIH VOL VOH IOL1IOH1
Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
3.3VLVTTL/
3.3 V LVCMOS
8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8
2.5 V LVCMOS 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8
1.8 V LVCMOS 4 mA High –0.3 0.35*
VCCxxxxIOBx
0.65*
VCCxxxxIOBx
3.6 0.45 VCCxxxxIOBx
– 0.45
44
1.5 V LVCMOS 2 mA High –0.3 0.35*
VCCxxxxIOBx
0.65*
VCCxxxxIOBx
3.6 0.25*
VCCxxxxIOBx
0.75*
VCCxxxxIOBx
22
Notes:
1. Currents are measured at 85°C juncti on temperature.
2. Output slew rate can be extracted by the IBIS Models.
SmartFusion DC and Switching Characteristics
2-24 Revision 6
Summary of I/O Timing Characteristics – Default I/O Software
Settings
Table 2-20 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial Conditions in all I/O Bank Types
DC I/O Standards
Commercial
IIL IIH
µA µA
3.3 V LVTTL / 3.3 V LVCMOS 15 15
2.5 V LVCMOS 15 15
1.8 V LVCMOS 15 15
1.5 V LVCMOS 15 15
3.3 V PCI 15 15
3.3 V PCI-X 15 15
Table 2-21 • Summary of AC Measuring Points Applicable to All I/O Bank Types
Standard Measuring T rip Point (Vtrip)
3.3 V LVTTL / 3.3 V LVCMOS 1.4 V
2.5 V LVCMOS 1.2 V
1.8 V LVCMOS 0.90 V
1.5 V LVCMOS 0.75 V
3.3 V PCI 0.285 * VCCxxxxIOBx (RR)
0.615 * VCCxxxxIOBx (FF)
3.3 V PCI-X 0.285 * VCCxxxxIOBx (RR)
0.615 * VCCxxxxIOBx (FF)
LVDS Cross point
LVPECL Cross point
Table 2-22 • I/O AC Parameter Definitions
Parameter Parameter Definition
tDP Data to pad delay through the output buffer
tPY Pad to data delay through the input buffer
tDOUT Data to output buffer delay through the I/O interface
tEOUT Enable to output buffer tristate control delay through the I/O interface
tDIN Input buffer to data delay through the I/O interface
tHZ Enable to pad delay through the output buffer—High to Z
tZH Enable to pad delay through the output buffer—Z to High
tLZ Enable to pad delay through the output buffer—Low to Z
tZL Enable to pad delay through the output buffer—Z to Low
tZHS Enable to pad delay through the output buffer with delayed enable—Z to High
tZLS Enable to pad delay through the output buffer with delayed enable—Z to Low
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-25
Table 2-23 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Worst Commercial-Case Conditions: TJ = 85°C, Wo rst Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx (per standard)
Applicable to FPGA I/O Banks, Assigned to EMC I/O Pins
I/O Standard
Drive Strength
Slew Rate
Capacitive Load (pF)
External Resistor (Ω)
tDOUT (ns)
tDP (ns)
tDIN (ns)
tPY (ns)
tEOUT (ns)
tZL (ns)
tZH (ns)
tLZ (ns)
tHZ (ns)
tZLS (ns)
tZHS (ns)
Units
3.3VLVTTL/
3.3 V LVCMOS
12 mA High 35 – 0.50 2.81 0.03 0.81 0.32 2.86 2.23 2.55 2.82 4.58 3.94 ns
2.5 V LVCMOS 12 mA High 35 – 0.50 2.73 0.03 1.03 0.32 2.88 2.69 2.62 2.70 4.60 4.41 ns
1.8 V LVCMOS 12 mA High 35 – 0.50 2.81 0.03 0.95 0.32 2.87 2.38 2.92 3.18 4.58 4.10 ns
1.5 V LVCMOS 12 mA High 35 – 0.50 3.24 0.03 1.12 0.32 3.30 2.79 3.10 3.27 5.02 4.50 ns
3.3 V PCI Per PCI spec High 10 2510.50 2.11 0.03 0.68 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns
3.3 V PCI-X Per PCI-X
spec
High 10 2510.50 2.11 0.03 0.64 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns
LVDS 24 mA High – – 0.50 1.53 0.03 1.55 – – – – – – – ns
LVPECL 24 mA High – – 0.50 1.46 0.03 1.46 – – – – – – – ns
Notes:
1. Resistance is used to measure I/O propagatio n delays as defi ned in PCI specifi cations. See Figure 2-10 on page 2-39 for
connectivity. This resistor is not required during normal operation.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Worst Commercial-Case Conditions: TJ = 85°C, Wo rst Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx (per standard)
Applicable to MSS I/O Banks
I/O Standard
Drive Strength
Slew Rate
Cap acitive Load (pF)
External Resistor
tDOUT (ns)
tDP (ns)
tDIN (ns)
tPY (ns)
tPYS (ns)
tEOUT (ns)
tZL (ns)
tZH (ns)
tLZ (ns)
tHZ (ns)
Units
3.3 V LVTTL /
3.3 V LVCMOS
8 mA High 10 – 0.18 1.92 0.07 0.78 1.09 0.18 1.96 1.55 1.83 2.04 ns
2.5 V LVCMOS 8 mA High 10 – 0.18 1.96 0.07 0.99 1.16 0.18 2.00 1.82 1.82 1.93 ns
1.8 V LVCMOS 4 mA High 10 – 0.18 2.31 0.07 0.91 1.37 0.18 2.35 2.27 1.84 1.87 ns
1.5 V LVCMOS 2 mA High 10 – 0.18 2.70 0.07 1.07 1.55 0.18 2.75 2.67 1.87 1.85 ns
Notes:
1. Resistance is used to measure I/O propagatio n delays as defi ned in PCI specifi cations. See Figure 2-10 on page 2-39 for
connectivity. This resistor is not required during normal operation.
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
SmartFusion DC and Switching Characteristics
2-26 Revision 6
Detailed I/O DC Characteristics
Table 2-25 • Input Capacitance
Symbol Definition Conditions Min. Max. Units
CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF
CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF
Table 2-26 • I/O Output Buffer Maximu m Resistances1
Applicable to FPGA I/O Banks
Standard Drive Strength RPULL-DOWN
(Ω)2RPULL-UP
(Ω)3
3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300
4 mA 100 300
6 mA 50 150
8 mA 50 150
12 mA 25 75
16 mA 17 50
24 mA 11 33
2.5 V LVCMOS 2 mA 100 200
4 mA 100 200
6 mA 50 100
8 mA 50 100
12 mA 25 50
16 mA 20 40
24 mA 11 22
1.8 V LVCMOS 2 mA 200 225
4 mA 100 112
6 mA 50 56
8 mA 50 56
12 mA 20 22
16 mA 20 22
1.5 V LVCMOS 2 mA 200 224
4 mA 100 112
6 mA 67 75
8 mA 33 37
12 mA 33 37
3.3 V PCI/PCI-X Per PCI/PCI-X specification 25 75
Notes:
1. These maximum values are provided for information only. Minimum output buffer resistance values
depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
Microsemi SoC Products Group website at http://www.actel.com/download/ibis/default.aspx (also
generated by the SoC Product s Group Libero IDE toolset).
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-27
Table 2-27 • I/O Output Buffer Maximu m Resistances1
Applicable to MSS I/O Banks
Standard Drive Strength RPULL-DOWN
(Ω)2RPULL-UP
(Ω)3
3.3 V LVTTL / 3.3 V LVCMOS 8mA 50 150
2.5 V LVCMOS 8 mA 50 100
1.8 V LVCMOS 4 mA 100 112
1.5 V LVCMOS 2 mA 200 224
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
SoC Products Group website at http://www.actel.com/download/ibis/default.aspx.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
Table 2-28 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
VCCxxxxIOBx
R(WEAK PULL-UP)1
(Ω)R(WEAK PULL-DOWN)2
(Ω)
Min. Max. Min. Max.
3.3 V 10 k 45 k 10 k 45 k
2.5 V 11 k 55 k 12 k 74 k
1.8 V 18 k 70 k 17 k 110 k
1.5 V 19 k 90 k 19 k 140 k
Notes:
1. R(WEAK PULL-DO W N -MAX) = (VOLspec) / I(WEAK PULL-DOWN-MIN)
2. R(WEAK PULL-UP -MA X) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)
SmartFusion DC and Switching Characteristics
2-28 Revision 6
Table 2-29 • I/O Short Currents IOSH/IOSL
Applicable to FPGA I/O Banks
Drive Strength IOSL (mA)*IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25
4 mA 27 25
6 mA 54 51
8 mA 54 51
12 mA 109 103
16 mA 127 132
24 mA 181 268
2.5 V LVCMOS 2 mA 18 16
4 mA 18 16
6 mA 37 32
8 mA 37 32
12 mA 74 65
16 mA 87 83
24 mA 124 169
1.8 V LVCMOS 2 mA 11 9
4 mA 22 17
6 mA 44 35
8 mA 51 45
12 mA 74 91
16 mA 74 91
1.5 V LVCMOS 2 mA 16 13
4 mA 33 25
6 mA 39 32
8 mA 55 66
12 mA 55 66
3.3 V PCI/PCI-X Per PCI/PCI-X specification 109 103
Note: *TJ = 85°C.
Table 2-30 • I/O Short Currents IOSH/IOSL
Applicable to MSS I/O Banks
Drive Strength IOSL (mA)* IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS 8 mA 54 51
2.5 V LVCMOS 8 mA 37 32
1.8 V LVCMOS 4 mA 22 17
1.5 V LVCMOS 2 mA 16 13
Note: *TJ = 85°C
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-29
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than 2200
operation hours to cause a reliability concern. The I/O design does not contain any short circuit
protection, but such protection would only be needed in extremely prolonged stress conditions.
Table 2-31 • Duration of Short Circuit Event before Failure
Temperature Time before Failure
–40°C > 20 years
0°C > 20 years
25°C > 20 years
70°C 5 years
85°C 2 years
100°C 6 months
Table 2-32 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (typi ca l) for Schmitt Mode Input Buffers
Input Buffer Configuration Hysteresis Value (typical)
3.3 V LVTTL / LVCMOS / PCI / PCI-X (Schmitt trigger mode) 240 mV
2.5 V LVCMOS (Schmitt trigger mode) 140 mV
1.8 V LVCMOS (Schmitt trigger mode) 80 mV
1.5 V LVCMOS (Schmitt trigger mode) 60 mV
Table 2-33 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer Input Rise /Fall Time (min.) Input Rise /Fall Time (max.) Reliabili ty
LVTTL/LVCMOS No requirement 10 ns * 20 years (100°C)
LVDS/B-LVDS/
M-LVDS/LVPECL
No requirement 10 ns * 10 years (100°C)
Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the
maximum value. The longer the rise/fall ti mes, the more susceptible the i nput signal is to the board
noise. Microsemi SoC Products Group recommends signal integrity evaluation/ch aracterization of
the system to ensure that there is no excessive no ise couplin g into input sig nals.
SmartFusion DC and Switching Characteristics
2-30 Revision 6
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer.
Table 2-34 • Minimum and Maximum DC Input and Output Levels
Applicable to FPGA I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmAMax.
mA1Max.
mA1µA2µA2
2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 15 15
4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 15 15
6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 15 15
8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 15 15
12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 15 15
16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 15 15
24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C juncti on temperature.
3. Software default selection highlighted in gray.
Table 2-35 • Minimum and Maximum DC Input and Output Levels
Applicable to MSS I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmAMax.
mA1Max.
mA1µA2µA2
8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 15 15
Notes:
1. Currents are measured at 100°C juncti on temperature and maximum voltage.
2. Currents are measured at 85°C juncti on temperature.
3. Software default selection highlighted in gray.
Figure 2-6 • AC Loading
Table 2-36 • AC Waveforms, Measuring Points, and Cap acitive Loads
Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)
0 3.3 1.4 – 35
Note: *Measuring point = Vtrip. See Table 2-21 on pa g e 2-24 for a complete table of trip points.
Test Point
Test Point
Enable Path
Datapath 35 pF
R = 1 K R to GND for t
HZ
/ t
ZH
/ t
ZHS
R to VCCxxxxIOBx for t
LZ
/ t
ZL
/ t
ZLS
35 pF for t
ZH
/ t
ZHS
/ t
ZL
/ t
ZLS
5 pF for t
HZ
/ t
LZ
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-31
Timing Characteristics
Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 3.0 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA Std. 0.60 7.20 0.04 0.97 0.39 7.34 6.18 2.52 2.46 9.39 8.23 ns
–1 0.50 6.00 0.03 0.81 0.32 6.11 5.15 2.10 2.05 7.83 6.86 ns
8 mA Std. 0.60 4.64 0.04 0.97 0.39 4.73 3.84 2.85 3.02 6.79 5.90 ns
–1 0.50 3.87 0.03 0.81 0.32 3.94 3.20 2.37 2.52 5.65 4.91 ns
12 mA Std. 0.60 3.37 0.04 0.97 0.39 3.43 2.67 3.07 3.39 5.49 4.73 ns
–1 0.50 2.81 0.03 0.81 0.32 2.86 2.23 2.55 2.82 4.58 3.94 ns
16 mA Std. 0.60 3.18 0.04 0.97 0.39 3.24 2.43 3.11 3.48 5.30 4.49 ns
–1 0.50 2.65 0.03 0.81 0.32 2.70 2.03 2.59 2.90 4.42 3.74 ns
24 mA Std. 0.60 2.93 0.04 0.97 0.39 2.99 2.03 3.17 3.83 5.05 4.09 ns
–1 0.50 2.45 0.03 0.81 0.32 2.49 1.69 2.64 3.19 4.21 3.41 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction t emperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 3.0 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA Std. 0.60 9.75 0.04 0.97 0.39 9.93 8.22 2.52 2.31 11.99 10.28 ns
–1 0.50 8.12 0.03 0.81 0.32 8.27 6.85 2.10 1.93 9.99 8.57 ns
8 mA Std. 0.60 6.96 0.04 0.97 0.39 7.09 5.85 2.84 2.87 9.15 7.91 ns
–1 0.50 5.80 0.03 0.81 0.32 5.91 4.88 2.37 2.39 7.62 6.59 ns
12 mA Std. 0.60 5.35 0.04 0.97 0.39 5.45 4.58 3.06 3.23 7.51 6.64 ns
–1 0.50 4.46 0.03 0.81 0.32 4.54 3.82 2.55 2.69 6.26 5.53 ns
16 mA Std. 0.60 5.01 0.04 0.97 0.39 5.10 4.30 3.11 3.32 7.16 6.36 ns
–1 0.50 4.17 0.03 0.81 0.32 4.25 3.58 2.59 2.77 5.97 5.30 ns
24 mA Std. 0.60 4.67 0.04 0.97 0.39 4.75 4.28 3.16 3.66 6.81 6.34 ns
–1 0.50 3.89 0.03 0.81 0.32 3.96 3.57 2.64 3.05 5.68 5.28 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 3.0 V
Applicable to MSS I/O Banks
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units
8 mA Std. 0.22 2.31 0.09 0.94 1.30 0.22 2.35 1.86 2.20 2.45 ns
–1 0.18 1.92 0.07 0.78 1.09 0.18 1.96 1.55 1.83 2.04 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction t emperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
SmartFusion DC and Switching Characteristics
2-32 Revision 6
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.
Table 2-40 • Minimum and Maximum DC Input and Output Levels
Applicable to FPGA I/O Banks
2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmAMax.
mA1Max.
mA1µA2µA2
2 mA –0.3 0.7 1.7 2.7 0.7 1.7 2 2 18 16 15 15
4 mA –0.3 0.7 1.7 2.7 0.7 1.7 4 4 18 16 15 15
6 mA –0.3 0.7 1.7 2.7 0.7 1.7 6 6 37 32 15 15
8 mA –0.3 0.7 1.7 2.7 0.7 1.7 8 8 37 32 15 15
12 mA –0.3 0.7 1.7 2.7 0.7 1.7 12 12 74 65 15 15
16 mA –0.3 0.7 1.7 2.7 0.7 1.7 16 16 87 83 15 15
24 mA –0.3 0.7 1.7 2.7 0.7 1.7 24 24 124 169 15 15
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C juncti on temperature.
3. Software default selection highlighted in gray.
Table 2-41 • Minimum and Maximum DC Input and Output Levels
Applicable to MSS I/O Banks
2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmAMax.
mA1Max.,
mA1µA2µA2
8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 15 15
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C juncti on temperature.
3. Software default selection highlighted in gray.
Figure 2-7 • AC Loading
Table 2-42 • AC Waveforms, Measuring Points, and Cap acitive Loads
Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)
0 2.5 1.2 – 35
*Measuring point = Vtrip. See Ta ble 2-21 on page 2-24 for a complete table of trip points.
Test Point
Test Point
Enable Path
Datapath 35 pF
R = 1 K R to GND for t
HZ
/ t
ZH
/ t
ZHS
R to VCCxxxxIOBx for t
LZ
/ t
ZL
/ t
ZLS
35 pF for t
ZH
/ t
ZHS
/ t
ZL
/ t
ZLS
5 pF for t
HZ
/ t
LZ
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-33
Timing Characteristics
Table 2-43 • 2.5 V LVCMOS High Slew
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 2.3 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA Std. 0.55 8.10 0.04 1.23 0.39 7.37 8.10 2.54 2.17 9.43 10.15 ns
–1 0.46 6.75 0.03 1.03 0.32 6.14 6.75 2.12 1.81 7.85 8.46 ns
8 mA Std. 0.55 4.85 0.04 1.23 0.39 4.76 4.85 2.90 2.83 6.82 6.91 ns
–1 0.46 4.04 0.03 1.03 0.32 3.97 4.04 2.42 2.36 5.68 5.76 ns
12 mA Std. 0.60 3.28 0.04 1.23 0.39 3.46 3.23 3.15 3.24 5.52 5.29 ns
–1 0.50 2.73 0.03 1.03 0.32 2.88 2.69 2.62 2.70 4.60 4.41 ns
16 mA Std. 0.60 3.09 0.04 1.23 0.39 3.27 2.88 3.20 3.35 5.33 4.94 ns
–1 0.50 2.57 0.03 1.03 0.32 2.72 2.40 2.67 2.79 4.44 4.12 ns
24 mA Std. 0.60 2.95 0.04 1.23 0.39 3.01 2.31 3.27 3.76 5.07 4.37 ns
–1 0.50 2.46 0.03 1.03 0.32 2.51 1.93 2.73 3.13 4.22 3.64 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction t emperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-44 • 2.5 V LVCMOS Low Slew
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 2.3 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
4 mA Std. 0.55 10.50 0.04 1.23 0.39 10.69 10.50 2.54 2.07 12.75 12.56 ns
–1 0.46 8.75 0.03 1.03 0.32 8.91 8.75 2.12 1.73 10.62 10.47 ns
8 mA Std. 0.55 7.61 0.04 1.23 0.39 7.46 7.19 2.81 2.66 9.52 9.25 ns
–1 0.46 6.34 0.03 1.03 0.32 6.22 5.99 2.34 2.22 7.93 7.71 ns
12 mA Std. 0.60 5.92 0.04 1.23 0.39 5.79 5.45 3.04 3.06 7.85 7.51 ns
–1 0.50 4.93 0.03 1.03 0.32 4.83 4.54 2.53 2.55 6.54 6.26 ns
16 mA Std. 0.60 5.53 0.04 1.23 0.39 5.40 5.09 3.09 3.16 7.46 7.14 ns
–1 0.50 4.61 0.03 1.03 0.32 4.50 4.24 2.58 2.64 6.22 5.95 ns
24 mA Std. 0.60 5.18 0.04 1.23 0.39 5.28 5.14 3.27 3.64 7.34 7.20 ns
–1 0.50 4.32 0.03 1.03 0.32 4.40 4.29 2.72 3.03 6.11 6.00 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-45 • 2.5 V LVCMOS High Slew
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 3.0 V
Applicable to MSS I/O Banks
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units
8 mA Std. 0.22 2.35 0.09 1.18 1.39 0.22 2.40 2.18 2.19 2.32 ns
–1 0.18 1.96 0.07 0.99 1.16 0.18 2.00 1.82 1.82 1.93 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction t emperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
SmartFusion DC and Switching Characteristics
2-34 Revision 6
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-46 • Minimum and Maximum DC Input and Output Levels
Applicable to FPGA I/O Banks
1.8 V
LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
Max.
mA1Max.
mA1µA2µA2
2 mA –0.3 0.35 *
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
1.9 0.45 VCCxxxxIOBx
– 0.45
2 2 11 9 15 15
4 mA –0.3 0.35 *
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
1.9 0.45 VCCxxxxIOBx
– 0.45
4 4 22 17 15 15
6 mA –0.3 0.35 *
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
1.9 0.45 VCCxxxxIOBx
– 0.45
6 6 44 35 15 15
8 mA –0.3 0.35 *
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
1.9 0.45 VCCxxxxIOBx
– 0.45
8 8 51 45 15 15
12 mA –0.3 0.35 *
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
1.9 0.45 VCCxxxxIOBx
– 0.45
12 12 74 91 15 15
16 mA –0.3 0.35 *
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
1.9 0.45 VCCxxxxIOBx
– 0.45
16 16 74 91 15 15
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C juncti on temperature.
3. Software default selection highlighted in gray.
Table 2-47 • Minimum and Maximum DC Input and Output Levels
Applicable to MSS I/O Banks
1.8 V
LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
Max.
mA1Max.
mA1µA2µA2
4 mA –0.3 0.35 *
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
3.6 0.45 VCCxxxxIOBx
– 0.45
4 4 22 17 15 15
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C juncti on temperature.
3. Software default selection highlighted in gray.
Figure 2-8 • AC Loading
Table 2-48 • AC Waveforms, Measuring Points, and Cap acitive Loads
Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)
0 1.8 0.9 – 35
*Measuring point = Vtrip. See Ta ble 2-21 on page 2-24 for a complete table of trip points.
Test Point
Test Point
Enable Path
Datapath 35 pF
R = 1 K R to GND for t
HZ
/ t
ZH
/ t
ZHS
R to VCCxxxxIOBx for t
LZ
/ t
ZL
/ t
ZLS
35 pF for t
ZH
/ t
ZHS
/ t
ZL
/ t
ZLS
5 pF for t
HZ
/ t
LZ
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-35
Timing Characteristics
Table 2-49 • 1.8 V LVCMOS High Slew
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 1.7 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA Std. 0.60 11.06 0.04 1.14 0.39 8.61 11.06 2.61 1.59 10.67 13.12 ns
–1 0.50 9.22 0.03 0.95 0.32 7.17 9.22 2.18 1.33 8.89 10.93 ns
4 mA Std. 0.60 6.46 0.04 1.14 0.39 5.53 6.46 3.04 2.66 7.59 8.51 ns
–1 0.50 5.38 0.03 0.95 0.32 4.61 5.38 2.54 2.22 6.33 7.10 ns
6 mA Std. 0.60 4.16 0.04 1.14 0.39 3.99 4.16 3.34 3.18 6.05 6.22 ns
–1 0.50 3.47 0.03 0.95 0.32 3.32 3.47 2.78 2.65 5.04 5.18 ns
8 mA Std. 0.60 3.69 0.04 1.14 0.39 3.76 3.67 3.40 3.31 5.81 5.73 ns
–1 0.50 3.07 0.03 0.95 0.32 3.13 3.06 2.84 2.76 4.85 4.78 ns
12 mA Std. 0.60 3.38 0.04 1.14 0.39 3.44 2.86 3.50 3.82 5.50 4.91 ns
–1 0.50 2.81 0.03 0.95 0.32 2.87 2.38 2.92 3.18 4.58 4.10 ns
16 mA Std. 0.60 3.38 0.04 1.14 0.39 3.44 2.86 3.50 3.82 5.50 4.91 ns
–1 0.50 2.81 0.03 0.95 0.32 2.87 2.38 2.92 3.18 4.58 4.10 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction t emperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-50 • 1.8 V LVCMOS Low Slew
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 1.7 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA Std. 0.60 14.24 0.04 1.14 0.39 13.47 14.24 2.62 1.54 15.53 16.30 ns
–1 0.50 11.87 0.03 0.95 0.32 11.23 11.87 2.18 1.28 12.94 13.59 ns
4 mA Std. 0.60 9.74 0.04 1.14 0.39 9.92 9.62 3.05 2.57 11.98 11.68 ns
–1 0.50 8.11 0.03 0.95 0.32 8.26 8.02 2.54 2.14 9.98 9.74 ns
6 mA Std. 0.60 7.67 0.04 1.14 0.39 7.81 7.24 3.34 3.08 9.87 9.30 ns
–1 0.50 6.39 0.03 0.95 0.32 6.51 6.03 2.79 2.56 8.23 7.75 ns
8 mA Std. 0.60 7.15 0.04 1.14 0.39 7.29 6.75 3.41 3.21 9.34 8.80 ns
–1 0.50 5.96 0.03 0.95 0.32 6.07 5.62 2.84 2.68 7.79 7.34 ns
12 mA Std. 0.60 6.76 0.04 1.14 0.39 6.89 6.75 3.50 3.70 8.95 8.81 ns
–1 0.50 5.64 0.03 0.95 0.32 5.74 5.62 2.92 3.08 7.46 7.34 ns
16 mA Std. 0.60 6.76 0.04 1.14 0.39 6.89 6.75 3.50 3.70 8.95 8.81 ns
–1 0.50 5.64 0.03 0.95 0.32 5.74 5.62 2.92 3.08 7.46 7.34 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-7 on page 2-9 for derating values.
SmartFusion DC and Switching Characteristics
2-36 Revision 6
Table 2-51 • 1.8 V LVCMOS High Slew
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 1.7 V
Applicable to MSS I/O Banks
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units
4 mA Std. 0.22 2.77 0.09 1.09 1.64 0.22 2.82 2.72 2.21 2.25 ns
–1 0.18 2.31 0.07 0.91 1.37 0.18 2.35 2.27 1.84 1.87 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction t emperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-37
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-52 • Minimum and Maximum DC Input and Output Levels
Applicable to FPGA I/O Banks
1.5 V
LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
Max.
mA1Max.
mA1µA2µA2
2 mA –0.3 0.35 *
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
1.575 0.25*
VCCxxxxIOBx
0.75 *
VCCxxxxIOBx
2 2 16 13 15 15
4 mA –
0.3
0.35*
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
1.575 0.25*
VCCxxxxIOBx
0.75 *
VCCxxxxIOBx
4 4 33 25 15 15
6 mA –
0.3
0.35 *
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
1.575 0.25*
VCCxxxxIOBx
0.75 *
VCCxxxxIOBx
6 6 39 32 15 15
8 mA –
0.3
0.35 *
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
1.575 0.25* VCC 0.75 *
VCCxxxxIOBx
8 8 55 66 15 15
12 mA –
0.3
0.35 *
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
1.575 0.25 *
VCCxxxxIOBx
0.75 *
VCCxxxxIOBx
12 12 55 66 15 15
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C juncti on temperature.
3. Software default selection highlighted in gray.
Table 2-53 • Minimum and Maximum DC Input and Output Levels
Applicable to MSS I/O Banks
1.5 V
LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive
Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmA
Max.
mA1Max.
mA1µA2µA
2
2 mA –0.3 0.35 *
VCCxxxxIOBx
0.65 *
VCCxxxxIOBx
1.575 0.25 *
VCCxxxxIOBx
0.75 *
VCCxxxxIOBx
2 2 16 13 15 15
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C juncti on temperature.
3. Software default selection highlighted in gray.
Figure 2-9 • AC Loading
Table 2-54 • AC Waveforms, Measuring Points, and Cap acitive Loads
Input Low (V) Inp ut High (V) Measuri ng Point* (V) VREF (typ.) (V) CLOAD (pF)
0 1.5 0.75 – 35
*Measuring point = Vtrip. See Ta ble 2-21 on page 2-24 for a complete table of trip points.
Test Point
Test Point
Enable Path
Datapath 35 pF
R = 1 K R to GND for t
HZ
/ t
ZH
/ t
ZHS
R to VCCxxxxIOBx for t
LZ
/ t
ZL
/ t
ZLS
35 pF for t
ZH
/ t
ZHS
/ t
ZL
/ t
ZLS
5 pF for t
HZ
/ t
LZ
SmartFusion DC and Switching Characteristics
2-38 Revision 6
Timing Characteristics
Table 2-55 • 1.5 V LVCMOS High Slew
Worst Commercial-Case C onditions: TJ = 85°C, Worst-C ase VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 1.425 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive
Strength Speed
Grade tDOUT tDP t
DIN t
PY t
EOUT t
ZL t
ZH t
LZ t
HZ t
ZLS t
ZHS Units
2 m Std. 0.60 7.79 0.04 1.34 0.39 6.43 7.79 3.19 2.59 8.49 9.85 ns
–1 0.50 6.49 0.03 1.12 0.32 5.36 6.49 2.66 2.16 7.08 8.21 ns
4 mA Std. 0.60 4.95 0.04 1.34 0.39 4.61 4.96 3.53 3.19 6.67 7.02 ns
–1 0.50 4.13 0.03 1.12 0.32 3.85 4.13 2.94 2.66 5.56 5.85 ns
6 mA Std. 0.60 4.36 0.04 1.34 0.39 4.34 4.36 3.60 3.34 6.40 6.42 ns
–1 0.50 3.64 0.03 1.12 0.32 3.62 3.64 3.00 2.78 5.33 5.35 ns
8 mA Std. 0.60 3.89 0.04 1.34 0.39 3.96 3.34 3.72 3.92 6.02 5.40 ns
–1 0.50 3.24 0.03 1.12 0.32 3.30 2.79 3.10 3.27 5.02 4.50 ns
12 mA Std. 0.60 3.89 0.04 1.34 0.39 3.96 3.34 3.72 3.92 6.02 5.40 ns
–1 0.50 3.24 0.03 1.12 0.32 3.30 2.79 3.10 3.27 5.02 4.50 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction t emperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-56 • 1.5 V LVCMOS Low Slew
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 1.4 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
2 mA Std. 0.60 11.96 0.04 1.34 0.39 12.18 11.70 3.20 2.47 14.24 13.76 ns
–1 0.50 9.96 0.03 1.12 0.32 10.15 9.75 2.67 2.06 11.86 11.46 ns
4 mA Std. 0.60 9.51 0.04 1.34 0.39 9.68 8.76 3.54 3.07 11.74 10.82 ns
–1 0.50 7.92 0.03 1.12 0.32 8.07 7.30 2.95 2.56 9.79 9.02 ns
6 mA Std. 0.60 8.86 0.04 1.34 0.39 9.03 8.17 3.61 3.22 11.08 10.23 ns
–1 0.50 7.39 0.03 1.12 0.32 7.52 6.81 3.01 2.68 9.24 8.52 ns
8 mA Std. 0.60 8.44 0.04 1.34 0.39 8.60 8.18 3.73 3.78 10.66 10.24 ns
–1 0.50 7.04 0.03 1.12 0.32 7.17 6.82 3.11 3.15 8.88 8.53 ns
12 mA Std. 0.60 8.44 0.04 1.34 0.39 8.60 8.18 3.73 3.78 10.66 10.24 ns
–1 0.50 7.04 0.03 1.12 0.32 7.17 6.82 3.11 3.15 8.88 8.53 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-57 • 1.5 V LVCMOS High Slew
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 3.0 V
Applicable to MSS I/O Banks
Drive
Strength Speed
Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units
2 mA Std. 0.22 3.24 0.09 1.28 1.86 0.22 3.30 3.20 2.24 2.21 ns
–1 0.18 2.70 0.07 1.07 1.55 0.18 2.75 2.67 1.87 1.85 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction t emperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-39
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus
applications.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; SoC Products Group loadings
for enable path characterization are described in Figure 2-10.
AC loadings are defined per PCI/PCI-X specifications for the datapath; SoC Products Group loading for
tristate is described in Table 2-59.
Timing Characteristics
Table 2-58 • Minimum and Maximum DC Input and Output Levels
3.3 V PCI/PCI-X VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Drive Strength Min.
VMax.
VMin.
VMax.
VMax.
VMin.
VmAmAMax.
mA1Max.
mA1µA2µA2
Per PCI specification Per PCI curves 15 15
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C juncti on temperature.
Figure 2-10 • AC Loading
Test Point
Enable Path
R to VCCXXXXIOBX for t
LZ
/ t
ZL
/ t
ZLS
10 pF for t
ZH
/ t
ZHS
/ t
ZL
/ t
ZLS
5 pF for t
HZ
/ t
LZ
R to GND for t
HZ
/ t
ZH
/ t
ZHS
R = 1 k
Test Point
Datapath
R = 25 R to VCCXXXXIOBX for t
DP
(F)
R to GND for t
DP
(R)
Table 2-59 • AC Waveforms, Measuring Points, and Cap acitive Loads
Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)
0 3.3 0.285 * VCCxxxxIOBx for tDP(R)
0.615 * VCCxxxxIOBx for tDP(F)
–10
*Measuring point = Vtrip. See Ta ble 2-21 on page 2-24 for a complete table of trip points.
Table 2-60 • 3.3 V PCI
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 3.0 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.60 2.54 0.04 0.82 0.39 2.58 1.88 3.06 3.39 4.64 3.94 ns
–1 0.50 2.11 0.03 0.68 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-61 • 3.3 V PCI-X
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCxxxxIOBx = 3.0 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units
Std. 0.60 2.54 0.04 0.77 0.39 2.58 1.88 3.06 3.39 4.64 3.94 ns
–1 0.50 2.11 0.03 0.64 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-7 on page 2-9 for derating values.
SmartFusion DC and Switching Characteristics
2-40 Revision 6
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by SoC Products Group Designer
software when the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-11. The
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, SmartFusion also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation
140 Ω100 Ω
Z0 = 50 Ω
Z0 = 50 Ω
165 Ω
165 Ω
+
–
P
N
P
N
INBUF_LVDS
OUTBUF_LVDS
FPGA FPGA
Bourns Part Number: CAT16-LV4F12
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-41
Timing Characteristics
Table 2-62 • LVDS Minimum and Maximum DC Input and Output Levels
DC Parameter Description Min. Typ. Max. Units
VCCFPGAIOBx Supply voltage 2.375 2.5 2.625 V
VOL Output low voltage 0.9 1.075 1.25 V
VOH Output high voltage 1.25 1.425 1.6 V
IOL1Output lower current 0.65 0.91 1.16 mA
IOH1Output high current 0.65 0.91 1.16 mA
VI Input voltage 0 2.925 V
IIH2Input high leakage current 15 µA
IIL2Input low leakage current 15 µA
VODIFF Differential output voltage 250 350 450 mV
VOCM Output common mode voltage 1.125 1.25 1.375 V
VICM Input common mode voltage 0.05 1.25 2.35 V
VIDIFF Input differential voltage 100 350 mV
Notes:
1. IOL/IOH defined by VODIFF/(resistor network).
2. Currents are measured at 85°C junction temperature.
Table 2-63 • AC Waveforms, Measuring Points, and Cap acitive Loads
Input Low (V) Input High (V) Measur ing Point* (V) VREF (typ.) (V)
1.075 1.325 Cross point –
*Measuring point = Vtrip. See Ta ble 2-21 on page 2-24 for a complete table of trip points.
Table 2-64 • LVDS
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCC F PGA IOBx = 2.3 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Speed Grade tDOUT tDP tDIN tPY Units
Std. 0.60 1.83 0.04 1.87 ns
–1 0.50 1.53 0.03 1.55 ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on
page 2-9 for derating values.
SmartFusion DC and Switching Characteristics
2-42 Revision 6
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to
high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain
any combination of drivers, receivers, and transceivers. SoC Products Group LVDS drivers provide the
higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require
series terminations for better signal quality and to control voltage swing. Termination is also required at
both ends of the bus since the driver can be located anywhere on the bus. These configurations can be
implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.
Multipoint designs using SoC Products Group LVDS macros can achieve up to 200 MHz with a maximum
of 20 loads. A sample application is given in Figure 2-12. The input and output buffer delays are available
in the LVDS section in Tab le 2- 6 4.
Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required
differential voltage, in worst-case commercial operating conditions, at the farthest receiver: RS=60Ω
and RT=70Ω, given Z0=50Ω (2") and Zstub =50Ω (~1.5").
Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
...
R
T
R
T
BIBUF_LVDS
R
+-T
+-R
+-T
+-
D
+-
EN EN EN EN EN
Receiver Transceiver Receiver TransceiverDriver
RSRSRSRSRSRSRSRS
RSRS
Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
Z0
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-43
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Timing Characteristics
Figure 2-13 • LVPECL Circuit Diagram and Board-Level Im plementation
Table 2-65 • Minimum and Maximum DC Input and Output Levels
DC Parameter Description Min. Max. Min. Max. Min. Max. Units
VCCFPGAIOBx Supply Voltage 3.0 3.3 3.6 V
VOL Output Low Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V
VOH Output High Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V
VIL, VIH Input Low, Input High Voltages 0 3.3 0 3.6 0 3.9 V
VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V
VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V
VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V
VIDIFF Input Differential Voltage 300 300 300 mV
Table 2-66 • AC Waveforms, Measuring Points, and Cap acitive Loads
Input Low (V) Input High (V) M easuring Point* (V) VREF (typ.) (V)
1.64 1.94 Cross point –
*Measuring point = Vtrip. See Ta ble 2-21 on page 2-24 for a complete table of trip points.
187 W 100 Ω
Z
0
= 50 Ω
Z
0
= 50 Ω
100 Ω
100 Ω
+
–
P
N
P
N
INBUF_LVPECL
OUTBUF_LVPECL
FPGA FPGA
Bourns Part Number: CAT16-PC4F12
Table 2-67 • LVPECL
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,
Worst-Case VCC F PGA IOBx = 3.0 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Speed Grade tDOUT tDP tDIN tPY Units
Std. 0.60 1.76 0.04 1.76 ns
–1 0.50 1.46 0.03 1.46 ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on
page 2-9 for derating values.
SmartFusion DC and Switching Characteristics
2-44 Revision 6
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchro nous Preset
INBUF
INBUF INBUF
TRIBUF
CLKBUF
INBUF
INBUF
CLKBUF
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive-Edge Triggered
Pad Out
CLK
Enable
Preset
Data_out
Data
EOUT
DOUT
Enable
CLK
DQ
DFN1E1P1
PRE
DQ
DFN1E1P1
PRE
DQ
DFN1E1P1
PRE
D_Enable
A
B
C
D
EE
E
EF
G
H
I
J
L
K
Y
Core
Array
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-45
Table 2-68 • Paramete r Definition and Measuring Nodes
Parameter Name Parameter Definition Measuring Nodes
(from, to)*
tOCLKQ Clock-to-Q of the Output Data Register H, DOUT
tOSUD Data Setup Time for the Output Data Register F, H
tOHD Data Hold Time for the Output Data Register F, H
tOSUE Enable Setup Time for the Output Data Register G, H
tOHE Enable Hold Time for the Output Data Register G, H
tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT
tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H
tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H
tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT
tOESUD Data Setup Time for the Output Enable Register J, H
tOEHD Data Hold Time for the Output Enable Register J, H
tOESUE Enable Setup Time for the Output Enable Register K, H
tOEHE Enable Hold Time for the Output Enable Register K, H
tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H
tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H
tICLKQ Clock-to-Q of the Input Data Register A, E
tISUD Data Setup Time for the Input Data Register C, A
tIHD Data Hold Time for the Input Data Register C, A
tISUE Enable Setup Time for the Input Data Register B, A
tIHE Enable Hold Time for the Input Data Register B, A
tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E
tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A
tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A
*See Figure 2-14 on page 2-44 for more information.
SmartFusion DC and Switching Characteristics
2-46 Revision 6
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
Figure 2-15 • Timing Model of the Registered I /O Buffers with Synchr onous Enable a nd Asynchronous Clear
Enable
CLK
Pad Out
CLK
Enable
CLR
Data_out
Data
Y
AA
EOUT
DOUT
Core
Array
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
D_Enable
BB
CC
DD
EE
FF
GG
LL
HH
JJ
KK
CLKBUF
INBUF
INBUF
TRIBUF
INBUF INBUF CLKBUF
INBUF
Data Input I/O Register with
Active High Enable
Active High Clear
Positive-Edge Triggered Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-47
Table 2-69 • Paramete r Definition and Measuring Nodes
Parameter Name Parameter Definition Measuring Nodes
(from, to)*
tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT
tOSUD Data Setup Time for the Output Data Register FF, HH
tOHD Data Hold Time for the Output Data Register FF, HH
tOSUE Enable Setup Time for the Output Data Register GG, HH
tOHE Enable Hold Time for the Output Data Register GG, HH
tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT
tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH
tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH
tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT
tOESUD Data Setup Time for the Output Enable Register JJ, HH
tOEHD Data Hold Time for the Output Enable Register JJ, HH
tOESUE Enable Setup Time for the Output Enable Register KK, HH
tOEHE Enable Hold Time for the Output Enable Register KK, HH
tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH
tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH
tICLKQ Clock-to-Q of the Input Data Register AA, EE
tISUD Data Setup Time for the Input Data Register CC, AA
tIHD Data Hold Time for the Input Data Register CC, AA
tISUE Enable Setup Time for the Input Data Register BB, AA
tIHE Enable Hold Time for the Input Data Register BB, AA
tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE
tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA
tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA
*See Figure 2-15 on page 2-46 for more information.
SmartFusion DC and Switching Characteristics
2-48 Revision 6
Input Register
Timing Characteristics
Figure 2-16 • Input Register Timing Diagram
50%
Preset
Clear
Out_1
CLK
Data
Enable
t
ISUE
50%
50%
t
ISUD
t
IHD
50% 50%
t
ICLKQ
10
t
IHE
t
IRECPRE
t
IREMPRE
t
IRECCLR
t
IREMCLR
t
IWCLR
t
IWPRE
t
IPRE2Q
t
ICLR2Q
t
ICKMPWH
t
ICKMPWL
50% 50%
50% 50% 50%
50% 50%
50% 50% 50% 50% 50% 50%
50%
Table 2-70 • Input Data Register Propagation Delays
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V
Parameter Description –1 Std. Units
tICLKQ Clock-to-Q of the Input Data Register 0.24 0.29 ns
tISUD Data Setup Time for the Input Data Register 0.27 0.32 ns
tIHD Data Hold Time for the Input Data Register 0.00 0.00 ns
tISUE Enable Setup Time for the Input Data Register 0.38 0.45 ns
tIHE Enable Hold Time for the Input Data Register 0.00 0.00 ns
tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.46 0.55 ns
tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.46 0.55 ns
tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns
tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.23 0.27 ns
tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 ns
tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.23 0.27 ns
tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.22 ns
tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.22 ns
tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.36 0.36 ns
tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.32 0.32 ns
Note: For the derating values at sp ecific junctio n temperature and voltage sup ply levels, refer to Table 2-7 on page 2-9
for derating values.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-49
Output Register
Timing Characteristics
Figure 2-17 • Output Register Timing Diagram
Preset
Clear
DOUT
CLK
Data_out
Enable
tOSUE
50%
50%
tOSUD tOHD
50% 50%
tOCLKQ
10
tOHE
tORECPRE
tOREMPRE
tORECCLR tOREMCLR
tOWCLR
tOWPRE
tOPRE2Q
tOCLR2Q
tOCKMPWH tOCKMPWL
50% 50%
50% 50% 50%
50% 50%
50% 50% 50% 50% 50% 50%
50%
50%
Table 2-71 • Output Data Regi ster Propagation Delays
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V
Parameter Description –1 Std. Units
tOCLKQ Clock-to-Q of the Output Data Register 0.60 0.72 ns
tOSUD Data Setup Time for the Output Data Register 0.32 0.38 ns
tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns
tOSUE Enable Setup Time for the Output Data Register 0.44 0.53 ns
tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns
tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.82 0.98 ns
tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.82 0.98 ns
tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 ns
tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.23 0.27 ns
tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns
tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.23 0.27 ns
tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.22 ns
tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.22 ns
tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.36 0.36 ns
tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.32 0.32 ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on
page 2-9 for derating values.
SmartFusion DC and Switching Characteristics
2-50 Revision 6
Output Enable Register
Timing Characteristics
Figure 2-18 • Output Enable Register Timing Diagram
50%
Preset
Clear
EOUT
CLK
D_Enable
Enable
t
OESUE
50%
50%
t
OESUD
t
OEHD
50% 50%
t
OECLKQ
10
t
OEHE
t
OERECPRE
t
OEREMPRE
t
OERECCLR
t
OEREMCLR
t
OEWCLR
t
OEWPRE
t
OEPRE2Q
t
OECLR2Q
t
OECKMPWH
t
OECKMPWL
50% 50%
50% 50% 50%
50% 50%
50% 50% 50% 50% 50% 50%
50%
Table 2-72 • Output Enable Register Propagation Delays
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V
Parameter Description –1 Std. Units
tOECLKQ Clock-to-Q of the Output Enable Register 0.45 0.54 ns
tOESUD Data Setup Time for the Output Enable Register 0.32 0.38 ns
tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 ns
tOESUE Enable Setup Time for the Output Enable Register 0.44 0.53 ns
tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 ns
tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.68 0.81 ns
tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.68 0.81 ns
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns
tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.23 0.27 ns
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns
tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.23 0.27 ns
tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.22 0.22 ns
tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.22 ns
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.36 0.36 ns
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register 0.32 0.32 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-7 on page 2-9 for derating values.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-51
DDR Module Specifications
Input DDR Module
Figure 2- 19 • Input DDR Timing Model
Table 2-73 • Parameter Definitions
Parameter Name Paramete r Definition Measuring Nodes (from, to)
tDDRICLKQ1 Clock-to-Out Out_QR B, D
tDDRICLKQ2 Clock-to-Out Out_QF B, E
tDDRISUD Data Setup Time of DDR input A, B
tDDRIHD Data Hold Time of DDR input A, B
tDDRICLR2Q1 Clear-to-Out Out_QR C, D
tDDRICLR2Q2 Clear-to-Out Out_QF C, E
tDDRIREMCLR Clear Removal C, B
tDDRIRECCLR Clear Recovery C, B
Input DDR
Data
CLK
CLKBUF
INBUF
Out_QF
(to core)
FF2
FF1
INBUF
CLR
DDR_IN
E
A
B
C
D
Out_QR
(to core)
SmartFusion DC and Switching Characteristics
2-52 Revision 6
Timing Characteristics
Figure 2-20 • Input DDR Timing Diagram
t
DDRICLR2Q2
t
DDRIREMCLR
t
DDRIRECCLR
t
DDRICLR2Q1
12 3 4 5 6 7 8 9
CLK
Data
CLR
Out_QR
Out_QF
t
DDRICLKQ1
246
357
t
DDRIHD
t
DDRISUD
t
DDRICLKQ2
Table 2-74 • Input DDR Propagation Delays
Worst Commercial-Case Conditions: TJ = 85°C, Worst Case VCC = 1.42 5 V
Parameter Description –1 Units
tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.39 ns
tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.28 ns
tDDRISUD Data Setup for Input DDR 0.29 ns
tDDRIHD Data Hold for Input DDR 0.00 ns
tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.58 ns
tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.47 ns
tDDRIREMCLR Asynchronous Clear Removal time for Input DDR 0.00 ns
tDDRIRECCLR Asynchronous Clear Recovery time for Input DDR 0.23 ns
tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 ns
tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.36 ns
tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.32 ns
FDDRIMAX Maximum Frequency for Input DDR 350 MHz
Note: For derating values at specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9
for derating values.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-53
Output DDR Module
Figure 2- 21 • Output DDR Timing Model
Table 2-75 • Parameter Definitions
Parameter Name Paramete r Definition Measuring Nodes (from, to)
tDDROCLKQ Clock-to-Out B, E
tDDROCLR2Q Asynchronous Clear-to-Out C, E
tDDROREMCLR Clear Removal C, B
tDDRORECCLR Clear Recovery C, B
tDDROSUD1 Data Setup Data_F A, B
tDDROSUD2 Data Setup Data_R D, B
tDDROHD1 Data Hold Data_F A, B
tDDROHD2 Data Hold Data_R D, B
Data_F
(from core)
CLK
CLKBUF
Out
FF2
INBUF
CLR
DDR_OUT
Output DDR
FF1
0
1
X
X
X
X
X
X
X
A
B
D
E
C
C
B
OUTBUF
Data_R
(from core)
SmartFusion DC and Switching Characteristics
2-54 Revision 6
Timing Characteristics
Figure 2-22 • Output DDR Timing Diagram
116
1
7
2
8
3
910
45
28 3 9
t
DDROREMCLR
t
DDROHD1
t
DDROREMCLR
t
DDROHD2
t
DDROSUD2
t
DDROCLKQ
t
DDRORECCLR
CLK
Data_R
Data_F
CLR
Out
t
DDROCLR2Q
7104
Table 2-76 • Output DDR Propagation Delays
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V
Parameter Description –1 Units
tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.71 ns
tDDROSUD1 Data_F Data Setup for Output DDR 0.38 ns
tDDROSUD2 Data_R Data Setup for Output DDR 0.38 ns
tDDROHD1 Data_F Data Hold for Output DDR 0.00 ns
tDDROHD2 Data_R Data Hold for Output DDR 0.00 ns
tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.81 ns
tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 ns
tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.23 ns
tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 ns
tDDROCKMPWH Clock Minimum Pulse Width High for the Output DDR 0.36 ns
tDDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR 0.32 ns
FDDOMAX Maximum Frequency for the Output DDR 350 MHz
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-7 on page 2-9 for derating values.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-55
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The SmartFusion library offers all combinations of LUT-3 combinatorial functions. In this section, timing
characteristics are presented for a sample of the library. For more details, refer to the IGLOO/e, Fusion,
ProASIC3/E, and SmartFusion Macro Library Guide.
Figure 2- 23 • Sample of Combinatorial Cells
MAJ3
A
C
BY
MUX2
B
0
1
A
S
Y
AY
B
B
A
XOR2 Y
NOR2
B
A
Y
B
A
YOR2
INV
A
Y
AND2
B
A
Y
NAND3
B
A
C
XOR3 Y
B
A
C
NAND2
SmartFusion DC and Switching Characteristics
2-56 Revision 6
Figure 2- 24 • Timing Mode l and Waveforms
tPD
A
B
tPD = MAX(tPD(RR), tPD(RF),
tPD(FF), tPD(FR)) where edges are
applicable for the particular
combinatorial cell
Y
NAND2 or
Any Combinatorial
Logic
tPD
tPD
50%
VCC
VCC
VCC
50%
GND
A, B, C
50% 50%
50%
(RR)
(RF) GND
OUT
OUT
GND
50%
(FF)
(FR)
tPD
tPD
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-57
Timing Characteristics
VersaTile Sp ecifications as a Sequential Module
The SmartFusion library offers a wide variety of sequential cells, including flip-flops and latches. Each
has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented
for a representative sample from the library. For more details, refer to the IGLOO/e, Fusion, ProASIC3/E,
and SmartFusion Macro Library Guide.
Table 2-77 • Comb inatorial Cell Propagation Delays
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V
Combinatorial Cell Equation Parameter –1 Std. Units
INV Y = !A tPD 0.41 0.49 ns
AND2 Y = A · B tPD 0.48 0.57 ns
NAND2 Y = !(A · B) tPD 0.48 0.57 ns
OR2 Y = A + B tPD 0.49 0.59 ns
NOR2 Y = !(A + B) tPD 0.49 0.59 ns
XOR2 Y = A ⊕ Bt
PD 0.75 0.90 ns
MAJ3 Y = MAJ(A, B, C) tPD 0.71 0.85 ns
XOR3 Y = A ⊕ B ⊕ Ct
PD 0.89 1.07 ns
MUX2 Y = A !S + B S tPD 0.51 0.62 ns
AND3 Y = A · B · C tPD 0.57 0.68 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for
derating values.
Figure 2- 25 • Sample of Sequential Cells
DQ
DFN1
Data
CLK
Out
DQ
DFN1C1
Data
CLK
Out
CLR
DQ
DFI1E1P1
Data
CLK
Out
En
PRE
DQ
DFN1E1
Data
CLK
Out
En
SmartFusion DC and Switching Characteristics
2-58 Revision 6
Timing Characteristics
Figure 2-26 • Timing Model and Waveforms
PRE
CLR
Out
CLK
Data
EN
tSUE
50%
50%
tSUD
tHD
50% 50%
tCLKQ
0
tHE
tRECPRE tREMPRE
tRECCLR tREMCLRtWCLR
tWPRE
tPRE2Q tCLR2Q
tCKMPWH tCKMPWL
50% 50%
50% 50% 50%
50% 50%
50% 50% 50% 50% 50% 50%
50%
50%
Table 2-78 • Register Delays
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V
Parameter Description –1 Std. Units
tCLKQ Clock-to-Q of the Core Register 0.56 0.67 ns
tSUD Data Setup Time for the Core Register 0.44 0.52 ns
tHD Data Hold Time for the Core Register 0.00 0.00 ns
tSUE Enable Setup Time for the Core Register 0.46 0.55 ns
tHE Enable Hold Time for the Core Register 0.00 0.00 ns
tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.41 0.49 ns
tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.41 0.49 ns
tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns
tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.23 0.27 ns
tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns
tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.23 0.27 ns
tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.22 ns
tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.22 ns
tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.32 0.32 ns
tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.36 0.36 ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-7 on page 2-9 for derating values.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-59
Global Resource Characteristics
A2F200 Clock Tree Topology
Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A2F200 device. It
is used to drive all D-flip-flops in the device.
Figure 2-27 • Example of Global Tree Use in an A2F200 Device for Clock Routing
Central
Global Rib
VersaTile
Rows
Global Spine
CCC
SmartFusion DC and Switching Characteristics
2-60 Revision 6
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-63. Ta ble 2 -8 0 presents minimum and maximum
global clock delays for the A2F200 device. Minimum and maximum delays are measured with minimum
and maximum loading.
Timing Characteristics
Table 2-79 • A2F500 Global Resource
Worst Commercial-Case Conditions: TJ = 85°C, VCC = 1.425 V
Parameter Description
–1 Std.
UnitsMin.1Max.2Min.1Max.2
tRCKL Input Low Delay for Global Clock 1.54 1.73 1.84 2.08 ns
tRCKH Input High Delay for Global Clock 1.53 1.76 1.84 2.12 ns
tRCKMPWH Minimum Pulse Width High for Global Clock ns
tRCKMPWL Minimum Pulse Width Low for Global Clock ns
tRCKSW Maximum Skew for Global Clock 0.23 0.28 ns
FRMAX Maximum Frequency for Global Clock MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, locat ed in a lightly loaded row (single element is connected to the global net ).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for derating
values.
Table 2-80 • A2F200 Global Resource
Worst Commercial-Case Conditions: TJ = 85°C, VCC = 1.425 V
Parameter Description
–1 Std.
UnitsMin.1Max.2Min.1Max.2
tRCKL Input Low Delay for Global Clock 0.74 0.99 0.88 1.19 ns
tRCKH Input High Delay for Global Clock 0.76 1.05 0.91 1.26 ns
tRCKMPWH Minimum Pulse Width High for Global Clock ns
tRCKMPWL Minimum Pulse Width Low for Global Clock ns
tRCKSW Maximum Skew for Global Clock 0.29 0.35 ns
FRMAX Maximum Frequency for Global Clock MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, locat ed in a lightly loaded row (single element is connected to the global net ).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for derating
values.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-61
RC Oscillator
The table below describes the electrical characteristics of the RC oscillator.
RC Oscillator Characteristics
Table 2-81 • Electrical Characteristics of the RC Oscillator
Parameter Description Condition Min. Typ.
Max.
Units
FRC Operating
frequency
100 MHz
Accuracy Temperature: 0°C to 85°C
Voltage: 3.3 V ± 5%
1 %
Output jitter Period jitter (at 5 K cycles) 100 ps
Cycle-to-cycle jitter (at 5 K cycles) 100 ps
Period jitter (at 5 K cycles) with 1 KHz / 300
mV peak-to-peak noise on power supply
150 ps
Cycle-to-cycle jitter (at 5 K cycles) with 1 KHz /
300 mV peak-to-peak noise on power supply
150 ps
Output duty
cycle
3.3 V domain 1 %
IDYNRC Operating
current
1.5 V domain 2 mA
SmartFusion DC and Switching Characteristics
2-62 Revision 6
Main and Lower Power Crystal Oscillator
The tables below describes the electrical characteristics of the main and low power crystal oscillator.
Table 2-82 • Electrical Ch aracteristics of the Main Crystal Oscillator
Parameter Description Condition Min. Typ. Max. Units
Operating frequency Using external crystal 0.032 20 MHz
Using ceramic resonator 0.5 8 MHz
Using RC Network 0.032 4 MHz
Output duty cycle 50 %
Output jitter With 10 MHz crystal 50 ps
RMS
IDYNXTAL Operating current RC 0.6 mA
0.032–0.2 0.6 mA
0.2–2.0 0.6 mA
2.0–20.0 0.6 mA
ISTBXTAL Standby current of crystal oscillator 10 µA
PSRRXTAL Power supply noise tolerance 0.5 Vp-p
VIHXTAL Input logic level High 90%
of
VCC
V
VILXTAL Input logic level Low 10%
of
VCC
V
Startup time RC µs
0.032–0.2 µs
0.2–2.0 µs
2.0–20.0 µs
Table 2-83 • Electrical Characteristics of the Low Power Oscillator
Parameter Description Condition Min. Typ. Max. Units
Operating frequency 32 KHz
Output duty cycle 50 %
Output jitter 50 ps
RMS
IDYNXTAL Operating current 32 KHz 10 µA
ISTBXTAL Standby current of crystal oscillator µA
PSRRXTAL
Power supply noise tolerance 0.5 Vp-p
VIHXTAL Input logic level High 90% of VCC V
VILXTAL Input logic level Low 10% of VCC V
Startup time Test load used: 20 pF 2.5 s
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-63
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-84 • SmartFusion CCC/PLL Specification
Parameter Minimum Typical Maximum Units
Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 3501MHz
Delay Increments in Programmable Delay Blocks2, 3 160 ps
Number of Programmable Values in Each Programmable
Delay Block
32
Input Period Jitter 1.5 ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max Peak-to-Peak Period Jitter
1 Global
Network
Used
3 Global
Networks
Used
0.75 MHz to 24 MHz 0.50% 0.70%
24 MHz to 100 MHz 1.00% 1.20%
100 MHz to 250 MHz 1.75% 2.00%
250 MHz to 350 MHz 2.50% 5.60%
Acquisition Time
LockControl = 0 300 µs
LockControl = 1 6.0 ms
Tracking Jitter4
LockControl = 0 1.6 ns
LockControl = 1 0.8 ns
Output Duty Cycle 48.5 5.15 %
Delay Range in Block: Programmable Delay 12,3 0.6 5.56 ns
Delay Range in Block: Programmable Delay 22,3 0.025 5.56 ns
Delay Range in Block: Fixed Delay2,3 2.2 ns
Notes:
1. One of the CCC outputs (GLA0) is used as an MSS clock and is limited to 100 MHz (maximum) by software. Details
regarding CCC/PLL are in the "PLLs, Clock Conditioning Circuitry, and On-Chip Crystal Oscillators" chapter of the
SmartFusion Microcontroller Subsystem User's Guide.
2. This delay is a function of voltage and temperature. See Table 2-7 on page 2-9 for deratings.
3. TJ = 25°C, VCC = 1.5 V
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
Note: Peak-to-peak jitter measurements are defi ned by T peak-to-peak = Tperiod_max – Tperiod_min.
Figure 2-28 • Peak-to-Peak Jitter Definition
T
period_max
T
period_min
Output Signal
SmartFusion DC and Switching Characteristics
2-64 Revision 6
FPGA Fabric SRAM and FIFO Characteristics
FPGA Fabric SRAM
Figure 2- 29 • RAM Models
ADDRA11 DOUTA8
DOUTA7
DOUTA0
DOUTB8
DOUTB7
DOUTB0
ADDRA10
ADDRA0
DINA8
DINA7
DINA0
WIDTHA1
WIDTHA0
PIPEA
WMODEA
BLKA
WENA
CLKA
ADDRB11
ADDRB10
ADDRB0
DINB8
DINB7
DINB0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WENB
CLKB
RAM4K9
RADDR8 RD17
RADDR7 RD16
RADDR0 RD0
WD17
WD16
WD0
WW1
WW0
RW1
RW0
PIPE
REN
RCLK
RAM512X18
WADDR8
WADDR7
WADDR0
WEN
WCLK
RESET
RESET
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-65
Timing Waveforms
Figure 2- 30 • RAM Read for Pass-Through Output
Figure 2- 31 • RAM Read for Pipelined Output
CLK
ADD
BLK_B
WEN_B
DO
A0A1A2
D0D1D2
tCYC
tCKH tCKL
tAS tAH
tBKS
tENS tENH
tDOH1
tBKH
Dn
tCKQ1
CLK
ADD
BLK_B
WEN_B
DO
A0A1A2
D0D1
tCYC
tCKH tCKL
tAS tAH
tBKS
tENS tENH
tDOH2
tCKQ2
tBKH
Dn
SmartFusion DC and Switching Characteristics
2-66 Revision 6
Figure 2- 32 • RAM Write, Output Retained (WMODE = 0)
Figure 2- 33 • RAM Write, Output as Write Data (WMODE = 1)
tCYC
tCKH tCKL
A0A1A2
DI0DI1
tAS tAH
tBKS
tENS tENH
tDS tDH
CLK
BLK_B
WEN_B
ADD
DI
Dn
DO
tBKH
D2
tCYC
tCKH tCKL
A0A1A2
DI0DI1
tAS tAH
tBKS
tENS
tDS tDH
CLK
BLK_B
WEN_B
ADD
DI
tBKH
DO
(pass-through) DI1
DnDI0
DO
(pipelined) DI0DI1
Dn
DI2
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-67
Figure 2- 34 • RAM Reset
CLK
RESET_B
DO Dn
tCYC
tCKH tCKL
tRSTBQ
Dm
SmartFusion DC and Switching Characteristics
2-68 Revision 6
Timing Characteristics
Table 2-85 • RAM4K9
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V
Parameter Description –1 Std. Units
tAS Address setup time 0.25 0.30 ns
tAH Address hold time 0.00 0.00 ns
tENS REN_B, WEN_B setup time 0.15 0.17 ns
tENH REN_B, WEN_B hold time 0.10 0.12 ns
tBKS BLK_B setup time 0.24 0.28 ns
tBKH BLK_B hold time 0.02 0.02 ns
tDS Input data (DI) setup time 0.19 0.22 ns
tDH Input data (DI) hold time 0.00 0.00 ns
tCKQ1 Clock High to new data valid on DO (output retained, WMODE = 0) 1.81 2.18 ns
Clock High to new data valid on DO (flow-through, WMODE = 1) 2.39 2.87 ns
tCKQ2 Clock High to new data valid on DO (pipelined) 0.91 1.09 ns
tC2CWWH Address collision clk-to-clk delay for reliable write after write on same
address—applicable to rising edge
0.30 0.35 ns
tC2CRWH Address collision clk-to-clk delay for reliable read access after write on same
address—applicable to opening edge
0.45 0.52 ns
tC2CWRH Address collision clk-to-clk delay for reliable write access after read on same
address— applicable to opening edge
0.49 0.57 ns
tRSTBQ RESET_B Low to data out Low on DO (flow-through) 0.94 1.12 ns
RESET_B Low to Data Out Low on DO (pipelined) 0.94 1.12 ns
tREMRSTB RESET_B removal 0.29 0.35 ns
tRECRSTB RESET_B recovery 1.52 1.83 ns
tMPWRSTB RESET_B minimum pulse width 0.22 0.22 ns
tCYC Clock cycle time 3.28 3.28 ns
FMAX Maximum clock frequency 305 305 MHz
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on
page 2-9 for derating values.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-69
Table 2-86 • RAM512X18
Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V
Parameter Description –1 Std. Units
tAS Address setup time 0.25 0.30 ns
tAH Address hold time 0.00 0.00 ns
tENS REN_B, WEN_B setup time 0.09 0.11 ns
tENH REN_B, WEN_B hold time 0.06 0.07 ns
tDS Input data (DI) setup time 0.19 0.22 ns
tDH Input data (DI) hold time 0.00 0.00 ns
tCKQ1 Clock High to new data valid on DO (output retained, WMODE = 0) 2.19 2.63 ns
tCKQ2 Clock High to new data valid on DO (pipelined) 0.91 1.09 ns
tC2CRWH Address collision clk-to-clk delay for reliable read access after write on same
address—applicable to opening edge
0.50 0.58 ns
tC2CWRH Address collision clk-to-clk delay for reliable write access after read on same
address—applicable to opening edge
0.59 0.67 ns
tRSTBQ RESET_B Low to data out Low on DO (flow-through) 0.94 1.12 ns
RESET_B Low to data out Low on DO (pipelined) 0.94 1.12 ns
tREMRSTB RESET_B removal 0.29 0.35 ns
tRECRSTB RESET_B recovery 1.52 1.83 ns
tMPWRSTB RESET_B minimum pulse width 0.22 0.22 ns
tCYC Clock cycle time 3.28 3.28 ns
FMAX Maximum clock frequency 305 305 MHz
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on
page 2-9 for derating values.
SmartFusion DC and Switching Characteristics
2-70 Revision 6
FIFO
Figure 2- 35 • FIFO Model
FIFO4K18
RW2
RD17
RW1
RD16
RW0
WW2
WW1
WW0 RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AFVAL11
AEMPTY
AFVAL10
AFVAL0
AEVAL11
AEVAL10
AEVAL0
REN
RBLK
RCLK
WEN
WBLK
WCLK
RPIPE
WD17
WD16
WD0
RESET
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-71
Timing Waveforms
Figure 2-36 • FIFO Reset
Figure 2-37 • FIFO EMPTY Flag and AEMPTY Flag Assertion
MATCH (A0)
tMPWRSTB
tRSTFG
tRSTCK
tRSTAF
RCLK/
WCLK
RESET_B
EMPTY
AEMPTY
WA/RA
(Address Counter)
tRSTFG
tRSTAF
FULL
AFULL
RCLK
NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY)
tCKAF
tRCKEF
EMPTY
AEMPTY
tCYC
WA/RA
(Address Counter)
SmartFusion DC and Switching Characteristics
2-72 Revision 6
Figure 2-38 • FIFO FULL Flag and AFULL Flag Assertion
Figure 2-39 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
Figure 2-40 • FIFO FULL Flag and AFULL Flag Deassertion
NO MATCH NO MATCH Dist = AFF_TH MATCH (FULL)
tCKAF
tWCKFF
tCYC
WCLK
FULL
AFULL
WA/RA
(Address Counter)
WCLK
WA/RA
(Address Counter) MATCH
(EMPTY) NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1
NO MATCH
RCLK
EMPTY
1st Rising
Edge
After 1st
Write
2nd Rising
Edge
After 1st
Write
tRCKEF
tCKAF
AEMPTY
Dist = AFF_TH – 1
MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH
t
WCKF
t
CKAF
1st Rising
Edge
After 1st
Read
1st Rising
Edge
After 2nd
Read
RCLK
WA/RA
(Address Counter)
WCLK
FULL
AFULL
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-73
Timing Characteristics
Embedded Nonvolatile Memory Block (eNVM)
Electrical Characteristics
Table 2-88 describes the eNVM maximum performance.
Table 2-87 • FIFO
Worst Commercial-Case Conditions: TJ = 85°C, VCC = 1.425 V
Parameter Description –1 Std. Units
tENS REN_B, WEN_B Setup Time 1.40 1.68 ns
tENH REN_B, WEN_B Hold Time 0.02 0.02 ns
tBKS BLK_B Setup Time 0.19 0.19 ns
tBKH BLK_B Hold Time 0.00 0.00 ns
tDS Input Data (DI) Setup Time 0.19 0.22 ns
tDH Input Data (DI) Hold Time 0.00 0.00 ns
tCKQ1 Clock High to New Data Valid on DO (flow-through) 2.39 2.87 ns
tCKQ2 Clock High to New Data Valid on DO (pipelined) 0.91 1.09 ns
tRCKEF RCLK High to Empty Flag Valid 1.74 2.09 ns
tWCKFF WCLK High to Full Flag Valid 1.66 1.99 ns
tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.29 7.54 ns
tRSTFG RESET_B Low to Empty/Full Flag Valid 1.72 2.06 ns
tRSTAF RESET_B Low to Almost Empty/Full Flag Valid 6.22 7.47 ns
tRSTBQ RESET_B Low to Data Out Low on DO (flow-through) 0.94 1.12 ns
RESET_B Low to Data Out Low on DO (pipelined) 0.94 1.12 ns
tREMRSTB RESET_B Removal 0.29 0.35 ns
tRECRSTB RESET_B Recovery 1.52 1.83 ns
tMPWRSTB RESET_B Minimum Pulse Width 0.22 0.22 ns
tCYC Clock Cycle Time 3.28 3.28 ns
FMAX Maximum Frequency for FIFO 305 305 MHz
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-7 on page 2-9 for derating values.
Table 2-88 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C, VCC = 1.425 V
Parameter Description
A2F200 A2F500
Units–1 Std. –1 Std.
tFMAXCLKeNVM Maximum frequency for clock for the control logic – 6 cycles
(6:1:1:1*)
80 80 50 50 MHz
tFMAXCLKeNVM Maximum frequency for clock for the control logic – 5 cycles
(5:1:1:1*)
100 80 100 80 MHz
Note: *6:1:1:1 indicates 6 cycles for the first access and 1 each for the next three accesses. 5:1:1:1 indicates 5 cycles
for the first access and 1 each fo r the ne xt three accesses.
SmartFusion DC and Switching Characteristics
2-74 Revision 6
Embedded FlashROM (eFROM)
Electrical Characteristics
Table 2-89 describes the eFROM maximum performance
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-19 for more details.
Timing Characteristics
Table 2-89 • FlashROM Access Time, Worse Commercial Case Cond itions: TJ = 85°C, VCC = 1.425 V
Parameter Description –1 Std. Units
tCK2Q Clock to out per configuration* 28.68 32.98 ns
Fmax Maximum Clock frequency 15.00 15.00 MHz
Table 2-90 • JTAG 1532
Worst Commercial-Case Conditions: TJ = 85°C, Wors t-Case VCC = 1.425 V
Parameter Description –1 Std. Units
tDISU Test Data Input Setup Time 0.67 0.77 ns
tDIHD Test Data Input Hold Time 1.33 1.53 ns
tTMSSU Test Mode Select Setup Time 0.67 0.77 ns
tTMDHD Test Mode Select Hold Time 1.33 1.53 ns
tTCK2Q Clock to Q (data out) 8.00 9.20 ns
tRSTB2Q Reset to Q (data out) 26.67 30.67 ns
FTCKMAX TCK Maximum Frequency 19.00 21.85 MHz
tTRSTREM ResetB Removal Time 0.00 0.00 ns
tTRSTREC ResetB Recovery Time 0.27 0.31 ns
tTRSTMPW ResetB Minimum Pulse TBD TBD ns
Note: For specific junction temperature and voltag e supply levels, refer to Table 2-7 on page 2-9 for derating values.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-75
Programmable Analog Specifications
Current Monitor
Unless otherwise noted, current monitor performance is specified at 25°C with nominal power supply
voltages, with the output measured using the internal voltage reference with the internal ADC in 12-bit
mode and 91 Ksps, after digital compensation. All results are based on averaging over 16 samples.
Table 2-91 • Current Monitor Pe rformance Specification
Specification Test Conditions Min. Typical Max. Units
Input voltage range (for driving ADC
over full range)
0 – 48 0 – 50 1 – 51 mV
Analog gain From the differential voltage across the
input pads to the ADC input
50 V/V
Input referred offset voltage Input referred offset voltage 0 0.1 0.5 mV
–40ºC to +100ºC 0 0.1 0.5 mV
Gain error Slope of BFSL vs. 50 V/V ±0.1 ±0.5 % nom.
–40ºC to +100ºC ±0.5 % nom.
Overall Accuracy Peak error from ideal transfer function,
25°C
±(0.1 +
0.25%)
±(0.4 +
1.5%)
mV plus
%
reading
Input referred noise 0 VDC input (no output averaging) 0.3 0.4 0.5 mVrms
Common-mode rejection ratio 0 V to 12 VDC common-mode voltage –86 –87 dB
Analog settling time To 0.1% of final value (with ADC load)
From CM_STB (High) 5 µs
From ADC_START (High) 5 200 µs
Input capacitance 8pF
Input biased current CM[n] or TM[n] pad,
–40°C to +100°C over maximum input
voltage range (plus is into pad)
Strobe = 0; IBIAS on CM[n] 0 µA
Strobe = 1; IBIAS on CM[n] 1 µA
Strobe = 0; IBIAS on TM[n] 2 µA
Strobe = 1; IBIAS on TM[n] 1 µA
Power supply rejection ratio DC (0 – 10 KHz) 41 42 dB
Incremental operational current
monitor power supply current
requirements (per current monitor
instance, not including ADC or
VAREFx)
VCC33A 150 µA
VCC33AP 140 µA
VCC15A 50 µA
Note: Under no condition should the TM pad ever be greate r than 1 0 mV above than the CM pad.
SmartFusion DC and Switching Characteristics
2-76 Revision 6
Temperature Monitor
Unless otherwise noted, temperature monitor performance is specified with a 2N3904 diode-connected
bipolar transistor from National Semiconductor or Infineon Technologies, nominal power supply voltages,
with the output measured using the internal voltage reference with the internal ADC in 12-bit mode and
62.5 Ksps. After digital compensation. Unless otherwise noted, the specifications pertain to conditions
where the SmartFusion device and the sensing diode are at the same temperature.
Table 2-92 • Temperature Monitor Performanc e Spe c ifications
Specification Test Conditions Min. Typical Max. Units
Input diode temperature range –55 150 °C
233.2 378.15 K
Temperature sensitivity 2.5 mV/K
Intercept Extrapolated to 0K 0 V
Input referred temperature offset
error
At 25°C (298.15K) ±1 1.5 °C
Gain error Slope of BFSL vs. 2.5 mV/K ±1 2.5 % nom.
Overall accuracy Peak error from ideal transfer function ±2 ±3 °C
Input referred noise At 25°C (298.15K) – no output averaging 4 °C rms
Output current Idle mode 100 µA
Final measurement phases 10 µA
Analog settling time Measured to 0.1% of final value, (with
ADC load)
From TM_STB (High) 5 µs
From ADC_START (High) 5 105 µs
AT parasitic capacitance 500 pF
Power supply rejection ratio DC (0–10 KHz) 1.2 0.7 °C/V
Input referred temperature
sensitivity error
Variation due to device temperature
(–40°C to +100°C). External temperature
sensor held constant.
0.005 0.008 °C/°C
Temperature monitor (TM)
operational power supply current
requirements (per temperature
monitor instance, not including ADC
or VAREFx)
VCC33A 200 µA
VCC33AP 150 µA
VCC15A 50 µA
Note: All results are based on averaging over 64 samples.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-77
Analog-to-Digital Converter (ADC)
Unless otherwise noted, ADC direct input performance is specified at 25°C with nominal power supply
voltages, with the output measured using the external voltage reference with the internal ADC in 12-bit
mode and 500 KHz sampling frequency, after trimming and digital compensation.
Figure 2-41 • Temperature Error Versus External Capacitance
-7
-6
-5
-4
-3
-2
-1
0
1
1.00E -06 1.00E -05 1.00E -04 1.00E -03 1.00E -02 1.00E -01 1.00E+00
Temperature Error (°C)
Capacitance (μF)
Table 2-93 • ADC Specifications
Specification Test Con dition s Min. Typ. Max. Units
Input voltage range (for driving ADC
over its full range)
2.56 V
Gain error ±0.4 ±0.7 %
–40ºC to +100ºC ±0.4 ±0.7 %
Input referred offset voltage ±1 ±2 mV
–40ºC to +100ºC ±1 ±2
Integral non-linearity (INL) RMS deviation from BFSL
12-bit mode 1.71 LSB
10-bit mode 0.60 1.00 LSB
8-bit mode 0.2 0.33 LSB
Differential non-linearity (DNL) 12-bit mode 2.4 LSB
10-bit mode 0.80 0.94 LSB
8-bit mode 0.2 0.23 LSB
Signal to noise ratio 62 64 dB
Note: All 3.3 V supplies are tied tog ether and varied from 3.0 V to 3.6 V. 1.5 V supplies are held constant.
SmartFusion DC and Switching Characteristics
2-78 Revision 6
Effective number of bits (ENOB)
EQ 10
–1 dBFS input
12-bit mode 10 KHz 9.9 10 Bits
12-bit mode 100 KHz 9.9 10 Bits
10-bit mode 10 KHz 9.5 9.6 Bits
10-bit mode 100 KHz 9.5 9.6 Bits
8-bit mode 10 KHz 7.8 7.9 Bits
8-bit mode 100 KHz 7.8 7.9 Bits
Full power bandwidth At –3 dB; –1 dBFS input 300 KHz
Analog settling time To 0.1% of final value (with 1 Kohm source
impedance and with ADC load)
2µs
Input capacitance Switched capacitance (ADC sample
capacitor)
12 15 pF
Cs: Static capacitance (Figure 2-42 on page 2-78)
CM[n] input 5 7 pF
TM[n] input 5 7 pF
ADC[n] input 5 7 pF
Input resistance Rin: Series resistance (Figure 2-42)2KΩ
Rsh: Shunt resistance, exclusive of
switched capacitance effects (Figure 2-42)
10 MΩ
Input leakage current –40°C to +100°C 1 µA
Power supply rejection ratio DC 44 53 dB
ADC power supply operational current
requirements
VCC33ADCx 2.5 mA
VCC15A 2 mA
Figure 2-42 • ADC Input Model
Table 2-93 • ADC Specifications (continued)
Specification Test Con dition s Min. Typ. Max. Units
Note: All 3.3 V supplies are tied tog ether and varied from 3.0 V to 3.6 V. 1.5 V supplies are held constant.
ENOB SINAD 1.76 dB–
6.02 dB/bit
---------------------------------------------=
Rin
RshCswCst
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-79
Analog Bipolar Prescaler (ABPS)
With the ABPS set to its high range setting (GDEC = 00), a hypothetical input voltage in the range –15.36
V to +15.36 V is scaled and offset by the ABPS input amplifier to match the ADC full range of 0 V to 2.56
V using a nominal gain of –0.08333 V/V. However, due to reliability considerations, the voltage applied to
the ABPS input should never be outside the range of –11.5 V to +14.4 V, restricting the usable ADC input
voltage to 2.238 V to 0.080 V and the corresponding 12-bit output codes to the range of 3581 to 128
(decimal), respectively.
Unless otherwise noted, ABPS performance is specified at 25°C with nominal power supply voltages,
with the output measured using the internal voltage reference with the internal ADC in 12-bit mode and
100 KHz sampling frequency, after trimming and digital compensation; and applies to all ranges.
Table 2-94 • ABPS Performance Specifications
Specification Test Conditions Min. Typ. Max. Units
Input voltage range (for driving ADC
over its full range)
GDEC[1:0] = 11 ±2.56 V
GDEC[1:0] = 10 ±5.12 V
GDEC[1:0] = 01 ±10.24 V
GDEC[1:0] = 00 (limited by
maximum rating)
See note 1 V
Analog gain (from input pad to ADC
input)
GDEC[1:0] = 11 –0.5 V/V
GDEC[1:0] = 10 –0.25 V/V
GDEC[1:0] = 01 –0.125 V/V
GDEC[1:0] = 00 –0.0833 V/V
Gain error –2.8 –0.4 0.7 %
–40ºC to +100ºC –2.8 –0.4 0.7 %
Input referred offset voltage
GDEC[1:0] = 11 –0.31 –0.07 0.31 % FR
–40ºC to +100ºC –1.00 1.47 % FR
GDEC[1:0] = 10 –0.34 –0.07 0.34 % FR
–40ºC to +100ºC –0.90 1.37 % FR
GDEC[1:0] = 01 –0.61 –0.07 0.35 % FR
–40ºC to +100ºC –1.05 1.35 % FR
GDEC[1:0] = 00 –0.39 –0.07 0.35 % FR
–40ºC to +100ºC –1.06 1.38 % FR
SINAD 53 56 dB
Non-linearity RMS deviation from BFSL 0.5 % FR
Effective number of bits (ENOB)
EQ 11
GDEC[1:0] = 11
(±2.56 range), –1 dBFS input
12-bit mode 10 KHz 8.6 9.1 Bits
12-bit mode 100 KHz 8.6 9.1 Bits
10-bit mode 10 KHz 8.5 8.9 Bits
10-bit mode 100 KHz 8.5 8.9 Bits
8-bit mode 10 KHz 7.7 7.8 Bits
8-bit mode 100 KHz 7.7 7.8 Bits
Large-signal bandwidth –1 dBFS input 1 MHz
ENOB SINAD 1.76 dB–
6.02 dB/bit
---------------------------------------------=
SmartFusion DC and Switching Characteristics
2-80 Revision 6
Analog settling time To 0.1% of final value (with ADC
load)
10 µs
Input resistance 1MΩ
Power supply rejection ratio DC (0–1 KHz) 38 40 dB
ABPS power supply current
requirements (not including ADC or
VAREFx)
ABPS_EN = 1 (operational mode)
VCC33A 123 134 µA
VCC33AP 89 94 µA
VCC15A 1 µA
Table 2-94 • ABPS Performance Specifications (continued)
Specification Test Conditions Min. Typ. Max. Units
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-81
Comparator
Unless otherwise specified, performance is specified at 25°C with nominal power supply voltages.
Table 2-95 • Comparator Performance Specificatio ns
Specification Test Conditions Min. Typ. Max. Unit s
Input voltage range Minimum 0 V
Maximum 2.56 V
Input offset voltage HYS[1:0] = 00
(no hysteresis)
±1 ±3 mV
Input bias current Comparator 1, 3, 5, 7, 9 (measured at
2.56 V)
40 60 nA
Comparator 0, 2, 4, 6, 8 (measured at
2.56 V)
150 300 nA
Input resistance 10 MΩ
Power supply rejection ratio DC (0 – 10 KHz) 50 60 dB
Propagation delay 100 mV overdrive
HYS[1:0] = 00
(no hysteresis)
15 18 ns
100 mV overdrive
HYS[1:0] = 10
(with hysteresis)
25 30 ns
Hysteresis
(± refers to rising and falling threshold
shifts, respectively)
HYS[1:0] = 00 –5 0 5 mV
–40ºC to +100ºC –5 5 mV
HYS[1:0] = 01 ±3 ± 16 ±30 mV
–40ºC to +100ºC 0 ±36 mV
HYS[1:0] = 10 ±19 ± 31 ±48 mV
–40ºC to +100ºC ±12 ±54 mV
HYS[1:0] = 11 ±80 ± 105 ±190 mV
–40ºC to +100ºC ±80 ±194 mV
Comparator current requirements (per
comparator)
VCC33A = 3.3 V (operational mode);
COMP_EN = 1
VCC33A 150 165 µA
VCC33AP 140 165 µA
VCC15A 1 3 µA
SmartFusion DC and Switching Characteristics
2-82 Revision 6
Analog Sigma-Delta Digital to Analog Converter (DAC)
Unless otherwise noted, sigma-delta DAC performance is specified at 25°C with nominal power supply
voltages, using the internal sigma-delta modulators with 16-bit inputs, HCLK = 100 MHz, modulator
inputs updated at a 100 KHz rate, in voltage output mode with an external 160 pF capacitor to ground,
after trimming and digital [pre-]compensation.
Table 2-96 • Analog Sigma-Delta DAC
Specification Test Conditions Min. Typ. Max. Units
Resolution 8 24 Bits
Output range 0 to 2.56 V
Current output mode 0 to 256 µA
Output Impedance 6 10 12 KΩ
Current output mode 10 MΩ
Output voltage compliance Current output mode 0–3.0 V
–40ºC to +100ºC 0–2.7 0–3.4 V
Gain error Voltage output mode 0.3 ±2 %
A2F200: –40ºC to +100ºC 1.2 ±5.3 %
A2F500: –40ºC to +100ºC 0.3 ±2 %
Current output mode 0.3 ±2 %
A2F200: –40ºC to +100ºC 1.2 ±5.3 %
A2F500: –40ºC to +100ºC 0.3 ±2 %
Output referred offset DACBYTE0 = h’00 (8-bit) 0.25 ±1 mV
–40ºC to +100ºC 1 ±2.5 mV
Current output mode 0.3 ±1 µA
–40ºC to +100ºC 1 ±2.5 µA
Integral non-linearity RMS deviation from BFSL 0.1 0.3 % FR
Differential non-linearity 0.05 0.4 % FR
Analog settling time Refer to
Figure 2-43 on
page 2-83
µs
Power supply rejection ratio DC, full scale output 33 34 dB
Sigma-delta DAC power supply current
requirements (not including VAREFx)
Input = 0, EN = 1
(operational mode)
VCC33SDDx 30 35 µA
VCC15A 3 5 µA
Input = Half scale, EN = 1
(operational mode)
VCC33SDDx 160 165 µA
VCC15A 33 35 µA
Input = Full scale, EN = 1
(operational mode)
VCC33SDDx 280 285 µA
VCC15A 70 75 µA
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-83
Figure 2-43 • Sigma-Delta DAC Setting Time
0
0123 4 56 78910324864128255
20
40
60
80
100
120
140
160
180
200
220
Settling T ime (us)
Input Code
Sigma Delta DAC Settling Time
SmartFusion DC and Switching Characteristics
2-84 Revision 6
Voltage Regulator
Table 2-97 • Voltage Reg ulato r
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VOUT Output voltage TJ = 25°C 1.425 1.5 1.575 V
VOS Output offset voltage TJ = 25°C 11 mV
ICC33A Operation current TJ = 25°C ILOAD = 1 mA 3.4 mA
ILOAD = 100 mA 11 mA
ILOAD = 0.5 A 21 mA
ΔVOUT Load regulation TJ = 25°C ILOAD = 1 mA to 0.5 A 5.8 mV
ΔVOUT Line regulation TJ = 25°C VCC33A = 2.97 V to 3.63 V
ILOAD = 1 mA
5.3 mV/V
VCC33A = 2.97 V to 3.63 V
ILOAD= 100 mA
5.3 mV/V
VCC33A = 2.97 V to 3.63 V
ILOAD = 500mA
5.3 mV/V
Dropout voltage1 T
J = 25°C ILOAD = 1 mA 0.63 V
ILOAD = 100 mA 0.84 V
ILOAD = 0.5 A 1.35 V
IPTBASE PTBase current TJ = 25°C ILOAD = 1 mA 48 µA
ILOAD = 100 mA 736 µA
ILOAD = 0.5 A 12 mA
Startup time2TJ = 25°C 200 ms
Notes:
1. Dropout voltage is defined as the minimum VCC33A voltage. The parameter is specified with respect to the output
voltage. The specification represents the minimum input-to-output differe ntial voltage required to maintain regulation.
2. Assumes 10 µF.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-85
Figure 2- 44 • Typical Output Voltage
Figure 2- 45 • Load Regulation
Load = 10 mA
Load = 100 mA
Load = 500 mA
-0.025
-0.02
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
-40-20 0 20406080100
Offset Voltage (V)
Temperature (°C)
Typical Output Voltage
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
-40 -20 0 20 40 60 80 100
Change in Output Voltage with Load (mV)
Temperature (°C)
Load Regulation
SmartFusion DC and Switching Characteristics
2-86 Revision 6
Serial Peripheral Interface (SPI) Characteristics
This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output
characteristics given for a 35 pF load on the pins and all sequential timing characteristics are related to
SPI_x_CLK. For timing parameter definitions, refer to Figure 2-46 on page 2-87.
Table 2-98 • SPI Characteristics
Commercial Case Conditions: TJ= 85ºC, VDD = 1.425 V, –1 Sp eed Grade
Symbol Description and Condition A2F200 A2F500 Unit
sp1 SPI_x_CLK minimum period
SPI_x_CLK = PCLK/2 NA 20 ns
SPI_x_CLK = PCLK/4 40 40 ns
SPI_x_CLK = PCLK/8 80 80 ns
SPI_x_CLK = PCLK/16 0.16 0.16 µs
SPI_x_CLK = PCLK/32 0.32 0.32 µs
SPI_x_CLK = PCLK/64 0.64 0.64 µs
SPI_x_CLK = PCLK/128 1.28 1.28 µs
SPI_x_CLK = PCLK/256 2.56 2.56 µs
sp2 SPI_x_CLK minimum pulse width high
SPI_x_CLK = PCLK/2 NA 10 ns
SPI_x_CLK = PCLK/4 20 20 ns
SPI_x_CLK = PCLK/8 40 40 ns
SPI_x_CLK = PCLK/16 0.08 0.08 µs
SPI_x_CLK = PCLK/32 0.16 0.16 µs
SPI_x_CLK = PCLK/64 0.32 0.32 µs
SPI_x_CLK = PCLK/128 0.64 0.64 µs
SPI_x_CLK = PCLK/256 1.28 1.28 us
sp3 SPI_x_CLK minimum pulse width low
SPI_x_CLK = PCLK/2 NA 10 ns
SPI_x_CLK = PCLK/4 20 20 ns
SPI_x_CLK = PCLK/8 40 40 ns
SPI_x_CLK = PCLK/16 0.08 0.08 µs
SPI_x_CLK = PCLK/32 0.16 0.16 µs
SPI_x_CLK = PCLK/64 0.32 0.32 µs
SPI_x_CLK = PCLK/128 0.64 0.64 µs
SPI_x_CLK = PCLK/256 1.28 1.28 µs
sp4 SPI_x_CLK, SPI_x_DO, SPI_x_SS rise time (10%-90%) 14.7 4.7 ns
sp5 SPI_x_CLK, SPI_x_DO, SPI_x_SS fall time (10%-90%) 13.4 3.4 ns
Notes:
1. These values are provided for a load of 35 pF. For board design considerations and detailed output buffer resistances,
use the corresponding IBIS models located on the Microsemi SoC Prod ucts Group website:
http://www.actel.com/download/ibis/default.aspx.
2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the SmartFusion
Microcontroller Subsystem User’s Guide.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-87
sp6 Data from master (SPI_x_DO) setup time 21 1 pclk cycles
sp7 Data from master (SPI_x_DO) hold time 21 1 pclk cycles
sp8 SPI_x_DI setup time 21 1 pclk cycles
sp9 SPI_x_DI hold time 21 1 pclk cycles
Figure 2-46 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)
Table 2-98 • SPI Characteristics
Commercial Case Conditions: TJ= 85ºC, VDD = 1.425 V, –1 Sp eed Grade (continued)
Symbol Description and Condition A2F200 A2F500 Unit
Notes:
1. These values are provided for a load of 35 pF. For board design considerations and detailed output buffer resistances,
use the corresponding IBIS models located on the Microsemi SoC Prod ucts Group website:
http://www.actel.com/download/ibis/default.aspx.
2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the SmartFusion
Microcontroller Subsystem User’s Guide.
SPI_x_CLK
SPO = 0
SPI_x_DO
SP6 SP7
50%50%
MSB
50% 50% 50%
SP2
SP1
90%
10% 10%
SP4 SP5
SP8 SP9
50%
50% MSB
SPI_x_DI
10%
90%
SP5
90%
10%
SP4
90%
10%10%
SP4SP5
90%
SPI_x_SS
SPI_x_CLK
SPO = 1
SP3
SmartFusion DC and Switching Characteristics
2-88 Revision 6
Inter-Integrated Circuit (I2C) Characteristics
This section describes the DC and switching of the I2C interface. Unless otherwise noted, all output
characteristics given are for a 100 pF load on the pins. For timing parameter definitions, refer to Figure 2-
47 on page 2-89.
Table 2-99 • I2C Characteristics
Commercial Case Conditions: TJ= 85ºC, VDD = 1.425 V, –1 Speed Gr ade
Parameter Definition Condition Value Unit
VIL Minimum input low voltage – SeeTable 2-35 on
page 2-30
–
Maximum input low voltage – See Ta ble 2 - 35 –
VIH Minimum input high voltage – See Tab le 2 -35 –
Maximum input high voltage – See Ta b le 2- 35 –
VOL Maximum output voltage low IOL =8mA See Tab le 2 -35 –
IIL Input current high – See Tab le 2- 35 –
IIH Input current low – See Tab le 2 -35 –
Vhyst Hysteresis of Schmitt trigger
inputs
– See Table 2-32
on page 2-29
V
TFALL Fall time 2VIHmin to VILMax, Cload = 400 pF 15.0 ns
VIHmin to VILMax, Cload = 100 pF 4.0 ns
TRISE Rise time 2VILMax to VIHmin, Cload = 400pF 19.5 ns
VILMax to VIHmin, Cload = 100pF 5.2 ns
Cin Pin capacitance VIN = 0, f = 1.0 MHz 8.0 pF
Rpull-up Output buffer maximum pull-
down Resistance 1
–50Ω
Rpull-down Output buffer maximum pull-up
Resistance 1
– 150 Ω
Dmax Maximum data rate Fast mode 400 Kbps
tLOW Low period of I2C_x_SCL 3– 1 pclk cycles
tHIGH High period of I2C_x_SCL 3– 1 pclk cycles
tHD;STA START hold time 3– 1 pclk cycles
tSU;STA START setup time 3– 1 pclk cycles
tHD;DAT DATA hold time 3– 1 pclk cycles
tSU;DAT DATA setup time 3– 1 pclk cycles
Notes:
1. These maximum values are provided for information only. Minimum output buffer resistance values depend on
VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output
buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at
http://www.actel.com/download/ibis/default.aspx.
2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located on the SoC Products Group website at
http://www.actel.com/download/ibis/default.aspx.
3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I2C) Peripherals section in the SmartFusion
Microcontroller Subsystem User’s Guide.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 2-89
tSU;STO STOP setup time 3– 1 pclk cycles
tFILT Maximum spike width filtered – 50 ns
Figure 2-47 • I2C Timing Parameter Definition
Table 2-99 • I2C Characteristics
Commercial Case Conditions: TJ= 85ºC, VDD = 1.425 V, –1 Speed Grade (continued)
Parameter Definition Condition Value Unit
Notes:
1. These maximum values are provided for information only. Minimum output buffer resistance values depend on
VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output
buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at
http://www.actel.com/download/ibis/default.aspx.
2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located on the SoC Products Group website at
http://www.actel.com/download/ibis/default.aspx.
3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I2C) Peripherals section in the SmartFusion
Microcontroller Subsystem User’s Guide.
SCL
TRISE TFALL
tLOW
tHD;STA
SDA
tHIGH
tHD;DAT tSU;DAT
tSU;STO
tSU;STA S
P
Revision 6 3-1
3 – SmartFusion Development Tools
SmartFusion applications will be developed by a multi-discipline team of designers working on one
project or one designer acting in several roles. The Microsemi SoC Products Group has developed
design tools and flows to meet the needs of three different skilled designers that can work smoothly
together in a single project (Figure 3-1).
• FPGA designers
• Embedded software designers
• Analog designers
For FPGA designers, Libero® Integrated Design Environment (IDE) is Microsemi SoC Product Group's
comprehensive toolset for designing with all SoC Products Group FPGAs. Libero IDE includes industry
leading synthesis, simulation, and place-and-route debug tools, including Synplicity® and ModelSim,® as
well as innovative timing, power optimization, and power analysis.
For embedded designers, the SoC Products Group offers FREE SoftConsole Eclipse-based IDE, as well
as evaluation versions from Keil™ and IAR Systems. Full versions of the latter are available from the
respective suppliers.
For analog designers, the microcontroller subsystem (MSS) configurator provides graphical setup for
current, voltage, and temperature monitors, sample sequencing setup and post processing configuration,
and DAC output.
The MSS configurator creates a bridge between the FPGA and embedded designers so device
configuration can be easily shared between multiple developers.
Figure 3- 1 • Three Design Roles
FPGA Design Embedded Design
MSS Configurator
MSS Configuration – Analog Configuration
Hardware Interfaces
FlashPro4, ULINK, J-LINK
Design Entry, IP Library
Simulation, Synthesis
Compile, Layout
Timing, Power Analysis
Hardware Debug
Drivers, Sample Projects
Application Development
Build Project
Simulation
Software Debug
SmartFusion Development Tools
3-2 Revision 6
The MSS configurator includes the following:
• A simple configurator for the embedded designer to control the MSS peripherals and I/Os
• A method to import and view a hardware configuration from the FPGA flow into the embedded
flow containing the memory map
• Automatic generation of drivers for any peripherals or soft IP used in the system configuration
• Comprehensive analog configuration for the programmable analog components
• Creation of a standard MSS block to be used in SmartDesign for connection of FPGA fabric
designs and IP
SmartFusion Ecosystem
The SoC Products Group has a long history of supplying comprehensive FPGA development tools and
recognizes the benefit of partnering with industry leaders to deliver the optimum usability and productivity
to users. Taking the same approach to processor development, The SoC Products Group has partnered
with key industry leaders in the microcontroller space to provide a robust solution that can be easily
adopted by existing embedded developers and has an easy learning path for FPGA designers. The SoC
Products Group is partnering with Keil and IAR to provide software IDE support to SmartFusion
Designers. In addition, Micrium provides support for SmartFusion with its new µC/OS-III,™ TCP/IP,™
and µC/Probe™ products (Table 3-1 on page 3-3).
Support for the SoC Products Group device and ecosystem resources is represented in Figure 3-2.
Starting from the base up, the ARM® Cortex™ Microcontroller Software Interface Standard (CMSIS)
hardware abstraction layer (HAL) is built on top of the SmartFusion hardware platform. Each of the
peripherals has its own driver, whether it is hard IP or soft IP added in the FPGA fabric. Then on top of
that we will work with third party real-time operating system (RTOS) vendors for OS, protocol stacks, and
interfaces. A designer can add a custom application with all, some, or none of the layers below.
Figure 3- 2 • SmartFusion Ecosystem
12C Driver
SPI Driver
UART Driver
Ethernet Driver
Timer Driver
NVM Driver
Application Layer
Protocol Stacks, File Systems,
Interfaces
RTOS – Real-Time Operating System
Hardware Abstraction Layer
Target Hardware Platform
Customer Alogorithms/
Intellectual Property
Third Party
TCP, HTTP, SMTP
DHCP, LCD
Third Party µC/OSII
Actel or Third Party
For Hard IP or Soft IP
I
2
C, SPI, UART, NVM
RAM, 10/100, Timer
Actel CMSIS-based
Actel SmartFusion
Application Code
HAL
Physical Layer
Middleware
RTOS
Drivers
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 3-3
Software Integrated Design Environment (IDE) Choices
Operating System and Middleware Support
Micrium is recognized as a leader in embedded software components. The company's flagship µC/OS
family is recognized for a variety of features and benefits, including unparalleled reliability, performance,
dependability, impeccable source code, and vast documentation, available from www.micrium.com
Software IDE SoftConsole Vision IDE Embedded Workbench
Website www.actel.com www.keil.com www.iar.com
Free versions from SoC
Products Group Free with Libero IDE 32 K code limited 32 K code limited
Available from Vendor N/A Full version Full version
Compiler GNU GCC RealView C/C++ IAR ARM Compiler
Debugger GDB debug Vision Debugger C-SPY Debugger
Instruction Set Simulator No Vision Simulator Yes
Debug Hardware FlashPro4 ULINK2 or ULINK-ME J-LINK or J-LINK Lite
Table 3-1 • Micrium Embedded Software Components
µC/OS-III,™ Micrium's newest RTOS,
is designed to save time on your next
embedded project and puts greater
control of the software in your hands,
yet maintains Micrium's ease-of-use,
ease-of-integration, short learning
curve, unsurpassed documentation,
and clean code.
µC/TCP-IP™ is a compact, reliable,
and high-performance stack built from
the ground up by Micrium and has the
quality, scalability, and reliability that
translates into a rapid configuration of
network options, remarkable ease-of-
use, and rapid time-to-market.
µC/Probe™ is one of the most useful
tools in embedded systems design
and puts you in the driver's seat,
allowing you to take charge of
virtually any variable, memory
location, and I/O port in your
embedded product, while your
system is running—there's no need to
stop.
Revision 6 4-5
4 – SmartFusion Programming
SmartFusion devices have three separate flash areas that can be programmed:
1. The FPGA fabric
2. The embedded nonvolatile memories (eNVMs)
3. The embedded flash ROM (eFROM)
There are essentially three methodologies for programming these areas:
1. In-system programming (ISP)
2. In-application programming (IAP)—only the FPGA Fabric and the eNVM
3. Pre-programming (non-ISP)
Programming, whether ISP or IAP methodologies are employed, can be done in two ways:
1. Securely using the on chip AES decryption logic
2. In plain text
In-System Programming
In-System Programming is performed with the aid of external JTAG programming hardware. Table 4-1
describes the JTAG programming hardware that will program a SmartFusion device and Table 4-2
defines the JTAG pins that provide the interface for the programming hardware.
Table 4-1 • Supported JTAG Programming Hardware
Dongle Source JTAG SWD1SWV2Program
FPGA Program
eFROM Program
eNVM
FlashPro3/4 SoC
Products
Group
Yes No No Yes Yes Yes
ULINK Pro Keil Yes Yes Yes Yes3Ye s 3Yes
ULINK2 Keil Yes Yes Yes Yes3Yes3Yes
IAR J-Link IAR Yes Yes Yes Yes3Yes3Yes
Notes:
1. SWD = ARM Serial Wire Debug
2. SWV = ARM Serial Wire Viewer
3. Planned support
Table 4-2 • SmartFusion JTAG Pin Descriptions
Pin Name Description
JTAGSEL ARM Cortex-M3 or FPGA test access port (TAP) controller selection
TRSTB Test reset bar
TCK Test clock
TMS Test mode select
TDI Test data input
TDO Test data output
SmartFusion Programming
4-6 Revision 6
The JTAGSEL pin selects the FPGA TAP controller or the Cortex-M3 debug logic. When JTAG SEL is
asserted, the FPGA TAP controller is selected and the TRSTB input into the Cortex-M3 is held in a reset
state (logic 0), as depicted in Figure 4-1. Users should tie the JTAGSEL pin high externally.
Note: Standard ARM JTAG connectors do not have access to the JTAGSEL pin. SoC Product Group’s
free Eclipse-based IDE, SoftConsole, automatically selects the appropriate TAP controller using
the CTXSELECT JTAG command. When using SoftConsole, the state of JTAGSEL is a "don't
care."
In-Application Programming
In-application programming refers to the ability to reprogram the various flash areas under direct
supervision of the Cortex-M3.
Reprogramming the FPGA Fabric Using the Cortex-M3
In this mode, the Cortex-M3 is executing the programming algorithm on-chip. The IAP driver can be
incorporated into the design project and executed from eNVM or eSRAM. The SoC Products Group
provides working example projects for SoftConsole, IAR, and Keil development environments. These
can be downloaded via the SoC Products Group Firmware Catalog. The new bitstream to be
programmed into the FPGA can reside on the user’s printed circuit board (PCB) in a separate SPI flash
memory. Alternately, the user can modify the existing projects supplied by the SoC Products Group and,
via custom handshaking software, throttle the download of the new image and program the FPGA a
piece at a time in real time. A cost-effective and reliable approach would be to store the bitstream in an
external SPI flash. Another option is storing a redundant bitstream image in an external SPI flash and
loading the newest version into the FPGA only when receiving an IAP command. Since the FPGA I/Os
are tristated or held at predefined or last known state during FPGA programming, the user must use MSS
I/Os to interface to external memories. Since there are two SPI controllers in the MSS, the user can
dedicate one to an SPI flash and the other to the particulars of an application. The amount of flash
memory required to program the FPGA always exceeds the size of the eNVM block that is on-chip. The
external memory controller (EMC) cannot be used as an interface to a memory device for storage of a
bitstream because its I/O pads are FPGA I/Os; hence they are tristated when the FPGA is in a
programming state.
Figure 4- 1 • TRSTB Logic
JTAG_SEL
TRSTB
Cortex-M3
TAP
Controller
FPGA
Programming Control
FPGA TAP
Controller
TRSTB
VJTAG (1.5 V to 3.3. V nominal)
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 4-7
Re-Programming the eNVM Blocks Using the Cortex-M3
In this mode the Cortex-M3 is executing the eNVM programming algorithm from eSRAM. Since individual
pages (132 bytes) of the eNVM can be write-protected, the programming algorithm software can be
protected from inadvertent erasure. When reprogramming the eNVM, both MSS I/Os and FPGA I/Os are
available as interfaces for sourcing the new eNVM image. The SoC Products Group provides working
example projects for SoftConsole, IAR, and Keil development environments. These can be downloaded
via the SoC Products Group Firmware Catalog.
Alternately, the eNVM can be reprogrammed by the Cortex-M3 via the IAP driver. This is necessary when
using an encrypted image.
Secure Programming
For background, refer to the Security in Low Power Flash Devices application note on the SoC Products
Group website. SmartFusion Secure ISP behaves identically to Fusion Secure ISP. Secure IAP of
SmartFusion devices is accomplished by using the IAP driver. Only the FPGA fabric and the eNVM can
be reprogrammed securely by using the IAP driver.
Typical Programming and Erase Times
Table 4-3 documents the typical programming and erase times for two components of SmartFusion
devices, FPGA fabric and eNVM, using the SoC Products Group’s FlashPro hardware and software.
These times will be different for other ISP and IAP methods. The Program action in FlashPro software
includes erase, program, and verify to complete.
The typical programming (including erase) time per page of the eNVM is 8 ms.
References
User’s Guides
DirectC User’s Guide
http://www.actel.com/documents/DirectC_UG.pdf
Fusion FGPA Fabric User’s Guide
http://www.actel.com/documents/Fusion_UG.pdf
Chapters:
"In-System Programming (ISP) of Actel’s Low-Power Flash Devices Using FlashPro4/3/3X"
"Security in Low Power Flash Devices"
"Programming Flash Devices"
"Microprocessor Programming of Actel’s Low-Power Flash Devices"
Table 4-3 • Typical Programming and Erase Times
FPGA Fabric (seconds) eNVM (seconds)
A2F200 A2F500 A2F200 A2F500
Erase 21 21 N/A N/A
Program 8 15 18 26
Verify 9 16 26 42
Revision 6 5-1
SmartFusion Intelligent Mixed Signal FPGAs
5 – Pin Descriptions
Supply Pins
Name Type Description
GND Ground Digital ground to the FPGA fabric, microcontroller subsystem and GPIOs
GND15ADC0 Ground Quiet analog ground to the 1.5 V circuitry of the first analog-to-digital converter (ADC)
GND15ADC1 Ground Quiet analog ground to the 1.5 V circuitry of the second ADC
GND15ADC2 Ground Quite analog ground to the 1.5 V circuitry of the third ADC
GND33ADC0 Ground Quiet analog ground to the 3.3 V circuitry of the first ADC
GND33ADC1 Ground Quiet analog ground to the 3.3 V circuitry of the second ADC
GND33ADC2 Ground Quiet analog ground to the 3.3 V circuitry of the third ADC
GNDA Ground Quiet analog ground to the analog front-end
GNDAQ Ground Quiet analog ground to the analog I/O of SmartFusion devices
GNDENVM Ground Digital ground to the embedded nonvolatile memory (eNVM)
GNDLPXTAL Ground Analog ground to the low power 32 KHz crystal oscillator circuitry
GNDMAINXTAL Ground Analog ground to the main crystal oscillator circuitry
GNDQ Ground Quiet digital ground supply voltage to input buffers of I/O banks. Within the package, the
GNDQ plane is decoupled from the simultaneous switching noise originated from the
output buffer ground domain. This minimizes the noise transfer within the package and
improves input signal integrity. GNDQ needs to always be connected on the board to
GND.
GNDRCOSC Ground Analog ground to the integrated RC oscillator circuit
GNDSDD0 Ground Analog ground to the first sigma-delta DAC
GNDSDD1 Ground Common analog ground to the second and third sigma-delta DACs
GNDTM0 Ground Analog temperature monitor common ground for signal conditioning blocks SCB 0 and
SCB 1 (see information for pins "TM0" and "TM1" in the "Analog Front-End (AFE)"
section on page 5-12).
GNDTM1 Ground Analog temperature monitor common ground for signal conditioning block SCB 2 and
SBCB 3 (see information for pins "TM2" and "TM3" in the "Analog Front-End (AFE)"
section on page 5-12).
GNDTM2 Ground Analog temperature monitor common ground for signal conditioning block SCB4
GNDVAREF Ground Analog ground reference used by the ADC. This pad should be connected to a quiet
analog ground.
VCC Supply Digital supply to the FPGA fabric and MSS, nominally 1.5 V. VCC is also required for
powering the JTAG state machine, in addition to VJTAG
. Even when a SmartFusion
device is in bypass mode in a JTAG chain of interconnected devices, both VCC and
VJTAG must remain powered to allow JTAG signals to pass through the SmartFusion
device.
Notes:
1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,
VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.
2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,
VCC15A, and VCC15ADCx.
Pin Descriptions
5-2 Revision 6
VCC15A Supply Clean analog 1.5 V supply to the analog circuitry
VCC15ADC0 Supply Analog 1.5 V supply to the first ADC
VCC15ADC1 Supply Analog 1.5 V supply to the second ADC
VCC15ADC2 Supply Analog 1.5 V supply to the third ADC
VCC33A Supply Clean 3.3 V analog supply to the analog circuitry. VCC33A is also used to feed the
1.5 V voltage regulator for designs that do not provide an external supply to VCC. Refer
to the Voltage Regulator (VR), Power Supply Monitor (PSM), and Power Modes section
in the SmartFusion Microcontroller Subsystem User’s Guide for more information.
VCC33ADC0 Supply Analog 3.3 V supply to the first ADC.
VCC33ADC1 Supply Analog 3.3 V supply to the second ADC
VCC33ADC2 Supply Analog 3.3 V supply to the third ADC
VCC33AP Supply Analog clean 3.3 V supply to the charge pump. To avoid high current draw, VCC33AP
should be powered up simultaneously with or after VCC33A.
VCC33N Supply –3.3 V output from the voltage converter. A 2.2 µF capacitor must be connected from
this pin to GND. Analog charge pump capacitors are not needed if none of the analog
SCB features are used and none of the SDDs are used. In that case it should be left
unconnected.
VCC33SDD0 Supply Analog 3.3 V supply to the first sigma-delta DAC
VCC33SDD1 Supply Common analog 3.3 V supply to the second and third sigma-delta DACs
VCCENVM Supply Digital 1.5 V power supply to the embedded nonvolatile memory blocks. To avoid high
current draw, VCC should be powered up before or simultaneously with VCCENVM.
VCCESRAM Supply Digital 1.5 V power supply to the embedded SRAM blocks. Available only on the
208PQFP package. It should be connected to VCC (in other packages, it is internally
connected to VCC).
VCCFPGAIOB0 Supply Digital supply to the FPGA fabric I/O bank 0 (north FPGA I/O bank) for the output
buffers and I/O logic.
Each bank can have a separate VCCFPGAIO connection. All I/Os in a bank will run off
the same VCCFPGAIO supply. VCCFPGAIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V,
nominal voltage. Unused I/O banks should have their corresponding VCCFPGAIO pins
tied to GND.
VCCFPGAIOB1 Supply Digital supply to the FPGA fabric I/O bank 1 (east FPGA I/O bank) for the output buffers
and I/O logic.
VCCFPGAIOB5 Supply Digital supply to the FPGA fabric I/O bank 5 (west FPGA I/O bank) for the output buffers
and I/O logic.
Each bank can have a separate VCCFPGAIO connection. All I/Os in a bank will run off
the same VCCFPGAIO supply. VCCFPGAIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V,
nominal voltage. Unused I/O banks should have their corresponding VCCFPGAIO pins
tied to GND.
Each bank can have a separate VCCFPGAIO connection. All I/Os in a bank will run off
the same VCCFPGAIO supply. VCCFPGAIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V,
nominal voltage. Unused I/O banks should have their corresponding VCCFPGAIO pins
tied to GND.
VCCLPXTAL Supply Analog supply to the low power 32 KHz crystal oscillator
Name Type Description
Notes:
1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,
VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.
2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,
VCC15A, and VCC15ADCx.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-3
VCCMAINXTAL Supply Analog supply to the main crystal oscillator circuit
VCCMSSIOB2 Supply Supply voltage to the microcontroller subsystem I/O bank 2 (east MSS I/O bank) for the
output buffers and I/O logic
VCCMSSIOB4 Supply Supply voltage to the microcontroller subsystem I/O bank 4 (west MSS I/O bank) for the
output buffers and I/O logic.
Each bank can have a separate VCCMSSIO connection. All I/Os in a bank will run off
the same VCCMSSIO supply. VCCMSSIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal
voltage. Unused I/O banks should have their corresponding VCCMSSIO pins tied to
GND.
Each bank can have a separate VCCMSSIO connection. All I/Os in a bank will run off
the same VCCMSSIO supply. VCCMSSIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal
voltage. Unused I/O banks should have their corresponding VCCMSSIO pins tied to
GND.
VCCPLLx Supply Analog 1.5 V supply to the PLL
VCCRCOSC Supply Analog supply to the integrated RC oscillator circuit
VCOMPLAx Supply Analog ground for the PLL
VDDBAT Supply External battery connection to the low power 32 KHz crystal oscillator (along with
VCCLPXTAL), RTC, and battery switchover circuit
VJTAG Supply Digital supply to the JTAG controller
SmartFusion devices have a separate bank for the dedicated JTAG pins. The JTAG
pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power
supply in a separate I/O bank gives greater flexibility in supply selection and simplifies
power supply and PCB design. If the JTAG interface is neither used nor planned to be
used, the VJTAG pin together with the TRSTB pin could be tied to GND. Note that VCC
is required to be powered for JTAG operation; VJTAG alone is insufficient. If a
SmartFusion device is in a JTAG chain of interconnected boards and it is desired to
power down the board containing the device, this can be done provided both VJTAG
and VCC to the device remain powered; otherwise, JTAG signals will not be able to
transition the device, even in bypass mode. See "JTAG Pins" section on page 5-8.
VPP Supply Digital programming circuitry supply
SmartFusion devices support single-voltage in-system programming (ISP) of the
configuration flash, embedded FlashROM (eFROM), and embedded nonvolatile
memory (eNVM).
For programming, VPP should be in the 3.3 V ± 5% range. During normal device
operation, VPP can be left floating or can be tied to any voltage between 0 V and 3.6 V.
When the VPP pin is tied to ground, it shuts off the charge pump circuitry, resulting in no
sources of oscillation from the charge pump circuitry. For proper programming, 0.01 µF
and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPP
and GND, and positioned as close to the FPGA pins as possible.
Name Type Description
Notes:
1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,
VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.
2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,
VCC15A, and VCC15ADCx.
Pin Descriptions
5-4 Revision 6
User-Defined Supply Pins
Name Type Polarity/Bus
Size Description
VAREF0 Input 1 Analog reference voltage for first ADC
The SmartFusion device can be configured to generate a 2.56 V internal
reference that can be used by the ADC. While using the internal
reference, the reference voltage is output on the VAREFOUT pin for use
as a system reference. If a different reference voltage is required, it can
be supplied by an external source and applied to this pin. The valid range
of values that can be supplied to the ADC is 1.0 V to 3.3 V. When
VAREF0 is internally generated, a bypass capacitor must be connected
from this pin to ground. The value of the bypass capacitor should be
between 3.3 µF and 22 µF, which is based on the needs of the individual
designs. The choice of the capacitor value has an impact on the settling
time it takes the VAREF0 signal to reach the required specification of 2.56
V to initiate valid conversions by the ADC. If the lower capacitor value is
chosen, the settling time required for VAREF0 to achieve 2.56 V will be
shorter than when selecting the larger capacitor value. The above range
of capacitor values supports the accuracy specification of the ADC, which
is detailed in the datasheet. Designers choosing the smaller capacitor
value will not obtain as much margin in the accuracy as that achieved with
a larger capacitor value. See the Analog-to-Digital Converter (ADC)
section in the SmartFusion Progra mmable Analog User ’s Guide for more
information. The SoC Products Group recommends customers use 10 µF
as the value of the bypass capacitor. Designers choosing to use an
external VAREF0 need to ensure that a stable and clean VAREF0 source
is supplied to the VAREF0 pin before initiating conversions by the ADC.
To use the internal voltage reference, you must connect the VAREFOUT
pin to the appropriate ADC VAREFx input—either the VAREF0 or
VAREF1 pin—on the PCB.
VAREF1 Input 1 Analog reference voltage for second ADC
See "VAREF0" above for more information.
VAREF2 Input 1 Analog reference voltage for third ADC
See "VAREF0" above for more.
VAREFOUT Out 1 Internal 2.56 V voltage reference output. Can be used to provide the two
ADCs with a unique voltage reference externally by connecting
VAREFOUT to both VAREF0 and VAREF1. To use the internal voltage
reference, you must connect the VAREFOUT pin to the appropriate ADC
VAREFx input—either the VAREF0 or VAREF1 pin—on the PCB.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-5
User Pins
Name Type Polarity/Bus Size Description
GPIO_x In/out 32 Microcontroller Subsystem (MSS)
General Purpose I/O (GPIO).
The MSS GPIO pin functions as an input, output, tristate, or bidirectional
buffer with configurable interrupt generation and Schmitt trigger support.
Input and output signal levels are compatible with the I/O standard selected.
Unused GPIO pins are tristated and do not include pull-up or pull-down
resistors.
During power-up, the used GPIO pins are tristated with no pull-up or
pull-down resistors until Sys boot configures them.
Some of these pins are also multiplexed with integrated peripherals in the
MSS (SPI, I2C, and UART).
GPIOs can be routed to dedicated I/O buffers (MSSIOBUF) or in some
cases to the FPGA fabric interface through an IOMUX. This allows GPIO
pins to be multiplexed as either I/Os for the FPGA fabric, the ARM®
Cortex™-M3 or for given integrated MSS peripherals. The MSS peripherals
are not multiplexed with each other; they are multiplexed only with the GPIO
block. For more information, see the General Purpose I/O Block (GPIO)
section in the SmartFusion Microcontroller Subsystem User’s Guide.
IO In/out FPGA user I/O
The FPGA user I/O pin functions as an input, output, tristate or bidirectional
buffer. Input and output signal levels are compatible with the I/O standard
selected. Unused I/O pins are disabled by Libero IDE software and include a
weak pull-up resistor. During power-up, the used I/O pins are tristated with
no pull-up or pull-down resistors until I/O enable (there is a delay after
voltage stabilizes, and different I/O banks power up sequentially to avoid a
surge of ICCI).
Some of these pins are also multiplexed with integrated peripherals in the
MSS (Ethernet MAC and external memory controller).
During programming, I/Os become tristated and weakly pulled up to VCCI.
With the VCCI and VCC supplies continuously powered up, when the device
transitions from programming to operating mode, the I/Os are instantly
configured to the desired user configuration. For more information, see the
SmartFusion FPGA User I/Os section in the SmartFusion FPGA Fabric
User’s Guide.
The naming convention used for each FPGA user I/O is:
IOuxwByVz where:
u = I/O pair number in bank, starting at 00 from the northwest I/O bank and
incrementing clockwise.
x = P (positive) or N (negative) or S (single-ended) or R (regular, single-
ended).
w = D (differential pair) or P (pair) or S (single-ended) or R (regular, single-
ended).
y = Bank number starting at 0 from northwest I/O bank and incrementing
clockwise.
z = VREF mini bank number.
Pin Descriptions
5-6 Revision 6
Special Function Pins
Name Type Polarity/B us Size Description
NC No connect
This pin is not connected to circuitry within the device. These pins can
be driven to any voltage or can be left floating with no effect on the
operation of the device.
DC Do not connect.
This pin should not be connected to any signals on the PCB. These
pins should be left unconnected.
LPXIN In 1 Low power 32 KHz crystal oscillator.
Input from the 32 KHz oscillator. Pin for connecting a low power 32
KHz watch crystal. If not used, the LPXIN pin can be left floating. For
more information, see the PLLs, Clock Conditioning Circuitry, and On-
Chip Crystal Oscillators section in the SmartFusion Microcontroller
Subsystem User’s Guide.
LPXOUT In 1 Low power 32 KHz crystal oscillator.
Output to the 32 KHz oscillator. Pin for connecting a low power 32 KHz
watch crystal. If not used, the LPXOUT pin can be left floating. For
more information, see the PLLs, Clock Conditioning Circuitry, and On-
Chip Crystal Oscillators section in the SmartFusion Microcontroller
Subsystem User’s Guide.
MAINXIN In 1 Main crystal oscillator circuit.
Input to the crystal oscillator circuit. Pin for connecting an external
crystal, ceramic resonator, or RC network. When using an external
crystal or ceramic oscillator, external capacitors are also
recommended. Refer to documentation from the crystal oscillator
manufacturer for proper capacitor value.
If using an external RC network or clock input, MAINXIN should be
used and MAINXOUT left unconnected. For more information, see the
PLLs, Clock Conditioning Circuitry, and On-Chip Crystal Oscillators
section in the SmartFusion Microcontroller Subsystem User’s Guide.
MAINXOUT Out 1 Main crystal oscillator circuit.
Output from the crystal oscillator circuit. Pin for connecting external
crystal or ceramic resonator. When using an external crystal or ceramic
oscillator, external capacitors are also recommended. Refer to
documentation from the crystal oscillator manufacturer for proper
capacitor value.
If using external RC network or clock input, MAINXIN should be used
and MAINXOUT left unconnected. For more information, see the PLLs,
Clock Conditioning Circuitry, and On-Chip Crystal Oscillators section in
the SmartFusion Microcontroller Subsystem User’s Guide.
NCAP 1 Negative capacitor connection.
This is the negative terminal of the charge pump. A capacitor, with a
2.2 µF recommended value, is required to connect between PCAP and
NCAP. Analog charge pump capacitors are not needed if none of the
analog SCB features are used and none of the SDDs are used. In that
case it should be left unconnected.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-7
PCAP 1 Positive Capacitor connection.
This is the positive terminal of the charge pump. A capacitor, with a 2.2
µF recommended value, is required to connect between PCAP and
NCAP. If this pin is not used, it must be left unconnected/floating. In this
case, no capacitor is needed. Analog charge pump capacitors are not
needed if none of the analog SCB features are used, and none of the
SDDs are used.
PTBASE 1 Pass transistor base connection
This is the control signal of the voltage regulator. This pin should be
connected to the base of an external pass transistor used with the 1.5
V internal voltage regulator and can be floating if not used.
PTEM 1 Pass transistor emitter connection.
This is the feedback input of the voltage regulator.
This pin should be connected to the emitter of an external pass
transistor used with the 1.5 V internal voltage regulator and can be
floating if not used.
MSS_RESET_N In Low Reset signal for the microcontroller subsystem.
PU_N In Low Push-button is the connection for the external momentary switch used
to turn on the 1.5 V voltage regulator and can be floating if not used.
Name Type Polarity/B us Size Description
Pin Descriptions
5-8 Revision 6
JTAG Pins
SmartFusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at
any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to
operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the
SmartFusion part must be supplied to allow JTAG signals to transition the SmartFusion device. Isolating
the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and simplifies
power supply and PCB design. If the JTAG interface is neither used nor planned to be used, the VJTAG
pin together with the TRSTB pin could be tied to GND.
Name Type Polarity/
Bus Size Description
JTAGSEL In 1 JTAG controller selection
Depending on the state of the JTAGSEL pin, an external JTAG controller will either
see the FPGA fabric TAP/auxiliary TAP (High) or the Cortex-M3 JTAG debug
interface (Low).
The JTAGSEL pin should be connected to an external pull-up resistor such that the
default configuration selects the FPGA fabric TAP.
TCK In 1 Test clock
Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have
an internal pull-up/-down resistor. If JTAG is not used, it is recommended to tie off
TCK to GND or VJTAG through a resistor placed close to the FPGA pin. This prevents
JTAG operation in case TMS enters an undesired state.
Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements.
Refer to Table 5-1 on page 5-9 for more information.
TDI In 1 Test data
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal
weak pull-up resistor on the TDI pin.
TDO Out 1 Test data
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
TMS HIGH Test mode select
The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO,
TRST). There is an internal weak pull-up resistor on the TMS pin.
TRSTB HIGH Boundary scan reset pin
The TRST pin functions as an active low input to asynchronously initialize (or reset)
the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST
pin. If JTAG is not used, an external pull-down resistor could be included to ensure
the TAP is held in reset mode. The resistor values must be chosen from Table 5-1 on
page 5-9 and must satisfy the parallel resistance value requirement. The values in
Table 5-1 on page 5-9 correspond to the resistor recommended when a single device
is used. The values correspond to the equivalent parallel resistor when multiple
devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could allow entering an undesired
JTAG state. In such cases, it is recommended that you tie off TRST to GND through
a resistor placed close to the FPGA pin.
The TRSTB pin also resets the serial wire JTAG – debug port (SWJ-DP) circuitry
within the Cortex-M3.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-9
Table 5-1 • Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG Tie-Off Resistance1, 2
VJTAG at 3.3 V 200 Ω to 1 kΩ
VJTAG at 2.5 V 200 Ω to 1 kΩ
VJTAG at 1.8 V 500 Ω to 1 kΩ
VJTAG at 1.5 V 500 Ω to 1 kΩ
Notes:
1. The TCK pin can be pulled up/down.
2. The TRST pin can only be pulled down.
1. Equivalent parallel resistance if more than one device is on JTAG chain.
Pin Descriptions
5-10 Revision 6
Microcontroller Subsystem (MSS)
Name Type Polarity/
Bus Size Description
External Memory Controller
EMC_ABx Out 26 External memory controller address bus
Can also be used as an FPGA user I/O (see "IO" on page 5-5).
EMC_BYTENx Out LOW/2 External memory controller byte enable
Can also be used as an FPGA user I/O (see "IO" on page 5-5).
EMC_CLK Out Rise External memory controller clock
Can also be used as an FPGA user I/O (see "IO" on page 5-5).
EMC_CSx_N Out LOW/2 External memory controller chip selects
Can also be used as an FPGA User IO (see "IO" on page 5-5).
EMC_DBx In/out 16 External memory controller data bus
Can also be used as an FPGA user I/O (see "IO" on page 5-5).
EMC_OENx_N Out LOW/2 External memory controller output enables
Can also be used as an FPGA User IO (see "IO" on page 5-5).
EMC_RW_N Out Level External memory controller read/write. Read = High, write = Low.
Can also be used as an FPGA user I/O (see "IO" on page 5-5).
Inter-Integrated Circuit (I2C) Peripherals
I2C_0_SCL In/out 1 I2C bus serial clock output. First I2C.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
I2C_0_SDA In/out 1 I2C bus serial data input/output. First I2C.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
I2C_1_SCL In/out 1 I2C bus serial clock output. Second I2C.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
I2C_1_SDA In/out 1 I2C bus serial data input/output. Second I2C.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
Serial Peripheral Interface (SPI) Controllers
SPI_0_CLK Out 1 Clock. First SPI.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
SPI_0_DI In 1 Data input. First SPI.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
SPI_0_DO Out 1 Data output. First SPI.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
SPI_0_SS Out 1 Slave select (chip select). First SPI.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
SPI_1_CLK Out 1 Clock. Second SPI.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
SPI_1_DI In 1 Data input. Second SPI.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-11
SPI_1_DO Out 1 Data output. Second SPI.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
SPI_1_SS Out 1 Slave select (chip select). Second SPI.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
Universal Asynchronous Receiver/Transmitter (UART) Peripherals
UART_0_RXD In 1 Receive data. First UART.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
UART_0_TXD Out 1 Transmit data. First UART.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
UART_1_RXD In 1 Receive data. Second UART.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
UART_1_TXD Out 1 Transmit data. Second UART.
Can also be used as an MSS GPIO (see "GPIO_x" on page 5-5).
Ethernet MAC
MAC_CLK In Rise Receive clock. 50 MHz ± 50 ppm clock source received from RMII PHY.
MAC_CRSDV In High Carrier sense/receive data valid for RMII PHY
Can also be used as an FPGA User IO (see "IO" on page 5-5).
MAC_MDC Out Rise RMII management clock
Can also be used as an FPGA User IO (see "IO" on page 5-5).
MAC_MDIO In/Out 1 RMII management data input/output
Can also be used as an FPGA User IO (see "IO" on page 5-5).
MAC_RXDx In 2 Ethernet MAC receive data. Data recovered and decoded by PHY. The
RXD[0] signal is the least significant bit.
Can also be used as an FPGA User I/O (see "IO" on page 5-5).
MAC_RXER In HIGH Ethernet MAC receive error. If MACRX_ER is asserted during reception,
the frame is received and status of the frame is updated with
MACRX_ER.
Can also be used as an FPGA user I/O (see "IO" on page 5-5).
MAC_TXDx Out 2 Ethernet MAC transmit data. The TXD[0] signal is the least significant
bit.
Can also be used as an FPGA user I/O (see "IO" on page 5-5).
MAC_TXEN Out HIGH Ethernet MAC transmit enable. When asserted, indicates valid data for
the PHY on the TXD port.
Can also be used as an FPGA User I/O (see "IO" on page 5-5).
Name Type Polarity/
Bus Size Description
Pin Descriptions
5-12 Revision 6
Analog Front-End (AFE)
Name Type Description
Associated With
ADC/SDD SCB
ABPS0 In SCB 0 / active bipolar prescaler input 1.
See the Active Bipolar Prescaler (ABPS) section in the SmartFusion
Programmable Analog User’s Guide.
ADC0 SCB0
ABPS1 In SCB 0 / active bipolar prescaler Input 2 ADC0 SCB0
ABPS2 In SCB 1 / active bipolar prescaler Input 1 ADC0 SCB1
ABPS3 In SCB 1 / active bipolar prescaler Input 2 ADC0 SCB1
ABPS4 In SCB 2 / active bipolar prescaler Input 1 ADC1 SCB2
ABPS5 In SCB 2 / active bipolar prescaler Input 2 ADC1 SCB2
ABPS6 In SCB 3 / active bipolar prescaler Input 1 ADC1 SCB3
ABPS7 In SCB 3 / active bipolar prescaler input 2 ADC1 SCB3
ABPS8 In SCB 4 / active bipolar prescaler input 1 ADC2 SCB4
ABPS9 In SCB 4 / active bipolar prescaler input 2 ADC2 SCB4
ADC0 In ADC 0 direct input 0 / FPGA Input.
See the "Sigma-Delta Digital-to-Analog Converter (DAC)" section in
the SmartFusion Programmab l e An al o g U ser’s Guide.
ADC0 SCB0
ADC1 In ADC 0 direct input 1 / FPGA input ADC0 SCB0
ADC2 In ADC 0 direct input 2 / FPGA input ADC0 SCB1
ADC3 In ADC 0 direct input 3 / FPGA input ADC0 SCB1
ADC4 In ADC 1 direct input 0 / FPGA input ADC1 SCB2
ADC5 In ADC 1 direct input 1 / FPGA input ADC1 SCB2
ADC6 In ADC 1 direct input 2 / FPGA input ADC1 SCB3
ADC7 In ADC 1 direct input 3 / FPGA input ADC1 SCB3
ADC8 In ADC 2 direct input 0 / FPGA input ADC2 SCB4
ADC9 In ADC 2 direct input 1 / FPGA input ADC2 SCB4
ADC10 In ADC 2 direct input 2 / FPGA input ADC2 N/A
ADC11 In ADC 2 direct input 3 / FPGA input ADC2 N/A
CM0 In SCB 0 / high side of current monitor / comparator
Positive input. See the Current Monitor section in the SmartFusion
Programmable Analog User’s Guide.
ADC0 SCB0
CM1 In SCB 1 / high side of current monitor / comparator. Positive input. ADC0 SCB1
CM2 In SCB 2 / high side of current monitor / comparator. Positive input. ADC1 SCB2
CM3 In SCB 3 / high side of current monitor / comparator. Positive input. ADC1 SCB3
CM4 In SCB 4 / high side of current monitor / comparator. Positive input. ADC2 SCB4
Note: Unused analog inputs should be ground ed. This aids in shielding and prevents an undesired coupling pa th.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-13
TM0 In SCB 0 / low side of current monitor / comparator
Negative input / high side of temperature monitor. See the
Temperature Monitor section.
ADC0 SCB0
TM1 In SCB 1 / low side of current monitor / comparator. Negative input /
high side of temperature monitor.
ADC0 SCB1
TM2 In SCB 2 / low side of current monitor / comparator. Negative input /
high side of temperature monitor.
ADC1 SCB2
TM3 In SCB 3 low side of current monitor / comparator. Negative input / high
side of temperature monitor.
ADC1 SCB3
TM4 In SCB 4 low side of current monitor / comparator. Negative input / high
side of temperature monitor.
ADC2 SCB4
SDD0 Out Output of SDD0
See the Sigma-Delta Digital-to-Analog Converter (DAC) section in
the SmartFusion Programmab l e An al o g U ser’s Guide.
SDD0 N/A
SDD1 Out Output of SDD1 SDD1 N/A
SDD2 Out Output of SDD2 SDD2 N/A
Name Type Description
Associated With
ADC/SDD SCB
Note: Unused analog inputs should be ground ed. This aids in shielding and prevents an undesired coupling pa th.
Pin Descriptions
5-14 Revision 6
Analog Front-End Pin-Level Function Multiplexing
Table 5-2 describes the relationships between the various internal signals found in the analog front-end
(AFE) and how they are multiplexed onto the external package pins. Note that, in general, only one
function is available for those pads that have numerous functions listed. The exclusion to this rule is
when a comparator is used; the ADC can still convert either input side of the comparator.
Table 5-2 • Relationsh ips Between Signals in the An alog Front-End
Pin ADC
Channel Dir.-In
Option Prescaler Current
Mon. Temp.
Mon. Comp ar. LVTTL SDD MUX SDD
ABPS0 ADC0_CH1 ABPS0_IN
ABPS1 ADC0_CH2 ABPS1_IN
ABPS2 ADC0_CH5 ABPS2_IN
ABPS3 ADC0_CH6 ABPS3_IN
ABPS4 ADC1_CH1 ABPS4_IN
ABPS5 ADC1_CH2 ABPS5_IN
ABPS6 ADC1_CH5 ABPS6_IN
ABPS7 ADC1_CH6 ABPS7_IN
ABPS8 ADC2_CH1 ABPS8_IN
ABPS9 ADC2_CH2 ABPS9_IN
ADC0 ADC0_CH9 Yes CMP1_P LVTTL0_IN
ADC1 ADC0_CH10 Yes CMP1_N LVTTL1_IN SDDM0_OUT
ADC2 ADC0_CH11 Yes CMP3_P LVTTL2_IN
ADC3 ADC0_CH12 Yes CMP3_N LVTTL3_IN SDDM1_OUT
ADC4 ADC1_CH9 Yes CMP5_P LVTTL4_IN
ADC5 ADC1_CH10 Yes CMP5_N LVTTL5_IN SDDM2_OUT
ADC6 ADC1_CH11 Yes CMP7_P LVTTL6_IN
ADC7 ADC1_CH12 Yes CMP7_N LVTTL7_IN SDDM3_OUT
ADC8 ADC2_CH9 Yes CMP9_P LVTTL8_IN
ADC9 ADC2_CH10 Yes CMP9_N LVTTL9_IN SDDM4_OUT
ADC10 ADC2_CH11 Yes LVTTL10_IN
ADC11 ADC2_CH12 Yes LVTTL11_IN
CM0 ADC0_CH3 Yes CM0_H CMP0_P
CM1 ADC0_CH7 Yes CM1_H CMP2_P
CM2 ADC1_CH3 Yes CM2_H CMP4_P
CM3 ADC1_CH7 Yes CM3_H CMP6_P
CM4 ADC2_CH3 Yes CM4_H CMP8_P
SDD0 ADC0_CH15 SDD0_OUT
SDD1 ADC1_CH15 SDD1_OUT
Notes:
1. ABPSx_IN: Input to active bipolar prescaler channel x.
2. CMx_H/L: Current monitor channel x, high/low side.
3. TMx_IO: Temperature monitor channel x.
4. CMPx_P/N: Comparator channel x, positive/negative input.
5. LVTTLx_IN: LVTTL I/O channel x.
6. SDDMx_OUT: Output from sigma-delta DAC MUX channel x.
7. SDDx_OUT: Direct output from sigma-delta DAC channel x.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-15
SDD2 ADC2_CH15 SDD2_OUT
TM0 ADC0_CH4 Yes CM0_L TM0_IO CMP0_N
TM1 ADC0_CH8 Yes CM1_L TM1_IO CMP2_N
TM2 ADC1_CH4 Yes CM2_L TM2_IO CMP4_N
TM3 ADC1_CH8 Yes CM3_L TM3_IO CMP6_N
TM4 ADC2_CH4 Yes CM4_L TM4_IO CMP8_N
Table 5-2 • Relationsh ips Between Signals in the An alog Front-End
Pin ADC
Channel Dir.-In
Option Prescaler Current
Mon. Temp.
Mon. Comp ar. LVTTL SDD MUX SDD
Notes:
1. ABPSx_IN: Input to active bipolar prescaler channel x.
2. CMx_H/L: Current monitor channel x, high/low side.
3. TMx_IO: Temperature monitor channel x.
4. CMPx_P/N: Comparator channel x, positive/negative input.
5. LVTTLx_IN: LVTTL I/O channel x.
6. SDDMx_OUT: Output from sigma-delta DAC MUX channel x.
7. SDDx_OUT: Direct output from sigma-delta DAC channel x.
Pin Descriptions
5-16 Revision 6
Pin Assignment Tables
288-Pin CSP
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
Note: Bottom view
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
A1 Ball Pad Corner
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-17
Pin
Number
288-Pin CSP
A2F060 Function A2F200 Function
A1 VCCFPGAIOB0 VCCFPGAIOB0
A2 GNDQ GNDQ
A3 EMC_CLK/IO00NDB0V0 EMC_CLK/GAA0/IO00NDB0V0
A4 EMC_RW_N/IO00PDB0V0 EMC_RW_N/GAA1/IO00PDB0V0
A5 GND GND
A6 EMC_CS1_N/IO01PDB0V0 EMC_CS1_N/GAB1/IO01PDB0V0
A7 EMC_CS0_N/IO01NDB0V0 EMC_CS0_N/GAB0/IO01NDB0V0
A8 EMC_AB[0]/IO04NPB0V0 EMC_AB[0]/IO04NPB0V0
A9 VCCFPGAIOB0 VCCFPGAIOB0
A10 EMC_AB[4]/IO06NDB0V0 EMC_AB[4]/IO06NDB0V0
A11 EMC_AB[8]/IO08NPB0V0 EMC_AB[8]/IO08NPB0V0
A12 EMC_AB[14]/IO11NPB0V0 EMC_AB[14]/IO11NPB0V0
A13 GND GND
A14 EMC_AB[18]/IO13NDB0V0 EMC_AB[18]/IO13NDB0V0
A15 EMC_AB[24]/IO16NDB0V0 EMC_AB[24]/IO16NDB0V0
A16 EMC_AB[25]/IO16PDB0V0 EMC_AB[25]/IO16PDB0V0
A17 VCCFPGAIOB0 VCCFPGAIOB0
A18 EMC_AB[20]/IO14NDB0V0 EMC_AB[20]/IO14NDB0V0
A19 EMC_AB[21]/IO14PDB0V0 EMC_AB[21]/IO14PDB0V0
A20 GNDQ GNDQ
A21 GND GND
AA1 NC ABPS1
AA2 GNDAQ GNDAQ
AA3 GNDA GNDA
AA4 VCC33N VCC33N
AA5 SDD0 SDD0
AA6 NC ABPS0
AA7 NC GNDTM0
AA8 NC ABPS2
AA9 NC VAREF0
AA10 NC GND15ADC0
AA11 ADC6 ADC6
AA12 ABPS7 ABPS7
AA13 TM2 (ADC) TM2
AA14 NC ABPS4
AA15 NC SDD1
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
Pin Descriptions
5-18 Revision 6
AA16 GNDVAREF GNDVAREF
AA17 VAREFOUT VAREFOUT
AA18 PU_N PU_N
AA19 VCC33A VCC33A
AA20 PTEM PTEM
AA21 GND GND
B1 GND GND
B21 IO20NDB1V0 GBB2/IO20NDB1V0
C1 EMC_DB[15]/IO71PDB5V0 EMC_DB[15]/GAA2/IO71PDB5V0
C3 VCOMPLA VCOMPLA
C4 VCCPLL VCCPLL
C5 VCCFPGAIOB0 VCCFPGAIOB0
C6 EMC_AB[1]/IO04PPB0V0 EMC_AB[1]/IO04PPB0V0
C7 GND GND
C8 EMC_OEN0_N/IO03NDB0V0 EMC_OEN0_N/IO03NDB0V0
C9 EMC_AB[2]/IO05NDB0V0 EMC_AB[2]/IO05NDB0V0
C10 EMC_AB[5]/IO06PDB0V0 EMC_AB[5]/IO06PDB0V0
C11 VCCFPGAIOB0 VCCFPGAIOB0
C12 EMC_AB[9]/IO08PPB0V0 EMC_AB[9]/IO08PPB0V0
C13 EMC_AB[15]/IO11PPB0V0 EMC_AB[15]/IO11PPB0V0
C14 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO13PDB0V0
C15 GND GND
C16 EMC_AB[22]/IO15NDB0V0 EMC_AB[22]/IO15NDB0V0
C17 EMC_AB[23]/IO15PDB0V0 EMC_AB[23]/IO15PDB0V0
C18 NC NC
C19 NC NC
C21 IO20PDB1V0 GBA2/IO20PDB1V0
D1 EMC_DB[14]/IO71NDB5V0 EMC_DB[14]/GAB2/IO71NDB5V0
D3 VCCFPGAIOB5 VCCFPGAIOB5
D19 GND GND
D21 VCCFPGAIOB1 VCCFPGAIOB1
E1 EMC_DB[13]/IO70PDB5V0 EMC_DB[13]/GAC2/IO70PDB5V0
E3 EMC_DB[12]/IO70NDB5V0 EMC_DB[12]/IO70NDB5V0
E5 GNDQ GNDQ
E6 EMC_BYTEN[0]/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO02NDB0V0
E7 EMC_BYTEN[1]/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO02PDB0V0
Pin
Number
288-Pin CSP
A2F060 Function A2F200 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-19
E8 EMC_OEN1_N/IO03PDB0V0 EMC_OEN1_N/IO03PDB0V0
E9 EMC_AB[3]/IO05PDB0V0 EMC_AB[3]/IO05PDB0V0
E10 EMC_AB[10]/IO09NDB0V0 EMC_AB[10]/IO09NDB0V0
E11 EMC_AB[7]/IO07PDB0V0 EMC_AB[7]/IO07PDB0V0
E12 EMC_AB[13]/IO10PDB0V0 EMC_AB[13]/IO10PDB0V0
E13 EMC_AB[16]/IO12NDB0V0 EMC_AB[16]/IO12NDB0V0
E14 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO12PDB0V0
E15 GCB0/IO27NDB1V0 GCB0/IO27NDB1V0
E16 GCB1/IO27PDB1V0 GCB1/IO27PDB1V0
E17 GCB2/IO24PDB1V0 GCB2/IO24PDB1V0
E19 GCA0/IO28NDB1V0 GCA0/IO28NDB1V0
E21 IO28PDB1V0 GCA1/IO28PDB1V0
F1 VCCFPGAIOB5 VCCFPGAIOB5
F3 GFB2/IO68NDB5V0 GFB2/IO68NDB5V0
F5 GFA2/IO68PDB5V0 GFA2/IO68PDB5V0
F6 EMC_DB[11]/IO69PDB5V0 EMC_DB[11]/IO69PDB5V0
F7 GND GND
F8 NC GFC1/IO66PPB5V0
F9 VCCFPGAIOB0 VCCFPGAIOB0
F10 EMC_AB[11]/IO09PDB0V0 EMC_AB[11]/IO09PDB0V0
F11 EMC_AB[6]/IO07NDB0V0 EMC_AB[6]/IO07NDB0V0
F12 EMC_AB[12]/IO10NDB0V0 EMC_AB[12]/IO10NDB0V0
F13 GND GND
F14 GCC1/IO26PPB1V0 GCC1/IO26PPB1V0
F15 GNDQ GNDQ
F16 VCCFPGAIOB1 VCCFPGAIOB1
F17 IO24NDB1V0 IO24NDB1V0
F19 IO30PDB1V0 GDB1/IO30PDB1V0
F21 GDB0/IO30NDB1V0 GDB0/IO30NDB1V0
G1 IO67NDB5V0 IO67NDB5V0
G3 GFC2/IO67PDB5V0 GFC2/IO67PDB5V0
G5 NC GFB1/IO65PDB5V0
G6 EMC_DB[10]/IO69NDB5V0 EMC_DB[10]/IO69NDB5V0
G9 NC GFC0/IO66NPB5V0
G13 GCC0/IO26NPB1V0 GCC0/IO26NPB1V0
G16 NC GDA0/IO31NDB1V0
Pin
Number
288-Pin CSP
A2F060 Function A2F200 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
Pin Descriptions
5-20 Revision 6
G17 IO29PDB1V0 GDC1/IO29PDB1V0
G19 GDC0/IO29NDB1V0 GDC0/IO29NDB1V0
G21 GND GND
H1 EMC_DB[9]/IO63PPB5V0 EMC_DB[9]/GEC1/IO63PPB5V0
H3 GND GND
H5 NC GFB0/IO65NDB5V0
H6 EMC_DB[7]/IO62PDB5V0 EMC_DB[7]/GEB1/IO62PDB5V0
H8 GND GND
H9 VCC VCC
H10 GND GND
H11 VCC VCC
H12 GND GND
H13 VCC VCC
H14 GND GND
H16 NC GDA1/IO31PDB1V0
H17 NC GDC2/IO32PPB1V0
H19 VCCFPGAIOB1 VCCFPGAIOB1
H21 NC GDB2/IO33PDB1V0
J1 EMC_DB[4]/IO61NPB5V0 EMC_DB[4]/GEA0/IO61NPB5V0
J3 EMC_DB[8]/IO63NPB5V0 EMC_DB[8]/GEC0/IO63NPB5V0
J5 EMC_DB[1]/IO59PDB5V0 EMC_DB[1]/GEB2/IO59PDB5V0
J6 EMC_DB[6]/IO62NDB5V0 EMC_DB[6]/GEB0/IO62NDB5V0
J7 VCCFPGAIOB5 VCCFPGAIOB5
J8 VCC VCC
J9 GND GND
J10 VCC VCC
J11 GND GND
J12 VCC VCC
J13 GND GND
J14 VCC VCC
J15 VPP VPP
J16 NC IO32NPB1V0
J17 GNDQ GNDQ
J19 VCCMAINXTAL VCCMAINXTAL
J21 NC GDA2/IO33NDB1V0
K1 GND GND
Pin
Number
288-Pin CSP
A2F060 Function A2F200 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-21
K3 EMC_DB[5]/IO61PPB5V0 EMC_DB[5]/GEA1/IO61PPB5V0
K5 EMC_DB[0]/IO59NDB5V0 EMC_DB[0]/GEA2/IO59NDB5V0
K6 EMC_DB[3]/IO60PPB5V0 EMC_DB[3]/GEC2/IO60PPB5V0
K8 GND GND
K9 VCC VCC
K10 GND GND
K11 VCC VCC
K12 GND GND
K13 VCC VCC
K14 GND GND
K16 LPXOUT LPXOUT
K17 GNDLPXTAL GNDLPXTAL
K19 GNDMAINXTAL GNDMAINXTAL
K21 MAINXIN MAINXIN
L1 GNDRCOSC GNDRCOSC
L3 VCCFPGAIOB5 VCCFPGAIOB5
L5 EMC_DB[2]/IO60NPB5V0 EMC_DB[2]/IO60NPB5V0
L6 GNDQ GNDQ
L8 VCC VCC
L9 GND GND
L10 VCC VCC
L12 VCC VCC
L13 GND GND
L14 VCC VCC
L16 VCCLPXTAL VCCLPXTAL
L17 VDDBAT VDDBAT
L19 LPXIN LPXIN
L21 MAINXOUT MAINXOUT
M1 VCCRCOSC VCCRCOSC
M3 MSS_RESET_N MSS_RESET_N
M5 GPIO_5/IO42RSB4V0 GPIO_5/IO42RSB4V0
M6 GND GND
M8 GND GND
M9 VCC VCC
M10 GND GND
M11 VCC VCC
Pin
Number
288-Pin CSP
A2F060 Function A2F200 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
Pin Descriptions
5-22 Revision 6
M12 GND GND
M13 VCC VCC
M14 GND GND
M16 TMS TMS
M17 VJTAG VJTAG
M19 TDO TDO
M21 TRSTB TRSTB
N1 VCCMSSIOB4 VCCMSSIOB4
N3 GND GND
N5 GPIO_4/IO43RSB4V0 GPIO_4/IO43RSB4V0
N6 GPIO_8/IO39RSB4V0 GPIO_8/IO39RSB4V0
N7 GPIO_9/IO38RSB4V0 GPIO_9/IO38RSB4V0
N8 VCC VCC
N9 GND GND
N10 VCC VCC
N11 GND GND
N12 VCC VCC
N13 GND GND
N14 VCC VCC
N15 GND GND
N16 TCK TCK
N17 TDI TDI
N19 GNDENVM GNDENVM
N21 VCCENVM VCCENVM
P1 IO48RSB4V0 MAC_MDC/IO48RSB4V0
P3 GPIO_7/IO40RSB4V0 GPIO_7/IO40RSB4V0
P5 GPIO_6/IO41RSB4V0 GPIO_6/IO41RSB4V0
P6 VCCMSSIOB4 VCCMSSIOB4
P8 GND GND
P9 VCC VCC
P10 GND GND
P11 VCC VCC
P12 GND GND
P13 VCC VCC
P14 GND GND
P16 JTAGSEL JTAGSEL
Pin
Number
288-Pin CSP
A2F060 Function A2F200 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-23
P17 I2C_0_SCL/GPIO_23 I2C_0_SCL/GPIO_23
P19 VCCMSSIOB2 VCCMSSIOB2
P21 GND GND
R1 IO49RSB4V0 MAC_MDIO/IO49RSB4V0
R3 IO52RSB4V0 MAC_TXEN/IO52RSB4V0
R5 IO56RSB4V0 MAC_TXD[0]/IO56RSB4V0
R6 IO51RSB4V0 MAC_CRSDV/IO51RSB4V0
R9 GNDA GNDA
R13 GNDA GNDA
R16 UART_1_RXD/GPIO_29 UART_1_RXD/GPIO_29
R17 UART_1_TXD/GPIO_28 UART_1_TXD/GPIO_28
R19 I2C_0_SDA/GPIO_22 I2C_0_SDA/GPIO_22
R21 I2C_1_SDA/GPIO_30 I2C_1_SDA/GPIO_30
T1 GND GND
T3 NC MAC_TXD[1]/IO55RSB4V0
T5 NC MAC_RXD[1]/IO53RSB4V0
T6 IO50RSB4V0 MAC_RXER/IO50RSB4V0
T7 NC CM1
T8 NC ADC1
T9 NC GND33ADC0
T10 NC VCC15ADC0
T11 GND33ADC1 GND33ADC1
T12 VAREF1 VAREF1
T13 ADC4 ADC4
T14 TM3 TM3
T15 SPI_1_SS/GPIO_27 SPI_1_SS/GPIO_27
T16 VCCMSSIOB2 VCCMSSIOB2
T17 UART_0_RXD/GPIO_21 UART_0_RXD/GPIO_21
T19 UART_0_TXD/GPIO_20 UART_0_TXD/GPIO_20
T21 I2C_1_SCL/GPIO_31 I2C_1_SCL/GPIO_31
U1 NC MAC_RXD[0]/IO54RSB4V0
U3 VCCMSSIOB4 VCCMSSIOB4
U5 VCC33SDD0 VCC33SDD0
U6 VCC15A VCC15A
U7 NC ABPS3
U8 NC ADC2
Pin
Number
288-Pin CSP
A2F060 Function A2F200 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
Pin Descriptions
5-24 Revision 6
U9 NC VCC33ADC0
U10 GND15ADC1 GND15ADC1
U11 VCC33ADC1 VCC33ADC1
U12 ADC7 ADC7
U13 ABPS6 ABPS6
U14 GNDTM1 GNDTM1
U15 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26
U16 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18
U17 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19
U19 GND GND
U21 SPI_1_DO/GPIO_24 SPI_1_DO/GPIO_24
V1 NC MAC_CLK
V3 GNDSDD0 GNDSDD0
V19 SPI_1_DI/GPIO_25 SPI_1_DI/GPIO_25
V21 VCCMSSIOB2 VCCMSSIOB2
W1 PCAP PCAP
W3 NCAP NCAP
W4 NC CM0
W5 NC TM0
W6 NC TM1
W7 NC ADC0
W8 NC ADC3
W9 NC GND33ADC0
W10 VCC15ADC1 VCC15ADC1
W11 GND33ADC1 GND33ADC1
W12 ADC5 ADC5
W13 CM3 CM3
W14 CM2 (ADC) CM2
W15 NC ABPS5
W16 GNDAQ GNDAQ
W17 NC VCC33SDD1
W18 NC GNDSDD1
W19 PTBASE PTBASE
W21 SPI_0_DI/GPIO_17 SPI_0_DI/GPIO_17
Y1 VCC33AP VCC33AP
Y21 SPI_0_DO/GPIO_16 SPI_0_DO/GPIO_16
Pin
Number
288-Pin CSP
A2F060 Function A2F200 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-25
Pin Number
288-Pin CSP
A2F200 Function A2F500 Function
A1 VCCFPGAIOB0 VCCFPGAIOB0
A2 GNDQ GNDQ
A3 EMC_CLK/GAA0/IO00NDB0V0 EMC_CLK/GAA0/IO02NDB0V0
A4 EMC_RW_N/GAA1/IO00PDB0V0 EMC_RW_N/GAA1/IO02PDB0V0
A5 GND GND
A6 EMC_CS1_N/GAB1/IO01PDB0V0 EMC_CS1_N/GAB1/IO05PDB0V0
A7 EMC_CS0_N/GAB0/IO01NDB0V0 EMC_CS0_N/GAB0/IO05NDB0V0
A8 EMC_AB[0]/IO04NPB0V0 EMC_AB[0]/IO06NPB0V0
A9 VCCFPGAIOB0 VCCFPGAIOB0
A10 EMC_AB[4]/IO06NDB0V0 EMC_AB[4]/IO10NDB0V0
A11 EMC_AB[8]/IO08NPB0V0 EMC_AB[8]/IO13NPB0V0
A12 EMC_AB[14]/IO11NPB0V0 EMC_AB[14]/IO15NPB0V0
A13 GND GND
A14 EMC_AB[18]/IO13NDB0V0 EMC_AB[18]/IO18NDB0V0
A15 EMC_AB[24]/IO16NDB0V0 EMC_AB[24]/IO20NDB0V0
A16 EMC_AB[25]/IO16PDB0V0 EMC_AB[25]/IO20PDB0V0
A17 VCCFPGAIOB0 VCCFPGAIOB0
A18 EMC_AB[20]/IO14NDB0V0 EMC_AB[20]/IO21NDB0V0
A19 EMC_AB[21]/IO14PDB0V0 EMC_AB[21]/IO21PDB0V0
A20 GNDQ GNDQ
A21 GND GND
AA1 ABPS1 ABPS1
AA2 GNDAQ GNDAQ
AA3 GNDA GNDA
AA4 VCC33N VCC33N
AA5 SDD0 SDD0
AA6 ABPS0 ABPS0
AA7 GNDTM0 GNDTM0
AA8 ABPS2 ABPS2
AA9 VAREF0 VAREF0
AA10 GND15ADC0 GND15ADC0
AA11 ADC6 ADC6
AA12 ABPS7 ABPS7
AA13 TM2 TM2
AA14 ABPS4 ABPS4
AA15 SDD1 SDD1
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
Pin Descriptions
5-26 Revision 6
AA16 GNDVAREF GNDVAREF
AA17 VAREFOUT VAREFOUT
AA18 PU_N PU_N
AA19 VCC33A VCC33A
AA20 PTEM PTEM
AA21 GND GND
B1 GND GND
B21 GBB2/IO20NDB1V0 GBB2/IO27NDB1V0
C1 EMC_DB[15]/GAA2/IO71PDB5V0 EMC_DB[15]/GAA2/IO88PDB5V0
C3 VCOMPLA VCOMPLA0
C4 VCCPLL VCCPLL0
C5 VCCFPGAIOB0 VCCFPGAIOB0
C6 EMC_AB[1]/IO04PPB0V0 EMC_AB[1]/IO06PPB0V0
C7 GND GND
C8 EMC_OEN0_N/IO03NDB0V0 EMC_OEN0_N/IO08NDB0V0
C9 EMC_AB[2]/IO05NDB0V0 EMC_AB[2]/IO09NDB0V0
C10 EMC_AB[5]/IO06PDB0V0 EMC_AB[5]/IO10PDB0V0
C11 VCCFPGAIOB0 VCCFPGAIOB0
C12 EMC_AB[9]/IO08PPB0V0 EMC_AB[9]/IO13PPB0V0
C13 EMC_AB[15]/IO11PPB0V0 EMC_AB[15]/IO15PPB0V0
C14 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO18PDB0V0
C15 GND GND
C16 EMC_AB[22]/IO15NDB0V0 EMC_AB[22]/IO19NDB0V0
C17 EMC_AB[23]/IO15PDB0V0 EMC_AB[23]/IO19PDB0V0
C18 NC VCCPLL1
C19 NC VCOMPLA1
C21 GBA2/IO20PDB1V0 GBA2/IO27PDB1V0
D1 EMC_DB[14]/GAB2/IO71NDB5V0 EMC_DB[14]/GAB2/IO88NDB5V0
D3 VCCFPGAIOB5 VCCFPGAIOB5
D19 GND GND
D21 VCCFPGAIOB1 VCCFPGAIOB1
E1 EMC_DB[13]/GAC2/IO70PDB5V0 EMC_DB[13]/GAC2/IO87PDB5V0
E3 EMC_DB[12]/IO70NDB5V0 EMC_DB[12]/IO87NDB5V0
E5 GNDQ GNDQ
E6 EMC_BYTEN[0]/GAC0/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO07NDB0V0
E7 EMC_BYTEN[1]/GAC1/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO07PDB0V0
Pin Number
288-Pin CSP
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-27
E8 EMC_OEN1_N/IO03PDB0V0 EMC_OEN1_N/IO08PDB0V0
E9 EMC_AB[3]/IO05PDB0V0 EMC_AB[3]/IO09PDB0V0
E10 EMC_AB[10]/IO09NDB0V0 EMC_AB[10]/IO11NDB0V0
E11 EMC_AB[7]/IO07PDB0V0 EMC_AB[7]/IO12PDB0V0
E12 EMC_AB[13]/IO10PDB0V0 EMC_AB[13]/IO14PDB0V0
E13 EMC_AB[16]/IO12NDB0V0 EMC_AB[16]/IO17NDB0V0
E14 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO17PDB0V0
E15 GCB0/IO27NDB1V0 GCB0/IO34NDB1V0
E16 GCB1/IO27PDB1V0 GCB1/IO34PDB1V0
E17 GCB2/IO24PDB1V0 GCB2/IO33PDB1V0
E19 GCA0/IO28NDB1V0 GCA0/IO36NDB1V0
E21 GCA1/IO28PDB1V0 GCA1/IO36PDB1V0
F1 VCCFPGAIOB5 VCCFPGAIOB5
F3 GFB2/IO68NDB5V0 GFB2/IO85NDB5V0
F5 GFA2/IO68PDB5V0 GFA2/IO85PDB5V0
F6 EMC_DB[11]/IO69PDB5V0 EMC_DB[11]/IO86PDB5V0
F7 GND GND
F8 GFC1/IO66PPB5V0 GFC1/IO83PPB5V0
F9 VCCFPGAIOB0 VCCFPGAIOB0
F10 EMC_AB[11]/IO09PDB0V0 EMC_AB[11]/IO11PDB0V0
F11 EMC_AB[6]/IO07NDB0V0 EMC_AB[6]/IO12NDB0V0
F12 EMC_AB[12]/IO10NDB0V0 EMC_AB[12]/IO14NDB0V0
F13 GND GND
F14 GCC1/IO26PPB1V0 GCC1/IO35PPB1V0
F15 GNDQ GNDQ
F16 VCCFPGAIOB1 VCCFPGAIOB1
F17 IO24NDB1V0 IO33NDB1V0
F19 GDB1/IO30PDB1V0 GDB1/IO39PDB1V0
F21 GDB0/IO30NDB1V0 GDB0/IO39NDB1V0
G1 IO67NDB5V0 IO84NDB5V0
G3 GFC2/IO67PDB5V0 GFC2/IO84PDB5V0
G5 GFB1/IO65PDB5V0 GFB1/IO82PDB5V0
G6 EMC_DB[10]/IO69NDB5V0 EMC_DB[10]/IO86NDB5V0
G9 GFC0/IO66NPB5V0 GFC0/IO83NPB5V0
G13 GCC0/IO26NPB1V0 GCC0/IO35NPB1V0
G16 GDA0/IO31NDB1V0 GDA0/IO40NDB1V0
Pin Number
288-Pin CSP
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
Pin Descriptions
5-28 Revision 6
G17 GDC1/IO29PDB1V0 GDC1/IO38PDB1V0
G19 GDC0/IO29NDB1V0 GDC0/IO38NDB1V0
G21 GND GND
H1 EMC_DB[9]/GEC1/IO63PPB5V0 EMC_DB[9]/GEC1/IO80PPB5V0
H3 GND GND
H5 GFB0/IO65NDB5V0 GFB0/IO82NDB5V0
H6 EMC_DB[7]/GEB1/IO62PDB5V0 EMC_DB[7]/GEB1/IO79PDB5V0
H8 GND GND
H9 VCC VCC
H10 GND GND
H11 VCC VCC
H12 GND GND
H13 VCC VCC
H14 GND GND
H16 GDA1/IO31PDB1V0 GDA1/IO40PDB1V0
H17 GDC2/IO32PPB1V0 GDC2/IO41PPB1V0
H19 VCCFPGAIOB1 VCCFPGAIOB1
H21 GDB2/IO33PDB1V0 GDB2/IO42PDB1V0
J1 EMC_DB[4]/GEA0/IO61NPB5V0 EMC_DB[4]/GEA0/IO78NPB5V0
J3 EMC_DB[8]/GEC0/IO63NPB5V0 EMC_DB[8]/GEC0/IO80NPB5V0
J5 EMC_DB[1]/GEB2/IO59PDB5V0 EMC_DB[1]/GEB2/IO76PDB5V0
J6 EMC_DB[6]/GEB0/IO62NDB5V0 EMC_DB[6]/GEB0/IO79NDB5V0
J7 VCCFPGAIOB5 VCCFPGAIOB5
J8 VCC VCC
J9 GND GND
J10 VCC VCC
J11 GND GND
J12 VCC VCC
J13 GND GND
J14 VCC VCC
J15 VPP VPP
J16 IO32NPB1V0 IO41NPB1V0
J17 GNDQ GNDQ
J19 VCCMAINXTAL VCCMAINXTAL
J21 GDA2/IO33NDB1V0 GDA2/IO42NDB1V0
K1 GND GND
Pin Number
288-Pin CSP
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-29
K3 EMC_DB[5]/GEA1/IO61PPB5V0 EMC_DB[5]/GEA1/IO78PPB5V0
K5 EMC_DB[0]/GEA2/IO59NDB5V0 EMC_DB[0]/GEA2/IO76NDB5V0
K6 EMC_DB[3]/GEC2/IO60PPB5V0 EMC_DB[3]/GEC2/IO77PPB5V0
K8 GND GND
K9 VCC VCC
K10 GND GND
K11 VCC VCC
K12 GND GND
K13 VCC VCC
K14 GND GND
K16 LPXOUT LPXOUT
K17 GNDLPXTAL GNDLPXTAL
K19 GNDMAINXTAL GNDMAINXTAL
K21 MAINXIN MAINXIN
L1 GNDRCOSC GNDRCOSC
L3 VCCFPGAIOB5 VCCFPGAIOB5
L5 EMC_DB[2]/IO60NPB5V0 EMC_DB[2]/IO77NPB5V0
L6 GNDQ GNDQ
L8 VCC VCC
L9 GND GND
L10 VCC VCC
L12 VCC VCC
L13 GND GND
L14 VCC VCC
L16 VCCLPXTAL VCCLPXTAL
L17 VDDBAT VDDBAT
L19 LPXIN LPXIN
L21 MAINXOUT MAINXOUT
M1 VCCRCOSC VCCRCOSC
M3 MSS_RESET_N MSS_RESET_N
M5 GPIO_5/IO42RSB4V0 GPIO_5/IO51RSB4V0
M6 GND GND
M8 GND GND
M9 VCC VCC
M10 GND GND
M11 VCC VCC
Pin Number
288-Pin CSP
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
Pin Descriptions
5-30 Revision 6
M12 GND GND
M13 VCC VCC
M14 GND GND
M16 TMS TMS
M17 VJTAG VJTAG
M19 TDO TDO
M21 TRSTB TRSTB
N1 VCCMSSIOB4 VCCMSSIOB4
N3 GND GND
N5 GPIO_4/IO43RSB4V0 GPIO_4/IO52RSB4V0
N6 GPIO_8/IO39RSB4V0 GPIO_8/IO48RSB4V0
N7 GPIO_9/IO38RSB4V0 GPIO_9/IO47RSB4V0
N8 VCC VCC
N9 GND GND
N10 VCC VCC
N11 GND GND
N12 VCC VCC
N13 GND GND
N14 VCC VCC
N15 GND GND
N16 TCK TCK
N17 TDI TDI
N19 GNDENVM GNDENVM
N21 VCCENVM VCCENVM
P1 MAC_MDC/IO48RSB4V0 MAC_MDC/IO57RSB4V0
P3 GPIO_7/IO40RSB4V0 GPIO_7/IO49RSB4V0
P5 GPIO_6/IO41RSB4V0 GPIO_6/IO50RSB4V0
P6 VCCMSSIOB4 VCCMSSIOB4
P8 GND GND
P9 VCC VCC
P10 GND GND
P11 VCC VCC
P12 GND GND
P13 VCC VCC
P14 GND GND
P16 JTAGSEL JTAGSEL
Pin Number
288-Pin CSP
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-31
P17 I2C_0_SCL/GPIO_23 I2C_0_SCL/GPIO_23
P19 VCCMSSIOB2 VCCMSSIOB2
P21 GND GND
R1 MAC_MDIO/IO49RSB4V0 MAC_MDIO/IO58RSB4V0
R3 MAC_TXEN/IO52RSB4V0 MAC_TXEN/IO61RSB4V0
R5 MAC_TXD[0]/IO56RSB4V0 MAC_TXD[0]/IO65RSB4V0
R6 MAC_CRSDV/IO51RSB4V0 MAC_CRSDV/IO60RSB4V0
R9 GNDA GNDA
R13 GNDA GNDA
R16 UART_1_RXD/GPIO_29 UART_1_RXD/GPIO_29
R17 UART_1_TXD/GPIO_28 UART_1_TXD/GPIO_28
R19 I2C_0_SDA/GPIO_22 I2C_0_SDA/GPIO_22
R21 I2C_1_SDA/GPIO_30 I2C_1_SDA/GPIO_30
T1 GND GND
T3 MAC_TXD[1]/IO55RSB4V0 MAC_TXD[1]/IO64RSB4V0
T5 MAC_RXD[1]/IO53RSB4V0 MAC_RXD[1]/IO62RSB4V0
T6 MAC_RXER/IO50RSB4V0 MAC_RXER/IO59RSB4V0
T7 CM1 CM1
T8 ADC1 ADC1
T9 GND33ADC0 GND33ADC0
T10 VCC15ADC0 VCC15ADC0
T11 GND33ADC1 GND33ADC1
T12 VAREF1 VAREF1
T13 ADC4 ADC4
T14 TM3 TM3
T15 SPI_1_SS/GPIO_27 SPI_1_SS/GPIO_27
T16 VCCMSSIOB2 VCCMSSIOB2
T17 UART_0_RXD/GPIO_21 UART_0_RXD/GPIO_21
T19 UART_0_TXD/GPIO_20 UART_0_TXD/GPIO_20
T21 I2C_1_SCL/GPIO_31 I2C_1_SCL/GPIO_31
U1 MAC_RXD[0]/IO54RSB4V0 MAC_RXD[0]/IO63RSB4V0
U3 VCCMSSIOB4 VCCMSSIOB4
U5 VCC33SDD0 VCC33SDD0
U6 VCC15A VCC15A
U7 ABPS3 ABPS3
U8 ADC2 ADC2
Pin Number
288-Pin CSP
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
Pin Descriptions
5-32 Revision 6
U9 VCC33ADC0 VCC33ADC0
U10 GND15ADC1 GND15ADC1
U11 VCC33ADC1 VCC33ADC1
U12 ADC7 ADC7
U13 ABPS6 ABPS6
U14 GNDTM1 GNDTM1
U15 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26
U16 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18
U17 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19
U19 GND GND
U21 SPI_1_DO/GPIO_24 SPI_1_DO/GPIO_24
V1 MAC_CLK MAC_CLK
V3 GNDSDD0 GNDSDD0
V19 SPI_1_DI/GPIO_25 SPI_1_DI/GPIO_25
V21 VCCMSSIOB2 VCCMSSIOB2
W1 PCAP PCAP
W3 NCAP NCAP
W4 CM0 CM0
W5 TM0 TM0
W6 TM1 TM1
W7 ADC0 ADC0
W8 ADC3 ADC3
W9 GND33ADC0 GND33ADC0
W10 VCC15ADC1 VCC15ADC1
W11 GND33ADC1 GND33ADC1
W12 ADC5 ADC5
W13 CM3 CM3
W14 CM2 CM2
W15 ABPS5 ABPS5
W16 GNDAQ GNDAQ
W17 VCC33SDD1 VCC33SDD1
W18 GNDSDD1 GNDSDD1
W19 PTBASE PTBASE
W21 SPI_0_DI/GPIO_17 SPI_0_DI/GPIO_17
Y1 VCC33AP VCC33AP
Y21 SPI_0_DO/GPIO_16 SPI_0_DO/GPIO_16
Pin Number
288-Pin CSP
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger density device.
Pin Descriptions
5-34 Revision 6
Pin Number
208-Pin PQFP
A2F200 A2F500
1VCCPLL VCCPLL0
2VCOMPLA VCOMPLA0
3 GNDQ GNDQ
4EMC_DB[15]/GAA2/IO71PDB5V0 EMC_DB[15]/GAA2/IO88PDB5V0
5EMC_DB[14]/GAB2/IO71NDB5V0 EMC_DB[14]/GAB2/IO88NDB5V0
6EMC_DB[13]/GAC2/IO70PDB5V0 EMC_DB[13]/GAC2/IO87PDB5V0
7EMC_DB[12]/IO70NDB5V0 EMC_DB[12]/IO87NDB5V0
8VCC VCC
9GND GND
10 VCCFPGAIOB5 VCCFPGAIOB5
11 EMC_DB[11]/IO69PDB5V0 EMC_DB[11]/IO86PDB5V0
12 EMC_DB[10]/IO69NDB5V0 EMC_DB[10]/IO86NDB5V0
13 GFA2/IO68PSB5V0 GFA2/IO85PSB5V0
14 GFA1/IO64PDB5V0 GFA1/IO81PDB5V0
15 GFA0/IO64NDB5V0 GFA0/IO81NDB5V0
16 EMC_DB[9]/GEC1/IO63PDB5V0 EMC_DB[9]/GEC1/IO80PDB5V0
17 EMC_DB[8]/GEC0/IO63NDB5V0 EMC_DB[8]/GEC0/IO80NDB5V0
18 EMC_DB[7]/GEB1/IO62PDB5V0 EMC_DB[7]/GEB1/IO79PDB5V0
19 EMC_DB[6]/GEB0/IO62NDB5V0 EMC_DB[6]/GEB0/IO79NDB5V0
20 EMC_DB[5]/GEA1/IO61PDB5V0 EMC_DB[5]/GEA1/IO78PDB5V0
21 EMC_DB[4]/GEA0/IO61NDB5V0 EMC_DB[4]/GEA0/IO78NDB5V0
22 VCC VCC
23 GND GND
24 VCCFPGAIOB5 VCCFPGAIOB5
25 EMC_DB[3]/GEC2/IO60PDB5V0 EMC_DB[3]/GEC2/IO77PDB5V0
26 EMC_DB[2]/IO60NDB5V0 EMC_DB[2]/IO77NDB5V0
27 EMC_DB[1]/GEB2/IO59PDB5V0 EMC_DB[1]/GEB2/IO76PDB5V0
28 EMC_DB[0]/GEA2/IO59NDB5V0 EMC_DB[0]/GEA2/IO76NDB5V0
29 VCC VCC
29 VCC VCC
30 GND GND
31 GNDRCOSC GNDRCOSC
32 VCCRCOSC VCCRCOSC
33 MSS_RESET_N MSS_RESET_N
34 VCCESRAM VCCESRAM
35 MAC_MDC/IO48RSB4V0 MAC_MDC/IO57RSB4V0
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-35
36 MAC_MDIO/IO49RSB4V0 MAC_MDIO/IO58RSB4V0
37 MAC_TXEN/IO52RSB4V0 MAC_TXEN/IO61RSB4V0
38 MAC_CRSDV/IO51RSB4V0 MAC_CRSDV/IO60RSB4V0
39 MAC_RXER/IO50RSB4V0 MAC_RXER/IO59RSB4V0
40 GND GND
41 VCCMSSIOB4 VCCMSSIOB4
42 VCC VCC
43 MAC_TXD[0]/IO56RSB4V0 MAC_TXD[0]/IO65RSB4V0
44 MAC_TXD[1]/IO55RSB4V0 MAC_TXD[1]/IO64RSB4V0
45 MAC_RXD[0]/IO54RSB4V0 MAC_RXD[0]/IO63RSB4V0
46 MAC_RXD[1]/IO53RSB4V0 MAC_RXD[1]/IO62RSB4V0
47 MAC_CLK MAC_CLK
48 GNDSDD0 GNDSDD0
49 VCC33SDD0 VCC33SDD0
50 VCC15A VCC15A
51 PCAP PCAP
52 NCAP NCAP
53 VCC33AP VCC33AP
54 VCC33N VCC33N
55 SDD0 SDD0
56 GNDA GNDA
57 GNDAQ GNDAQ
58 ABPS0 ABPS0
59 ABPS1 ABPS1
60 CM0 CM0
61 TM0 TM0
62 GNDTM0 GNDTM0
63 TM1 TM1
64 CM1 CM1
65 ABPS3 ABPS3
66 ABPS2 ABPS2
67 ADC0 ADC0
68 ADC1 ADC1
69 ADC2 ADC2
70 ADC3 ADC3
71 VAREF0 VAREF0
Pin Number
208-Pin PQFP
A2F200 A2F500
Pin Descriptions
5-36 Revision 6
72 GND33ADC0 GND33ADC0
73 VCC33ADC0 VCC33ADC0
74 GND33ADC0 GND33ADC0
75 VCC15ADC0 VCC15ADC0
76 GND15ADC0 GND15ADC0
77 GND15ADC1 GND15ADC1
78 VCC15ADC1 VCC15ADC1
79 GND33ADC1 GND33ADC1
80 VCC33ADC1 VCC33ADC1
81 GND33ADC1 GND33ADC1
82 VAREF1 VAREF1
83 ADC7 ADC7
84 ADC6 ADC6
85 ADC5 ADC5
86 ADC4 ADC4
87 ABPS6 ABPS6
88 ABPS7 ABPS7
89 CM3 CM3
90 TM3 TM3
91 GNDTM1 GNDTM1
92 TM2 TM2
93 CM2 CM2
94 ABPS5 ABPS5
95 ABPS4 ABPS4
96 GNDAQ GNDAQ
97 GNDA GNDA
98 NC NC
99 GNDVAREF GNDVAREF
100 VAREFOUT VAREFOUT
101 PU_N PU_N
102 VCC33A VCC33A
103 PTEM PTEM
104 PTBASE PTBASE
105 SPI_0_DO/GPIO_16 SPI_0_DO/GPIO_16
106 SPI_0_DI/GPIO_17 SPI_0_DI/GPIO_17
107 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18
Pin Number
208-Pin PQFP
A2F200 A2F500
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-37
108 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19
109 UART_0_RXD/GPIO_21 UART_0_RXD/GPIO_21
110 UART_0_TXD/GPIO_20 UART_0_TXD/GPIO_20
111 UART_1_RXD/GPIO_29 UART_1_RXD/GPIO_29
112 UART_1_TXD/GPIO_28 UART_1_TXD/GPIO_28
113 VCC VCC
114 VCCMSSIOB2 VCCMSSIOB2
115 GND GND
116 I2C_1_SDA/GPIO_30 I2C_1_SDA/GPIO_30
117 I2C_1_SCL/GPIO_31 I2C_1_SCL/GPIO_31
118 I2C_0_SDA/GPIO_22 I2C_0_SDA/GPIO_22
119 I2C_0_SCL/GPIO_23 I2C_0_SCL/GPIO_23
120 GNDENVM GNDENVM
121 VCCENVM VCCENVM
122 JTAGSEL JTAGSEL
123 TCK TCK
124 TDI TDI
125 TMS TMS
126 TDO TDO
127 TRSTB TRSTB
128 VJTAG VJTAG
129 VDDBAT VDDBAT
130 VCCLPXTAL VCCLPXTAL
131 LPXOUT LPXOUT
132 LPXIN LPXIN
133 GNDLPXTAL GNDLPXTAL
134 GNDMAINXTAL GNDMAINXTAL
135 MAINXOUT MAINXOUT
136 MAINXIN MAINXIN
137 VCCMAINXTAL VCCMAINXTAL
138 GND GND
139 VCC VCC
139 VCC VCC
140 VPP VPP
141 VCCFPGAIOB1 VCCFPGAIOB1
142 GDA0/IO31NDB1V0 GDA0/IO40NDB1V0
Pin Number
208-Pin PQFP
A2F200 A2F500
Pin Descriptions
5-38 Revision 6
143 GDA1/IO31PDB1V0 GDA1/IO40PDB1V0
144 GDC0/IO29NSB1V0 GDC0/IO38NSB1V0
145 GCA0/IO28NDB1V0 GCA0/IO36NDB1V0
146 GCA1/IO28PDB1V0 GCA1/IO36PDB1V0
147 VCCFPGAIOB1 VCCFPGAIOB1
148 GND GND
149 VCC VCC
150 IO25NDB1V0 IO30NDB1V0
151 GCC2/IO25PDB1V0 GBC2/IO30PDB1V0
152 IO23NDB1V0 IO28NDB1V0
153 GCA2/IO23PDB1V0 GCA2/IO28PDB1V0
154 GBC2/IO21PSB1V0 GBB2/IO27NDB1V0
155 GBA2/IO20PSB1V0 GBA2/IO27PDB1V0
156 GNDQ GNDQ
157 GNDQ GNDQ
158 VCCFPGAIOB0 VCCFPGAIOB0
159 GBA1/IO19PDB0V0 GBA1/IO23PDB0V0
160 GBA0/IO19NDB0V0 GBA0/IO23NDB0V0
161 VCCFPGAIOB0 VCCFPGAIOB0
162 GND GND
163 VCC VCC
164 EMC_AB[25]/IO16PDB0V0 EMC_AB[21]/IO21PDB0V0
165 EMC_AB[24]/IO16NDB0V0 EMC_AB[20]/IO21NDB0V0
166 EMC_AB[23]/IO15PDB0V0 EMC_AB[25]/IO20PDB0V0
167 EMC_AB[22]/IO15NDB0V0 EMC_AB[24]/IO20NDB0V0
168 EMC_AB[21]/IO14PDB0V0 EMC_AB[23]/IO19PDB0V0
169 EMC_AB[20]/IO14NDB0V0 EMC_AB[22]/IO19NDB0V0
170 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO18PDB0V0
171 EMC_AB[18]/IO13NDB0V0 EMC_AB[18]/IO18NDB0V0
172 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO17PDB0V0
173 EMC_AB[16]/IO12NDB0V0 EMC_AB[16]/IO17NDB0V0
174 VCCFPGAIOB0 VCCFPGAIOB0
175 GND GND
176 VCC VCC
177 EMC_AB[15]/IO11PDB0V0 EMC_AB[13]/IO14PDB0V0
178 EMC_AB[14]/IO11NDB0V0 EMC_AB[12]/IO14NDB0V0
Pin Number
208-Pin PQFP
A2F200 A2F500
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-39
179 EMC_AB[13]/IO10PDB0V0 EMC_AB[9]/IO13PDB0V0
180 EMC_AB[12]/IO10NDB0V0 EMC_AB[8]/IO13NDB0V0
181 EMC_AB[11]/IO09PDB0V0 EMC_AB[7]/IO12PDB0V0
182 EMC_AB[10]/IO09NDB0V0 EMC_AB[6]/IO12NDB0V0
183 EMC_AB[9]/IO08PDB0V0 EMC_AB[11]/IO11PDB0V0
184 EMC_AB[8]/IO08NDB0V0 EMC_AB[10]/IO11NDB0V0
185 EMC_AB[7]/IO07PDB0V0 EMC_AB[5]/IO10PDB0V0
186 EMC_AB[6]/IO07NDB0V0 EMC_AB[4]/IO10NDB0V0
187 VCCFPGAIOB0 VCCFPGAIOB0
188 GND GND
189 VCC VCC
190 EMC_AB[5]/IO06PDB0V0 EMC_OEN1_N/IO08PDB0V0
191 EMC_AB[4]/IO06NDB0V0 EMC_OEN0_N/IO08NDB0V0
192 EMC_AB[3]/IO05PDB0V0 EMC_BYTEN[1]/GAC1/IO07PDB0V0
193 EMC_AB[2]/IO05NDB0V0 EMC_BYTEN[0]/GAC0/IO07NDB0V0
194 EMC_AB[1]/IO04PDB0V0 IO04PDB0V0
195 EMC_AB[0]/IO04NDB0V0 IO04NDB0V0
196 EMC_OEN1_N/IO03PDB0V0 IO03PDB0V0
197 EMC_OEN0_N/IO03NDB0V0 IO03NDB0V0
198 EMC_BYTEN[1]/GAC1/IO02PDB0V0 EMC_RW_N/GAA1/IO02PDB0V0
199 EMC_BYTEN[0]/GAC0/IO02NDB0V0 EMC_CLK/GAA0/IO02NDB0V0
200 VCCFPGAIOB0 VCCFPGAIOB0
201 GND GND
202 VCC VCC
203 EMC_CS1_N/GAB1/IO01PDB0V0 IO01PDB0V0
204 EMC_CS0_N/GAB0/IO01NDB0V0 IO01NDB0V0
205 EMC_RW_N/GAA1/IO00PDB0V0 IO00PDB0V0
206 EMC_CLK/GAA0/IO00NDB0V0 IO00NDB0V0
207 VCCFPGAIOB0 VCCFPGAIOB0
208 GNDQ GNDQ
Pin Number
208-Pin PQFP
A2F200 A2F500
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-41
Pin
Number
256-Pin FBGA
A2F060 Func tion A2F200 Functio n
A1 GND GND
A2 VCCFPGAIOB0 VCCFPGAIOB0
A3 EMC_AB[0]/IO04NDB0V0 EMC_AB[0]/IO04NDB0V0
A4 EMC_AB[1]/IO04PDB0V0 EMC_AB[1]/IO04PDB0V0
A5 GND GND
A6 EMC_AB[3]/IO05PDB0V0 EMC_AB[3]/IO05PDB0V0
A7 EMC_AB[5]/IO06PDB0V0 EMC_AB[5]/IO06PDB0V0
A8 VCCFPGAIOB0 VCCFPGAIOB0
A9 GND GND
A10 EMC_AB[14]/IO11NDB0V0 EMC_AB[14]/IO11NDB0V0
A11 EMC_AB[15]/IO11PDB0V0 EMC_AB[15]/IO11PDB0V0
A12 GND GND
A13 EMC_AB[20]/IO14NDB0V0 EMC_AB[20]/IO14NDB0V0
A14 EMC_AB[24]/IO16NDB0V0 EMC_AB[24]/IO16NDB0V0
A15 VCCFPGAIOB0 VCCFPGAIOB0
A16 GND GND
B1 EMC_DB[15]/IO71PDB5V0 EMC_DB[15]/GAA2/IO71PDB5V0
B2 GND GND
B3 EMC_BYTEN[1]/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO02PDB0V0
B4 EMC_OEN0_N/IO03NDB0V0 EMC_OEN0_N/IO03NDB0V0
B5 EMC_OEN1_N/IO03PDB0V0 EMC_OEN1_N/IO03PDB0V0
B6 EMC_AB[2]/IO05NDB0V0 EMC_AB[2]/IO05NDB0V0
B7 EMC_AB[4]/IO06NDB0V0 EMC_AB[4]/IO06NDB0V0
B8 EMC_AB[9]/IO08PDB0V0 EMC_AB[9]/IO08PDB0V0
B9 EMC_AB[12]/IO10NDB0V0 EMC_AB[12]/IO10NDB0V0
B10 EMC_AB[13]/IO10PDB0V0 EMC_AB[13]/IO10PDB0V0
B11 EMC_AB[16]/IO12NDB0V0 EMC_AB[16]/IO12NDB0V0
B12 EMC_AB[18]/IO13NDB0V0 EMC_AB[18]/IO13NDB0V0
B13 EMC_AB[21]/IO14PDB0V0 EMC_AB[21]/IO14PDB0V0
B14 EMC_AB[25]/IO16PDB0V0 EMC_AB[25]/IO16PDB0V0
B15 GND GND
B16 GNDQ GNDQ
C1 EMC_DB[14]/IO71NDB5V0 EMC_DB[14]/GAB2/IO71NDB5V0
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
Pin Descriptions
5-42 Revision 6
C2 VCCPLL VCCPLL
C3 EMC_BYTEN[0]/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO02NDB0V0
C4 VCCFPGAIOB0 VCCFPGAIOB0
C5 EMC_CS0_N/IO01NDB0V0 EMC_CS0_N/GAB0/IO01NDB0V0
C6 EMC_CS1_N/IO01PDB0V0 EMC_CS1_N/GAB1/IO01PDB0V0
C7 GND GND
C8 EMC_AB[8]/IO08NDB0V0 EMC_AB[8]/IO08NDB0V0
C9 EMC_AB[11]/IO09PDB0V0 EMC_AB[11]/IO09PDB0V0
C10 VCCFPGAIOB0 VCCFPGAIOB0
C11 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO12PDB0V0
C12 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO13PDB0V0
C13 GND GND
C14 GBA2/IO20PPB1V0 GBA2/IO20PPB1V0
C15 GCA2/IO23PDB1V0 GCA2/IO23PDB1V0
C16 IO23NDB1V0 IO23NDB1V0
D1 VCCFPGAIOB5 VCCFPGAIOB5
D2 VCOMPLA VCOMPLA
D3 GND GND
D4 GNDQ GNDQ
D5 EMC_CLK/IO00NDB0V0 EMC_CLK/GAA0/IO00NDB0V0
D6 EMC_RW_N/IO00PDB0V0 EMC_RW_N/GAA1/IO00PDB0V0
D7 EMC_AB[6]/IO07NDB0V0 EMC_AB[6]/IO07NDB0V0
D8 EMC_AB[7]/IO07PDB0V0 EMC_AB[7]/IO07PDB0V0
D9 EMC_AB[10]/IO09NDB0V0 EMC_AB[10]/IO09NDB0V0
D10 EMC_AB[22]/IO15NDB0V0 EMC_AB[22]/IO15NDB0V0
D11 EMC_AB[23]/IO15PDB0V0 EMC_AB[23]/IO15PDB0V0
D12 GNDQ GNDQ
D13 GBB2/IO20NPB1V0 GBB2/IO20NPB1V0
D14 GCB2/IO24PDB1V0 GCB2/IO24PDB1V0
D15 IO24NDB1V0 IO24NDB1V0
D16 VCCFPGAIOB1 VCCFPGAIOB1
E1 EMC_DB[13]/IO70PDB5V0 EMC_DB[13]/GAC2/IO70PDB5V0
E2 EMC_DB[12]/IO70NDB5V0 EMC_DB[12]/IO70NDB5V0
Pin
Number
256-Pin FBGA
A2F060 Func tion A2F200 Functio n
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-43
E3 GFA2/IO68PDB5V0 GFA2/IO68PDB5V0
E4 EMC_DB[10]/IO69NPB5V0 EMC_DB[10]/IO69NPB5V0
E5 GNDQ GNDQ
E6 GND GND
E7 VCCFPGAIOB0 VCCFPGAIOB0
E8 GND GND
E9 VCCFPGAIOB0 VCCFPGAIOB0
E10 GND GND
E11 VCCFPGAIOB0 VCCFPGAIOB0
E12 GCA1/IO28PDB1V0 GCA1/IO28PDB1V0
E13 VCCFPGAIOB1 VCCFPGAIOB1
E14 GCB1/IO27PDB1V0 GCB1/IO27PDB1V0
E15 GDC1/IO29PDB1V0 GDC1/IO29PDB1V0
E16 IO29NDB1V0 GDC0/IO29NDB1V0
F1 EMC_DB[9]/IO63PDB5V0 EMC_DB[9]/GEC1/IO63PDB5V0
F2 GND GND
F3 GFB2/IO68NDB5V0 GFB2/IO68NDB5V0
F4 VCCFPGAIOB5 VCCFPGAIOB5
F5 EMC_DB[11]/IO69PPB5V0 EMC_DB[11]/IO69PPB5V0
F6 VCCFPGAIOB5 VCCFPGAIOB5
F7 GND GND
F8 VCC VCC
F9 GND GND
F10 VCC VCC
F11 GND GND
F12 IO28NDB1V0 GCA0/IO28NDB1V0
F13 GNDQ GNDQ
F14 IO27NDB1V0 GCB0/IO27NDB1V0
F15 GND GND
F16 VCCENVM VCCENVM
G1 EMC_DB[8]/IO63NDB5V0 EMC_DB[8]/GEC0/IO63NDB5V0
G2 EMC_DB[7]/IO62PDB5V0 EMC_DB[7]/GEB1/IO62PDB5V0
G3 EMC_DB[6]/IO62NDB5V0 EMC_DB[6]/GEB0/IO62NDB5V0
Pin
Number
256-Pin FBGA
A2F060 Func tion A2F200 Functio n
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
Pin Descriptions
5-44 Revision 6
G4 GFC2/IO67PDB5V0 GFC2/IO67PDB5V0
G5 IO67NDB5V0 IO67NDB5V0
G6 GND GND
G7 VCC VCC
G8 GND GND
G9 VCC VCC
G10 GND GND
G11 VCCFPGAIOB1 VCCFPGAIOB1
G12 VPP VPP
G13 TRSTB TRSTB
G14 TMS TMS
G15 TCK TCK
G16 GNDENVM GNDENVM
H1 GND GND
H2 EMC_DB[5]/IO61PPB5V0 EMC_DB[5]/GEA1/IO61PPB5V0
H3 VCCFPGAIOB5 VCCFPGAIOB5
H4 EMC_DB[1]/IO59PDB5V0 EMC_DB[1]/GEB2/IO59PDB5V0
H5 EMC_DB[0]/IO59NDB5V0 EMC_DB[0]/GEA2/IO59NDB5V0
H6 VCCFPGAIOB5 VCCFPGAIOB5
H7 GND GND
H8 VCC VCC
H9 GND GND
H10 VCC VCC
H11 GND GND
H12 VJTAG VJTAG
H13 TDO TDO
H14 TDI TDI
H15 JTAGSEL JTAGSEL
H16 GND GND
J1 EMC_DB[4]/IO61NPB5V0 EMC_DB[4]/GEA0/IO61NPB5V0
J2 EMC_DB[3]/IO60PDB5V0 EMC_DB[3]/GEC2/IO60PDB5V0
J3 EMC_DB[2]/IO60NDB5V0 EMC_DB[2]/IO60NDB5V0
J4 GNDRCOSC GNDRCOSC
Pin
Number
256-Pin FBGA
A2F060 Func tion A2F200 Functio n
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-45
J5 GNDQ GNDQ
J6 GND GND
J7 VCC VCC
J8 GND GND
J9 VCC VCC
J10 GND GND
J11 VCCMSSIOB2 VCCMSSIOB2
J12 I2C_0_SCL/GPIO_23 I2C_0_SCL/GPIO_23
J13 I2C_0_SDA/GPIO_22 I2C_0_SDA/GPIO_22
J14 I2C_1_SCL/GPIO_31 I2C_1_SCL/GPIO_31
J15 VCCMSSIOB2 VCCMSSIOB2
J16 I2C_1_SDA/GPIO_30 I2C_1_SDA/GPIO_30
K1 IO49RSB4V0 MAC_MDIO/IO49RSB4V0
K2 IO48RSB4V0 MAC_MDC/IO48RSB4V0
K3 VCCMSSIOB4 VCCMSSIOB4
K4 MSS_RESET_N MSS_RESET_N
K5 VCCRCOSC VCCRCOSC
K6 VCCMSSIOB4 VCCMSSIOB4
K7 GND GND
K8 VCC VCC
K9 GND GND
K10 VCC VCC
K11 GND GND
K12 UART_0_RXD/GPIO_21 UART_0_RXD/GPIO_21
K13 GND GND
K14 UART_1_TXD/GPIO_28 UART_1_TXD/GPIO_28
K15 UART_1_RXD/GPIO_29 UART_1_RXD/GPIO_29
K16 UART_0_TXD/GPIO_20 UART_0_TXD/GPIO_20
L1 GND GND
L2 IO52RSB4V0 MAC_TXEN/IO52RSB4V0
L3 IO51RSB4V0 MAC_CRSDV/IO51RSB4V0
L4 IO50RSB4V0 MAC_RXER/IO50RSB4V0
L5 NC MAC_CLK
Pin
Number
256-Pin FBGA
A2F060 Func tion A2F200 Functio n
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
Pin Descriptions
5-46 Revision 6
L6 GND GND
L7 VCC VCC
L8 GND GND
L9 VCC VCC
L10 GND GND
L11 VCCMSSIOB2 VCCMSSIOB2
L12 SPI_1_DO/GPIO_24 SPI_1_DO/GPIO_24
L13 SPI_1_SS/GPIO_27 SPI_1_SS/GPIO_27
L14 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26
L15 SPI_1_DI/GPIO_25 SPI_1_DI/GPIO_25
L16 GND GND
M1 IO56RSB4V0 MAC_TXD[0]/IO56RSB4V0
M2 IO55RSB4V0 MAC_TXD[1]/IO55RSB4V0
M3 IO54RSB4V0 MAC_RXD[0]/IO54RSB4V0
M4 GND GND
M5 NC ADC3
M6 NC GND15ADC0
M7 GND33ADC1 GND33ADC1
M8 GND33ADC1 GND33ADC1
M9 ADC4 ADC4
M10 GNDTM1 GNDTM1
M11 TM2 (ADC) TM2
M12 CM2 (ADC) CM2
M13 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19
M14 VCCMSSIOB2 VCCMSSIOB2
M15 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18
M16 SPI_0_DI/GPIO_17 SPI_0_DI/GPIO_17
N1 IO53RSB4V0 MAC_RXD[1]/IO53RSB4V0
N2 VCCMSSIOB4 VCCMSSIOB4
N3 VCC15A VCC15A
N4 VCC33AP VCC33AP
N5 NC ABPS3
N6 NC TM1
Pin
Number
256-Pin FBGA
A2F060 Func tion A2F200 Functio n
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-47
N7 NC GND33ADC0
N8 VCC33ADC1 VCC33ADC1
N9 ADC5 ADC5
N10 CM3 CM3
N11 GNDAQ GNDAQ
N12 VAREFOUT VAREFOUT
N13 NC GNDSDD1
N14 NC VCC33SDD1
N15 GND GND
N16 SPI_0_DO/GPIO_16 SPI_0_DO/GPIO_16
P1 GNDSDD0 GNDSDD0
P2 VCC33SDD0 VCC33SDD0
P3 VCC33N VCC33N
P4 GNDA GNDA
P5 GNDAQ GNDAQ
P6 NC CM1
P7 NC ADC2
P8 NC VCC15ADC0
P9 ADC6 ADC6
P10 TM3 TM3
P11 GNDA GNDA
P12 VCCMAINXTAL VCCMAINXTAL
P13 GNDLPXTAL GNDLPXTAL
P14 VDDBAT VDDBAT
P15 PTEM PTEM
P16 PTBASE PTBASE
R1 PCAP PCAP
R2 SDD0 SDD0
R3 NC ABPS0
R4 NC TM0
R5 NC ABPS2
R6 NC ADC1
R7 NC VCC33ADC0
Pin
Number
256-Pin FBGA
A2F060 Func tion A2F200 Functio n
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
Pin Descriptions
5-48 Revision 6
R8 VCC15ADC1 VCC15ADC1
R9 ADC7 ADC7
R10 ABPS7 ABPS7
R11 NC ABPS4
R12 MAINXIN MAINXIN
R13 MAINXOUT MAINXOUT
R14 LPXIN LPXIN
R15 LPXOUT LPXOUT
R16 VCC33A VCC33A
T1 NCAP NCAP
T2 NC ABPS1
T3 NC CM0
T4 NC GNDTM0
T5 NC ADC0
T6 NC VAREF0
T7 NC GND33ADC0
T8 GND15ADC1 GND15ADC1
T9 VAREF1 VAREF1
T10 ABPS6 ABPS6
T11 NC ABPS5
T12 NC SDD1
T13 GNDVAREF GNDVAREF
T14 GNDMAINXTAL GNDMAINXTAL
T15 VCCLPXTAL VCCLPXTAL
T16 PU_N PU_N
Pin
Number
256-Pin FBGA
A2F060 Func tion A2F200 Functio n
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-49
Pin Number
256-Pin FBGA
A2F200 Function A2F500 Function
A1 GND GND
A2 VCCFPGAIOB0 VCCFPGAIOB0
A3 EMC_AB[0]/IO04NDB0V0 EMC_AB[0]/IO06NDB0V0
A4 EMC_AB[1]/IO04PDB0V0 EMC_AB[1]/IO06PDB0V0
A5 GND GND
A6 EMC_AB[3]/IO05PDB0V0 EMC_AB[3]/IO09PDB0V0
A7 EMC_AB[5]/IO06PDB0V0 EMC_AB[5]/IO10PDB0V0
A8 VCCFPGAIOB0 VCCFPGAIOB0
A9 GND GND
A10 EMC_AB[14]/IO11NDB0V0 EMC_AB[14]/IO15NDB0V0
A11 EMC_AB[15]/IO11PDB0V0 EMC_AB[15]/IO15PDB0V0
A12 GND GND
A13 EMC_AB[20]/IO14NDB0V0 EMC_AB[20]/IO21NDB0V0
A14 EMC_AB[24]/IO16NDB0V0 EMC_AB[24]/IO20NDB0V0
A15 VCCFPGAIOB0 VCCFPGAIOB0
A16 GND GND
B1 EMC_DB[15]/GAA2/IO71PDB5V0 EMC_DB[15]/GAA2/IO88PDB5V0
B2 GND GND
B3 EMC_BYTEN[1]/GAC1/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO07PDB0V0
B4 EMC_OEN0_N/IO03NDB0V0 EMC_OEN0_N/IO08NDB0V0
B5 EMC_OEN1_N/IO03PDB0V0 EMC_OEN1_N/IO08PDB0V0
B6 EMC_AB[2]/IO05NDB0V0 EMC_AB[2]/IO09NDB0V0
B7 EMC_AB[4]/IO06NDB0V0 EMC_AB[4]/IO10NDB0V0
B8 EMC_AB[9]/IO08PDB0V0 EMC_AB[9]/IO13PDB0V0
B9 EMC_AB[12]/IO10NDB0V0 EMC_AB[12]/IO14NDB0V0
B10 EMC_AB[13]/IO10PDB0V0 EMC_AB[13]/IO14PDB0V0
B11 EMC_AB[16]/IO12NDB0V0 EMC_AB[16]/IO17NDB0V0
B12 EMC_AB[18]/IO13NDB0V0 EMC_AB[18]/IO18NDB0V0
B13 EMC_AB[21]/IO14PDB0V0 EMC_AB[21]/IO21PDB0V0
B14 EMC_AB[25]/IO16PDB0V0 EMC_AB[25]/IO20PDB0V0
B15 GND GND
B16 GNDQ GNDQ
C1 EMC_DB[14]/GAB2/IO71NDB5V0 EMC_DB[14]/GAB2/IO88NDB5V0
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only on
a larger density device.
C2 VCCPLL VCCPLL0
C3 EMC_BYTEN[0]/GAC0/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO07NDB0V0
C4 VCCFPGAIOB0 VCCFPGAIOB0
C5 EMC_CS0_N/GAB0/IO01NDB0V0 EMC_CS0_N/GAB0/IO05NDB0V0
C6 EMC_CS1_N/GAB1/IO01PDB0V0 EMC_CS1_N/GAB1/IO05PDB0V0
C7 GND GND
C8 EMC_AB[8]/IO08NDB0V0 EMC_AB[8]/IO13NDB0V0
C9 EMC_AB[11]/IO09PDB0V0 EMC_AB[11]/IO11PDB0V0
C10 VCCFPGAIOB0 VCCFPGAIOB0
C11 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO17PDB0V0
C12 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO18PDB0V0
C13 GND GND
C14 GBA2/IO20PPB1V0 GBA2/IO27PPB1V0
C15 GCA2/IO23PDB1V0 GCA2/IO28PDB1V0
C16 IO23NDB1V0 IO28NDB1V0
D1 VCCFPGAIOB5 VCCFPGAIOB5
D2 VCOMPLA VCOMPLA0
D3 GND GND
D4 GNDQ GNDQ
D5 EMC_CLK/GAA0/IO00NDB0V0 EMC_CLK/GAA0/IO02NDB0V0
D6 EMC_RW_N/GAA1/IO00PDB0V0 EMC_RW_N/GAA1/IO02PDB0V0
D7 EMC_AB[6]/IO07NDB0V0 EMC_AB[6]/IO12NDB0V0
D8 EMC_AB[7]/IO07PDB0V0 EMC_AB[7]/IO12PDB0V0
D9 EMC_AB[10]/IO09NDB0V0 EMC_AB[10]/IO11NDB0V0
D10 EMC_AB[22]/IO15NDB0V0 EMC_AB[22]/IO19NDB0V0
D11 EMC_AB[23]/IO15PDB0V0 EMC_AB[23]/IO19PDB0V0
D12 GNDQ GNDQ
D13 GBB2/IO20NPB1V0 GBB2/IO27NPB1V0
D14 GCB2/IO24PDB1V0 GCB2/IO33PDB1V0
D15 IO24NDB1V0 IO33NDB1V0
D16 VCCFPGAIOB1 VCCFPGAIOB1
E1 EMC_DB[13]/GAC2/IO70PDB5V0 EMC_DB[13]/GAC2/IO87PDB5V0
E2 EMC_DB[12]/IO70NDB5V0 EMC_DB[12]/IO87NDB5V0
Pin Number
256-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only on
a larger density device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-51
E3 GFA2/IO68PDB5V0 GFA2/IO85PDB5V0
E4 EMC_DB[10]/IO69NPB5V0 EMC_DB[10]/IO86NPB5V0
E5 GNDQ GNDQ
E6 GND GND
E7 VCCFPGAIOB0 VCCFPGAIOB0
E8 GND GND
E9 VCCFPGAIOB0 VCCFPGAIOB0
E10 GND GND
E11 VCCFPGAIOB0 VCCFPGAIOB0
E12 GCA1/IO28PDB1V0 GCA1/IO36PDB1V0
E13 VCCFPGAIOB1 VCCFPGAIOB1
E14 GCB1/IO27PDB1V0 GCB1/IO34PDB1V0
E15 GDC1/IO29PDB1V0 GDC1/IO38PDB1V0
E16 GDC0/IO29NDB1V0 GDC0/IO38NDB1V0
F1 EMC_DB[9]/GEC1/IO63PDB5V0 EMC_DB[9]/GEC1/IO80PDB5V0
F2 GND GND
F3 GFB2/IO68NDB5V0 GFB2/IO85NDB5V0
F4 VCCFPGAIOB5 VCCFPGAIOB5
F5 EMC_DB[11]/IO69PPB5V0 EMC_DB[11]/IO86PPB5V0
F6 VCCFPGAIOB5 VCCFPGAIOB5
F7 GND GND
F8 VCC VCC
F9 GND GND
F10 VCC VCC
F11 GND GND
F12 GCA0/IO28NDB1V0 GCA0/IO36NDB1V0
F13 GNDQ GNDQ
F14 GCB0/IO27NDB1V0 GCB0/IO34NDB1V0
F15 GND GND
F16 VCCENVM VCCENVM
G1 EMC_DB[8]/GEC0/IO63NDB5V0 EMC_DB[8]/GEC0/IO80NDB5V0
G2 EMC_DB[7]/GEB1/IO62PDB5V0 EMC_DB[7]/GEB1/IO79PDB5V0
G3 EMC_DB[6]/GEB0/IO62NDB5V0 EMC_DB[6]/GEB0/IO79NDB5V0
Pin Number
256-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only on
a larger density device.
Pin Descriptions
5-52 Revision 6
G4 GFC2/IO67PDB5V0 GFC2/IO84PDB5V0
G5 IO67NDB5V0 IO84NDB5V0
G6 GND GND
G7 VCC VCC
G8 GND GND
G9 VCC VCC
G10 GND GND
G11 VCCFPGAIOB1 VCCFPGAIOB1
G12 VPP VPP
G13 TRSTB TRSTB
G14 TMS TMS
G15 TCK TCK
G16 GNDENVM GNDENVM
H1 GND GND
H2 EMC_DB[5]/GEA1/IO61PPB5V0 EMC_DB[5]/GEA1/IO78PPB5V0
H3 VCCFPGAIOB5 VCCFPGAIOB5
H4 EMC_DB[1]/GEB2/IO59PDB5V0 EMC_DB[1]/GEB2/IO76PDB5V0
H5 EMC_DB[0]/GEA2/IO59NDB5V0 EMC_DB[0]/GEA2/IO76NDB5V0
H6 VCCFPGAIOB5 VCCFPGAIOB5
H7 GND GND
H8 VCC VCC
H9 GND GND
H10 VCC VCC
H11 GND GND
H12 VJTAG VJTAG
H13 TDO TDO
H14 TDI TDI
H15 JTAGSEL JTAGSEL
H16 GND GND
J1 EMC_DB[4]/GEA0/IO61NPB5V0 EMC_DB[4]/GEA0/IO78NPB5V0
J2 EMC_DB[3]/GEC2/IO60PDB5V0 EMC_DB[3]/GEC2/IO77PDB5V0
J3 EMC_DB[2]/IO60NDB5V0 EMC_DB[2]/IO77NDB5V0
J4 GNDRCOSC GNDRCOSC
Pin Number
256-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only on
a larger density device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-53
J5 GNDQ GNDQ
J6 GND GND
J7 VCC VCC
J8 GND GND
J9 VCC VCC
J10 GND GND
J11 VCCMSSIOB2 VCCMSSIOB2
J12 I2C_0_SCL/GPIO_23 I2C_0_SCL/GPIO_23
J13 I2C_0_SDA/GPIO_22 I2C_0_SDA/GPIO_22
J14 I2C_1_SCL/GPIO_31 I2C_1_SCL/GPIO_31
J15 VCCMSSIOB2 VCCMSSIOB2
J16 I2C_1_SDA/GPIO_30 I2C_1_SDA/GPIO_30
K1 MAC_MDIO/IO49RSB4V0 MAC_MDIO/IO58RSB4V0
K2 MAC_MDC/IO48RSB4V0 MAC_MDC/IO57RSB4V0
K3 VCCMSSIOB4 VCCMSSIOB4
K4 MSS_RESET_N MSS_RESET_N
K5 VCCRCOSC VCCRCOSC
K6 VCCMSSIOB4 VCCMSSIOB4
K7 GND GND
K8 VCC VCC
K9 GND GND
K10 VCC VCC
K11 GND GND
K12 UART_0_RXD/GPIO_21 UART_0_RXD/GPIO_21
K13 GND GND
K14 UART_1_TXD/GPIO_28 UART_1_TXD/GPIO_28
K15 UART_1_RXD/GPIO_29 UART_1_RXD/GPIO_29
K16 UART_0_TXD/GPIO_20 UART_0_TXD/GPIO_20
L1 GND GND
L2 MAC_TXEN/IO52RSB4V0 MAC_TXEN/IO61RSB4V0
L3 MAC_CRSDV/IO51RSB4V0 MAC_CRSDV/IO60RSB4V0
L4 MAC_RXER/IO50RSB4V0 MAC_RXER/IO59RSB4V0
L5 MAC_CLK MAC_CLK
Pin Number
256-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only on
a larger density device.
Pin Descriptions
5-54 Revision 6
L6 GND GND
L7 VCC VCC
L8 GND GND
L9 VCC VCC
L10 GND GND
L11 VCCMSSIOB2 VCCMSSIOB2
L12 SPI_1_DO/GPIO_24 SPI_1_DO/GPIO_24
L13 SPI_1_SS/GPIO_27 SPI_1_SS/GPIO_27
L14 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26
L15 SPI_1_DI/GPIO_25 SPI_1_DI/GPIO_25
L16 GND GND
M1 MAC_TXD[0]/IO56RSB4V0 MAC_TXD[0]/IO65RSB4V0
M2 MAC_TXD[1]/IO55RSB4V0 MAC_TXD[1]/IO64RSB4V0
M3 MAC_RXD[0]/IO54RSB4V0 MAC_RXD[0]/IO63RSB4V0
M4 GND GND
M5 ADC3 ADC3
M6 GND15ADC0 GND15ADC0
M7 GND33ADC1 GND33ADC1
M8 GND33ADC1 GND33ADC1
M9 ADC4 ADC4
M10 GNDTM1 GNDTM1
M11 TM2 TM2
M12 CM2 CM2
M13 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19
M14 VCCMSSIOB2 VCCMSSIOB2
M15 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18
M16 SPI_0_DI/GPIO_17 SPI_0_DI/GPIO_17
N1 MAC_RXD[1]/IO53RSB4V0 MAC_RXD[1]/IO62RSB4V0
N2 VCCMSSIOB4 VCCMSSIOB4
N3 VCC15A VCC15A
N4 VCC33AP VCC33AP
N5 ABPS3 ABPS3
N6 TM1 TM1
Pin Number
256-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only on
a larger density device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-55
N7 GND33ADC0 GND33ADC0
N8 VCC33ADC1 VCC33ADC1
N9 ADC5 ADC5
N10 CM3 CM3
N11 GNDAQ GNDAQ
N12 VAREFOUT VAREFOUT
N13 GNDSDD1 GNDSDD1
N14 VCC33SDD1 VCC33SDD1
N15 GND GND
N16 SPI_0_DO/GPIO_16 SPI_0_DO/GPIO_16
P1 GNDSDD0 GNDSDD0
P2 VCC33SDD0 VCC33SDD0
P3 VCC33N VCC33N
P4 GNDA GNDA
P5 GNDAQ GNDAQ
P6 CM1 CM1
P7 ADC2 ADC2
P8 VCC15ADC0 VCC15ADC0
P9 ADC6 ADC6
P10 TM3 TM3
P11 GNDA GNDA
P12 VCCMAINXTAL VCCMAINXTAL
P13 GNDLPXTAL GNDLPXTAL
P14 VDDBAT VDDBAT
P15 PTEM PTEM
P16 PTBASE PTBASE
R1 PCAP PCAP
R2 SDD0 SDD0
R3 ABPS0 ABPS0
R4 TM0 TM0
R5 ABPS2 ABPS2
R6 ADC1 ADC1
R7 VCC33ADC0 VCC33ADC0
Pin Number
256-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only on
a larger density device.
Pin Descriptions
5-56 Revision 6
R8 VCC15ADC1 VCC15ADC1
R9 ADC7 ADC7
R10 ABPS7 ABPS7
R11 ABPS4 ABPS4
R12 MAINXIN MAINXIN
R13 MAINXOUT MAINXOUT
R14 LPXIN LPXIN
R15 LPXOUT LPXOUT
R16 VCC33A VCC33A
T1 NCAP NCAP
T2 ABPS1 ABPS1
T3 CM0 CM0
T4 GNDTM0 GNDTM0
T5 ADC0 ADC0
T6 VAREF0 VAREF0
T7 GND33ADC0 GND33ADC0
T8 GND15ADC1 GND15ADC1
T9 VAREF1 VAREF1
T10 ABPS6 ABPS6
T11 ABPS5 ABPS5
T12 SDD1 SDD1
T13 GNDVAREF GNDVAREF
T14 GNDMAINXTAL GNDMAINXTAL
T15 VCCLPXTAL VCCLPXTAL
T16 PU_N PU_N
Pin Number
256-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only on
a larger density device.
Pin Descriptions
5-58 Revision 6
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
A1 GND GND
A2 NC NC
A3 NC NC
A4 GND GND
A5 EMC_CS0_N/GAB0/IO01NDB0V0 EMC_CS0_N/GAB0/IO05NDB0V0
A6 EMC_CS1_N/GAB1/IO01PDB0V0 EMC_CS1_N/GAB1/IO05PDB0V0
A7 GND GND
A8 EMC_AB[0]/IO04NDB0V0 EMC_AB[0]/IO06NDB0V0
A9 EMC_AB[1]/IO04PDB0V0 EMC_AB[1]/IO06PDB0V0
A10 GND GND
A11 NC NC
A12 EMC_AB[7]/IO07PDB0V0 EMC_AB[7]/IO12PDB0V0
A13 GND GND
A14 EMC_AB[12]/IO10NDB0V0 EMC_AB[12]/IO14NDB0V0
A15 EMC_AB[13]/IO10PDB0V0 EMC_AB[13]/IO14PDB0V0
A16 GND GND
A17 NC IO16NDB0V0
A18 NC IO16PDB0V0
A19 GND GND
A20 NC NC
A21 NC NC
A22 GND GND
AA1 GPIO_4/IO43RSB4V0 GPIO_4/IO52RSB4V0
AA2 GPIO_12/IO37RSB4V0 GPIO_12/IO46RSB4V0
AA3 MAC_MDC/IO48RSB4V0 MAC_MDC/IO57RSB4V0
AA4 MAC_RXER/IO50RSB4V0 MAC_RXER/IO59RSB4V0
AA5 MAC_TXD[0]/IO56RSB4V0 MAC_TXD[0]/IO65RSB4V0
AA6 ABPS0 ABPS0
AA7 TM1 TM1
AA8 ADC1 ADC1
AA9 GND15ADC1 GND15ADC1
AA10 GND33ADC1 GND33ADC1
AA11 CM3 CM3
AA12 GNDTM1 GNDTM1
AA13 NC ADC10
AA14 NC ADC9
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-59
AA15 NC GND15ADC2
AA16 MAINXIN MAINXIN
AA17 MAINXOUT MAINXOUT
AA18 LPXIN LPXIN
AA19 LPXOUT LPXOUT
AA20 NC NC
AA21 NC NC
AA22 SPI_1_CLK/GPIO_26 SPI_1_CLK/GPIO_26
AB1 GND GND
AB2 GPIO_13/IO36RSB4V0 GPIO_13/IO45RSB4V0
AB3 GPIO_14/IO35RSB4V0 GPIO_14/IO44RSB4V0
AB4 GND GND
AB5 PCAP PCAP
AB6 NCAP NCAP
AB7 ABPS3 ABPS3
AB8 ADC3 ADC3
AB9 GND15ADC0 GND15ADC0
AB10 VCC33ADC1 VCC33ADC1
AB11 VAREF1 VAREF1
AB12 TM2 TM2
AB13 CM2 CM2
AB14 ABPS4 ABPS4
AB15 GNDAQ GNDAQ
AB16 GNDMAINXTAL GNDMAINXTAL
AB17 GNDLPXTAL GNDLPXTAL
AB18 VCCLPXTAL VCCLPXTAL
AB19 VDDBAT VDDBAT
AB20 PTBASE PTBASE
AB21 NC NC
AB22 GND GND
B1 EMC_DB[15]/GAA2/IO71PDB5V0 EMC_DB[15]/GAA2/IO88PDB5V0
B2 GND GND
B3 NC NC
B4 NC NC
B5 VCCFPGAIOB0 VCCFPGAIOB0
B6 EMC_RW_N/GAA1/IO00PDB0V0 EMC_RW_N/GAA1/IO02PDB0V0
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
Pin Descriptions
5-60 Revision 6
B7 NC IO04PPB0V0
B8 VCCFPGAIOB0 VCCFPGAIOB0
B9 EMC_BYTEN[0]/GAC0/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO07NDB0V0
B10 EMC_AB[2]/IO05NDB0V0 EMC_AB[2]/IO09NDB0V0
B11 EMC_AB[3]/IO05PDB0V0 EMC_AB[3]/IO09PDB0V0
B12 EMC_AB[6]/IO07NDB0V0 EMC_AB[6]/IO12NDB0V0
B13 EMC_AB[14]/IO11NDB0V0 EMC_AB[14]/IO15NDB0V0
B14 EMC_AB[15]/IO11PDB0V0 EMC_AB[15]/IO15PDB0V0
B15 VCCFPGAIOB0 VCCFPGAIOB0
B16 EMC_AB[18]/IO13NDB0V0 EMC_AB[18]/IO18NDB0V0
B17 EMC_AB[19]/IO13PDB0V0 EMC_AB[19]/IO18PDB0V0
B18 VCCFPGAIOB0 VCCFPGAIOB0
B19 GBB0/IO18NDB0V0 GBB0/IO24NDB0V0
B20 GBB1/IO18PDB0V0 GBB1/IO24PDB0V0
B21 GND GND
B22 GBA2/IO20PDB1V0 GBA2/IO27PDB1V0
C1 EMC_DB[14]/GAB2/IO71NDB5V0 EMC_DB[14]/GAB2/IO88NDB5V0
C2 NC NC
C3 NC NC
C4 NC IO01NDB0V0
C5 NC IO01PDB0V0
C6 EMC_CLK/GAA0/IO00NDB0V0 EMC_CLK/GAA0/IO02NDB0V0
C7 NC IO03PPB0V0
C8 NC IO04NPB0V0
C9 EMC_BYTEN[1]/GAC1/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO07PDB0V0
C10 EMC_OEN1_N/IO03PDB0V0 EMC_OEN1_N/IO08PDB0V0
C11 GND GND
C12 VCCFPGAIOB0 VCCFPGAIOB0
C13 EMC_AB[8]/IO08NDB0V0 EMC_AB[8]/IO13NDB0V0
C14 EMC_AB[16]/IO12NDB0V0 EMC_AB[16]/IO17NDB0V0
C15 EMC_AB[17]/IO12PDB0V0 EMC_AB[17]/IO17PDB0V0
C16 EMC_AB[24]/IO16NDB0V0 EMC_AB[24]/IO20NDB0V0
C17 EMC_AB[22]/IO15NDB0V0 EMC_AB[22]/IO19NDB0V0
C18 EMC_AB[23]/IO15PDB0V0 EMC_AB[23]/IO19PDB0V0
C19 GBA0/IO19NPB0V0 GBA0/IO23NPB0V0
C20 NC NC
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-61
C21 GBC2/IO21PDB1V0 GBC2/IO30PDB1V0
C22 GBB2/IO20NDB1V0 GBB2/IO27NDB1V0
D1 GND GND
D2 EMC_DB[12]/IO70NDB5V0 EMC_DB[12]/IO87NDB5V0
D3 EMC_DB[13]/GAC2/IO70PDB5V0 EMC_DB[13]/GAC2/IO87PDB5V0
D4 NC NC
D5 NC NC
D6 GND GND
D7 NC IO00NPB0V0
D8 NC IO03NPB0V0
D9 GND GND
D10 EMC_OEN0_N/IO03NDB0V0 EMC_OEN0_N/IO08NDB0V0
D11 EMC_AB[10]/IO09NDB0V0 EMC_AB[10]/IO11NDB0V0
D12 EMC_AB[11]/IO09PDB0V0 EMC_AB[11]/IO11PDB0V0
D13 EMC_AB[9]/IO08PDB0V0 EMC_AB[9]/IO13PDB0V0
D14 GND GND
D15 GBC1/IO17PPB0V0 GBC1/IO22PPB0V0
D16 EMC_AB[25]/IO16PDB0V0 EMC_AB[25]/IO20PDB0V0
D17 GND GND
D18 GBA1/IO19PPB0V0 GBA1/IO23PPB0V0
D19 NC NC
D20 NC NC
D21 IO21NDB1V0 IO30NDB1V0
D22 GND GND
E1 GFC2/IO67PPB5V0 GFC2/IO84PPB5V0
E2 VCCFPGAIOB5 VCCFPGAIOB5
E3 GFA2/IO68PDB5V0 GFA2/IO85PDB5V0
E4 GND GND
E5 NC NC
E6 GNDQ GNDQ
E7 VCCFPGAIOB0 VCCFPGAIOB0
E8 NC IO00PPB0V0
E9 NC NC
E10 VCCFPGAIOB0 VCCFPGAIOB0
E11 EMC_AB[4]/IO06NDB0V0 EMC_AB[4]/IO10NDB0V0
E12 EMC_AB[5]/IO06PDB0V0 EMC_AB[5]/IO10PDB0V0
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
Pin Descriptions
5-62 Revision 6
E13 VCCFPGAIOB0 VCCFPGAIOB0
E14 GBC0/IO17NPB0V0 GBC0/IO22NPB0V0
E15 NC NC
E16 VCCFPGAIOB0 VCCFPGAIOB0
E17 NC VCOMPLA1
E18 NC IO25NPB1V0
E19 GND GND
E20 NC NC
E21 VCCFPGAIOB1 VCCFPGAIOB1
E22 IO22NDB1V0 IO32NDB1V0
F1 GFB1/IO65PPB5V0 GFB1/IO82PPB5V0
F2 IO67NPB5V0 IO84NPB5V0
F3 GFB2/IO68NDB5V0 GFB2/IO85NDB5V0
F4 EMC_DB[10]/IO69NPB5V0 EMC_DB[10]/IO86NPB5V0
F5 VCCFPGAIOB5 VCCFPGAIOB5
F6 VCCPLL VCCPLL0
F7 VCOMPLA VCOMPLA0
F8 NC NC
F9 NC NC
F10 NC NC
F11 NC NC
F12 NC NC
F13 EMC_AB[20]/IO14NDB0V0 EMC_AB[20]/IO21NDB0V0
F14 EMC_AB[21]/IO14PDB0V0 EMC_AB[21]/IO21PDB0V0
F15 GNDQ GNDQ
F16 NC VCCPLL1
F17 NC IO25PPB1V0
F18 VCCFPGAIOB1 VCCFPGAIOB1
F19 IO23NDB1V0 IO28NDB1V0
F20 NC IO31PDB1V0
F21 NC IO31NDB1V0
F22 IO22PDB1V0 IO32PDB1V0
G1 GND GND
G2 GFB0/IO65NPB5V0 GFB0/IO82NPB5V0
G3 EMC_DB[9]/GEC1/IO63PDB5V0 EMC_DB[9]/GEC1/IO80PDB5V0
G4 GFC1/IO66PPB5V0 GFC1/IO83PPB5V0
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-63
G5 EMC_DB[11]/IO69PPB5V0 EMC_DB[11]/IO86PPB5V0
G6 GNDQ GNDQ
G7 NC NC
G8 GND GND
G9 VCCFPGAIOB0 VCCFPGAIOB0
G10 GND GND
G11 VCCFPGAIOB0 VCCFPGAIOB0
G12 GND GND
G13 VCCFPGAIOB0 VCCFPGAIOB0
G14 GND GND
G15 VCCFPGAIOB0 VCCFPGAIOB0
G16 GNDQ GNDQ
G17 NC IO26PDB1V0
G18 NC IO26NDB1V0
G19 GCA2/IO23PDB1V0 GCA2/IO28PDB1V0
G20 IO24NDB1V0 IO33NDB1V0
G21 GCB2/IO24PDB1V0 GCB2/IO33PDB1V0
G22 GND GND
H1 EMC_DB[7]/GEB1/IO62PDB5V0 EMC_DB[7]/GEB1/IO79PDB5V0
H2 VCCFPGAIOB5 VCCFPGAIOB5
H3 EMC_DB[8]/GEC0/IO63NDB5V0 EMC_DB[8]/GEC0/IO80NDB5V0
H4 GND GND
H5 GFC0/IO66NPB5V0 GFC0/IO83NPB5V0
H6 GFA1/IO64PDB5V0 GFA1/IO81PDB5V0
H7 GND GND
H8 VCC VCC
H9 GND GND
H10 VCC VCC
H11 GND GND
H12 VCC VCC
H13 GND GND
H14 VCC VCC
H15 GND GND
H16 VCCFPGAIOB1 VCCFPGAIOB1
H17 IO25NDB1V0 IO29NDB1V0
H18 GCC2/IO25PDB1V0 GCC2/IO29PDB1V0
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
Pin Descriptions
5-64 Revision 6
H19 GND GND
H20 GCC0/IO26NPB1V0 GCC0/IO35NPB1V0
H21 VCCFPGAIOB1 VCCFPGAIOB1
H22 GCB0/IO27NDB1V0 GCB0/IO34NDB1V0
J1 EMC_DB[6]/GEB0/IO62NDB5V0 EMC_DB[6]/GEB0/IO79NDB5V0
J2 EMC_DB[5]/GEA1/IO61PDB5V0 EMC_DB[5]/GEA1/IO78PDB5V0
J3 EMC_DB[4]/GEA0/IO61NDB5V0 EMC_DB[4]/GEA0/IO78NDB5V0
J4 EMC_DB[3]/GEC2/IO60PPB5V0 EMC_DB[3]/GEC2/IO77PPB5V0
J5 VCCFPGAIOB5 VCCFPGAIOB5
J6 GFA0/IO64NDB5V0 GFA0/IO81NDB5V0
J7 VCCFPGAIOB5 VCCFPGAIOB5
J8 GND GND
J9 VCC VCC
J10 GND GND
J11 VCC VCC
J12 GND GND
J13 VCC VCC
J14 GND GND
J15 VCC VCC
J16 GND GND
J17 NC IO37PDB1V0
J18 VCCFPGAIOB1 VCCFPGAIOB1
J19 GCA0/IO28NDB1V0 GCA0/IO36NDB1V0
J20 GCA1/IO28PDB1V0 GCA1/IO36PDB1V0
J21 GCC1/IO26PPB1V0 GCC1/IO35PPB1V0
J22 GCB1/IO27PDB1V0 GCB1/IO34PDB1V0
K1 GND GND
K2 EMC_DB[0]/GEA2/IO59NDB5V0 EMC_DB[0]/GEA2/IO76NDB5V0
K3 EMC_DB[1]/GEB2/IO59PDB5V0 EMC_DB[1]/GEB2/IO76PDB5V0
K4 NC IO74PPB5V0
K5 EMC_DB[2]/IO60NPB5V0 EMC_DB[2]/IO77NPB5V0
K6 NC IO75PDB5V0
K7 GND GND
K8 VCC VCC
K9 GND GND
K10 VCC VCC
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-65
K11 GND GND
K12 VCC VCC
K13 GND GND
K14 VCC VCC
K15 GND GND
K16 VCCFPGAIOB1 VCCFPGAIOB1
K17 NC IO37NDB1V0
K18 GDA1/IO31PDB1V0 GDA1/IO40PDB1V0
K19 GDA0/IO31NDB1V0 GDA0/IO40NDB1V0
K20 GDC1/IO29PDB1V0 GDC1/IO38PDB1V0
K21 GDC0/IO29NDB1V0 GDC0/IO38NDB1V0
K22 GND GND
L1 NC IO73PDB5V0
L2 NC IO73NDB5V0
L3 NC IO72PPB5V0
L4 GND GND
L5 NC IO74NPB5V0
L6 NC IO75NDB5V0
L7 VCCFPGAIOB5 VCCFPGAIOB5
L8 GND GND
L9 VCC VCC
L10 GND GND
L11 VCC VCC
L12 GND GND
L13 VCC VCC
L14 GND GND
L15 VCC VCC
L16 GND GND
L17 GNDQ GNDQ
L18 GDA2/IO33NDB1V0 GDA2/IO42NDB1V0
L19 VCCFPGAIOB1 VCCFPGAIOB1
L20 GDB1/IO30PDB1V0 GDB1/IO39PDB1V0
L21 GDB0/IO30NDB1V0 GDB0/IO39NDB1V0
L22 GDC2/IO32PDB1V0 GDC2/IO41PDB1V0
M1 NC IO71PDB5V0
M2 NC IO71NDB5V0
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
Pin Descriptions
5-66 Revision 6
M3 VCCFPGAIOB5 VCCFPGAIOB5
M4 NC IO72NPB5V0
M5 GNDQ GNDQ
M6 NC IO68PDB5V0
M7 GND GND
M8 VCC VCC
M9 GND GND
M10 VCC VCC
M11 GND GND
M12 VCC VCC
M13 GND GND
M14 VCC VCC
M15 GND GND
M16 VCCFPGAIOB1 VCCFPGAIOB1
M17 NC NC
M18 GDB2/IO33PDB1V0 GDB2/IO42PDB1V0
M19 VJTAG VJTAG
M20 GND GND
M21 VPP VPP
M22 IO32NDB1V0 IO41NDB1V0
N1 GND GND
N2 NC IO70PDB5V0
N3 NC IO70NDB5V0
N4 VCCRCOSC VCCRCOSC
N5 VCCFPGAIOB5 VCCFPGAIOB5
N6 NC IO68NDB5V0
N7 VCCFPGAIOB5 VCCFPGAIOB5
N8 GND GND
N9 VCC VCC
N10 GND GND
N11 VCC VCC
N12 GND GND
N13 VCC VCC
N14 GND GND
N15 VCC VCC
N16 NC GND
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-67
N17 NC NC
N18 VCCFPGAIOB1 VCCFPGAIOB1
N19 VCCENVM VCCENVM
N20 GNDENVM GNDENVM
N21 NC NC
N22 GND GND
P1 NC IO69NDB5V0
P2 NC IO69PDB5V0
P3 GNDRCOSC GNDRCOSC
P4 GND GND
P5 NC NC
P6 NC NC
P7 GND GND
P8 VCC VCC
P9 GND GND
P10 VCC VCC
P11 GND GND
P12 VCC VCC
P13 GND GND
P14 VCC VCC
P15 GND GND
P16 VCCFPGAIOB1 VCCFPGAIOB1
P17 TDI TDI
P18 TCK TCK
P19 GND GND
P20 TMS TMS
P21 TDO TDO
P22 TRSTB TRSTB
R1 MSS_RESET_N MSS_RESET_N
R2 VCCFPGAIOB5 VCCFPGAIOB5
R3 GPIO_1/IO46RSB4V0 GPIO_1/IO55RSB4V0
R4 NC NC
R5 NC NC
R6 NC NC
R7 NC NC
R8 GND GND
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
Pin Descriptions
5-68 Revision 6
R9 VCC VCC
R10 GND GND
R11 VCC VCC
R12 GND GND
R13 VCC VCC
R14 GND GND
R15 VCC VCC
R16 JTAGSEL JTAGSEL
R17 NC NC
R18 NC NC
R19 NC NC
R20 NC NC
R21 VCCFPGAIOB1 VCCFPGAIOB1
R22 NC NC
T1 GND GND
T2 VCCMSSIOB4 VCCMSSIOB4
T3 GPIO_8/IO39RSB4V0 GPIO_8/IO48RSB4V0
T4 GPIO_11/IO57RSB4V0 GPIO_11/IO66RSB4V0
T5 GND GND
T6 MAC_CLK MAC_CLK
T7 VCCMSSIOB4 VCCMSSIOB4
T8 VCC33SDD0 VCC33SDD0
T9 VCC15A VCC15A
T10 GNDAQ GNDAQ
T11 GND33ADC0 GND33ADC0
T12 ADC7 ADC7
T13 NC TM4
T14 NC VAREF2
T15 VAREFOUT VAREFOUT
T16 VCCMSSIOB2 VCCMSSIOB2
T17 SPI_1_DO/GPIO_24 SPI_1_DO/GPIO_24
T18 GND GND
T19 NC NC
T20 NC NC
T21 VCCMSSIOB2 VCCMSSIOB2
T22 GND GND
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-69
U1 GND GND
U2 GPIO_5/IO42RSB4V0 GPIO_5/IO51RSB4V0
U3 GPIO_10/IO58RSB4V0 GPIO_10/IO67RSB4V0
U4 VCCMSSIOB4 VCCMSSIOB4
U5 MAC_RXD[1]/IO53RSB4V0 MAC_RXD[1]/IO62RSB4V0
U6 NC NC
U7 VCC33AP VCC33AP
U8 VCC33N VCC33N
U9 CM1 CM1
U10 VAREF0 VAREF0
U11 GND33ADC1 GND33ADC1
U12 ADC4 ADC4
U13 NC GNDTM2
U14 NC ADC11
U15 GNDVAREF GNDVAREF
U16 VCC33SDD1 VCC33SDD1
U17 SPI_0_DO/GPIO_16 SPI_0_DO/GPIO_16
U18 UART_0_RXD/GPIO_21 UART_0_RXD/GPIO_21
U19 VCCMSSIOB2 VCCMSSIOB2
U20 I2C_1_SCL/GPIO_31 I2C_1_SCL/GPIO_31
U21 I2C_0_SCL/GPIO_23 I2C_0_SCL/GPIO_23
U22 GND GND
V1 GPIO_0/IO47RSB4V0 GPIO_0/IO56RSB4V0
V2 GPIO_6/IO41RSB4V0 GPIO_6/IO50RSB4V0
V3 GPIO_9/IO38RSB4V0 GPIO_9/IO47RSB4V0
V4 MAC_MDIO/IO49RSB4V0 MAC_MDIO/IO58RSB4V0
V5 MAC_RXD[0]/IO54RSB4V0 MAC_RXD[0]/IO63RSB4V0
V6 GND GND
V7 SDD0 SDD0
V8 ABPS1 ABPS1
V9 ADC2 ADC2
V10 VCC33ADC0 VCC33ADC0
V11 ADC6 ADC6
V12 ADC5 ADC5
V13 ABPS5 ABPS5
V14 NC ADC8
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
Pin Descriptions
5-70 Revision 6
V15 NC GND33ADC2
V16 NC NC
V17 GND GND
V18 SPI_0_DI/GPIO_17 SPI_0_DI/GPIO_17
V19 SPI_1_DI/GPIO_25 SPI_1_DI/GPIO_25
V20 UART_1_TXD/GPIO_28 UART_1_TXD/GPIO_28
V21 I2C_0_SDA/GPIO_22 I2C_0_SDA/GPIO_22
V22 I2C_1_SDA/GPIO_30 I2C_1_SDA/GPIO_30
W1 GPIO_2/IO45RSB4V0 GPIO_2/IO54RSB4V0
W2 GPIO_7/IO40RSB4V0 GPIO_7/IO49RSB4V0
W3 GND GND
W4 MAC_CRSDV/IO51RSB4V0 MAC_CRSDV/IO60RSB4V0
W5 MAC_TXD[1]/IO55RSB4V0 MAC_TXD[1]/IO64RSB4V0
W6 NC SDD2
W7 GNDA GNDA
W8 TM0 TM0
W9 ABPS2 ABPS2
W10 GND33ADC0 GND33ADC0
W11 VCC15ADC1 VCC15ADC1
W12 ABPS6 ABPS6
W13 NC CM4
W14 NC ABPS9
W15 NC VCC33ADC2
W16 GNDA GNDA
W17 PU_N PU_N
W18 GNDSDD1 GNDSDD1
W19 SPI_0_CLK/GPIO_18 SPI_0_CLK/GPIO_18
W20 GND GND
W21 SPI_1_SS/GPIO_27 SPI_1_SS/GPIO_27
W22 UART_1_RXD/GPIO_29 UART_1_RXD/GPIO_29
Y1 GPIO_3/IO44RSB4V0 GPIO_3/IO53RSB4V0
Y2 VCCMSSIOB4 VCCMSSIOB4
Y3 GPIO_15/IO34RSB4V0 GPIO_15/IO43RSB4V0
Y4 MAC_TXEN/IO52RSB4V0 MAC_TXEN/IO61RSB4V0
Y5 VCCMSSIOB4 VCCMSSIOB4
Y6 GNDSDD0 GNDSDD0
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 5-71
Y7 CM0 CM0
Y8 GNDTM0 GNDTM0
Y9 ADC0 ADC0
Y10 VCC15ADC0 VCC15ADC0
Y11 ABPS7 ABPS7
Y12 TM3 TM3
Y13 NC ABPS8
Y14 NC GND33ADC2
Y15 NC VCC15ADC2
Y16 VCCMAINXTAL VCCMAINXTAL
Y17 SDD1 SDD1
Y18 PTEM PTEM
Y19 VCC33A VCC33A
Y20 SPI_0_SS/GPIO_19 SPI_0_SS/GPIO_19
Y21 VCCMSSIOB2 VCCMSSIOB2
Y22 UART_0_TXD/GPIO_20 UART_0_TXD/GPIO_20
Pin Number
484-Pin FBGA
A2F200 Function A2F500 Function
Note: Shading denotes pins that do not have completely identical functions from density to density. For
example, the bank assignment can be different for an I/O, or the function might be available only
on a larger d ensity device.
Revision 6 6-1
6 – Dat asheet Information
List of Changes
The following table lists critical changes that were made in each revision of the SmartFusion datasheet.
Revision Changes Page
Revision 6
(March 2011)
The "PQ208" package was added to product tables and "Product Ordering Codes" for
A2F200 and A2F500 (SAR 31005).
III
The "Package I/Os: MSS + FPGA I/Os" table was revised to add the CS288 package
for A2F060 and the PQ208 package for A2F200 and A2F500. A row was added for
shared analog inputs (SAR 31034).
III
The "SmartFusion Device Status" table was updated (SAR 31084).III
VCCESRAM was added to Table 2-1 • Absolute Maximum Ratings, Ta ble 2- 3 •
Recommended Operating Conditions, Table 2-8 • Quiescent Supply Current
Characteristics, and the "Supply Pins" table (SAR 31035).
2-1, 2-3,
2-10, 5-1
The following note was removed from Table 2-8 • Quiescent Supply Current
Characteristics (SAR 30984):
"Current monitors and temperature monitors should not be used when Power-Down
and/or Sleep mode are required by the application."
2-10
Dynamic power values were updated in the following tables. The table subtitles
changed where FPGA I/O banks were involved to note "I/O assigned to EMC I/O pins"
(SAR 30987).
Table 2-9 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software
Settings
Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software
Settings.
2-10
2-11
The "Timing Model" was updated (SAR 30986). 2-19
Values in the timing tables for the following sections were updated. Table subtitles
were updated for FPGA I/O banks to note "I/O assigned to EMC I/O pins " (SAR
30986).
"Overview of I/O Performance" section: Tabl e 2-2 3 , Table 2-24
"Detailed I/O DC Characteristics" section: Table 2-37, Ta ble 2 -3 8, Table 2-39,
Table 2-43, Tabl e 2 -44 , Table 2-45, Ta bl e 2-4 9, Table 2-50, Ta b le 2- 51 , Table 2-55,
Table 2-56, Table 2-57, Tab l e 2-6 0, Tab le 2- 6 1
"LVDS" section: Ta bl e 2-6 4
"LVPECL" section: Tab l e 2-6 7
"Global Tree Timing Characteristics" section: Tab le 2 -79 , Tabl e 2- 80
2-23
2-26
2-40
2-43
2-60
The "208-Pin PQFP" section and pin tables are new (SAR 31005). 5-33
Global clocks were removed from the A2F060 pin table for the "288-Pin CSP" and
"256-Pin FBGA" packages, resulting in changed function names for affected pins (SAR
31033).
5-41
Datasheet Information
6-2 Revision 6
Revision 5
(December 2010)
Table 2-2 • Analog Maximum Ratings was revised. The recommended CM[n] pad
voltage (relative to ground) was changed from –11 to –0.3 (SAR 28219).
2-2
Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays was revised
to change the values for 100ºC.
2-9
Power-down and Sleep modes, and all associated notes, were removed from
Table 2-8 • Quiescent Supply Current Characteristics (SAR 29479). IDC3 and IDC4
were renamed to IDC1 and IDC2 (SAR 29478). These modes are no longer supported.
A note was added to the table stating that current monitors and temperature monitors
should not be used when Power-down and/or Sleep mode are required by the
application.
2-10
The "Power-Down and Sleep Mode Implementation" section was deleted (SAR
29479).
N/A
Values for PAC9 and PAC10 for LVDS and LVPECL were revised in Table 2-9 •
Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings and
Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software
Settings*.
2-10,
2-11
Values for PAC1 through PAC4, PDC1, and PDC2 were added for A2F500 in
Table 2-13 • Different Components Contributing to Dynamic Power Consumption in
SmartFusion Devices and Table 2-14 • Different Components Contributing to the Static
Power Consumption in SmartFusion Devices
2-12,
2-13
The equation for "Total Dynamic Power Consumption—PDYN" in "SoC Mode" was
revised to add PMSS. The "Microcontroller Subsystem Dynamic Contribution—PMSS"
section is new (SAR 29462).
2-14,
2-18
Information in Table 2-23 • Summary of I/O Timing Characteristics—Software Default
Settings (applicable to FPGA I/O banks) and Table 2-24 • Summary of I/O Timing
Characteristics—Software Default Settings (applicable to MSS I/O banks) was
updated.
2-25
Available values for the Std. speed were added to the timing tables from Table 2-37 •
3.3 V LVTTL / 3.3 V LVCMOS High Slew to Table 2-90 • JTAG 1532 (SAR 29331).
One or more values changed for the –1 speed in tables covering 3.3 V LVCMOS, 2.5 V
LVCMOS, 1.8 V LVCMOS, 1.5 V LVCMOS, Combinatorial Cell Propagation Delays,
and A2F200 Global Resources.
2-31 to
2-74
Table 2-79 • A2F500 Global Resource is new. 2-60
Table 2-88 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C,
VCC = 1.425 V was revised (SAR 27585).
2-73
The programmable analog specifications tables were revised with updated
information.
2-75 to
2-84
Table 4-1 • Supported JTAG Programming Hardware was revised by adding a note to
indicate "planned support" for several of the items in the table.
4-5
The note on JTAGSEL in the "In-System Programming" section was revised to state
that SoftConsole selects the appropriate TAP controller using the CTXSELECT JTAG
command. When using SoftConsole, the state of JTAGSEL is a "don't care" (SAR
29261).
4-5
The "288-Pin CSP" and "256-Pin FBGA" pin tables for A2F060 are new, comparing the
A2F060 function with the A2F200 function (SAR 29353).
5-17
The "Handling When Unused" column was removed from the "256-Pin FBGA" pin
table for A2F200 and A2F500 (SAR 29691).
5-49
Revision Changes Page
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 6-3
Revision 4
(September
2010)
Table 2-8 • Quiescent Supply Current Characteristics was revised. VCCRCOSC was
moved to a column of its own with new values. VCCENVM was added to the table.
Standby mode for VJTAG and VPP was changed from 0 V to N/A. "Disable" was
changed to "Off "in the eNVM column. The column for RCOSC was deleted.
2-10
The "Power-Down and Sleep Mode Implementation" section was revised to include
VCCROSC.
2-11
Revision 3
(September
2010)
The "I/Os and Operating Voltage" section was revised to list "single 3.3 V power supply
with on-chip 1.5 V regulator" and "external 1.5 V is allowed" (SAR 27663).
I
The CS288 package was added to the "Package I/Os: MSS + FPGA I/Os" table (SAR
27101), "Product Ordering Codes" table, and "Temperature Grade Offerings" table
(SAR 27044). The number of direct analog inputs for the FG256 package in A2F060
was changed from 8 to 6.
III, VI, VI
Two notes were added to the "SmartFusion Family Product Table" indicating
limitations for features of the A2F500 device:
Two PLLs are available in CS288 and FG484 (one PL L in FG256).
[ADCs, DACs, SCBs, comparators, current monitors, and bipolar high voltage
monitors are] Available on FG484 only. FG256 and CS288 packages offer the same
programmable analog capabiliti es a s A2F200.
Table cells were merged in rows containing the same values for easier reading (SAR
24748).
II
The security feature option was added to the "Product Ordering Codes" table. VI
In Table 2-3 • Recommended Operating Conditions, the VDDBAT recommended
operating range was changed from "2.97 to 3.63" to "2.7 to 3.63" (SAR 25246).
Recommended operating range was changed to "3.15 to 3.45" for the following
voltages:
VCC33A
VCC33ADCx
VCC33AP
VCC33SDDx
VCCMAINXTAL
VCCLPXTAL
Two notes were added to the table (SAR 27109):
1. The following 3.3 V supplies should be connected together while following proper noise
filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL,
and VCCLPXTAL.
2. The following 1.5 V supplies should be connected together while following proper noise
filtering practices: VCC, VCC15A, and VCC15ADCx.
2-3
In Table 2-3 • Recommended Operating Conditions, the description for VCCLPXTAL
was corrected to change "32 Hz" to "32 KHz" (SAR 27110).
2-3
The "Power Supply Sequencing Requirement" section is new (SAR 27178). 2-4
Table 2-8 • Quiescent Supply Current Characteristics was revised to change most
on/off entries to voltages. Note 5 was added, stating that "on" means proper voltage is
applied. The values of 6 µA and 16 µA were removed for IDC1 and IDC2 for 3.3 V. A
note was added for IDC1 and IDC2: "Power mode and Sleep mode are consuming
higher current than expected in the current version of silicon. These specifications will
be updated when new version of the silicon is available" (SAR 27926).
2-10
The "Power-Down and Sleep Mode Implementation" section is new (SAR 27178). 2-11
Revision Changes Page
Datasheet Information
6-4 Revision 6
Revision 3
(continued)
A note was added to Table 2-84 • SmartFusion CCC/PLL Specification, pertaining to
fout_CCC, stating that "one of the CCC outputs (GLA0) is used as an MSS clock and is
limited to 100 MHz (maximum) by software" (SAR 26388).
2-63
Table 2-88 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C,
VCC = 1.425 V was revised. Values were included for A2F200 and A2F500, for –1 and
Std. speed grades. A note was added to define 6:1:1:1 and 5:1:1:1 (SAR 26166).
2-73
The units were corrected (mV instead of V) for input referred offset voltage, GDEC[1:0]
= 00 in Table 2-94 • ABPS Performance Specifications (SAR 25381).
2-79
The test condition values for operating current (ICC33A, typical) were changed in
Table 2-97 • Voltage Regulator (SAR 26465).
2-84
Figure 2-44 • Typical Output Voltage was revised to add legends for the three curves,
stating the load represented by each (SAR 25247).
2-85
The "SmartFusion Programming" chapter was moved to this document from the
SmartFusion Subsystem Microcontroller User’s Guide (SAR 26542). The "Typical
Programming and Erase Times" section was added to this chapter.
4-5
Figure 4-1 • TRSTB Logic was revised to change 1.5 V to "VJTAG (1.5 V to 3.3 V
nominal)" (SAR 24694).
4-6
Two notes were added to the "Supply Pins" table (SAR 27109):
1. The following supplies should be connected together while following proper noise
filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL,
and VCCLPXTAL.
2. The following 1.5 V supplies should be connected together while following proper noise
filtering practices: VCC, VCC15A, and VCC15ADCx.
5-1
The descriptions for the "VCC33N", "NCAP", and "PCAP" pins were revised to include
information on what to do if analog SCB features and SDDs are not used (SAR
26744).
5-2, 5-6,
5-7
Information was added to the "User Pins" table regarding tristating of used and unused
GPIO pins. The IO portion of the table was revised to state that unused I/O pins are
disabled by Libero IDE software and include a weak pull-up resistor (SAR 26890).
Information was added regarding behavior of used I/O pins during power-up.
5-5
The type for "EMC_RW_N" was changed from In/out to Out (SAR 25113). 5-10
A note was added to the "Analog Front-End (AFE)" table stating that unused analog
inputs should be grounded (SAR 26744).
5-12
The "288-Pin CSP" section is new, with pin tables for A2F200 and A2F500 (SAR
27044).
5-16
The "256-Pin FBGA" pin table was replaced and now includes "Handling When
Unused" information (SAR 27709).
5-40
Revision Changes Page
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 6-5
Revision 2
(May 2010)
Embedded nonvolatile flash memory (eNVM) was changed from "64 to 512 Kbytes" to
"128 to 512 Kbytes" in the "Microcontroller Subsystem (MSS)" section and
"SmartFusion Family Product Table" (SAR 26005).
I, II
The main oscillator range of values was changed to "32 KHz to 20 MHz" in the
"Microcontroller Subsystem (MSS)" section and the "SmartFusion Family Product
Table" (SAR 24906).
I, II
The value for tPD was changed from 50 ns to 15 ns for the high-speed voltage
comparators listed in the "Analog Front-End (AFE)" section (SAR 26005).
I
The number of PLLs for A2F200 was changed from 2 to 1 in the "SmartFusion Family
Product Table" (SAR 25093).
II
Values for direct analog input, total analog input, and total I/Os were updated for the
FG256 package, A2F060, in the "Package I/Os: MSS + FPGA I/Os" table. The Max.
column was removed from the table (SAR 26005).
III
The Speed Grade section of the "Product Ordering Codes" table was revised
(SAR 25257).
VI
Revision 1
(March 2010)
The "Product Ordering Codes" table was revised to add "blank" as an option for lead-
free packaging and application (junction temperature range).
VI
Table 2-3 • Recommended Operating Conditions was revised. Ta (ambient
temperature) was replaced with TJ (junction temperature).
2-3
PDC5 was deleted from Table 2-14 • Different Components Contributing to the Static
Power Consumption in SmartFusion Devices.
2-13
The formulas in the footnotes for Table 2-28 • I/O Weak Pull-Up/Pull-Down
Resistances were revised.
2-27
The values for input biased current were revised in Table 2-91 • Current Monitor
Performance Specification.
2-75
Revision 0
(March 2010)
The "Analog Front-End (AFE)" section was updated to change the throughput for 10-
bit mode from 600 Ksps to 550 Ksps.
I
The A2F060 device was added to product information tables. N/A
The "Product Ordering Codes" table was updated to removed Std. speed and add
speed grade 1. Pre-production was removed from the application ordering code
category.
VI
The "SmartFusion Block Diagram" was revised. IV
The "Datasheet Categories" section was updated, referencing the "SmartFusion Block
Diagram" table, which is new.
1-4, IV
The "VCCI" parameter was renamed to "VCCxxxxIOBx."
"Advanced I/Os" were renamed to "FPGA I/Os."
Generic pin names that represent multiple pins were standardized with a lower case x
as a placeholder. For example, VAREFx designates VAREF0, VAREF1, and VAREF2.
Modes were renamed as follows:
Operating mode was renamed to SoC mode.
32KHz Active mode was renamed to Standby mode.
Battery mode was renamed to Time Keeping mode.
Table entries have been filled with values as data has become available.
N/A
Revision Changes Page
Datasheet Information
6-6 Revision 6
Revision 0
(continued)
Table 2-1 • Absolute Maximum Ratings, Table 2-2 • Analog Maximum Ratings, and
Table 2-3 • Recommended Operating Conditions were revised extensively.
2-1
through
2-3
Device names were updated in Table 2-6 • Package Thermal Resistance.2-7
Table 2-8 • Quiescent Supply Current Characteristics was revised extensively. 2-10
Table 2-10 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software
Settings was revised extensively.
2-11
Removed "Example of Power Calculation." N/A
Table 2-13 • Different Components Contributing to Dynamic Power Consumption in
SmartFusion Devices was revised extensively.
2-12
Table 2-14 • Different Components Contributing to the Static Power Consumption in
SmartFusion Devices was revised extensively.
2-13
The "Power Calculation Methodology" section was revised. 2-14
Table 2-81 • Electrical Characteristics of the RC Oscillator was revised extensively. 2-61
Table 2-83 • Electrical Characteristics of the Low Power Oscillator was revised
extensively.
2-62
The parameter tRSTBQ was changed to TC2CWRH in Tabl e 2 - 85 • RA M 4K9 .2-68
The 12-bit mode row for integral non-linearity was removed from Table 2-93 • ADC
Specifications. The typical value for 10-bit mode was revised. The table note was
punctuated correctly to make it clear.
2-77
Figure 37-34 • Write Access after Write onto Same Address, Figure 37-34 • Read
Access after Write onto Same Address, and Figure 37-34 • Write Access after Read
onto Same Address were deleted.
N/A
Table 2-97 • Voltage Regulator was revised extensively. 2-84
The "Serial Peripheral Interface (SPI) Characteristics" section and "Inter-Integrated
Circuit (I2C) Characteristics" section are new.
2-86,
2-88
"SmartFusion Development Tools" section was replaced with new content. 3-1
The pin description tables were revised by adding additional pins to reflect the pinout
for A2F500.
5-1
through
5-14
The descriptions for "GNDSDD1" and "VCC33SDD1" were revised. 5-1, 5-2
The description for "VCC33A" was revised. 5-2
The pin tables for the "256-Pin FBGA" and "484-Pin FBGA" were replaced with tables
that compare pin functions across densities for each package.
5-40
Revision Changes Page
SmartFusion Intelligent Mixed Signal FPGAs
Revision 6 6-7
Draft B
(December 2009)
The "Digital I/Os" section was renamed to the "I/Os and Operating Voltage" section
and information was added regarding digital and analog VCC.
I
The "SmartFusion Family Product Table" and "Package I/Os: MSS + FPGA I/Os"
section were revised.
II
The terminology for the analog blocks was changed to "programmable analog,"
consisting of two blocks: the analog front-end and analog compute engine. This is
reflected throughout the text and in the "SmartFusion Block Diagram".
IV
The "Product Ordering Codes" table was revised to add G as an ordering code for
eNVM size.
VI
Timing tables were populated with information that has become available for speed
grade –1.
N/A
All occurrences of the VMV parameter were removed. N/A
The SDD[n] voltage parameter was removed from Table 2-2 • Analog Maximum
Ratings.
2-2
Table 36-4 • Flash Programming Limits – Retention, Storage and Operating
Temperature was replaced with Table 2-4 • FPGA and Embedded Flash
Programming, Storage and Operating Limits.
2-4
The "Thermal Characteristics" section was revised extensively. 2-7
Table 2-8 • Quiescent Supply Current Characteristics was revised significantly. 2-10
Table 2-13 • Different Components Contributing to Dynamic Power Consumption in
SmartFusion Devices and Table 2-14 • Different Components Contributing to the Static
Power Consumption in SmartFusion Devices were updated.
2-12
Figure 2-2 • Timing Model was updated. 2-19
The temperature associated with the reliability for LVTTL/LVCMOS in Table 2-33 • I/O
Input Rise Time, Fall Time, and Related I/O Reliability was changed from 110º to 100º.
2-29
The values in Table 2-77 • Combinatorial Cell Propagation Delays were updated. 2-57
Table 2-83 • Electrical Characteristics of the Low Power Oscillator is new. Table 2-82 •
Electrical Characteristics of the Main Crystal Oscillator was revised.
2-62
Table 2-88 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C,
VCC = 1.425 V and Table 2-89 • FlashROM Access Time, Worse Commercial Case
Conditions: TJ = 85°C, VCC = 1.425 V are new.
2-73
The performance tables in the "Programmable Analog Specifications" section were
revised, including new data available. Table 2-96 • Analog Sigma-Delta DAC is new.
2-75
The "256-Pin FBGA" table for A2F200 is new. 4-15
Revision Changes Page
Datasheet Information
6-8 Revision 6
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device, as
highlighted in the "SmartFusion Device Status" table on page III, is designated as either "Product Brief,"
"Advance," "Preliminary," or "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production. This label only applies to the
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Production
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Microsemi SoC Products Group Safety Critical, Life Support,
and High-Reliability Applications Policy
The SoC Products Group products described in this advance status document may not have completed
the SoC Products Group’s qualification process. Products may be amended or enhanced during the
product introduction and qualification process, resulting in changes in device functionality or
performance. It is the responsibility of each customer to ensure the fitness of any product (but especially
a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and
other high-reliability applications. Consult the SoC Products Group’s Terms and Conditions for specific
liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products
Group’s products is available on the SoC Products Group website at
http://www.actel.com/documents/ORT_Report.pdf. Microsemi SoC Products Group also offers a variety
of enhanced qualification and lot acceptance screening procedures. Contact your local SoC Products
Group sales office for additional reliability information.
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Corporation. All other trademarks and service marks are the property of their respective owners.
Microsemi Corporation (NASDAQ: MSCC) offers the industry’s most comprehensive portfolio of
semiconductor technology. Committed to solving the most critical system challenges, Microsemi’s
products include high-performance, high-reliability analog and RF devices, mixed signal integrated
circuits, FPGAs and customizable SoCs, and complete subsystems. Microsemi serves leading
system manufacturers around the world in the defense, security, aerospace, enterprise,
commercial, and industrial markets. Learn more at www.microsemi.com.
Microsemmi Corporate Headquarters
2381 Morse Avenue, Irvine, CA 92614
Phone: 949-221-7100·Fax: 949-756-0308
www.microsemi.com
