1MARCH 2002
CMOS SyncFIFOTM
64 x 36
IDT723611
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBIFIFO is a trademark of Integrated Device Technology, Inc.
DSC-3024/1
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEATURES:
••
••
•Free-running CLKA and CLKB may be asynchronous or coincident
(permits simultaneous reading and writing of data on a single clock
edge)
••
••
•64 x 36 storage capacity
••
••
•Synchronous data buffering from Port A to Port B
••
••
•Mailbox bypass register in each direction
••
••
•Programmable Almost-Full (AF) and Almost-Empty (AE) flags
••
••
•Microprocessor Interface Control Logic
••
••
•Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA
••
••
•Empty Flag (EF) and Almost-Empty (AE) flags synchronized by
CLKB
••
••
•Passive parity checking on each Port
••
••
•Parity Generation can be selected for each Port
••
••
•Supports clock frequencies up to 67MHz
••
••
•Fast access times of 10ns
••
••
•Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving
120-pin Thin Quad Flatpack (PF)
••
••
•Industrial temperature range (–40°°
°°
°C to +85°°
°°
°C) is available
DESCRIPTION:
The IDT723611 is a monolithic, high-speed, low-power, CMOS Synchro-
nous (clocked) FIFO memory which supports clock frequencies up to 67MHz
and has read access times as fast as 10ns. The 64 x 36 dual-port FIFO buffers
data from Port A to Port B. The FIFO has flags to indicate empty and full conditions,
and two programmable flags, Almost-Full (AF) and Almost-Empty (AE), to
indicate when a selected number of words is stored in memory. Communication
between each port can take place through two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored. Parity
is checked passively on each port and may be ignored if not desired. Parity
generation can be selected for data read from each port. Two or more devices
may be used in parallel to create wider data paths.
The IDT723611 is a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
FUNCTIONAL BLOCK DIAGRAM
Mail 2
Register
Mail 1
Register
Input
Register
Output
Register
Write
Pointer Read
Pointer
Status Flag
Logic
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Reset
Logic
RST
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
MBF1
EF
AE
B
0
- B
35
FF
AF
FS
0
FS
1
Programmable
Flag Offset
Registers
A
0
- A
35
Parity
Gen/Check
Parity
Generation
FIFO
ODD/
EVEN
Parity
Gen/Check
PGB
PEFB
36
RAM
ARRAY
64 x 36
3024 drw 01
PGA
PEFA
MBF2
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723611
CMOS SyncFIFOTM 64 x 36
64 x 36
DESCRIPTION (CONTINUED)
NOTE:
1. NC = No internal connection
TQFP (PN120-1, order code: PF)
TOP VIEW
PIN CONFIGURATIONS
3024 drw 02
A
23
A
22
A
21
GND
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
GND
A
9
A
8
A
7
V
CC
A
6
A
5
A
4
A
3
GND
A
2
A
1
A
0
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
22
B
21
GND
B
20
B
19
B
18
B
17
B
16
B
15
B
14
B
13
B
12
B
11
B
10
GND
B
9
B
8
B
7
V
CC
B
6
B
5
B
4
B
3
GND
B
2
B
1
B
0
EF
AE
NC
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
AF
FF
CSA
ENA
CLKA
W/RA
V
CC
PGA
PEFA
MBF2
MBA
FS
1
FS
0
ODD/EVEN
RST
GND
NC
NC
NC
NC
MBB
MBF1
PEFB
PGB
V
CC
W/RB
CLKB
ENB
CSB
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60 91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92 B
23
A
24
A
25
A
26
V
CC
A
27
A
28
A
29
GND
A
30
A
31
A
34
A
35
B
35
GND
B
34
B
33
B
32
B
30
B
31
GND
B
29
B
28
B
27
V
CC
B
26
B
25
B
24
A
32
A
33
The Full Flag (FF) and Almost-Full (AF) flag of the FIFO are two-stage
synchronized to the port clock that writes data into its array (CLKA). The Empty
Flag (EF) and Almost-Empty (AE) flag of the FIFO are two-stage synchronized
to the port clock that reads data from its array.
The IDT723611 is characterized for operation from 0°C to 70°C.
3
IDT723611
CMOS SyncFIFOTM 64 x 36 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
GND
AE
EF
B
0
B
1
B
2
GND
B
3
B
4
B
5
B
6
V
CC
B
7
B
8
B
9
GND
B
10
B
11
V
CC
B
12
B
13
B
14
GND
B
15
B
16
B
17
B
18
B
19
B
20
GND
B
21
B
22
B
23
GND
NC
NC
A
0
A
1
A
2
GND
A
3
A
4
A
5
A
6
V
CC
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
13
A
14
GND
A
15
A
16
A
17
A
18
A
19
A
20
GND
A
21
A
22
A
23
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
3024 drw 03
117
17
16
15
14
13
12
11
10
9
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
V
CC
V
CC
A
24
A
25
A
26
A
27
GND
A
28
A
29
V
CC
A
30
A
31
A
32
GND
A
33
A
34
A
35
GND
B
35
B
34
B
33
GND
B
32
B
31
B
30
V
CC
B
29
B
28
B
27
GND
B
26
B
25
B
24
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83 NC
AF
FF
CSA
ENA
CLKA
W/RA
V
CC
PGA
FS
0
ODD/EVEN
FS
1
PEFA
MBF2
RST
NC
GND
NC
NC
NC
MBF1
GND
PEFB
V
CC
W/RB
CLKB
ENB
CSB
NC
GND
MBA
MBB
PGB
8
PQFP (PQ132-1, order code: PQF)
TOP VIEW
*
*Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PIN CONFIGURATIONS (CONTINUED)
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723611
CMOS SyncFIFOTM 64 x 36
64 x 36
Symbol Name I/O Description
A0-A35 Port-A Data I/O 36-bit bidirectional data port for side A.
AE Almost-Empty Flag O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in the
FIFO is less than or equal to the value in the offset register, X.
AF Almost-Full Flag O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of emptylocations
in the FIFO is less than or equal to the value in the Offset register, X.
B0-B35 Port-B Data. I/O 36-bit bidirectional data port for side B.
CLKA Port-A Clock I CLKA is a continuous clock that synchronizes all data transfers through port-A and can be asynchron-
ous or coincident to CLKB. FF and AF are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB Port-B Clock I CLKB is a continuous clock that synchronizes all data transfers through port-B and can be asynchron-
ous or coincident to CLKA. EF and AE are synchronized to the LOW-to-HIGH transition of CLKB.
CSA Port-A Chip Select I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The
A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB Port-B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The
B0-B35 outputs are in the high-impedance state when CSB is HIGH.
EF Empty Flag O EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW, the FIFO is empty, and
reads from its memory are disabled. Data can be read from the FIFO to its output register when EF is
HIGH. EF is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH
transition of CLKB after data is loaded into empty FIFO memory.
ENA Port-A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
ENB Port-B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
FF Full Flag O FF is synchronized to the LOW-to-HIGH/ transition of CLKA. When FF is LOW, the FIFO is full, and
writes to its memory are disabled. FF is forced LOW when the device is reset and is set HIGH by the
second LOW-to-HIGH transition of CLKA after reset.
FS1, FS0 Flag-Offset Selects I The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which loads one of four
preset values into the Almost-Full and Almost-Empty Offset register (X).
MB A Port-A Mailbox Select I A HIGH level on MBA chooses a mailbox register for a port-A read or write operation.
MB B Port-B Mailbox Select I A HIGH level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output, and a
LOW level selects the FIFO output register data for output.
MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.Writes to
the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH
transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH when the
device is reset.
MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.Writes to
the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of
CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset.
ODD/ Odd/Even Parity I Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
EVEN Select ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity
generation is enabled for a read operation.
PEFA Port-A Parity Error O When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as
Flag (Port A) A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity
bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity genera-
tion is selected by PGA. Therefore, if a mail2 read with parity generation is setup by having CSA
LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless
of the state of A0-A35 inputs.
PEFB Port-B Parity Error O When any byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as
Flag (Port B) B0-B8, B9-B17, B18-B26, B27-B35, with the most significant bit of each byte serving as the
parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity
trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity
generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having
CSB LOW, ENB HIGH, W/RB LOW, MBB HIGH, and PGB HIGH, the PEFB flag is forced HIGH
regardless of the state of the B0-B35 inputs
PIN DESCRIPTION
5
IDT723611
CMOS SyncFIFOTM 64 x 36 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION (Continued)
Symbol Name I/O Description
PG A Port-A Parity I Parity is generated for mail2 register reads from port A when PGA is HIGH. The type of parity generated
Generation is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26, and
A27-A35. The generated parity bits are output in the most significant bit of each byte.
PGB Port-B Parity I Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected
Generation by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35.
The generated parity bits are output in the most significant bit of each byte.
RST Reset I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the EF, AE, and FF flags
LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select Almost-
Full and Almost-Empty flag offset.
W/RA Port-A Write/Read I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
Select transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA isHIGH.
W/RB Port-B Write/Read I A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH
Select transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723611
CMOS SyncFIFOTM 64 x 36
64 x 36
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol Rating Commercial Unit
VCC Supply Voltage Range –0.5 to 7 V
VI(2) Input Voltage Range –0.5 to VCC+0.5 V
VO(2) Output Voltage Range –0.5 to VCC+0.5 V
IIK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA
IOK Output Clamp Current, (VO = < 0 or VO > VCC) ±50 mA
IOUT Continuous Output Current, (VO = 0 to VCC) ±50 mA
ICC Continuous Current Through VCC or GND ±500 mA
TSTG Storage Temperature Range –65 to 150 °C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. All typical values are at VCC = 5V, TA = 25°C.
3. For additional ICC information, see the following page.
IDT723611
Commercial & Industrial(1)
tA = 15, 20 ns
Parameter Test Conditions Min. Typ. (2) Max. Unit
VOH VCC = 4.5V, IOH = –4 mA 2.4 — — V
VOL VCC = 4.5V, IOL = 8 mA — — 0.5 V
ILI VCC = 5.5V, VI = VCC or 0 — — ±50 µA
ILO VCC = 5.5V, VO = VCC or 0 — — ±50 µA
ICC(3) VCC = 5.5V, IO = 0 mA, VI = VCC or GND Outputs HIGH — — 60 mA
Outputs LOW — — 130
Outputs Disabled — — 60
CIN VI = 0, f = 1 MHz — 4 — pF
COUT VO = 0, f = 1 MHZ — 8 — pF
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
RECOMMENDED OPERATING
CONDITIONS
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
VIH High-Level Input Voltage 2 — V
VIL Low-Level Input Voltage — 0.8 V
IOH High-Level Output Current — –4 mA
IOL Low-Level Output Current — 8 mA
TAOperating Free-Air Temperature 0 70 °C
7
IDT723611
CMOS SyncFIFOTM 64 x 36 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
CALCULATING POWER DISSIPATION
The ICC(f) data for the graph was taken while simultaneously reading and writing the FIFO on the IDT723611 with CLKA and CLKB operating at
frequency fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were discon-
nected to normalize the graph to a zero-capacitance load. Once the capacitance load per data-output channel is known, the power dissipation can be
calculated with the equation below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT723611 may be calculated by:
PT = VCC x ICC(f) +
Σ
(CL x VOH - VOL)2 X fO)
where:
CL= output capacitance load
fO= switching frequency of an output
VOH = output high-level voltage
VOL = output low-level voltage
When no read or writes are occurring on this device, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculated by: PT = VCC x fS x 0.290 mA/MHz
Figure 1. Typical Characteristics: Supply Current vs Clock Frequency
010203040506070
0
50
100
150
200
250
300
350
400
VCC = 5.0V
fdata = 1/2 fS
CL = 0 pF
80
VCC = 4.5V
VCC = 5.5V
3024 drw 04
TA = 25°C
Icc(f) Supply Current mA
fclock Clock Frequency MHz
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723611
CMOS SyncFIFOTM 64 x 36
64 x 36
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURES
Commercial Com'l & Ind'l(1)
IDT723611L15 IDT723611L20
Symbol Parameter Min. Max. Min. Max. Unit
fSClock Frequency, CLKA or CLKB – 66.7 – 50 MHz
tCLK Clock Cycle Time, CLKA or CLKB 15 – 20 – MHz
tCLKH Pulse Duration, CLKA or CLKB HIGH 6 – 8 – n s
tCLKL Pulse Duration, CLKA or CLKB LOW 6 – 8 – n s
tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑4–5–ns
tENS1 CSA, W/RA, before CLKA↑; CSB, W/RB before CLKB↑6–6–ns
tENS2 ENA before CLKA↑; ENB before CLKB↑4–5–ns
tENS3 MBA before CLKA↑; ENB before CLKB↑4–5–ns
tPGS Setup Time, ODD/EVEN and PGB before CLKB↑(1) 4–5–ns
tRSTS Setup Time, RST LOW before CLKA↑ or CLKB↑(2) 5–6–ns
tFSS Setup Time, FS0 and FS1 before RST HIGH 5 – 6 – n s
tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑1–1–ns
tENH1 CSA, W/RA after CLKA↑; CSB, W/RB after CLKB↑1–1–ns
tENH2 ENA after CLKA↑; ENB after CLKB↑1–1–ns
tENH3 MBA after CLKA↑; MBB after CLKB↑1–1–ns
tPGH Hold TIme, ODD/EVEN and PGB after CLKB↑(2) 0–0–ns
tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑(3) 6–6–ns
tFSH Hold Time, FS0 and FS1 after RST HIGH 4 – 4 – n s
tSKEW1(4) Skew Time, between CLKA↑ and CLKB↑ for EF, FF 8–8–ns
tSKEW2(4) Skew Time, between CLKA↑ and CLKB↑ for AE, AF 14 – 16 – ns
NOTES:
1. Industrial Temperature Range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Only applies for a rising edge of CLKB that does a FIFO read.
3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
9
IDT723611
CMOS SyncFIFOTM 64 x 36 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 PF
Commercial Com'l & Ind'l(1)
IDT723611L15 IDT723611L20
Symbol Parameter Min. Max. Min. Max. Unit
fSClock Frequency, CLKA or CLKB – 66.7 – 50 MH z
tAAccess Time, CLKB↑ to B0-B35 2 10 2 12 ns
tWFF Propagation Delay Time, CLKA↑ to FF 210212ns
tREF Propagation Delay Time, CLKB↑ to EF 210212ns
tPAE Propagation Delay Time, CLKB↑ to AE 210212ns
tPAF Propagation Delay Time, CLKA↑ to AF 210212ns
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑19112ns
to MBF2 LOW or MBF1 HIGH
tPMR Propagation Delay Time, CLKA↑ to B0-B35(2) and CLKB↑ to A0-A35(3) 312314ns
tMDV Propagation Delay Time, MBB to B0-B35 Valid 1 11 1 11.5 n s
tPDPE Propagation Delay Time, A0-A35 Valid to PEFA Valid; B0-B35 Valid to 3 12 3 13 ns
PEFB Valid
tPOPE Propagation Delay Time, ODD/EVEN to PEFA and PEFB 311312ns
tPOPB(4) Propagation Delay Time, ODD/EVEN to Parity Bits (A8, A17, A26, A35) and 2 12 2 13 n s
(B8, B17, B26, B35)
tPEPE Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB,112113ns
ENB, W/RB, MBB, or PGB to PEFB
tPEPB(4) Propagation Delay Time, CSA, ENA W/RA, MBA, or PGA to Parity Bits (A8, A17, 3 14 3 15 ns
A26, A35); CSB, ENB, W/RB, MBB, or PGB to ParityBits (B8, B17, B26, B35)
tRSF Propagation Delay Time, RST to AE LOW and (AF, MBF1, MBF2) HIGH 1 15 1 20 n s
tEN Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB210212ns
HIGH to B0-B35 Active
tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH 1 9 1 10 ns
or W/RB LOW to B0-B35 at high impedance
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3 Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Only applies when reading data from a mail register.
(Commercial: VCC = 5.0V ±10%, T A = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723611
CMOS SyncFIFOTM 64 x 36
64 x 36
SIGNAL DESCRIPTION
RESET ( RST )
The IDT723611 is reset by taking the Reset (RST) input LOW for at least
four port-A clock (CLKA) and four port-B clock (CLKB) LOW-to-HIGH transi-
tions. The reset input can switch asynchronously to the clocks. A device reset
initializes the internal read and write pointers of the FIFO and forces the Full Flag
(FF) LOW, the Empty Flag (EF) LOW, the Almost-Empty flag (AE) LOW, and the
Almost-Full flag (AF) HIGH. A reset also forces the Mailbox Flags (MBF1, MBF2)
HIGH. After a reset, FF is set HIGH after two LOW-to-HIGH transitions of CLKA.
The device must be reset after power up before data is written to its memory.
A LOW-to-HIGH transition on the RST input loads the Almost-Full and Almost-
Empty Offset register (X) with the value selected by the Flag Select (FS0, FS1)
inputs. The values that can be loaded into the register are shown in Table 1.
FIFO WRITE/READ OPERATION
The state of the port-A data (A0-A35) outputs is controlled by the port-A Chip
Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35 outputs
are in the high-impedance state when either CSA or W/RA is HIGH. The A0-
A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into
the FIFO from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when
CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FF is HIGH (see
Table 2).
The port-B control signals are identical to those of port A. The state of the
port-B data (B0-B35) outputs is controlled by the port-B Chip Select (CSB) and
the port-B Write/Read select (W/RB). The B0-B35 outputs are in the high-
impedance state when either CSB or W/RB is HIGH. The B0-B35 outputs are
active when both CSB and W/RB are LOW. Data is read from the FIFO to the
B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB
is LOW, ENB is HIGH, MBB is LOW, and EF is HIGH (see Table 3).
The setup and hold-time constraints to the port clocks for the port Chip
Selects (CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling
write and read operations and are not related to HIGH-impedance control of
the data outputs. If a port enable is LOW during a clock cycle, the port’s Chip
Select and Write/Read select can change states during the setup and hold-time
window of the cycle.
SYNCHRONIZED FIFO FLAGS
Each FIFO flag is synchronized to its port clock through two flip-flop stages.
This is done to improve the flags’ reliability by reducing the probability of
mestastable events on their outputs when CLKA and CLKB operate asynchro-
nously to one another. FF and AF are synchronized to CLKA. EF and AE are
synchronized to CLKB. Table 4 shows the relationship to the flags to the FIFO.
CSB W/RB ENB MBB CLKB B0-B35 Outputs Port Functions
H X X X X In High-Impedance State None
L H L X X In High-Impedance State None
LHHL↑In High-Impedance State None
LHHH↑In High-Impedance State Mail2 Write
L L L L X Active, FIFO Output Register None
LLHL↑Active, FIFO Output Register FIFO Read
L L L H X Active, Mail1 Register None
LLHH↑Active, Mail1 Register Mail1 Read (set MBF1 HIGH)
CSA W/RA ENA MBA CLKA A0-A35 Outputs Port Functions
H X X X X In High-Impedance State None
L H L X X In High-Impedance State None
LHHL↑In High-Impedance State FIFO Write
LHHH↑In High-Impedance State Mail1 Write
L L L L X Active, Mail2 Register None
LLHL↑Active, Mail2 Register None
L L L H X Active, Mail2 Register None
LLHH↑Active, Mail2 Register Mail2 Read (set MBF2 HIGH)
Almost-Full and
Almost-Empty Flag FS1 FS0 RST
Offset Register (X)
16 H H ↑
12 H L ↑
8LH↑
4LL↑
TABLE 1 FLAG PROGRAMMING
TABLE 2 PORT-A ENABLE FUNCTION TABLE
TABLE 3 PORT-B ENABLE FUNCTION TABLE
11
IDT723611
CMOS SyncFIFOTM 64 x 36 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
write pointer and read pointer comparator that indicates when the FIFO SRAM
status is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty
state is defined by the value of the Almost-Full and Almost-Empty Offset register
(X). This register is loaded with one of four preset values during a device reset
(see reset above). The AE flag is LOW when the FIFO contains X or less words
in memory and is HIGH when the FIFO contains (X+1) or more words.
Two LOW-to-HIGH transitions on the port-B clock (CLKB) are required
after a FIFO write for the
AE
flag to reflect the new level of fill. Therefore, the
AE
flag of a FIFO containing (X+1) or more words remains LOW if two CLKB
cycles have not elapsed since the write that filled the memory to the (X+1) level.
The
AE
flag is set HIGH by the second CLKB LOW-to-HIGH transition after the
FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition on
CLKB begins the first synchronization cycle if it occurs at time t
SKEW2
or greater
after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent CLKB
cycle can be the first synchronization cycle (see Figure 7).
ALMOST-FULL FLAG ( AF )
The FIFO Almost-Full flag is synchronized to the port clock that writes
data to its array (CLKA). The state machine that controls an AF flag monitors
a write pointer and read pointer comparator that indicates when the FIFO SRAM
status is almost-full, almost- full-1, or almost-full-2. The almost-full state is defined
by the value of the Almost-Full and Almost-Empty Offset register (X). This register
is loaded with one of four preset values during a device reset (see reset above).
The AF flag is LOW when the FIFO contains (64-X) or more words in memory
and is HIGH when the FIFO contains [64-(X+1)] or less words.
Two LOW-to-HIGH transitions on the port-A clock (CLKA) are required
after a FIFO read for the AF flag to reflect the new level of fill. Therefore, the
AF flag of a FIFO containing [64-(X+1)] or less words remains LOW if two CLKA
cycles have not elapsed since the read that reduced the number of words in
memory to [64-(X+1)]. The AF flag is set HIGH by the second CLKA LOW-to-
HIGH transition after the FIFO read that reduces the number of words in memory
to [64-(X+1)]. A LOW-to-HIGH transition on CLKA begins the first synchroni-
zation cycle if it occurs at time tSKEW2 or greater after the read that reduces the
number of words in memory to [64-(X+1)]. Otherwise, the subsequent CLKA
cycle can be the first synchronization cycle (see Figure 8).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT723611 to pass command and
control information between port A and port B. The Mailbox select (MBA, MBB)
inputs choose between a mail register and a FIFO for a port data transfer
operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1
register when port-A write is selected by CSA, W/RA, and ENA with MBA HIGH.
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register
when port-B write is selected by CSB, W/RB, and ENB with MBB HIGH. Writing
data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW.
Attempted writes to a mail register are ignored while its mail flag is LOW.
When the port-B data (B0-B35) outputs are active, the data on the bus
comes from the FIFO output register when the port-B Mailbox select (MBB)
input is LOW and from the mail1 register when MBB is HIGH. Mail2 data is always
present on the port-A data (A0-A35) outputs when they are active. The Mail1
Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when
a port-B read is selected by CSB, W/RB, and ENB with MBB HIGH. The Mail2
Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when
a port-A read is selected by CSA, W/RA, and ENA with MBA HIGH. The data
in a mail register remains intact after it is read and changes only when new data
is written to the register.
EMPTY FLAG ( EF )
The FIFO Empty Flag is synchronized to the port clock that reads data from
its array (CLKB). When the EF is HIGH, new data can be read to the FIFO output
register. When the EF is LOW, the FIFO is empty and attempted FIFO reads
are ignored.
The FIFO read pointer is incremented each time a new word is clocked
to its output register. The state machine that controls an EF monitors a write
pointer and read pointer comparator that indicates when the FIFO SRAM
status is empty, empty+1, or empty+2. A word written to the FIFO can be read
to the FIFO output register in a minimum of three port-B clock (CLKB) cycles.
Therefore, an EF is LOW if a word in memory is the next data to be sent to the
FIFO output register and two CLKB cycles have not elapsed since the time the
word was written. The EF of the FIFO is set HIGH by the second LOW-to-HIGH
transition of CLKB, and the new data word can be read to the FIFO output register
in the following cycle.
A LOW-to-HIGH transition on CLKB begins the first synchronized cycle of
a write if the clock transition occurs at time t
SKEW1
or greater after the write.
Otherwise, the subsequent CLKB cycle can be the first synchronization cycle
(see Figure 5).
FULL FLAG ( FF )
The FIFO Full Flag is synchronized to the port clock that writes data to
its array (CLKA). When the FF is HIGH, an SRAM location is free to receive
new data. No memory locations are free when the FF is LOW and attempted
writes to the FIFO are ignored.
Each time a word is written to the FIFO, its write pointer is incremented. The
state machine that controls the FF monitors a write pointer and read pointer
comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From
the time a word is read from the FIFO, its previous memory location is ready
to be written in a minimum of three port-A clock cycles. Therefore, a FF is LOW
if less than two CLKA cycles have elapsed since the next memory write location
has been read. The second LOW-to-HIGH transition on CLKA after the read
sets the FF HIGH and data can be written in the following clock cycle.
A LOW-to-HIGH transition on CLKA begins the first synchronization cycle
of a read if the clock transition occurs at time tSKEW1 or greater after the read.
Otherwise, the subsequent clock cycle can be the first synchronization cycle (see
Figure 6).
ALMOST-EMPTY FLAG ( AE )
The FIFO Almost-Empty flag is synchronized to the port clock that reads data
from its array (CLKB). The state machine that controls the AE flag monitors a
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag register.
TABLE 4 FIFO FLAG OPERATION
EF AE AF FF
0LLHH
1 to X H L H H
(X+1) to [64-(X+1)] H H H H
(64-X) to 63 H H L H
64 H H L L
Number of Words
in the FIFO
Synchronized
to CLKB Synchronized
to CLKA
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723611
CMOS SyncFIFOTM 64 x 36
64 x 36
Figure 2. Device Reset Loading the X Register with the Value of Eight
PARITY CHECKING
The port-A (A0-A35) inputs and port-B (B0-B35) inputs each have four
parity trees to check the parity of incoming (or outgoing) data. A parity failure
on one or more bytes of the input bus is reported by a LOW level on the port
Parity Error Flag (PEFA, PEFB). Odd or even parity checking can be selected,
and the Parity Error Flags can be ignored if this feature is not desired.
Parity status is checked on each input bus according to the level of the Odd/
Even parity (ODD/EVEN) select input. A parity error on one or more bytes of
a port is reported by a LOW level on the corresponding port Parity Error Flag
(PEFA, PEFB) output. Port-A bytes are arranged as A0-A8, A9-A17, A18-A26,
and A27-A35, and port-B bytes are arranged as B0-B8, B9-B17, B18-B26,
and B27-B35. When Odd/Even parity is selected, a port Parity Error Flag
(PEFA, PEFB) is LOW if any byte on the port has an odd/even number of LOW
levels applied to its bits.
The four parity trees used to check the A0-A35 inputs are shared by the
mail2 register when parity generation is selected for port-A reads (PGA=HIGH).
When port-A read from the mail2 register with parity generation is selected with
CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port-A
Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to the
A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are
shared by the mail1 register when parity generation is selected for port-B reads
(PGB=HIGH). When a port-B read from the mail1 register with parity generation
is selected with CSB LOW, ENB HIGH, W/RB LOW, MBB HIGH, and PGB HIGH,
the port-B Parity Error Flag (PEFB) is held HIGH regardless of the levels applied
to the B0-B35 inputs.
PARITY GENERATION
A HIGH level on the port-A Parity Generate select (PGA) or port-B Parity
Generate select (PGB) enables the IDT723611 to generate parity bits for port
reads from a FIFO or mailbox register. Port-A bytes are arranged as A0-A8,
A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte used
as the parity bit. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26, and
B27-B35, with the most significant bit of each byte used as the parity bit. A write
to a FIFO or mail register stores the levels applied to all thirty-six inputs
regardless of the state of the Parity Generate select (PGA, PGB) inputs. When
data is read from a port with parity generation selected, the lower eight bits of
each byte are used to generate a parity bit according to the level on the ODD/
EVEN select. The generated parity bits are substituted for the levels originally
written to the most significant bits of each byte as the word is read to the data
outputs.
Parity bits for FIFO data are generated after the data is read from SRAM
and before the data is written to the output register. Therefore, the port-B Parity
Generate select (PGB) and ODD/EVEN have setup and hold time constraints
to the port-B clock (CLKB) for a rising edge of CLKB used to read a new word
to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the
port-B bus (B0-B35) to check parity and the circuit used to generate parity
for the mail2 data is shared by the port-A bus (A0-A35) to check parity. The
shared parity trees of a port are used to generate parity bits for the data in
a mail register when the port Write/Read select (W/RA, W/RB) input is LOW, the
port Mail select (MBA, MBB) input is HIGH, Chip Select (CSA, CSB) is LOW,
Enable (ENA, ENB) is HIGH, and the port Parity Generate select (PGA, PGB)
is HIGH. Generating parity for mail register data does not change the contents
of the register.
CLKA
RST
FF
AE
AF
MBF1,
MBF2
CLKB
EF
FS1,FS0
t
RSTS
t
RSTH
t
FSH
t
FSS
t
WFF
t
WFF
t
PAE
0,1
t
PAF
t
RSF
t
REF
3024drw 05
13
IDT723611
CMOS SyncFIFOTM 64 x 36 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 3. FIFO Write Cycle Timing
CLKA
FF
ENA
MBA
CSA
W/RA
t
CLKH
t
CLKL
t
CLK
t
ENS1
t
ENS1
t
ENS3
t
ENS2
t
ENH1
t
ENH1
t
ENH3
t
ENH2
t
ENS2
t
ENH2
PEFA
A0 - A35
t
DS
t
DH
W1 W2
ODD/
EVEN
Valid
Valid
t
PDPE
t
PDPE
3024 drw 06
No Operation
t
ENH2
t
ENS2
Figure 4. FIFO Read Cycle Timing
3024 drw 07
CLKB
EF
ENB
B0 - B35
MBB
CSB
W/RB
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
MDV
t
EN
t
A
t
A
t
ENH2
t
ENS2
t
ENH2
t
ENS2
t
ENH2
t
DIS
No Operation
HIGH
PGB,
ODD/
EVEN
Previous Data Word 1 Word 2
t
PGS
t
PGH
t
PGS
t
PGH
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723611
CMOS SyncFIFOTM 64 x 36
64 x 36
Figure 5.
EF
Flag Timing and First Data Read when the FIFO is Empty
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
CSA
WRA
MBA
FFA
A0 - A35
CLKB
EF
CSB
W/RB
MBB
ENA
CLKA
12
t
CLKH
t
CLKL
t
CLK
t
ENS3
t
ENS2
t
ENH3
t
ENH2
t
DS
t
DH
t
SKEW1
(1) t
CLK
t
CLKL
t
REF
t
REF
t
ENS2
t
ENH2
t
A
W1
Empty FIFO
LOW
HIGH
LOW
LOW
LOW
t
CLKH
W1
HIGH
3024 drw 08
B0 - B35
ENB
15
IDT723611
CMOS SyncFIFOTM 64 x 36 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 7. Timing for
AE
when the FIFO is Almost-Empty
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.
Figure 6.
FF
Flag Timing and First Available Write when the FIFO is Full
CSB
EFB
W/RB
MBB
ENB
B0 - B35
CLKB
FF
CLKA
CSA
WRA
12
MBA
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH2
t
A
t
SKEW1
(1)
t
CLK
t
CLKH
t
CLKL
t
WFF
t
ENS3
t
ENS2
t
DS
t
ENH3
t
ENH2
t
DH
Previous Word in FIFO Output Register Next Word From FIFO
LOW
LOW
LOW
HIGH
LOW
HIGH
FIFO Full t
WFF
3024 drw 09
ENA
A0 - A35
AE
CLKA
ENB
ENA
CLKB 2
1
t
ENS2
t
ENH2
t
SKEW2
(1)
t
PAE
t
PAE
t
ENS2
t
ENH2
X Word in FIFO
(X+1) Words in FIFO
3024 drw 10
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723611
CMOS SyncFIFOTM 64 x 36
64 x 36
Figure 8. Timing for
AF
when the FIFO is Almost-Full
Figure 9. Timing for Mail1 Register and
MBF1
Flag
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
NOTE:
1 . Port-B parity generation off (PGB = L)
AF
CLKA
ENB
ENA
CLKB
1
tSKEW2
(1)
tENS2 tENH2
tPAF
tENS2 tENH2
tPAF
[64-(X+1)] Words in FIFO (64-X) Words in FIFO
3024 drw 11
2
CLKA
ENA
A0 - A35
MBA
CSA
W/RA
CLKB
MBF1
CSB
MBB
ENB
B0 - B35
W/RB
W1
t
ENS1
t
ENH1
t
DS
t
DH
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS2
t
ENH2
t
DIS
W1 (Remains valid in Mail1 Register after read)FIFO Output Register
t
ENS1
t
ENH1
t
ENS1
t
ENH1
t
ENS1
t
ENH1
3024 drw 12
17
IDT723611
CMOS SyncFIFOTM 64 x 36 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 10. Timing for Mail2 Register and
MBF2
Flag
Figure 11. ODD/
EVEN
, W/
R
A, MBA, and PGA to
PEFA
Timing
NOTE:
1. CSA = L and ENA = H.
3024 drw 13
CLKB
ENB
B0 - B35
MBB
CSB
W/RB
CLKA
MBF2
CSA
MBA
ENA
A0 - A35
W/RA
W1
t
ENS1
t
ENH1
t
DS
t
DH
t
PMF
t
PMF
t
ENS2
t
ENH2
t
DIS
t
EN
t
PMR
W1 (Remains valid in Mail2 Register after read)
t
ENS1
t
ENH1
t
ENS1
t
ENH1
t
ENS1
t
ENH1
3024 drw 14
ODD/
EVEN
PEFA
PGA
MBA
W/RA
Valid Valid Valid Valid
t
POPE
t
PEPE
t
POPE
t
PEPE
NOTE:
1 . Port-A parity generation off (PGA = L)
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723611
CMOS SyncFIFOTM 64 x 36
64 x 36
Figure 14. Parity Generation Timing when reading from the Mail1 Register
Figure 13. Parity Generation Timing when reading from the Mail2 Register
NOTE:
1. ENA = H.
NOTE:
1. ENB = H.
3024 drw 16
ODD/
EVEN
A8, A17,
A26, A35
PGA
MBA
W/RA
Mail2 Data Generated Parity Generated Parity Mail2 Data
CSA LOW
t
EN
t
PEPB
t
POPB
t
PEPB
ODD/
EVEN
B8, B17,
B26, B35
PGB
MBB
W/RB
Mail1
Data
Generated Parity Generated Parity
CSB LOW
t
EN
t
PEPB
t
POPB
t
PEPB
t
MDV
3024 drw 17
Mail1 Data
NOTE:
1. CSB = L and ENB = H. Figure 12. ODD/
EVEN
,
W
/RB, MBB, and PGB to
PEFB
Timing
3024 drw 15
ODD/
EVEN
PEFB
PGB
MBB
W/RB
Valid Valid Valid Valid
t
POPE
t
PEPE
t
POPE
t
PEPE
19
IDT723611
CMOS SyncFIFOTM 64 x 36 COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NOTE:
1. Includes probe and jig capacitance.
Figure 16. Load Circuit and Voltage Waveforms
3024 drw 18
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
1.1 kΩ
5 V
680Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
GND
Timing
Input
Data,
Enable
Input
GND
3 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3 V
GND
GND
3 V
1.5 V
1.5 V
1.5 V
1.5 V
t
W
Output
Enable
Low-Level
Output
High-Level
Output
3 V
OL
GND
3 V
1.5 V 1.5 V
1.5 V
1.5 V
≈
OH
OV
≈
GND
OH
OL
1.5 V 1.5 V
1.5 V 1.5 V
Input
In-Phase
Output
High-Level
Input
Low-Level
Input
V
V
V
V
1.5 V
3 V
t
S
t
h
t
PLZ
t
PHZ
t
PZL
t
PD
t
PD
(1)
t
PZH
20
CORPORATE HEADQUARTERS for SALES: for TECH SUPPORT:
2975 Stender Way 800-345-7015 or 408-727-6116 e-mail: FIFOhelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 Phone: (408) 330-1753
www.idt.com
NOTE:
1. Industrial temperature range product for 20ns speed grade is avaiable as a standard device. All other speed grades are available by special order.
ORDERING INFORMATION
723611
3024 drw 19
XXXXXX
IDT Device Type XXXX X
Power Speed Package
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
Process/
Temperature
Range
I
(1)
Industrial (40°C to +85°C)
BLANK
PF
PQF
15
20
L
Commercial (0°C to +70°C)
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
Commercial Only
Com’l & Ind’l
Low Power
64 x 36 Synchronous FIFO
DATASHEET DOCUMENT HISTORY
03/05/2002 pgs. 1, 6, 8, 9 and 20.
