DATA SHEET R-IN32M3 Series R18DS0008EJ0500 LSI for Industrial Ethernet Dec. 28, 2018 1. Overview 1.1 Introduction Ethernet communication continues to spread rapidly in the field of industrial automation as manufacturers seek to improve the capability, efficiency, and flexibility of their organizations. Modern Industrial Ethernet applications require high-speed real-time response, low power consumption, and high performance. These requirements are not necessarily met by traditional methods such as hard-wired Ethernet processors or dedicated high-speed CPUs. Renesas R-IN32M3 series of large-scale integrated circuits (LSI) are specifically tailored to meet the demands of Industrial Ethernet applications. Key features include: * * * * * * * * * High-speed, real-time, deterministic, low-latency, low-jitter response for real-time applications Low power consumption Integrated Arm(R) Cortex(R)-M3 core for flexibility Integrated Real-Time OS Accelerator with support for ITRON version 4.0 Integrated Gigabit Ethernet MAC (R-IN32M3-CL only) Integrated 10/100Mbps EtherPHY (R-IN32M3-EC only) Dedicated, DMA controller and buffer for the network processor High performance with low CPU usage by offloading functions to Real-Time OS Accelerator Multiple timers, serial interfaces, general purpose I/O (GPIO), external memory interfaces 1.2 Product Lineup Renesas R-IN32M3 series includes the following two devices: Table1.1 R-IN32M3 Product Lineup Product name Feature EtherCAT(R) R-IN32M3-EC R-IN32M3 with built-in R-IN32M3-CL R-IN32M3 with built-in CC-Link IE Field (intelligent device station) R18DS0008EJ0500 Dec. 28, 2018 Slave Controller Page 1 of 1 R-IN32M3 Series Data Sheet 1.3 1. Overview Overview Table 1.2 Overview of R-IN32M3 (1/2) Product R-IN32M3 Item CPU cores Arm Cortex-M3 32-bit RISC CPU + Real-Time OS Accelerator (Hardware Real-Time OS, HW-RTOS) Operating frequency 100 MHz Instruction set Thumb-2 instruction Armv7-M architecture Instruction RAM 768 Kbytes (RAM with ECC) Data RAM 512 Kbytes (RAM with ECC) Buffer RAM 64 Kbytes (RAM with ECC) Internal system bus - 32-bit system bus at 100 MHz - 128-bit communication bus at 100 MHz DMA - 4 channels + 1 channel (for real-time port) Boot options - Serial flash ROM boot - Supports software and various interrupt-triggered DMA - External memory boot - External MPU boot External memory support - 16-bit or 32-bit bus interface - Page ROM / ROM / SRAM interface - Synchronous burst memory interface - Four chip selects for external SRAM - 256-Mbyte (max) external memory space - Programmable wait function External MCU Interface - 16-bit or 32-bit bus interface - General-purpose interface for static memory - Address space:2 Mbytes (instruction RAM, data RAM, register area) Serial flash ROM memory controller - Support serial interface compatible with SPI of the companies - Support direct boot from serial memory device - Support Fast Read, Fast Read Dual Output, Fast Read Dual I/O mode - Direct layout in memory space Interrupt - 29 external interrupt pins Internal peripheral circuit I/O Ports CMOS I/O: 96 pins (max.) System timers (three systems) - Internal timer of Hardware RTOS - Internal timer of CPU - 4-channel timer array - 32-bit counter & 32-bit data register - Counter by external signal Watchdog timer - 1 channel - Software-triggered start mode - Selectable operations in response to errors: - Generation of a non-maskable interrupt (NMI) - Generation of a reset R18DS0008EJ0500 Dec. 28, 2018 Page 2 of 3 R-IN32M3 Series Data Sheet 1. Overview Table 1.2 Overview of R-IN32M3 (2/2) Product R-IN32M3 Item Internal Peripherals (cont.) Asynchronous serial interface - 2 channels - Full duplex - FIFOs: 10 bits x 16 receive and 8 bits x 16 transmit - Support output of receive errors and status - Character length: 7 or 8 bits - Parity bit options: Odd, even, 0, none - Transmit stop bits: 1 or 2 bits I2C serial interface - 2 channels - Operating modes: Normal or high-speed - Transfer modes: Single-transfer mode or continuous-transfer mode - Transmission data length: 8 bits CAN controller - 2 channels - Conforming to ISO11898 - Support to transfer and receive normal frame and expand frame - Transmission speed: 1 Mbps (max) Clock synchronous serial interface - 2 channels - Synchronized serial data transmission by three-wire system - Selectable master mode or slave mode - Built-in baud-rate generator - Transmission data length: 7 bits to 16 bits - Intelligent device station Notes3 CC-Link - Remote device station 10/100/1000Mbps Ether MAC Notes1 - 1 channel - Built-in 2-port switch - GMII / MII interface 10/100Mbps EtherPHY Notes2 - 2 ports - Support for 10BaseT and 100BaseTX/FX CC-Link IE Notes1 EtherCAT Notes2 On-chip debug function CC-Link IE field (Intelligent device station) EtherCAT slave controller - Select serial wire or JTAG - Support full trace (Built-in ETM) Internal PLL Generates various clocks from 25-MHz input clock Power supply voltage I/O: VDD33 = 3.30.3 V Internal circuit: VDD10 = 1.00.1 V Power supply for internal PHY Note 2: VDD15 = 1.50.15 V (internal regulator available) <R> Notes 1. Only applied to R-IN32M3-CL. 2. Only applied to R-IN32M3-EC. 3. Please contact our sales representative for details. R18DS0008EJ0500 Dec. 28, 2018 Page 3 of 4 R18DS0008EJ0500 Dec. 28, 2018 CPU System S DMAC _RTPORT M S DMAC M HOST_CPU DMAC_RTPORT DMAC CPU I-Code CPU D-Code S S MUX S Serial Flash ROM MEMC S M M M NVIC Debug S GPIO S S MUX S S MUX Real-Time GPIO S Hardware Real-Time OS Bridge OS S S S Buffer Allocator MEMC S S MUX S Selector S MUX S S S S S MUX S M MAC_DMA M Ext_ Micon Interface S S S APB Gigabit Ether Ether SWITCH S AHB_APB Bridge S S MUX MUX S S EtherCAT MAC_TOP INT_DMA M Instruction RAM 768KB(ECC) S S MUX S S AHB2DMA M 128bit Communication Bus Buffer RAM 64KB(ECC) S Data RAM 512KB(ECC) Header Endec M M Buffer ID S S MUX CC-Link Bridge S CPU System S HOST_CPU DMAC_RTPORT DMAC CPU I-Code CPU D-Code PHY PHY 1.4.1 Hardware Function Control 128bit Hardware Function Bus 1.4 Cortex-M3 CPU R-IN32M3-EC R-IN32M3 Series Data Sheet 1. Overview Internal Block Diagram R-IN32M3-EC Block Diagram Timer Array UART x 2ch I2C x 2ch CAN x 2ch CSI x 2ch WDT Page 4 of 5 R18DS0008EJ0500 Dec. 28, 2018 CPU System S DMAC _RTPORT M S DMAC M HOST_CPU DMAC_RTPORT DMAC CPU I-Code CPU D-Code S S MUX S Serial Flash ROM MEMC S M M M NVIC Debug S GPIO S S MUX S S MUX Real-Time GPIO S Hardware Real-Time OS Bridge OS S Hardware Function Control S S Buffer Allocator MEMC S S MUX S Selector S MUX S S S S S MUX S M MAC_DMA M Ext_ Micon Interface S S S APB Ether SWITCH Gigabit Ether Buffer ID S AHB_APB Bridge S S MUX MUX S S MAC_TOP CC-Link IE Field Network INT_DMA M Instruction RAM 768KB(ECC) S S MUX S S AHB2DMA M 128bit Communication Bus Buffer RAM 64KB(ECC) S Data RAM 512KB(ECC) Header Endec M M 128bit Hardware Function Bus DMAC CPU I-Code CC-Link S HOST_CPU DMAC_RTPORT S S MUX Bridge S CPU System CPU D-Code PHY PHY 1.4.2 Cortex-M3 CPU R-IN32M3-CL R-IN32M3 Series Data Sheet 1. Overview R-IN32M3-CL Block Diagram Timer Array UART x 2ch I2C x 2ch CAN x 2ch CSI x 2ch WDT Page 5 of 6 R-IN32M3 Series Data Sheet 1.5 1. Overview Memory Maps FFFF FFFFH E000 0000H DFFF FFFFH 4400 0000H 43FF FFFFH 4200 0000H 400A FFFFH Cortex-M3 system level area (512 Mbytes) 400A 8000H Reserved 400A 4800H Bitband alias area (32 Mbytes) 400A 4400H Reserved Synchronous burst access MEMC control registers area (8 Kbytes) Reserved CC-Link (master/slave) bridge control registers area (1 Kbyte) Reserved Reserved 400A 3400H 400F C000H 400F BFFFH 400F B000H 400F AFFFH 400F A000H 400F 9FFFH 400F 8000H 400A 3000H CC-Link slave area (4 Kbytes) CC-Link master memory area (8 Kbytes) 400E 0000H 400B 0000H 400A FFFFH 4008 0000H 4007 FFFFH 4000 0000H Ether CAT area (12 Kbytes) GPIO (1 Kbyte) DMA controller RTPORT 400A 2C00H control registers area (1 Kbyte) DMA controller control registers area (1 Kbyte) 400A 2800H Serial flash ROM memory controller 400A 2400H control registers area (1 Kbyte) Asynchronous SRAM MEMC 400A 2000H control registers area (1 Kbyte) CC-Link master I/O area (4 Kbytes) Reserved 400E 3000H 400E 2FFFH Real-time port (1 Kbyte) System area 4009 2000H 4009 1000H Reserved 4009 0000H AHB peripheral registers area (192 Kbytes) APB peripheral registers area (512 Kbytes) 4008 0000H Reserved QINT BUFID (4 Kbytes) Giga bit Ether (4 Kbytes) HW-RTOS (64 Kbytes) Reserved 22FF FFFFH 2200 0000H 2008 0000H 2007 FFFFH 2000 0000H 1FFF FFFFH 1000 0000H 0FFF FFFFH 0800 0000H 040C 0000H 040B FFFFH 0400 0000H 03FF FFFFH 0200 0000H 000C 0000H 000B FFFFH 0000 0000H Bitband alias area (16 Mbytes) Reserved Data RAM area (512 Kbytes) External memory area (256 Mbytes) Buffer memory area (128 Mbytes) Reserved Instruction RAM area <R> (768 Kbytes) iCode, dCode area Serial flash ROM area (32 Mbytes) Reserved Instruction RAM mirror area Note <R> (768 Kbytes) Figure 1.1 Memory Map (ALL) (R-IN32M3-EC) <R>Note: The addresses of the instruction RAM mirror area (768 Kbytes) where access actually occurs will change according to the selected boot mode. For details, see section 5.3, Memory MAP in Each Boot Mode, in the R-IN32M3 Series User's Manual: Peripheral Modules. R18DS0008EJ0500 Dec. 28, 2018 Page 6 of 7 R-IN32M3 Series Data Sheet FFFF FFFFH E000 0000H DFFF FFFFH 4400 0000H 43FF FFFFH 4200 0000H 1. Overview 400A FFFFH Cortex-M3 system level area (512 Mbytes) Reserved 400A 4800H Bitband alias area (32 Mbytes) 400A 4400H Reserved 4014 0000H 4013 FFFFH 4010 0000H 400F C000H 400F BFFFH 400F B000H 400F AFFFH 400F A000H 400F 9FFFH 400F 8000H 400F 7FFFH 400A 4000H 400A 3400H Reserved 400A 3000H CC-Link slave area (4 Kbytes) 400A 2C00H CC-Link master I/O area (4 Kbytes) 400A 2800H CC-Link master memory area (8 Kbytes) 400A 2400H 400A 2000H System area 4009 2000H 4009 1000H 4008 0000H 4007 FFFFH 4000 0000H Reserved CC-Link(master/slave) bridge control registers (1 Kbyte) CC-Link IE field network bridge control registers (1 Kbyte) Reserved CC-Link IE field network area (256 Kbytes) Reserved 400B 0000H 400A FFFFH Reserved Synchronous burst access MEMC control registers area (8 Kbytes) 400A 8000H 4009 0000H AHB peripheral registers area (192 Kbytes) APB peripheral registers area (512 Kbytes) 4008 0000H Real-time port (1 Kbyte) GPIO (1 Kbyte) DMA controller RTPORT control registers area (1 Kbyte) DMA controller control registers area(1Kbyte) Serial flash ROM memory controller control registers area (1 Kbyte) Asynchronous SRAM MEMC control registers area (1 Kbyte) Reserved QINT BUFID (4 Kbytes) Giga bit Ether (4 Kbytes) HW-RTOS (64 Kbytes) Reserved 22FF FFFFH 2200 0000H 2008 0000H 2007 FFFFH 2000 0000H 1FFF FFFFH 1000 0000H 0FFF FFFFH 0800 0000H 040C 0000H 040B FFFFH 0400 0000H 03FF FFFFH 0200 0000H 000C 0000H 000B FFFFH 0000 0000H Bitband alias area (16 Mbytes) Reserved Data RAM area (512 Kbytes) External memory area (256 Mbytes) Buffer memory area (128 Mbytes) Reserved Instruction RAM area <R> (768 Kbytes) iCode, dCode area Serial flash ROM area (32 Mbytes) Reserved Instruction RAM mirror area Note <R> (768 Kbytes) Figure 1.2 Memory Map (ALL) (R-IN32M3-CL) <R>Note: The addresses of the instruction RAM mirror area (768 Kbytes) where access actually occurs will change according to the selected boot mode. For details, see section 5.3, Memory MAP in Each Boot Mode, in the R-IN32M3 Series User's Manual: Peripheral Modules. R18DS0008EJ0500 Dec. 28, 2018 Page 7 of 8 R-IN32M3 Series Data Sheet 1. Overview 4007 FFFFH 4007 0000H ETHER SWITCH control register area (64 Kbytes) Reserved 4004 0000H 4002 0000H 4001 0000H CAN1 area (128 Kbytes) CAN0 area (128 Kbytes) System register area (64 Kbytes) Reserved 4000 0700H Watchdog timer (16 bytes) Reserved 4000 0600H IIC1 (64 bytes) Reserved 4000 0500H IIC0 (64 bytes) Reserved 4000 0400H UART1 (128 bytes) Reserved 400B 0000H 400A FFFFH 4008 0000H 4007 FFFFH 4000 0000H Reserved 4000 0300H AHB peripheral registers area (192 Kbytes) 4000 0200H APB peripheral registers area (512 Kbytes) 4000 0100H Reserved 4000 0000H UART0 (128 bytes) CSI1 (256 bytes) CSI0 (256 bytes) Timer (TAUJ) (256 bytes) Figure 1.3 Memory Map (APB Peripheral Registers Area; Common to R-IN32M3-EC/CL) R18DS0008EJ0500 Dec. 28, 2018 Page 8 of 9 R-IN32M3 Series Data Sheet 1. Overview 1FFF FFFFH CSZ3 area (64 Mbytes) 1C00 0000H 1BFF FFFFH 2008 0000H 2007 FFFFH 2000 0000H 1FFF FFFFH 1000 0000H 0FFF FFFFH 0800 0000H CSZ2 area (64 Mbytes) Reserved Data RAM area (512 Kbytes) External memory area (256 Mbytes) Buffer memory area (128 Mbytes) 1800 0000H 17FF FFFFH CSZ1 area (64 Mbytes) 1400 0000H 13FF FFFFH CSZ0 area (64 Mbytes) 1000 0000H Reserved Figure 1.4 Memory Map (External Memory Area; Common to R-IN32M3-EC/CL) 400F AFFFH Reserved 400F A37FH CC-Link master I/O area (4 Kbytes) 400F A100H Reserved 400F 9CFFH 400F 9000H Reserved 400F BFFFH 400F B000H 400F AFFFH 400F A000H 400F 9FFFH 400F 8000H CC-Link slave area (4 Kbytes) CC-Link master I/O area (4 Kbytes) CC-Link master memory area (8 Kbytes) 400F 8C00H CC-Link master memory area receive buffer (3328 bytes) Reserved CC-Link master memory area PAT1 (256 bytes) Reserved 400F 8B9FH CC-Link master memory area 400F 8800H transmit buffer 2 (924 bytes) Reserved 400F 84FFH CC-Link master memory area PAT0 (256 bytes) 400F 8400H Reserved 400F 839FH CC-Link master memory area 400F 8000H transmit buffer 1 (924 bytes) Reserved Figure 1.5 Memory Map (CC-Link Master Area; Common to R-IN32M3-EC/CL) Cautions 1. CC-Link master shows the function block of intelligent device station. 2. CC-Link slave shows the function block of the remote device station. R18DS0008EJ0500 Dec. 28, 2018 Page 9 of 10 R-IN32M3 Series Data Sheet 1. Overview Internal AHB area MCU area 1F FFFFH 18 0000H 17 FFFFH Data RAM area (512 Kbytes) Reserved 10 0000H 0F FFFFH 0F FF00H 0F C000H 0F BFFFH 0F B000H 0F AFFFH 2 Mbytes 0F A000H 0F 9FFFH 0F 8000H 0E 3000H 0E 2FFFH 0E 0F80H 0D FFFFH 0D 0000H 0C FFFFH 0C 3000H 0C 0000H 0B FFFFH 00 0000H Reserved HOSTIF registers area (256 bytes) Reserved CC-Link slave area (4 Kbytes) CC-Link slave area (4 Kbytes) CC-Link master I/O area (4 Kbytes) CC-Link master I/O area (4 Kbytes) CC-Link master memory area (8 Kbytes) CC-Link master memory area (8 Kbytes) Reserved Reserved Ether CAT area (8.125 Kbytes) Reserved Ether CAT area (8.125 Kbytes) Reserved 400F C000H 400F BFFFH 400F B000H 400F AFFFH 400F A000H 400F 9FFFH 400F 8000H 400E 3000H 400E 2FFFH 4 Gbytes 400E 0F80H 400E 0000H System registers area (64 Kbytes) AHB peripheral area (upper 52 Kbytes) AHB peripheral area (upper 52 Kbytes) 400A FFFFH 400A 3000H Reserved Instruction RAM mirror area Note <R> (768 Kbytes) System registers area (64 Kbytes) Data RAM area (512 Kbytes) Reserved Instruction RAM mirror area Note <R> (768 Kbytes) 4001 FFFFH 4001 0000H 2007 FFFFH 2000 0000H 000D 2FFFH 000C 0000H 000B FFFFH 0000 0000H Figure 1.6 External MCU Interface Area (R-IN32M3-EC) <R>Note: The addresses of the instruction RAM mirror area (768 Kbytes) where access actually occurs will change according to the selected boot mode, as shown in the table below. For details, see section 5.3, Memory MAP in Each Boot Mode, and section 4, Bus Architecture, in the R-IN32M3 Series User's Manual: Peripheral Modules. BOOT1 BOOT0 Boot Mode Access Destination Area Remarks 0 0 External memory boot -- External MCU interface is disabled 0 1 External serial flash ROM boot Reserved Access disabled 1 0 External MCU boot Instruction RAM area -- 1 1 Instruction RAM boot Instruction RAM area Enabled only for debugging R18DS0008EJ0500 Dec. 28, 2018 Page 10 of 11 R-IN32M3 Series Data Sheet 1. Overview Internal SRAM area 1F FFFFH CC-Link IE field network area (256 Kbytes) 13 FFFFH 2 Mbytes 10 0000H 00 0000H MCU area 1F FFFFH 18 0000H 17 FFFFH Internal AHB area FFFF FFFFH Data RAM area (512 Kbytes) Reserved 14 0000H 13 FFFFH 10 0000H 0F FFFFH 0F FF00H 0F C000H 0F BFFFH 0F B000H 0F AFFFH 2Mbyte 0F A000H 0F 9FFFH 0F 8000H 0F 7FFFH CC-Link IE field network area (256 Kbytes) Reserved HOSTIF registers area (256 bytes) Reserved CC-Link slave area (4 Kbytes) CC-Link slave area (4 Kbytes) CC-Link master I/O area (4 Kbytes) CC-Link master I/O area (4 Kbytes) CC-Link master momory area (8 Kbytes) CC-Link master memory area (8 Kbytes) Reserved Reserved 400F C000H 400F BFFFH 400F B000H 400F AFFFH 400F A000H 400F 9FFFH 400F 8000H 400F 7FFFH 4 Gbytes 0E 0000H 0D FFFFH 0D 0000H 0C FFFFH 0C 3000H 0C 0000H 0B FFFFH 00 0000H 400E 0000H System registers area (64 Kbytes) AHB peripheral area (upper 52 Kbytes) AHB peripheral area (upper 52 Kbytes) 400A FFFFH 400A 3000H Reserved Instruction RAM mirror area Note <R> (768 Kbytes) System registers area (64 Kbytes) Data RAM area (512 Kbytes) Reserved Instruction RAM mirror area Note <R> (768 Kbytes) 4001 FFFFH 4001 0000H 2007 FFFFH 2000 0000H 000D 2FFFH 000C 0000H 000B FFFFH 0000 0000H Figure 1.7 External MCU Interface Area (R-IN32M3-CL) <R>Note: The addresses of the instruction RAM mirror area (768 Kbytes) where access actually occurs will change according to the selected boot mode, as shown in the table below. For details, see section 5.3, Memory MAP in Each Boot Mode, and section 4, Bus Architecture, in the R-IN32M3 Series User's Manual: Peripheral Modules. R18DS0008EJ0500 Dec. 28, 2018 Page 11 of 12 R-IN32M3 Series Data Sheet 1. Overview BOOT1 BOOT0 Boot Mode Access Destination Area Remarks 0 0 External memory boot -- External MCU interface is disabled 0 1 External serial flash ROM boot Reserved Access disabled 1 0 External MCU boot Instruction RAM area -- 1 1 Instruction RAM boot Instruction RAM area Enabled only for debugging R18DS0008EJ0500 Dec. 28, 2018 Page 12 of 13 R18DS0008EJ0500 Dec. 28, 2018 P0_ SD_P D13 RP23 RP25 P0_ RD_N P0_ SD_N 14 13 12 RP33 RP35 RP10 RP12 RP14 RP15 B RP34 RP36 RP37 RP11 RP13 GND A 6 5 4 3 2 1 C RP17 RP16 RP03 RP05 VDD15 RP07 RP32 P0_FX_ TEST EN_OUT DOUT5 7 D RP00 RP01 RP02 RP04 GND RP06 RP31 P70 TEST3 P75 P74 F P71 P76 E P72 GND GND VDD33 GND VDD33 GND GND VDD33 GND A15 A5 A4 P77 VDD33 GND GND GND VDD33 GND TMC1 GND D8 A16 A9 A8 A3 A2 F H G H BGND AGND_ REG AVDD_ REG FB TEST2 P60 VDD33 GND VDD10 GND GND GND GND VDD10 GND P43 CSZ0 GND AGND P61 P73 GND VDD33 GND VDD10 VDD10 VDD10 VDD10 GND VDD33 A14 WRZ1 WRZ0 WRSTBZ P0VDD BUSCLK ARXTX G J LX GND TEST1 P62 VDD33 GND VDD10 GND GND GND GND VDD10 VDD33 P40 RDZ K BVDD GND L VDD15 P67 P66 P64 P63 GND TCK GND VDD10 GND GND GND GND VDD10 GND P47 P42 P65 GND VDD10 GND GND GND GND VDD10 GND P44 P41 AGND VDD33 ESD VDD15 VSSA PLLCB P0_ TX_P L VDD APLL P0_ RX_P K P0_ TX_N J P0_ RX_N M N P46 AGND P1_ TX_P P1_ TX_N P M P07 P05 P06 P00 TRSTZ VDD33 GND VDD10 VDD10 VDD10 VDD10 GND VDD33 N P04 P03 P01 P20 GND GND VDD33 GND GND VDD33 GND VDD33 GND R P P02 P22 P23 P21 R P24 P25 P26 P27 VDD15 GND PLL_ GND TDO P10 P17 GND VDD33 HWRZ SEL PLL_ VDD TMS TDI GND MEMC SEL HIF SYNC ADMUX MODE T XT1 GND P36 P34 OSCTH P15 P16 VDD33 P1_ SD_N P1_ RD_N VDD33 CCM_ CLK80M BOOT1 RESETZ TRACE DATA0 TRACE CLK P53 GND V P31 P32 P30 P33 U XT2 V GND P35 P12 P13 P37 P1_FX_ EN_OUT P14 P1_TD_ P1_TD_ OUT_P OUT_N GND P1_ SD_P VDDQ_ PECL_B1 P11 P1_ RD_P GND BOOT 0 MEM IFSEL VDD15 GND VDD15 PONRZ BUS32 EN TMC2 TRACE DATA2 TRACE DATA1 RST OUTZ P54 P55 P56 U P52 P51 P50 T JTAG SEL NMIZ GND AGND P1VDD ARXTX TRACE DATA3 P57 VDD15 P1_ RX_P P1_ RX_N TMODE TMODE TMODE 2 1 0 P45 ATP EXT RES VDD ACB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin Placement (R-IN32M3-EC Top View) RP30 RP26 RP22 D15 VDD15 D9 D7 A13 A12 A7 A6 E 2.1 RP20 VDD33 VDDQ_ PECL_B0 RP27 D14 D11 D10 A20 A19 A11 A10 D Pin Information P0_TD_ P0_TD_ OUT_N OUT_P GND RP21 D12 D5 D3 A18 A17 C 2. 8 9 10 VDD15 P0_ RD_P D6 15 11 RP24 D4 16 D1 D2 17 D0 B GND A 18 R-IN32M3 Series Data Sheet 2. Pin Information Page 13 of 14 RP27 RP33 RP37 RP14 RP10 RP04 D0 D2 D6 D10 D14 RP23 RP25 RP26 RP32 RP36 RP13 RP17 RP05 RP02 16 15 R18DS0008EJ0500 Dec. 28, 2018 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C D ETH0_ GTXC CLKOUT ETH0_ 25M0 TXD4 GND B ETH0_ TXD1 ETH0_ TXD5 ETH0_ TXD7 RP00 A ETH0_ TXD2 ETH0_ TXD6 RP01 E ETH0_ RXC ETH0_ TXER ETH0_ TXEN ETH0_ TXD0 ETH0_ TXD3 GND GND GND GND GND GND GND GND GND A8 A7 RP03 RP16 RP12 RP35 RP31 RP20 TMC1 D11 D7 D3 A12 A11 A6 A5 E GND RP07 RP15 RP11 RP34 RP30 RP21 D15 D12 D8 D4 A16 A15 A10 A9 D RP06 RP24 RP22 D13 D9 D5 D1 A19 A14 A13 C F ETH0_ TXC ETH_ MDIO ETH0_ COL ETH0_ CRS GND GND VDD33 GND VDD33 GND GND VDD33 GND GND A4 A3 A2 WRZ1 F G ETH0_ RXDV ETH0_ RXER ETH0_ GE_INT ETH_ MDC H ETH0_ RXD3 ETH0_ RXD2 ETH0_ RXD1 ETH0_ RXD0 VDD33 GND VDDQ_ MII GND VDD10 GND GND GND GND VDD10 GND GND P40 P41 P42 BUSCLK H GND VDD10 VDD10 VDD10 VDD10 GND VDD33 GND WRZ0 WRSTBZ CSZ0 RDZ G J ETH0_ RXD7 ETH0_ RXD6 ETH0_ RXD5 ETH0_ RXD4 GND GND VDD10 GND GND GND GND VDD10 VDD33 GND P46 P45 P44 P43 J P75 P74 P73 GND L P61 P60 P77 P76 M P65 P64 P63 P62 N K ETH1_ TXD7 ETH1_ TXD6 ETH1_ TXD5 ETH1_ TXD4 GND VDDQ_ MII VDD10 GND GND GND GND VDD10 GND L ETH1_ TXD3 ETH1_ TXD2 ETH1_ TXD1 ETH1_ TXD0 VDD33 GND VDD10 GND GND GND GND VDD10 GND M ETH1_ GTXC ETH1_ TXEN ETH1_ TXER TCK GND VDDQ_ MII GND VDD10 VDD10 VDD10 VDD10 GND VDD33 N ETH1_ TXC ETH1_ GE_INT ETH1_ COL TRSTZ GND GND VDD33 GND GND VDD33 GND VDD33 GND P04 MEMC SEL P ETH1_ RXC ETH1_ CRS ETH1_ RXER ETH1_ RXDV OSCTH R ETH1_ RXD0 ETH1_ RXD1 ETH1_ RXD2 ETH1_ RXD3 TDO TMS TDI PLL_ VDD PLL_ GND P12 P13 GND ETH1_ RXD7 P37 T U ETH1_ CLKOUT RXD4 25M1 ETH1_ RXD5 ETH1_ RXD6 P35 P33 P34 P15 P11 P25 P22 P06 P02 BOOT0 P30 P36 RESETZ V GND XT1 XT2 GND P32 P17 P14 P10 P24 P23 P07 P03 CCM_CL K80M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TRACE CLK TRACE DATA2 18 GND V HWRZ CCI_CLK SEL 2_097M P31 P16 P26 P21 P05 P27 GND P20 P00 ADMUX MODE GND BOOT1 HIF SYNC TMC2 P01 MEMIF SEL JTAG SEL TRACE DATA3 RST OUTZ TRACE DATA1 TRACE DATA0 P56 P53 U NMIZ P54 T P55 P57 P52 R PONRZ P51 P50 P67 P66 P TMODE TMODE TMODE HOT BUS32 2 1 0 RESETZ EN P72 P71 P70 P47 K 2.2 A18 A20 17 A17 B GND A 18 R-IN32M3 Series Data Sheet 2. Pin Information Pin Placement (R-IN32M3-CL Top View) Page 14 of 15 R-IN32M3 Series Data Sheet 2.3 2. Pin Information Pin Functions The meanings of the symbols and abbreviations used in this document are given below. Table 2.1 Meanings of the Items in the List of Pins Item Meaning Pin name Name of the pin shown in the following sections. 2.1, Pin Placement (R-IN32M3-EC Top View), 2.2, Pin Placement (R-IN32M3-CL Top View). I/O I/O direction of the given pin Function Summary of the given pin function Active Active level of the given pin Level during reset Indicates the pin state while RSTOUTZ = Low. For details on the reset specifications, refer to the R-IN32M3 Series User's Manual (Peripheral Modules). Table 2.2 Meanings of the Symbols and Abbreviations in the List of Pins Target Symbol and Meaning Abbreviation Pin name - (hyphen) Indicates that the pin is a dedicated pin and is not multiplexed with a port-pin function. I/O - (hyphen) Indicates that the pin is a pin such as a power supply or ground pin and so does not have an I/O direction. Active - (hyphen) Indicates that there is no active level (clock signals, data bus, and address bus). Level during reset High The active level is high. Low The active level is low. - (hyphen) Indicates an input-dedicated pin that has no initial level or state following a reset. High The pin state during a reset is high. Low The pin state during a reset is low. Hi-Z (High) The pin state during a reset is hi-Z (High) with the internal pull-up resistor pulling it to the high level. Hi-Z (Low) The pin state during a reset is hi-Z (Low) with the internal pull-up resistor pulling it to the low level. R18DS0008EJ0500 Dec. 28, 2018 Page 15 of 16 R-IN32M3 Series Data Sheet 2.3.1 (1) 2. Pin Information Ethernet Pins PHY Interface Pins (R-IN32M3-CL only) Caution: Only applied to R-IN32M3-CL. Level during Pin Name I/O Function Active Reset ETH0_TXC I Ethernet 0 10-M/100-M transmit clock (2.5 MHz/25 MHz) - - ETH0_GTXC Note O Ethernet 0 1-G transmit clock (125 MHz) - High ETH0_TXEN Note O Ethernet 0 transmit enable output High Low ETH0_TXER Note O Ethernet 0 transmit error output High Low ETH0_TXD0- O Ethernet 0 transmit data output - Low ETH0_GE_INT I Ethernet 0 PHY interrupt High/Low - ETH0_RXC I Ethernet 0 receive clock - - ETH0_RXDV I Ethernet 0 receive enable input High - ETH0_RXER I Ethernet 0 receive error input High - ETH0_RXD0- I Ethernet 0 receive data input - - ETH0_CRS I Ethernet 0 carrier sense input High - ETH0_COL I Ethernet 0 collision input High - ETH1_TXC I Ethernet 1 10-M/100-M transmit clock (2.5 MHz/25 MHz) - - ETH1_GTXC Note O Ethernet 1 1-G transmit clock (125 MHz) - High ETH1_TXEN Note O Ethernet 1 transmit enable output High Low ETH1_TXER Note O Ethernet 1 transmit error output High Low ETH1_TXD0- O Ethernet 1 transmit data output - Low ETH1_GE_INT I Ethernet 1 PHY interrupt input High/Low - ETH1_RXC I Ethernet 1 receive clock - - ETH1_RXDV I Ethernet 1 receive enable input High - ETH1_RXER I Ethernet 1 receive error input High - ETH1_RXD0- I Ethernet 1 receive data input - - ETH1_CRS I Ethernet 1 carrier sense input High - ETH1_COL I Ethernet 1 collision input High - ETH_MDC O Ethernet management interface clock - Low ETH_MDIO I/O Ethernet management interface data input/output - Hi-Z ETH0_TXD7 Note ETH0_RXD7 ETH1_TXD7 Note ETH1_RXD7 Note: The driving ability can be switched by the setting of the ETHDRCTRL register. For details, see the R-IN32M3 Series User's Manual (Peripheral Modules). R18DS0008EJ0500 Dec. 28, 2018 Page 16 of 17 R-IN32M3 Series Data Sheet (2) 2. Pin Information Media Interface Pins (R-IN32M3-EC only) Caution: Only applied to R-IN32M3-EC. Pin Name I/O Function Active Level during Reset P0_RX_P I PHY0 receive data input (+) - - P0_RX_N I PHY0 receive data input (-) - - P1_RX_P I PHY1 receive data input (+) - - P1_RX_N I PHY1 receive data input (-) - - P0_TX_P O PHY0 transmit data output (+) - - P0_TX_N O PHY0 transmit data output (-) - - P1_TX_P O PHY1 transmit data output (+) - - P1_TX_N O PHY1 transmit data output (-) - - P0_SD_P I PHY0 100BASE-FX signal detect input (+) High - P0_SD_N I PHY0 100BASE-FX signal detect input (-) Low - P1_SD_P I PHY1 100BASE-FX signal detect input (+) High - P1_SD_N I PHY1 100BASE-FX signal detect input (-) Low - P0_RD_P I PHY0 100BASE-FX receive data input (+) - - P0_RD_N I PHY0 100BASE-FX receive data input (-) - - P1_RD_P I PHY1 100BASE-FX receive data input (+) - - P1_RD_N I PHY1 100BASE-FX receive data input (-) - - P0_TD_OUT_P O PHY0 100BASE-FX transmit data output (+) - - P0_TD_OUT_N O PHY0 100BASE-FX transmit data output (-) - - P1_TD_OUT_P O PHY1 100BASE-FX transmit data output (+) - - P1_TD_OUT_N O PHY1 100BASE-FX transmit data output (-) - - P0_FX_EN_OUT O PHY0 100BASE-FX FX enable indication output High - High - 1: 100BASE-FX mode P1_FX_EN_OUT O PHY1 100BASE-FX FX enable indication output 1: 100BASE-FX mode Remark: In MDI-X mode, the input and output attributes of TXP/TXN and RXP/RXN are reversed. R18DS0008EJ0500 Dec. 28, 2018 Page 17 of 18 R-IN32M3 Series Data Sheet (3) 2. Pin Information Other Pins Pin Name I/O Function Shared Port Active Level during Reset PHYLINK0, PHYLINK1 I PHY link input Note1 (for EtherSwitch) P06-P07 High Hi-Z (High) P0LINKLEDZ O SIP_PHY0 link status LED output Note2 P06 Low Hi-Z P1LINKLEDZ O SIP_PHY1 link status LED output Note2 P07 Low ETHSWSECOUT O EtherSwitch event output par second P24 High P0DUPLEXLEDZ O SIP_PHY0 half-duplex transfer status LED P70 - P72 Low Note 3 output Note2 0: Full-duplex 1: Half-duplex P0SPEED100LEDZ O SIP_PHY0 100-BASE status LED output Note2 output Note2 P0SPEED10LEDZ O SIP_PHY0 10-BASE status LED P1DUPLEXLEDZ O SIP_PHY1 half-duplex status LED output Note2 P73 Low P74 - P76 Low 0: Full-duplex 1: Half-duplex P1SPEED100LEDZ O SIP_PHY1 100-BASE status LED output Note2 output Note2 P1SPEED10LEDZ O SIP_PHY1 10-BASE status LED P77 Low P0ACTLEDZ O SIP_PHY0 RX status LED output Note2 RP02 Low O output Note2 RP04 Low P1ACTLEDZ SIP_PHY1 TX status LED Hi-Z (High) Notes 1. Only applies to R-IN32M3-CL. 2. Only applies to R-IN32M3-EC. 3. Hi-Z for R-IN32M3-EC and hi-Z (High) for R-IN32M3-CL. R18DS0008EJ0500 Dec. 28, 2018 Page 18 of 19 R-IN32M3 Series Data Sheet 2.3.2 2. Pin Information EtherCAT Slave Controller Pins (R-IN32M3-EC only) Caution: Only applies to R-IN32M3-EC. Pin Name I/O Function Shared Port Active Level during Reset CATLEDRUN O EtherCAT RUN LED output P00 High Hi-Z CATIRQ O EtherCAT IRQ output P01 High CATLEDSTER O EtherCAT dual-color state LED output P02 High CATLEDERR O EtherCAT error LED output P03 High CATLINKACT0, O EtherCAT link / activity LED output P04-P05 High CATSYNC1 O EtherCAT SYNC1 output P10 High Hi-Z (High) CATSYNC0 O EtherCAT SYNC0 output P11 High Hi-Z (Low) CATLATCH1 I EtherCAT LATCH1 input P10 High Hi-Z (High) CATLATCH0 I EtherCAT LATCH0 input P11 High Hi-Z (Low) CATI2CCLK O EtherCAT EEPROM I2C clock output P22 - Hi-Z CATI2CDATA I/O EtherCAT EEPROM I2C data input/output P23 - CATRESTOUT O EtherCAT PHY RESETOUT P56 - CATLINKACT1 R18DS0008EJ0500 Dec. 28, 2018 Hi-Z (High) Page 19 of 20 R-IN32M3 Series Data Sheet 2.3.3 2. Pin Information External Memory Interface Pins Pin Name I/O Function Shared Shared Signal Port Active Level during Reset BUSCLK O Bus clock output - - - Clock output CSZ0 O Chip select signal output HCSZ - Low Hi-Z (High) CSZ1 O HPGCSZ P44 CSZ2 O - P51 CSZ3 O - P50 A1 / MA0 Note4 O HA1 P40 - Hi-Z (High) A2-A20 / O HA2-HA20 - O - RP21- HD0-HD15 - HD16-HD31 RP30- Address output Hi-Z (Low) MA1-MA19 Note4 A21-A27 / MA20-MA26 Note4 D0-D15 / RP27 I/O Data bus MD0-MD15 / MA0-MA15 Note1, Note4 D16-D31 / I/O MD16-MD31 / RP37 MA16-MA31Note1, Note4 RP10- - Hi-Z (High) Hi-Z (High) RP17 RDZ O WRSTBZ O WRZ0, WRZ1/ O BENZ0, BENZ1 WRZ2, WRZ3/ Read strobe output HRDZ - Low Write strobe output HWRSTBZ - Low Valid byte lane strobe HWRZ0, HWRZ1/ - Low HWRZ2, HWRZ3/ RP06 Low output O BENZ2, BENZ3 WAITZ WAITZ1-WAITZ3 Note2 BCYSTZ / ADVZ Note3 HBENZ0, HBENZ1 HBENZ2, HBENZ3 RP07 I Wait signal input HWAITZ P41 Low I Wait signal input - P45-P47 Low O Address valid output HBCYSTZ RP20 Low Hi-Z (High) Hi-Z (High) Remark: Pins of the external memory interface other than BUSCLK are input pins while the internal reset signal (HRESETZ) is at its active level. Notes 1. While the synchronous burst access memory controller is in use, these signals are multiplexed with the address signals if the ADMUXMODE pin is driven high. ADMUXMODE = 0: MD0-MD31 (Separate address and data lines) ADMUXMODE = 1: MD0-MD31/MA0-MA31 (Multiplexed address and data lines) 2. These pins are only available when the synchronous burst access memory controller is in use. 3. This pin functions as BCYSTZ when the asynchronous SRAM memory controller is in use and as ADVZ when the synchronous burst access memory controller is in use. 4. This pin functions as A1-A27 and D0-D31 functions when the asynchronous SRAM memory controller is in use and as MA0-MA26 and MD0-MD31 functions when the synchronous burst access memory controller is in use. R18DS0008EJ0500 Dec. 28, 2018 Page 20 of 21 R-IN32M3 Series Data Sheet 2.3.4 2. Pin Information External MCU Interface Pins Pin Name I/O Function Shared Pin Shared Port Active HBUSCLK I Bus clock input for host INTPZ11 P43 - HCSZ I Chip select signal input CSZ0 - Low HPGCSZ I PageRom mode chip CSZ1 P44 Low Level during Reset Hi-Z (High) select input HWAITZ O Wait signal output WAITZ P41 Low HA1 I Address signal input A1 P40 - HA2-HA20 I A2-A20 - HD0-HD15 I/O D0-D15 - HD16-HD31 I/O D16-D31 RP30- Data bus Hi-Z (High) Hi-Z (Low) Hi-Z (High) RP37 RP10RP17 HRDZ I Read strobe input RDZ - Low HWRSTBZ I Write strobe output WRSTBZ - Low HWRZ0, HWRZ1/ I Valid byte lane strobe WRZ0, WRZ1/ - Low input BENZ0, BENZ1 HBENZ0, HBENZ1 HWRZ2, HWRZ3/ I HBENZ2, HBENZ3 WRZ2, WRZ3/ RP06 Hi-Z (High) BENZ2, BENZ3 RP07 HERROUTZ O Error interrupt output SLEEPING P42 Low High HBCYSTZ I Bus cycle input BCYSTZ / ADVZ RP20 Low Hi-Z (High) Caution: Input the low level to the HBUSCLK pin while asynchronous mode is in use. Remark: The external MCU interface pins continue to operate during a reset. R18DS0008EJ0500 Dec. 28, 2018 Page 21 of 22 R-IN32M3 Series Data Sheet 2.3.5 2. Pin Information Port Pins and Real-time Port Pins The port and pins are configured as 12 sets of 8-bit ports. They are accessible in 32-bit units by grouping sets of 4 ports; i.e. ports 0 to 3, 4 to 7, and real-time ports 0 to3. (1/4) Pin Mode 1 Name P0 Mode 3 Mode 4 Level during Reset INTPZ0 CATLEDRUN Note1 CCI_RUNLEDZ Note2 - P01 INTPZ1 CATIRQ Note1 - - P02 INTPZ2 CATLEDSTER Note1 CCI_DLINKLEDZ Note2 - INTPZ3 CATLEDERR Note1 CCI_ERRLEDZ Note2 CCS_MON5 P04 INTPZ4 CATLINKACT0 Note1 CCI_LERR1LEDZNote2 CCS_MON6 P05 INTPZ5 CATLINKACT1 Note1 CCI_LERR2LEDZNote2 CCS_MON7 P06 PHYLINK0 Note2 P0LINKLEDZ Note1 CCI_SDLEDZ Note2 CCS_MON0 P07 PHYLINK1 Note2 P1LINKLEDZ Note1 CCI_RDLEDZ Note2 CCS_RESOUT P10 CATLATCH1 CATSYNC1 Note1 - CCS_REFSTB Hi-Z (High) CATSYNC0 Note1 - CCS_MON4 Hi-Z (Low) - CCI_NMIZ Note2 - Hi-Z (High) - CCI_WDTIZ Note2 / - P00 P03 P1 Mode 2 Note 3 Note1 P11 CATLATCH0 Note1 P12 P13 INTPZ6 INTPZ7 CCS_WDTZ / CCM_WDTENZ P2 P14 SMSCK - - - P15 SMSI - - - P16 SMSO - - - P17 SMCSZ - - - P20 RXD0 - CCM_LINKERRZ - P21 TXD0 - CCM_ERRZ - P22 INTPZ8 CATI2CCLK Note1 CCS_IOTENSU - P23 INTPZ9 CATI2CDATA Note1 CCS_SENYU0 - P24 INTPZ10 ETHSWSECOUT CCS_SENYU1 - P25 WDTOUTZ - CCS_ERRZ - P26 TIN1 TOUT1 CCM_RUNZ / - Note3 CCS_RUNZ P27 TIN0 TOUT0 - - Notes 1. Only applies to R-IN32M3-EC. 2. Only applies to R-IN32M3-CL. 3. Hi-Z for R-IN32M3-EC and hi-Z (High) for R-IN32M3-CL R18DS0008EJ0500 Dec. 28, 2018 Page 22 of 23 R-IN32M3 Series Data Sheet 2. Pin Information (2/4) Port Mode 1 Name P3 Mode 2 Mode 3 Mode 4 P30 RXD1 - - - P31 TXD1 - - - P32 DMAREQZ1 - - CCS_MON1 P33 DMAACKZ1 CCI_WAITEDGEH - CCS_MON2 Level during Reset Hi-Z (High) Note2 P4 P5 P34 DMATCZ1 CCI_WRLENH Note2 - CCS_MON3 P35 CSISCK1 INTPZ22 CCM_IRLZ <R> - P36 CSISI1 INTPZ23 CCS_FUSEZ - P37 CSISO1 INTPZ24 CCM_MSTZ - P40 A1 / MA0 HA1 - - P41 WAITZ HWAITZ - - P42 SLEEPING HERROUTZ CCM_SDGCZ - P43 INTPZ11 HBUSCLK - - P44 CSZ1 HPGCSZ - - P45 CSISCK0 WAITZ1 - - P46 CSISI0 WAITZ2 - - Hi-Z (High) P47 CSISO0 WAITZ3 - - P50 CSZ3 - CCM_LNKRUNZ / - P51 CSZ2 - CCM_RDLEDZ / P52 TIN3 TOUT3 CCS_SDGATEON - Hi-Z (Low) P53 CRXD0 CCS_RD CCM_RD - Hi-Z (High) P54 CTXD0 CCS_SD CCM_SD - P55 CRXD1 - - - CTXD1 CATRESTOUT Notes1 CCI_PHYREZ1 Notes2 - TOUT2 CCI_PHYREZ0 Notes2 - CCS_LNKRUNZ - CCS_RDLEDZ P56 P57 TIN2 Notes 1. Only applies to R-IN32M3-EC. 2. Only applies to R-IN32M3-CL. R18DS0008EJ0500 Dec. 28, 2018 Page 23 of 24 R-IN32M3 Series Data Sheet 2. Pin Information (3/4) Port Mode 1 Name P6 P7 Mode 2 Mode 3 Mode 4 P60 SCL0 - - - P61 SDA0 - - - P62 RTDMAREQZ - CCM_MDIN0 - P63 RTDMAACKZ - CCM_MDIN1 - P64 RTDMATCZ - CCM_MDIN2 - P65 DMAREQZ0 - CCM_MDIN3 - P66 DMAACKZ0 - CCI_INTZ Note2 - P67 DMATCZ0 - - - P70 CSICS00 P0DUPLEXLEDZ CCS_STATION_NO_0 / - Note1 CCM_SNIN0 - CCS_STATION_NO_1 / - P71 CSICS01 Level during reset Note3 CCM_SNIN1 P72 P73 P74 CSICS10 CSICS11 INTPZ12 P0SPEED100LEDZ CCS_STATION_NO_2 / - Note1 CCM_SNIN2 P0SPEED10LEDZ CCS_STATION_NO_3 / - Note1 CCM_SNIN3 P1DUPLEXLEDZ CCS_STATION_NO_4 / - Note1 CCM_SNIN4 CCS_STATION_NO_5 / - P75 INTPZ13 - P76 INTPZ14 P1SPEED100LEDZ CCS_STATION_NO_6 / - Note1 CCM_SNIN6 P1SPEED10LEDZ CCS_STATION_NO_7 / - Note1 CCM_SNIN7 CCM_SNIN5 P77 INTPZ15 Notes 1. Only applies to R-IN32M3-EC. 2. Only applies to R-IN32M3-CL. 3. Hi-Z for R-IN32M3-EC and hi-Z (High) for R-IN32M3-CL R18DS0008EJ0500 Dec. 28, 2018 Page 24 of 25 R-IN32M3 Series Data Sheet 2. Pin Information RP0x to RP3x functions as real-time ports which can transfer data via a dedicated DMA controller. They are able to input and output data in 32-bit units in synchronization with the DMA transfer trigger. (4/4) Port Mode 1 Name RP0 RP00 INTPZ16 Mode 2 SCL1 Mode 3 CCM_SDLEDZ / Mode 4 - Level during Reset Hi-Z (High) CCS_SDLEDZ RP1 RP2 RP3 RP01 INTPZ17 SDA1 CCM_SMSTZ - RP02 INTPZ18 P0ACTLEDZ Note CCS_BS1 - RP03 INTPZ19 - CCS_BS2 - RP04 INTPZ20 P1ACTLEDZ Note CCS_BS4 - RP05 INTPZ21 - CCS_BS8 - RP06 WRZ2/BENZ2 HWRZ2/HBENZ2 - - RP07 WRZ3/BENZ3 HWRZ3/HBENZ3 - - RP10 D24/MD24/HD24 - - - RP11 D25/MD25/HD25 - - - RP12 D26/MD26/HD26 - - - RP13 D27/MD27/HD27 - - - RP14 D28/MD28/HD28 - - - RP15 D29/MD29/HD29 - - - RP16 D30/MD30/HD30 - - - RP17 D31/MD31/HD31 - - - RP20 BCYSTZ / ADVZ HBCYSTZ - - Hi-Z (High) RP21 A21/MA20 - - - Hi-Z (Low) RP22 A22/MA21 - - - RP23 A23/MA22 - - - RP24 A24/MA23 INTPZ25 - - RP25 A25/MA24 INTPZ26 - - RP26 A26/MA25 INTPZ27 - - RP27 A27/MA26 INTPZ28 - - RP30 D16/MD16/HD16 - - - RP31 D17/MD17/HD17 - - - RP32 D18/MD18/HD18 - - - RP33 D19/MD19/HD19 - - - RP34 D20/MD20/HD20 - - - RP35 D21/MD21/HD21 - - - RP36 D22/MD22/HD22 - - - RP37 D23/MD23/HD23 - - - Hi-Z (High) Hi-Z (High) Note: Only applies to R-IN32M3-EC. R18DS0008EJ0500 Dec. 28, 2018 Page 25 of 26 R-IN32M3 Series Data Sheet 2.3.6 2. Pin Information Serial Flash ROM Interface Pins The serial flash ROM interface pins are pins of the serial flash ROM memory controller. They support fast read, fast read dual output and fast read dual I/O modes. Pin Name I/O Function Shared Port Active Level during Reset SMSCK O Serial clock output signal for serial P14 - Hi-Z (High) P15 High P16 High P17 Low flash ROM SMSI I/O Serial data I/O signal for serial flash ROM (connected to the SO pin of serial flash ROM) SMSO I/O Serial data I/O signal for serial flash ROM (connected to the SI pin of serial flash ROM) SMCSZ O Chip select output signal for serial flash ROM 2.3.7 DMA Interface Pins The DMA interface pins are interface pins of the DMA controllers for the internal AHB bus. There are two DMA controllers: one with four internal channels but only two external interfaces, and one with one internal channel and one external interface. Pin Name I/O Function Shared Port Active Level during Reset RTDMAREQZ I RTDMAC DMA transfer request input P62 Low RTDMAACKZ O RTDMAC DMA acknowledge output P63 Low RTDMATCZ O RTDMAC terminal count output P64 Low DMAREQZ0 I DMA transfer request input 0 P65 Low DMAACKZ0 O DMA acknowledge output 0 P66 Low DMATCZ0 O DMA terminal count output 0 P67 Low DMAREQZ1 I DMA transfer request input 1 P32 Low DMAACKZ1 O DMA acknowledge output 1 P33 Low DMATCZ1 O Terminal count output 1 P34 Low Note Hi-Z (High) Caution: Each DMA interface is assigned to a specific DMA channel. Note: Hi-Z for R-IN32M3-EC and hi-Z (High) for R-IN32M3-CL. R18DS0008EJ0500 Dec. 28, 2018 Page 26 of 27 R-IN32M3 Series Data Sheet 2.3.8 2. Pin Information External Interrupt Input Pins The chip has one non-maskable interrupt and 29 maskable interrupt input pins. Pin Name I/O Function Shared Port Active Level during Reset NMIZ I Non-maskable external interrupt input - Low Hi-Z (High) INTPZ0-INTPZ5 I External interrupt input P00-P05 Low Note INTPZ6, INTPZ7 P12, P13 Low Hi-Z (High) INTPZ8-INTPZ10 P22-P24 Low Note INTPZ11 P43 Low Hi-Z (High) INTPZ12-INTPZ15 P74-P77 Low Note INTPZ16-INTPZ21 RP00-RP05 Low Hi-Z (High) INTPZ22-INTPZ24 P35-P37 INTPZ25-INTPZ28 RP24-RP27 Hi-Z (Low) Note: Hi-Z for R-IN32M3-EC and hi-Z (High) for R-IN32M3-CL. R18DS0008EJ0500 Dec. 28, 2018 Page 27 of 28 R-IN32M3 Series Data Sheet 2.3.9 2. Pin Information Timer I/O Pins Pin Name I/O Function Shared Port Active Level during Reset TIN0 / TOUT0 I/O Timer TAUJ0 input/output P27 - Note TIN1 / TOUT1 I/O Timer TAUJ1 input/output P26 - TIN2 / TOUT2 I/O Timer TAUJ2 input/output P57 - Hi-Z (High) TIN3 / TOUT3 I/O Timer TAUJ3 input/output P52 - Hi-Z (Low) Note: Hi-Z for R-IN32M3-EC and hi-Z (High) for R-IN32M3-CL. 2.3.10 Watchdog Timer Output Pin Pin Name WDTOUTZ I/O O Function Watchdog timer output Shared Port P25 Active Level during Reset Low Note Note: Hi-Z for R-IN32M3-EC and hi-Z (High) for R-IN32M3-CL. 2.3.11 Trace Pins Pin Name I/O Function Active TRACECLK O Trace port clock output - TRACEDATA3- O Trace port data output - Level during Reset Clock output Low TRACEDATA0 2.3.12 CPU Power Control Pin Pin Name SLEEPING R18DS0008EJ0500 Dec. 28, 2018 I/O O Function CPU SLEEP mode output Shared Port P42 Active High Level during Reset Hi-Z (High) Page 28 of 29 R-IN32M3 Series Data Sheet 2.3.13 2. Pin Information Serial Interface Pins Pin Name I/O Function Shared Port Active TXD0 O UART0 serial data output P21 - RXD0 I UART0 serial data input P20 - TXD1 O UART1 serial data output P31 - RXD1 I UART1 serial data input P30 - CSISCK0 I/O CSI0 serial clock input/output P45 - CSISI0 I CSI0 serial data input P46 - CSISO0 O Level during Reset Note Hi-Z (High) CSI0 serial data output P47 - CSICS00, CSICS01 O CSI0 chip select output 0,1 P70, P71 Low Note CSISCK1 I/O CSI1 serial clock input/output P35 - Hi-Z (High) CSISI1 I CSI1 serial data input P36 - CSISO1 O CSI1 serial data output P37 - CSICS10, CSICS11 O CSI1 chip select output 0,1 P72, P73 Low SCL0 I/O I2C0 serial clock input/output P60 - SDA0 I/O I2C0 serial data input/output P61 - SCL1 I/O I2C1 serial clock input/output RP00 - SDA1 I/O I2C1 serial data input/output RP01 - CRXD0 I CAN0 receive data input P53 - CAN0 transfer data output P54 - CAN1 receive data input P55 - P56 - Note Hi-Z (High) (5V-tolerant buffer) CTXD0 O CRXD1 I (5V-tolerant buffer) CTXD1 O CAN1 transfer data output Note: Hi-Z for R-IN32M3-EC and hi-Z (High) for R-IN32M3-CL. R18DS0008EJ0500 Dec. 28, 2018 Page 29 of 30 R-IN32M3 Series Data Sheet 2.3.14 2. Pin Information CC-Link IE Field Pins (Intelligent Device Station) (R-IN32M3-CL only) Pin Name I/O Function Shared Active Level during Reset Port CCI_RUNLEDZ O RUN status output P00 Low CCI_DLINKLEDZ O Cyclic communication status output P02 Low CCI_ERRLEDZ O Field network error status output P03 Low CCI_LERR1LEDZ O Link error status output 1 P04 Low CCI_LERR2LEDZ O Link error status output 2 P05 Low CCI_SDLEDZ O Transmission state output P06 Low CCI_RDLEDZ O Port reception state output P07 Low CCI_NMIZ O Output NMI interrupt to MCU P12 Low CCI_WDTIZ I Input from external watchdog timer P13 Low CCI_WAITEDGEH I/O Wait synchronized edge setting P33 - P34 - Note Hi-Z (High) Hi-Z (High) 0: Fall edge mode 1: Rise edge mode CCI_WRLENH I/O Note WRL signal enable setting 0: Write byte enable mode 1: Normal byte enable mode CCI_PHYREZ1 O PHY reset output 1 P56 Low CCI_PHYREZ0 O PHY reset output 0 P57 Low CCI_INTZ O Output Interrupt to MCU P66 Low CCI_CLK2_097M I 2.097152-MHz clock (crystal oscillator) - - - Note: When user does boot with the external memory boot mode, external serial flash ROM boot mode, or instruction RAM boot mode, be sure not to input the low level to P33 (multiplexed with CCI_WAITEDGEH) and P34 (multiplexed with CCI_WRLENH) pins during a reset. P33 and P34 pins should be left open circuit or the high level should be input to the pins during a reset. If you input the low level to P33 and P34 pins during a reset, you cannot access the CC-Link IE field from the CPU of the R-IN32M3. R18DS0008EJ0500 Dec. 28, 2018 Page 30 of 31 R-IN32M3 Series Data Sheet 2.3.15 2. Pin Information CC-Link Pins (Intelligent Device Station) Pin Name I/O Function Shared Active Level during Port Reset CCM_LINKERRZ O Link error LED control output P20 Low CCM_ERRZ O Not used <R> P21 Low CCM_RUNZ O Run LED control output P26 Low CCM_MDIN0- I Transfer rate setting input <R> P62-P65 - I Station no. setting switch input P70-P77 - CCM_LNKRUNZ O Link run LED control output P50 Low CCM_RDLEDZ O Receive data LED control output P51 Low CCM_SDLEDZ O Transfer data LED control output RP00 Low CCM_IRLZ <R> O Interrupt signal output from communications circuit <R> P35 Low CCM_WDTENZ I Watchdog timer error input P13 Low CCM_MSTZ O Not used <R> P37 Low CCM_SMSTZ O Not used <R> RP01 Low CCM_RD I Communications circuit data reception P53 - CCM_SD O Communications circuit data transmission pin P54 - CCM_SDGCZ O Communications circuit transmit data & gate control pin P42 Low CCM_CLK80M I CC-Link clock input (80 MHz) - Note CCM_MDIN3 CCM_SNIN0CCM_SNIN7 - Hi-Z (High) - Note: Hi-Z for R-IN32M3-EC and hi-Z (High) for R-IN32M3-CL. R18DS0008EJ0500 Dec. 28, 2018 Page 31 of 32 R-IN32M3 Series Data Sheet 2.3.16 2. Pin Information CC-Link Pins (Remote Device Station) Caution: To use a remote device station, it is necessary to connect a CCS_REFSTB pin (P10) to a port pin with the external interrupt function (INTPZ). Pin Name CCS_MON1- I/O Function Shared Port Active Level during Reset O Monitor signal output P32-P34 - Hi-Z (High) CCS_MON4 O Monitor signal output P11 - Hi-Z (Low) CCS_MON0 O Monitor signal output P06 - Note 1 CCS_MON5- O Monitor signal output P03-P05 - CCS_RESOUT O Reset output signal P07 High CCS_IOTENSU I Initial setting pin P22 - CCS_SENYU0 I Initial setting pin P23 - CCS_SENYU1 I Initial setting pin P24 - CCS_ERRZ O Operation check LED P25 Low CCS_RUNZ O Operation check LED P26 Low CCS_STATION_NO_0- I Station no. setting switch input P70-P77 - CCS_LNKRUNZ O Link run LED control output P50 Low CCS_REFSTB O Interrupt signal P10 High CCS_WDTZ I Watchdog timer input P13 Low CCS_RDLEDZ O Receive data LED control output P51 Low CCS_RD I Communications circuit data reception P53 - CCS_SD O P54 - CCS_MON3 CCS_MON7 CCS_STATION_NO_7 Hi-Z (High) pin Communications circuit data transmission pin CCS_SDLEDZ O Operation check LED RP00 Low CCS_SDGATEON O Communication circuit transmit data & P52 High Hi-Z (Low) CCS_BS1 I Baud rate setting switch input RP02 - Hi-Z (High) CCS_BS2 I Baud rate setting switch input RP03 - CCS_BS4 I Baud rate setting switch input RP04 - CCS_BS8 I Baud rate setting switch input RP05 - CCS_FUSEZ I Fuse cutting input signal P36 Low CCM_CLK80MNote2 I CC-Link clock input port (80 MHz) - - gate control pin - Notes 1. Hi-Z for R-IN32M3-EC and hi-Z (High) for R-IN32M3-CL. 2. This pin is shared with the pin for CC-Link intelligent device station. R18DS0008EJ0500 Dec. 28, 2018 Page 32 of 33 R-IN32M3 Series Data Sheet 2.3.17 2. Pin Information System Pins (1/2) Pin Name XT1 I/O I XT2 I/O Function Clock input pins OSCTH = 1: Oscillator is in use. Active Level during Reset - - - - XT1 and XT2 are respectively connected to GND and oscillator. OSCTH = 0: Resonator is in use. XT1 and XT2 are connected to resonator. RESETZ HOTRESETZ Note1 I Reset input Low - I Hot reset input Low - PONRZ I Internal RAM power-on reset input Low - OSCTH I External clock input mode setting High - - - 0: Resonator using mode 1: External clock input mode JTAGSEL I JTAG pin operating mode setting 0: Cortex-M3 JTAG mode 1: B-SCAN JTAG mode RSTOUTZ O External reset output Low Low CLKOUT25M0 Note1 O PHY clock output - Oscillation source CLKOUT25M1 Note1 O PHY clock output - is passed through PLL_VDD - PLL power supply (1.0 V) - - PLL_GND - PLL ground level (GND) - - VDD33 - I/O power supply (3.3 V) - - VDD10 - Internal power supply (1.0 V) - - GND - Power supply ground level (GND) - - VDDQ_MII Note1 - Ethernet I/O power supply (3.3 V) - - these pins R18DS0008EJ0500 Dec. 28, 2018 Page 33 of 34 R-IN32M3 Series Data Sheet 2. Pin Information (2/2) Pin Name I/O LX Note2 EXTRES Note2 Function Active Level during Reset O 1.5-V output for on-chip regulator - - - Reference resistor connecting pin for on-chip PHY - - P0VDDARXTX Note2 - Analog power supply for Rx/Tx pin (1.5 V) - port 0 - - Note2 - Analog power supply for Rx/Tx pin (1.5 V) - port 1 - - - Analog power supply for on-chip PHY (3.3 V) - - - Analog ground level for on-chip PHY (GND) - - - Power supply for on-chip PHY (1.5V) - - - Analog core power supply for on-chip PHY (1.5V) - - - Analog core ground level for on-chip PHY (GND) - - P1VDDARXTX VDDACB Note2 AGND Note2 VDD15 Note2 VDDAPLL Note2 VSSAPLLCB Note2 VDD33ESD Note2 - Analog test power supply for on-chip PHY (3.3 V) - - AVDD_REG Note2 - Analog power supply for on-chip regulator (3.3 V) - - Note2 AGND_REG - Analog ground level for on-chip regulator (GND) - - Note2 - Power supply for on-chip regulator (3.3 V) - - BGND Note2 - Ground level for on-chip regulator (GND) - - BVDD FB Note2 I Feedback input for on-chip regulator - - Note2 - PECL buffer power supply (3.3 V) - - VDDQ_PECL_B1 Note2 - PECL buffer power supply (3.3 V) - - VDDQ_PECL_B0 Notes 1. Only applies to R-IN32M3-CL. 2. Only applies to R-IN32M3-EC. R18DS0008EJ0500 Dec. 28, 2018 Page 34 of 35 R-IN32M3 Series Data Sheet 2.3.18 2. Pin Information Test Pins Pin Name I/O Function Active Level during Reset TMODE0-TMODE2 I Test mode select pin - - TMS I/O Mode select signal - - TDI I Serial data input - - TDO O Serial data output - - TRSTZ I Reset signal Low - TCK I Clock signal (JTAG clock) - - TMC1 I Renesas test pins - - TMC2 I - - ATP Note I TEST1 Note I - - TEST2 Note I - - TEST3 Note I - - O - - TESTOUT5 Note Note: Only applies to R-IN32M3-EC. R18DS0008EJ0500 Dec. 28, 2018 Page 35 of 36 R-IN32M3 Series Data Sheet 2.3.19 2. Pin Information Operating Mode Setting Pins Pin Name BOOT1-BOOT0 I/O I Function Boot mode select Active Level during Reset - - - - - - - - - - - - - - 00: External memory boot 01: External serial flash ROM boot 10: External MCU boot 11: Instruction RAM boot (only available for debugging) MEMIFSEL I External memory interface select 0: Slave memory interface 1: External MCU interface BUS32EN I External memory interface bus width select 0: 16-bit bus 1: 32-bit bus HIFSYNC I External MCU interface operation mode select 0: Asynchronous SRAM interface 1: Synchronous SRAM interface HWRZSEL I External MCU interface HWRZ/HBENZ select 0: Used as HBENZ 1: Used as HWRZ MEMCSEL I Internal memory controller select port 0: Asynchronous SRAM memory controller 1: Synchronous burst access memory controller ADMUXMODE I Multiplexing of address and data lines 0: Separated address and data lines 1: Multiplexed address and data lines R18DS0008EJ0500 Dec. 28, 2018 Page 36 of 37 R-IN32M3 Series Data Sheet 2. Pin Information The combinations of available operating mode setting pins in this product are as follows. Boot Mode External Memory Boot External MCU Boot External Memory Slave Memory External MCU Interface Interface Interface MEMC Type External Serial Flash ROM Boot Slave Memory Interface External MCU Interface Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous External Bus Width 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit BOOT1-0 16-bit 32-bit 16-bit 32-bit 00 00 00 00 10 10 10 10 01 01 01 01 01 01 01 01 MEMIFSEL 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MEMCSEL 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BUS32EN 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note1 Note1 HIFSYNC 0 0 0 0 Note1 1 1 0 0 0 0 Note1 1 1 HWRZSEL 0 0 0 0 Note2 Note2 0 0 0 0 0 0 Note2 Note2 0 0 ADMUXMODE 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Caution: Any combination of operating mode setting pins other than the above is prohibited. Notes 1. The mode of the external MCU interface is selectable by the level on the HIFSYNC pin. HIFSYNC = 0: Asynchronous SRAM interface mode HIFSYNC = 1: Synchronous SRAM interface mode For details, see section 11, External MCU Interface, in the R-IN32M3 Series User's Manual (Peripheral Modules). 2. The external MCU interface HWRZ or HBENZ is selectable by the level on the HWRZSEL pin. For details, see section 2.3.3, External Memory Interface Pins. Remarks 1. The combination of operating-mode setting pins used to select booting for instruction RAM (BOOT1-0 = 11) is the same as that for booting from external memory (BOOT1-0 = 00). 2. Asynchronous: Asynchronous SRAM memory controller (MEMCSEL = 0) Synchronous: Synchronous burst access memory controller (MEMCSEL = 1) R18DS0008EJ0500 Dec. 28, 2018 Page 37 of 38 R-IN32M3 Series Data Sheet 2.4 Buffer Types and Recommended Connections for Unused Pins 2.4.1 (1) 2. Pin Information Ethernet Pins PHY Interface Pins Caution: Only applies to R-IN32M3-CL. Pin Name I/O Interface Recommended Connection when Not in Use ETH0_TXC I Input buffer (3.3 V) Connect to GND ETH0_GTXC O BID_BUF (3.3 V_GMII_MII)_with_IOLH_Control Open ETH0_GE_INT I Input buffer (3.3 V) Connect to GND ETH0_RXC I BID_BUF (3.3 V_GMII_MII)_with_IOLH_Control Connect to GND I Input buffer (3.3 V) Connect to GND O BID_BUF (3.3 V_GMII_MII)_with_IOLH_Control Open ETH1_GE_INT I Input buffer (3.3 V) Connect to GND ETH1_RXC I BID_BUF (3.3 V_GMII_MII)_with_IOLH_Control Connect to GND I Input buffer (3.3 V) Connect to GND ETH_MDC O Output buffer (3.3 V) 6 mA Open ETH_MDIO I/O I/O buffer (3.3 V) 6 mA Connect to GND ETH0_TXEN ETH0_TXER ETH0_TXD0ETH0_TXD7 ETH0_RXDV ETH0_RXER ETH0_RXD0ETH0_RXD7 ETH0_CRS ETH0_COL ETH1_TXC ETH1_GTXC ETH1_TXEN ETH1_TXER ETH1_TXD0ETH1_TXD7 ETH1_RXDV ETH1_RXER ETH1_RXD0ETH1_RXD7 ETH1_CRS ETH1_COL R18DS0008EJ0500 Dec. 28, 2018 Page 38 of 39 R-IN32M3 Series Data Sheet (2) 2. Pin Information Media Interface Pins Caution: Only applies to R-IN32M3-EC. Pin Name I/O Interface Recommended Connection when Not in Use P0_RX_P I P0_RX_N I P1_RX_P I P1_RX_N I P0_TX_P O P0_TX_N O P1_TX_P O P1_TX_N O P0_SD_P I P0_SD_N I P1_SD_P I P1_SD_N I P0_RD_P I P0_RD_N I P1_RD_P I P1_RD_N I P0_TD_OUT_P O P0_TD_OUT_N O P1_TD_OUT_P O P1_TD_OUT_N O P0_FX_EN_OUT O P1_FX_EN_OUT O 2.4.2 Management data interface (analog) Open Management data interface (analog) Open 3.3 -V PECL input buffer Connect to GND 3.3-V PECL output buffer Open Output buffer (3.3 V) 12 mA Open External Memory/ MCU Interface Pins Pin Name I/O Interface Recommended Connection when Not in Use BUSCLK O Output buffer (3.3 V) 9 mA Open CSZ0 / HCSZ I/O I/O buffer (3.3 V) 6 mA 50k pull-up Open A2-A20 / HA2-HA20 I/O I/O buffer (3.3 V) 6 mA 50k pull-down Open I/O I/O buffer (3.3 V) 6 mA 50k pull-up Open D0-D15 / HD0-HD15 RDZ / HRDZ WRSTBZ / HWRSTBZ WRZ0, WRZ1 / BENZ0, BENZ1 / HWRZ0, HWRZ1 R18DS0008EJ0500 Dec. 28, 2018 Page 39 of 40 R-IN32M3 Series Data Sheet 2.4.3 2. Pin Information System Pins Pin Name I/O Interface Recommended Connection when Not in Use NMIZ I Input buffer (3.3 V) Schmitt in, Connect to VDD33 (3.3 V) 50k pull-up XT1 I XT2 I/O Oscillator with EN Connect to GND RSTOUTZ O Output buffer (3.3 V) 6m A Open RESETZ I Input buffer (3.3 V) Schmitt in - I Input buffer (3.3 V) Schmitt in, Set these pins according to the 50k pull-down operating mode - PONRZ HOTRESETZ Connect to VDD33 (3.3 V) OSCTH JTAGSEL 2.4.4 Test Pins Pin Name I/O Interface REQUIRED Connection when Not in Use TMODE0-TMODE2 I Input buffer (3.3 V) Schmitt in, Connect to GND 50k pull-down TMS I/O I/O buffer (3.3 V) 6 mA 50k pull-up Open TDI I Input buffer (3.3 V), 50k pull-up Open TDO O 3-state output buffer (3.3 V) 6 mA Open TRSTZ I Input buffer (3.3 V) Schmitt in, Open 50k pull-up TCK I Input buffer (3.3 V), 50k pull-down Open TMC1 I (TMC1) input buffer (3.3 V) for TMC terminal Connect to GND TMC2 I (TMC2) input buffer (3.3 V) for TMC terminal Connect to GND ATP Note I Input buffer (3.3 V) Open TEST1 Note I Input buffer (3.3 V) Connect to GND TEST2 Note I Input buffer (3.3 V) TEST3 Note I Input buffer (3.3 V) O Output buffer (3.3 V) TESTDOUT5 Note Open Note: Only applies to R-IN32M3-EC. R18DS0008EJ0500 Dec. 28, 2018 Page 40 of 41 R-IN32M3 Series Data Sheet 2.4.5 2. Pin Information Port Pins (1/2) Pin Name I/O Interface Recommended Connection when Not in Use P00-P07 I/O [R-IN32M3-EC] I/O buffer (3.3 V) (6 mA) R-IN32M3-EC: Connect to GND R-IN32M3-CL: Open [R-IN32M3-CL] Programmable I/O buffer (3.3 V) Load drive select function (6 mA, 12 mA) Resistor select function (50k pull-up or 50k pull-down or neither) P10 I/O Programmable I/O buffer (3.3 V) Open Load drive select function (6 mA, 12 mA) Resistor select function (50k pull-up or 50k pull-down or neither) P11-P17 I/O Programmable I/O buffer (3.3 V) (6 mA) Open Resistor select function (50k pull-up or 50k pull-down or neither) P20-21, P25-26 I/O [R-IN32M3-EC] I/O buffer (3.3 V) (6 mA) R-IN32M3-EC: Connect to GND R-IN32M3-CL: Open [R-IN32M3-CL] Programmable I/O buffer (3.3 V) Load drive select function (6 mA, 12 mA) Resistor select function (50k pull-up or 50k pull-down or neither) P22-24, 27 I/O [R-IN32M3-EC] I/O buffer (3.3 V) (6 mA) [R-IN32M3-CL] Programmable I/O buffer (3.3 V) (6 mA) Resistor select function (50k pull-up or 50k pull-down or neither) P30, P31 I/O Programmable I/O buffer (3.3 V) Open Load drive select function (6 mA, 12 mA) Resistor select function (50k pull-up or 50k pull-down or neither) P32-P36 I/O Programmable I/O buffer (3.3 V) (6 mA) Resistor select function (50k pull-up or 50k pull-down or neither) P37 I/O Programmable I/O buffer (3.3 V) Load drive select function (6 mA, 12 mA) Resistor select function (50k pull-up or 50k pull-down or neither) R18DS0008EJ0500 Dec. 28, 2018 Page 41 of 42 R-IN32M3 Series Data Sheet 2. Pin Information (2/2) Pin Name I/O Interface Recommended Connection when Not in Use P40-P47 I/O Programmable I/O buffer (3.3 V) (6 mA) Open Resistor select function (50k pull-up or 50k pull-down or neither) P50-P52 I/O Programmable I/O buffer (3.3 V) Load drive select function (6 mA, 12 mA) Resistor select function (50k pull-up or 50k pull-down or neither) P53-P56 I/O 5V-tolerant I/O buffer 4 mA 50k pull-up P57 I/O Programmable I/O buffer (3.3 V) (6 mA) Resistor select function (50k pull-up or 50k pull-down or neither) P60, P65-P67 I/O [R-IN32M3-EC] I/O buffer (3.3 V) (6 mA) R-IN32M3-EC: Connect to GND R-IN32M3-CL: Open [R-IN32M3-CL] Programmable I/O buffer (3.3 V) (6 mA) Resistor select function (50k pull-up or 50k pull-down or neither) P61-P64 I/O [R-IN32M3-EC] I/O buffer (3.3 V) (6 mA) [R-IN32M3-CL] Programmable I/O buffer (3.3 V) Load drive select function (6 mA, 12 mA) Resistor select function (50k pull-up or 50k pull-down or neither) P70-P77 I/O [R-IN32M3-EC] I/O buffer (3.3 V) (6 mA) R-IN32M3-EC: Connect to GND R-IN32M3-CL: Open [R-IN32M3-CL] Programmable I/O buffer (3.3 V) (6 mA) Resistor select function (50k pull-up or 50k pull-down or neither) RP00-RP07 I/O Programmable I/O buffer (3.3 V) RP10-RP17 Load drive select function (6 mA, 12 mA) RP20-RP27 Resistor select function RP30-RP37 (50k pull-up or 50k pull-down or neither) R18DS0008EJ0500 Dec. 28, 2018 Open Page 42 of 43 R-IN32M3 Series Data Sheet 2.4.6 2. Pin Information Operation Mode Setting Pins Pin Name I/O Interface Recommended Connection when Not in Use BOOT0, BOOT1 I Input buffer (3.3 V) Schmitt in Set these pins according to the operating mode MEMIFSEL BUS32EN HIFSYNC HWRZSEL MEMCSEL ADMUXMODE 2.4.7 CC-Link IE Field (Intelligent Device Station) Pin (R-IN32M3-CL Only) Pin Name I/O Interface Recommended Connection when Not in Use CCI_CLK2_097M I Input buffer (3.3 V) 2.097152-MHz clock input Caution: This pin requires a clock input even when the CC-Link IE Field is not in use. 2.4.8 CC-Link Pins (Intelligent Device Station, Remote Device Station) Pin Name I/O Interface Recommended Connection when Not in Use CCM_CLK80M 2.4.9 I Input buffer (3.3 V) Connect to GND Trace Pins Pin Name I/O Interface Recommended Connection when Not in Use TRACECLK O Output buffer (3.3 V) 6 mA Open TRACEDATA0TRACEDATA3 R18DS0008EJ0500 Dec. 28, 2018 Page 43 of 44 R-IN32M3 Series Data Sheet 3. Specifications 3.1 CPU (Cortex-M3) 3. Specifications An R-IN32M3 device incorporates a high-performance 32-bit processor (Arm Cortex-M3 core). This chapter explains information specific to R-IN32M3 products. 3.1.1 CPU Core Information The version of the Cortex-M3 core currently used in an R-IN32M3 is shown below. More information about the architecture of the CPU can be obtained from: http://infocenter.arm.com/help/topic/com.arm.doc.set.cortexm/index.html R18DS0008EJ0500 Dec. 28, 2018 Product Name Revision R-IN32M3 Series Cortex-M3 r2p1 Page 44 of 45 R-IN32M3 Series Data Sheet 3.1.2 3. Specifications CPU Core Configuration The Cortex-M3 of an R-IN32M3 has the following configurations. Category Interrupts Configuration Item NUM_IRQ Setting 128 Remark The number of IRQ interrupts to be input: 1 to 240 (NMI interrupts are counted separately) Interrupt priority LVL_WIDTH 4 Priority bit number 3 to 8 (8 to 256 priority levels) MPU MPU_PRESENT Yes Presence of the memory protection unit Debug level DEBUG_LVL 3 Debug level 1 to 3 Trace level TRACE_LVL 2 Trace level 0 to 2 SW/SWJ-DP JTAG_PRESENT SWJ-DP SWJ-DP is selected when JTAG access circuit is BB_PRESENT Yes selection built in. Bit-band area Debug Level Function outline Presence of bit-banding 1 2 3 (Settings in R-IN32M3) Minimum debug Full Debug configuration Full debug configuration configuration (Data matching is not (with data matching) available) Debugging halt Breakpoints DWT comparator number Yes 2 (Instruction) Yes Yes 6 (Instruction) 6 (Instruction) 2 (Literal) 2 (Literal) 1 (Data matching is not 4 (Data matching is not 4 available) available) Flash patch function Trace Level Function outline No Yes Yes 0 1 2 (Settings in R-IN32M3) No trace Standard trace Full trace ITM and TPIU functions No Yes Yes DWT trigger and counter No Yes Yes ETM function No No Yes Caution: R-IN32M3 products do not support SLEEPDEEP mode. Do not set the SLEEPDEEP bit of the SCR register to 1. R18DS0008EJ0500 Dec. 28, 2018 Page 45 of 46 R-IN32M3 Series Data Sheet 3.2 3.2.1 3. Specifications Gigabit Ethernet MAC Features - 1 port (by switching between two ports) - 10BASE, 100BASE, 1000BASE MAC - Supports 1000BASE-X Physical Coding Sublayer (PCS) - Supports full-duplex and half-duplex communication modes - Automatic pause packet transmission function - Auto broadcast suspension in response to reception of a pause packet - Supports MII/GMII interface 3.2.2 Switch Functions Following switching features are provided in an R-IN32M3. - Two-port interface - Hardware switching, look-up and filtering - QoS with frame prioritization - Priority control based on VLAN Priority (IEEE802.1q), which enables priorities to be re-assigned - Classification and assigning of priority based on Differentiated Services (DiffServ) Code Point Field of IP v.4 and Class of Service (CoS) in IP v.6 - Queue with four priority levels - Multicasting and broadcasting - VLAN frames - Cut-through and hub features - Device level ring (DLR) R18DS0008EJ0500 Dec. 28, 2018 Page 46 of 47 R-IN32M3 Series Data Sheet 3.3 3. Specifications EtherCAT Slave Controller Function (R-IN32M3-EC only) The EtherCAT Slave Controller (ESC) uses the EtherCAT Slave Controller IP Core made by Beckhoff Automation GmbH, Germany. The ESC handles EtherCAT communications by serving as an interface between EtherCAT field bus and slave applications. Table 3.1 Features of the EtherCAT Slave Controller Feature R-IN32M3-EC ET1100 Ports 2 2-4 FMMUs 8 8 SyncManagers 8 8 RAM [Kbytes] 8 8 Distributed clocks 64 bits 64 bits EBus Not available Available (0-4) Process data interfaces (PDIs) - - Digital I/O Not available Available SPI slave Not available Available Host CPU interface On-chip bus (external MCU interface) 8 bits/16 bits, synchronous/asynchronous Caution: The register area (0E_0000H-0E_0F7FH) cannot be accessed from the external MPU interface (host CPU interface). R18DS0008EJ0500 Dec. 28, 2018 Page 47 of 48 R-IN32M3 Series Data Sheet 3.4 3. Specifications CC-Link IE Field (Intelligent Device Station) Function (R-IN32M3-CL only) The CC-Link IE field intelligent device station has functionality equivalent to that of the dedicated CP220 communications LSI chips manufactured by Mitsubishi Electric Corporation. The outline specifications of the CC-Link IE field are as follows. For detailed specifications on the CC-Link IE field network, visit the following CC-Link Partner Association website. https://www.cc-link.org/en/cclink/cclinkie/index.html Table 3.2 Outline Specifications of CC-Link IE Field Item Specification Ethernet standards IEEE802.3ab (1000BASE-T) compliant Transfer rate 1Gbps Topology Line, star, ring Maximum number of connected units 254 modules Maximum station-to-station distance 100 m R18DS0008EJ0500 Dec. 28, 2018 Page 48 of 49 R-IN32M3 Series Data Sheet 3.5 3. Specifications General DMA Controller 3.5.1 Features - Number of channels: 4 independent channels - Transfer data size Independently selectable for source and destination Size range: 8 to 512 bits - Maximum number of transfer bytes: 232-1 - Channel priority control Fixed priority mode Round robin mode (The channel that last completed a transfer is shifted to the lowest priority position.) - DMA transfer methods The data used for DMA transfer is set in an internal register by using the following two modes. Register mode: DMA transfer is performed using the values set in the control registers of the DMA controller written by the CPU. This mode supports conventional general DMA transfer. Link mode: DMA transfer is performed according to a descriptor located in data RAM and external memory. The responsiveness of this mode is inferior to register mode because access of the descriptor occurs at every DMA transfer. - Skip function Continuous access size and skip space size can each be set for the areas that are accessed with DMA transfer. Following access of the set size, it is possible to skip to the next address to be accessed. - Buffer data dump function Then DMA is forced to stop, the function can dump the data stored in the buffer. After the dump, the DMA transfer is continued. - Suspension function The ongoing DMA transaction can be suspended. - DMA transfers interval setting function The DMA transfer interval can be specified to adjust the bus occupancy rate. - Transfer mode Single transfer mode When a DMA transfer request is made, the right to use the bus is acquired and the bus is released each time a transfer is completed. After that, whenever a DMA transfer request is made, this operation is repeated until the numbers of transfers specified in the control register are completed. Block transfer mode When a DMA transfer request is made, the right to use the bus is acquired and data transfer is repeated until the numbers of transfers specified in the control register are completed. In this case, the bus is not occupied. Caution: Transfer 512-bit wide data requires the data to be aligned on a 512-bit boundary. R18DS0008EJ0500 Dec. 28, 2018 Page 49 of 50 R-IN32M3 Series Data Sheet 3.6 3. Specifications DMA Controller for Real-time Port 3.6.1 Features - Number of channels: 1 - Transfer data size Independently selectable for source and destination Size range: 8 to 128 bits - Maximum number of transfer bytes: 232-1 - DMA transfer methods Register mode: DMA transfer is performed according to the control register in the DMA controller that is set from the CPU. The conventionally used General DMA transfer is supported. Link mode: DMA transfer is performed according to a descriptor located in data RAM and external memory. The responsiveness of this mode is inferior to register mode because the access of the descriptor occurs at every DMA transfer. - SKIP function A continuous access size and skip space size can be set respectively for the area to be accessed for DMA transfer. After space of the set continuous access size has been accessed, the function can skip space of the set discrete access size before accessing the next address. - Buffer data dump function When DMA is forced to stop, the function can dump the data stored in the buffer. After the dump, the DMA transfer is continued. - Suspension function The ongoing DMA transaction can be suspended. - DMA transfers interval setting function The DMA transfer interval can be specified to adjust the bus occupancy rate. - Transfer mode Single transfer mode When a DMA transfer request is made, the right to use the bus is acquired and the bus is released each time a transfer is completed. After that, whenever a DMA transfer request is made, this operation is repeated until the numbers of transfers specified in the control register are completed. Block transfer mode When a DMA transfer request is made, the right to use the bus is acquired and data transfer is repeated until the numbers of transfers specified in the control register are completed. In this case, the bus is not occupied. Caution: Transfer 128-bit wide data requires the data to be aligned on a 128-bit boundary. R18DS0008EJ0500 Dec. 28, 2018 Page 50 of 51 R-IN32M3 Series Data Sheet 3.7 3. Specifications Window Watchdog Timer 3.7.1 Features - Operation mode after reset selectable by using start-up option - Software triggered start mode - Error mode options Generates an NMI request on error detection Generates a reset on error detection - Window watchdog function - Overflow interval time 25MHz operation: 163 s to 5.36 s R18DS0008EJ0500 Dec. 28, 2018 Page 51 of 52 R-IN32M3 Series Data Sheet 3.8 3.8.1 3. Specifications Timer Array Unit Features -1 unit with 4 channels is provided -32-bit counter and 32-bit data registers per channel -Independent channel operation -Synchronous channel operation (master and slave operation) -Generation of different types of output signals -Counter can be triggered by an external signal -Interrupt generation Independent Channel Operation Independent channel operation functions Interval timer function Synchronous Channel Operation Synchronous channel operation function PWM output function External input interval timer function External event count function Independent channel signal measurement functions Overflow interrupt output function External input period count detection function External input pulse interval judgment function External input signal width judgment function Other independent channel function External input position detection function -Supplementary note Timers support prescaler options: count clock selectable from among four types of internal clocks as well as from an external clock. Each timer may be configured to PCLK frequency divided by 20 to 215, and one clock may be configured to be further divided by 1 to 256. R18DS0008EJ0500 Dec. 28, 2018 Page 52 of 53 R-IN32M3 Series Data Sheet 3.9 3. Specifications Asynchronous Serial Interface 3.9.1 Features -Full-duplex communication via built-in receive and transmit FIFOs Internal 10-bit x 16 receive data FIFO Internal 8-bit x 16 transmit data FIFO -2-pin configuration Transmit data output pin Receive data input pin -Error detection functions Rx parity error Rx framing error Tx data consistency error -Tx FIFO overflow error Rx FIFO overrun error Rx timeout error Rx BF receive error -FIFO status information Rx FIFO full/empty status Tx FIFO empty/empty status Rx FIFO fill level Tx FIFO fill level -Interrupt requests: 3 Transmission interrupt Reception interrupt Status interrupt -Character length: 7 or 8 bits -Parity options: odd, even, 0, none -Transmission stop bits: 1 or 2 bits -MSB-/LSB-first transfer selectable -Transmit/receive data inverted input/output possible -13 to 20 bits selectable for the BF (Break Field) in the LIN (Local Interconnect Network) communication format Recognition of 11 bits or more possible for BF reception in LIN communication format BF reception flag provided -BF reception can be detected during data communication -Bus monitor function to keep data consistency of the transmit data -Supported Baud rate: 300 to 12,500,000bps R18DS0008EJ0500 Dec. 28, 2018 Page 53 of 54 R-IN32M3 Series Data Sheet 3. Specifications Table 3.3 Baud Rate Generator Clocks Output (PCLK: 100 MHz) Baud Rate (bps) Prescaler Clock (PRSCLK) Baud Rate Clock (BRCLK) Divisor "URTJnPRS" Divisor "URTJnBRS" ERR (%) 300 6 2604 0.01 600 5 2604 0.01 1200 4 2604 0.01 2400 3 2604 0.01 4800 2 2604 0.01 9600 1 2604 0.01 19200 0 2604 0.01 31250 0 1600 0.01 38400 0 1302 0.01 76800 0 651 0.01 115200 0 434 0.01 153600 0 326 -0.15 312500 0 160 0.00 1000000 0 50 0.00 2000000 0 25 0.00 2500000 0 20 0.00 5000000 0 10 0.00 6250000 0 8 0.00 1000000 0 5 0.00 1250000 0 4 0.00 R18DS0008EJ0500 Dec. 28, 2018 Page 54 of 55 R-IN32M3 Series Data Sheet 3.10 3. Specifications Clocked Serial Interface 3.10.1 Features - Three-wire serial synchronous data transfer - Master mode and slave mode selectable - Multiple slaves configuration plus RCB (Recessive Configuration for Broadcasting) thanks to two configurable chip select output signals - Built-in baud rate generator - Adjustable baud rate; in slave mode it is determined by the input clock - Maximum transmission speed: (at 100 MHz PCLK operation) in master mode: PCLK/4 (25 MHz) in slave mode: PCLK/6 (16.6 MHz) - Phase of clock and data selectable - Data transfer with MSB or LSB first selectable - Transfer data length selectable from 7 to 16 bits in 1-bit increments - Extended data length (EDL) function for transferring more than 16 bits of data - Three selectable transfer modes: Transmission mode Reception mode Transmission and reception mode - Error detection (data consistency check, parity, timeout, overflow, overrun) - Full support of job concept - 128 words I/O buffer memory - Memory mode selectable (FIFO, dual buffer, Tx-only buffer, direct access) - Four different interrupt request signals communication interrupt reception interrupt error interrupt job completion interrupt - Loop back mode (LBM) function for self-test R18DS0008EJ0500 Dec. 28, 2018 Page 55 of 56 R-IN32M3 Series Data Sheet 3.11 3. Specifications I2C Bus 3.11.1 Features - Operating mode Standard mode (serial clock frequency: 100 kHz max.) Fast mode (serial clock frequency: 400 kHz max.) - Transfer mode Single transfer mode Continuous transfer mode - Pin configuration Serial clock pin Serial transmit/receive data pin - Interrupt request signal Data transmit/receive interrupt request signal Status interrupt request signal - Communication data length 8 bits - Multi master support Multiple masters can control the bus simultaneously. - Serial clock signal level width Serial clock signal (SCLn) high- and low-level pulse width can be changed. - Automatic detection Start and stop conditions can be detected automatically R18DS0008EJ0500 Dec. 28, 2018 Page 56 of 57 R-IN32M3 Series Data Sheet 3.12 3. Specifications CC-Link Function The outline specifications of CC-Link are as follows. Please refer to the following URL for the additional details of CC-Link. https://www.cc-link.org/en/ Table 3.4 CC-Link Outline Specifications Item Specification Version Ver.1.10 and Ver.2.00 Supported stations Intelligent device station and Remote device station Maximum number of link points Remote I/O: 8192 points each, Remote register: 2048 words Total number of slave stations 64 units Communication speed and 10 Mbps: 100 m maximum overall cable extension 5 Mbps: 160 m length 2.5 Mbps: 400 m 625 kbps: 900 m 156 kbps: 1200 m Communication system Broadcast polling system Caution: To use a remote device station, it is necessary to connect CCS_REFSTB pin (P10) to a port pin with the external interrupt function (INTPZ). R18DS0008EJ0500 Dec. 28, 2018 Page 57 of 58 R-IN32M3 Series Data Sheet 3.13 3. Specifications CAN Controller 3.13.1 Features - Compliant with ISO-11898 - Standard frame and extended frame transmission/reception enabled - Transfer rate: 1 Mbps max. - 64 message buffers per channel - Receive/transmit history list function (can be set individually for each message buffer) - Automatic block transmission function - Multi-buffer receive block function - Mask setting of 8 patterns is possible for each channel, applicable for data and remote frames - Data bit time, communication baud rate and sample point can be controlled For example: 66.7%, 70.0%, 75.0%, 80.0%, 81.3%, 85.0%, 87.5% Baud rates in the range of 10 kbps up to 1 Mbps can be configured - Enhanced features: Each message buffer can be configured to operate as a transmit or a receive message buffer A transmission request can be aborted by clearing the Transmit-Request flag of the relevant message buffer. Supported by Transmission Abort Interrupt, on successful abortion. Automatic block transmission operation mode (ABT) Time stamp function in collaboration with timers capture channels A centralized global data update bit monitor register makes it possible to check all data update bits from one location R18DS0008EJ0500 Dec. 28, 2018 Page 58 of 59 R-IN32M3 Series Data Sheet 3.14 3. Specifications External MCU Interface The external MCU interface is used to connect external MCUs. It functions both as an I/O port and an interface with external memory. The pin for the external MCU interface also functions for the external memory interface. The external MCU interface can be used when the high level is applied to the MEMIFSEL pin. After the power for the module is turned on, the level of the pin needs to be determined before the module is released from a reset state. This module does not support dynamic switching of levels. 3.14.1 (1) Features External MCU interface - Interface system Asynchronous SRAM with wait control (for reading and writing) Page ROM reading with wait control - Synchronous relationship (set up with the HIFSYNC pin) HBUSCLK synchronous mode (max. 50 MHz), asynchronous mode Caution: Drive the HBUSCLK pin to low when asynchronous mode is to be used. - Bus width (set up with the BUS32EN pin) 32 bits / 16 bits Remark: The module does not support 8-bit bus width. - Transfer data size 32 bits / 16 bits / 8 bits - Buffers Write buffer: Two stages (synchronous mode is selected) or one stage (asynchronous mode is selected) Read buffer: Advance reading of up to 32 bytes is possible. - Transfer type Single transfer Page read transfer - Timing control function R18DS0008EJ0500 Dec. 28, 2018 Page 59 of 60 R-IN32M3 Series Data Sheet (2) 3. Specifications AHB master port function - AMBA Ver. 2.0 compliant 32-bit AHB-Lite Little endian fixed - Address conversion 4-Gbyte resource in the AHB memory area can be assigned as the area for the external MCU interface - Bus sizing External 16-bit => 32-bit - Error response (3) Outputs an interrupt request HERROUTZ in response to reception of an error Access information which involves the error source is stored in the register Status check function - Check status of: Internal reset (available in synchronous/asynchronous SRAM interface mode) The HIFSYNC pin, the BUS32EN pin R18DS0008EJ0500 Dec. 28, 2018 Page 60 of 61 R-IN32M3 Series Data Sheet 3.15 3. Specifications Asynchronous SRAM Memory Controller The asynchronous SRAM memory controller is connectable to external paged ROM, ROM, and SRAM through a 16- or 32-bit bus. It is also connectable to peripheral devices compliant with the SRAM interface. The pin functions for the asynchronous SRAM memory controller are multiplexed with those for the synchronous burst access memory controller and the external MCU interface, and the asynchronous controller can be used when the low level is applied to both the MEMCSEL and MEMIFSEL pins. When both the BOOT0 and BOOT1 pins are at the low level, booting is from the memory connected to CSZ0. 3.15.1 Features - Memory controller supporting page ROM, ROM, SRAM - 32- or 16-bit data Bus - Static memory control SRAM and I/O connection Page ROM connection (CSZ0 only) Four chip select signals are available (CSZ0-CSZ3) CSZ0: page ROM / SRAM: 1000 0000H-13FF_FFFFH (64 Mbytes) CSZ1: SRAM only: 1400 0000H-17FF_FFFFH (64 Mbytes) CSZ2: SRAM only: 1800 0000H-1BFF_FFFFH (64 Mbytes) CSZ3: SRAM only: 1C00 0000H-1FFF_FFFFH (64 Mbytes) - Programmable wait Address setup wait Data wait Write recovery wait Idle wait R18DS0008EJ0500 Dec. 28, 2018 Page 61 of 62 R-IN32M3 Series Data Sheet 3.16 3. Specifications Synchronous Burst Access Memory Controller The synchronous burst access memory controller can be used to connect external page ROM, ROM, SRAM, PSRAM, NOR-Flash, and peripheral devices with an interface similar to the SRAM interface via the 32/16-bit bus. By setting the ADMUXMODE pin to high level, the address signals can be multiplexed to be output from data pins. The synchronous burst access memory controller and asynchronous SRAM memory controller share external microcontroller interface pins. Using these pins for the synchronous burst access memory controller is selected when the MEMCSEL pin outputs a high level and the MEMIFSEL pin outputs a low level. The CPU is booted from the memory connected to CSZ0 when the BOOT0 pin outputs a low level and the BOOT1 pin outputs a high level. 3.16.1 Features - Memory controller supporting page ROM, ROM, SRAM (synchronous /asynchronous), PSRAM and NOR-Flash - 32- or 16-bit data bus - Address / data multiplex feature Remark: Page access is possible only when performing asynchronous access in separate bus mode. - Static memory control External connection of SRAM (synchronous, asynchronous) and other peripheral devices with an interface Four chip select signals are available (CSZ0-CSZ3) similar to the SRAM interface CSZ0: 1000 0000H-13FF_FFFFH (64 Mbytes) CSZ1: 1400 0000H-17FF_FFFFH (64 Mbytes) CSZ2: 1800 0000H-1BFF_FFFFH (64 Mbytes) CSZ3: 1C00 0000H-1FFF_FFFFH (64 Mbytes) Remark: Chip select areas can be assigned to the area between addresses 1000_0000H 1FFF_FFFFH by using the SMADSEL register (specified in 16-MB units). - Programmable wait - Memory access frequency (by dividing 100 MHz signal by 2 to 6) - Up to four wait state signals available (WAITZ, WAITZ1 to WAITZ3) R18DS0008EJ0500 Dec. 28, 2018 Page 62 of 63 R-IN32M3 Series Data Sheet 3.17 3. Specifications Instruction RAM The instruction RAM is 768 Kbytes of memory that can be accessed from I-code AHB, D-code AHB, DMAC or an external MCU. 3.17.1 Features - 128-bit (32-bit x 4) read buffer - Latency: latency is 2 in read access in general but 1 in the case of hitting the read buffer. latency is 1 in write access. - AHB bus width: 32 bits - RAM data bus width: 128 bits (without ECC circuit) - Transfer size: 16- or 32-bit transfer selectable - Burst transfer: single burst transfer, burst transfer of the required length, burst transfer of the fixed length (INCR4/8/16, WRAP4/8/16) - Little endian fixed - ECC response: 1-bit error correction, 2-bit error detection 3.17.2 Read Buffer - 128-bit (32bit x 4) read buffer - Response to the AHB involves no waiting in the case of hitting the read buffer - Clear the data in the read buffer when a 2-bit ECC error occurs. - A 2-bit ECC error at the time of the read response generates an ECC error interrupt. 3.17.3 Write Interface - When 16-bit write access arises, write to the RAM in 32-bit units through two consecutive rounds of access. - When 8-bit write access arises, return an error response. Caution: Write access by an external MCU in 16-bit units may occur. The specification assumes that such access to the RAM will always proceed two consecutive times (for the writing of data in 32-bit units). R18DS0008EJ0500 Dec. 28, 2018 Page 63 of 64 R-IN32M3 Series Data Sheet 3.18 3. Specifications Data RAM The internal data RAM is a 512-Kbyte RAM that can be accessed from the AHB and Header Endec (communication bus). 3.18.1 Features - AHB latency: latency is 1 in read and write access (latency is 2 in read access following write access). - Communication bus latency: latency is 1 in read and write access - Arbitration of access when contention arises: Round robin - AHB bus width: 32 bits - Communication bus width: 128 bits - RAM bus width: 128 bits (without ECC circuit) - AHB transfer size: 8/16/ 32-bit selectable - Communication bus transfer size: 8/16/32/128-bit selectable - Burst transmission: single burst transfer, burst transfer of the required length, burst transfer of the fixed length (INCR4/8/16, WRAP4/8/16) - Little endian fixed - ECC response: 1-bit error correction, 2-bit error detection R18DS0008EJ0500 Dec. 28, 2018 Page 64 of 65 R-IN32M3 Series Data Sheet 3.19 3. Specifications Buffer RAM Buffer RAM is 64KByte of memory that can be accessed by the AHB and communication bus. 3.19.1 Features - Communication-bus latency: latency is 1 in read and write access - Arbitration of access when contention arises: Fixed priority (the communication bus is given priority) - Communication bus width: 128 bits - RAM bus width: 128 bits (without ECC circuit) - Communication-bus transfer size: 8-, 16-, 32-, 128-bit transfer selectable - ECC response: 1-bit error correction, 2-bit error detection R18DS0008EJ0500 Dec. 28, 2018 Page 65 of 66 R-IN32M3 Series Data Sheet 3.20 3. Specifications Hardware Real-time OS The Hardware Real-time OS supports 30 types of system-calls including event, semaphore and mailbox. 3.20.1 Outline of Features -Task Scheduler Hardware ISR: 32 routines selectable from 128 interrupt sources Number of contexts elements: 64 Number of semaphore identifiers: 128 Number of event identifiers: 64 Number of mailbox identifiers: 64 Number of mailbox elements: 192 Number of context priority levels: 16 -Hardware Function Manager -Internal DMA -Buffer allocator -Header EnDec Remark: The hardware real-time OS can be controlled by using the ITRON system calls provided by the sample driver. For how to use the driver, see the R-IN32M3 Series Programming Manual (OS). R18DS0008EJ0500 Dec. 28, 2018 Page 66 of 67 R-IN32M3 Series Data Sheet 3. Specifications MT BUS CortexTM-M3 AHB BUS Bridge GP BUS I/F System call Control Signal Context Cotrol Register Mail Box CNTX Type 0 [1:0] CNTX Type 0 [1:0] PRTY 0 [1:0] PRTY 0 [1:0] CNTX_STAT_0 [2:0] CNTX_STAT_n [2:0] INIT_ADD_0 [31:0] INIT_ADD_n [31:0] WT_RSN_0 WT_RSN_n SM_ID_0 [7:0] SM_ID_n [7:0] EVENT_ID_0 [7:0] EVENT_FLG_0 [15:0] ............ SEMAPHORE Table EVENT Table EVENT_ID_n [7:0] EVENT_FLG_n [15:0] FLG_CND_0 FLG_CND_n WT_TIMOUT_0 WT_TIMOUT_n AT_CLR_0 AT_CLR_n RSDN_TIM_0 RSDN_TIM_n HWFUNC_ID_0 HWFUNC_ID_n CLL_TYP_0 CLL_TYP_n RSLT_RG_0 RSLT_RG_n CONTX_0 CONTX_n n = max 63 HW HW HW Function HW Function HW Function Function Function Interrupts SELECT Controller Scheduler HW Function Manager Interrupt Manager RTOS Core Figure 3.1 Structure of Hardware Real-time OS R18DS0008EJ0500 Dec. 28, 2018 Page 67 of 68 R-IN32M3 Series Data Sheet 3.21 3.21.1 3. Specifications Port Functions Features - 96 I/O ports - Shared with I/O ports of other peripheral circuits - Ports can be designated as input or output on 1-bit basis Cautions 1: Switching from a signal for a peripheral module that is multiplexed with a port pin to port mode might lead to a spike, depending on the state of the pin at the time. The following general countermeasure for spikes should therefore be implemented in software. Switch the pin function while the peripheral function is stopped. If the multiplexed pin function in use is an interrupt signal, clear the interrupt request flag and then remove masking of the interrupt. Only switch the mode after the output value is fixed. 2: Do not externally apply an intermediate voltage to input buffers because these buffers do not implement through-current countermeasures. 3.21.2 Port Configuration The R-IN32M3-EC incorporates eight 3-state I/O ports and four real-time control ports. Input or output mode can be specified for ports in 1-bit units. The basic structure of ports is the 8-bit unit, but ports P0x-P3x, P4x-P7x, and RP0x-RP3x (x = 0-7) can also be grouped to enable reading and writing in 32-bit units. The real-time port pins (RP00 to RP37) can be used for input and output in synchronization with interrupt signals. Each port allows access in 8-, 16-, or 32-bit access depending on the setting of the corresponding register. R18DS0008EJ0500 Dec. 28, 2018 Page 68 of 69 R-IN32M3 Series Data Sheet 4. Electrical Specifications 4. Electrical Specifications 4.1 Terminology Table 4.1 Terms Used in Absolute Maximum Ratings Parameter Power supply voltage Symbol VDD Meaning Indicates the voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Input voltage VI Indicates the voltage range within which damage or reduced reliability will not Output voltage VO Output current IO Indicates the absolute tolerance value for DC current to prevent damage or Operating ambient TA Indicates the ambient temperature range for normal logic operations. Tstg Indicates the element temperature range within which damage or reduced result when power is applied to an input pin. Indicates the voltage range within which damage or reduced reliability will not result when power is applied to an output pin. reduced reliability when a current flows out of or into an output pin. temperature Storage temperature reliability will not result while no voltage or current is being applied to the device. Table 4.2 Terms Used in Recommended Operating Range Ratings Parameter Symbol Meaning Power supply voltage VDD Indicates the voltage range for normal logic operations that occur when VSS = 0 V. Input voltage, high VIH Indicates the voltage, which is applied to the input pins of R-IN32M3, is the voltage indicates that the high level state for normal operation of the input buffer. -If a voltage that is equal to or greater than the "Min." value is applied, the input voltage is guaranteed as a high level voltage. Input voltage, low VIL Indicates the voltage, which is applied to the input pins of R-IN32M3, is the voltage indicates that the low level state for normal operation of the input buffer. -If a voltage that is equal to or less than the "Max." value is applied, the input voltage is guaranteed as a low level voltage. Positive trigger voltage VP Indicates the input level at which the output level is inverted when the input to R-IN32M3 is changed from the low-level side to the high-level side. Negative trigger voltage VN Indicates the input level at which the output level is inverted when the input to R-IN32M3 is changed from the high-level side to the low-level side. Hysteresis Voltage VH Indicates the differential between the positive trigger voltage and the negative Input rise time tried, Indicates the limit value for the time period when an input voltage applied to tric, R-IN32M3 rises from 10% to 90%. tried, tric, and tris each indicate the input rise time tris for the data clock and Schmitt buffer. trigger voltage. Input fall time R18DS0008EJ0500 Dec. 28, 2018 tfid, Indicates the limit value for the time period when an input voltage applied to tfic, R-IN32M3 falls from 90% to 10%. tfid, tfic, and tfis each indicate the input fall time for tfis the data clock and Schmitt buffer. Page 69 of 70 R-IN32M3 Series Data Sheet 4. Electrical Specifications Table 4.3 Terms Used for DC Characteristics Parameter Off-state output current Symbol IOZ Meaning Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Output short circuit IOS current Indicates the current that flows when the output pins are shorted (to GND pins) when output is at high level. Input leakage current ILI Indicates the current that flows via an input pin when a voltage is applied to that pin. Output current, low IOL Indicates the current that flows to the output pins when the rated low-level output Output current, high IOH Output voltage, low VOL Indicates the output voltage at low level and when the output pin is open. Output voltage, high VOH Indicates the output voltage at high level and when the output pin is open. voltage is being applied. Indicates the current that flows from the output pins when the rated high-level output voltage is being applied. 4.2 Absolute Maximum Ratings Table4.4 Absolute Maximum Ratings Parameter Power supply voltage I/O voltage Symbol VDD VI /VO Output current (3.3 V buffer) IO Conditions Ratings Unit 1.0V type -0.5 to +1.4 V 1.5 V type <R> -0.5 to +2.0 V 3.3 V type -0.5 to +4.6 V 3.3 V buffer VI /VO < VDD + 0.5V -0.5 to +4.6 V 5V-Tolerant buffer VI /VO < VDD + 3.0V -0.5 to +6.6 V 6 mA type 15 mA 12 mA type 25 mA Output current (5V-Tolerant buffer) IO 4 mA type 10.35 mA Operating ambient temperature TA - -40 to +85 C Storage temperature Tstg - -65 to +125 C Caution: Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark: 3.3 V must be applied to the I/O pins only after applying the power supply voltage. R18DS0008EJ0500 Dec. 28, 2018 Page 70 of 71 R-IN32M3 Series Data Sheet 4.3 4. Electrical Specifications Recommended Operating Conditions Table 4.5 Recommended Operating Conditions Parameter Power supply voltage Negative trigger voltage Positive trigger voltage Hysteresis voltage Symbol VDD VN VP VH Input voltage, low VIL Input voltage, high VIH MIN. TYP. MAX. Unit 1.0 V power supply Conditions 0.9 1.0 1.1 V 1.5 V power supply <R> 1.35 1.5 1.65 V 3.3 V power supply 3.0 3.3 3.6 V 3.3 V buffer 0.6 - 1.8 V 5 V tolerant buffer 0.8 - 1.1 V 3.3 V buffer 1.2 - 2.4 V 5 V tolerant buffer 1.7 - 2.2 V 3.3 V buffer 0.3 - 1.5 V 5 V tolerant buffer 0.9 - 1.1 V 3.3 V buffer -0.3 - 0.8 V 5 V tolerant buffer Input rise/fall time Input rise/fall time (clock) Input rise/fall time (Schmitt input) Operating ambient temperature R18DS0008EJ0500 Dec. 28, 2018 0 - 0.8 V 3.3 V buffer 2.0 - VDD + 0.3 V 5 V tolerant buffer 2.0 - 5.5 V tried - 0 - 200 ns tfid - 0 - 200 ns tric - 0 - 4 ns tfic - 0 - 4 ns tris - 0 - 1 ms tfis - 0 - 1 ms TA - -40 - 85 C Page 71 of 72 R-IN32M3 Series Data Sheet 4.4 4. Electrical Specifications DC Characteristics Table 4.6 DC Characteristics (VDD = 3.3 0.3 V, TA = -40 to +85C) (1/2) Parameter Supply current Symbol IDD Conditions VI = VDD or GND MIN. TYP. MAX. Unit - - - - 1.0V - 270 880 mA 3.3 V - 210 220 mA - - - - 270 880 mA With an internal regulator (R-IN32M3-EC) Without an internal regulator 1.0V 3.3 V 120 130 mA - 150 170 mA 1.0V - 280 890 mA 3.3 V - 45 50 mA 3.3 V output - - 10 A 5V-tolerant buffer - - 10 A - - - -250 mA - - 10 A -28.9 -65.7 -129.8 A 10.2 43.4 83.9 A 39.0 - 100.9 A 1.5V IDD Supply current VI = VDD or GND (R-IN32M3-CL) Off-state current Output short circuit current Note Input leakage current IOZ VI = VDD or GND IOS VO = GND II VI = VDD or GND Normal input VI = GND With pull-up resistor (3.3 V buffer) (50k) VI = VDD With pull-down resistor (50k) Input leakage current (5V-tolerant buffer) II VI = GND With pull-up resistor (50k) Note: The output short circuit time is no more than one second and is only for one pin on the LSI. Remark: In the notes for the table, the (+) and (-) signs indicate the current direction. Current flowing to the device is indicated by (+) and current flowing out is indicated by (-). Table 4.7 DC Characteristics (VDD = 3.3 0.3 V, TA = -40 to +85oC) (2/2) Parameter Output current, low Symbol IOL Conditions VOL = 0.4V (3.3 V buffer) Output current, low MIN. TYP. MAX. Unit 6 mA type 6.0 - - mA 12 mA type 12.0 - - mA 4.0 - - IOL VOL = 0.4V 4 mA type IOH VOH = 2.4V 6 mA type -6.0 - - mA 12 mA type -12.0 - - mA 4 mA type -4.0 - - - - 0.1 V (5V-Tolerant buffer) Output current, high (3.3 V buffer) Output current, high IOH VOH = 2.4V Output voltage, low VOL IOL = 0 mA Output voltage, high VOH IOH = 0 mA (5V-Tolerant buffer) 3.3 V buffer 5V-Tolerant buffer R18DS0008EJ0500 Dec. 28, 2018 mA mA - - 0.1 V 3.3 V buffer VDD - 0.1 - - V 5V-Tolerant buffer VDD - 0.1 - - V Page 72 of 73 R-IN32M3 Series Data Sheet 4.5 4. Electrical Specifications Pull-up/Pull-down Resistor Values Table 4.8 Pull-up/Pull-down Resistor Values (VDD = 3.3 0.3 V, TA = -40 to +85oC) MIN. TYP. MAX. Unit Pull-up resistor (3.3 V buffer) Parameter 50k 27.7 50.2 103.9 k Pull-up resistor (5V-Tolerant buffer) 50k 35.7 51.2 77.0 k Pull-down resistor (3.3 V buffer) 50k 42.9 76.1 295.5 k 4.6 Library Specification Terminal Capacity Values Table 4.9 Terminal Capacity Values Parameter MIN. TYP. MAX. Unit 5.0 - 7.0 pF Output Buffer 5.0 - 7.0 pF I/O Buffer 5.0 - 7.0 pF Input Buffer R18DS0008EJ0500 Dec. 28, 2018 Symbol CB Page 73 of 74 R-IN32M3 Series Data Sheet 4.7 4. Electrical Specifications Power-on/off sequence The power circuit for the R-IN32M3 products consists of an internal power supply (VDD10: 1.0V), I/O power supply (VDD33: 3.3 V) and PHY power supply (VDD15: 1.5V). (PHY power only applies to R-IN32M3-EC.) Supply power to the internal circuit then to the I/O circuit. Conversely, cut-off power to the I/O circuit then internal circuit. This is not a stipulated sequence for power supply (See Figure 4.1). If power to the I/O circuit is supplied before power to the internal circuit is supplied, the mode of the I/O buffer will not be determined until the internal circuit starts up and thus the output values become unstable regardless of the mode of the buffer. Also, be sure to apply 3.3 V to the I/O pins after the power supply voltage has been decided. Regardless of the power on/off sequence, the time difference between the startup of the first module and the levels of both modules having been stabilized should fall within 100 ms. Here, the time to be measured is when the voltage of each module is at 0.1 VDD to 0.9 VDD. I/O voltage VDD33 0.9 VDD33 PHY voltageNote VDD15 Internal voltage VDD10 GND 100ms 0.1 VDD10 100ms 0.1 VDD10 Figure 4.1 Recommended Sequence of Power-on/off Note: The recommendation for time difference should also be applied to the PHY module only when a build-in regulator of an R-IN32M3-EC is not in use. R18DS0008EJ0500 Dec. 28, 2018 Page 74 of 75 R-IN32M3 Series Data Sheet 4.8 4. Electrical Specifications AC Characteristics 4.8.1 (1) Clock Pins Input clock Parameter Symbol XT1, XT2 ETH0_TXC, ETH1_TXC Note Conditions tSYSCLK - MIN MAX Unit 25 50ppm MHz tTXC - - 25 MHz ETH0_RXC, ETH1_RXC Note tRXC - - 125 MHz CCM_CLK80M tCCLCLK - 80 50ppm MHz CCI_CLK2_097M Note tCCLIECLK - 2.097152 100ppm MHz HBUSCLK tHBUSCLK - - 50 MHz CSISCK0, CSISCK1 tCSISSCK Slave mode - 16.6 MHz TCK tTCK - - 50. MHz MIN MAX Unit 10 - ns 0.5 x tBUSCLK - 2.0 0.5 x tBUSCLK + 2.0 ns 0.5 x tBUSCLK - 2.0 0.5 x tBUSCLK + 2.0 ns - 1.2 ns Note: This applies to R-IN32M3-CL only. (2) Output clock Parameter Symbol Conditions BUSCLK output cycle tBUSCLK BUSCLK high level width tBCKH BUSCLK low level width tBCKL BUSCLK rising time tBCKR BUSCLK falling time tBCKF - 1.2 ns CLKOUT25MnNote1 output cycle tCO25M 40 - ns CLKOUT25MnNote1 high 0.5 x tBUSCLK - 5.3 0.5 x tBUSCLK + 5.3 ns 0.5 x tBUSCLK - 5.3 0.5 x tBUSCLK + 5.3 ns - 3.4 ns level width tCO25MH CLKOUT25MnNote1 low level width tCO25ML CLKOUT25MnNote1 tCO25MR rise time CLKOUT25MnNote1 fall time CL = 15pF CL = 15pF tCO25MF ETHn_GTXC Note1 output frequency tGTXC CSISCKn output frequency tCSIMSCK SCLn output frequency tSCL CL = 13pF Master mode CL = 15pF High speed mode CL = 30pF - 3.4 ns - 125 MHz - 25 MHz - 400 KHz MHz SMSCK output frequency tSMSCK CL = 15pF - 50 CATI2CCLK Note2 t ECIICCLK CL = 30pF - 148.8 kHz t TRACECLK CL = 15pF - 50 MHz output frequency TRACECLK output frequency Notes 1. Only applies to R-IN32M3-CL. 2. Only applies to R-IN32M3-EC. Remark: n = 0 or1 R18DS0008EJ0500 Dec. 28, 2018 Page 75 of 76 R-IN32M3 Series Data Sheet 4. Electrical Specifications BUSCLK (output) < tBCKR > < tBCKF > < tBCKH > < tBCKL > < tBUSCLK > CLKOUT25Mn (output) < tCO25MF > < tCO25MR > < tCO25MH > < tCO25ML > < tCO25M > Figure 4.2 Output Clock Timing Diagram Remarks 1: For the output timing of other clocks, see the sections of AC characteristics for the individual interfaces. 2: n = 0, 1 R18DS0008EJ0500 Dec. 28, 2018 Page 76 of 77 R-IN32M3 Series Data Sheet 4.8.2 4. Electrical Specifications Reset Pins Parameter Symbol Conditions RESETZ low level width tWRSL - HOTRESETZ Note low level width tWHRSL - PONRZ low level width tWPRSL - PONRZ input timing (to RESETZ) tSKPR - MIN Secure enough time for the external oscillator to be stabilized + 1 sec. 0 MAX Unit - ns - ns - ns - ns < tWRSL > RESETZ (input) < tWHRSL > HOTRESETZ (input)Note < tWPRSL > PONRZ (input) < tSKPR > Figure 4.3 Reset Timing Diagram Note: Only applies to R-IN32M3-CL. R18DS0008EJ0500 Dec. 28, 2018 Page 77 of 78 R-IN32M3 Series Data Sheet 4.8.3 (1) 4. Electrical Specifications External Memory Interface Pins Calculating value for delay due to an external load The values for transition delay of the external memory interface pins of the R-IN32M3 products do not consider external load on them because it depends on the user environment. Calculate the value for delay in consideration with the load under your environment and also with wiring delays on the printed board. Drive capability Delay value per pF (ns) MIN. MAX. 6 mA 0.026 0.067 12 mA 0.012 0.034 Example) When an address pin (6- mA output buffer) has 30-pF load, the actual delay is as follows. MIN.: 1.0 ns (The MIN delay value at the time of 0 pF) + (0.026x30) ns = 1.78ns MAX.: 7.0 ns (The MAX delay value at the time of 0 pF) + (0.067x30) ns = 9.01ns (2) Asynchronous SRAM MEMC access timing Parameter Symbol Address, CSZ0-CSZ3 output delay time (from BUSCLK) tDKA RDZ output delay time (from BUSCLK) tDKRD WRZ0 - WRZ3 (BENZ0-BENZ3), WRSTBZ output delay time MIN MAX 1.0 7.0 (1.78) Note (9.01) Note 1.0 7.0 (1.78) Note (9.01) Note 1.0 7.0 Unit ns ns (from BUSCLK) tDKWR BCYSTZ output delay time (from BUSCLK) tDKBSL WAITZ input setup time (to BUSCLK) tSKW 4.0 - ns WAITZ input hold time (to BUSCLK) tHKW 0 - ns Date input setup time (from BUSCLK) tSKID 4.0 - ns Data input hold time (from BUSCLK) tHKID 0 - ns Date output delay time (from BUSCLK) tDKOD Data float delay time (from BUSCLK) tHKOD (1.78) Note 1.0 (1.78) (9.01) Note 7.0 Note (9.01) Note 1.0 7.0 (1.78) Note (9.01) Note 1.0 7.0 (1.78) Note (9.01) Note ns ns ns ns Note: Values in parenthesis are based on a 30pF capacitive load. R18DS0008EJ0500 Dec. 28, 2018 Page 78 of 79 R-IN32M3 Series Data Sheet (a) 4. Electrical Specifications Read timing BUSCLK (output) < tDKA > A1-A26 (output) < tDKA > < tDKA > < tDKWR > < tDKWR > < tDKRD > < tDKRD > CSZ0-CSZ3 (output) WRZ0-WRZ3note, WRSTB (output) BENZ0-BENZ3note (output) RDZ (output) < tHKID > < tHKOD > < tSK ID > D0-D31 (i/o) < tHKW > < tSK W > WAITZ (input) < tDKBS > < tDKBS > BCYSTZ (output) Figure 4.4 Memory Controller Read Timing Diagram (Asynchronous Memory) Note: The WRZ0-WRZ3 pins function both as WRZ0-WRZ3 and BENZ0-BENZ3. These pins function as BENZ0-BENZ3 after a reset and can be switched with the write enable switch registers (WREN). For details, see section 9.3.5, Write Enable Switch Registers (WREN), in the R-IN32M3 Series User's Manual: Peripheral Modules. Remark: Above timing shows the case for when "Idle Wait", "Write Recovery Wait", and "Address Wait" are set to 0, and "Data Wait" is set to 3. R18DS0008EJ0500 Dec. 28, 2018 Page 79 of 80 R-IN32M3 Series Data Sheet (b) 4. Electrical Specifications Write timing BUSCLK (output) < tDKA > A1-A26 (output) < tDKA > < tDKA > CSZ0-CSZ3 (output) < tDKWR > < tDKWR > WRZ0-WRZ3note, WRSTB (output) < tDKWR > < tDKWR > BENZ0-BENZ3note (output) RDZ (output) < tDKOD > < tHKOD > < tDKOD > D0-D31 (i/o) < tHKW > < tSK W > WAITZ (input) < tDKBS > < tDKBS > BCYSTZ (output) Figure 4.5 Memory Controller Read Timing Diagram (Asynchronous Memory) Note: The WRZ0-WRZ3 pins function both as WRZ0-WRZ3 and BENZ0-BENZ3. These pins function as BENZ0-BENZ3 after a reset and can be switched with the write enable switch registers (WREN). For details, see section 9.3.5, Write Enable Switch Registers (WREN), in the R-IN32M3 Series User's Manual: Peripheral Modules. Remark: Above timing shows the case for when "Idle Wait", "Write Recovery Wait", and "Address Wait" are set to 0, and "Data Wait" is set to 3. R18DS0008EJ0500 Dec. 28, 2018 Page 80 of 81 R-IN32M3 Series Data Sheet (3) 4. Electrical Specifications Synchronous burst access MEMC access timing Parameter BUSCLK output frequency Symbol tBUSCLK Address, CSZ0-CSZ3 output delay time tDKA RDZ output delay time tDKRD WRZ0-WRZ3 (BENZ0-BENZ3), WRSTBZ output delay time MIN tDKWR MAX Unit MHz - 50 1.0 7.8 (1.78) Note (9.81) Note 1.0 7.8 Note (9.81) Note 1.0 7.8 (1.78) Note (9.81) Note (1.78) ns ns ns 1.0 7.8 (1.78) Note (9.81) Note tSKW 5.3 - ns tHKW 0 - ns Data input setup time tSKID 5.3 - ns Data input hold time tHKID ns ADVZ output delay time tDKBSL WAITZ input setup time WAITZ input hold time Data output delay time tDKOD Data float delay time tHKOD 0 - 1.0 7.8 (1.78) Note (9.81) Note 1.0 7.8 (1.78) Note (9.81) Note ns ns ns Note: Values in parenthesis are based on a 30pF capacitive load. R18DS0008EJ0500 Dec. 28, 2018 Page 81 of 82 R-IN32M3 Series Data Sheet (a) 4. Electrical Specifications Read timing BUSCLK (output) (SMCMD_CMCRDLTH:0) BUSCLK (output) (SMCMD_CMCRDLTH:1) < tDKA > < tDKA > CSZ0-CSZ3 (output) WRSTBZ (output) < tDKRD > < tDKRD > RDZ (output) < tHKID > < tHKOD > < tSKID > D0-D31 (i/o) < tHKW > < tSKW > WAITZ, WAITZ1-WAITZ3 (input) < tDKBS > < tDKBS > ADVZ (input) Figure 4.6 Memory Controller Read Timing Diagram (Synchronous Memory) Remark: Above timing is for the case where "t_ceoe" is 2 and "t_rc" is 4. R18DS0008EJ0500 Dec. 28, 2018 Page 82 of 83 R-IN32M3 Series Data Sheet (b) 4. Electrical Specifications Write timing BUSCLK (output) < tDKA > < tDKA > CSZ0-CSZ3 (output) < tDKWR > < tDKWR > WRSTBZ (output) RDZ (output) < tHKOD > < tSKID > < tDKOD > D0-D15 (i/o) < tHKW > < tSKW > WAITZ, WAITZ1-WAITZ3 (input) < tDKBS > < tDKBS > ADVZ (input) Figure 4.7 Memory Controller Write Timing Diagram (Synchronous Memory) Remark: Above timing is for the case where "t_wp" is 2 and "t_wc" is 5. R18DS0008EJ0500 Dec. 28, 2018 Page 83 of 84 R-IN32M3 Series Data Sheet 4.8.4 4. Electrical Specifications External MCU Interface Pins The timing specification of external MCU interface pins are based on a 65pF (HD pins) and 35pF (HWAITZ pin) capacitive load. (1) Synchronous Mode (1/2) No. Parameter Symbol MIN MAX Unit 1 HBUSCLK high-level width tHBHIGH 0.5tHBUSCLK - 2.1 0.5tHBUSCLK + 2.1 ns 2 HBUSCLK low-level width tHBLOW 0.5tHBUSCLK - 2.1 0.5tHBUSCLK + 2.1 ns 3 HBUSCLK input cycle tHBUSCLK 20 - ns 4 Address, HCSZ/HPGCSZ input setup time (to HBUSCLK) tSKHA 4.0 - ns HBENZ0-HBENZ3 (HWRZ0-HWRZ3), tSKHWR 4.0 - ns 5 HWRSTBZ input setup time (to HBUSCLK) 6 Address, HCSZ/HPGCSZ input hold time (from HBUSCLK) tHKHA 1.0 - ns 7 HBENZ0-HBENZ3 (HWRZ0-HWRZ3), tHKHWR 1.0 - ns HWRSTBZ input hold time (from HBUSCLK) 8 HWRZ0-HWRZ3, HWRSTBZ recovery time (high width) tWHWR 35.0 - ns 9 Data input setup time (to HBUSCLK) tSKIHD 4.0 - ns 10 Data input hold time (from HBUSCLK) tHKIHD 1.0 - ns 11 HWAITZ output delay time (from HCSZ, HPGCSZ) tDKHD 2.0 - ns 12 HWAITZ output delay time tDKHWT 2.0 - ns (from HWRSTBZ, HWRZ0-HWRZ3) 13 HWAITZ enable data output delay time (from HBUSCLK) tDKHWTV 2.0 10.0 ns 14 HWAITZ enable data hold time tHKHWTV 3.0 - ns tHKWTWR - 13.6 ns (from HWRSTBZ, HWRZ0-HWRZ3) 15 HWAITZ output hold time (from HWRSTBZ, HWRZ0-HWRZ3) 16 Data, HWAITZ output hold time (from HCSZ/HPGCSZ) tHKWTCS - 13.6 ns 17 Address, HCSZ/HPGCSZ input setup time (to HRDZ) tSKHAHR 4.3 - ns 18 Data at the page access, Address input hold time (from HRDZ) tHKHAHR 4.3 - ns 19 HRDZ recovery time (high width) tWHRD 35.0 - ns 20 Data, HWAITZ output delay time (from HRDZ) tDKHDHR 2.0 - ns 21 HWAITZ enable data output delay time (from HRDZ) tDKWTVHR - 16.4 ns R18DS0008EJ0500 Dec. 28, 2018 Page 84 of 85 R-IN32M3 Series Data Sheet 4. Electrical Specifications (2/2) No. Parameter Symbol MIN MAX Unit 22 Data settle time (from HWAITZ) tSKHDHWT tHBUSCLK - 10 - ns 23 Data, HWAITZ enable data output hold time (from HRDZ) tHKHWTHR 3.0 - ns 24 Data, HWAITZ output hold time (from HRDZ) tHKOHD - 13.6 ns 25 Data at the on-page access, HWAITZ output delay time tDKPON 3.0 16.4 ns tDKPOFF 3.0 16.4 ns tDKWTVCS - 16.4 ns (from the address) 26 Data at the off-page access, HWAITZ output delay time (from the address) 27 HWAITZ enable data output delay time (from HCSZ/HPGCSZ) 28 HRDZ input setup time (to HBUSCLK) tSKHRD 4.0 - ns 29 HRDZ input hold time (to HBUSCLK) tHKHRD 1.0 - ns R18DS0008EJ0500 Dec. 28, 2018 Page 85 of 86 R-IN32M3 Series Data Sheet 4. Electrical Specifications <1> <2> HBUSCLK (input) <3> <4> <6> <4> <6> HCSZ, HPGCSZ (input) HA1-HA20 (input) <5> <7> HBENZ0-HBENZ3 (input) <7> <7> <5> <5> HWRSTBZ (input) HWRZ0-HWRZ3 (input) <8> <8> HRDZ (input) <10> <9> HD0-HD31 (input/output) <13> <16> <15> <12> <13> <14> <11> HWAITZ (output) Figure 4.8 External MCU Write Timing (MEMCSEL = L, HIFSYNC = H) Caution: Supply a stable signal to address/data/control system pins while being accessed. R18DS0008EJ0500 Dec. 28, 2018 Page 86 of 87 R-IN32M3 Series Data Sheet 4. Electrical Specifications <1> <2> HBUSCLK (input) <3> <13> <17> HCSZ, HPGCSZ (input) <17> HA1-HA20 (input) HBENZ0-HBENZ3 (input) HWRSTBZ (input) HWRZ0-HWRZ3 (input) <29> <28> <19> <19> HRDZ (input) <16> <24> <20> <23> <11> HD0-HD31 (input/output) <21> <22> <16> <27> <24> <11> <20> <23> HWAITZ (output) Figure 4.9 External MCU Read Timing (MEMCSEL = L, HIFSYNC = H) Caution: Supply a stable signal to address/data/control system pins while being accessed. R18DS0008EJ0500 Dec. 28, 2018 Page 87 of 88 R-IN32M3 Series Data Sheet 4. Electrical Specifications <1> <2> HBUSCLK (input) <3> <13> <17> HCSZ, HPGCSZ (input) <17> <18> HA4-HA20 (input) <17> HA1-HA3 (input) Off Page On Page Off Page On Page HBENZ0-HBENZ3 (input) HWRSTBZ (input) HWRZ0-HWRZ3 (input) <29> <28> <19> <19> HRDZ (input) <16> <25> <26> <25> <20> <24> <11> <23> HD0-HD31 (input/output) <21> <22> <22> <16> <27> <11> <20> <24> <25> <26> <25> <23> HWAITZ (output) Figure 4.10 External MCU Page Read Timing (MEMCSEL = L, HIFSYNC = H) Caution: Supply a stable signal to address/data/control system pins while being accessed. R18DS0008EJ0500 Dec. 28, 2018 Page 88 of 89 R-IN32M3 Series Data Sheet (2) 4. Electrical Specifications Synchronous Mode (CC-Link IE Field) No. Parameter Symbol MIN MAX Unit 1 HBUSCLK high-level width tHBHIGH 0.5tHBUSCLK-2.1 0.5tHBUSCLK+2.1 ns 2 HBUSCLK low-level width tHBLOW 0.5tHBUSCLK-2.1 0.5tHBUSCLK+2.1 ns 3 HBUSCLK input cycle tHBUSCLK 20 - ns 4 Address, HCSZ/HPGCSZ input setup time (to HBUSCLK) tSKHCS 5.0 - ns 5 HBENZ0-HBENZ3 (HWRZ0-HWRZ3), tSKHWR 5.0 - ns tHKHA 0 - ns HWRSTBZ input setup time (to HBUSCLK) 6 Address, HCSZ/HPGCSZ, HBENZ0-HBENZ3, Data input hold time (from HRDZ, HWRSTBZ, HWRZ0-HWRZ3 7 HWRZ0-HWRZ3, HWRSTBZ recovery time (high width) tWHWR tHBUSCLK x 1 - ns 8 Data input setup time (to HWRSTBZ, HWRZ0- HWRZ3) tSKIHD 0 - ns 9 HWAITZ output delay time (from HCSZ, HPGCSZ) tDKHD 2.0 - ns 10 HWAITZ output delay time (from HWRSTBZ, HWRZ0 - HWRZ3) tDKHWT 2.0 - ns 11 HWAITZ enable data output delay time (from HBUSCLK) tDKHWTV 3.0 11.0 ns tDKHWTV 3.0 11.0 ns tHKHWTV 3.0 - ns "HWAITZ output in synchronization with HBUSCLK" HWAITZ enable data output delay time (from HBUSCLK) "HWAITZ output in synchronization with HBUSCLK" 12 HWAITZ enable data output hold time (from HWRSTBZ, HWRZ0-HWRZ3 13 HWAITZ output hold time (from HWRSTBZ, HWRZ0-HWRZ3 tHKWTWR - 13.6 ns 14 Data, HWAITZ output hold time (from HCSZ, HPGCSZ tHKWTCS - 13.6 ns 15 HRDZ recovery time (high width) tWHRD tHBUSCLK x 1 - ns 16 Data, HWAITZ output delay time (from HRDZ) tDKHDHR 2.0 - ns HWAITZ enable data output delay time (from Latch timing of tDKWTVHR - tHBUSCLK/2 + 11.0 ns tDKWTVHR - tHBUSCLK + 11.0 ns tSKHDHWT - 10Note ns 17 HRDZ, HWWRSTBZ, HWRZ0 - HWRZ3) "HWAITZ output in synchronization with HBUSCLK" HWAITZ enable data output delay time (from Latch timing of HRDZ, HWWRSTBZ, HWRZ0 - HWRZ3) "HWAITZ output in synchronization with HBUSCLK" 18 Data settle time (from HWAITZ) "HWAITZ output in synchronization with HBUSCLK" Data settle time (from HWAITZ) - tHBUSCLK x n tSKHDHWT - "HWAITZ output in synchronization with HBUSCLK" 0Note ns - tHBUSCLK x n 19 Data, HWAITZ enable data output hold time (from HRDZ) tHKHWTHR 3.0 - ns 20 Data, HWAITZ output delay time (from HRDZ) tHKOHD - 13.6 ns 21 HRDZ input setup time (to HBUSCLK) tSKHRD 5.0 - ns R18DS0008EJ0500 Dec. 28, 2018 Page 89 of 90 R-IN32M3 Series Data Sheet 4. Electrical Specifications Remark: When setting the value other than 100B to the CIEWAITDLY register, refer to the value of HWAITZ output in synchronization with HBUSCLK. Note: This indicates the value when WAITDLY2-WAITDLY0 in the CIEWAITDLY register is 100B. n: 000 B = 4, 001B = 3, 010 B = 2, 011 B = 1 R18DS0008EJ0500 Dec. 28, 2018 Page 90 of 91 R-IN32M3 Series Data Sheet 4. Electrical Specifications <1> <2> HBUSCLK (input) <3> <4> <6> <4> <6> <5> <6> HCSZ, HPGCSZ (input) HA1-HA20 (input) HBENZ0-HBENZ3 (input) <5> <7> <7> HWRSTBZ (input) HWRZ0-HWRZ3 (input) HRDZ (input) <6> <8> HD0-HD31 (input/output) <11> <11> <13> <10> <9> <11> <14> <12> HWAITZ (output) "Synchronous mode with a rise of HBUSCLK" <11> <17> <11> HWAITZ (output) "Synchronous mode with a fall of HBUSCLK" Figure 4.11 External MCU Write Timing (MEMCSEL = L, HIFSYNC = H) Caution: Supply a stable signal to address/data/control system pins while being accessed. R18DS0008EJ0500 Dec. 28, 2018 Page 91 of 92 R-IN32M3 Series Data Sheet 4. Electrical Specifications <1> <2> HBUSCLK (input) <3> <4> <6> <4> <6> <5> <6> HCSZ, HPGCSZ (input) HA1-HA20 (input) HBENZ0-HBENZ3 (input) HWRSTBZ (input) HWRZ0-HWRZ3 (input) <15> <21> <15> HRDZ (input) <14> <20> <16> <19> <9> HD0-HD31 (input/output) <14> <11> <17> <20> <18> <11> <19> HWAITZ (output) "Synchronous mode with a rise of HBUSCLK" <11> <17> <11> <18> HWAITZ (output) "Synchronous mode with a fall of HBUSCLK" Figure 4.12 External MCU Read Timing (MEMCSEL = L, HIFSYNC = H) Caution: Supply a stable signal to address/data/control system pins while being accessed. R18DS0008EJ0500 Dec. 28, 2018 Page 92 of 93 R-IN32M3 Series Data Sheet (3) Asynchronous Mode No. 1 4. Electrical Specifications Parameter Address, HCSZ/HPGCSZ, HBENZ0-HBENZ3 input setup time (to HWRSTBZ, HWRZ0-HWRZ3) 2 HWRZ0-HWRZ3, HWRSTBZ recovery time (high width) 3 Data input setup time (to HWRSTBZ, HWRZ0-HWRZ3) Symbol MIN MAX Unit Note1 tADDWRS tWRW tWRS 4.8 - 10xn 35.0 Note1 4.8 - ns - ns - ns - 10xn 4 Data input hold time (from HWRSTBZ, HWRZ0-HWRZ3) tWRH 4.8 - ns 5 HWAITZ output delay time (from HCSZ or HPGCSZ) tCLZ 2.0 - ns 6 HWAITZ output delay time (from HWRSTBZ, HWRZ0-HWRZ3) tWAITD 2.0 - ns 7 HWAITZ enable data output delay time tWRWAITF - 16.4 ns tWAITVH 3.0 - ns (from HWRSTBZ, HWRZ0-HWRZ3) 8 HWAITZ enable data output hold time (from HWRSTBZ, HWRZ0-HWRZ3) 9 HWAITZ output hold time (from HWRZ0-3, HWRSTBZ) tWAITH - 13.6 ns 10 Data, HWAITZ output hold time (from HCSZ/HPGCSZ) tCHZ - 13.6 ns 11 Address, HCSZ/HPGCSZ input setup time (to HRDZ) tADDRDS 4.3Note2 - ns - 10xn 12 Data at the off-page access, Address input hold time (from HRDZ) tADDRDH 4.3 - ns 13 HRDZ recovery time (high width) tRDW 35.0 - ns 14 Data, HWAITZ output delay time (from HRDZ) tRDLZ 2.0 - ns 15 HWAITZ enable data output delay time (from HRDZ) tRDWAITF - 16.4 ns 16 Data settle time (from HWAITZ) tWAITR - -7.5Note3 ns +10xn 17 Data, HWAITZ enable data output hold time (from HRDZ) tDATAOH 3.0 - ns 18 Data, HWAITZ output hold time (from HRDZ) tRDHZ - 13.6 ns 19 Data at the on-page access, HWAITZ output delay time tPAGEOND 3.0 16.4 ns tPAGEOFD 3.0 16.4 ns tWAITVD - 16.4 ns tADDRDHP 4.3 - ns (from the address) 20 Data at the off-page access, HWAITZ output delay time (from the address) 21 HWAITZ enable data output delay time (from HCSZ/HPGCSZ) 22 Address input hold time when advance reading is enabled (from <R> HRDZ) Notes 1. This indicates the value when WRSTD2-WRSTD0 in the HIFBTC register is 000B. n: Indicated by the value of WRSTD2-WRSTD0 2. This indicates the value when RDSTD1-RDSTD0 in the HIFBTC register is 00B. n: Indicated by the value of RDSTD1-RDSTD0 3. This indicates the value when RDDTS1-RDDTS0 in the HIFBTC register is 00B. n: Indicated by the value of RDDTS1-RDDTS0 R18DS0008EJ0500 Dec. 28, 2018 Page 93 of 94 R-IN32M3 Series Data Sheet 4. Electrical Specifications <1> HCSZ, HPGCSZ (input) <1> HA1-HA20 (input) <1> HBENZ0-HBENZ3 (input) <2> <2> HWRSTBZ (input) HWRZ0-HWRZ3 (input) HRDZ (input) <3> <4> HD0-HD31 (input/output) <7> <10> <9> <6> <5> <8> HWAITZ (output) Figure 4.13 External MCU Write Timing (MEMCSEL = L, HIFSYNC = L) Caution: Supply a stable signal to address/data/control system pins while being accessed. R18DS0008EJ0500 Dec. 28, 2018 Page 94 of 95 R-IN32M3 Series Data Sheet 4. Electrical Specifications <11> HCSZ, HPGCSZ (input) <11> <22> <R> HA1-HA20 (input) HBENZ0-HBENZ3 (input) HWRSTBZ (input) HWRZ0-HWRZ3 (input) <13> <13> HRDZ (input) <10> <18> <14> <17> HD0-HD31 (input/output) <15> <10> <16> <21> <5> <18> <14> <17> HWAITZ (output) Figure 4.14 External MCU Read Timing (MEMCSEL = L, HIFSYNC = L) Caution: Supply a stable signal to address/data/control system pins while being accessed. R18DS0008EJ0500 Dec. 28, 2018 Page 95 of 96 R-IN32M3 Series Data Sheet 4. Electrical Specifications <11> HCSZ, HPGCSZ (input) <12> <11> HA4-HA20 (input) <11> HA1-HA3 (input) Off Page On Page Off Page On Page HBENZ0-HBENZ3 (input) HWRSTBZ (input) HWRZ0-HWRZ3 (input) <13> <13> HRDZ (input) <10> <19> <20> <19> <18> <14> <17> HD0-HD31 (input/output) <15> <16> <16> <10> <21> <5> <14> <18> <19> <20> <19> <17> HWAITZ (output) Figure 4.15 External MCU Page-Read Timing (MEMCSEL = L, HIFSYNC = L) Caution: Supply a stable signal to address/data/control system pins while being accessed. R18DS0008EJ0500 Dec. 28, 2018 Page 96 of 97 R-IN32M3 Series Data Sheet (4) 4. Electrical Specifications Synchronous SRAM Type Transfer Mode No. Parameter Symbol MIN MAX Unit 1 HBUSCLK high-level width tHBHIGH 0.5tHBUSCLK - 2.1 0.5tHBUSCLK + 2.1 ns 2 HBUSCLK low-level width tHBLOW 0.5tHBUSCLK - 2.1 0.5tHBUSCLK + 2.1 ns 3 HBUSCLK input cycle tHBUSCLK 20 - ns 4 Address, HCSZ/HPGCSZ input setup time tSKPHA 4.0 - ns tHKPCS 1.0 - ns tSKNHA 4.0 - ns tHKNHA 1.0 - ns (to HBUSCLK) 5 Address, HCSZ/HPGCSZ input hold time (from HBUSCLK) 6 Address, HCSZ/HPGCSZ input setup time (to HBUSCLK) 7 Address, HCSZ/HPGCSZ input hold time (from HBUSCLK) 8 HWRZ0-HWRZ3 input setup time (to HBUSCLK) tSKPHWR 4.0 - ns 9 HWRZ0-HWRZ3 input hold time (from HBUSCLK) tHKPHWR 1.0 - ns 10 HWRZ0-HWRZ3 input setup time (to HBUSCLK) tSKNHWR 4.0 - ns 11 HWRZ0-HWRZ3 input hold time (from HBUSCLK) tHKNHWR 1.0 - ns 12 HBCYSTZ, HWRSTBZ input setup time (to HBUSCLK) tSKPHBCY 4.0 - ns 13 HBCYSTZ, HWRSTBZ input hold time (from HBUSCLK) tHKPHBCY 1.0 - ns 14 HBCYSTZ, HWRSTBZ input setup time (to HBUSCLK) tSKNHBCY 4.0 - ns 15 HBCYSTZ, HWRSTBZ input hold time (from HBUSCLK) tHKNHBCY 1.0 - ns 16 HRDZ input setup time (to HBUSCLK) tSKPHRD 4.0 - ns 17 HRDZ input hold time (from HBUSCLK) tHKPHRD 1.0 - ns 18 HRDZ input setup time (to HBUSCLK) tSKNHRD 4.0 - ns 19 HRDZ input hold time (from HBUSCLK) tHKNHRD 1.0 - ns 20 Data input setup time (to HBUSCLK) tSKPHD 4.0 - ns 21 Data input hold time (from HBUSCLK) tHKPHD 1.0 - ns 22 Data input setup time (to HBUSCLK) tSKNHD 4.0 - ns 23 Data input hold time (from HBUSCLK) tHKNHD 1.0 - ns 24 Data output delay time (from HRDZ) tDKNHRD 2.0 - ns 25 Data output hold time (from HRDZ) tHKPHRD - 13.6 ns 26 Data output delay time (from HBUSCLK) tDKPHD 2.0 10.0 ns 27 Data output delay time (from HBUSCLK) tDKNHD 2.0 10.0 ns 28 HWAITZ output delay time (from HBUSCLK) tDKPHWT 2.0 10.0 ns 29 HWAITZ output delay time (from HBUSCLK) tDKNHWT 2.0 10.0 ns 30 Data output hold time (from HCSZ/HPGCSZ ) tHKPHCS - 13.6 ns R18DS0008EJ0500 Dec. 28, 2018 Page 97 of 98 R-IN32M3 Series Data Sheet 4. Electrical Specifications <1> <2> HBUSCLK (input) <3> <4> <5> <6> <7> HCSZHPGCSZ (input) <5> <4> <7> <6> HA0-HA20 (input) <9> <8> <11> <10> HWRZ0-HWRZ3 (input) <13> <12> <15> <14> HBCYSTZ (input) <13> <12> <15> <14> HWRZSTB (input) Write status <12> <13> <14> <15> HWRZSTB (input) Write strobe HRDZ (input) <21> <20> <25> HD0-HD31 (input/output) OUT <21> <20> <22> <23> IN <22> <23> IN <29> <28> HWAITZ (output) Figure 4.16 External MCU Write Timing (MEMCSEL = H, ADMUXMODE = H) Remark: Address is input in A/D multiplex mode. R18DS0008EJ0500 Dec. 28, 2018 Page 98 of 99 R-IN32M3 Series Data Sheet 4. Electrical Specifications <1> <2> HBUSCLK (input) <3> <4> <5> <6> <7> HCSZHPGCSZ (input) <5> <4> <7> <6> HA0-HA20 (input) HWRZ0-HWRZ3 (input) <13> <12> <15> <14> HBCYSTZ (input) HWRZSTB (input) <17> <16> <18> <19> HRDZ (input) <27> <21> <20> <25> HD0-HD31 (input/output) OUT <26> <22> <23> <24> IN <30> <25> OUT <29> <28> HWAITZ (output) Figure 4.17 External MCU Read Timing (MEMCSEL = H, ADMUXMODE = H) Remark: Address is input in A/D multiplex mode. R18DS0008EJ0500 Dec. 28, 2018 Page 99 of 100 R-IN32M3 Series Data Sheet 4.8.5 4. Electrical Specifications Serial Flash ROM Interface Parameter Symbol Conditions MAX Unit SMSCK output cycle tSFRCYC 20 - ns SMSCK high level width tSMCKH 0.5 tSFRCYC - 2.0 0.5 tSFRCYC + 2.0 ns SMSCK low level width tSMCKL 0.5 tSFRCYC - 2.0 0.5 tSFRCYC + 2.0 ns SMSCK rise time tSMCKR 1.9 ns SMSCK fall time tSFRCYC 1.9 ns tDSMCSCK 6.0 Note <R> ns 9.0 Note<R> ns 14 Note ns Delay time from a falling of SMCSZ to a rising of SMSCK Hold time until a rising of SMCSZ from a CL = 15 pF MIN CL = 15 pF Freq = 50 MHz tDSMCKCS rising of SMSCK CL = 15 pF Freq = 50 MHz SMCSZ high level width tSMCSH CL = 15 pF SMSI input setup time (to SMSCK) tSSMI - 6.0 - Ns SMSI input hold time (from SMSCK) tHSMI - 0 - ns SMSI output delay time (from SMSCK) tDSMI CL = 15 pF -1.0 5.0 ns SMSO input setup time (to SMSCK) tSSMO - 6.0 - ns SMSO input hold time (from SMSCK) tHSMO - 0 - ns SMSO output delay time (from SMSCK) tDSMO CL = 15 pF -1.0 5.0 ns Note: Timing can be extended by setting of SFMSSC register. Please refer to 12.2.2 Chip Selection Control Register (SFMSSC) of User's Manual (Peripheral Modules). < tSFRCYC > < tSMCKR > < tSMCKH > SMSCK (output) [SPI MODE 3] < tSMCKF > < tSMCKL > SMSCK (output) [SPI MODE 0] < tDSMCSCK > < tDSMCKCS > < tSMCSH > SMCSZ (output) < tDSMI > < tDSMO > SMSO/SMSI (output) MSB < tSSMO > < tSSMI> SMSI/SMSO (input) MSB LSB < tHSMO > < tHSMI > LSB Figure 4.18 Serial Flash Rom Access Timing Diagram R18DS0008EJ0500 Dec. 28, 2018 Page 100 of 101 R-IN32M3 Series Data Sheet 4.8.6 4. Electrical Specifications External DMA Interface Parameter Symbol DMAREQZn, RTDMAREQZ Conditions MIN MAX Unit tSKDR - 7.0 - ns tHKDR1 - Until DMAACKZn, - ns tBUSCLK Note1 x m Note2 - ns input setup time (from BUSCLK) DMAREQZn, RTDMAREQZ input hold time 1 RTDMAACKZ DMAREQZn, REDMAREQZ tHKDR2 - - input hold time 2 (from BUSCLK) DMAACKZn, RTDMACKZ 7.0 tDKDA CL = 30pF tWDAL - tDKTC CL = 30pF 2.0 10.0 ns tBUSCLK Note1 x m Note2 - 8 tBUSCLK Note1 x m Note2 + 8 ns 2.0 10.0 ns output delay time (from BUSCLK) DMAACKZn, RTDMAACKZ output low level width DMATCZn, RTDMATCZ output delay time (from BUSCLK) Notes 1. tBUSCLK is one cycle (10 ns) of BUSCLK. 2. n = 0,1 and m = 1-31 (DMAIFC0, DMAIFC1, RTMDAIFC registers). BUSCLK (output) < tHKDR2 > < tHKDR1 > DMAREQZn, RTDMAREQZ (input) < tSKDR > < tWDAL > DMAACKZn, RTDMAACKZ (output) < tDKDA > < tDKTC > DMATCZn, RTDMATCZ (output) Figure 4.19 External DMA Access Timing Diagram Remark: n = 0, 1 R18DS0008EJ0500 Dec. 28, 2018 Page 101 of 102 R-IN32M3 Series Data Sheet 4.8.7 4. Electrical Specifications CSI Interface The clocked serial interface (CSI) supports both master and slave mode. (1) Master mode Parameter Symbol Conditions MIN MAX Unit CSISCKn output cycle tCSIMSCK CSISCKn output high level width tWSKH CL = 15pF 40 - ns CL = 15pF tCSIMSCKx0.5 - 5.0 - ns CSISCKn output low level width tWSKL CL = 15pF tCSIMSCKx0.5 - 5.0 - ns CSISIn input setup time (to CSISCKn) tSMSI - 8.5 - ns CSISIn input setup time (to CSISCKn) tSMSI - 8.5 - ns CSISIn input hold time (from CSISCKn) tHMSI - 7.0 - ns CSISIn input hold time (from CSISCKn) tHMSI - 7.0 - ns CSISOn output delay time (from CSISCKn) tDMSO CL = 15pF - 7.0 ns CSISOn output delay time (from CSISCKn) tDMSO - 7.0 ns CSISOn output hold time (from CSISCKn) tHMSO tCSIMSCK x 0.5 - 5.0 - ns CSISOn output hold time (from CSISCKn) tHMSO tCSIMSCK x 0.5 - 5.0 - ns < tCSIMSCK > CSISCKn (I/O) < tHMSI> < tSMSI > CSISIn (Input) < tDMSO > < tHMSO> CSISOn (Output) Figure 4.20 CSI Access Timing Diagram (Master Mode) Remarks 1. n = 0, 1 2. Above timing diagram shows the case for when "Data Output from CSISCKn" and "Data Input from CSISCKn". See the timing diagram according to the operating mode. R18DS0008EJ0500 Dec. 28, 2018 Page 102 of 103 R-IN32M3 Series Data Sheet (2) 4. Electrical Specifications Slave mode Parameter Symbol Conditions MIN MAX Unit CSISCKn input cycle tCSISSCK CSISCKn input high level width tWSKH - 60 - ns - tCSIMSCKx0.5 - 5.0 - ns CSISCKn input low level width tWSKL - tCSIMSCKx0.5 - 5.0 - ns CSISIn input setup time (to CSISCKn) tSSSI - 10.0 - ns CSISIn input setup time (to CSISCKn) tSSSI - 10.0 - ns CSISIn input hold time (from CSISCKn) tHSSI - 15 - ns CSISIn input hold time (from CSISCKn) tHSSI - 15 - ns CSISOn output delay time (from CSISCKn) tDSSO CL = 15pF - 10.0 ns CSISOn output delay time (from CSISCKn) tDSSO - 10.0 ns CSISOn output hold time (from CSISCKn) tHSSO tCSISSCK x 0.5 - 5.0 - ns CSISOn output hold time (from CSISCKn) tHSSO tCSISSCK x 0.5 - 5.0 - ns < tCSISSCK > CSISCKn (I/O) < tHSSI > < tSSSI > CSISIn (input) < tDSSO > < tHSSO > CSISOn (output) Figure 4.21 CSI Access Timing Diagram (Slave Mode) Remarks 1. n = 0, 1 2. Above timing diagram shows the case for when "Data Output from CSISCKn" and "Data Input from CSISCKn". See the timing diagram according to the operating mode. R18DS0008EJ0500 Dec. 28, 2018 Page 103 of 104 R-IN32M3 Series Data Sheet 4.8.8 4. Electrical Specifications I2C Interface Parameter Symbol Conditions SCL clock frequency tSCL CL = 30pF Bus-free time between the stop condition Normal mode High speed mode Unit MIN MAX MIN MAX 0 100 0 400 kHz tBUF 4.7 - 1.3 - s Hold time tHSTA 4.0 - 0.6 - s SCL clock low-level width tSCLL 4.7 - 1.3 - s SCL clock high-level width tSCLH 4.0 - 0.6 - s Setup time for the start and restart tSSTA 4.7 - 0.6 - s tHDAT 5.0 - - - s 0 - 0 0.9 s and start condition conditions Data hold time For a CBUS compatible master For an IIC bus Data setup time tSDAT 250 - 100 - ns SDA and SCL signal rise time tSCLR - 1000 20 + 0.1Cb 300 ns SDA and SCL signal fall time tSCLF - 300 20 + 0.1Cb 300 ns Stop condition setup time tSSTO 4.0 - 0.6 - s Pules width of spike suppressed by input tSP - - 0 50 ns - 400 - 400 pF filter Capacitance load of each bus line Cb < tSCL> - < tSCLL> < tSCLH> SCLn (I/O) < tHSTA> < tSSTA> < tHDAT> < tSDAT> < tHSTA> SDAn (output) < tSP> < tSSTO> < tBUF> Stop condition Start condition Restart condition Stop condition Figure 4.22 I2C Access Timing Diagram Remark 1 n = 0, 1 tSCLR and tSCLF are omitted from the diagram. R18DS0008EJ0500 Dec. 28, 2018 Page 104 of 105 R-IN32M3 Series Data Sheet 4.8.9 4. Electrical Specifications CAN Interface Parameter Symbol Internal delay time tNODE Conditions CL = 30pF MIN MAX Unit - 75 ns CAN internal clock (I/O) < tOUTPUT> CTXDn (transmission data) < tINPUT> CRXDn (reception data) Figure 4.23 CAN Access Timing Diagram Internal delay time (tNODE) = Internal transmission delay time (tOUTPUT) + Internal reception delay time (tINPUT) R-IN32M3 Internal transmission delay time <tOUTPUT> CTXDn pin CAN controller Internal reception delay time <tINPUT> CRXDn pin Figure 4.24 CAN Access Timing (Supplementary Information) Remarks 1. CAN internal clock (fCAN): CAN baud late clock 2. n = 0,1 R18DS0008EJ0500 Dec. 28, 2018 Page 105 of 106 R-IN32M3 Series Data Sheet 4.8.10 (1) 4. Electrical Specifications Ethernet Interface (R-IN32M3-CL only) GMII interface Parameter Symbol Conditions MIN MAX Unit 8 - ns ETHn_GTXC output cycle tGTXC CL = 13pF ETHn_RXC input cycle tGRXC - 8 - ns ETHn_TXDm output delay time (from ETHn_GTXC) tDGTKTD CL = 13pF 0.5 5.5 ns ETHn_TXEN, ETHn_TXER output delay time (from tDGTKTE CL = 13pF 0.5 5.5 ns ETHn_RXDm input setup time (to ETHn_RXC) tSGRDRK - 2.0 - ns ETHn_RXDm input hold time (from ETHn_RXC) tHGRDRK - 0 - ns ETHn_RXDV, ETHn_RXER input setup time (to ETHn_RXC) tSGRVRK - 2.0 - ns ETHn_RXDV, ETHn_RXER input hold time (from tHGRVRK - 0 - ns ETHn_GTXC) ETHn_RXC) < tGTXC> ETHn_GTXC (output < tDGTKTD> ETHn_TXDm output ETHn_TXEN ETHn_TXER output < tDGTKTE> < tDGTKTE> Figure 4.25 Ethernet Access Timing Diagram (GMII Transmission) < tGRXC> ETHn_RXC (input) < tSGRDRK> < tHGRDRK> < tSGRVRK> < tHGRVRK> ETHn_RXDm (input) ETHn_RXDV ETHn_RXER (input) Figure 4.26 Ethernet Access Timing Diagram (GMII Reception) Remark: n = 0, 1, m = 0-7 R18DS0008EJ0500 Dec. 28, 2018 Page 106 of 107 R-IN32M3 Series Data Sheet (2) 4. Electrical Specifications MII interface Parameter Symbol Conditions MIN MAX Unit ETHn_TXC input cycle tTXC - 40 - ns ETHn_RXC input cycle tRXC - 40 - ns ETHn_TXDm output delay time (from ETHn_TXC) tDTKTD CL = 30pF 0 25 ns ETHn_TXEN, ETHn_TXER output delay time (from tDTKTE CL = 30pF 0 25 ns ETHn_RXDm input setup time (to ETHn_RXC) tSRDRK - 10 - ns ETHn_RXDm input hold time (from ETHn_RXC) tHRDRK - 10 - ns ETHn_RXDV, ETHn_RXER input setup time (to ETHn_RXC) tSRVRK - 10 - ns ETHn_RXDV, ETHn_RXER input hold time (from tHRVRK - 10 - ns ETHn_TXC) ETHn_RXC) < tTXC> ETHn_TXC (input) < tDTKTD> ETHn_TXDm (output) ETHn_TXEN ETHn_TXER (oiutput) < tDTKTE> < tDTKTE> Figure 4.27 Ethernet Access Timing Diagram (MII Transmission) < tRXC> ETHn_RXC (input) < tSRDRK> < tHRDRK> < tSRVRK> < tHRVRK> ETHn_RXDm (input) ETHn_RXDV ETHn_RXER (input) Figure 4.28 Ethernet Access Timing (MII Reception) Remark: n = 0, 1, m = 0-7 R18DS0008EJ0500 Dec. 28, 2018 Page 107 of 108 R-IN32M3 Series Data Sheet (3) 4. Electrical Specifications Serial management interface Parameter Symbol Conditions CL = 30pF MIN MAX Unit ETH_MDC output cycle tMDC 80 - ns ETH_MDIO input setup time (to ETH_MDC) tSMDIO 10 - ns ETH_MDIO input hold time (from ETH_MDC) tHMDIO 0 - ns ETH_MDIO output delay time (from ETH_MDC) tDMDIO 20 - ns < tMDC> ETH_MDC (output) < tSMDIO> < tHMDIO> ETH_MDIO (input) < tDMDIO> < tDMDIO> ETH_MDIO (output) Figure 4.29 Ethernet Access Timing Diagram (Serial Management) R18DS0008EJ0500 Dec. 28, 2018 Page 108 of 109 R-IN32M3 Series Data Sheet 4.8.11 (1) 4. Electrical Specifications Debug Interface Debug serial interface Parameter Symbol Conditions MIN MAX Unit TCK input cycle tTCK - 20 - ns TMS input setup time (to TCK) tSTMS - 6.5 - ns TMS input hold time (from TCK) tHTMS - 0 - ns TDI input setup time (to TCK) tSTDI - 6.5 - ns TDI input hold time (from TCK) tHTDI - 0 - ns TDO output delay time (from TCK) tDTDO CL = 30pF 3.0 13.0 ns < tTCK > TCK (input) < tSTMS > < tHTMS > TMS (input) < tSTDI > < tHTDI > TDI (input) < tDTDO > TDO (output) Figure 4.30 Debug Serial Interface R18DS0008EJ0500 Dec. 28, 2018 Page 109 of 110 R-IN32M3 Series Data Sheet (2) 4. Electrical Specifications Trace interface Parameter Symbol Conditions MIN MAX Unit TRACECLK output frequency tTRCCLK CL = 15pF 20 - ns TRACEDATA output delay time (from TRACECLK) tDTRCDAT CL = 15pF 0.26 8.43 ns < tTRCCLK > TRACECLK (output) < tDTRCDAT > < tDTRCDAT > TRACEDATA0TRACEDATA3 (output) Figure 4.31 Trace Interface R18DS0008EJ0500 Dec. 28, 2018 Page 110 of 111 R-IN32M3 Series Data Sheet 5. 5. Package Drawing Package Drawing R18DS0008EJ0500 Dec. 28, 2018 Page 111 of 111 R-IN32M3 Series Data Sheet REVISION HISTORY REVISION HISTORY Rev. R-IN32M3 Series Data Sheet Date Description Page Preliminary 2011.06.14 - 2012.12.03 overall Summary First edition issued 1.00 Preliminary 2.00 "CC-Link IE Field network" "CC-Link IE Field" 12-13 Addition of 2.1 Pin Placement 14-16 Modification of 2.3.1 Ethernet Signal 20 Modification of pin name of 2.3.5 Port Signal, Real-time port Signal 26 Modification of level during reset of 2.3.9 Timer I/O Signal 28 Addition of new pin information of 2.3.14 System Signal 29 Addition of new pin information of 2.3.15 Test Signal 30 Addition of new pin information of 2.3.16 Operation mode Setting Signal 36 Addition of new pin information of 2.4.4Test Signal 39-62 Addition of 3 Specification 65-68 Modification of the description of output buffer of 4 Electrical Specifications 69 70-89 Preliminary 3.00 Change the description of "CC-Link IE Field" 2013.1.17 Addition of 4.6 Power-on/off sequence Addition of 4.7 AC characteristics 2 Modification of Access to External Memory of 1.3 Overview 3 Modification of status of CC-Link of 1.3 Overview Addition EtherPHY Information of 1.3 Overview 4 Modification of block diagram of R-IN32M3-EC of 1.4 INTERNAL BLOCK DIAGRAM 5 Modification of block diagram of R-IN32M3-CL of 1.4 INTERNAL BLOCK DIAGRAM 14 Modification of list of PHY Interface of 2.3.1 Ethernet Signal 16 Modification of level during reset of PHYLINK0/1 of 2.3.1 Ethernet Signal 17 Modification of level during reset of CATSYNC1 of 2.3.2 EtherCAT Slave Controller Signal 18 Addition of WAITZ1-3 port and list of note of 2.3.3 External Memory Interface Signal 25 Modification of level during reset of 2.3.8 External Interrupt Input Signal 26 Modification of level during reset of TIN2/TOUT2 of 2.3.8 External Interrupt Input Signal and level during reset of 2.3.10 Watchdog Timer Output Signal 30 Modification of level during reset of 2.3.16 CC-Link (Remote device station) 31 Addition the signal of VDDQ_PECL_B0/ VDDQ_PECL_B1 of 2.3.17 System 34 Modification of Required Connection when not in use of ETH0_TXC of 2.4.1 signal Ethernet Signal C-1 R-IN32M3 Series Data Sheet Rev. REVISION HISTORY Date Description Page Preliminary 2013.1.17 36 3.00 1.00 Summary Modification of Required Connection when not in use of TRSTZ of 2.4.4 Test Signal Mar 29,2013 64 Addition the figure of HW-RTOS structure of 3.20 Hardware Real-time OS 65 Addition the list of service call of 3.20 Hardware Real-time OS overall Modification of English expressions overall Change the description of "CC-Link IE Field" "CC-Link IE Field Slave" "CC-Link IE Field (Intelligent device station)" overall Change the description of "CC-Link" "CC-Link (Slave)" "CC-Link (Remote device station)" 1 Modification of the contents of 1.1 Introduction 14 Modification of the status of ETH_MDC during the reset of 2.3.1 Ethernet Signals Modification of the contents of Note of 2.3.1 Ethernet Signals 18 Modification of the status of BUSCLK during the reset of 2.3.3 External Memory Interface Signals 19 Modification of the status of HD0-HD15 during the reset of 2.3.4 External MPU Interface Signals 31 Addition the signals of HOTRESETZ, VDDQ_MII, CLKOUT25M0, CLKOUT25M1 of 2.3.17 System Signals Modification of the function of PONRZ of 2.3.17 System Signals 53 Modification of the status of the kind of supported station of 3.12 CC-Link Function 78 Modification of the example calculation of 4.7.3 External memory interface signals (1) 78 Modification of the MIN calculation result at the time of 30pF of 4.7.3 External memory interface signals (2) 81 Modification of the MIN calculation result at the time of 30pF of 4.7.3 External memory interface signals (3) 84 2.00 Dec 9 ,2013 Addition the 4.7.4 External microcomputer interface signal overall Change the kind of CC-Link station to support 3 Standby mode deletion of Table1.1 Overview of R-IN32M3 6 to 10 Modification of the accessible area of EtherCAT of 1.5 Memory Map 28 Addition explanation of Function of 2.1.14 CC-Link IE Field Signals 31 Modification of the function of VDD15 of 2.3.17 System Signals Addition the note to VDDQ_MII of 2.3.17 System Signals 47 Modification of WDT overflow time of 3.7 Watchdog Timer 71 Addition of the value of Supply current of 4.4 DC Characteristics 73 Modification of the contents of 4.6 Power-on/off sequence 80 Modification of the contents of 4.7.3 External memory interface signals (3) 81 Modification of the contents of Figure 4.6 Memory controller read timing diagram (synchronous memory) 92 Modification of the value of output delay time of ETHn_TXDm/ETHn_TXEN, ETHn_TXER of 4.7.10 Ethernet interface (1) C-2 R-IN32M3 Series Data Sheet Rev. REVISION HISTORY Date Description Page 2.01 Feb 07 ,2014 6, 10 30 Summary Modification of the accessible area of EtherCAT of 1.5 Memory Map Add CCM_CLK80M pins to list of 2.3.16 CC-Link Signals (Remote device station) 33 Modification of Boot mode select of 2.3.19 Operation mode Setting Signals 37 Addition the resister value for Pull-up/down 39 Modification of title name of 2.4.8 CC-Link Signal (Intelligent device station, Remote device station) 2.02 Apr 18 ,2014 72 Delete the description of 5k row of 4.5 Pull-up/down Resister Values 71 Addition Table4.6 DC Characteristics TYP value 86 Addition the description at 4.7.5 Serial flash ROM interface overall Modification of CC-Link Signals (Remote device station) 39 Modification of the description about `recommended connection' and addition a caution description at 2.4.7 CC-Link IE Field Signal 2.03 May 30 ,2014 73 Add a notes of "4.6 Power-on-off sequence" 2.04 Dec 25 ,2014 3 Change status for Intelligent device station for CC-Link in 1.3 Overview 6 to 10 Modification of the accessible area of EtherCAT of 1.5 Memory Map 31 Modify the property for FB pin from "-" to "Input" 76 Modify the description of MIN value for low level width in 4.7.2 Reset signals 86 Add description for "Asynchronous mode" in 4.7.4 External microcomputer interface signal. 3.00 Aug 31,2015 83 to 93 Correction the timing information of 4.7.4 External Microcomputer Interface Signal 3.01 Sep 18,2015 88 to 91 Add description for "Synchronous mode (CC-Link IE Field)" in 4.7.4 External microcomputer interface signal. 4.00 Nov 30,2015 14 to 36 Add description of "Symbol and Abbreviation", port functions of synchronous burst access memory controller at 2.3 Signals by Function. 15 Add a Note of Ethernet Transmit ports at 2.3.1(1) PHY Interface. 19 Modify the "Level during reset" for BUSCLK and add Note1 at 2.3.3 External Memory Interface Signals. 27 Modify the "Level during reset" for TRACECLK at 2.3.11 Trace Signals. 29 Add a Note for CCI_WAITEDGEH and CCI_WRLENH at 2.3.14 CC-Link IE Field (Intelligent device station) Signals. 30 Modify the "Function" for CCM_CLK80M at 2.3.15 CC-Link Signals (Intelligent device station). 31 Add a Note2 for CCM_CLK80M at 2.3.16 CC-Link Signals (Remote device station). 32 Modify the "Function" for XT1/XT2, OSCTH, JTAGSEL and "Active" for OSCTH and "Level during reset" for RSTOUTZ, CLKOUT25M0/1 at 2.3.17 System Signals. 36 Add the combinations of available operating mode at 2.3.19 Operation Mode Setting Signal. 39 Modify "I/O" for XT2 and "Recommended connection when not in use" for OSCTH, JTAGSEL at 2.4.3 System Signals. C-3 R-IN32M3 Series Data Sheet Rev. 4.00 REVISION HISTORY Description Date Nov 30,2015 Page Summary 42 Modify "Recommended connection when not in use" at 2.4.6 Operating Mode Setting Signals. 46 Modify "Table3.1" at 3.3 EtherCAT Slave Controller Function. 51 Add "External event count function" at 3.8.1 Features. 65-66 Modify "QINT" and add "Remark" at 3.20.1 Features. 72 Add 4.6 Terminal Capacity Values. 74 Modify "MAX" values for CCI_CLK2_097M at 4.8.1(1) Input clock characteristics. 78-82 Modify a Note for Figure4.4, Figure4.5 and Add WAITZ1-WAITZ3 for Figure4.6, Figure4.7 at 4.8.3(3) Synchronous burst access MEMC access timing. 100 Modify "Symbol" for DMAACKZn, RTDMAACKZoutput low level width at 4.8.6 External DMA Interface. 101-102 Add "Symbol" for CSISCKn output high/low level width and "Remark" at 4.8.7 CSI Interface. 105-106 107 Modify the signals "ETHn_RXDm" at 4.8.10 Ethernet Interface. Modify "Parameter" and "MAX" value for TRACEDATA output delay time at 4.8.11(2) Trace interface. 4.01 Feb 28, 2017 30 Modify description of the CCM_MDIN0-3 signals at 2.3.15 CC-Link Pins (Intelligent Device Station). (complement) 58 Modify interface system, synchronous relationship, and buffers at 3.14.1(1) External MCU Interface. (complement) 59 Modify description of address conversion at 3.14.1(2) AHB master port function. (expression alignment) Explicitly notate applicable modes at 3.14.1(3) Status check function. (complement) 60 Change from "state" to "wait" at 3.15.1 Features. (expression alignment) 61 Change pin names for wait signal at 3.16.1 Features. (error correction) 62 Add the ECC error interrupt function at 3.17.1 Features. (new function) Correct operation of the AHB bus at occurrence of a 2-bit ECC error at 3.17.2 Read Buffer. (error correction) 63 Change expression of Header Endec at 3.18 Data RAM. (expression alignment) Add an ECC error interrupt function at 3.18.1 Features. (new function) 64 Add an ECC error interrupt function at 3.19.1 Features. (new function) 65 Add a supported function "Internal DMA/Buffer Allocator/Header EnDec" at 3.20.1 Features. (new function) 71 Delete the column of 5k resistor from Table 4.6 Input leakage current (error correction) and modify the symbol for the voltage of high-level output (IOLIOH) in Table 4.7 (error correction) at 4.4 DC Characteristics. C-4 R-IN32M3 Series Data Sheet Rev. REVISION HISTORY Date Description Page 5.00 Dec 28, 2018 3 Summary 1.3 Overview, Table 1.2 Overview of R-IN32M3 (2/2) Description of 1.5 V power supply for internal PHY was added. 6, 7, 10 to 12 1.5 Memory Maps Note describing that the addresses the instruction RAM mirror area (768 Kbytes) where access actually occurs will change according to the select boot mode, was added. Figure 1.1 Memory Map (All) (R-IN32M3-EC) Figure 1.2 Memory Map (All) (R-IN32M3-CL) Figure 1.6 External MCU Interface Area (R-IN32M3-EC) Figure 1.7 External MCU Interface Area (R-IN32M3-CL) 6, 7 1.5 Memory Maps Figure 1.1 Memory Map (All) (R-IN32M3-EC) Figure 1.2 Memory Map (All) (R-IN32M3-CL) Locations of instruction RAM area and instruction RAM mirror area were corrected. 10 to 12 1.5 Memory Maps Figure 1.6 External MCU Interface Area (R-IN32M3-EC) Figure 1.7 External MCU Interface Area (R-IN32M3-CL) "Instruction RAM area" was corrected to "Instruction RAM mirror area". 23 2.3.5 Port Pins and Real-time Port Pins The pin name indicated as "CCM_IRZ" was modified to "CCM_IRLZ". 31 2.3.15 CC-Link Pins (Intelligent Device Station) The name and functional descriptions of the CC-Link (intelligent device station) pins were modified. 70 4.2 Absolute Maximum Ratings, Table 4.4 Absolute Maximum Ratings 1.5 V type was added as the condition for power supply voltage. 71 4.3 Recommended Operating Conditions, Table 4.5 Recommended Operating Conditions 1.5 V power supply was added as the condition for power supply voltage. 93, 95 4.8.4 External MCU Interface Pins, (3) Asynchronous Mode Figure 4.14 External MCU Read Timing (MEMCSEL = L, HIFSYNC = L) Specification of "Address input hold time when advance reading" was added 100 4.8.5 Serial Flash ROM Interface Specifications of tDSMCSCK and tDSMCKCS were modified. -- Error corrected, description modified, and contents and expressions adjusted C-5 Instructions for the use of product In this section, the precautions are described for over whole of CMOS device. Please refer to this manual about individual precaution: When there is a mention unlike the text of this manual, a mention of the text takes first priority 1.Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. -The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2.Processing at Power-on The state of the product is undefined at the moment when power is supplied. -The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3.Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. -The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4.Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. -When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. Arm(R) and Cortex(R) are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. Ethernet is a registered trademark of Fuji Xerox Co., Ltd. IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers Inc. TRON is an acronym for "The Real-time Operation system Nucleus". ITRON is an acronym for "Industrial TRON". ITRON is an acronym for "Micro Industrial TRON". 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