RMS25CB080 924871 - INTEL - Product.Network

1. General description

The LPC15xx are ARM Cortex-M3 based microcontrollers for embedded applications

featuring a rich peripheral set with very low power consumption. The ARM Cortex-M3 is a

next generation core that offers system enhancement s such as enhanced debug features

and a higher level of support block integration.

The LPC15xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU

incorporate s a 3- stage pipelin e an d us es a Ha rva rd arc hit ec tu re with separat e local

instruction and data buses as well as a third bus for periphera ls. The ARM Cortex-M3

CPU also includes an internal prefetch unit that supports speculative branching.

The LPC15xx includes up to 256 kB of flash memory, 32 kB of ROM, a 4 kB EEPROM,

and up to 36 kB of SRAM. The peripheral complement includes one full-speed USB 2.0

device, two SPI interfaces, three USARTs, one Fast-mode Plus I2C-bus interface, one

C_CAN module, PWM/timer subsystem with four configurable, multi-purpose State

Configurable Timers (SCTimer/PWM) with input pre-processing unit, a Real-time clock

module with independent power supply and a dedicated oscillator, two 12-channel/12-bit,

2 Msamples/s ADCs, one 12-bit, 500 kSamples/s DAC, four voltage comparators with

internal voltage reference, and a temperature sensor. A DMA engine can service most

peripherals.

For additional documentation related to the LPC15xx parts, see Sectio n 17 “References”.

2. Features and benefits

System:

ARM Cortex-M3 processor (version r2p1), running at frequencies of up to 72 MHz.

ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

System tick timer.

Serial Wire Debug (SWD) with four breakpo ints and two watchpoints.

Single-cycle multiplier supported.

Memory Protection Unit (MPU) included.

Memory:

Up to 256 kB on-chip flash programming memory with 256 Byte page write and

erase.

Up to 36 kB SRAM.

4 kB EEPROM.

LPC15xx

32-bit ARM Cortex-M3 microcontroller; up to 256 kB flash and

36 kB SRAM; FS USB, CAN, RTC, SPI, USART, I2C

Rev. 1.1 — 29 April 2015 Product data sheet

Product data sheet Rev. 1.1 — 29 April 2015 2 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

ROM API support:

Boot loader with boot op tions from flash or external sou rce via USART, C_CAN, or

USB

USB drivers

ADC drivers

SPI drivers

USART drivers

I2C drivers

Power profiles and power mode co nfiguration with low-power mode configuration

option

DMA drivers

C_CAN drivers

Flash In-Application Programming (IAP) and In-System Programming (ISP).

Digital peripherals:

Simple DMA engine with 18 channels and 20 programmable input triggers.

High-speed GPIO interface with up to 76 General-Purpose I/O (GPIO) pins with

configurable pull-up/pull-down resistors, open-drain mode, input inverter, and

programmable digital glitch filter.

GPIO interrupt generation capability with boolean pattern-matching feature on eight

external inpu ts.

Two GPIO grouped port interrupts.

Switch matrix for flexible configuration of each I/O pin function.

CRC engine.

Quadrature Encoder Interface (QEI).

Configurable PWM/timer/motor control subsystem:

Up to four 32-b it counter/timers or up to eight 16-bit counter/timers or combinations

of 16-bit and 32-bit timers.

Up to 28 match outputs and 22 configurable capture inputs with input multiplexer.

Up to 28 PWM outputs total.

Dither engine for improved average resolution of pulse edges.

Four State Configurable Timers (SCTimers) for highly flexible, event-driven timing

and PWM applications.

SCT Input Pre-processo r Unit (SCTIPU) for p rocessing timer inpu ts an d immediate

handling of abort situations.

Integrated with ADC threshold co mpare interrupt s, temperature se nsor , and analog

comparator outputs for motor co ntrol feedback using analog signals.

Special-application and simple timers:

24-bit, four-channel, multi-rate timer (MRT) for repetitive interrupt generation at up

to four programmable, fixed rates.

Repetitive interrupt timer for general purpose use.

Windowed Watchdog timer (WWDT).

High-resolution 32-bit Real-time clock (RTC) with selectable 1 s or 1 ms time

resolution running in the always-on power domain. RTC can be used for wake-up

from all low power modes including Deep power-down.

Product data sheet Rev. 1.1 — 29 April 2015 3 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Analog peripherals:

Two 12-bit ADC with up to 12 input channels per ADC and with multiple internal

and external trigger inputs and sample rates of up to 2 Msamples/s. Each ADC

support s two independent conversion sequences. ADC conversion clock can be

the system clock or an asynchronous clock derived from one of the three PLLs.

One 12-bit DAC.

Integrated temperature sensor and band gap internal reference voltage.

Four comparators with external and internal voltage references (ACMP0 to 3).

Comparator outputs are internally connected to the SCTimer/PWMs and ADCs and

externally to pins. Each comparator output contains a programmable glitch filter.

Serial interfaces:

Three USART interfaces with DMA, RS-485 support, autobaud, and with

synchronous mode and 32 kHz mode for wake-up from Deep-sleep and

Power-down modes. The USARTs share a fractional baud-rate generator.

Two SPI controllers.

One I2C-bus interface suppor ting fa st m ode an d F ast-mo de Plu s with data rates of

up to 1Mbit/s and with mu ltip le ad d ress re co gn itio n an d m on ito r mo de .

One C_CAN controller.

One USB 2.0 full-speed device controller with on-chip PHY.

Clock generation :

12 MHz internal RC oscillator trimmed to 1 % accuracy for 25 C  Tamb  +85 C

that can optionally be used as a system clock.

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

Watchdog oscillator with a frequency range of 503 kHz.

32 kHz low-power RTC oscillator with 32 kHz, 1 kHz, and 1 Hz outputs.

System PLL allows CPU operation up to the maximum CPU rate without the need

for a high-frequency crystal. May be run from the system oscillator or the internal

RC oscillator.

Two additional PLLs for generating the USB and SCTimer/PWM clocks.

Clock output function with divider that can reflect the crystal oscillator, the main

clock, the IRC, or the watchdog oscillator.

Power control:

Integrated PMU (Power Management Unit) to minimize power consumption.

Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode.

APIs provided for optim izing power consumption in active and sleep modes and for

configuring Deep-sleep, Power-down, and Deep power-down modes.

Wake-up from Deep-sleep and Power-down modes on activity on USB, USART,

SPI, and I2C peripherals.

Wake-up from Sleep, Deep-sleep, Power-down, and Deep power-down modes

from the RTC alarm or wake-up interrupts.

Timer-controlled self wake-up from Deep power-down mode using the RTC

high-resolution/wake-up 1 kHz timer.

Power-On Reset (POR).

BrownOut Detect BOD).

JTAG boundary scan modes supported.

Unique device serial number for identification.

Product data sheet Rev. 1.1 — 29 April 2015 4 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Single power supply 2.4 V to 3.6 V.

Temperature range 40 °C to +105 °C.

Availa ble as LQFP100, LQFP64, and LQFP48 packages.

3. Applications

4. Ordering information

Motor control Solar inverters

Motion drives Home appliances

Digital power supplies Building and factory auto m at ion

Industrial and medical

Table 1. Ordering information

Type number Package

Name Description Version

LPC1549JBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1

LPC1549JBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1549JBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC1548JBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1

LPC1548JBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1547JBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1547JBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

LPC1519JBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1

LPC1519JBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1518JBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1

LPC1518JBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1517JBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2

LPC1517JBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2

Product data sheet Rev. 1.1 — 29 April 2015 5 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

4.1 Ordering options

Table 2. Ordering options for LPC15xx

Type number Flash/

kB EEPROM/

kB Total

SRAM/

USB USART I2CSPI C_CAN SCTimer/

PWM 12-bit

ADC0/1

channels

DAC GPIO

LPC1549JBD100 256 4 36 yes 3 1 2 1 4 12/12 1 76

LPC1549JBD64 256 4 36 yes 3 1 2 1 4 12/12 1 44

LPC1549JBD48 256 4 36 yes 3 1 2 1 4 9/7 1 30

LPC1548JBD100 128 4 20 yes 3 1 2 1 4 12/12 1 76

LPC1548JBD64 128 4 20 yes 3 1 2 1 4 12/12 1 44

LPC1547JBD64 64 4 12 yes 3 1 2 1 4 12/12 1 44

LPC1547JBD48 64 4 12 yes 3 1 2 1 4 9/7 1 30

LPC1519JBD100 256 4 36 no 3 1 2 1 4 12/12 1 78

LPC1519JBD64 256 4 36 no 3 1 2 1 4 12/12 1 46

LPC1518JBD100 128 4 20 no 3 1 2 1 4 12/12 1 78

LPC1518JBD64 128 4 20 no 3 1 2 1 4 12/12 1 46

LPC1517JBD64 64 4 12 no 3 1 2 1 4 12/12 1 46

LPC1517JBD48 64 4 12 no 3 1 2 1 4 9/7 1 32

Product data sheet Rev. 1.1 — 29 April 2015 6 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

5. Marking

The LPC15xx devices typically have the following top-side marking for LQFP100

packages:

LPC15xxJxxx

Xxxxxx xx

xxxyywwxxx

The LPC15xx devices typically have the following top-sid e marking for LQFP64 p ackages:

LPC15xxJ

Xxxxxx xx

xxxyywwxxx

The LPC15xx devices typically have the following top-sid e marking for LQFP48 p ackages:

LPC15xxJ

Xxxxxx

Xxxyy

wwxxx

Field ‘yy’ states the year the device was manufactured. Field ‘ww’ states the week the

device was manufactured during that year.

Fig 1. LQFP64/100 package marking Fig 2. LQFP48 package marking

Terminal 1 index area

aaa-011231 aaa-011232

Terminal 1 index area 1

Product data sheet Rev. 1.1 — 29 April 2015 7 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

6. Block diagram

Grey-shaded blocks show peripherals that can provide hardware triggers for DMA transfers or have DMA request lines.

Fig 3. LPC15xx Block diagram

ARM

CORTEX-M3 TEST/DEBUG INTERFACE

SWD/ETM SYSTICK

NVIC MPU

PROCESSOR CORE

PRECISION

IRC

SYSTEM

PLL

WATCHDOG

OSCILLATOR

USB

PLL

SCT

PLL

FREQUENCY

MEASUREMENT

SYSTEM

OSCILLATOR

RTC

OSCILLATOR

CLOCK

GENERATION

SCTIPU

256/128/64 kB FLASH

32 kB ROM

36/20/12 kB SRAM

4 kB EEPROM

12-bit DAC

MEMORY

PORT0/1/2

GINT0/1

PINT/

PATTERN MATCH

SCTIMER0/

PWM

SCTIMER1/

PWM

SCTIMER2/

PWM

SCTIMER3/

PWM

HS GPIO

QEI

DMA TRIGGER

ACMP0/

TEMPERATURE

SENSOR

ACMP1 ACMP2 ACMP3

INPUT MUX

SCTIMER/PWM/MOTOR CONTROL SUBSYSTEM

SPI0

USART0 SPI1

USART1

FM+ I2C0

USART2

C_CAN FS USB/

PHY

INPUT MUX

SYSCON IOCON PMU CRC FLASH CTRL EEPROM CTRL

SYSTEM/MEMORY CONTROL

MRT RIT WWDT RTC

TIMERS

SERIAL PERIPHERALS

12-bit ADC0

TRIGGER MUX

ANALOG PERIPHERALS

12-bit ADC1

TRIGGER MUX

AHB MULTILAYER

MATRIX

AHB/APB BRIDGES

INPUT MUX INPUT MUX

DMA

pads

LPC15xx

pads n

SWM

aaa-010869

Product data sheet Rev. 1.1 — 29 April 2015 8 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

7. Pinning information

7.1 Pinning

Fig 4. LQFP48 pin configuration (with USB)

LPC1547JBD48

LPC1549JBD48

37PIO0_22/I2C0_SCL 24 PIO0_16/ADC1_9

38PIO0_23/I2C0_SDA 23 PIO0_15/ADC1_8

39VDD 22 PIO0_14/ADC1_7/ SCT1_OUT5

40VSS 21 PIO0_13/ADC1_6

41VSS 20 VSS

42VDD 19 PIO0_12/DAC_OUT

43PIO0_24/SCT0_OUT6 18 PIO0_11/ADC1_3

44PIO0_25/ACMP0_I4 17 VSSA

45PIO0_26/ACMP0_I3/ SCT3_OUT3 16 VDDA

46PIO0_27/ACMP_I1 15 PIO0_10/ADC1_2

47PIO0_28/ACMP1_I3 14 VREFP_DAC_VDDCMP

48PIO0_29/ACMP2_I3/ SCT2_OUT4 13 PIO0_18/ SCT0_OUT5

1PIO0_0/ADC0_10/ SCT0_OUT3 36 USB_DM

2PIO0_1/ADC0_7/ SCT0_OUT4 35 USB_DP

3PIO0_2/ADC0_6/ SCT1_OUT3 34 RESET/PIO0_21

4PIO0_3/ADC0_5/ SCT1_OUT4 33 SWDIO/ PIO0_20/SCT1_OUT6/ TMS

5PIO0_4/ADC0_4 32 RTCXOUT

6PIO0_5/ADC0_3 31 RTCXIN

7PIO0_6/ADC0_2/ SCT2_OUT3 30 VBAT

8PIO0_7/ADC0_1 29 SWCLK/ PIO0_19/TCK

9PIO0_8/ADC0_0/TDO 28 PIO0_17/WAKEUP/TRST

10VREFP_ADC 27 VDD

11VREFN 26 XTALIN

12PIO0_9/ADC1_1/TDI 25 XTALOUT

aaa-009352

Product data sheet Rev. 1.1 — 29 April 2015 9 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Fig 5. LQFP48 pin configuration (without USB)

LPC1517JBD48

37PIO0_22/I2C0_SCL 24 PIO0_16/ADC1_9

38PIO0_23/I2C0_SDA 23 PIO0_15/ADC1_8

39VDD 22 PIO0_14/ADC1_7/ SCT1_OUT5

40VSS 21 PIO0_13/ADC1_6

41VSS 20 VSS

42VDD 19 PIO0_12/DAC_OUT

43PIO0_24/SCT0_OUT6 18 PIO0_11/ADC1_3

44PIO0_25/ACMP0_I4 17 VSSA

45PIO0_26/ACMP0_I3/ SCT3_OUT3 16 VDDA

46PIO0_27/ACMP_I1 15 PIO0_10/ADC1_2

47PIO0_28/ACMP1_I3 14 VREFP_DAC_VDDCMP

48PIO0_29/ACMP2_I3/ SCT2_OUT4 13 PIO0_18/ SCT0_OUT5

1PIO0_0/ADC0_10/ SCT0_OUT3 36 PIO2_13

2PIO0_1/ADC0_7/ SCT0_OUT4 35 PIO2_12

3PIO0_2/ADC0_6/ SCT1_OUT3 34 RESET/PIO0_21

4PIO0_3/ADC0_5/ SCT1_OUT4 33 SWDIO/ PIO0_20/SCT1_OUT6/ TMS

5PIO0_4/ADC0_4 32 RTCXOUT

6PIO0_5/ADC0_3 31 RTCXIN

7PIO0_6/ADC0_2/ SCT2_OUT3 30 VBAT

8PIO0_7/ADC0_1 29 SWCLK/ PIO0_19/TCK

9PIO0_8/ADC0_0/TDO 28 PIO0_17/WAKEUP/TRST

10VREFP_ADC 27 VDD

11VREFN 26 XTALIN

12PIO0_9/ADC1_1/TDI 25 XTALOUT

aaa-009354

Product data sheet Rev. 1.1 — 29 April 2015 10 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

See Table 3 for the full pin name.

Fig 6. LQFP64 pin configuration (with USB)

LPC1549JBD64

LPC1548JBD64

LPC1547JBD64

49PIO0_22 32 PIO0_16

50PIO0_23 31 PIO0_15

51PIO1_7 30 PIO0_14

52VDD 29 PIO0_13

53PIO1_8 28 PIO1_3

54PIO1_9 27 VSS

55VSS 26 VSS

56VSS 25 PIO1_2

57VDD 24 PIO0_12

58PIO0_24 23 PIO0_11

59PIO1_10 22 VDD

60PIO0_25 21 VSSA

61PIO0_26 20 VDDA

62PIO0_27 19 PIO0_10

63PIO0_28 18 VREFP_DAC_VDDCMP

64PIO0_29 17 PIO0_18

1PIO0_30 48 USB_DM

2PIO0_0 47 USB_DP

3PIO0_31 46 PIO1_6

4PIO1_0 45 RESET/PIO0_21

5PIO0_1 44 SWDIO/ PIO0_20

6PIO0_2 43 RTCXOUT

7PIO0_3 42 RTCXIN

8PIO0_4 41 VBAT

9PIO0_5 40 SWCLK/ PIO0_19

10PIO0_6 39 PIO0_17/WAKEUP

11PIO0_7 38 PIO1_11

12PIO0_8 37 VDD

13VREFP_ADC 36 XTALIN

14VREFN 35 XTALOUT

15PIO1_1 34 PIO1_5

16PIO0_9 33 PIO1_4

aaa-009353

Product data sheet Rev. 1.1 — 29 April 2015 11 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Fig 7. LQFP64 pin configuration (without USB)

LPC1519JBD64

LPC1518JBD64

LPC1517JBD64

49PIO0_22 32 PIO0_16

50PIO0_23 31 PIO0_15

51PIO1_7 30 PIO0_14

52VDD 29 PIO0_13

53PIO1_8 28 PIO1_3

54PIO1_9 27 VSS

55VSS 26 VSS

56VSS 25 PIO1_2

57VDD 24 PIO0_12

58PIO0_24 23 PIO0_11

59PIO1_10 22 VDD

60PIO0_25 21 VSSA

61PIO0_26 20 VDDA

62PIO0_27 19 PIO0_10

63PIO0_28 18 VREFP_DAC_VDDCMP

64PIO0_29 17 PIO0_18

1PIO0_30 48 PIO2_13

2PIO0_0 47 PIO2_12

3PIO0_31 46 PIO1_6

4PIO1_0 45 RESET/PIO0_21

5PIO0_1 44 SWDIO/ PIO0_20

6PIO0_2 43 RTCXOUT

7PIO0_3 42 RTCXIN

8PIO0_4 41 VBAT

9PIO0_5 40 SWCLK/ PIO0_19

10PIO0_6 39 PIO0_17/WAKEUP

11PIO0_7 38 PIO1_11

12PIO0_8 37 VDD

13VREFP_ADC 36 XTALIN

14VREFN 35 XTALOUT

15PIO1_1 34 PIO1_5

16PIO0_9 33 PIO1_4

aaa-009376

Fig 8. LQFP100 pin configuration

LPC1548JBD100

LPC1518JBD100

100

aaa-009351

Product data sheet Rev. 1.1 — 29 April 2015 12 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

7.2 Pin description

Most pins are configurable for multiple functions, which can be analog or digital. Digital

inputs can b e connected to several peripherals a t once, however only one dig ital output or

one analog function can be assigned to any on pin. The pin’s connections to internal

peripheral blocks are configured by the switch matrix (SWM), the input multiplexer (INPUT

MUX), and the SCT Input Pre-processor Unit (SCTIPU).

The switch matrix enables certain fixed-pin functions that can only reside on specific pins

(see Table 3) and assigns all other pin functions (movable functions) to any available pin

(see Table 4), so that the pinout can be optimize d for a given application.

The input multiplexer provides many choices (pins and internal signals) for selecting the

inputs of the SCTimer/PWMs and the frequency measure block. Pins that are connected

to the input multiplexer are listed in Table 5. If a pin is selected in the input multiplexer, it is

directly connec te d to the pe rip h er al inpu t with out being routed through the switch matrix.

Independently of being selected in the input multiplexer, the same pin can also be

assigned by the switch matrix to another peripheral input.

Four pins can also be connected directly to the SCTIPU an d at the same time be inputs to

the input multiplexer and the switch matrix (see Table 5).

Table 3. Pin description with fixed-pin functions

Symbol

LQFP48

LQFP64

LQFP100

Reset

state[1] Type Description

PIO0_0/ADC0_10/

SCT0_OUT3

122[2] I; PU IO PIO0_0 — General purpose port 0 input/output 0.

AADC0_10 — ADC0 input 10.

OSCT0_OUT3 — SCTimer0/PWM output 3.

PIO0_1/ADC0_7/

SCT0_OUT4

256[2] I; PU IO PIO0_1 — General purpose port 0 input/output 1.

AADC0_7 — ADC0 input 7.

OSCT0_OUT4 — SCTimer0/PWM output 4.

PIO0_2/ADC0_6/

SCT1_OUT3

368[2] I; PU IO PIO0_2 — General purpose port 0 input/output 2.

ADC0_6 — ADC0 input 6.

OSCT1_OUT3 — SCTimer1/PWM output 3.

PIO0_3/ADC0_5/

SCT1_OUT4

4710

[2] I; PU IO PIO0_3 — General purpose port 0 input/output 3.

AADC0_5 — ADC0 input 5.

OSCT1_OUT4 — SCTimer1/PWM output 4.

PIO0_4/ADC0_4

5813

[2] I; PU IO PIO0_4 — General purpose port 0 input/output 4. This is

the ISP_0 boot pin for the LQFP48 package.

AADC0_4 — ADC0 input 4.

PIO0_5/ADC0_3

6914

[2] I; PU IO PIO0_5 — General purpose port 0 input/output 5.

AADC0_3 — ADC0 input 3.

PIO0_6/ADC0_2/

SCT2_OUT3

71016

[2] I; PU IO PIO0_6 — General purpose port 0 input/output 6.

AADC0_2 — ADC0 input 2.

OSCT2_OUT3 — SCTimer2/PWM output 3.

PIO0_7/ADC0_1

81117

[2] I; PU IO PIO0_7 — General purpose port 0 input/output 7.

AADC0_1 — ADC0 input 1.

Product data sheet Rev. 1.1 — 29 April 2015 13 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

PIO0_8/ADC0_0/TDO 9 12 19 [2] I; PU IO PIO0_8 — General purpose port 0 input/output 8.

In boundary scan mode: TDO (Test Data Out).

AADC0_0 — ADC0 input 0.

PIO0_9/ADC1_1/TDI 12 16 24 [2] I; PU IO PIO0_9 — General purpose port 0 input/output 9.

In boundary scan mode: TDI (Test Data In).

AADC1_1 — ADC1 input 1.

PIO0_10/ADC1_2

15 19 28 [2] I; PU IO PIO0_10 — General purpose port 0 input/output 10.

AADC1_2 — ADC1 input 2.

PIO0_11/ADC1_3

18 23 33 [2] I; PU IO PIO0_11 — General purp ose port 0 input/outpu t 11.

On the LQFP64 package, this pin is assigned to

CAN0_RD in ISP C_CAN mode.

AADC1_3 — ADC1 input 3.

PIO0_12/DAC_OUT

19 24 35 [3] I; PU IO PIO0_12 — General purpose port 0 input/output 12. If this

pin is configured as a digital input, the input voltage level

must not be higher than VDDA.

ADAC_OUT — DAC analog output.

PIO0_13/ADC1_6

21 29 43 [2] I; PU IO PIO0_13 — General purpose port 0 input/outp ut 13.

On the LQFP64 package, this pin is assigned to U0_RXD

in ISP USART mode.

On the LQFP48 package, this pin is assigned to

CAN0_RD in ISP C_CAN mode.

AADC1_6 — ADC1 input 6.

PIO0_14/ADC1_7/

SCT1_OUT5

22 30 45 [2] I; PU IO PIO0_14 — General purpose port 0 input/outp ut 14.

On the LQFP48 package, this pin is assigned to U0_RXD

in ISP USART mode.

AADC1_7 — ADC1 input 7.

OSCT1_OUT5 — SCTimer1/PWM output 5.

PIO0_15/ADC1_8

23 31 47 [2] I; PU IO PIO0_15 — General purpose port 0 input/outp ut 15.

On the LQFP48 package, this pin is assigned to U0_TXD

in ISP USART mode.

AADC1_8 — ADC1 input 8.

PIO0_16/ADC1_9

24 32 49 [2] I; PU IO PIO0_16 — General purpose port 0 input/outp ut 16.

On the LQFP48 package, this is the ISP_1 boot pin.

AADC1_9 — ADC1 input 9.

PIO0_17/WAKEUP/

TRST 28 39 61 [4] I; PU IO PIO0_17 — General purpose port 0 input/outp ut 17. In

boundary scan mode: TRST (Test Reset).

This pin triggers a wake-up from Deep power-down mode.

For wake up from Deep power-down mode via an external

pin, do not assign any movable function to this pin. Pull

this pin HIGH externally while in Deep power-down mode.

Pull this pin LOW to exit Deep power-down mode. A

LOW-going pulse as short as 50 ns wakes up the part.

Table 3. Pin description with fixed-pin functions

Symbol

LQFP48

LQFP64

LQFP100

Reset

state[1] Type Description

Product data sheet Rev. 1.1 — 29 April 2015 14 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

PIO0_18/

SCT0_OUT5

13 17 26 [5] I; PU IO PIO0_18 — General purpose port 0 input/outp ut 18.

On the LQFP64 package, this pin is assigned to U0_TXD

in ISP USART mode.

On the LQFP48 package, this pin is assigned to

CAN0_TD in ISP C_CAN mode.

OSCT0_OUT5 — SCTimer0/PWM output 5.

SWCLK/

PIO0_19/TCK 29 40 63 [5] I; PU I SWCLK — Serial Wire Clock. SWCLK is enabled by

default on this pin.

In boundary scan mode: TCK (Test Clock).

IO PIO0_19 — General purpose port 0 input/output 19.

SWDIO/

PIO0_20/SCT1_OUT6/

TMS

33 44 69 [5] I; PU I/O SWDIO — Serial Wire Debug I/O. SWDIO is enabled by

default on this pin.

In boundary scan mode: TMS (Test Mode Select).

I/O PIO0_20 — General purpose port 0 input/output 20.

OSCT1_OUT6 — SCTimer1/PWM output 6.

RESET/PIO0_21 34 45 71 [6] I; PU I RESET — External reset input: A LOW-going pulse as

short as 50 ns on this pin resets the device, causing I/O

ports and peripherals to take on their default states, and

processor execution to begin at address 0.

In deep power-down mode, this pin must be pulled HIGH

externally. The RESET pin can be left unconnected or be

used as a GPIO or for any movable function if an external

RESET function is not needed and the Deep power-down

mode is not us ed .

I/O PIO0_21 — General purpose port 0 input/output 21.

PIO0_22/I2C0_SCL

37 49 78 [7] IA IO PIO0_22 — General purpose port 0 input/output 22

(open-drain)

I/O I2C0_SCL — Open-drain I2C-bus clock input/outp ut.

High-current sink if I2C Fast-mode Plus is selected in the

I/O configuration register.

PIO0_23/I2C0_SDA

38 50 79 [7] IA IO PIO0_23 — General purpose po rt 0 input/output 23

(open-drain).

I/O I2C0_SDA — I2C-bus data input/output. High-current sink

if I2C Fast-mode Plus is selected in the I/O configuration

PIO0_24/SCT0_OUT6

43 58 90 [8] I; PU IO PIO0_24 — General purpose port 0 input/outp ut 24.

High-current output driver.

OSCT0_OUT6 — SCTimer0/PWM output 6.

PIO0_25/ACMP0_I4

44 60 93 [2] I; PU IO PIO0_25 — General purpose port 0 input/output 25.

AACMP0_I4 — Analog comparator 0 input 4.

PIO0_26/ACMP0_I3/

SCT3_OUT3

45 61 95 [2] I; PU IO PIO0_26 — General purpose port 0 input/outp ut 26.

AACMP0_I3 — Analog comparator 0 input 3.

OSCT3_OUT3 — SCTimer3/PWM output 3.

Table 3. Pin description with fixed-pin functions

Symbol

LQFP48

LQFP64

LQFP100

Reset

state[1] Type Description

Product data sheet Rev. 1.1 — 29 April 2015 15 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

PIO0_27/ACMP_I1

46 62 97 [2] I; PU IO PIO0_27 — General purpose port 0 input/output 27.

AACMP_I1 — Analog comparator common input 1.

PIO0_28/ACMP1_I3

47 63 98 [2] I; PU IO PIO0_28 — General purpose port 0 input/outp ut 28.

AACMP1_I3 — Analog comparator 1 input 3.

PIO0_29/ACMP2_I3/

SCT2_OUT4

48 64 100 [2] I; PU IO PIO0_29 — General purpose port 0 input/output 29.

AACMP2_I3 — Analog comparator 2 input 3.

OSCT2_OUT4 — SCTimer2/PWM output 4.

PIO0_30/ADC0_11

-11

[2] I; PU IO PIO0_30 — General purpose port 0 input/output 30.

AADC0_11 — ADC0 inp ut 11.

PIO0_31/ADC0_9

-33

[2] I; PU IO PIO0_31 — General purpose port 0 input/output 31.

On the LQFP64 package, this pin is assigned to

CAN0_TD in ISP C_CAN mode.

AADC0_9 — ADC0 input 9.

PIO1_0/ADC0_8

-45

[2] I; PU IO PIO1_0 — General purpose port 1 input/output 0.

AADC0_8 — ADC0 input 8.

PIO1_1/ADC1_0

-1523

[2] I; PU IO PIO1_1 — General purpose port 1 input/output 1.

AADC1_0 — ADC1 input 0.

PIO1_2/ADC1_4

-2536

[2] I; PU IO PIO1_2 — General purpose port 1 input/output 2.

AADC1_4 — ADC1 input 4.

PIO1_3/ADC1_5

-2841

[2] I; PU IO PIO1_3 — General purpose port 1 input/output 3.

AADC1_5 — ADC1 input 5.

PIO1_4/ADC1_10

-3351

[2] I; PU IO PIO1_4 — General purpose port 1 input/output 4.

AADC1_10 — ADC1 input 10.

PIO1_5/ADC1_11

-3452

[2] I; PU IO PIO1_5 — General purpose port 1 input/output 5.

AADC1_11 — ADC1 inp ut 11.

PIO1_6/ACMP_I2

-4673

[2] I; PU IO PIO1_6 — General purpose port 1 input/output 6.

AACMP_I2 — Analog comparator common input 2.

PIO1_7/ACMP3_I4

-5181

[2] I; PU IO PIO1_7 — General purpose port 1 input/output 7.

AACMP3_I4 — Analog comparator 3 input 4.

PIO1_8/ACMP3_I3/

SCT3_OUT4

-5384

[2] I; PU IO PIO1_8 — General purpose port 1 input/output 8.

AACMP3_I3 — Analog comparator 3 input 3.

OSCT3_OUT4 — SCTimer3/PWM output 4.

PIO1_9/ACMP2_I4

-5485

[2] I; PU IO PIO1_9 — General purpose port 1 input/output 9.

On the LQFP64 package, this is the ISP_0 boot pin.

AACMP2_I4 — Analog comparator 2 input 4.

PIO1_10/ACMP1_I4

-5991

[2] I; PU IO PIO1_10 — General purpose port 1 input/output 10.

AACMP1_I4 — Analog comparator 1 input 4.

PIO1_11 - 38 58 [5] I; PU IO PIO1_11 — General purpose port 1 input/output 11.

On the LQFP64 package, this is the ISP_1 boot pin.

Table 3. Pin description with fixed-pin functions

Symbol

LQFP48

LQFP64

LQFP100

Reset

state[1] Type Description

Product data sheet Rev. 1.1 — 29 April 2015 16 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

PIO1_12 - - 9 [5] I; PU IO PIO1_12 — General purpose port 1 inpu t/output 12.

PIO1_13 - - 11 [5] I; PU IO PIO1_13 — General purpose port 1 input/output 13.

PIO1_14/SCT0_OUT7

--12

[5] I; PU IO PIO1_14 — General purpose port 1 input/output 14.

OSCT0_OUT7 — SCTimer0/PWM output 7.

PIO1_15 - - 15 [5] I; PU IO PIO1_15 — General purpose port 1 input/output 15.

PIO1_16 - - 18 [5] I; PU IO PIO1_16 — General purpose port 1 input/output 16.

PIO1_17/SCT1_OUT7

--20

[5] I; PU IO PIO1_17 — General purpose port 1 input/output 17.

OSCT1_OUT7 — SCTimer1/PWM output 7.

PIO1_18 - - 25 [5] I; PU IO PIO1_18 — General purpose port 1 input/output 18.

PIO1_19 - - 29 [5] I; PU IO PIO1_19 — General purpose port 1 input/output 19.

PIO1_20/SCT2_OUT5

--34

[5] I; PU IO PIO1_20 — General purpose port 1 input/output 20.

OSCT2_OUT5 — SCTimer2/PWM output 5.

PIO1_21 - - 37 [5] I; PU IO PIO1_21 — General purpose port 1 input/output 21.

PIO1_22 - - 38 [5] I; PU IO PIO1_22 — General purpose port 1 input/output 22.

PIO1_23 - - 42 [5] I; PU IO PIO1_23 — General purpose port 1 input/output 23.

PIO1_24/SCT3_OUT5

--44

[5] I; PU IO PIO1_24 — General purpose port 1 input/output 24.

OSCT3_OUT5 — SCTimer3/PWM output 5.

PIO1_25 - - 46 [5] I; PU IO PIO1_25 — General purpose port 1 input/output 25.

PIO1_26 - - 48 [5] I; PU IO PIO1_26 — General purpose port 1 input/output 26.

PIO1_27 - - 50 [5] I; PU IO PIO1_27 — General purpose port 1 input/output 27.

PIO1_28 - - 55 [5] I; PU IO PIO1_28 — General purpose port 1 input/output 28.

PIO1_29 - - 56 [5] I; PU IO PIO1_29 — General purpose port 1 input/output 29.

PIO1_30 - - 59 [5] I; PU IO PIO1_30 — General purpose port 1 input/output 30.

PIO1_31 - - 60 [5] I; PU IO PIO1_31 — General purpose port 1 input/output 31.

PIO2_0 - - 62 [5] I; PU IO PIO2_0 — General purp ose port 2 input/outpu t 0.

PIO2_1 - - 64 [5] I; PU IO PIO2_1 — General purp ose port 2 input/output 1.

PIO2_2 - - 72 [5] I; PU IO PIO2_2 — General purpose port 2 input/output 2.

PIO2_3 - - 76 [5] I; PU IO PIO2_3 — General purp ose port 2 input/output 3.

PIO2_4 - - 77 [5] I; PU IO PIO2_4 — General purp ose port 2 input/output 4.

On the LQFP100 package, this is the ISP_1 boot pin.

PIO2_5 - - 80 [5] I; PU IO PIO2_5 — General purp ose port 2 input/output 5.

On the LQFP100 package, this is the ISP_0 boot pin.

PIO2_6 - - 82 [5] I; PU IO PIO2_6 — General purp ose port 2 input/output 6.

On the LQFP100 package, this pin is assigned to U0_TXD

in ISP USART mode.

PIO2_7 - - 86 [5] I; PU IO PIO2_7 — General purp ose port 2 input/output 7.

On the LQFP100 package, this pin is assigned to

U0_RXD in ISP USART mode.

Table 3. Pin description with fixed-pin functions

Symbol

LQFP48

LQFP64

LQFP100

Reset

state[1] Type Description

Product data sheet Rev. 1.1 — 29 April 2015 17 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

PIO2_8 - - 92 [5] I; PU IO PIO2_8 — General purp ose port 2 input/outpu t 8.

On the LQFP100 package, this pin is assigned to

CAN0_TD in ISP C_CAN mode.

PIO2_9 - - 94 [5] I; PU IO PIO2_9 — General purp ose port 2 input/output 9.

On the LQFP100 package, this pin is assigned to

CAN0_RD in ISP C_CAN mode.

PIO2_10 - - 96 [5] I; PU IO PIO2_10 — General purpose port 2 input/output 10.

PIO2_11 - - 99 [5] I; PU IO PIO2_11 — General purpose port 2 input/output 11.

PIO2_12 35 47 74 [5] I; PU IO PIO2_12 — General purpose port 2 input/outp ut 12. On

parts LPC1519/17/18 only.

PIO2_13 36 48 75 [5] I; PU IO PIO2_13 — General purpose port 2 input/outp ut 13. On

parts LPC1519/17/18 only.

USB_DP 35 47 74 [10] - IO USB bidirectional D+ line. Pad includes interna l 33 

series termination resistor. On parts LPC1549/48/47 only.

USB_DM 36 48 75 [10] - IO USB bidirectional D line. Pad includes internal 33 

series termination resistor. On parts LPC1549/48/47 only.

RTCXIN 31 42 66 [9] - RTC oscillator input. This input should be grounded if the

RTC is not used.

RTCXOUT 32 43 67 [9] - RTC oscillator output.

XTALIN 26 36 54 [9]

[11] - Input to the oscillator circuit and internal clock generator

circuits. Input voltage must not exceed 1.8 V.

XTALOUT 25 35 53 [9]

[11] - Output from the oscillator amplifier.

VBAT 30 41 65 - Battery supply voltage. Supplies power to the RTC. If no

battery is used, tie VBAT to VDD or to ground.

VDDA 16 20 30 - Analog supply voltage. VDD and the analog reference

voltages VREFP_ADC and VREFP_DAC_VDDCMP must

not exceed the voltage level on VDDA. VDDAshould typically

be the same voltages as VDD but should be isolated to

minimize noise and error . VDDA should be tied to VDD if the

ADC is not used.

VDD 39,

27,

22,

52,

37,

32,

70,

83,

57,

- 3.3 V supply voltage (2.4 V to 3.6 V). The voltage level on

VDD must be equal or lower than the analog supply

voltage VDDA.

VREFP_DAC_VDDCMP 14 18 27 [9] - DAC positive reference voltage and analog comparator

reference voltage. The voltage level on

VREFP_DAC_VDDCMP must be equal to or lower than

the voltage applied to VDDA.

VREFN 11 14 22 - ADC and DAC negative voltage reference. If the ADC is

not used, tie VREFN to VSS.

Table 3. Pin description with fixed-pin functions

Symbol

LQFP48

LQFP64

LQFP100

Reset

state[1] Type Description

Product data sheet Rev. 1.1 — 29 April 2015 18 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;

F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.

[2] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as analog input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin includes a 10 ns on/off

glitch filter. By default, the glitch filter is turned on.

[3] This pin is not 5 V tolerant due to special analog functionality. When configured for a digital function, this pin is 3 V tolerant and provides

standard digital I/O functions with configurable internal pull-up and pull-down resistors and hysteresis. When configured for DAC_OUT,

the digital section of the pin is disabled and this pin is a 3 V tolerant analog output. This pin includes a 10 ns on/off glitch filter . By default,

the glitch filter is turned on.

[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, and configurable hysteresis. This pin

includes a 10 ns on/off glitch filter. By default, the glitch filter is turned on. This pin is powered in deep power-down mode and can wake

up the part. The wake-up pin function can be disabled and the pin can be used for other purposes, if the RTC is enabled for waking up

the part from Deep power-down mode.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[6] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up

from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

[7] I2C-bus pin compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. The pin requires an

external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines.

Open-drain configuration applies to all functions on this pin.

[8] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes

high-current output driver.

[9] Special analog pin.

[10] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only). This pad is not 5 V tolerant.

[11] When the main oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

VREFP_ADC 10 13 21 - ADC positive reference voltage. The voltage level on

VREFP_ADC must be equal to or lower than the voltage

applied to VDDA. If the ADC is not used, tie VREFP_ADC

to VDD.

VSSA 17 21 31 - Analog ground. VSSAshould typically be the same voltage

as VSS but should be isolated to minimize noise and error.

VSSA should be tied to VSS if the ADC is not used.

VSS 41,

20,

56,

26,

27,

88,

39,

40,

68,

- Ground.

Table 3. Pin description with fixed-pin functions

Symbol

LQFP48

LQFP64

LQFP100

Reset

state[1] Type Description

Table 4. Movable functions

Function name Type Description

U0_TXD O Transmitter output for USART0.

U0_RXD I Receiver input for USART0.

U0_RTS O Request To Send output for USART0.

U0_CTS I Clear To Send input for USART0.

U0_SCLK I/O Serial clock input/output for USART0 in synchronous mode.

Product data sheet Rev. 1.1 — 29 April 2015 19 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

U1_TXD O Transmitter output for USART1.

U1_RXD I Receiver input for USART1.

U1_RTS O Request To Send output for USART1.

U1_CTS I Clear To Send input for USART1.

U1_SCLK I/O Serial clock input/output for USART1 in synchronous mode.

U2_TXD O Transmitter output for USART2.

U2_RXD I Receiver input for USART2.

U2_SCLK I/O Serial clock input/output for USART1 in synchronous mode.

SPI0_SCK I/O Serial clock for SPI0.

SPI0_MOSI I/O Master Ou t Slave In for SPI0.

SPI0_MISO I/O Master In Slave Out for SPI0.

SPI0_SSEL0 I/O Slave select 0 for SPI0.

SPI0_SSEL1 I/O Slave select 1 for SPI0.

SPI0_SSEL2 I/O Slave select 2 for SPI0.

SPI0_SSEL3 I/O Slave select 3 for SPI0.

SPI1_SCK I/O Serial clock for SPI1.

SPI1_MOSI I/O Master Ou t Slave In for SPI1.

SPI1_MISO I/O Master In Slave Out for SPI1.

SPI1_SSEL0 I/O Slave select 0 for SPI1.

SPI1_SSEL1 I/O Slave select 1 for SPI1.

CAN0_TD O CAN0 transmi t.

CAN0_RD I CAN0 receive.

USB_VBUS I USB VBUS.

SCT0_OUT0 O SCT imer0/PWM output 0.

SCT0_OUT1 O SCT imer0/PWM output 1.

SCT0_OUT2 O SCT imer0/PWM output 2.

SCT1_OUT0 O SCT imer1/PWM output 0.

SCT1_OUT1 O SCT imer1/PWM output 1.

SCT1_OUT2 O SCT imer1/PWM output 2.

SCT2_OUT0 O SCT imer2/PWM output 0.

SCT2_OUT1 O SCT imer2/PWM output 1.

SCT2_OUT2 O SCT imer2/PWM output 2.

SCT3_OUT0 O SCT imer3/PWM output 0.

SCT3_OUT1 O SCT imer3/PWM output 1.

SCT3_OUT2 O SCT imer3/PWM output 2.

SCT_ABORT0 I SCT abort 0.

SCT_ABORT1 I SCT abort 1.

ADC0_PINTRIG0 I ADC0 external pin trigger input 0.

ADC0_PINTRIG1 I ADC0 external pin trigger input 1.

ADC1_PINTRIG0 I ADC1 external pin trigger input 0.

ADC1_PINTRIG1 I ADC1 external pin trigger input 1.

Table 4. Movable functions …continued

Function name Type Description

Product data sheet Rev. 1.1 — 29 April 2015 20 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

DAC_PINTRIG I DAC external pin trigger input.

DAC_SHUTOFF I DAC shut-off external input.

ACMP0_O O Analog comparator 0 output.

ACMP1_O O Analog comparator 1 output.

ACMP2_O O Analog comparator 2 output.

ACMP3_O O Analog comparator 3 output.

CLKOUT O Clock output.

ROSC O Analog comparator ring oscillator output.

ROSC_RESET I Analog comparator ring oscillator reset.

USB_FTOGGLE O USB frame toggle. Do not assign this function to a pin until a USB

device is connected and the first SOF interrupt has been received

by the device.

QEI_PHA I QEI phase A input.

QEI_PHB I QEI phase B input.

QEI_IDX I QEI index input.

GPIO_INT_BMAT O Output of the pattern match engine.

SWO O Serial wire output.

Table 5. Pins connected to the INPUT multiplexer and SCT IPU

Symbol

LQFP48

LQFP64

LQFP100

Description

PIO0_2/ADC0_6/SCT1_OUT3 3 6 8 SCT0 input multiplexer

PIO0_3/ADC0_5/SCT1_OUT4 4 7 10 SCT0 input multiplexer

PIO0_4/ADC0_4 5 8 13 SCT2 input multiplexer

PIO0_5/ADC0_3 6 9 14 FREQMEAS

PIO0_7/ADC0_1 8 11 17 SCT3 input multiplexer

PIO0_14/ADC1_7/SCT1_OUT5 22 30 45 SCTIPU input SAMPLE_IN_A0

PIO0_15/ADC1_8 23 31 47 SCT1 input multiplexer

PIO0_16/ADC1_9 24 32 49 SCT1 input multiplexer

PIO0_17/WAKEUP/TRST 28 39 61 SCT0 input multiplexer

SWCLK/PIO0_19/TCK 29 40 63 FREQMEAS

RESET/PIO0_21 34 45 71 SCT1 input multiplexer

PIO0_25/ACMP0_I4 44 60 93 SCTIPU input SAMPLE_IN_A1

PIO0_27/ACMP_I1 46 62 97 SCT2 input multiplexer

PIO0_30/ADC0_11 - 1 1 FREQMEAS

SCT0 input multiplexer

PIO0_31/ADC0_9 - 3 3 SCT1 input multiplexer

PIO1_4/ADC1_10 - 33 51 SCT1 input multiplexer

PIO1_5/ADC1_11 - 34 52 SCT1 input multiplexer

PIO1_6/ACMP_I2 - 46 73 SCT0 input multiplexer

Table 4. Movable functions …continued

Function name Type Description

Product data sheet Rev. 1.1 — 29 April 2015 21 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8. Functional description

8.1 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers hig h

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware division,

hardware single-cycle multiply, interruptible/continuable multiple load and store

instructions, automatic state save and restore for interrupts, tightly integrated interrupt

controller, and multiple core buses capable of simultaneous accesses.

Pipeline techniques are em ployed so that all p arts of the processing and memory system s

can operate continuously. Typically, while one instruction is being executed, its successo r

is being decoded, and a thir d instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual, which is available on the official ARM website.

8.2 Memory Protection Unit (MPU)

The LPC15xx have a Memory Protection Unit (MPU) which can be used to improve the

reliability of an embedded system by protecting critical data within the user application.

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory r egio ns, allowing me mor y regi ons to be de fined as re ad -onl y

and detecting unexpected memory accesses that could potentially break the system.

PIO1_7/ACMP3_I4 - 51 81 SCT0 input multiplexer

PIO1_11 - 38 58 SCT3 input multiplexer

SCTIPU input SAMPLE_IN_A2

PIO1_12 - - 9 SCT0 input multiplexer

PIO1_13 - - 11 SCT0 input multiplexer

PIO1_15 - - 12 SCT1 input multiplexer

PIO1_16 - - 18 SCT1 input multiplexer

PIO1_18 - - 25 SCT2 input multiplexer

PIO1_19 - - 29 SCT2 input multiplexer

PIO1_21 - - 37 SCT3 input multiplexer

PIO1_22 - - 38 SCT3 input multiplexer

PIO1_26 - - 48 SCTIPU input SAMPLE_IN_A3

PIO1_27 - - 50 FREQMEAS

Table 5. Pins connected to the INPUT multiplexer and SCT IPU

Symbol

LQFP48

LQFP64

LQFP100

Description

Product data sheet Rev. 1.1 — 29 April 2015 22 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU support s up to eight r egions each of which can

be divided into eight subregions. Accesses to memory locations that are not defined in the

MPU regions, or not permitted by the region setting, will cause the Memory Management

Fault exception to take place.

8.3 On-chip flash programming memory

The LPC15xx contain up to 256 kB on-chip flash program memory. The flash can be

programmed using In-System Programming (ISP) or In-Application Programming (IAP)

via the on-chip boot loader software. Flash updates via USB are supported as well.

The flash memor y is divide d int o 4 kB sect ors with each sector consisting of 16 pages.

Individual pages of 256 byte each can be erased using the IAP erase page command.

8.3.1 ISP pin configuration

The LPC15xx support s ISP via the USAR T0, C_CAN, or USB interfaces. Th e ISP mode is

determined by the state of two pins (ISP_0 and ISP_1) at boot time:

The ISP pin assignment is different for each package, so that the fewest functions

possible are blocked. No more than four pins must be set aside for entering ISP in any

ISP mode. The boot code assigns two ISP pins for each packag e, which are probed when

the part boots to determine whether or not to enter ISP mode. Once the ISP mode has

been determined, the boot loader configu res the necessary serial pins for each pa ckage.

Pins which are not configured by the boot loader for th e selected boot mode ( for e xample

CAN0_RD and CAN0_TD in USART mode) can be assigned to any function through the

switch matrix.

Table 6. ISP modes

Boot mode ISP_0 ISP_1 Description

No ISP HIGH HIGH ISP byp a ssed. Part attempt s to boot

from flash. If the user code in flash is

not valid, then enters ISP via USB.

C_CAN HIGH LOW Part enters ISP via C_CAN.

USB LOW HIGH Part enters ISP via USB.

USART0 LOW LOW Part enters ISP via USART0.

Table 7. Pin assignments for ISP modes

Boot pin LQFP48 LQFP64 LQFP100

ISP_0 PIO0_4 PIO1_9 PIO2_5

ISP_1 PIO0_16 PIO1_11 PIO2_4

USART mode

U0_TXD PIO0_15 PIO0_18 PIO2_6

U0_RXD PIO0_14 PIO0_13 PIO2_7

C_CAN mode

CAN0_TD PIO0_18 PIO0_31 PIO2_8

CAN0_RD PIO0_13 PIO0_11 PIO2_9

USB mode

USB_VBUS (same as ISP_1) PIO0_16 PIO1_11 PIO2_4

Product data sheet Rev. 1.1 — 29 April 2015 23 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.4 EEPROM

The LPC15xx contain 4 kB of on-chip byte-erasable and byte-programmable EEPROM

data memor y . The EEPROM can be pr ogrammed using In-Application Programming (I AP)

via the on-chip boot loade r software.

8.5 SRAM

The LPC15xx cont ain a total 36 kB, 20 kB or 12 kB of contiguous, on-chip static RAM

memory. For each SRAM configuration, the SRAM is divided into three blocks: 2 x 16 kB +

4 kB for 36 kB SRAM, 2 x 8 kB + 4 kB for 20 kB SRAM, and 2 x 4 kB + 4 kB for 12 kB

SRAM. The bottom 16 kB, 8 kB, or 4 kB are enabled by the bootloader and cannot be

disabled. The next two SRAM blocks in each configuration can be disabled or enabled

individually in the SYSCON block to save power.

8.6 On-chip ROM

The on-chip ROM contains the boot loader and the following Applicatio n Prog ram min g

Interfaces (APIs):

•In-System Programming (ISP) and In-Application Programming (IAP) support for flash

including IAP erase page command.

•IAP support for EEPROM.

•Flash updates via USB and C_CAN supported.

•USB API (HID, CDC, and MSC drivers).

•DMA, I2C, USART, SPI, and C_CAN drivers.

•Power profiles for configuring power consumption and PLL settings.

Table 8. LPC15xx SRAM configurations

SRAM0 SRAM1 SRAM2

LPC1549/19 (total SRAM = 36 kB)

address range 0x0200 0000 to

0x0200 3FFF 0x0200 4000 to

0x0200 7FFF 0x0200 8000 to

0x0200 8FFF

size 16 kB 16 kB 4 kB

control cannot be disabled disable/enable disable/enable

default enabled enabled enabled

LPC1548/18 (total SRAM = 20 kB)

address range 0x0200 0000 to

0x0200 1FFF 0x0200 2000 to

0x0200 3FFF 0x0200 4000 to

0x0200 4FFF

size 8 kB 8 kB 4 kB

control cannot be disabled disable/enable disable/enable

default enabled enabled enabled

LPC1547/17 (total SRAM = 12 kB)

address range 0x0200 0000 to

0x0200 0FFF 0x0200 1000 to

0x0200 1FFF 0x0200 2000 to

0x0200 2FFF

size 4 kB 4 kB 4 kB

control cannot be disabled disable/enable disable/enable

default enabled enabled enabled

Product data sheet Rev. 1.1 — 29 April 2015 24 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

•Power mode configuration for configuring deep-sleep, power-down, and deep

power-down modes.

•ADC drivers for analog-to-digital conversion and ADC calibration.

Product data sheet Rev. 1.1 — 29 April 2015 25 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.7 AHB multilayer matrix

Fig 9. AHB multilayer matrix

ARM

CORTEX-M3

TEST/DEBUG

INTERFACE

DMA

AHB-TO-APB

BRIDGE0

AHB-TO-APB

BRIDGE1

EEPROM

HS GPIO

slaves

SRAM2

System

bus

I-code

bus

D-code

bus

masters

FLASH

ROM

AHB MULTILAYER MATRIX

= master-slave connection

DAC ACMP

WWDT

ADC0

RIT

I2C0 QEI

SWM SPI0

SPI1

USART1PMU

SYSCON

USART2

PINT

GINT0 GINT1

MRT

ADC1

USB

SRAM0

SRAM1

SCTIMER0/PWM

SCTIMER1/PWM

SCTIMER2/PWM

SCTIMER3/PWM

CRC

INPUT MUX RTC

SCTIPU FLASH CTRL

IOCON EEPROM CTRL

USART2 C_CAN

aaa-010870

Product data sheet Rev. 1.1 — 29 April 2015 26 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.8 Memory map

See Section 8.5 “SRAM” for SRAM configuration.

Fig 10. Memory map

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 8000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 0000

0x4005 8000

0x4005 C000

0x4008 0000

0x4001 C000

0x4001 4000

0x4000 0000

0x4002 C000

0x4003 0000

reserved

256 kB flash

0x0000 0000

0 GB

4 GB

0x0200 0000

0x0300 8000

0x0320 0000

0x0320 1000

0x1C01 0000

0x1C01 4000

0xFFFF FFFF

4 kB EEPROM

reserved

0x1000 0000

0x1C00 0000

APB peripherals 0

0x1C01 8000

0x1C01 C000

0x1C00 4000

CRC

GPIO

0x1C00 8000

0x1C00 C000

DMA

0x1C02 4000

0x4000 0000

0x4008 0000

APB peripherals 1

0x400F 0000

0x0200 9000

36 kB SRAM (LPC1549/19)

0x0200 5000

20 kB SRAM (LPC1548/18)

0x0200 3000

12 kB SRAM (LPC1547/17)

reserved

LPC15xx

0x0004 0000

32 kB boot ROM

0x0000 0000

0x0000 00C0

active interrupt vectors

reserved

0x0300 0000

reserved

SCTimer0/PWM

0x1C02 0000

SCTimer1/PWM

SCTimer2/PWM

0x1C02 8000

SCTimer3/PWM

0x4005 4000

0x4007 4000

0xE000 0000

0xE010 0000

private peripheral bus

0x4007 8000

ADC0

DAC

analog comparators ACMP

reserved

RTC

WWDT

reserved

USART0

QEI

reserved

USART1

SPI0

reserved

I2C0

SYSCON

INPUT MUX

reserved

switch matrix SWM

PMU

SPI1

reserved

4:3

9:7

28:23

13:12

31:30

APB peripherals

0x4008 4000

0x400A 0000

0x400A 4000

0x400A C000

0x400B 4000

0x400C 0000

0x400C 4000

0x400E 8000

0x400E C000

0x400F 0000

0x400F 4000

0x400F 8000

0x400F 0000

0x400B 0000

0x400A 8000

0x400B 8000

0x400B C000

0x400F C000

ADC1

reserved

MRT

reserved

RIT

SCTIPU

flash ctrl FMC

reserved

PINT

reserved

C_CAN

IOCON

GINT0

GINT1

USART2

reserved

EEPROM CTRL

7:1

25:17

USB

aaa-010871

Product data sheet Rev. 1.1 — 29 April 2015 27 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.9 Nested Vectored Interrupt controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M3. The tight

coupling to the CPU allows for low interrupt latency and ef ficient processing of late arriving

interrupts.

8.9.1 Features

•Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3.

•Tightly coupled interrupt controller provides low interrupt latency.

•Controls system exceptions and peripheral interrupts.

•The NVIC supports 47 vectored interrupts.

•Eight programmable interrupt priority levels with hardware priority level masking.

•Software interrupt generation using the ARM exceptions SVCall and PendSV.

•Support for NMI .

•ARM Cortex-M3 Vector table offset regi ster VTOR implemented.

8.9.2 Interrupt sources

Typically, each peripheral device has one interrupt line connected to the NVIC but can

have several interrupt flags. Individual interrupt flags can also represent mor e than one

interrupt source.

8.10 IOCON block

The IOCON block configures the electrical properties of the pins such as pull-up and

pull-down resistors, hysteresis, open-drain modes and input filters.

Remark: The pin function and whether the pin operates in digital or analog mode are

entirely under the control of the switch matrix.

Enabling an analog function through the switch matrix disables the digital pad. However,

the internal pull-up and pull-d own resistors as well as th e pin hysteresis must be disa bled

to obtain an accurate reading of the analog input.

8.10.1 Features

•Programmable pull-up, pull-down, or repeater mode.

•All pins (except PIO0_22 and PIO0_23) are pulled up to 3.3 V (VDD = 3.3 V) if their

pull-up resistor is enabled.

•Programmable pseudo open-drain mode.

•Programmable (on/ off) 10 ns glitch filter on 36 pins (PIO0_0 to PIO0_17, PIO0_25 to

PIO0_31, PIO1_0 to PIO1_10). The glitch filter is turned on by default.

•Programmable hysteresis.

•Programmable input inverter.

•Digital filter with programmable filter constant on all pins.

8.10.2 Standard I/O pad configuration

Figure 11 shows the possible pin modes for standard I/O pins with analog input function:

Product data sheet Rev. 1.1 — 29 April 2015 28 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

•Digital output driver with configurable open-drain output

•Digital input: Weak pull-up resistor (PMOS device) enabled/disabled

•Digital input: Weak pull-down resistor (NMOS device) enabled/disabled

•Digital input: Repeater mode enabled/disabled

•Digital input: Input digital filter configurable on all pins

•Digital input: Input glitch filter enabled/disabled on select pins

•Analog input

8.11 Switch Matrix (SWM)

The switch matrix controls the function of each digital or mixed analog/digital pin in a

highly flexible way by allowing to connect many functions like the USART, SPI, SCT, and

I2C functions to any pin that is not power or ground. These functions are called movable

functions and are listed in Table 4.

Functions that need specialized pads like the ADC or analog comp arator inputs can be

enabled or disabled through the switch matrix. These functions are called fixed-pin

functions and cannot move to other pins. The fixed-pin functions are listed in Table 3. If a

fixed-pin function is disabled, any other movable function can be assigned to this pin.

Fig 11. Standard I/O pin configurat ion

VDD VDD

ESD

VSS

ESD

strong

pull-up

strong

pull-down

VDD

weak

pull-up

weak

pull-down

open-drain enable

output enable

repeater mode

enable

pull-up enable

pull-down enable

select data

inverter

data output

data input

select glitch

filter

analog input

select analog input

pin configured

as digital output

driver

pin configured

as digital input

pin configured

as analog input

PROGRAMMABLE

DIGITAL FILTER 10 ns GLITCH

FILTER

aaa-010776

Product data sheet Rev. 1.1 — 29 April 2015 29 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.12 Fast General-Purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function through the switch

matrix are co ntrolled by the GPIO register s. Pins may be dynamically configured as inputs

or outputs. Multiple outputs can be set or cleared in one write operation.

LPC15xx use accelerated GPIO functions.

•An entire port value can be written in one instruction.

•Mask, set, and clear operations are supported for the entire port.

8.12.1 Features

•Bit level port registers allow a single instruction to set and clear any number of bits in

one write operation.

•Direction control of individual bits.

8.13 Pin interrupt/pattern match engine (PINT)

The pin interrupt block configures up to e ight pins from the digit al pins on port s 1 and 2 for

providing eight external interru pts connected to the NVIC. The input multiplexer block is

used to select the pins.

The pattern match engine can be used, in conjunction with software, to create complex

state machines based on pin inp uts.

Any digital pin on ports 0 and 1 can be configured through the SYSCON block as input to

the pin interrupt or pattern match engine. The registers that control the pin interrupt or

pattern match engine are located on the IO+ bus for fast single-cycle access.

8.13.1 Features

•Pin interrupts

–Up to eight pins can be selected from all digital pins on ports 0 and 1 as edge- or

level-sensitive interrupt requests. Each request creates a separate interrupt in the

NVIC.

–Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

–Level-sensitive interrupt pins can be HIGH- or LOW-active.

–Pin interrupts can wake up the part from sleep mode, deep-sleep mode, and

power-down mode.

•Pin interrupt pattern match engine

–Up to 8 pins can be selected from all digit al pins on port s 0 an d 1 to contrib ute to a

boolean expression. The boolean expression consists of specified levels and/or

transitions on various combinations of these pins.

–Each minterm (product term) comprising the specified boolean expression can

generate its own, dedicated interrupt request.

–Any occurrence of a pattern match can be programmed to also generate an RXEV

notification to the ARM CPU.

–The pattern match engine does not facilitate wake-up.

Product data sheet Rev. 1.1 — 29 April 2015 30 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.14 GPIO group interrupts (GINT0/1)

The GPIO pins can be used in several ways to set pins as inputs or outputs and use the

inputs as combina tions of level and edge sensitive interrupt s. For each port/pi n connected

to one of the two the GPIO Grouped Interrupt blocks (GINT0 and GINT1), the GPIO

grouped interr up t re gisters determ in e whic h pin s ar e en ab le d to ge n er at e int er ru pts and

what the active polarities of each of those inputs are.

The GPIO grouped interrupt registers also select whether the interrupt output will be level

or edge triggered and whether it will be based on the OR or the AND of all of the enabled

inputs.

When the designated pattern is detected on the selected input pins, the GPIO grouped

interrupt block generates an interrupt. If the part is in a power-savings mode, it first

asynchronously wakes the part up prior to asserting the interrupt re quest. The interrupt

request line can be cleared by writing a one to the interrupt status bit in the control

8.14.1 Features

• Two group interrupts are supported to reflect two distinct interrupt patterns.

•The input s from any number of digit al pins can be enabled to co ntribute to a combined

group interrupt.

• The polarity of each input enabled for the group interrupt can be configured HIGH or

LOW.

• Enabled interrupts can be logically combined through an OR or AND operation.

•The grouped inte rrupts can wake up the part from slee p, deep-sleep or power-down

modes.

8.15 DMA controller

The DMA controller can access all memories and the USART, SPI, I2C, and DAC

peripherals using DMA requests. DMA transfers can also be triggered by internal events

like the ADC interrupts, the SCT DMA request signals, or the analog comparator outputs.

8.15.1 Features

•18 channels with 14 channels connected to peripheral request inputs.

•DMA operations can be trigge red by on-chip events. Each DMA channel can select

one trigger input from 24 sources through the input multiplexer.

•Priority is user selectable for each channel.

•Continuous priority arbitration.

•Address cache with four entries.

•Efficient use of data bus.

•Supports single transfers up to 1,024 words.

•Address increment options allow packing and/or unpacking data.

Product data sheet Rev. 1.1 — 29 April 2015 31 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.16 Input multiplexing (Input mux)

The input multiplexer allows to select from multiple external and internal sources for the

SCT inputs, DMA trigger inputs, and the freque n cy me as ur e blo ck . Th e in p ut multiple xe r

is implemented as a register interface with one source selection register for each input.

The input multiplexer can for example connect SCT outputs, the ADC interrupts, or the

comparator outputs to the SCT input s and thus enables the SCT to use a large variety of

events to control the timing operation.

The ADCs and analog co mparato rs also support in put multiplexing using so urce selection

registers as p art of their configuration registers.

8.17 USB interface

Remark: The USB interface is available on parts LPC1549/48/47 only.

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host contro ller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports

hot-plugging an d dynamic configuration of th e devices. All transactions are initiated by the

host controller.

The USB interface consists of a full-speed device controller with on-chip PHY (PHYsical

layer) for device functions.

Remark: Configure the part in default power mode with the power profiles before using

the USB (see Section 8.40.1). Do not use the USB when the part runs in performance,

efficiency, or low-powe r mode.

8.17.1 Full-speed USB device controller

The device controller enable s 12 Mbit/s data exchange with a USB Host controller. It

consists of a register interface, serial interface engine , and endpoint buffer memory. The

serial interface engine decod es the USB data stream and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

8.17.1.1 Features

•Dedicated USB PLL available.

•Fully compliant with USB 2.0 specification (full speed).

•Supports 10 physical (5 logical) endpoints including one control endpoint.

•Single and double buffering supported.

•Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.

•Supports wake-up from Deep-sleep mode and Power-down mode on USB activity

and remote wake-up.

•Supports SoftConnect functionality through internal pull-up resistor.

•Internal 33  series termination resistor s on USB_DP and USB_DM lines eliminate

the need for external series resistors.

•Supports Link Power Management (LPM).

Product data sheet Rev. 1.1 — 29 April 2015 32 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.18 USART0/1/2

Remark: All USART functions are movable functions and are assigned to pin s through

the switch matrix. Do not connect USART functions to the open-drain pins PIO0_22 and

PIO0_23.

Interrupts generated by the USART peripherals can wake up the part from Deep-sleep

and power-do wn modes if the USART is in synchronous mode, the 32 kHz mode is

enabled, or the CTS interrupt is enabled.

8.18.1 Features

•Maximum bit rates of 4.5 Mb it/s in asynchronous mode, 15 Mbit/s in synchronous

mode master mode, and 18 Mbit/s in synchronous slave mode.

•7, 8, or 9 data bits and 1 or 2 stop bits.

•Synchronous mode with master or slave operation. Includes dat a phase selection and

continuous clock option.

•Multiprocessor/multidrop (9-bit) mode with software address compare.

•RS-485 transceiver output enable.

•Autobaud mode for automatic baud rate detection

•Parity generation and checkin g: odd, even, or none.

•Software selectable oversampling from 5 to 16 clocks in asynchronous mode.

•One transmit and one receive data buffer.

•RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

•Received data and status can optionally be read from a single register

•Break generation and detection.

•Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

•Built-in Baud Rate Generator with auto-baud function.

•A fractional rate divider is shar ed among all USARTs.

•Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

•Loopback mode for testing of data and flow control.

•In synchronous slave mode, wakes up the part from deep-sleep and power-down

modes.

•Special operating mode allows operation at up to 9600 baud using the 32 kHz RTC

oscillator as the UART clock. This mode can be used while the device is in

Deep-sleep or Power-down mode and can wake-up the device when a character is

received.

• USART transmit and receive functions work with the system DMA controller.

8.19 SPI0/1

All SPI functions are movable functions and are assigned to pins through the switch

matrix. Do not connect SPI functions to the open-drain pins PIO0_22 and PIO0_23.

Product data sheet Rev. 1.1 — 29 April 2015 33 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.19.1 Features

•Maximum data rates of 17 Mbit/s in master mode and slave mode for SPI functions

connected to all digital pins except PIO0_22 and PIO0_23.

•Data transmit s of 1 to 16 bits sup ported directly. Larger frames suppor ted by sof tware.

•Master and slave operation.

•Data can be transmitte d to a slave without the need to read incoming data. This can

be useful while setting up an SPI memory.

•Control information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

•Up to four Slave Select input/outputs with selectable polarity and flexible usage.

•Supports DMA transfers: SPIn transmit and receive functions work with the system

DMA controller.

Remark: Texas Instruments SSI and National Microwire modes are not supported.

8.20 I2C-bus interface

The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a r eceiver-only de vice ( e.g., an LCD driver) or a tra nsmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can oper ate in eithe r master or sl ave mo de, dependin g on whe ther th e chip ha s

to initiate a data transfer or is only addressed. The I2C is a multi-master bus an d ca n be

controlled by more than one bus master connected to it.

The I2C-bus functions are fixed-pin functions and must be enabled through the switch

matrix on the open-drain pins PIO0_22 and PIO0_23.

8.20.1 Features

•Supports standard and fast mode with data rates of up to 400 kbit/s.

•Supports Fast-mode Plus with bit rates up to 1 Mbit/s.

•Fail-safe operation: When the power to an I2C-bus device is switched off, the SDA

and SCL pins connected to the I2C-bus are floating and do not distur b th e bu s.

•Independent Master, Slave, and Monitor functions.

•Supports both Multi-mas te r and Mu lti- m ast er with Slav e fu nct ion s.

•Multiple I2C slave addresses supported in hardware.

•One slave address ca n be selectively qualified with a b it mask or an ad dress range in

order to respon d to multiple I2C bus addresses.

•10-bit addressing supported with software assist.

•Supports SMBus.

•Supported by on- ch ip ROM A PI.

Product data sheet Rev. 1.1 — 29 April 2015 34 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.21 C_CAN

Controller Area Network (CAN) is the definition of a high performance communication

protocol for seri al data communication. The C_ CAN controller is desig ned to provide a full

implement ation of the CAN protocol according to the CAN Specification V ersion 2.0B. The

C_CAN controller can build powerful local networks with low-cost multiplex wiring by

supporting distributed real-time control with a high level of reliability.

The C_CAN functions are movable functions and are assigned to pins throug h the switch

matrix. Do not connect C_CAN functions to the open-drain pins PIO0_22 and PIO0_23.

8.21.1 Features

•Conforms to protocol version 2.0 parts A and B.

•Supports bit rate of up to 1 Mbit/s.

•Supports 32 Message Objects.

•Each Message Object has its own identifier mask.

•Provides programmable FIFO mode (concatenation of Message Objects).

•Provides maskable interrupts.

•Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN

applications.

•Provides programmable loop-back mode for self-test operation.

8.22 PWM/timer/motor control subsystem

The SCTimer/PWMs (State Configurable Timer/Pulse Width Modulators) and the analog

peripherals support multiple ways of interconnecting their inputs and output s and of

interfacing to th e pins and the DMA controller. Using the highly flexible and programmable

connection scheme makes it easy to configure various subsystems for motor control and

complex timing and tracking applica tions. Specifically, the inputs to the SCTs and the

trigger inputs of the ADCs and DMA are selected through the input multiplexer which

offers a choice of many possible sources for each input or trigger. SCT outputs are

assigned to pins through the switch matrix allowing for many pinout solutions.

8.22.1 SCtimer/PWM subsystem

The SCTimer/PWMs can be configured to build a PWM controller with multiple output s by

programming the MATCH and MATCHRELOAD registers to control the base frequency

and the duty cycle of each SCTimer/PWM output. More complex waveforms that span

multiple counter cycles or change behavior across or within counter cycles can be

generated using the state capa bilit y built into the SCTimer/PWMs.

Combining the PWM functions with the analog fu nctions, the PWM output can react to

control signals like comparator outputs or the ADC interrupt s. The SCT IPU adds

emergency shut-down functions and pre-processing of controlling events. For an overview

of the PWM subsystem, see Figure 12 “PWM-Analog subsystem”.

For high-speed PWM functionality, use only outputs that are fixed-pin functions to

minimize pin-to-pin differences in output skew. See also Table 22 “SCTimer/PWM output

dynamic characteristics”. This reduces the number of PWM outputs to five for each large

SCT.

Product data sheet Rev. 1.1 — 29 April 2015 35 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.22.2 Timer controlled subsystem

The timers, the anal og componen t s, and th e DMA can be configur ed to form a subsystem

that can run independently of the main processor under the control of the SCTs and any

events that are generated by the A/D converters, the comp arators, the SCT output

themselves, or the external pins. A/D conversions can be triggered by the timer outputs,

the comparator outputs or b y events from external pins. Data can be tr ansferred from the

ADCs to memory using the DMA contr oller , and the DMA tra nsfers can be triggered by the

ADCs, the comparator outputs, or by the timer outputs.

For an overview of the subsystem, see Figure 13 “Subsystem with timers, switch matrix,

DMA, and analog components”.

Fig 12. PWM-Analog subsystem

INPUT MUX

SWITCH MATRIX

TEMP SENSOR

VDDA DIVIDER

VOLTAGE

REFERENCE

TRIGGER

ADC0/ADC1

ANALOG IN

INTERRUPTS

ACMP0

ACMP1

ACMP2

ACMP3

OUTPUTS

SCT IPU

ANALOG IN

TIMER0

MATCH/

MATCHRELOAD

SCT0

OUTPUTS

TIMER1 MATCH/

MATCHRELOAD

SCT1

OUTPUTS

TIMER2 MATCH/

MATCHRELOAD

SCT2

OUTPUTS

TIMER3 MATCH/

MATCHRELOAD

SCT3

OUTPUTS

8 x PWM OUT

6 x PWM OUT

SCT0/1/2/3

digital signal from/to pins

analog signal from/to pins

digital signal internal

analog signal internal

analog peripheral

digital peripheral

THRESHOLD CROSSING

aaa-010873

Product data sheet Rev. 1.1 — 29 April 2015 36 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.22.3 SCTimer/PWM in the large configuration (SCT0/1)

Remark: For applications that require exact timing of the SCT outputs (for example

PWM), assign the outputs only to fixed-pin functions to ensure that the output skew is

nearly the same for all outputs.

8.22.3.1 Features

The following feature list summarizes the configuration for the two large SCTs. Each large

SCT has a companion small SCT (see Section 8.22.4) with fewer inputs and outputs and

a reduced feature set.

•Each SCT supports:

–16 match/capture registers

–16 events

–16 states

–Match register 0 to 5 support a fractional component for th e dither engine

Fig 13. Subsystem with timers, switch matrix, DMA, and analog compon ents

TEMP SENSOR

VDDA DIVIDER

VOLTAGE

REFERENCE

ACMP0

ACMP1

ACMP2

ACMP3

TIMER0 (SCT0)

TIMER1 (SCT1)

TIMER2 (SCT2)

TIMER3 (SCT3)

INPUT MUX

OUTPUTS

TRIGGER

ADC0/ADC1

DAC

SCT IPU

ANALOG IN

INPUT MUX

DMA

SWITCH MATRIX

ANALOG IN

INTERRUPTS

NVIC

DAC_SHUTOFF

digital signal from/to pins

analog signal from/to pins

digital signal internal

analog signal internal

analog peripheral

digital peripheral

THRESHOLD CROSSING

aaa-010874

Product data sheet Rev. 1.1 — 29 April 2015 37 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

–8 inputs and 10 output s

–DMA support

•Counter/timer features:

–Configurable as two 16-bit counters or one 32-bit counter.

–Counters clocked by system clock or selected input.

–Configurable as up counters or up-do wn counters.

–Configurable number of match and capture registers. Up to 16 match and capture

registers total.

–Upon match create the following event s: stop, halt, limit counter or change counter

direction; togg le ou tp u ts; create an inte rr up t; chan g e the state.

–Counter value can be loaded into capture register trig gered by match or

input/output toggle.

•PWM features:

–Counters can be used in conjunction with match registers to toggle outputs and

create time-proportioned PWM signals.

–Up to eight single-edge or dual-edge controlled PWM outputs with up to eight

independent duty cycles when configured as 32-bit timers.

•Event creation features:

–The following conditions define an event: a counter match condition, an input (or

output) condition such as an rising or falling edge or level, a combination of match

and/or input/output condition.

–Events can only have an effect while the counter is running.

–Selected events can limit, halt, start, or stop a counter or change its direction.

–Events trigge r state changes, output toggles, interrupts, and DMA transactions.

–Match register 0 can be used as an automatic limit.

–In bi-directional mode, events can be enabled based on the count direction.

–Match events can be held until an ot he r qu a lifyin g ev en t occurs.

•State control features:

–A state is defined by the set of events that are allowed to happen in the state.

–A state changes into another state as result of an event.

–Each event can be assigned to one or more st ates.

–State variable allows sequencing across multiple counter cycles.

•Dither engine.

•Integrated with an inp ut pre -p ro ce ssin g unit (SCT IPU) to combine or dela y input

events.

Inputs an d output s on the SCTimer0/PWM and SCTimer1/PWM are configured as follows:

•8 inputs

–7 inputs. Each input except input 7 can select one of 23 sources from an input

multiplexer.

–One input connected directly to the SCT PLL for a high-speed dedicated clock

input.

Product data sheet Rev. 1.1 — 29 April 2015 38 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

•10 outputs (some outputs are connected to multiple locations)

–Three outputs connected to external pins throug h the switch matrix as movable

functions.

–Five outputs connected to external pins through the switch matrix as fixed-pin

functions.

–Two outputs connected to the SCTIPU to sample or latch input events.

–One output connected to the other large SCT

–Four outputs connected to one small SCT

–Two outputs connected to each ADC trigger input

8.22.4 State-Configurable Timers in the small configuration (SCT2/3)

Remark: For applications that require exact timing of the SCT outputs (for example

PWM), assign the outputs only to fixed-pin functions to ensure that the output skew is

nearly the same for all outputs.

8.22.4.1 Features

The following feature list summa rizes the configuration for the two small SCTs. Each small

SCT has a companion large SCT (see Section 8.22.3) with more input s and outp uts and a

dither engine.

•Each SCT supports:

–8 match/capture registers

–10 events

–10 states

–3 inputs and 6 outputs

–DMA support

•Counter/timer features:

–Configurable as two 16-bit counters or one 32-bit counter.

–Counters clocked by bus clock or selected input.

–Up counters or up-down counters.

–Configurable number of match and capture registers. Up to 16 match and capture

registers total.

–Upon match create the following events: interrupt, stop, limit timer or change

direction; toggle outputs; change state.

–Counter value can be loaded into capture register trig gered by match or

input/output toggle.

•PWM features:

–Counters can be used in conjunction with match registers to toggle outputs and

create time-proportioned PWM signals.

–Up to six single-edge or dual-edge controlled PWM outputs with independent duty

cycles if configured as 32-bit timers.

•Event creation features:

Product data sheet Rev. 1.1 — 29 April 2015 39 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

–The following conditions define an event: a counter match condition, an input (or

output) condition, a combination of a match and/or and input/output condition in a

specified state.

–Selected events can limit, ha lt, start, or stop a counter.

–Events control state changes, outputs, interrupts, and DMA requests.

–Match register 0 can be used as an automatic limit.

–In bi-directional mode, events can be enabled based on the count direction.

–Match events can be held until an ot he r qu a lifyin g ev en t occurs.

•State control features:

–A state is defined by events that can take place in the state while the counter is

running.

–A state changes into another state as result of an event.

–Each event can be assigned to one or more st ates.

–State variable allows sequencing across multiple counter cycles.

•Integrated with an inp ut pre -p ro ce ssin g unit (SCT IPU) to combine or dela y input

events.

Inputs an d output s on the SCTimer2/PWM and SCTimer3/PWM are configured as follows:

•3 inputs. Each input selects one of 21 sources from a pin multiplexer.

•6 outputs (some outputs are connec te d to m ultip le locat ion s)

–Three outputs connected to external pins throug h the switch matrix as movable

functions.

–Three outputs connected to external pins through the switch matrix as fixed-pin

functions.

–Two outputs connected to the SCT IPU to sample or latch input events.

–Four outputs connecte d to the ac co mpanyin g large SCT

–Two outputs connected to each ADC trigger input

8.22.5 SCT Input processing unit (SCTIPU)

The SCTIPU allows to block or prop agate signa ls to inputs of th e SCT under the control of

an SCT output. Usin g the SCT IPU in th is way, allows signals to be bloc ke d fro m enter ing

the SCT inputs for a certain amount of time, for example while they are known to be

invalid.

In addition, the SCTIPU can generate a common signal from several combined input

sources that can be selected on all SCT inputs. Such a mechanism can be useful to

create an abort sign a l that stops all timers.

8.22.5.1 Features

The SCTIPU pre-processes inputs to the State-Configurable Timers (SCT).

•Four outputs created from a selection of input transitions. Each output can be use d as

abort input to the SCTs or for any other application which requires a collection of

multiple SCT inputs to trigger an identical SCT response.

Product data sheet Rev. 1.1 — 29 April 2015 40 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

•Four registers to indicate which specific input sources caused the abort input to the

SCTs.

•Four additional outputs which can be sampled at certain times and latche d at ot he rs

before being routed to SCT inputs.

•Nine abort inputs. Any combination of the abort inputs can trigger the dedicated abo rt

input of each SCT.

8.23 Quadrature Encoder Interface (QEI)

A quadrature encoder, also known as a 2-channel incremental encoder, converts angular

displacement into two pulse signals. By monitoring both the number of pulses and the

relative phase of the two signals, the user code ca n track the position, direction of rotation,

and velocity. In addition, a third channe l, or ind ex signal, can be u sed to rese t th e position

counter. The quadrature encoder interface decodes the digital pulses from a quadrature

encoder wheel to integrate position over time and determine direction of rotation. In

addition, the QEI can capture the velocity of the encoder wheel.

8.23.1 Features

•Tracks encoder position.

•Increments/decrements depending on direction.

•Programmable for 2 or 4 position counting.

•Velocity capture using built-in timer.

•Velocity compare function with “less than” interrupt.

•Uses 32-bit regis ter s for po sitio n an d ve loc ity.

•Three position- co mpare registers with interrup ts.

•Index counter for revolution counting.

•Index compare regis te r with int er ru p ts.

•Can combine index and position interrupts to produce an interrupt for whole and

partial revolution displacement.

•Digital filter with programmable delays for encoder input signals.

•Can accept decoded signal inputs (clock and direction).

8.24 Analog-to-Digital Converter (ADC)

The ADC supports a resolution of 12 bit and fast conversion rates of up to 2 Msamples/s.

Sequences of analog-to-digit al conversions can be triggere d by multiple sources. Possible

trigger sources ar e internal connections to other on- chip peripherals such as the SCT and

analog comparator outputs, external pins, and the ARM TXEV interrupt.

The ADC supports a variable clocking scheme with clocking synchron ous to the system

clock or independent, asynchronous clocking for high-speed conversions.

The ADC includes a hardware threshold compare function with zero-crossing detection.

The threshold crossing interrupt is connected internally to the SCT inputs for tight timing

control between the ADC and the SCTs.

Product data sheet Rev. 1.1 — 29 April 2015 41 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.24.1 Features

•12-bit successive approximation analog-to-digital converter.

•12-bit conversion rate of 2 MHz.

•Input multiplexing among 12 pins and up to 4 internal sources.

•Internal sources are the temperature sensor voltage, internal reference voltage, core

voltage regulator output, and VDDA/2.

•Two configurable conversion sequences with indepen dent triggers.

•Optional automatic high/low threshold comparison and zero-crossing detection.

•Power-down mode and low-power operating mode.

•Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage

level).

•Burst conversion mode for single or multiple inputs.

•Synchronous or asynchronous oper ation. Asynchronous operation maximizes

flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger

latency and can eliminate uncer tainty and jitter in response to a trigger.

8.25 Digital-to-Analog Converter (DAC)

The DAC support s a resolution of 12 bit s. Conversions can be triggered by an external pin

input or an internal timer.

The DAC includes an optional automatic hardware shut-off feature which forces the DAC

output voltage to zero while a HIGH level on the exte rnal DAC_SHUT OFF pin is detected.

8.25.1 Features

•12-bit digital-to-analog converter.

•Supports DMA.

•Internal timer or pin external trigger for staged, jitter-free DAC

conversion sequencing.

•Automatic hardware shut-off triggered by an external pin.

8.26 Analog comparator (ACMP)

The LPC15xx include four analog comparat ors with seven select able inputs ea ch for each

positive or negative input cha nnel. T wo analog inp uts are common to all fou r comparators.

Internal voltage inputs include a voltage ladder reference with selectable voltage supply

source, the temperature sensor or the internal voltage reference.

The analog inpu ts to the comp arators are fixed-pin functions and must be enabled through

the switch matrix.

The output s of each ana log comp arator are interna lly connected to the ADC trigger inpu t s

and to the SCT inputs, so that the result of a voltage compariso n can trigger a timer

operation or an an alog -to - dig ital conversion .

Product data sheet Rev. 1.1 — 29 April 2015 42 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.26.1 Features

•Seven selectable inputs. Fully configurable on either the positive side or the negative

input channel.

•32-stage voltage ladder internal reference for selectable voltages on each

comparator; configurable on either positive or negative comparator input.

•Voltage ladder source voltage is selectable from an external pin or the 3.3 V analog

voltage supply.

•0.9 V internal band ga p re fe rence voltage selectable as either posit ive or neg ative

input on each comparator.

•Temperature sensor voltage selectable as either positive or negative input on each

comparator.

•Voltage ladder can be separately powered down for applications only re qu iring the

comparator function.

•Individual comp arator outputs can be connected internally to the SCT and ADC trigger

inputs or the external pins.

•Separate interrupt for each comparator.

•Pin filter included on each comparator output.

•Three propagation delay values ar e programmable to optimize between speed and

power consum p tio n.

•Relaxation oscillator circuitry output for a 555 style timer operation using comparator

blocks 0 and 1.

8.27 Temperature sensor

The temperature sensor transducer uses an intrinsic pn-junction diode reference and

outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage

varies inversely with device temperature with an absolute accuracy of better than ±5 C

over the full temperature range (40 C to +105 C). The temperature sensor is only

approximately linear with a slight curvature. The output voltage is measured over different

ranges of temperatures and fit with linear-least-square lines.

After power- up, the tempe rature sensor output must be a llowed to settle to its st able value

before it can be used as an accurate ADC input.

For an accurate measurement of the temperature sensor by the ADC, the ADC must be

configured in single-channel burst mode. The last value of a nine-conversion (or more)

burst provides an accurate result.

8.28 Internal volt age reference

The internal volt age reference is an accurate 0.9 V and is the output of a low voltage band

gap circuit. A typical value at Tamb = 25 C is 0.905 V. The internal voltage reference can

be used in the following applications:

•When the supply voltage VDD is known accurately, the internal voltage reference can

be used to reduce the offset error EO of the ADC code output. The ADC error

correction then increases the accuracy of temper ature sensor voltage output

measurements.

Product data sheet Rev. 1.1 — 29 April 2015 43 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

•When the ADC is accurately calibrated, the internal voltage reference can be used to

measure the power supply voltage. This requires calibration by recording the ADC

code of the internal voltage reference at different power supply levels yielding a

diff erent ADC code va lue for ea ch supply volt age level. In a par ticul ar application, th e

internal voltage reference can be measured and the actual power supply voltage can

be determined from the stored calibration valu es. The calibration values can be stored

in the EEPROM for easy access.

After power-up, the in ternal voltage reference must be allowed to settle to its stable value

before it can be used as an ADC reference voltage input.

For an accurate measurement of the internal voltage reference by the ADC, the ADC must

be configured in single-chan nel burst mode. The last value of a nine-conversion (or mo re)

burst provides an accurate result.

8.29 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each

channel can be programmed with an independent time interval, and each channel

operates independently from the other channels.

8.29.1 Features

•24-bit interrupt timer

•Four channels independen tly counting down from individually set values

•Repeat and one-shot in terrupt modes

8.30 Windowed WatchDog Timer (WWDT)

The watchdog timer r esets the controller if software fails to periodically service it within a

programmable time window.

8.30.1 Features

•Internally resets chip if not periodically reloaded dur ing the programmable time-out

period.

•Optional windowed operation re quires reload to occur between a minimum and

maximum time period, both programmable.

•Optional warning interrupt can be generated at a progr ammable time prior to

watchdog time-out.

•Enabled by soft ware but requires a hardwar e reset or a watchdog reset/interrupt to be

disabled.

•Incorrect feed sequence causes reset or interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 24-bit tim er with internal prescaler.

•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in

multiples of Tcy(WDCLK) 4.

•The WWDT is clocked by the dedicated watchdog oscillator (WDOsc) running at a

fixed frequency.

Product data sheet Rev. 1.1 — 29 April 2015 44 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.31 Repetitive Interrupt (RI) timer

The repetitive interrupt timer provides a free-running 48-bit counter which is compared to

a selectable value, gen erating an interrupt when a match occurs. Any bits of the

timer/compare can be masked such that they do not contribute to the match d etection.

The repetitive interrupt timer can be used to create an interrupt that repeats at

predetermined intervals.

8.31.1 Features

•48-bit counter ru nn in g fro m the main cloc k. Counter can be free-running or can be

reset when an RIT interrupt is generated.

•48-bit compare value.

•48-bit compare mask. An inter rupt is generated when the counter value equals the

compare value, after masking. This allows for combinations not possible with a simple

compare.

8.32 System tick timer

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).

8.33 Real-T ime Clock (RTC)

The RTC resides in a se para te, always-on volt age domain with battery back- up. The R TC

uses an independent 32 kHz oscillator, also located in the always-on voltage domain.

8.33.1 Features

•32-bit, 1 Hz RTC counter and associated match register for alarm generation.

•Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution

with a more that one minute maximum time-out period.

•RTC alarm and high-resolution/wake-up timer time-out each generate independent

interrupt requests. Either time-out can wake up the part from any of the low power

modes, including Deep power-down.

Product data sheet Rev. 1.1 — 29 April 2015 45 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.34 Clock generation

Fig 14. Clock generation

system oscillator

watchdog oscillator

IRC system oscillator

IRC

USB PLL

USBPLLCLKSEL

(USB PLL clock select)

SYSTEM CLOCK

DIVIDER

SYSAHBCLKCTRLn

(AHB clock enable)

CPU, system control,

PMU

memories,

peripheral clocks

SYSTICK PERIPHERAL

CLOCK DIVIDER

ARM core

SYSTICK

IOCONCLKDIV

CLOCK DIVIDER

IOCON digital

glitch filter

ARM TRACE CLOCK

CLOCK DIVIDER ARM trace

USART PERIPHERAL

CLOCK DIVIDER

FRACTIONAL RATE

GENERATOR USART[n:0]

WWDT

CLKOUTSELA

(CLKOUT clock select A)

USB 48 MHz CLOCK

DIVIDER USB

watchdog oscillator

IRC

system oscillator

USBCLKSEL

(USB clock select)

CLKOUT PIN CLOCK

DIVIDER CLKOUT pin

system clock

SYSTEM PLL

IRC

system oscillator

watchdog oscillator

MAINCLKSELB

(main clock select B)

MAINCLKSELA

(main clock select A)

SYSPLLCLKSEL

(system PLL clock select)

main clock

IRC

system oscillator

RTC oscillator

system oscillator

IRC

SCT PLL

SCTPLLCLKSEL

(SCT PLL clock select)

SCT

ASYNC ADC CLOCK

DIVIDER ADC

ADCASYNCCLKSEL

(clock select)

32 kHz

RTC oscillator 32 kHz

CLKOUTSELB

(CLKOUT clock select B)

aaa-010875

Product data sheet Rev. 1.1 — 29 April 2015 46 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.35 Power domains

The LPC15xx provide two ind ependent power doma ins that allow the bulk of the device to

have power removed while maintaining operation of the RTC and the backup Registers.

The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of

power to operate, which can be supplied by an external battery. The device core power

(VDD) is used to operate the RTC whenever VDD is present. Therefore, there is no power

drain from the RTC battery when VDD is and VDD >= VBAT + 0.3 V.

8.36 Integrated oscillators

The LPC15xx include the following independent oscillators: the system osc illator, the

Internal RC oscillator (IRC), the watchdog oscillator, and the 32 kHz RTC oscillator. Each

oscillator can be used for multiple purposes.

Following reset, the LPC15xx operates from the internal RC oscillator until software

switches to a different clock source. The IRC allows the system to operate without any

external crystal and the bootloader code to operate at a known frequency.

See Figure 14 for an overview of the LPC15xx clock generation.

Fig 15. Power distributio n

REAL-TIME CLOCK

BACKUP REGISTERS

WAKE-UP

CONTROL

REGULATOR

32 kHz

OSCILLATOR

ALWAYS-ON/RTC POWER DOMAIN

MAIN POWER DOMAIN

RTCXIN

VBAT

VDD

RTCXOUT

VDD

VSS

to memories,

peripherals,

oscillators,

PLLs

to core

to I/O pads

ADC TEMP SENSE

ACMP

DAC

INTERNAL

VOLTAGE REF

ADC POWER DOMAIN

VDDA

VSSA

LPC15xx

ULTRA LOW-POWER

REGULATOR

WAKEUP

aaa-010876

Product data sheet Rev. 1.1 — 29 April 2015 47 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.36.1 Internal RC oscillator

The IRC can be used as the clock that drives the system PLL and then the CPU. In

addition, the IRC can be selected as input to various clock dividers and as the clo ck

source for the USB PLL and the SCT PLL (see Figure 14). The nominal IRC frequency is

12 MHz.

Upon power-up, any chip reset, or wake-up from Deep power-down mod e, the LPC15xx

use the IRC as the clock source. Software can later switch to one of the othe r available

clock sources.

8.36.2 System oscillator

The system oscillator can be used as a stable and accurate clock source for the CPU, with

or without using the PLL. For USB applications, use the system oscillator to provide the

clock source to USB PLL.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL.

The system oscillator has a wake-up time of approximately 500 s.

8.36.3 Watchdog oscillator

The low-power watchdog oscillator can be used as a clock source that directly drives the

CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency

is fixed at 503 kHz. The frequency spread over processing and temperature is 40 %.

8.36.4 RTC oscillator

The low-power RTC oscillator provides a 1 Hz clock and a 1 kHz clock to the RTC and a

32 kHz clock output that can be used to obt ain the main clock (see Figure 14).The 32 kHz

oscillator output can be observed on the CLKOUT pin to allow trimming the RTC oscillator

without interference from a probe.

8.37 System PLL, USB PLL, and SCT PLL

The LPC15xx contain a three identical PLLs for generating the system clock, the 48 MHz

USB clock, and an asynchronous clock for the ADCs and SCTs. The system PLL is used

to create the main clock. The SCT and USB PLLs create dedicated clocks for the

asynchronous ADC, the asynchronous SCT clock inpu t, an d th e USB.

Remark: The USB PLL is available on parts LPC1549/48/47 only.

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz. To support this frequency range, an additio nal divider keeps the

CCO within its frequency range while the PLL is providing the desired output frequency.

The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The

PLL output frequency must be lower than 100 MHz. Since the minimum output divider

value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off

and bypassed following a chip reset. Software can enable the PLL later. The program

must configure and activate the PLL, wait for the PLL to lock, and then connect to th e PLL

as a clock source. The PLL settling time is 100 s.

Product data sheet Rev. 1.1 — 29 April 2015 48 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.38 Clock output

The LPC15xx feature a clock output function that routes the internal oscillator outputs, the

PLL outputs, or the main clock an outpu t pin where they can be observed directly.

8.39 Wake-up process

The LPC15xx begin operation by using the 12 MHz IRC oscillator as the clock source at

power-up and when awakened from Deep power-down mode. This mechanism allows

chip operation to resume quickly. If the application uses the system oscillator or the PLL,

software must enable these components and wait for them to stabilize. Only then can the

system use the PLL and system oscillator as a clock source.

8.40 Power control

The LPC15xx support various power control features. There are four special modes of

processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode. The CPU clock rate can also be controlled as needed by

changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider

value. This power control mechanism allows a trade-of f of power versus processing speed

based on application require ments. In addition, a register is provided for shutting down the

clocks to individual on-chip peripherals. This register allows fine-tuning of power

consumption by eliminating all dynamic power use in any pe ripherals that are not required

for the application. Selected peripherals have their own clock divider which provides

additional power control.

8.40.1 Power profiles

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile. The power configuration routine configu res the

LPC15xx for one of the following power modes:

•Default mode corresponding to power configuration after reset.

•CPU performance mode corresponding to optimized processing capability.

•Efficie ncy mode corresponding to optimi zed balance of current consumption and CPU

performance.

•Low-current mode corresponding to lowest power consumption.

In addition, the power profile include s routines to select the optimal PLL settings for a

given system clock and PLL input clock and to easily set the configuration options for

Deep-sleep and power-down modes.

Remark: When using the USB, configure the LPC15xx in Default mode.

8.40.2 Sleep mode

When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep

mode does not need an y special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and can generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, by memory systems and related controllers, and by

internal buses.

Product data sheet Rev. 1.1 — 29 April 2015 49 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.40.3 Deep-sleep mode

In Deep-sleep mode, the LPC15xx is in Slee p-mode and all peripheral clocks and all clock

sources are off except for the IRC. The IRC output is disabled unless the IRC is selected

as input to the watchdog tim er. In addition all analog blocks are shu t down and the flash is

in stand-by mode. In Deep-sleep mode, the application can keep the watchdog oscillator

and the BOD circuit running for self-timed wake-up and BOD protection.

The LPC15xx can wake up from Deep-sleep mode via reset, selected GPIO pins, a

watchdog timer interrupt, an interrupt generating USB port activity, an RTC interrupt, or

any interrupts that the USART, SPI, or I2C interfaces can create in Deep-sleep mode. The

USART wake-up requires the 32 kHz mode, the synchronous mode, or the CTS interrupt

to be set up.

Deep-sleep mode saves power and allows for short wake-up times.

8.40.4 Power-down mode

In Power-down mode, the LPC15xx is in Sleep-mode and all peripheral clocks and all

clock sources are off except for watchdog oscillator if selected. In addition all analog

blocks and the flash are shut down. In Power-down mode, the application can keep the

BOD circuit running for BOD protection.

The LPC15xx can wake up from Power-down mod e via reset, selected GPIO pins, a

watchdog timer interrupt, an interrupt generating USB port activity, an RTC interrupt, or

any interrupts that the USART, SPI, or I2C interfaces can create in Power-down mode.

The USART wake-up requires the 32 kHz mode, the synchronous mode, or the CTS

interrupt to be set up.

Power-down mode reduces power consump tion compared to Deep-sleep mode at the

expense of longer wa ke-up times.

8.40.5 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP

pin and the always-on RTC power-domain. The LPC15xx can wake up from De ep

power-down mode via the WAKEUP pin or a wake-up signal generated by the RTC

interrupt.

The LPC15xx can be blocked from entering Deep power-down mode by setting a lock bit

in the PMU block. Blocking the Deep power-down mode enables the application to keep

the watchdog timer or the BOD running at all times.

If the WAKEUP pin is used in the application, an external pull-up resistor is required on

the WAKEUP pin to hold it HIGH while the part is in deep power-down mode. Pulling the

WAKEUP pin LOW wakes up the part from deep power-down mode. In addition, pull the

RESET pin HIGH to prevent it from floating while in Deep power-down mode.

Product data sheet Rev. 1.1 — 29 April 2015 50 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.41 System control

8.41.1 Reset

Reset has four sources on the LPC15xx: the RESET pin, the Watchdog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip re set by a ny source, on ce the opera tin g voltage attains

a usable level, starts the IRC and initializes the flash controller.

When the internal Reset is removed, th e processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

In Deep power-down mode, an external pull-up resistor is required on the RESET pin.

The RESET pin is operational in acti ve, sleep, deep-sleep, and power-down modes if the

RESET function is selected through the switch matri x for pin PIO0_21 (th is is the default).

A LOW-going pulse as short as 50 ns executes the reset and thereby wakes up the p art to

its active state. The RESET pin is not functional in Deep power-down mode and must be

pulled HIGH externally while the part is in Deep power-down mode.

8.41.2 Brownout detection

The LPC15xx includes brown-out detection (BOD) with two levels for monitoring the

voltage on the VDD pin. If this voltage falls below one of two selected levels, the BOD

asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the

Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can

monitor the signal by reading a d edicated status register. Two threshold levels can be

selected to cause a forced reset of the chip.

8.41.3 Code security (Code Read Protection - CRP)

CRP provides different levels of security in the system so that access to the on-chip flash

and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be

restricted. Programming a specific pattern into a dedicated flash location invokes CRP.

IAP commands are not affected by the CRP.

Fig 16. RESET pin configuration

UHVHW

DDD

5SX

(6'

QV5&

*/,7&+),/7(5 3,1

Product data sheet Rev. 1.1 — 29 April 2015 51 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

In addition, ISP entry the external pins can be disable d without enablin g CRP. For det ails,

see the LPC15xx user man u al .

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is requ ired and flash field upda tes are needed b ut all sectors cannot

be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected, fully disables any access to the chip

via the SWD pins and the ISP. This mode effectively disables ISP override using ISP

pin as well. If necessary, the application must provide a flash update mechanism

using IAP calls or using a call to th e reinvoke ISP command to enable flash upda te via

the USART.

In addition to the three CRP levels, sampling of th e ISP pins for valid user code can be

disabled. For details, see the LPC15xx user manual.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

Product data sheet Rev. 1.1 — 29 April 2015 52 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.42 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M3. Serial wire debug functions are

supported in addition to a standard JTAG boundary scan. The ARM Cortex-M3 is

configured to support up to four breakpoints and two watch points.

The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM

SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC15xx

is in reset.

To perform boundary scan testing, follow these steps:

1. Erase any user code residing in flash.

2. Power up the part with the RESET pin pulled HIGH externally.

3. Wait for at least 250 s.

4. Pull the RESET pin LOW externally.

5. Perform boundary scan operations.

6. Once the b oundary scan operations are comp leted, assert the TRST pin to enable the

SWD debug mode, and release the RESET pin (pull HIGH).

Remark: The JTAG interface cannot be used for debug purposes.

9. Limiting values

Table 9. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD supply voltage (3.3 V) [2] 0.5 VDDA V

VDDA analog supply voltage 0.5 +4.6 V

Vref reference voltage on pin VREFP_DAC_VDDCMP 0.5 VDDA V

on pin VREFP_ADC 0.5 VDDA V

VBAT battery supply voltage 0.5 +4.6 V

VIinput voltage 5 V tolerant I/O pins; only valid

when the VDD(IO) supply voltage

is presen t

[3][4] 0.5 +5.5 V

on I2C open-drain pins

PIO0_22, PIO0_23 [5] 0.5 +5.5 V

3 V tolerant I/O pin without

over-voltage protection. Applies

to PIO0_12.

[6] 0.5 VDDA V

USB_DM, USB_DP pins 0.5 VDD + 0.5 V

VIA analog input voltage [7][8]

[9] 0.5 +4.6 V

Vi(xtal) crystal input voltage [2] 0.5 +2.5 V

Vi(rtcx) 32 kHz oscillator in put voltage [2] 0.5 +4.6 V

IDD supply current per supply pin - 100 mA

ISS ground current per ground pin - 100 mA

Product data sheet Rev. 1.1 — 29 April 2015 53 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Maximum/minimum voltage above the maximum operating voltage (see Table 11) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] Applies to all 5 V tolerant I/O pins except true open-drain pins PIO0_22 and PIO0_23 and except the 3 V tolerant pin PIO0_12.

[4] Including the voltage on outputs in 3-state mode.

[5] VDD(IO) present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD(IO) is powered down.

[6] Applies to 3 V tolerant pin PIO0_12.

[7] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated

exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the

ADC inputs for a long time affects the reliability of the device and reduces its lifetime.

[8] If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below

VDD without affecting the hysteresis range of the comparator function.

[9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[10] Dependent on package type.

[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

10. Thermal characteristics

The average chip junction temperature, Tj (C), can be calculated us ing the following

equation:

(1)

•Tamb = ambient temperature (C),

•Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)

•PD = sum of internal and I/O power dissipation

Ilatch I/O latch-up curre n t (0.5VDD) < VI < (1.5VDD);

Tj < 125 C- 100 mA

Tstg storage temperature [10] 65 +150 C

Tj(max) maximu m ju nction temper at ure - +150 C

Ptot(pack) total power dissipation (per

package) based on package heat

transfer, not device power

consumption

-1.5W

Vesd electrostatic discharge voltage human body model; all pins [11] -5kV

Table 9. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

TjTamb PDRth j a–

+=

Product data sheet Rev. 1.1 — 29 April 2015 54 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Table 10. Thermal resistance value (C/W): ±15 %

Symbol Parameter Conditions Typ Unit

LQFP48

ja thermal resistance

junction-to-ambient JEDEC (4.5 in  4 in)

0 m/s 64 C/W

1 m/s 55 C/W

2.5 m/s 50 C/W

8-layer (4.5 in  3 in)

0 m/s 96 C/W

1 m/s 76 C/W

2.5 m/s 67 C/W

jc thermal resistance

junction-to-case 13 C/W

jb thermal resistance

junction-to-board 16 C/W

LQFP64

ja thermal resistance

junction-to-ambient JEDEC (4.5 in  4 in)

0 m/s 51 C/W

1 m/s 45 C/W

2.5 m/s 41 C/W

8-layer (4.5 in  3 in)

0 m/s 75 C/W

1 m/s 60 C/W

2.5 m/s 54 C/W

jc thermal resistance

junction-to-case 13 C/W

jb thermal resistance

junction-to-board 17 C/W

LQFP100

ja thermal resistance

junction-to-ambient JEDEC (4.5 in  4 in)

0 m/s 42 C/W

1 m/s 37 C/W

2.5 m/s 34 C/W

8-layer (4.5 in  3 in)

0 m/s 59 C/W

1 m/s 48 C/W

2.5 m/s 44 C/W

jc thermal resistance

junction-to-case 12 C/W

jb thermal resistance

junction-to-board 17 C/W

Product data sheet Rev. 1.1 — 29 April 2015 55 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of

the I/O pins is of ten small and ma ny times can b e negligible. However it can be significant

in some applications.

11. Static characteristics

Table 11. Static chara cteristics

Tamb =





C to +105



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD supply voltage (core

and external rail) [2] 2.4 3.3 VDDA V

VDDA analog supply voltage 2.4 3.3 3.6 V

Vref reference voltage on pin VREFP_DAC_VDDCMP 2.4 - VDDA V

on pin VREFP_ADC - - VDDA V

VBAT battery supply voltage 2.4 3.3 3.6 V

IDD supply current Active mode; code

while(1){}

executed from flash;

system clock = 12 MHz; default

mode; VDD = 3.3 V [3][4][5]

[7][8] -4.3-mA

system clock = 12 MHz;

low-current mode; VDD = 3.3 V [3][4][5]

[7][8] -2.7-mA

system clock = 72 MHz; default

mode; VDD = 3.3 V [3][4][7]

[8][10] -19.3-mA

system clock = 72 MHz;

low-current mode; VDD = 3.3 V [3][4][7]

[8][10] -18 -mA

Sleep mode;

system clock = 12 MHz; default

mode; VDD = 3.3 V [3][4][5]

[7][8] -2.1-mA

system clock = 12 MHz;

low-current mode; VDD = 3.3 V [3][4][5]

[7][8] -1.5-mA

system clock = 72 MHz; default

mode; VDD = 3.3 V [3][4][10]

[7][8] -8.0-mA

system clock = 72 MHz;

low-current mode; VDD = 3.3 V [3][4][10]

[7][8] -7.3-mA

IDD supply current Deep-sleep mode;

VDD = 3.3 V;

Tamb =25C

[3][4][11] -

310 380 A

Tamb =105C - - 620 A

IDD supply current Power-down mode;

VDD = 3.3 V

Tamb =25C

[3][4][11] -

3.8 15 A

Tamb =105C - - 163 A

Product data sheet Rev. 1.1 — 29 April 2015 56 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

IDD supply current Deep power-down mode; VDD =

3.3 V; VBAT = 0 or VBAT = 3.0 V

RTC oscillator running

Tamb =25C

[3][12][13]

-1.11.3

[14] A

Tamb =105C--15A

RTC oscillator input grounded;

Tamb =25C[3][12] -560-nA

IBAT battery supply current Deep power-down mode; VDD =

VDDA = 3.3 V; VBAT = 3.0 V [13] 0-nA

VDD and VDDA tied to ground;

VBAT = 3.0 V [13] 1-A

Standard port pins configured as digital pins, RESET; see Figure 17

IIL LOW-level input current VI= 0 V; on-chip pull-up resistor

disabled -0.510

[14] nA

IIH HIGH-level input

current VI=V

DD; on-chip pull-down

resistor disabled -0.510

[14] nA

IOZ OFF-state output

current VO=0V; V

O=V

DD; on-chip

pull-up/down resistors disabled -0.510

[14] nA

VIinput voltage VDD  2.4 V; 5 V tolerant pins

except PIO0_12 [16]

[18] 0- 5V

VDD  2.4 V; on 3 V tolerant pin

PIO0_12 0- V

DDA

VDD = 0 V 0 - 3.6 V

VOoutput voltage output active 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage 2.4 V <= VDD < 3.0 V 0.30 - - V

3.0 V <= VDD <= 3.6 V 0.35 - - V

VOH HIGH-level output

voltage IOH =4 mA V

DD  0.4 - - V

VOL LOW-level output

voltage IOL =4 mA - - 0.4 V

IOH HIGH-level output

current VOH =V

DD 0.4 V 4 - - mA

IOL LOW-level output

current VOL =0.4V 4 - - mA

IOHS HIGH-level short-circuit

output current VOH =0V [19] -- -45mA

IOLS LOW-level short-circuit

output current VOL =V

DD [19] -- 50mA

Ipd pull-down current VI= 5 V 10 50 150 A

Ipu pull-up current VI=0V; 10 50 85 A

VDD <V

I<5V 0 0 0 A

Table 11. Static chara cteristics …continued

Tamb =





C to +105



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 1.1 — 29 April 2015 57 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

High-drive output pin configured as digital pin (PIO0_24); see Figure 17

IIL LOW-level input current VI= 0 V; on-chip pull-up resistor

disabled -0.510

[14] nA

IIH HIGH-level input

current VI=V

DD; on-chip pull-down

resistor disabled -0.510

[14] nA

IOZ OFF-state output

current VO=0V; V

O=V

DD; on-chip

pull-up/down resistors disabled -0.510

[14] nA

VIinput voltage VDD  2.4 V [16]

[18] 0- 5.0V

VDD = 0 V 0 - 3.6 V

VOoutput voltage output active 0 - VDD V

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage 2.4 V <= VDD < 3.0 V 0.30 - - V

3.0 V <= VDD <= 3.6 V 0.35 - - V

VOH HIGH-level output

voltage IOH = 20 mA; 2.7 V <= V DD <

3.6 V VDD  0.4 - - V

IOH = 12 mA; 2.4 V <= VDD <

2.7 V VDD  0.4 - - V

VOL LOW-level output

voltage IOL =4 mA - - 0.4 V

IOH HIGH-level output

current VOH =V

DD 0.4 V; 2.7 V <= VDD

< 3.6 V 20 - - mA

VOH =V

DD 0.4 V; 2.4 V <= VDD

< 2.7 V 12 - - mA

IOL LOW-level output

current VOL = 0.4 V 4 - - mA

IOLS LOW-level short-circuit

output current VOL =V

DD [19] -- 50mA

Ipd pull-down current VI=5V [20] 10 50 150 A

Ipu pull-up current VI=0V [20] 10 50 85 A

VDD <V

I<5V 0 0 0 A

I2C-bus pins (PIO0_22 and PIO0_23); see Figure 17

VIH HIGH-level input

voltage 0.7VDD --V

VIL LOW-level input voltage - - 0.3VDD V

Vhys hysteresis voltage - 0.05VDD -V

IOL LOW-level output

current VOL =0.4V; I

2C-bus pins

configured as standard mode pins 3.5 - - mA

Table 11. Static chara cteristics …continued

Tamb =





C to +105



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 1.1 — 29 April 2015 58 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.

[2] For USB operation: 3.0 VVDD  3.6 V.

[3] Tamb =25C.

[4] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

IOL LOW-level output

current VOL =0.4V; I

2C-bus pins

configured as Fast-mode Plus

pins; 2.7 V <= VDD < 3.6 V

20 - - mA

VOL =0.4V; I

2C-bus pins

configured as Fast-mode Plus

pins; 2.4 V <= VDD < 2.7 V

16 - - mA

ILI input leakage current VI=V

DD [21] -2 4A

VI=5V - 10 22 A

USB_DM and USB_DP pins

VIinput voltage [2] 0- V

DD V

VIH HIGH-level input

voltage 1.8 - - V

VIL LOW-level input voltage - - 1.0 V

Vhys hysteresis voltage 0 .32 - - V

Zout output impedance 28 - 44 

VOH HIGH-level output

voltage 2.9 - - V

VOL LOW-level output

voltage -- 0.18V

IOH HIGH-level output

current VOH =V

DD 0.3 V [22] 4.8 - - mA

IOL LOW-level output

current VOL = 0.3 V [22] 5.0 - - mA

IOLS LOW-level short-circuit

output current drive LOW; pad connected to

ground - - 125 mA

IOHS HIGH-level short-circuit

output current drive HIGH; pad connected to

ground - - 125 mA

Oscillator pins

Vi(xtal) crystal input voltage on pin XTALIN 0.5 1.8 1.95 V

Vo(xtal) crystal output voltage on pin XTALOUT 0.5 1.8 1.95 V

Vi(rtcx) 32 kHz oscillator input

voltage on pin RTCXIN [23] 0.5 - 3.6 V

Vo(rtcx) 32 kHz oscillator output

voltage on pin RTCXOUT [23] 0.5 - 3.6 V

Pin capacitance

Cio input/output

capacitance pi ns with analog and digital

functions [24] -- 7.1pF

I2C-bus pins (PIO0_22 and

PIO0_23) [24] - - 2.5 pF

pins with digital functions only [24] -- 2.8pF

Table 11. Static chara cteristics …continued

Tamb =





C to +105



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 1.1 — 29 April 2015 59 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[5] IRC enabled; system oscillator disabled; system PLL disabled.

[6] System oscillator enabled; IRC disabled; system PLL disabled.

[7] BOD disabled.

[8] All peripherals disabled in the SYSAHBCLKCTRL0/1 registers. Peripheral clocks to USART, CLKOUT, and IOCON disabled in system

configuration block.

[9] IRC enabled; system oscillator disabled; system PLL enabled.

[10] IRC disabled; system oscillator enabled; system PLL enabled.

[11] All oscillators and analog blocks turned off: Use API power_mode_configure() with mode parameter set to DEEP_SLEEP or

POWER_DOWN and peripheral parameter set to 0xFF.

[12] WAKEUP pin pulled HIGH externally.

[13] RTC running or not running.

[14] Characterized on samples. Not tested in production.

[15] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[16] Including voltage on outputs in tri-state mode.

[17] VDD supply voltage must be present.

[18] Tri-state outputs go into tri-state mode in Deep power-down mode.

[19] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[20] Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 17.

[21] To VSS.

[22] The parameter values specified are simulated and absolute values.

[23] The input voltage of the RTC oscillator is limited as follows: Vi(rtcx), Vo(rtcx) < max(VBAT, VDD).

[24] Including bonding pad capacitance.

Fig 17. Pin input/output current measurement

aaa-010819

pin PIO0_n

Product data sheet Rev. 1.1 — 29 April 2015 60 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

11.1 Power consumption

Power measurements in Active, Sleep, Deep-sleep, and Power-down modes were

performed under the following conditions:

•Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.

•Configure GPIO pins as outputs using the GPIO DIR register.

•Write 1 to the GPIO CLR register to drive the outputs LOW.

Conditions: Tamb = 25 C; active mode entered executing code

while(1){}

from flash; all

peripherals disabled in the SYSAHBCLKCTRL0/1 registers; all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz - 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz to 72 MHz: IRC enabled; PLL enabled.

Fig 18. Active mode: Typical supp ly current IDD versus supply voltage VDD

aaa-011384

2.4 2.6 2.8 3 3.2 3.4 3.6

VDD (V)

IDDDD

IDD

(mA)(mA)(mA)

12 MHz

24 MHz

48 MHz

60 MHz

72 MHz

36 MHz

6 MHz

1 MHz

Product data sheet Rev. 1.1 — 29 April 2015 61 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Conditions: VDD = 3.3 V; active mode entered executing code

while(1){}

from flash; all

peripherals disabled in the SYSAHBCLKCTRL0/1 registers; all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz - 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz to 72 MHz: IRC enabled; PLL enabled.

Fig 19. Active mode: Typical supp ly current IDD versus temperature

Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL0/1 registers; all peripheral clocks disabled; internal pull-up resistors disabled;

BOD disabled; low-current mode.

1 MHz - 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz to 72 MHz: IRC enabled; PLL enabled.

Fig 20. Sleep mode: Typical supply current IDD versus temperature for different system

clock frequencies

aaa-011385

-40 -10 20 50 80 110

temperature (°C)

(mA)

12 MHz

24 MHz

48 MHz

60 MHz

72 MHz

36 MHz

6 MHz

1 MHz

aaa-011386

-40 -10 20 50 80 110

temperature (°C)

(mA)

(mA) 72 MHz

48 MHz

36 MHz

24 MHz

12 MHz

6 MHz

1 MHz

60 MHz

Product data sheet Rev. 1.1 — 29 April 2015 62 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Conditions: BOD disabled; all oscillators and analog blocks disabled. Use API

power_mode_configure() with mode parameter set to DEEP_SLEEP and peripheral p arameter set

to 0xFF.

Fig 21. Deep-sleep mode: Typical supply current IDD versus temperature for different

supply vo ltages VDD

Conditions: BOD disabled; all oscillators and analog blocks disabled; VDD = 2.4 V to 3.6 V. Use API

power_mode_configure() with mode parameter set to POWER_DOWN and peripheral parameter

set to 0xFF.

Fig 22. Power-dow n mode: Typical su pply current IDD versus temperature for different

supply vo ltages VDD

aaa-011234

-40 -10 20 50 80 110

280

300

320

340

360

380

400

temperature (°C)

IDDDD

IDD

(μA)(μA)(μA)

3.6 V

3.3 V

3.0 V

2.7 V

2.4 V

aaa-011235

-40 -10 20 50 80 110

temperature (°C)

IDDDD

IDD

(μA)(μA)(μA)

Product data sheet Rev. 1.1 — 29 April 2015 63 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

VBAT = 0 V.

Fig 23. Deep power-down mode: Typical supply current IDD versus temperature for

different supply voltages VDD

VBAT = 3.3 V; VDD floating.

Fig 24. Deep power-down mode: Typical battery supply current IBAT versus temperature

aaa-011236

-40 -10 20 50 80 110

temperature (°C)

IDDDD

IDD

(μA)(μA)(μA)

2.4 V

3.3 V3.6 V

aaa-011333

-40 -10 20 50 80 110

temperature (°C)

IBATBAT

IBAT

(μA)(μA)(μA)

Product data sheet Rev. 1.1 — 29 April 2015 64 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

11.2 CoreMark data

Conditions: VDD = 3.3 V; active mode; all peripherals except one UART and the SCT disabled in

the SYSAHBCLKCTRL0/1 register; internal pull-up resistors enabled; BOD disabled. Measured

with Keil uVision v.4.73.0.0, C compiler v.5.03.0.76.

Fig 25. CoreMark score

Conditions: VDD = 3.3 V; T amb = 25 C; active mode; all peripherals except one UART and the SCT

disabled in the SYSAHBCLKCTRL0/1 registers; system clock derived from the IRC; system

oscillator disabled; internal pull-up resisto rs enabled; BOD disabled. Measured with Keil uVision

v.4.73.0.0, C compiler v.5.03.0.76.

Fig 26. Active mode: CoreMark power con sumption IDD

aaa-011746

012 24 36 48 60 72

2.35

2.4

2.45

2.5

2.55

2.6

2.65

system clock frequency (MHz)

CM score

efficiency

cpu

default/low current

aaa-011747

012 24 36 48 60 72

system clock frequency (MHz)

IDD

(mA)

default

cpu

efficiency

low-current

Product data sheet Rev. 1.1 — 29 April 2015 65 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

11.3 Peripheral power consumption

The supply current p er peripheral is measured as the differ ence in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code accessing the peripheral is executed. Measured on a typical

sample at Tamb =25 C. Unless noted otherwise, the system oscillator and PLL are

running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz and 72 MHz.

Table 12. Power consumption for individual analog and digital blocks

Peripheral Typical supply current in mA Notes

n/a 12 MHz 72 MHz

IRC 0.008 - - System oscillator run ning; PLL off; independent

of main clock frequency.

System oscillator at 12 MHz 0.220 - - IRC running; PLL off; independent of main clock

frequency.

Watchdog oscillator 0.002 - - System oscilla tor running; PLL off; independent

of main clock frequency.

BOD 0.045 - - Independent of main clock frequency.

Main PLL - 0.085 - -

USB PLL 0.100

SCT PLL 0.110

CLKOUT - 0.005 0.01 Main clock divided by 4 in the CLKOUTDIV

ROM - 0.015 0.02 -

GPIO + pin interrupt/pattern

match - 0.55 0.60 GPIO pins configured as outputs and set to

LOW. Direction and pin state are maintained if

the GPIO is disabled in the SYSAHBCLKCFG

SWM - 0.04 0.29 -

INPUT MUX 0.05 0.30

IOCON - 0.06 0.40 -

SCTimer0/PWM - 0.18 1.10 -

SCTimer1/PWM - 0.19 1.10 -

SCTimer2/PWM - 0.13 0.70 -

SCTimer3/PWM - 0.16 0.90 -

SCT IPU 0.02 0.1

RTC - 0.01 0.05 -

MRT - 0.03 0.10 -

WWDT - 0.01 0.10 Main clock selected as clock source for the

WDT.

RIT 0.07 0.20

QEI 0.12 0.80

I2C0 - 0.02 0.12 -

SPI0 - 0.03 0.3 -

SPI1 - 0.01 0.28 -

Product data sheet Rev. 1.1 — 29 April 2015 66 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

11.4 Electrical pin characteristics

USART0 - 0.02 0.15 -

USART1 - 0.02 0.16 -

USART2 - 0.02 0.15 -

C_CAN - 0.50 3.00

USB - 0.10 0.50

Comparator ACMP0/1/2/3 - 0.01 0.03 -

ADC0 - 0.05 0.33 -

ADC1 - 0.04 0.33 -

temperature sensor - 0.03 0.03

internal voltage reference/band

gap - 0.03 0.04

DAC - 0.02 0.09 -

DMA - 0.36 1.5

CRC - 0.01 0.08 -

Table 12. Power consumption for individual analog and digital blocks …continued

Peripheral Typical supply current in mA Notes

n/a 12 MHz 72 MHz

Conditions: VDD = 3.3 V; on pin PIO0_24.

Fig 27. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level

output current IOH

aaa-011257

010 20 30 40 50

2.7

2.8

2.9

3.1

3.2

3.3

(mA)

(V)

-40 °C

25 °C

90 °C

105 °C

Product data sheet Rev. 1.1 — 29 April 2015 67 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Conditions: VDD = 3.3 V; on pins PIO0_22 and PIO0_23.

Fig 28. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus

LOW-level output voltage VOL

Conditions: VDD = 3.3 V; standard port pins and high-drive pin PIO0_24.

Fig 29. Typical LOW-l evel output current IOL versus LOW-level output voltage VOL

aaa-011258

0 0.1 0.2 0.3 0.4 0.5

VOL (V)

IOL

(mA)

-40 °C

25 °C

90 °C

105 °C

aaa-011263

0 0.1 0.2 0.3 0.4 0.5

IOL (mA)

VOL

(V)

-40 °C

25 °C

90 °C

105 °C

Product data sheet Rev. 1.1 — 29 April 2015 68 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Conditions: VDD = 3.3 V; standard port pins.

Fig 30. Typical HIGH-level output voltage VOH versus HIGH-level output source current

IOH

Conditions: VDD = 3.3 V; standard port pins.

Fig 31. Typical pull-up current Ipu versus input volt age VI

aaa-011276

036912

2.7

2.9

3.1

3.3

VOH (V)

IOH

(mA)

-40 °C

25 °C

90 °C

105 °C

aaa-011277

0 1 2 3 4 5

-80

-60

-40

-20

VI (V)

Ipu

(μA)

105 °C

90 °C

25 °C

-40 °C

Product data sheet Rev. 1.1 — 29 April 2015 69 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Conditions: VDD = 3.3 V; standard port pins.

Fig 32. Typical pull-down current Ipd versus input voltage VI

aaa-011278

0 1 2 3 4 5

VI (V)

Ipu

(μA)

-40 °C

25 °C

90 °C

105 °C

Product data sheet Rev. 1.1 — 29 April 2015 70 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

12. Dynamic characteristics

12.1 Flash/EEPROM memory

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes to the flash. Tamb <= +85 C. Flash programming with

IAP calls (see LPC15xx user manual).

12.2 External clock for the oscillator in slave mode

Remark: The input voltage on the XTALIN and XTALOUT pins must be  1.95 V (see

Table 11). For connecting the oscillator to the XTAL pins, also see Section 14.3.

[1] Parameters are valid over operating temperature range unless otherwise specified.

Table 13. Flash characteristics

Tamb =





C to +105



C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as

specified below.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance [1] 10000 100000 - cycles

tret retention time powered 10 20 - years

not powered 20 40 - years

ter erase time page or multiple

consecutive pages,

sector or multiple

consecutive

sectors

95 100 105 ms

tprog programming

time [2] 0.95 1 1.05 ms

Table 14. EEPROM characteristics

Tamb =





Cto+85



C; VDD = 2.7 V to 3.6 V. Based on JEDEC NVM qualificati on. Fai lure rate <

10 ppm for parts as specified below.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance 100000 1000000 - cycles

tret retention time p owered 100 200 - years

not powered 150 300 - years

tprog programming

time 64 bytes - 2.9 - ms

Table 15. Dynamic characteristic: external clock (XTALIN input)

Tamb =





C to +105



C; VDD over specified ranges.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc oscillator frequency 1 - 25 MHz

Tcy(clk) clock cycle time 40 - 1000 ns

tCHCX clock HIGH time Tcy(clk) 0.4 - - ns

tCLCX clock LOW time Tcy(clk) 0.4 - - ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Product data sheet Rev. 1.1 — 29 April 2015 71 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply

voltages.

12.3 Internal oscillators

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply

voltages.

Fig 33. External clock timing (with an amplitu de of at least Vi(RMS) = 200 mV)

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Table 16. Dynamic ch ar acteristics: IRC

Tamb =





C to +105



C; 2.7 V



VDD



3.6 V[1].

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc(RC) internal RC

oscillator frequency 25 C  Tamb  +85 C 1 2 - 1% 12 12 + 1 % MHz

40 C  Tamb < 25 C 12 - 2% 12 12 + 1 % MHz

85 C < Tamb  105 C 12 - 1.5 % 12 12 + 1.5 % MHz

Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for

2.7 V  VDD  3.6 V and Tamb =25 C to +85 C. Variations between parts may cause the IRC to

fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V.

Fig 34. Typical Internal RC oscillator frequency versus temperature

aaa-011233

-40 -10 20 50 80 110

11.85

11.9

11.95

12.05

12.1

12.15

temperature (°C)

fosc(RC)osc(RC)

fosc(RC)

(MHz)(MHz)(MHz) 3.6 V

3.3 V

3.0 V

2.7 V

Product data sheet Rev. 1.1 — 29 April 2015 72 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %.

12.4 I/O pins

[1] Applies to standard port pins and RESET pin.

12.5 I2C-bus

Table 17. Dynamic ch aracteristics: Watchdog oscillator

Symbol Parameter Conditions Min Typ[1] Max Unit

fosc(int) internal oscillator

frequency -[2] -503-kHz

Table 18. Dynamic chara cteristics: I/O pins[1]

Tamb =





C to +105



C; 3.0 V



VDD



3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

trrise time pin configured as output 3.0 - 5.0 ns

tffall time pin configured as output 2.5 - 5.0 ns

Table 19. Dynamic characteristic: I2C-bus pins[1]

Tamb =





C to +105



C; values guaranteed by design.[2]

Symbol Parameter Conditions Min Max Unit

fSCL SCL clock

frequency Standard-mode 0 100 kHz

Fast-mode 0 400 kHz

Fast-mode Plus; on

pins PIO0_22 and

PIO0_23

01MHz

tffall time [4][5][6][7] of both SDA and

SCL signals

Standard-mode

- 300 ns

Fast-mode 20 + 0.1  Cb300 ns

Fast-mode Plus;

on pins PIO0_22

and PIO0_23

- 120 ns

tLOW LOW period of

the SCL clock Standard-mode 4.7 - s

Fast-mode 1.3 - s

Fast-mode Plus; on

pins PIO0_22 and

PIO0_23

0.5 - s

tHIGH HIGH period of

the SCL clock Standard-mode 4.0 - s

Fast-mode 0.6 - s

Fast-mode Plus; on

pins PIO0_22 and

PIO0_23

0.26 - s

tHD;DAT data hold time [3][4][8] Standard-mode 0 - s

Fast-mode 0 - s

Fast-mode Plus; on

pins PIO0_22 and

PIO0_23

0-s

Product data sheet Rev. 1.1 — 29 April 2015 73 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[1] See the I2C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] Cb = total capacitance of one bus line in pF.

[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for S tandard-mode and Fast-mode but must be less than

the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement

tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must

meet this set-up time.

tSU;DAT data set-up

time

[9][10] Standard-mode 250 - ns

Fast-mode 100 - ns

Fast-mode Plus; on

pins PIO0_22 and

PIO0_23

50 - ns

Table 19. Dynamic characteristic: I2C-bus pins[1]

Tamb =





C to +105



C; values guaranteed by design.[2]

Symbol Parameter Conditions Min Max Unit

Fig 35. I2C-bus pins clock timing

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Product data sheet Rev. 1.1 — 29 April 2015 74 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

12.6 SPI interfaces

The maximum data bit rate is 17 Mbit/s in master mode and in slave mode.

Remark: SPI functions can be assigned to all dig it al pins. The characteristics are valid for

all digital pins except the open - dr ain pins PIO0_22 and PIO0 _2 3.

Table 20. SPI dynamic characteris tics

Tamb =





C to 105



C; 2.4 V <= VDD <= 3.6 V; CL = 10 pF; input slew = 1 ns. Simulated

parameters sampled at the 50 % le vel of the rising or falling edge; values guarante ed by design.

Symbol Parameter Min Max Unit

SPI master

tDS data set-up time 30 - ns

tDH data hold time 0 - ns

tv(Q) data output valid time - 4 ns

th(Q) data output hold time 2 - ns

SPI slave

tDS data set-up time 6 - ns

tDH data hold time 0 - ns

tv(Q) data output valid time - 29 ns

th(Q) data output hold time 12 - ns

Tcy(clk) = CCLK/DIVVAL with CCLK = system clock frequency. DIVVAL is the SPI clock divider . See

the LPC15xx User manual UM10736.

Fig 36. SPI master timing

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Product data sheet Rev. 1.1 — 29 April 2015 75 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Fig 37. SPI slave timing

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Product data sheet Rev. 1.1 — 29 April 2015 76 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

12.7 USART interface

The maximum USART bit rate is 15 Mbit/s in synchronous mode master mode and

18 Mbit/s in synchronous slave mode.

Remark: USART functions can be assig ned to all digital pins. The characteristics are valid

for all digital pins except the open-drain pins PIO0_22 and PIO0_23.

Table 21. USART dynamic ch aracteristics

Tamb =





C to 105



C; 2.4 V <= VDD <= 3.6 V; CL = 10 pF; input slew = 10 ns. Simulated

parameters sampled at the 50 % level of the falling or rising edge; values guarante ed by design.

Symbol Parameter Min Max Unit

USART master (in synchronous mode)

tsu(D) data input set-up time 33 - ns

th(D) data input hold time 0 - ns

tv(Q) data output valid time - 7 n s

th(Q) data output hold time 2 - ns

USART slave (in synchronous mode)

tsu(D) data input set-up time 13 - ns

th(D) data input hold time 0 - ns

tv(Q) data output valid time - 28 ns

th(Q) data output hold time 12 - ns

In master mode, Tcy(clk) = U_PCLK/BRGVAL. See the LPC15xx User manual UM10736.

Fig 38. USART timing

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Product data sheet Rev. 1.1 — 29 April 2015 77 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

12.8 SCTimer/PWM output timing

13. Characteristics of analog peripherals

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see the

LPC15xx user manual.

Table 22. SCTimer/PWM output dynamic characteristics

Tamb =





C to 105



C; 2.4 V <= VDD <= 3.6 V Cl = 10 pF. Simulated skew (over process, voltage,

and temperature) of any two SCT fixed-pin output signals; sampled at the 50 % level of the falling or

rising edge; values guarante ed by design.

Symbol Parameter Conditions Min Typ Max Unit

tsk(o) output skew time SCTimer0/PWM - - 4 ns

SCTimer1/PWM - - 3 ns

SCTimer2/PWM - - 1 ns

SCTimer3/PWM - - 2 ns

Table 23. BOD static characteristics[1]

Tamb =25



Symbol Parameter Conditions Min Typ Max Unit

Vth threshold voltage interrupt level 2

assertion - 2.55 - V

de-assertion - 2.69 - V

interrupt level 3

assertion - 2.83 - V

de-assertion - 2.96 - V

reset level 2

assertion - 2.34 - V

de-assertion - 2.49 - V

reset level 3

assertion - 2.64 - V

de-assertion - 2.79 - V

Product data sheet Rev. 1.1 — 29 April 2015 78 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[1] The input resistance of ADC channel 0 is higher than for all other channels.

[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width.

See Figure 40.

[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 40.

[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 40.

[5] The full-scale error voltage or gain error (EG) is the difference between the straight line fitting the actual

transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See

Figure 40.

[6] Tamb = 25 C; maximum sampling frequency fs = 2 Msamples/s and analog input capacitance Cia = 0.132

pF.

[7] Input impedance Zi is inversely proportional to the sampling frequency and the total input capacity including

Cia and Cio: Zi  1 / (fs  Ci). See Table 11 for Cio.

Table 24. 12-bit ADC static characteristics

Tamb =





C to +105



C; VDD = 2.4 V to 3.6 V; VREFP = VDDA; VSSA = 0; VREFN = VSSA.

Symbol Parameter Conditions Min Max Unit

VIA analog input voltage [1] 0V

DDA V

Cia analog input

capacitance -0.32pF

fclk(ADC) ADC clock frequency VDDA 2.7 V 50 MHz

VDDA 2.4 V 25 MHz

fssampling frequency VDDA 2.7 V - 2 Msam pl e s /s

VDDA 2.4 V - 1 Msamples/s

EDdifferential linearity

error [2] -+/- 2LSB

EL(adj) integral non-linearity [3] -+/- 2LSB

EOoffset error [4] -+/- 3LSB

Verr(fs) full-scale error voltage 2 Msamples/s [5] - +/- 0.12 %

1 Msamples/s +/- 0.07 %

Ziinput impedance fs = 2 Msamples/s [6][7] 0.1 - M

Product data sheet Rev. 1.1 — 29 April 2015 79 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Fig 39. ADC input impedance

DAC

ADC

Rsw = 5 Ω...25 Ω

R1 = 0.25 kΩ...2.5 kΩ

Cia

CDAC

ADCn_0

ADCn_[1:11]

aaa-011748

Cio

Product data sheet Rev. 1.1 — 29 April 2015 80 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 40. 12-bit ADC characteristics

002aaf436

4095

4094

4093

4092

4091

(2)

(1)

40964090 4091 4092 4093 4094 4095

7123456

4090

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VREFP - VSS

4096

offset

error

gain

error

offset error

VIA (LSBideal)

1 LSB =

Product data sheet Rev. 1.1 — 29 April 2015 81 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

Table 25. DAC static and dynamic characteristics

VDDA = 2.4 V to 3.6 V; Tamb =





C to +105



C unless otherwise specified; C L = 100 pF ;

RL=10k



Symbol Parameter Conditions Min Typ

[1] Max Unit

fc(DAC) DAC conversion

frequency - - 500 kSamples/s

ROoutput resistance - 300 

tssettling time - - 2.5 s

EDdifferential

linearity error -- +/-0.4 LSB

EL(adj) integral

non-linearity -- +/-3 LSB

EOoffset error VDDA = 3.3 V - - +/-9 L SB

VDDA = 2.4 V - - +/-8 LSB

EGgain error - - +/- 0.1 %

VOoutput voltage Output voltage range

with less than 1 LSB

deviation; with

minimum RL

connected to ground

or power supply

-- V

DDA - 0.3 V

Fig 41. DAC test circuit

DAC

10 kΩ

DVM

LPCxxxx

aaa-011964

Product data sheet Rev. 1.1 — 29 April 2015 82 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[1] Maximum and minimum values are measured on samples from the corners of the process matrix lot.

Table 26. Internal voltage reference static and dynamic characteristics

Symbol Parameter Conditions Min Typ Max Unit

VOoutput voltage Tamb = 40 C to +105 C[1] 875 - 925 mV

Tamb = 25 C 905 mV

ts(pu) power-up

settling time to 99% of VO- - 125 s

VDDA = 3.3 V; averaged over process corners

Fig 42. Average internal voltage reference output voltage

aaa-011179

-40 -10 20 50 80 110

890

895

900

905

910

915

920

temperature (°C)

VoltageVoltageVoltage

(V)(V)(V)

Product data sheet Rev. 1.1 — 29 April 2015 83 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[1] Absolute temperature accuracy.

[2] Typical values are derived from nominal simulation (VDDA = 3.3 V; Tamb = 27 C; nominal process models).

Maximum values are derived from worst case simulation (VDDA = 2.6 V; Tamb = 105 C; slow process

models).

[3] Internal voltage reference must be powered before the temperature sensor can be turned on.

[4] Settling time applies to switching between comparator and ADC channels.

[1] Measured over matrix samples.

[2] Measured for samples over process corners.

Table 27. Temperature sensor static and dynamic characteristics

VDDA = 2.4 V to 3.6 V

Symbol Parameter Conditions Min Typ Max Unit

DTsen sensor

temperature

accuracy

Tamb = 40 C to +105 C[1] -- 5 C

ELlinearity error Tamb = 40 C to +105 C- - 5 C

ts(pu) power-up

settling time to 99% of temperature

sensor output value [2][3] -81110s

Table 28. Temperature sensor Linear-Least-Square (LLS) fit parameters

VDDA = 2.4 V to 3.6 V

Fit parameter Range Min Typ Max Unit

LLS slope Tamb = 40 C to +105 C[1] - -2.29 - mV/C

LLS intercept at 0 CT

amb = 40 C to +105 C[1] - 577.3 - mV

Value at 30 C[2] 502 - 514 mV

VDDA = 3.3 V; measured on matrix samples.

Fig 43. LLS fit of the temperat ure sensor output voltage

aaa-011334

-40 -10 20 50 80 110

200

400

600

800

temperature (°C)

(mV)

Measured temperature sensor output

measured temperature sensor output

LLS fit

Product data sheet Rev. 1.1 — 29 April 2015 84 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[1] CL = 10 pF; results from measurements on silicon samples over process corners and over the full temperature range Tamb = -40 C to

+105 C.

[2] Input hysteresis is relative to the reference input channel and is software programmable.

Table 29. Comparator characteristics

VDDA = 3.0 V. DLY = 0x0 in the analog comparator CTRL register for shortest propagation delay setting. See the LPC15xx

user manual UM10736.

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

IDD supply current VP > VM - 48 - A

VM > VP - 38 - A

VIC common-mode input voltage 0 - VDDA V

DVOoutput voltage variation 0 - VDD V

Voffset offset voltage VIC = 0. 1 V - +/- 3 - mV

VIC = 1.5 V - +/- 3 - mV

VIC = 2.9 V - +/- 6 - mV

Dynamic character istics

tstartup start-up time nominal process - 4.5 6 s

tPD propagation delay HIGH to LOW; VDDA = 3.0 V;

VIC = 0.1 V; 50 mV overdrive input [1] - 86 130 ns

VIC = 0.1 V; rail-to-rail input [1] - 196 250 ns

VIC = 1.5 V; 50 mV overdrive input [1] - 68 110 ns

VIC = 1.5 V; rail-to-rail input [1] -64 90 ns

VIC = 2.9 V; 50 mV overdrive input [1] - 86 130 ns

VIC = 2.9 V; rail-to-rail input [1] -48 80 ns

tPD propagation delay LOW to HIGH; VDDA = 3.0 V;

VIC = 0.1 V; 50 mV overdrive input [1] - 98 130 ns

VIC = 0.1 V; rail-to-rail input [1] -24 40 ns

VIC = 1.5 V; 50 mV overdrive input [1] - 88 130 ns

VIC = 1.5 V; rail-to-rail input [1] - 68 120 ns

VIC = 2.9 V; 50 mV overdrive input [1] - 84 110 ns

VIC = 2.9 V; rail-to-rail input [1] - 98 180 ns

Vhys hysteresis voltage positive hysteresis; VDDA = 3.0 V;

VIC = 1.5 V; settings:

5 mV

[2]

3- 8 mV

10 mV 8 - 13 mV

15 mV 17 - 25 mV

Vhys hysteresis voltage negative hysteresis; VDDA = 3.0 V;

VIC = 1.5 V; settings:

5 mV

[1][2]

3- 9 mV

10 mV 8 - 18 mV

15 mV 18 - 27 mV

Rlad ladder resistance - - 1 - M

Product data sheet Rev. 1.1 — 29 April 2015 85 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

[1] Measured over a polyresistor matrix lot with a 2 kHz input signal and overdrive < 100 V.

[2] All peripherals except comparator, temperature sensor, and IRC turned off.

Table 30. Comparator voltage ladder dynamic characteristics

Symbol Parameter Conditions Min Typ Max Unit

ts(pu) power-up settling

time to 99% of voltage

ladder output

value

--30 s

ts(sw) switching settling

time to 99% of voltage

ladder output

value

--20 s

Table 31. Comparator voltage ladder reference static characteristics

VDDA = 3.3 V; Tamb = -40



C to + 105



C; external or internal reference.

Symbol Parameter Conditions Min Typ Max[1] Unit

EV(O) output voltage error decimal code = 00 [2] -03 mV

decimal code = 08 -1.5 0 +1.5 %

decimal code = 16 -1.5 0 +1.5 %

decimal code = 24 -1.5 0 +1.5 %

decimal code = 30 -1.5 0 +1.5 %

decimal code = 31 -1.5 0 +1.5 %

Product data sheet Rev. 1.1 — 29 April 2015 86 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

14. Application information

14.1 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy

environment beyond the ADC specifications listed in Table 24:

•The ADC input trace must be short and as close as possible to the LPC15xx chip.

•The ADC input traces must be shielded from fast switching digital signals and noisy

power supply lin e s.

•If the ADC and the digital core share the same power su pply, the power supply line

must be adequately filtered.

•To improve the ADC performance in a very noisy environment, put the device in Sleep

mode during the ADC conversion.

14.2 Suggested USB interface solutions

The USB device can be connected to the USB as self-powered device (see Figure 44) or

bus-powered device (s ee Figure 45).

On the LPC15xx, the PIO0_3/USB_VBUS pin is 5 V tolerant only when VDD is applie d and

at operating voltage level. Therefore, if the USB_VBUS function is connected to the USB

connector an d the de vice is self- po we re d, the USB_VBUS pin must be protected for

situations when VDD = 0 V.

If VDD is always greater than 0 V while VBUS = 5 V, the USB_VBUS pin can be connected

directly to the VBUS pin on the USB connector.

For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin,

precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum

allowable voltage on the USB_VBUS pin in this case.

One method is to use a volt age divider to connect th e USB_VBUS pin to the VBUS on the

USB connector. The voltage divider ratio should be such that the USB_VBUS pin will be

greater than 0.7VDD to indicate a logic HIGH while below the 3.6 V allow ab le ma xim u m

voltage.

For the following operat ing conditions

VBUSmax = 5.25 V

VDD = 3.6 V,

the voltage divider shou ld pr ov ide a red uc tio n of 3.6 V/5 .2 5 V or ~0. 68 6 V.

Product data sheet Rev. 1.1 — 29 April 2015 87 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

For a bus-powered device, the VBUS signal does not need to be connected to the

USB_VBUS pin (see Figure 45). The USB_CONNECT function can additionally be

enabled internally by settin g the DCO N bit in th e DEVCMD STAT register to preven t the

USB from timing out when there is a significant delay between power-up and handling

USB traffic. External circuitry is not required for the USB_CONNECT functionality.

Remark: When a bus-powered circuit as shown in Figure 45 is used or , for a self-powered

device, when the VBUS pin is not conn ected, configure the PIO0_3/USB_VBUS pin for

GPIO (PIO0_3) in the IOCON block. This ties the VBUS signal HIGH internally.

14.2.1 USB Low-speed operation

The USB device controller can be used in low-speed mode supporting 1.5 Mbit/s data

exchange with a USB host controller.

Remark: To operate in low-speed mode, change the board connections as follows:

1. Connect USB_DP to the D- pin of the connector.

2. Connect USB_DM to the D+ pin of the connector.

Fig 44. USB interface on a self-powered device where USB_VBUS = 5 V

LPC1xxx

VDD

1.5 kΩ

aaa-010820

USB-B

connector

USB_DP

USB_DM

USB_VBUS

VSS

RS = 33 Ω

USB

USB_CONNECT R2

Fig 45. USB interface on a bus-powered device

REGULATOR

VBUS

LPC1xxx

VDD

1.5 kΩ

aaa-010821

USB-B

connector

USB_DP

USB_DM

VSS

RS = 33 Ω

USB

USB_CONNECT

Product data sheet Rev. 1.1 — 29 April 2015 88 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

External 10  resistors are recommended in low-speed mode to reduce over-shoots and

accommodate for 5 m cable length required for USB-IF testing.

14.3 XTAL input and crystal oscillator component selection

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommende d that the inpu t be coupled th rough a cap acitor with

Ci = 100 pF. To limit the input voltag e to the specified range, choose an additional

capacitor to ground Cg which attenuates the input volt age by a facto r Ci/(Ci + Cg). In slave

mode, a minimum of 200 mV(RMS) is needed.

In slave mode the input clock signal should be coup led by means of a cap acitor of 100 pF

(Figure 46), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 47 and in

Table 32 and Table 33. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances CX1 and CX2 need to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, CL and

RS). Capacitance CP in Figure 47 represent s the p arallel p ackage cap acitance and should

not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by th e cry s tal

manufacturer (see Table 32).

Fig 46. Slave mode operation of the on-chip oscillator

LPC1xxx

XTALIN

100 pF Cg

002aae788

Product data sheet Rev. 1.1 — 29 April 2015 89 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

14.4 XTAL Printed-Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the lo ad cap acitors Cx1, Cx2, and Cx3 in case of

third overtone crystal usage have a common ground plane. The external components

must also be conne cted to the g round p lane. Lo op s must be made as small as possible in

Fig 47. Oscillator modes and models: oscillation mod e of op eration and external crystal

model used for CX1/CX2 evaluation

Table 32. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

1 MHz to 5 MHz 10 pF < 300 18 pF, 18 pF

20 pF < 300 39 pF, 39 pF

30 pF < 300 57 pF, 57 pF

5 MHz to 10 MHz 10 pF < 300 18 pF, 18 pF

20 pF < 200 39 pF, 39 pF

30 pF < 100 57 pF, 57 pF

10 MHz to 15 MHz 10 pF < 160 18 pF, 18 pF

20 pF < 60 39 pF, 39 pF

15 MHz to 20 MHz 10 pF < 80 18 pF, 18 pF

Table 33. Recommended values for CX1/CX2 in oscillation mode (crystal and external

components parameters) high frequency mode

Fundamental oscillation

frequency FOSC

Crystal load

capacitance CL

Maximum crystal

series resistance RS

External load

capacitors CX1, CX2

15 MHz to 20 MHz 10 pF < 180 18 pF, 18 pF

20 pF < 100 39 pF, 39 pF

20 MHz to 25 MHz 10 pF < 160 18 pF, 18 pF

20 pF < 80 39 pF, 39 pF

002aaf424

LPC1xxx

XTALIN XTALOUT

CX2

CX1

XTAL

=CLCP

Product data sheet Rev. 1.1 — 29 April 2015 90 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

order to keep the noise coup le d in via the PCB as sm all as po ss ible . A lso parasitics

should stay as small as possible. Smaller values of Cx1 and Cx2 should be chosen

according to the increase in parasitics of the PCB layout.

Product data sheet Rev. 1.1 — 29 April 2015 91 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

14.5 RTC oscillator component selection

The 32 kHz crystal must be con nected to the p ar t via the R TCXIN and RTCXOUT pins as

shown in Figure 48. If the RTC is not used, the RTCXIN pin can be grounded.

Select Cx1 and Cx2 based on the external 32 kHz crystal used in the application

circuitry.The pad cap acitance CP of the R TCXIN and R TCXOUT pad is 3 pF. If the external

crystal’s load capacitance is CL, the optimal Cx1 and Cx2 can be selected as:

Cx1 = Cx2 = 2 x CL – CP

14.6 Connecting power, clocks, and debug functions

Figure 49 shows the basic board connections used to power the LPC15xx, connect the

external crystal and the 32 kHz oscillator for the RTC, and provide debug capabilities via

the serial wire port .

Fig 48. RTC oscillator components

LPC1xxx

RTCXIN RTCXOUT

CX2

CX1

XTAL

=CLCP

aaa-010822

Product data sheet Rev. 1.1 — 29 April 2015 92 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

(1) See Section 14.3 “XTAL input and crystal oscillator component selection” for the values of C1 and C2.

(2) See Section 14.5 “RTC oscillator component selection” for the values of C3 and C4.

(3) Position the decoupling capacitors of 0.1 F and 0.01 F as close as possible to the VDD pin. Add one set of decoupling

capacitors to each VDD pin.

(4) Position the decoupling capacitors of 0.1 F as close as possible to the VREFN and VDDA pins. The 10 F bypass capacitor

filters the power line. Tie VDDA and VREFP to VDD if the ADC is not used. Tie VREFN to VSS if ADC is not used.

(5) Position the decoupling capacitor of 0.1 F as close as possible to the VBAT pin. Tie VBAT to VDD if not used.

(6) Uses the ARM 10-pin interface for SWD.

(7) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see

Ref. 3.

(8) ISP pin assignments is dependent on package type. See Table 7 “Pin assignments for ISP modes”.

Fig 49. Power, clock, and debug connec tions

SWDIO/PIO0_20/

SCT1_OUT6/TMS

SWCLK/PIO0_19/TCK

RESET/PIO0_21

VSS

VSSA

ISP_0

ISP_1

pins with analog functions

XTALIN

XTALOUT

RTCXIN

RTCXOUT

VDD (3 to 6 pins)

VDDA

VREFP_ADC/VREFP_DAC_VDDCMP

VREFN

VBAT

LPC15xx

3.3 V

DGND

DGND DGND

DGND

AGND

Note 6

Note 7

Note 8

Note 1

DGND

Note 2

Note 3

Note 4

Note 5

0.01 μF

0.1 μF

3.3 V

DGND

10 μF

0.1 μF

3.3 V

AGND

10 μF

0.1 μF

ISP select pins

n.c.

SWD connector

3.3 V

~10 kΩ - 100 kΩ

aaa-018157

Product data sheet Rev. 1.1 — 29 April 2015 93 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

14.7 Termination of unused pins

Table 34 shows how to terminate pins that are not used in the application. In many ca ses,

unused pins may should be connected externally or configured correctly by softwa re to

minimize the overall power consumption of the part.

Unused pins with GPIO function shou ld be configured as GPIO (switch matrix default) and

setto outputs driving LOW with thei r internal pull-up disabled. To drive the output LOW,

select output in the GPIO DIR register, and write a 0 to the GPIO PORT register for that

pin. Disable the pull-up in the pin’s IOCON register.

In addition, it is recommended to configure all GPIO pins that are not bond e d out on

smaller packages as outputs driven LOW with their internal pull-up disabled.

[1] I = Input, O = Output, IA = Inactive (no pull-up/pull-down enabled), F = floating, PU = Pull-Up.

Table 34. Termination of unused pins

Pin Default

state[1] Recommended termina tio n of un us ed pins

RESET/PIO0_21 I; PU In an application that does not use the RESET pin or its GPIO function, the

termination of this pin depends on whether Deep power-down mode is used:

•Deep power-down used: Connect an external pull-up resistor and keep pin in

default state (input, pull-up enabled) during all other power modes.

•Deep power-down not used and no external pull-up connected: can be left

unconnected if internal pull-up is disabled and pin is driven LOW and

configured as output by software.

all PIOn_m (not

open-drain) I; PU Can be left unconnected if driven LOW and configured as GPIO output with pull-up

disabled by software.

PIOn_m (I2C open-drain) IA Can be left unconnected if driven LOW and configured as GPIO output by software.

USB_DP/USB_DM F Can be left unconnected. When the USP PHY is disabled, the pins are LOW.

RTCXIN - Connect to ground. When grounded, the RTC oscillator is disabled.

RTCXOUT - Can be left unconnected.

VREFP_DAC_VDDCMP - Tie to VDD.

VREFP_ADC Tie to VDD.

VREFN - Tie to VSS.

VDDA - Tie to VDD.

VBAT - Tie to VDD if no external battery connected.

VSSA - Tie to VSS.

Product data sheet Rev. 1.1 — 29 April 2015 94 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

14.8 Pin states in different power modes

[1] Default and programmed pin states are retained in sleep, deep-sleep, and power-down modes.

Table 35. Pin states in different power modes

Pin Active Sleep Deep-sleep/Power-

down Deep power-down

PIOn_m pins (not

I2C) As configured in the IOCON[1]. Default: internal pull-up

enabled. Floating.

PIO0_22,

PIO0_23

(open-drain

I2C-bus pins)

As configured in the IOCON[1]. Floating.

RESET/PIO0_21 Reset function enabled. Default: input, internal pull-up

enabled. Reset function disabled; floating; if the part

is in deep power-down mode, addan

external pull-up to the RESET pin to reduce

power consumption.

PIO0_17/

WAKEUP/TRST As configured in the IOCON[1]. W AKEUP function inactive. W ake-up function enabled; can be disabled

by software.

Product data sheet Rev. 1.1 — 29 April 2015 95 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

14.9 ElectroMagnetic Compatibility (EMC)

Radiated emission measurements according to the IEC61967-2 standard using the

TEM-cell method are shown for part LPC1549JBD100.

[1] IEC levels refer to Appendix D in the IEC61967-2 Specification.

Table 36. ElectroMagnetic Compatibility (EMC) for part LPC1549 (TEM-cell method)

VDD = 3.3 V; Tamb = 25



Parameter Frequency band System

clock = Unit

12 MHz 24 MHz 36 MHz 48 MHz 60 MHz 72 MHz

Input clock: IRC (12 MHz)

maximum

peak level 1 MHz to 30 MHz -5 -1 -5 -4 -3 0 dBV

30 MHz to 150 MHz -1 +3 +6 +8 +11 +14 dBV

150 MHz to 1 GHz -1 +2 +5 +10 +9 +11 dBV

IEC level[1] -OOONNM-

Input clock: crystal oscillator (12 MHz)

maximum

peak level 1 MHz to 30 MHz -2 0 -5 -2 -2 2 dBV

30 MHz to 150 MHz 0 +3 +6 +8 +12 +14 dBV

150 MHz to 1 GHz -1 +3 +5 +10 +10 +11 dBV

IEC level[1] -OOONNM-

Product data sheet Rev. 1.1 — 29 April 2015 96 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

15. Package outline

Fig 50. Package outline LQFP48 (SOT313-2)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 7.1

6.9 0.5 9.15

8.85 0.95

0.55 7

0.12 0.10.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2 MS-026136E05 00-01-19

03-02-25

D(1) (1)(1)

7.1

6.9

9.15

8.85

0.95

0.55

vMB

vMA

36 25

detail X

(A )

0 2.5 5 mm

scale

pin 1 index

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

Product data sheet Rev. 1.1 — 29 April 2015 97 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Fig 51. Package outline LQFP64 (SOT314-2)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 10.1

9.9 0.5 12.15

11.85 1.45

1.05 7

0.12 0.11 0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT314-2 MS-026136E10 00-01-19

03-02-25

D(1) (1)(1)

10.1

9.9

12.15

11.85

1.45

1.05

EA1

detail X

(A )

HA2

vMB

vMA

48 33

pin 1 index

0 2.5 5 mm

scale

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2

Product data sheet Rev. 1.1 — 29 April 2015 98 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Fig 52. Package outline LQFP100 (SOT407-1)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.15

0.05 1.45

1.35 0.25 0.27

0.17 0.20

0.09 14.1

13.9 0.5 16.25

15.75 1.15

0.85 7

0.08 0.080.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT407-1 136E20 MS-026 00-02-01

03-02-20

D(1) (1)(1)

14.1

13.9

16.25

15.75

1.15

0.85

EA1

detail X

(A )

HA2

vMB

vMA

100

7675 5150

pin 1 index

0 5 10 mm

scale

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1

Product data sheet Rev. 1.1 — 29 April 2015 99 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

16. Soldering

Fig 53. Reflow soldering for the LQFP48 package

SOT313-2

DIMENSIONS in mm

occupied area

Footprint information for reflow soldering of LQFP48 package

AyBy

D2 (8×)D1

(0.125)

Ax Ay Bx By D1 D2 Gx Gy Hx Hy

10.350

0.560 10.350 7.350 7.350

0.500 0.280

1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr

solder land

Generic footprint pattern

Refer to the package outline drawing for actual layout

Product data sheet Rev. 1.1 — 29 April 2015 100 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Fig 54. Reflow soldering for the LQFP64 package

SOT314-2

DIMENSIONS in mm

occupied area

Footprint information for reflow soldering of LQFP64 package

AyBy

P1P2

D2 (8×) D1

(0.125)

Ax Ay Bx By D1 D2 Gx Gy Hx Hy

13.300 13.300 10.300 10.300

0.500

0.560 0.280

1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr

solder land

Generic footprint pattern

Refer to the package outline drawing for actual layout

Product data sheet Rev. 1.1 — 29 April 2015 101 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Fig 55. Reflow soldering for the LQFP100 package

SOT407-1

DIMENSIONS in mm

occupied area

Footprint information for reflow soldering of LQFP100 package

AyBy

P1P2

D2 (8×) D1

(0.125)

Ax Ay Bx By D1 D2 Gx Gy Hx HyP1 P2 C

sot407-1

solder land

Generic footprint pattern

Refer to the package outline drawing for actual layout

17.300 17.300 14.300 14.3000.500 0.560 0.2801.500 0.400 14.500 14.500 17.550 17.550

Product data sheet Rev. 1.1 — 29 April 2015 102 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

17. References

[1] LPC15xx User manual UM10736:

http://www.nxp.com/documents/user_manual/UM10736.pdf

[2] LPC15xx Errata sheet:

http://www.nxp.com/documents/errata_sheet/ES_LPC15XX.pdf

[3] Tec hnical note ADC design guidelines:

http://www.nxp.com/documents/technical_note/TN00009.pdf

Product data sheet Rev. 1.1 — 29 April 2015 103 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

18. Revision history

Table 37. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC15XX v.1.1 20150429 Product data sheet - LPC15XX v.1

Modifications: •Pin description table updated for clarification (I2C-bus pins, VBAT, WAKEUP,

RTCXIN/OUT).

•Table note 11 added in Table 3.

•Section 14.1 “ADC usage notes” added.

•Section 14.6 “Connecting power, clocks, and debug functions” added.

•Section 14.7 “Termination of unused pins” added.

•Section 14.8 “Pin states in different power modes” added.

•Section 14.9 “ElectroMagnetic Compatibility (EMC)” added.

•Table 11 “Static characteristics”: Changed the power-down max specification value: IDD

Power-down mode; VDD = 3.3 V Tamb = 25 °C from 8 A to 15 A.

LPC15XX v.1 <tbd> Product data sheet - -

Product data sheet Rev. 1.1 — 29 April 2015 104 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

19. Legal information

19.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device (s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

19.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

19.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for t he customer’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with t heir

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo mer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains dat a from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contain s the product specification.

Product data sheet Rev. 1.1 — 29 April 2015 105 of 107

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qua lified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims result ing from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

19.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP Semi conductors N.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 1.1 — 29 April 2015 106 of 107

continued >>

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

21. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 5

5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 8

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 12

8 Functional description . . . . . . . . . . . . . . . . . . 21

8.1 ARM Cortex-M3 processor. . . . . . . . . . . . . . . 21

8.2 Memory Protection Unit (MPU). . . . . . . . . . . . 21

8.3 On-chip flash programming memory . . . . . . . 22

8.3.1 ISP pin configuration . . . . . . . . . . . . . . . . . . . 22

8.4 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.5 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.6 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.7 AHB multilayer matrix. . . . . . . . . . . . . . . . . . . 25

8.8 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.9 Nested V e ctored Interrupt controller (NVIC). . 27

8.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.9.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 27

8.10 IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.10.2 Standard I/O pad configuration. . . . . . . . . . . . 27

8.11 Switch Matrix (SWM) . . . . . . . . . . . . . . . . . . . 28

8.12 Fast General-Purpose parallel I/O (GPI O) . . . 29

8.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.13 Pin interrupt/pattern match engine (PINT) . . . 29

8.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.14 GPIO group interrupts (GINT0/1) . . . . . . . . . . 30

8.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.15 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 30

8.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.16 Input multiplexing (Input mux) . . . . . . . . . . . . 31

8.17 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 31

8.17.1 Full-speed USB device controller . . . . . . . . . . 31

8.17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.18 USART0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.19 SPI0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.20 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 33

8.20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.21 C_CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.22 PWM/timer/motor control subsystem. . . . . . . 34

8.22.1 SCtimer/PWM subsystem . . . . . . . . . . . . . . . 34

8.22.2 Timer controlle d su bsystem. . . . . . . . . . . . . . 35

8.22.3 SCT imer/PWM in the large configuration (SCT0/1)

8.22.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.22.4 State-Configurable T imers in the small

configuration (SCT2/3). . . . . . . . . . . . . . . . . . 38

8.22.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.22.5 SCT Input processing unit (SCTIPU). . . . . . . 39

8.22.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.23 Quadrature Encoder Interface (QEI) . . . . . . . 40

8.23.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.24 Analog-to-Digital Converter (ADC). . . . . . . . . 40

8.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.25 Digital-to-Analog Converter (DAC). . . . . . . . . 41

8.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.26 Analog comparator (ACMP). . . . . . . . . . . . . . 41

8.26.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.27 Temperature sensor. . . . . . . . . . . . . . . . . . . . 42

8.28 Internal voltage reference . . . . . . . . . . . . . . . 42

8.29 Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 43

8.29.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.30 Windowed WatchDog Timer (WWDT) . . . . . . 43

8.30.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.31 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 44

8.31.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.32 System tick timer . . . . . . . . . . . . . . . . . . . . . . 44

8.33 Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . 44

8.33.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.34 Clock generation . . . . . . . . . . . . . . . . . . . . . . 45

8.35 Power domains . . . . . . . . . . . . . . . . . . . . . . . 46

8.36 Integrated oscillators . . . . . . . . . . . . . . . . . . . 46

8.36.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 47

8.36.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 47

8.36.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 47

8.36.4 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 47

8.37 System PLL, USB PLL, and SCT PLL . . . . . . 47

8.38 Clock output. . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.39 Wake-up process. . . . . . . . . . . . . . . . . . . . . . 48

8.40 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 48

8.40.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 48

8.40.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.40.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 49

8.40.4 Power-down mode. . . . . . . . . . . . . . . . . . . . . 49

8.40.5 Deep power-down mode . . . . . . . . . . . . . . . . 49

8.41 System control. . . . . . . . . . . . . . . . . . . . . . . . 50

NXP Semiconductors LPC15xx

32-bit ARM Cortex-M3 microcontroller

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 29 April 2015

Document identifier: LPC15XX

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

8.41.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.41.2 Brownout detection. . . . . . . . . . . . . . . . . . . . . 50

8.41.3 Code security (Code Read Protection - CRP) 50

8.42 Emulation and debugging. . . . . . . . . . . . . . . . 52

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 52

10 Thermal characteristics . . . . . . . . . . . . . . . . . 53

11 Static characteristics. . . . . . . . . . . . . . . . . . . . 55

11 .1 Power consumption . . . . . . . . . . . . . . . . . . . . 60

11 .2 CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 64

11.3 Peripheral power consumption. . . . . . . . . . . . 65

11.4 Electrical pin characteristics . . . . . . . . . . . . . . 66

12 Dynamic characteristics . . . . . . . . . . . . . . . . . 70

12.1 Flash/EEPROM memory . . . . . . . . . . . . . . . . 70

12.2 External clock for the oscillator in slave mode 70

12.3 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 71

12.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

12.5 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

12.6 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 74

12.7 USART interface. . . . . . . . . . . . . . . . . . . . . . . 76

12.8 SCTimer/PWM output timing . . . . . . . . . . . . . 77

13 Characteristics of analog peripherals . . . . . . 77

14 Application information. . . . . . . . . . . . . . . . . . 86

14.1 ADC usage notes . . . . . . . . . . . . . . . . . . . . . . 86

14.2 Suggested USB interface solutions . . . . . . . . 86

14.2.1 USB Low-speed operation . . . . . . . . . . . . . . . 87

14.3 XTAL input and crystal oscillator component

selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

14.4 XTAL Printed-Circuit Board (PCB) layout

guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

14.5 RTC oscillator component selection. . . . . . . . 91

14.6 Connecting power, clocks, and debug

functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

14.7 Termination of unused pins. . . . . . . . . . . . . . . 93

14.8 Pin states in different power modes . . . . . . . . 94

14.9 ElectroMagnetic Compatibility (EMC). . . . . . . 95

15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 96

16 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

17 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

18 Revision history. . . . . . . . . . . . . . . . . . . . . . . 103

19 Legal information. . . . . . . . . . . . . . . . . . . . . . 104

19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 104

19.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 104

19.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 104

19.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 105

20 Contact information. . . . . . . . . . . . . . . . . . . . 105

21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106