LPC15xx 32-bit ARM Cortex-M3 microcontroller; up to 256 kB flash and 36 kB SRAM; FS USB, CAN, RTC, SPI, USART, I2C Rev. 1.1 -- 29 April 2015 Product data sheet 1. General description The LPC15xx are ARM Cortex-M3 based microcontrollers for embedded applications featuring a rich peripheral set with very low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The LPC15xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The LPC15xx includes up to 256 kB of flash memory, 32 kB of ROM, a 4 kB EEPROM, and up to 36 kB of SRAM. The peripheral complement includes one full-speed USB 2.0 device, two SPI interfaces, three USARTs, one Fast-mode Plus I2C-bus interface, one C_CAN module, PWM/timer subsystem with four configurable, multi-purpose State Configurable Timers (SCTimer/PWM) with input pre-processing unit, a Real-time clock module with independent power supply and a dedicated oscillator, two 12-channel/12-bit, 2 Msamples/s ADCs, one 12-bit, 500 kSamples/s DAC, four voltage comparators with internal voltage reference, and a temperature sensor. A DMA engine can service most peripherals. For additional documentation related to the LPC15xx parts, see Section 17 "References". 2. Features and benefits System: ARM Cortex-M3 processor (version r2p1), running at frequencies of up to 72 MHz. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). System tick timer. Serial Wire Debug (SWD) with four breakpoints and two watchpoints. Single-cycle multiplier supported. Memory Protection Unit (MPU) included. Memory: Up to 256 kB on-chip flash programming memory with 256 Byte page write and erase. Up to 36 kB SRAM. 4 kB EEPROM. LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller ROM API support: Boot loader with boot options from flash or external source via USART, C_CAN, or USB USB drivers ADC drivers SPI drivers USART drivers I2C drivers Power profiles and power mode configuration with low-power mode configuration option DMA drivers C_CAN drivers Flash In-Application Programming (IAP) and In-System Programming (ISP). Digital peripherals: Simple DMA engine with 18 channels and 20 programmable input triggers. High-speed GPIO interface with up to 76 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, open-drain mode, input inverter, and programmable digital glitch filter. GPIO interrupt generation capability with boolean pattern-matching feature on eight external inputs. Two GPIO grouped port interrupts. Switch matrix for flexible configuration of each I/O pin function. CRC engine. Quadrature Encoder Interface (QEI). Configurable PWM/timer/motor control subsystem: Up to four 32-bit counter/timers or up to eight 16-bit counter/timers or combinations of 16-bit and 32-bit timers. Up to 28 match outputs and 22 configurable capture inputs with input multiplexer. Up to 28 PWM outputs total. Dither engine for improved average resolution of pulse edges. Four State Configurable Timers (SCTimers) for highly flexible, event-driven timing and PWM applications. SCT Input Pre-processor Unit (SCTIPU) for processing timer inputs and immediate handling of abort situations. Integrated with ADC threshold compare interrupts, temperature sensor, and analog comparator outputs for motor control feedback using analog signals. Special-application and simple timers: 24-bit, four-channel, multi-rate timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates. Repetitive interrupt timer for general purpose use. Windowed Watchdog timer (WWDT). High-resolution 32-bit Real-time clock (RTC) with selectable 1 s or 1 ms time resolution running in the always-on power domain. RTC can be used for wake-up from all low power modes including Deep power-down. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 2 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Analog peripherals: Two 12-bit ADC with up to 12 input channels per ADC and with multiple internal and external trigger inputs and sample rates of up to 2 Msamples/s. Each ADC supports two independent conversion sequences. ADC conversion clock can be the system clock or an asynchronous clock derived from one of the three PLLs. One 12-bit DAC. Integrated temperature sensor and band gap internal reference voltage. Four comparators with external and internal voltage references (ACMP0 to 3). Comparator outputs are internally connected to the SCTimer/PWMs and ADCs and externally to pins. Each comparator output contains a programmable glitch filter. Serial interfaces: Three USART interfaces with DMA, RS-485 support, autobaud, and with synchronous mode and 32 kHz mode for wake-up from Deep-sleep and Power-down modes. The USARTs share a fractional baud-rate generator. Two SPI controllers. One I2C-bus interface supporting fast mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. One C_CAN controller. One USB 2.0 full-speed device controller with on-chip PHY. Clock generation: 12 MHz internal RC oscillator trimmed to 1 % accuracy for 25 C Tamb +85 C that can optionally be used as a system clock. Crystal oscillator with an operating range of 1 MHz to 25 MHz. Watchdog oscillator with a frequency range of 503 kHz. 32 kHz low-power RTC oscillator with 32 kHz, 1 kHz, and 1 Hz outputs. System PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. Two additional PLLs for generating the USB and SCTimer/PWM clocks. Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator. Power control: Integrated PMU (Power Management Unit) to minimize power consumption. Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. APIs provided for optimizing power consumption in active and sleep modes and for configuring Deep-sleep, Power-down, and Deep power-down modes. Wake-up from Deep-sleep and Power-down modes on activity on USB, USART, SPI, and I2C peripherals. Wake-up from Sleep, Deep-sleep, Power-down, and Deep power-down modes from the RTC alarm or wake-up interrupts. Timer-controlled self wake-up from Deep power-down mode using the RTC high-resolution/wake-up 1 kHz timer. Power-On Reset (POR). BrownOut Detect BOD). JTAG boundary scan modes supported. Unique device serial number for identification. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 3 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Single power supply 2.4 V to 3.6 V. Temperature range 40 C to +105 C. Available as LQFP100, LQFP64, and LQFP48 packages. 3. Applications Motor control Motion drives Digital power supplies Industrial and medical Solar inverters Home appliances Building and factory automation 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC1549JBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm LPC1549JBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1549JBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2 LPC1548JBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm LPC1548JBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1547JBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1547JBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2 LPC1519JBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm LPC1519JBD64 LQFP64 LPC1518JBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm LPC1518JBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1517JBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1517JBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2 LPC15XX Product data sheet plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 SOT407-1 SOT407-1 SOT407-1 SOT314-2 SOT407-1 (c) NXP Semiconductors N.V. 2015. All rights reserved. 4 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 4.1 Ordering options Table 2. Ordering options for LPC15xx Type number Flash/ kB EEPROM/ Total USB kB SRAM/ kB USART I2C SPI C_CAN SCTimer/ 12-bit DAC GPIO PWM ADC0/1 channels LPC1549JBD100 256 4 36 yes 3 1 2 1 4 12/12 1 76 LPC1549JBD64 256 4 36 yes 3 1 2 1 4 12/12 1 44 LPC1549JBD48 256 4 36 yes 3 1 2 1 4 9/7 1 30 LPC1548JBD100 128 4 20 yes 3 1 2 1 4 12/12 1 76 LPC1548JBD64 128 4 20 yes 3 1 2 1 4 12/12 1 44 LPC1547JBD64 64 4 12 yes 3 1 2 1 4 12/12 1 44 LPC1547JBD48 64 4 12 yes 3 1 2 1 4 9/7 1 30 LPC1519JBD100 256 4 36 no 3 1 2 1 4 12/12 1 78 LPC1519JBD64 256 4 36 no 3 1 2 1 4 12/12 1 46 LPC1518JBD100 128 4 20 no 3 1 2 1 4 12/12 1 78 LPC1518JBD64 128 4 20 no 3 1 2 1 4 12/12 1 46 LPC1517JBD64 64 4 12 no 3 1 2 1 4 12/12 1 46 LPC1517JBD48 64 4 12 no 3 1 2 1 4 9/7 1 32 LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 5 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 5. Marking n n Terminal 1 index area 1 aaa-011231 Fig 1. LQFP64/100 package marking Terminal 1 index area Fig 2. 1 aaa-011232 LQFP48 package marking The LPC15xx devices typically have the following top-side marking for LQFP100 packages: LPC15xxJxxx Xxxxxx xx xxxyywwxxx The LPC15xx devices typically have the following top-side marking for LQFP64 packages: LPC15xxJ Xxxxxx xx xxxyywwxxx The LPC15xx devices typically have the following top-side marking for LQFP48 packages: LPC15xxJ Xxxxxx Xxxyy wwxxx Field `yy' states the year the device was manufactured. Field `ww' states the week the device was manufactured during that year. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 6 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 6. Block diagram LPC15xx PROCESSOR CORE ARM CORTEX-M3 NVIC TEST/DEBUG INTERFACE SWD/ETM MPU HS GPIO MEMORY 256/128/64 kB FLASH PORT0/1/2 pads n SYSTICK AHB MULTILAYER MATRIX PINT/ PATTERN MATCH 4 kB EEPROM INPUT MUX 36/20/12 kB SRAM GINT0/1 AHB/APB BRIDGES 32 kB ROM ANALOG PERIPHERALS ACMP1 ACMP0/ TEMPERATURE SENSOR 12-bit DAC ACMP2 ACMP3 12-bit ADC0 12-bit ADC1 TRIGGER MUX TRIGGER MUX INPUT MUX INPUT MUX SWM pads n SCTIMER/PWM/MOTOR CONTROL SUBSYSTEM DMA TRIGGER QEI SCTIMER0/ SCTIMER1/ SCTIMER2/ SCTIMER3/ PWM PWM PWM PWM DMA SCTIPU SERIAL PERIPHERALS C_CAN FS USB/ PHY USART0 FM+ I2C0 SPI1 USART1 USART2 SPI0 TIMERS CLOCK GENERATION MRT RIT PRECISION IRC WATCHDOG OSCILLATOR SYSTEM PLL USB PLL SCT PLL WWDT RTC SYSTEM OSCILLATOR FREQUENCY MEASUREMENT RTC OSCILLATOR INPUT MUX SYSTEM/MEMORY CONTROL SYSCON IOCON PMU CRC FLASH CTRL EEPROM CTRL aaa-010869 Grey-shaded blocks show peripherals that can provide hardware triggers for DMA transfers or have DMA request lines. Fig 3. LPC15xx Block diagram LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 7 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7. Pinning information 25 XTALOUT 26 XTALIN 27 VDD 28 PIO0_17/WAKEUP/TRST 29 SWCLK/ PIO0_19/TCK 30 VBAT 31 RTCXIN 32 RTCXOUT 33 SWDIO/ PIO0_20/SCT1_OUT6/ TMS 34 RESET/PIO0_21 35 USB_DP 36 USB_DM 7.1 Pinning PIO0_22/I2C0_SCL 37 24 PIO0_16/ADC1_9 PIO0_23/I2C0_SDA 38 23 PIO0_15/ADC1_8 VDD 39 22 PIO0_14/ADC1_7/ SCT1_OUT5 VSS 40 21 PIO0_13/ADC1_6 VSS 41 20 VSS VDD 42 19 PIO0_12/DAC_OUT LPC1547JBD48 LPC1549JBD48 PIO0_24/SCT0_OUT6 43 18 PIO0_11/ADC1_3 PIO0_25/ACMP0_I4 44 17 VSSA PIO0_26/ACMP0_I3/ SCT3_OUT3 45 16 VDDA PIO0_27/ACMP_I1 46 15 PIO0_10/ADC1_2 PIO0_28/ACMP1_I3 47 14 VREFP_DAC_VDDCMP PIO0_9/ADC1_1/TDI 12 VREFN 11 VREFP_ADC 10 PIO0_7/ADC0_1 8 PIO0_8/ADC0_0/TDO 9 PIO0_5/ADC0_3 6 PIO0_6/ADC0_2/ SCT2_OUT3 7 PIO0_4/ADC0_4 5 PIO0_3/ADC0_5/ SCT1_OUT4 4 PIO0_2/ADC0_6/ SCT1_OUT3 3 PIO0_1/ADC0_7/ SCT0_OUT4 2 13 PIO0_18/ SCT0_OUT5 PIO0_0/ADC0_10/ SCT0_OUT3 1 PIO0_29/ACMP2_I3/ SCT2_OUT4 48 aaa-009352 Fig 4. LQFP48 pin configuration (with USB) LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 8 of 107 LPC15xx NXP Semiconductors 25 XTALOUT 26 XTALIN 27 VDD 28 PIO0_17/WAKEUP/TRST 29 SWCLK/ PIO0_19/TCK 30 VBAT 31 RTCXIN 32 RTCXOUT 33 SWDIO/ PIO0_20/SCT1_OUT6/ TMS 34 RESET/PIO0_21 35 PIO2_12 36 PIO2_13 32-bit ARM Cortex-M3 microcontroller PIO0_22/I2C0_SCL 37 24 PIO0_16/ADC1_9 PIO0_23/I2C0_SDA 38 23 PIO0_15/ADC1_8 VDD 39 22 PIO0_14/ADC1_7/ SCT1_OUT5 VSS 40 21 PIO0_13/ADC1_6 VSS 41 20 VSS VDD 42 19 PIO0_12/DAC_OUT LPC1517JBD48 PIO0_24/SCT0_OUT6 43 18 PIO0_11/ADC1_3 PIO0_25/ACMP0_I4 44 17 VSSA PIO0_26/ACMP0_I3/ SCT3_OUT3 45 16 VDDA PIO0_27/ACMP_I1 46 15 PIO0_10/ADC1_2 PIO0_28/ACMP1_I3 47 14 VREFP_DAC_VDDCMP PIO0_9/ADC1_1/TDI 12 VREFN 11 VREFP_ADC 10 PIO0_7/ADC0_1 8 PIO0_8/ADC0_0/TDO 9 PIO0_5/ADC0_3 6 PIO0_6/ADC0_2/ SCT2_OUT3 7 PIO0_4/ADC0_4 5 PIO0_3/ADC0_5/ SCT1_OUT4 4 PIO0_2/ADC0_6/ SCT1_OUT3 3 PIO0_1/ADC0_7/ SCT0_OUT4 2 13 PIO0_18/ SCT0_OUT5 PIO0_0/ADC0_10/ SCT0_OUT3 1 PIO0_29/ACMP2_I3/ SCT2_OUT4 48 aaa-009354 Fig 5. LQFP48 pin configuration (without USB) LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 9 of 107 LPC15xx NXP Semiconductors 33 PIO1_4 34 PIO1_5 35 XTALOUT 36 XTALIN 37 VDD 38 PIO1_11 39 PIO0_17/WAKEUP 40 SWCLK/ PIO0_19 41 VBAT 42 RTCXIN 43 RTCXOUT 44 SWDIO/ PIO0_20 45 RESET/PIO0_21 46 PIO1_6 47 USB_DP 48 USB_DM 32-bit ARM Cortex-M3 microcontroller PIO0_22 49 32 PIO0_16 PIO0_23 50 31 PIO0_15 PIO1_7 51 30 PIO0_14 VDD 52 29 PIO0_13 PIO1_8 53 28 PIO1_3 PIO1_9 54 27 VSS VSS 55 26 VSS LPC1549JBD64 LPC1548JBD64 LPC1547JBD64 VSS 56 VDD 57 25 PIO1_2 24 PIO0_12 PIO0_9 16 VREFN 14 PIO1_1 15 PIO0_8 12 VREFP_ADC 13 PIO0_7 11 17 PIO0_18 PIO0_6 10 PIO0_29 64 PIO0_5 9 18 VREFP_DAC_VDDCMP PIO0_4 8 19 PIO0_10 PIO0_28 63 PIO0_3 7 PIO0_27 62 PIO0_2 6 20 VDDA PIO0_1 5 21 VSSA PIO0_26 61 PIO1_0 4 PIO0_25 60 PIO0_0 2 22 VDD PIO0_31 3 23 PIO0_11 PIO1_10 59 PIO0_30 1 PIO0_24 58 aaa-009353 See Table 3 for the full pin name. Fig 6. LQFP64 pin configuration (with USB) LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 10 of 107 LPC15xx NXP Semiconductors 33 PIO1_4 34 PIO1_5 35 XTALOUT 36 XTALIN 37 VDD 38 PIO1_11 39 PIO0_17/WAKEUP 40 SWCLK/ PIO0_19 41 VBAT 42 RTCXIN 43 RTCXOUT 44 SWDIO/ PIO0_20 45 RESET/PIO0_21 46 PIO1_6 47 PIO2_12 48 PIO2_13 32-bit ARM Cortex-M3 microcontroller PIO0_22 49 32 PIO0_16 PIO0_23 50 31 PIO0_15 PIO1_7 51 30 PIO0_14 VDD 52 29 PIO0_13 PIO1_8 53 28 PIO1_3 PIO1_9 54 27 VSS VSS 55 26 VSS LPC1519JBD64 LPC1518JBD64 LPC1517JBD64 VSS 56 VDD 57 24 PIO0_12 PIO0_9 16 VREFN 14 PIO1_1 15 PIO0_8 12 VREFP_ADC 13 17 PIO0_18 PIO0_7 11 PIO0_29 64 PIO0_6 10 18 VREFP_DAC_VDDCMP PIO0_5 9 19 PIO0_10 PIO0_28 63 PIO0_4 8 PIO0_27 62 PIO0_3 7 20 VDDA PIO0_2 6 21 VSSA PIO0_26 61 PIO0_1 5 PIO0_25 60 PIO1_0 4 22 VDD PIO0_0 2 23 PIO0_11 PIO1_10 59 PIO0_31 3 PIO0_24 58 PIO0_30 1 aaa-009376 51 LQFP64 pin configuration (without USB) 75 Fig 7. 25 PIO1_2 76 50 LPC1548JBD100 LPC1518JBD100 25 26 1 100 aaa-009351 Fig 8. LPC15XX Product data sheet LQFP100 pin configuration All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 11 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.2 Pin description Most pins are configurable for multiple functions, which can be analog or digital. Digital inputs can be connected to several peripherals at once, however only one digital output or one analog function can be assigned to any on pin. The pin's connections to internal peripheral blocks are configured by the switch matrix (SWM), the input multiplexer (INPUT MUX), and the SCT Input Pre-processor Unit (SCTIPU). The switch matrix enables certain fixed-pin functions that can only reside on specific pins (see Table 3) and assigns all other pin functions (movable functions) to any available pin (see Table 4), so that the pinout can be optimized for a given application. The input multiplexer provides many choices (pins and internal signals) for selecting the inputs of the SCTimer/PWMs and the frequency measure block. Pins that are connected to the input multiplexer are listed in Table 5. If a pin is selected in the input multiplexer, it is directly connected to the peripheral input without being routed through the switch matrix. Independently of being selected in the input multiplexer, the same pin can also be assigned by the switch matrix to another peripheral input. Four pins can also be connected directly to the SCTIPU and at the same time be inputs to the input multiplexer and the switch matrix (see Table 5). PIO0_1/ADC0_7/ SCT0_OUT4 LQFP100 PIO0_0/ADC0_10/ SCT0_OUT3 LQFP64 Pin description with fixed-pin functions Symbol LQFP48 Table 3. 1 2 2 2 PIO0_2/ADC0_6/ SCT1_OUT3 3 PIO0_3/ADC0_5/ SCT1_OUT4 4 PIO0_4/ADC0_4 5 6 6 8 [2] [2] [2] 5 7 8 10 [2] I; PU I; PU I; PU I; PU 9 14 PIO0_6/ADC0_2/ SCT2_OUT3 7 10 16 [2] 8 11 I; PU 13 6 Product data sheet I; PU [2] PIO0_5/ADC0_3 LPC15XX Description IO PIO0_0 -- General purpose port 0 input/output 0. A ADC0_10 -- ADC0 input 10. O SCT0_OUT3 -- SCTimer0/PWM output 3. IO PIO0_1 -- General purpose port 0 input/output 1. A ADC0_7 -- ADC0 input 7. O SCT0_OUT4 -- SCTimer0/PWM output 4. IO PIO0_2 -- General purpose port 0 input/output 2. ADC0_6 -- ADC0 input 6. [2] PIO0_7/ADC0_1 Reset Type state[1] 17 [2] I; PU I; PU O SCT1_OUT3 -- SCTimer1/PWM output 3. IO PIO0_3 -- General purpose port 0 input/output 3. A ADC0_5 -- ADC0 input 5. O SCT1_OUT4 -- SCTimer1/PWM output 4. IO PIO0_4 -- General purpose port 0 input/output 4. This is the ISP_0 boot pin for the LQFP48 package. A ADC0_4 -- ADC0 input 4. IO PIO0_5 -- General purpose port 0 input/output 5. A ADC0_3 -- ADC0 input 3. IO PIO0_6 -- General purpose port 0 input/output 6. A ADC0_2 -- ADC0 input 2. O SCT2_OUT3 -- SCTimer2/PWM output 3. IO PIO0_7 -- General purpose port 0 input/output 7. A ADC0_1 -- ADC0 input 1. All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 12 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PIO0_8/ADC0_0/TDO LQFP100 Symbol LQFP64 Pin description with fixed-pin functions LQFP48 Table 3. 9 12 19 [2] Reset Type state[1] Description I; PU PIO0_8 -- General purpose port 0 input/output 8. IO In boundary scan mode: TDO (Test Data Out). PIO0_9/ADC1_1/TDI 12 16 24 [2] I; PU A ADC0_0 -- ADC0 input 0. IO PIO0_9 -- General purpose port 0 input/output 9. In boundary scan mode: TDI (Test Data In). PIO0_10/ADC1_2 15 19 28 [2] PIO0_11/ADC1_3 18 23 33 [2] I; PU I; PU A ADC1_1 -- ADC1 input 1. IO PIO0_10 -- General purpose port 0 input/output 10. A ADC1_2 -- ADC1 input 2. IO PIO0_11 -- General purpose port 0 input/output 11. On the LQFP64 package, this pin is assigned to CAN0_RD in ISP C_CAN mode. PIO0_12/DAC_OUT PIO0_13/ADC1_6 19 21 24 29 35 [3] 43 [2] I; PU I; PU A ADC1_3 -- ADC1 input 3. IO PIO0_12 -- General purpose port 0 input/output 12. If this pin is configured as a digital input, the input voltage level must not be higher than VDDA. A DAC_OUT -- DAC analog output. IO PIO0_13 -- General purpose port 0 input/output 13. On the LQFP64 package, this pin is assigned to U0_RXD in ISP USART mode. On the LQFP48 package, this pin is assigned to CAN0_RD in ISP C_CAN mode. PIO0_14/ADC1_7/ SCT1_OUT5 PIO0_15/ADC1_8 22 30 45 [2] I; PU A ADC1_6 -- ADC1 input 6. IO PIO0_14 -- General purpose port 0 input/output 14. On the LQFP48 package, this pin is assigned to U0_RXD in ISP USART mode. 23 31 47 [2] I; PU A ADC1_7 -- ADC1 input 7. O SCT1_OUT5 -- SCTimer1/PWM output 5. IO PIO0_15 -- General purpose port 0 input/output 15. On the LQFP48 package, this pin is assigned to U0_TXD in ISP USART mode. PIO0_16/ADC1_9 24 32 49 [2] I; PU A ADC1_8 -- ADC1 input 8. IO PIO0_16 -- General purpose port 0 input/output 16. On the LQFP48 package, this is the ISP_1 boot pin. PIO0_17/WAKEUP/ TRST 28 39 61 [4] I; PU A ADC1_9 -- ADC1 input 9. IO PIO0_17 -- General purpose port 0 input/output 17. In boundary scan mode: TRST (Test Reset). This pin triggers a wake-up from Deep power-down mode. For wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin. Pull this pin HIGH externally while in Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 13 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PIO0_18/ SCT0_OUT5 LQFP100 Symbol LQFP64 Pin description with fixed-pin functions LQFP48 Table 3. 13 17 26 [5] Reset Type state[1] Description I; PU PIO0_18 -- General purpose port 0 input/output 18. IO On the LQFP64 package, this pin is assigned to U0_TXD in ISP USART mode. On the LQFP48 package, this pin is assigned to CAN0_TD in ISP C_CAN mode. SWCLK/ PIO0_19/TCK 29 40 63 [5] I; PU O SCT0_OUT5 -- SCTimer0/PWM output 5. I SWCLK -- Serial Wire Clock. SWCLK is enabled by default on this pin. In boundary scan mode: TCK (Test Clock). SWDIO/ PIO0_20/SCT1_OUT6/ TMS RESET/PIO0_21 33 44 69 [5] I; PU IO PIO0_19 -- General purpose port 0 input/output 19. I/O SWDIO -- Serial Wire Debug I/O. SWDIO is enabled by default on this pin. In boundary scan mode: TMS (Test Mode Select). 34 45 71 [6] I; PU I/O PIO0_20 -- General purpose port 0 input/output 20. O SCT1_OUT6 -- SCTimer1/PWM output 6. I RESET -- External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO or for any movable function if an external RESET function is not needed and the Deep power-down mode is not used. PIO0_22/I2C0_SCL PIO0_23/I2C0_SDA PIO0_24/SCT0_OUT6 PIO0_25/ACMP0_I4 PIO0_26/ACMP0_I3/ SCT3_OUT3 LPC15XX Product data sheet 37 38 43 44 45 49 50 58 60 61 78 79 [7] [7] 90 [8] 93 [2] 95 [2] IA IA I; PU I; PU I; PU I/O PIO0_21 -- General purpose port 0 input/output 21. IO PIO0_22 -- General purpose port 0 input/output 22 (open-drain) I/O I2C0_SCL -- Open-drain I2C-bus clock input/output. High-current sink if I2C Fast-mode Plus is selected in the I/O configuration register. IO PIO0_23 -- General purpose port 0 input/output 23 (open-drain). I/O I2C0_SDA -- I2C-bus data input/output. High-current sink if I2C Fast-mode Plus is selected in the I/O configuration register. IO PIO0_24 -- General purpose port 0 input/output 24. High-current output driver. O SCT0_OUT6 -- SCTimer0/PWM output 6. IO PIO0_25 -- General purpose port 0 input/output 25. A ACMP0_I4 -- Analog comparator 0 input 4. IO PIO0_26 -- General purpose port 0 input/output 26. A ACMP0_I3 -- Analog comparator 0 input 3. O SCT3_OUT3 -- SCTimer3/PWM output 3. All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 14 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description with fixed-pin functions IO PIO0_27 -- General purpose port 0 input/output 27. A ACMP_I1 -- Analog comparator common input 1. IO PIO0_28 -- General purpose port 0 input/output 28. A ACMP1_I3 -- Analog comparator 1 input 3. IO PIO0_29 -- General purpose port 0 input/output 29. A ACMP2_I3 -- Analog comparator 2 input 3. O SCT2_OUT4 -- SCTimer2/PWM output 4. IO PIO0_30 -- General purpose port 0 input/output 30. A ADC0_11 -- ADC0 input 11. IO PIO0_31 -- General purpose port 0 input/output 31. LQFP100 Description LQFP64 Reset Type state[1] LQFP48 Symbol PIO0_27/ACMP_I1 46 62 97 [2] I; PU PIO0_28/ACMP1_I3 47 63 98 [2] I; PU 100 [2] PIO0_29/ACMP2_I3/ SCT2_OUT4 PIO0_30/ADC0_11 PIO0_31/ADC0_9 48 - 64 1 3 1 [2] 3 [2] I; PU I; PU I; PU On the LQFP64 package, this pin is assigned to CAN0_TD in ISP C_CAN mode. PIO1_0/ADC0_8 - 4 5 [2] I; PU I; PU I; PU PIO1_1/ADC1_0 - 15 23 [2] PIO1_2/ADC1_4 - 25 36 [2] I; PU I; PU PIO1_3/ADC1_5 - 28 41 [2] PIO1_4/ADC1_10 - 33 51 [2] I; PU I; PU PIO1_5/ADC1_11 - 34 52 [2] PIO1_6/ACMP_I2 - 46 73 [2] I; PU I; PU PIO1_7/ACMP3_I4 - 51 81 [2] PIO1_8/ACMP3_I3/ SCT3_OUT4 - 53 84 [2] PIO1_9/ACMP2_I4 - 54 85 [2] I; PU A ADC0_9 -- ADC0 input 9. IO PIO1_0 -- General purpose port 1 input/output 0. A ADC0_8 -- ADC0 input 8. IO PIO1_1 -- General purpose port 1 input/output 1. A ADC1_0 -- ADC1 input 0. IO PIO1_2 -- General purpose port 1 input/output 2. A ADC1_4 -- ADC1 input 4. IO PIO1_3 -- General purpose port 1 input/output 3. A ADC1_5 -- ADC1 input 5. IO PIO1_4 -- General purpose port 1 input/output 4. A ADC1_10 -- ADC1 input 10. IO PIO1_5 -- General purpose port 1 input/output 5. A ADC1_11 -- ADC1 input 11. IO PIO1_6 -- General purpose port 1 input/output 6. A ACMP_I2 -- Analog comparator common input 2. IO PIO1_7 -- General purpose port 1 input/output 7. A ACMP3_I4 -- Analog comparator 3 input 4. IO PIO1_8 -- General purpose port 1 input/output 8. A ACMP3_I3 -- Analog comparator 3 input 3. O SCT3_OUT4 -- SCTimer3/PWM output 4. IO PIO1_9 -- General purpose port 1 input/output 9. On the LQFP64 package, this is the ISP_0 boot pin. A PIO1_10/ACMP1_I4 PIO1_11 - 59 38 91 58 [2] [5] I; PU I; PU ACMP2_I4 -- Analog comparator 2 input 4. IO PIO1_10 -- General purpose port 1 input/output 10. A ACMP1_I4 -- Analog comparator 1 input 4. IO PIO1_11 -- General purpose port 1 input/output 11. On the LQFP64 package, this is the ISP_1 boot pin. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 15 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PIO1_12 LQFP100 Symbol LQFP64 Pin description with fixed-pin functions LQFP48 Table 3. - - 9 Reset Type state[1] Description [5] I; PU IO PIO1_12 -- General purpose port 1 input/output 12. I; PU IO PIO1_13 -- General purpose port 1 input/output 13. I; PU IO PIO1_14 -- General purpose port 1 input/output 14. O SCT0_OUT7 -- SCTimer0/PWM output 7. PIO1_13 - - 11 [5] PIO1_14/SCT0_OUT7 - - 12 [5] 15 [5] I; PU IO PIO1_15 -- General purpose port 1 input/output 15. I; PU IO PIO1_16 -- General purpose port 1 input/output 16. I; PU IO PIO1_17 -- General purpose port 1 input/output 17. O SCT1_OUT7 -- SCTimer1/PWM output 7. PIO1_15 - - PIO1_16 - - 18 [5] PIO1_17/SCT1_OUT7 - - 20 [5] 25 [5] I; PU IO PIO1_18 -- General purpose port 1 input/output 18. I; PU IO PIO1_19 -- General purpose port 1 input/output 19. I; PU IO PIO1_20 -- General purpose port 1 input/output 20. O SCT2_OUT5 -- SCTimer2/PWM output 5. PIO1_18 - - PIO1_19 - - 29 [5] PIO1_20/SCT2_OUT5 - - 34 [5] 37 [5] I; PU IO PIO1_21 -- General purpose port 1 input/output 21. PIO1_21 - - PIO1_22 - - 38 [5] I; PU IO PIO1_22 -- General purpose port 1 input/output 22. PIO1_23 - - 42 [5] I; PU IO PIO1_23 -- General purpose port 1 input/output 23. 44 [5] I; PU IO PIO1_24 -- General purpose port 1 input/output 24. O SCT3_OUT5 -- SCTimer3/PWM output 5. PIO1_24/SCT3_OUT5 - - PIO1_25 - - 46 [5] I; PU IO PIO1_25 -- General purpose port 1 input/output 25. PIO1_26 - - 48 [5] I; PU IO PIO1_26 -- General purpose port 1 input/output 26. 50 [5] I; PU IO PIO1_27 -- General purpose port 1 input/output 27. 55 [5] I; PU IO PIO1_28 -- General purpose port 1 input/output 28. PIO1_27 PIO1_28 - - PIO1_29 - - 56 [5] I; PU IO PIO1_29 -- General purpose port 1 input/output 29. PIO1_30 - - 59 [5] I; PU IO PIO1_30 -- General purpose port 1 input/output 30. 60 [5] I; PU IO PIO1_31 -- General purpose port 1 input/output 31. 62 [5] I; PU IO PIO2_0 -- General purpose port 2 input/output 0. PIO1_31 PIO2_0 - - PIO2_1 - - 64 [5] I; PU IO PIO2_1 -- General purpose port 2 input/output 1. PIO2_2 - - 72 [5] I; PU IO PIO2_2 -- General purpose port 2 input/output 2. 76 [5] I; PU IO PIO2_3 -- General purpose port 2 input/output 3. 77 [5] I; PU IO PIO2_4 -- General purpose port 2 input/output 4. I; PU IO I; PU IO PIO2_3 PIO2_4 - - On the LQFP100 package, this is the ISP_1 boot pin. PIO2_5 - - 80 [5] PIO2_6 - - 82 [5] PIO2_5 -- General purpose port 2 input/output 5. On the LQFP100 package, this is the ISP_0 boot pin. PIO2_6 -- General purpose port 2 input/output 6. On the LQFP100 package, this pin is assigned to U0_TXD in ISP USART mode. PIO2_7 - - 86 [5] I; PU IO PIO2_7 -- General purpose port 2 input/output 7. On the LQFP100 package, this pin is assigned to U0_RXD in ISP USART mode. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 16 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PIO2_8 LQFP100 Symbol LQFP64 Pin description with fixed-pin functions LQFP48 Table 3. - - 92 [5] Reset Type state[1] Description I; PU PIO2_8 -- General purpose port 2 input/output 8. IO On the LQFP100 package, this pin is assigned to CAN0_TD in ISP C_CAN mode. PIO2_9 - - 94 [5] I; PU IO PIO2_9 -- General purpose port 2 input/output 9. On the LQFP100 package, this pin is assigned to CAN0_RD in ISP C_CAN mode. PIO2_10 - - 96 [5] I; PU IO PIO2_10 -- General purpose port 2 input/output 10. PIO2_11 - - 99 [5] I; PU IO PIO2_11 -- General purpose port 2 input/output 11. PIO2_12 35 47 74 [5] I; PU IO PIO2_12 -- General purpose port 2 input/output 12. On parts LPC1519/17/18 only. PIO2_13 36 48 75 [5] I; PU IO PIO2_13 -- General purpose port 2 input/output 13. On parts LPC1519/17/18 only. USB_DP 35 47 74 [10] - IO USB bidirectional D+ line. Pad includes internal 33 series termination resistor. On parts LPC1549/48/47 only. USB_DM 36 48 75 [10] - IO USB bidirectional D line. Pad includes internal 33 series termination resistor. On parts LPC1549/48/47 only. RTCXIN 31 42 66 [9] - RTC oscillator input. This input should be grounded if the RTC is not used. RTCXOUT 32 43 67 [9] - RTC oscillator output. 54 [9] - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. - Output from the oscillator amplifier. XTALIN 26 36 [11] XTALOUT 25 35 53 [9] [11] VBAT 30 41 65 - Battery supply voltage. Supplies power to the RTC. If no battery is used, tie VBAT to VDD or to ground. VDDA 16 20 30 - Analog supply voltage. VDD and the analog reference voltages VREFP_ADC and VREFP_DAC_VDDCMP must not exceed the voltage level on VDDA. VDDAshould typically be the same voltages as VDD but should be isolated to minimize noise and error. VDDA should be tied to VDD if the ADC is not used. VDD 39, 27, 42 22, 52, 37, 57 4, 32, 70, 83, 57, 89 - 3.3 V supply voltage (2.4 V to 3.6 V). The voltage level on VDD must be equal or lower than the analog supply voltage VDDA. VREFP_DAC_VDDCMP 14 18 27 - DAC positive reference voltage and analog comparator reference voltage. The voltage level on VREFP_DAC_VDDCMP must be equal to or lower than the voltage applied to VDDA. VREFN 14 22 - ADC and DAC negative voltage reference. If the ADC is not used, tie VREFN to VSS. LPC15XX Product data sheet 11 [9] All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 17 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP64 LQFP100 Pin description with fixed-pin functions LQFP48 Table 3. Symbol Reset Type state[1] Description VREFP_ADC 10 13 21 - ADC positive reference voltage. The voltage level on VREFP_ADC must be equal to or lower than the voltage applied to VDDA. If the ADC is not used, tie VREFP_ADC to VDD. VSSA 17 21 31 - Analog ground. VSSAshould typically be the same voltage as VSS but should be isolated to minimize noise and error. VSSA should be tied to VSS if the ADC is not used. VSS 41, 20, 40 56, 26, 27, 55 88, 7, 39, 40, 68, 87 - Ground. [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled; F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption. [2] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as analog input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin includes a 10 ns on/off glitch filter. By default, the glitch filter is turned on. [3] This pin is not 5 V tolerant due to special analog functionality. When configured for a digital function, this pin is 3 V tolerant and provides standard digital I/O functions with configurable internal pull-up and pull-down resistors and hysteresis. When configured for DAC_OUT, the digital section of the pin is disabled and this pin is a 3 V tolerant analog output. This pin includes a 10 ns on/off glitch filter. By default, the glitch filter is turned on. [4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, and configurable hysteresis. This pin includes a 10 ns on/off glitch filter. By default, the glitch filter is turned on. This pin is powered in deep power-down mode and can wake up the part. The wake-up pin function can be disabled and the pin can be used for other purposes, if the RTC is enabled for waking up the part from Deep power-down mode. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. [6] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. [7] I2C-bus pin compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [8] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver. [9] Special analog pin. [10] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. [11] When the main oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. Table 4. LPC15XX Product data sheet Movable functions Function name Type Description U0_TXD O Transmitter output for USART0. U0_RXD I Receiver input for USART0. U0_RTS O Request To Send output for USART0. U0_CTS I Clear To Send input for USART0. U0_SCLK I/O Serial clock input/output for USART0 in synchronous mode. All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 18 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. LPC15XX Product data sheet Movable functions ...continued Function name Type Description U1_TXD O Transmitter output for USART1. U1_RXD I Receiver input for USART1. U1_RTS O Request To Send output for USART1. U1_CTS I Clear To Send input for USART1. U1_SCLK I/O Serial clock input/output for USART1 in synchronous mode. U2_TXD O Transmitter output for USART2. U2_RXD I Receiver input for USART2. U2_SCLK I/O Serial clock input/output for USART1 in synchronous mode. SPI0_SCK I/O Serial clock for SPI0. SPI0_MOSI I/O Master Out Slave In for SPI0. SPI0_MISO I/O Master In Slave Out for SPI0. SPI0_SSEL0 I/O Slave select 0 for SPI0. SPI0_SSEL1 I/O Slave select 1 for SPI0. SPI0_SSEL2 I/O Slave select 2 for SPI0. SPI0_SSEL3 I/O Slave select 3 for SPI0. SPI1_SCK I/O Serial clock for SPI1. SPI1_MOSI I/O Master Out Slave In for SPI1. SPI1_MISO I/O Master In Slave Out for SPI1. SPI1_SSEL0 I/O Slave select 0 for SPI1. SPI1_SSEL1 I/O Slave select 1 for SPI1. CAN0_TD O CAN0 transmit. CAN0_RD I CAN0 receive. USB_VBUS I USB VBUS. SCT0_OUT0 O SCTimer0/PWM output 0. SCT0_OUT1 O SCTimer0/PWM output 1. SCT0_OUT2 O SCTimer0/PWM output 2. SCT1_OUT0 O SCTimer1/PWM output 0. SCT1_OUT1 O SCTimer1/PWM output 1. SCT1_OUT2 O SCTimer1/PWM output 2. SCT2_OUT0 O SCTimer2/PWM output 0. SCT2_OUT1 O SCTimer2/PWM output 1. SCT2_OUT2 O SCTimer2/PWM output 2. SCT3_OUT0 O SCTimer3/PWM output 0. SCT3_OUT1 O SCTimer3/PWM output 1. SCT3_OUT2 O SCTimer3/PWM output 2. SCT_ABORT0 I SCT abort 0. SCT_ABORT1 I SCT abort 1. ADC0_PINTRIG0 I ADC0 external pin trigger input 0. ADC0_PINTRIG1 I ADC0 external pin trigger input 1. ADC1_PINTRIG0 I ADC1 external pin trigger input 0. ADC1_PINTRIG1 I ADC1 external pin trigger input 1. All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 19 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Movable functions ...continued Function name Type Description DAC_PINTRIG I DAC external pin trigger input. DAC_SHUTOFF I DAC shut-off external input. ACMP0_O O Analog comparator 0 output. ACMP1_O O Analog comparator 1 output. ACMP2_O O Analog comparator 2 output. ACMP3_O O Analog comparator 3 output. CLKOUT O Clock output. ROSC O Analog comparator ring oscillator output. ROSC_RESET I Analog comparator ring oscillator reset. USB_FTOGGLE O USB frame toggle. Do not assign this function to a pin until a USB device is connected and the first SOF interrupt has been received by the device. QEI_PHA I QEI phase A input. QEI_PHB I QEI phase B input. QEI_IDX I QEI index input. GPIO_INT_BMAT O Output of the pattern match engine. SWO O Serial wire output. LQFP48 LQFP100 Pins connected to the INPUT multiplexer and SCT IPU Symbol LQFP64 Table 5. Description PIO0_2/ADC0_6/SCT1_OUT3 3 6 8 SCT0 input multiplexer PIO0_3/ADC0_5/SCT1_OUT4 4 7 10 SCT0 input multiplexer PIO0_4/ADC0_4 5 8 13 SCT2 input multiplexer PIO0_5/ADC0_3 6 9 14 FREQMEAS PIO0_7/ADC0_1 8 11 17 SCT3 input multiplexer PIO0_14/ADC1_7/SCT1_OUT5 22 30 45 SCTIPU input SAMPLE_IN_A0 PIO0_15/ADC1_8 23 31 47 SCT1 input multiplexer PIO0_16/ADC1_9 24 32 49 SCT1 input multiplexer PIO0_17/WAKEUP/TRST 28 39 61 SCT0 input multiplexer SWCLK/PIO0_19/TCK 29 40 63 FREQMEAS RESET/PIO0_21 34 45 71 SCT1 input multiplexer PIO0_25/ACMP0_I4 44 60 93 SCTIPU input SAMPLE_IN_A1 PIO0_27/ACMP_I1 46 62 97 SCT2 input multiplexer PIO0_30/ADC0_11 - 1 1 FREQMEAS SCT0 input multiplexer LPC15XX Product data sheet PIO0_31/ADC0_9 - 3 3 SCT1 input multiplexer PIO1_4/ADC1_10 - 33 51 SCT1 input multiplexer PIO1_5/ADC1_11 - 34 52 SCT1 input multiplexer PIO1_6/ACMP_I2 - 46 73 SCT0 input multiplexer All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 20 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP64 LQFP100 Pins connected to the INPUT multiplexer and SCT IPU LQFP48 Table 5. Symbol Description PIO1_7/ACMP3_I4 - 51 81 SCT0 input multiplexer PIO1_11 - 38 58 SCT3 input multiplexer SCTIPU input SAMPLE_IN_A2 PIO1_12 - - 9 SCT0 input multiplexer PIO1_13 - - 11 SCT0 input multiplexer PIO1_15 - - 12 SCT1 input multiplexer PIO1_16 - - 18 SCT1 input multiplexer PIO1_18 - - 25 SCT2 input multiplexer PIO1_19 - - 29 SCT2 input multiplexer PIO1_21 - - 37 SCT3 input multiplexer PIO1_22 - - 38 SCT3 input multiplexer PIO1_26 - - 48 SCTIPU input SAMPLE_IN_A3 PIO1_27 - - 50 FREQMEAS 8. Functional description 8.1 ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware division, hardware single-cycle multiply, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual, which is available on the official ARM website. 8.2 Memory Protection Unit (MPU) The LPC15xx have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 21 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to eight regions each of which can be divided into eight subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. 8.3 On-chip flash programming memory The LPC15xx contain up to 256 kB on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip boot loader software. Flash updates via USB are supported as well. The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages. Individual pages of 256 byte each can be erased using the IAP erase page command. 8.3.1 ISP pin configuration The LPC15xx supports ISP via the USART0, C_CAN, or USB interfaces. The ISP mode is determined by the state of two pins (ISP_0 and ISP_1) at boot time: Table 6. ISP modes Boot mode ISP_0 ISP_1 Description No ISP HIGH HIGH ISP bypassed. Part attempts to boot from flash. If the user code in flash is not valid, then enters ISP via USB. C_CAN HIGH LOW Part enters ISP via C_CAN. USB LOW HIGH Part enters ISP via USB. USART0 LOW LOW Part enters ISP via USART0. The ISP pin assignment is different for each package, so that the fewest functions possible are blocked. No more than four pins must be set aside for entering ISP in any ISP mode. The boot code assigns two ISP pins for each package, which are probed when the part boots to determine whether or not to enter ISP mode. Once the ISP mode has been determined, the boot loader configures the necessary serial pins for each package. Pins which are not configured by the boot loader for the selected boot mode (for example CAN0_RD and CAN0_TD in USART mode) can be assigned to any function through the switch matrix. Table 7. Pin assignments for ISP modes Boot pin LQFP48 LQFP64 LQFP100 ISP_0 PIO0_4 PIO1_9 PIO2_5 ISP_1 PIO0_16 PIO1_11 PIO2_4 U0_TXD PIO0_15 PIO0_18 PIO2_6 U0_RXD PIO0_14 PIO0_13 PIO2_7 CAN0_TD PIO0_18 PIO0_31 PIO2_8 CAN0_RD PIO0_13 PIO0_11 PIO2_9 PIO0_16 PIO1_11 PIO2_4 USART mode C_CAN mode USB mode USB_VBUS (same as ISP_1) LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 22 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.4 EEPROM The LPC15xx contain 4 kB of on-chip byte-erasable and byte-programmable EEPROM data memory. The EEPROM can be programmed using In-Application Programming (IAP) via the on-chip boot loader software. 8.5 SRAM The LPC15xx contain a total 36 kB, 20 kB or 12 kB of contiguous, on-chip static RAM memory. For each SRAM configuration, the SRAM is divided into three blocks: 2 x 16 kB + 4 kB for 36 kB SRAM, 2 x 8 kB + 4 kB for 20 kB SRAM, and 2 x 4 kB + 4 kB for 12 kB SRAM. The bottom 16 kB, 8 kB, or 4 kB are enabled by the bootloader and cannot be disabled. The next two SRAM blocks in each configuration can be disabled or enabled individually in the SYSCON block to save power. Table 8. LPC15xx SRAM configurations SRAM0 SRAM1 SRAM2 LPC1549/19 (total SRAM = 36 kB) address range 0x0200 0000 to 0x0200 3FFF 0x0200 4000 to 0x0200 7FFF 0x0200 8000 to 0x0200 8FFF size 16 kB 16 kB 4 kB control cannot be disabled disable/enable disable/enable default enabled enabled enabled LPC1548/18 (total SRAM = 20 kB) address range 0x0200 0000 to 0x0200 1FFF 0x0200 2000 to 0x0200 3FFF 0x0200 4000 to 0x0200 4FFF size 8 kB 8 kB 4 kB control cannot be disabled disable/enable disable/enable default enabled enabled enabled LPC1547/17 (total SRAM = 12 kB) address range 0x0200 0000 to 0x0200 0FFF 0x0200 1000 to 0x0200 1FFF 0x0200 2000 to 0x0200 2FFF size 4 kB 4 kB 4 kB control cannot be disabled disable/enable disable/enable default enabled enabled enabled 8.6 On-chip ROM The on-chip ROM contains the boot loader and the following Application Programming Interfaces (APIs): * In-System Programming (ISP) and In-Application Programming (IAP) support for flash including IAP erase page command. * * * * * LPC15XX Product data sheet IAP support for EEPROM. Flash updates via USB and C_CAN supported. USB API (HID, CDC, and MSC drivers). DMA, I2C, USART, SPI, and C_CAN drivers. Power profiles for configuring power consumption and PLL settings. All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 23 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller * Power mode configuration for configuring deep-sleep, power-down, and deep power-down modes. * ADC drivers for analog-to-digital conversion and ADC calibration. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 24 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.7 AHB multilayer matrix TEST/DEBUG INTERFACE ARM CORTEX-M3 System bus I-code bus USB DMA masters D-code bus slaves FLASH SRAM0 SRAM1 SRAM2 ROM EEPROM HS GPIO SCTIMER0/PWM SCTIMER1/PWM SCTIMER2/PWM SCTIMER3/PWM CRC AHB-TO-APB BRIDGE0 WWDT SWM PMU SPI1 AHB MULTILAYER MATRIX ACMP DAC ADC0 INPUT MUX USART1 I2C0 QEI USART2 RTC SPI0 SYSCON AHB-TO-APB BRIDGE1 RIT PINT MRT ADC1 SCTIPU IOCON FLASH CTRL GINT0 GINT1 USART2 C_CAN EEPROM CTRL = master-slave connection aaa-010870 Fig 9. AHB multilayer matrix LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 25 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.8 Memory map APB peripherals 0x400F 0000 31 EEPROM CTRL 30 IOCON 29 reserved 28 C_CAN 27 reserved 26 reserved 0xE010 0000 25:17 reserved 0xE000 0000 16 USART2 15 flash ctrl FMC 14 SCTIPU 13 RIT 12 reserved 11 GINT1 10 GINT0 9 PINT 8 MRT LPC15xx 4 GB 0xFFFF FFFF reserved private peripheral bus reserved 0x400F 0000 APB peripherals 1 0x4008 0000 APB peripherals 0 0x4000 0000 reserved 0x1C02 8000 SCTimer3/PWM 0x1C02 4000 SCTimer2/PWM SCTimer1/PWM SCTimer0/PWM reserved CRC USB reserved DMA GPIO reserved 0x400E 8000 0x400C 4000 0x400C 0000 0x400B 4000 0x400B 0000 0x400A C000 0x400A 8000 0x400A 4000 0x400A 0000 reserved 31:30 reserved 29 SYSCON 28:23 reserved 0x4008 4000 ADC1 0x4008 0000 0x4008 0000 0x4007 8000 22 QEI 0x1C00 C000 21 reserved 0x1C00 8000 20 I2C0 0x1C00 4000 19 SPI1 0x1C00 0000 18 SPI0 17 USART1 16 USART0 15 PMU 14 switch matrix SWM 0x4005 8000 0x4005 4000 0x4005 0000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 reserved 0x0300 8000 13:12 0x0300 0000 11 WWDT 10 RTC 9:7 reserved 6 reserved 5 INPUT MUX 0x0200 9000 36 kB SRAM (LPC1549/19) 0x0200 5000 20 kB SRAM (LPC1548/18) 0x4002 C000 0x4002 8000 0x4001 C000 0x4001 8000 4:3 0x0200 0000 2 analog comparators ACMP 1 DAC 0 ADC0 reserved 0x0004 0000 reserved 256 kB flash 0x4003 8000 0x4003 0000 0x0200 3000 12 kB SRAM (LPC1547/17) 0x4007 4000 0x4005 C000 0x1C01 0000 0x0320 0000 0x400B C000 0x400B 8000 0x1C01 8000 reserved 0x4001 4000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000 0x0000 00C0 active interrupt vectors 0 GB 0x400E C000 0 reserved 32 kB boot ROM 0x400F 0000 0x1C01 C000 0x0320 1000 4 kB EEPROM 0x400F 4000 7:1 0x1000 0000 reserved 0x400F 8000 0x1C02 0000 0x1C01 4000 0x400F C000 0x0000 0000 0x0000 0000 aaa-010871 See Section 8.5 "SRAM" for SRAM configuration. Fig 10. Memory map LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 26 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.9 Nested Vectored Interrupt controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.9.1 Features * * * * * * * * Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3. Tightly coupled interrupt controller provides low interrupt latency. Controls system exceptions and peripheral interrupts. The NVIC supports 47 vectored interrupts. Eight programmable interrupt priority levels with hardware priority level masking. Software interrupt generation using the ARM exceptions SVCall and PendSV. Support for NMI. ARM Cortex-M3 Vector table offset register VTOR implemented. 8.9.2 Interrupt sources Typically, each peripheral device has one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source. 8.10 IOCON block The IOCON block configures the electrical properties of the pins such as pull-up and pull-down resistors, hysteresis, open-drain modes and input filters. Remark: The pin function and whether the pin operates in digital or analog mode are entirely under the control of the switch matrix. Enabling an analog function through the switch matrix disables the digital pad. However, the internal pull-up and pull-down resistors as well as the pin hysteresis must be disabled to obtain an accurate reading of the analog input. 8.10.1 Features * Programmable pull-up, pull-down, or repeater mode. * All pins (except PIO0_22 and PIO0_23) are pulled up to 3.3 V (VDD = 3.3 V) if their pull-up resistor is enabled. * Programmable pseudo open-drain mode. * Programmable (on/off) 10 ns glitch filter on 36 pins (PIO0_0 to PIO0_17, PIO0_25 to PIO0_31, PIO1_0 to PIO1_10). The glitch filter is turned on by default. * Programmable hysteresis. * Programmable input inverter. * Digital filter with programmable filter constant on all pins. 8.10.2 Standard I/O pad configuration Figure 11 shows the possible pin modes for standard I/O pins with analog input function: LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 27 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller * * * * * * * Digital output driver with configurable open-drain output Digital input: Weak pull-up resistor (PMOS device) enabled/disabled Digital input: Weak pull-down resistor (NMOS device) enabled/disabled Digital input: Repeater mode enabled/disabled Digital input: Input digital filter configurable on all pins Digital input: Input glitch filter enabled/disabled on select pins Analog input VDD VDD open-drain enable strong pull-up output enable ESD data output PIN pin configured as digital output driver strong pull-down ESD VSS VDD weak pull-up pull-up enable weak pull-down repeater mode enable pull-down enable PROGRAMMABLE DIGITAL FILTER data input pin configured as digital input 10 ns GLITCH FILTER select data inverter select glitch filter select analog input analog input pin configured as analog input aaa-010776 Fig 11. Standard I/O pin configuration 8.11 Switch Matrix (SWM) The switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowing to connect many functions like the USART, SPI, SCT, and I2C functions to any pin that is not power or ground. These functions are called movable functions and are listed in Table 4. Functions that need specialized pads like the ADC or analog comparator inputs can be enabled or disabled through the switch matrix. These functions are called fixed-pin functions and cannot move to other pins. The fixed-pin functions are listed in Table 3. If a fixed-pin function is disabled, any other movable function can be assigned to this pin. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 28 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.12 Fast General-Purpose parallel I/O (GPIO) Device pins that are not connected to a specific peripheral function through the switch matrix are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC15xx use accelerated GPIO functions. * An entire port value can be written in one instruction. * Mask, set, and clear operations are supported for the entire port. 8.12.1 Features * Bit level port registers allow a single instruction to set and clear any number of bits in one write operation. * Direction control of individual bits. 8.13 Pin interrupt/pattern match engine (PINT) The pin interrupt block configures up to eight pins from the digital pins on ports 1 and 2 for providing eight external interrupts connected to the NVIC. The input multiplexer block is used to select the pins. The pattern match engine can be used, in conjunction with software, to create complex state machines based on pin inputs. Any digital pin on ports 0 and 1 can be configured through the SYSCON block as input to the pin interrupt or pattern match engine. The registers that control the pin interrupt or pattern match engine are located on the IO+ bus for fast single-cycle access. 8.13.1 Features * Pin interrupts - Up to eight pins can be selected from all digital pins on ports 0 and 1 as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC. - Edge-sensitive interrupt pins can interrupt on rising or falling edges or both. - Level-sensitive interrupt pins can be HIGH- or LOW-active. - Pin interrupts can wake up the part from sleep mode, deep-sleep mode, and power-down mode. * Pin interrupt pattern match engine - Up to 8 pins can be selected from all digital pins on ports 0 and 1 to contribute to a boolean expression. The boolean expression consists of specified levels and/or transitions on various combinations of these pins. - Each minterm (product term) comprising the specified boolean expression can generate its own, dedicated interrupt request. - Any occurrence of a pattern match can be programmed to also generate an RXEV notification to the ARM CPU. - The pattern match engine does not facilitate wake-up. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 29 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.14 GPIO group interrupts (GINT0/1) The GPIO pins can be used in several ways to set pins as inputs or outputs and use the inputs as combinations of level and edge sensitive interrupts. For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks (GINT0 and GINT1), the GPIO grouped interrupt registers determine which pins are enabled to generate interrupts and what the active polarities of each of those inputs are. The GPIO grouped interrupt registers also select whether the interrupt output will be level or edge triggered and whether it will be based on the OR or the AND of all of the enabled inputs. When the designated pattern is detected on the selected input pins, the GPIO grouped interrupt block generates an interrupt. If the part is in a power-savings mode, it first asynchronously wakes the part up prior to asserting the interrupt request. The interrupt request line can be cleared by writing a one to the interrupt status bit in the control register. 8.14.1 Features * Two group interrupts are supported to reflect two distinct interrupt patterns. * The inputs from any number of digital pins can be enabled to contribute to a combined group interrupt. * The polarity of each input enabled for the group interrupt can be configured HIGH or LOW. * Enabled interrupts can be logically combined through an OR or AND operation. * The grouped interrupts can wake up the part from sleep, deep-sleep or power-down modes. 8.15 DMA controller The DMA controller can access all memories and the USART, SPI, I2C, and DAC peripherals using DMA requests. DMA transfers can also be triggered by internal events like the ADC interrupts, the SCT DMA request signals, or the analog comparator outputs. 8.15.1 Features * 18 channels with 14 channels connected to peripheral request inputs. * DMA operations can be triggered by on-chip events. Each DMA channel can select one trigger input from 24 sources through the input multiplexer. * * * * * * LPC15XX Product data sheet Priority is user selectable for each channel. Continuous priority arbitration. Address cache with four entries. Efficient use of data bus. Supports single transfers up to 1,024 words. Address increment options allow packing and/or unpacking data. All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 30 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.16 Input multiplexing (Input mux) The input multiplexer allows to select from multiple external and internal sources for the SCT inputs, DMA trigger inputs, and the frequency measure block. The input multiplexer is implemented as a register interface with one source selection register for each input. The input multiplexer can for example connect SCT outputs, the ADC interrupts, or the comparator outputs to the SCT inputs and thus enables the SCT to use a large variety of events to control the timing operation. The ADCs and analog comparators also support input multiplexing using source selection registers as part of their configuration registers. 8.17 USB interface Remark: The USB interface is available on parts LPC1549/48/47 only. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot-plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The USB interface consists of a full-speed device controller with on-chip PHY (PHYsical layer) for device functions. Remark: Configure the part in default power mode with the power profiles before using the USB (see Section 8.40.1). Do not use the USB when the part runs in performance, efficiency, or low-power mode. 8.17.1 Full-speed USB device controller The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, and endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. 8.17.1.1 Features * * * * * * Dedicated USB PLL available. Fully compliant with USB 2.0 specification (full speed). Supports 10 physical (5 logical) endpoints including one control endpoint. Single and double buffering supported. Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types. Supports wake-up from Deep-sleep mode and Power-down mode on USB activity and remote wake-up. * Supports SoftConnect functionality through internal pull-up resistor. * Internal 33 series termination resistors on USB_DP and USB_DM lines eliminate the need for external series resistors. * Supports Link Power Management (LPM). LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 31 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.18 USART0/1/2 Remark: All USART functions are movable functions and are assigned to pins through the switch matrix. Do not connect USART functions to the open-drain pins PIO0_22 and PIO0_23. Interrupts generated by the USART peripherals can wake up the part from Deep-sleep and power-down modes if the USART is in synchronous mode, the 32 kHz mode is enabled, or the CTS interrupt is enabled. 8.18.1 Features * Maximum bit rates of 4.5 Mbit/s in asynchronous mode, 15 Mbit/s in synchronous mode master mode, and 18 Mbit/s in synchronous slave mode. * 7, 8, or 9 data bits and 1 or 2 stop bits. * Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option. * * * * * * * Multiprocessor/multidrop (9-bit) mode with software address compare. * * * * * * Received data and status can optionally be read from a single register RS-485 transceiver output enable. Autobaud mode for automatic baud rate detection Parity generation and checking: odd, even, or none. Software selectable oversampling from 5 to 16 clocks in asynchronous mode. One transmit and one receive data buffer. RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output. Break generation and detection. Receive data is 2 of 3 sample "voting". Status flag set when one sample differs. Built-in Baud Rate Generator with auto-baud function. A fractional rate divider is shared among all USARTs. Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected. * Loopback mode for testing of data and flow control. * In synchronous slave mode, wakes up the part from deep-sleep and power-down modes. * Special operating mode allows operation at up to 9600 baud using the 32 kHz RTC oscillator as the UART clock. This mode can be used while the device is in Deep-sleep or Power-down mode and can wake-up the device when a character is received. * USART transmit and receive functions work with the system DMA controller. 8.19 SPI0/1 All SPI functions are movable functions and are assigned to pins through the switch matrix. Do not connect SPI functions to the open-drain pins PIO0_22 and PIO0_23. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 32 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.19.1 Features * Maximum data rates of 17 Mbit/s in master mode and slave mode for SPI functions connected to all digital pins except PIO0_22 and PIO0_23. * Data transmits of 1 to 16 bits supported directly. Larger frames supported by software. * Master and slave operation. * Data can be transmitted to a slave without the need to read incoming data. This can be useful while setting up an SPI memory. * Control information can optionally be written along with data. This allows very versatile operation, including "any length" frames. * Up to four Slave Select input/outputs with selectable polarity and flexible usage. * Supports DMA transfers: SPIn transmit and receive functions work with the system DMA controller. Remark: Texas Instruments SSI and National Microwire modes are not supported. 8.20 I2C-bus interface The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. The I2C-bus functions are fixed-pin functions and must be enabled through the switch matrix on the open-drain pins PIO0_22 and PIO0_23. 8.20.1 Features * Supports standard and fast mode with data rates of up to 400 kbit/s. * Supports Fast-mode Plus with bit rates up to 1 Mbit/s. * Fail-safe operation: When the power to an I2C-bus device is switched off, the SDA and SCL pins connected to the I2C-bus are floating and do not disturb the bus. * * * * Independent Master, Slave, and Monitor functions. Supports both Multi-master and Multi-master with Slave functions. Multiple I2C slave addresses supported in hardware. One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C bus addresses. * 10-bit addressing supported with software assist. * Supports SMBus. * Supported by on-chip ROM API. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 33 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.21 C_CAN Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B. The C_CAN controller can build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a high level of reliability. The C_CAN functions are movable functions and are assigned to pins through the switch matrix. Do not connect C_CAN functions to the open-drain pins PIO0_22 and PIO0_23. 8.21.1 Features * * * * * * * Conforms to protocol version 2.0 parts A and B. Supports bit rate of up to 1 Mbit/s. Supports 32 Message Objects. Each Message Object has its own identifier mask. Provides programmable FIFO mode (concatenation of Message Objects). Provides maskable interrupts. Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN applications. * Provides programmable loop-back mode for self-test operation. 8.22 PWM/timer/motor control subsystem The SCTimer/PWMs (State Configurable Timer/Pulse Width Modulators) and the analog peripherals support multiple ways of interconnecting their inputs and outputs and of interfacing to the pins and the DMA controller. Using the highly flexible and programmable connection scheme makes it easy to configure various subsystems for motor control and complex timing and tracking applications. Specifically, the inputs to the SCTs and the trigger inputs of the ADCs and DMA are selected through the input multiplexer which offers a choice of many possible sources for each input or trigger. SCT outputs are assigned to pins through the switch matrix allowing for many pinout solutions. 8.22.1 SCtimer/PWM subsystem The SCTimer/PWMs can be configured to build a PWM controller with multiple outputs by programming the MATCH and MATCHRELOAD registers to control the base frequency and the duty cycle of each SCTimer/PWM output. More complex waveforms that span multiple counter cycles or change behavior across or within counter cycles can be generated using the state capability built into the SCTimer/PWMs. Combining the PWM functions with the analog functions, the PWM output can react to control signals like comparator outputs or the ADC interrupts. The SCT IPU adds emergency shut-down functions and pre-processing of controlling events. For an overview of the PWM subsystem, see Figure 12 "PWM-Analog subsystem". For high-speed PWM functionality, use only outputs that are fixed-pin functions to minimize pin-to-pin differences in output skew. See also Table 22 "SCTimer/PWM output dynamic characteristics". This reduces the number of PWM outputs to five for each large SCT. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 34 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller digital signal from/to pins analog peripheral analog signal from/to pins digital peripheral digital signal internal analog signal internal ANALOG IN TRIGGER SWITCH MATRIX THRESHOLD CROSSING INTERRUPTS ADC0/ADC1 4 VDDA DIVIDER TEMP SENSOR VOLTAGE REFERENCE SCT0 MATCH/ MATCHRELOAD OUTPUTS 8 x PWM OUT TIMER0 SCT1 MATCH/ MATCHRELOAD OUTPUTS 8 x PWM OUT TIMER1 TIMER2 SCT2 MATCH/ MATCHRELOAD OUTPUTS TIMER3 SCT3 MATCH/ MATCHRELOAD OUTPUTS 6 x PWM OUT ACMP0 ACMP1 ACMP2 ACMP3 OUTPUTS ANALOG IN SCT IPU 6 x PWM OUT SWITCH MATRIX INPUT MUX SCT0/1/2/3 aaa-010873 Fig 12. PWM-Analog subsystem 8.22.2 Timer controlled subsystem The timers, the analog components, and the DMA can be configured to form a subsystem that can run independently of the main processor under the control of the SCTs and any events that are generated by the A/D converters, the comparators, the SCT output themselves, or the external pins. A/D conversions can be triggered by the timer outputs, the comparator outputs or by events from external pins. Data can be transferred from the ADCs to memory using the DMA controller, and the DMA transfers can be triggered by the ADCs, the comparator outputs, or by the timer outputs. For an overview of the subsystem, see Figure 13 "Subsystem with timers, switch matrix, DMA, and analog components". LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 35 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller analog peripheral analog signal from/to pins digital peripheral INPUT MUX DMA digital signal from/to pins digital signal internal analog signal internal 4 VOLTAGE REFERENCE SCT IPU INPUT MUX TEMP SENSOR TIMER1 (SCT1) TIMER2 (SCT2) NVIC OUTPUTS TIMER0 (SCT0) VDDA DIVIDER THRESHOLD CROSSING INTERRUPTS TRIGGER SWITCH MATRIX ANALOG IN ADC0/ADC1 SWITCH MATRIX ACMP0 ACMP1 ACMP2 ACMP3 OUTPUTS ANALOG IN TIMER3 (SCT3) DAC_SHUTOFF DAC aaa-010874 Fig 13. Subsystem with timers, switch matrix, DMA, and analog components 8.22.3 SCTimer/PWM in the large configuration (SCT0/1) Remark: For applications that require exact timing of the SCT outputs (for example PWM), assign the outputs only to fixed-pin functions to ensure that the output skew is nearly the same for all outputs. 8.22.3.1 Features The following feature list summarizes the configuration for the two large SCTs. Each large SCT has a companion small SCT (see Section 8.22.4) with fewer inputs and outputs and a reduced feature set. * Each SCT supports: - 16 match/capture registers - 16 events - 16 states - Match register 0 to 5 support a fractional component for the dither engine LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 36 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller - 8 inputs and 10 outputs - DMA support * Counter/timer features: - Configurable as two 16-bit counters or one 32-bit counter. - Counters clocked by system clock or selected input. - Configurable as up counters or up-down counters. - Configurable number of match and capture registers. Up to 16 match and capture registers total. - Upon match create the following events: stop, halt, limit counter or change counter direction; toggle outputs; create an interrupt; change the state. - Counter value can be loaded into capture register triggered by match or input/output toggle. * PWM features: - Counters can be used in conjunction with match registers to toggle outputs and create time-proportioned PWM signals. - Up to eight single-edge or dual-edge controlled PWM outputs with up to eight independent duty cycles when configured as 32-bit timers. * Event creation features: - The following conditions define an event: a counter match condition, an input (or output) condition such as an rising or falling edge or level, a combination of match and/or input/output condition. - Events can only have an effect while the counter is running. - Selected events can limit, halt, start, or stop a counter or change its direction. - Events trigger state changes, output toggles, interrupts, and DMA transactions. - Match register 0 can be used as an automatic limit. - In bi-directional mode, events can be enabled based on the count direction. - Match events can be held until another qualifying event occurs. * State control features: - A state is defined by the set of events that are allowed to happen in the state. - A state changes into another state as result of an event. - Each event can be assigned to one or more states. - State variable allows sequencing across multiple counter cycles. * Dither engine. * Integrated with an input pre-processing unit (SCTIPU) to combine or delay input events. Inputs and outputs on the SCTimer0/PWM and SCTimer1/PWM are configured as follows: * 8 inputs - 7 inputs. Each input except input 7 can select one of 23 sources from an input multiplexer. - One input connected directly to the SCT PLL for a high-speed dedicated clock input. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 37 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller * 10 outputs (some outputs are connected to multiple locations) - Three outputs connected to external pins through the switch matrix as movable functions. - Five outputs connected to external pins through the switch matrix as fixed-pin functions. - Two outputs connected to the SCTIPU to sample or latch input events. - One output connected to the other large SCT - Four outputs connected to one small SCT - Two outputs connected to each ADC trigger input 8.22.4 State-Configurable Timers in the small configuration (SCT2/3) Remark: For applications that require exact timing of the SCT outputs (for example PWM), assign the outputs only to fixed-pin functions to ensure that the output skew is nearly the same for all outputs. 8.22.4.1 Features The following feature list summarizes the configuration for the two small SCTs. Each small SCT has a companion large SCT (see Section 8.22.3) with more inputs and outputs and a dither engine. * Each SCT supports: - 8 match/capture registers - 10 events - 10 states - 3 inputs and 6 outputs - DMA support * Counter/timer features: - Configurable as two 16-bit counters or one 32-bit counter. - Counters clocked by bus clock or selected input. - Up counters or up-down counters. - Configurable number of match and capture registers. Up to 16 match and capture registers total. - Upon match create the following events: interrupt, stop, limit timer or change direction; toggle outputs; change state. - Counter value can be loaded into capture register triggered by match or input/output toggle. * PWM features: - Counters can be used in conjunction with match registers to toggle outputs and create time-proportioned PWM signals. - Up to six single-edge or dual-edge controlled PWM outputs with independent duty cycles if configured as 32-bit timers. * Event creation features: LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 38 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller - The following conditions define an event: a counter match condition, an input (or output) condition, a combination of a match and/or and input/output condition in a specified state. - Selected events can limit, halt, start, or stop a counter. - Events control state changes, outputs, interrupts, and DMA requests. - Match register 0 can be used as an automatic limit. - In bi-directional mode, events can be enabled based on the count direction. - Match events can be held until another qualifying event occurs. * State control features: - A state is defined by events that can take place in the state while the counter is running. - A state changes into another state as result of an event. - Each event can be assigned to one or more states. - State variable allows sequencing across multiple counter cycles. * Integrated with an input pre-processing unit (SCTIPU) to combine or delay input events. Inputs and outputs on the SCTimer2/PWM and SCTimer3/PWM are configured as follows: * 3 inputs. Each input selects one of 21 sources from a pin multiplexer. * 6 outputs (some outputs are connected to multiple locations) - Three outputs connected to external pins through the switch matrix as movable functions. - Three outputs connected to external pins through the switch matrix as fixed-pin functions. - Two outputs connected to the SCT IPU to sample or latch input events. - Four outputs connected to the accompanying large SCT - Two outputs connected to each ADC trigger input 8.22.5 SCT Input processing unit (SCTIPU) The SCTIPU allows to block or propagate signals to inputs of the SCT under the control of an SCT output. Using the SCTIPU in this way, allows signals to be blocked from entering the SCT inputs for a certain amount of time, for example while they are known to be invalid. In addition, the SCTIPU can generate a common signal from several combined input sources that can be selected on all SCT inputs. Such a mechanism can be useful to create an abort signal that stops all timers. 8.22.5.1 Features The SCTIPU pre-processes inputs to the State-Configurable Timers (SCT). * Four outputs created from a selection of input transitions. Each output can be used as abort input to the SCTs or for any other application which requires a collection of multiple SCT inputs to trigger an identical SCT response. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 39 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller * Four registers to indicate which specific input sources caused the abort input to the SCTs. * Four additional outputs which can be sampled at certain times and latched at others before being routed to SCT inputs. * Nine abort inputs. Any combination of the abort inputs can trigger the dedicated abort input of each SCT. 8.23 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user code can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 8.23.1 Features * * * * * * * * * * Tracks encoder position. Increments/decrements depending on direction. Programmable for 2 or 4 position counting. Velocity capture using built-in timer. Velocity compare function with "less than" interrupt. Uses 32-bit registers for position and velocity. Three position-compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts. Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. * Digital filter with programmable delays for encoder input signals. * Can accept decoded signal inputs (clock and direction). 8.24 Analog-to-Digital Converter (ADC) The ADC supports a resolution of 12 bit and fast conversion rates of up to 2 Msamples/s. Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible trigger sources are internal connections to other on-chip peripherals such as the SCT and analog comparator outputs, external pins, and the ARM TXEV interrupt. The ADC supports a variable clocking scheme with clocking synchronous to the system clock or independent, asynchronous clocking for high-speed conversions. The ADC includes a hardware threshold compare function with zero-crossing detection. The threshold crossing interrupt is connected internally to the SCT inputs for tight timing control between the ADC and the SCTs. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 40 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.24.1 Features * * * * 12-bit successive approximation analog-to-digital converter. * * * * Two configurable conversion sequences with independent triggers. 12-bit conversion rate of 2 MHz. Input multiplexing among 12 pins and up to 4 internal sources. Internal sources are the temperature sensor voltage, internal reference voltage, core voltage regulator output, and VDDA/2. Optional automatic high/low threshold comparison and zero-crossing detection. Power-down mode and low-power operating mode. Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage level). * Burst conversion mode for single or multiple inputs. * Synchronous or asynchronous operation. Asynchronous operation maximizes flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger latency and can eliminate uncertainty and jitter in response to a trigger. 8.25 Digital-to-Analog Converter (DAC) The DAC supports a resolution of 12 bits. Conversions can be triggered by an external pin input or an internal timer. The DAC includes an optional automatic hardware shut-off feature which forces the DAC output voltage to zero while a HIGH level on the external DAC_SHUTOFF pin is detected. 8.25.1 Features * 12-bit digital-to-analog converter. * Supports DMA. * Internal timer or pin external trigger for staged, jitter-free DAC conversion sequencing. * Automatic hardware shut-off triggered by an external pin. 8.26 Analog comparator (ACMP) The LPC15xx include four analog comparators with seven selectable inputs each for each positive or negative input channel. Two analog inputs are common to all four comparators. Internal voltage inputs include a voltage ladder reference with selectable voltage supply source, the temperature sensor or the internal voltage reference. The analog inputs to the comparators are fixed-pin functions and must be enabled through the switch matrix. The outputs of each analog comparator are internally connected to the ADC trigger inputs and to the SCT inputs, so that the result of a voltage comparison can trigger a timer operation or an analog-to-digital conversion. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 41 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.26.1 Features * Seven selectable inputs. Fully configurable on either the positive side or the negative input channel. * 32-stage voltage ladder internal reference for selectable voltages on each comparator; configurable on either positive or negative comparator input. * Voltage ladder source voltage is selectable from an external pin or the 3.3 V analog voltage supply. * 0.9 V internal band gap reference voltage selectable as either positive or negative input on each comparator. * Temperature sensor voltage selectable as either positive or negative input on each comparator. * Voltage ladder can be separately powered down for applications only requiring the comparator function. * Individual comparator outputs can be connected internally to the SCT and ADC trigger inputs or the external pins. * Separate interrupt for each comparator. * Pin filter included on each comparator output. * Three propagation delay values are programmable to optimize between speed and power consumption. * Relaxation oscillator circuitry output for a 555 style timer operation using comparator blocks 0 and 1. 8.27 Temperature sensor The temperature sensor transducer uses an intrinsic pn-junction diode reference and outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage varies inversely with device temperature with an absolute accuracy of better than 5 C over the full temperature range (40 C to +105 C). The temperature sensor is only approximately linear with a slight curvature. The output voltage is measured over different ranges of temperatures and fit with linear-least-square lines. After power-up, the temperature sensor output must be allowed to settle to its stable value before it can be used as an accurate ADC input. For an accurate measurement of the temperature sensor by the ADC, the ADC must be configured in single-channel burst mode. The last value of a nine-conversion (or more) burst provides an accurate result. 8.28 Internal voltage reference The internal voltage reference is an accurate 0.9 V and is the output of a low voltage band gap circuit. A typical value at Tamb = 25 C is 0.905 V. The internal voltage reference can be used in the following applications: * When the supply voltage VDD is known accurately, the internal voltage reference can be used to reduce the offset error EO of the ADC code output. The ADC error correction then increases the accuracy of temperature sensor voltage output measurements. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 42 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller * When the ADC is accurately calibrated, the internal voltage reference can be used to measure the power supply voltage. This requires calibration by recording the ADC code of the internal voltage reference at different power supply levels yielding a different ADC code value for each supply voltage level. In a particular application, the internal voltage reference can be measured and the actual power supply voltage can be determined from the stored calibration values. The calibration values can be stored in the EEPROM for easy access. After power-up, the internal voltage reference must be allowed to settle to its stable value before it can be used as an ADC reference voltage input. For an accurate measurement of the internal voltage reference by the ADC, the ADC must be configured in single-channel burst mode. The last value of a nine-conversion (or more) burst provides an accurate result. 8.29 Multi-Rate Timer (MRT) The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be programmed with an independent time interval, and each channel operates independently from the other channels. 8.29.1 Features * 24-bit interrupt timer * Four channels independently counting down from individually set values * Repeat and one-shot interrupt modes 8.30 Windowed WatchDog Timer (WWDT) The watchdog timer resets the controller if software fails to periodically service it within a programmable time window. 8.30.1 Features * Internally resets chip if not periodically reloaded during the programmable time-out period. * Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. * Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. * Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. * * * * Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in multiples of Tcy(WDCLK) 4. * The WWDT is clocked by the dedicated watchdog oscillator (WDOsc) running at a fixed frequency. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 43 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.31 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 48-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 8.31.1 Features * 48-bit counter running from the main clock. Counter can be free-running or can be reset when an RIT interrupt is generated. * 48-bit compare value. * 48-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 8.32 System tick timer The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms). 8.33 Real-Time Clock (RTC) The RTC resides in a separate, always-on voltage domain with battery back-up. The RTC uses an independent 32 kHz oscillator, also located in the always-on voltage domain. 8.33.1 Features * 32-bit, 1 Hz RTC counter and associated match register for alarm generation. * Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution with a more that one minute maximum time-out period. * RTC alarm and high-resolution/wake-up timer time-out each generate independent interrupt requests. Either time-out can wake up the part from any of the low power modes, including Deep power-down. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 44 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.34 Clock generation IRC system oscillator watchdog oscillator MAINCLKSELA (main clock select A) main clock SYSTEM CLOCK DIVIDER system clock CPU, system control, PMU n memories, peripheral clocks RTC oscillator 32 kHz SYSAHBCLKCTRLn (AHB clock enable) MAINCLKSELB (main clock select B) SYSTICK PERIPHERAL CLOCK DIVIDER IRC SYSTEM PLL system oscillator USART PERIPHERAL CLOCK DIVIDER SYSPLLCLKSEL (system PLL clock select) FRACTIONAL RATE GENERATOR IOCONCLKDIV CLOCK DIVIDER ARM core SYSTICK USART[n:0] IOCON digital glitch filter ARM TRACE CLOCK CLOCK DIVIDER ARM trace USB 48 MHz CLOCK DIVIDER USB IRC system oscillator IRC USB PLL system oscillator USBPLLCLKSEL (USB PLL clock select) USBCLKSEL (USB clock select) IRC SCT PLL SCT system oscillator IRC SCTPLLCLKSEL (SCT PLL clock select) ASYNC ADC CLOCK DIVIDER ADC ADCASYNCCLKSEL (clock select) IRC system oscillator watchdog oscillator CLKOUTSELA (CLKOUT clock select A) CLKOUT PIN CLOCK DIVIDER CLKOUT pin RTC oscillator 32 kHz CLKOUTSELB (CLKOUT clock select B) watchdog oscillator WWDT aaa-010875 Fig 14. Clock generation LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 45 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.35 Power domains The LPC15xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD) is used to operate the RTC whenever VDD is present. Therefore, there is no power drain from the RTC battery when VDD is and VDD >= VBAT + 0.3 V. LPC15xx to I/O pads to core VSS REGULATOR to memories, peripherals, oscillators, PLLs VDD MAIN POWER DOMAIN WAKEUP ULTRA LOW-POWER REGULATOR VBAT WAKE-UP CONTROL BACKUP REGISTERS RTCXIN 32 kHz OSCILLATOR RTCXOUT REAL-TIME CLOCK ALWAYS-ON/RTC POWER DOMAIN ADC VDDA ACMP TEMP SENSE INTERNAL VOLTAGE REF VDD VSSA ADC POWER DOMAIN DAC aaa-010876 Fig 15. Power distribution 8.36 Integrated oscillators The LPC15xx include the following independent oscillators: the system oscillator, the Internal RC oscillator (IRC), the watchdog oscillator, and the 32 kHz RTC oscillator. Each oscillator can be used for multiple purposes. Following reset, the LPC15xx operates from the internal RC oscillator until software switches to a different clock source. The IRC allows the system to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 14 for an overview of the LPC15xx clock generation. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 46 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.36.1 Internal RC oscillator The IRC can be used as the clock that drives the system PLL and then the CPU. In addition, the IRC can be selected as input to various clock dividers and as the clock source for the USB PLL and the SCT PLL (see Figure 14). The nominal IRC frequency is 12 MHz. Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC15xx use the IRC as the clock source. Software can later switch to one of the other available clock sources. 8.36.2 System oscillator The system oscillator can be used as a stable and accurate clock source for the CPU, with or without using the PLL. For USB applications, use the system oscillator to provide the clock source to USB PLL. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. The system oscillator has a wake-up time of approximately 500 s. 8.36.3 Watchdog oscillator The low-power watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is fixed at 503 kHz. The frequency spread over processing and temperature is 40 %. 8.36.4 RTC oscillator The low-power RTC oscillator provides a 1 Hz clock and a 1 kHz clock to the RTC and a 32 kHz clock output that can be used to obtain the main clock (see Figure 14).The 32 kHz oscillator output can be observed on the CLKOUT pin to allow trimming the RTC oscillator without interference from a probe. 8.37 System PLL, USB PLL, and SCT PLL The LPC15xx contain a three identical PLLs for generating the system clock, the 48 MHz USB clock, and an asynchronous clock for the ADCs and SCTs. The system PLL is used to create the main clock. The SCT and USB PLLs create dedicated clocks for the asynchronous ADC, the asynchronous SCT clock input, and the USB. Remark: The USB PLL is available on parts LPC1549/48/47 only. The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz. To support this frequency range, an additional divider keeps the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset. Software can enable the PLL later. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 47 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.38 Clock output The LPC15xx feature a clock output function that routes the internal oscillator outputs, the PLL outputs, or the main clock an output pin where they can be observed directly. 8.39 Wake-up process The LPC15xx begin operation by using the 12 MHz IRC oscillator as the clock source at power-up and when awakened from Deep power-down mode. This mechanism allows chip operation to resume quickly. If the application uses the system oscillator or the PLL, software must enable these components and wait for them to stabilize. Only then can the system use the PLL and system oscillator as a clock source. 8.40 Power control The LPC15xx support various power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate can also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This power control mechanism allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals. This register allows fine-tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides additional power control. 8.40.1 Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile. The power configuration routine configures the LPC15xx for one of the following power modes: * Default mode corresponding to power configuration after reset. * CPU performance mode corresponding to optimized processing capability. * Efficiency mode corresponding to optimized balance of current consumption and CPU performance. * Low-current mode corresponding to lowest power consumption. In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock and to easily set the configuration options for Deep-sleep and power-down modes. Remark: When using the USB, configure the LPC15xx in Default mode. 8.40.2 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and can generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, by memory systems and related controllers, and by internal buses. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 48 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.40.3 Deep-sleep mode In Deep-sleep mode, the LPC15xx is in Sleep-mode and all peripheral clocks and all clock sources are off except for the IRC. The IRC output is disabled unless the IRC is selected as input to the watchdog timer. In addition all analog blocks are shut down and the flash is in stand-by mode. In Deep-sleep mode, the application can keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. The LPC15xx can wake up from Deep-sleep mode via reset, selected GPIO pins, a watchdog timer interrupt, an interrupt generating USB port activity, an RTC interrupt, or any interrupts that the USART, SPI, or I2C interfaces can create in Deep-sleep mode. The USART wake-up requires the 32 kHz mode, the synchronous mode, or the CTS interrupt to be set up. Deep-sleep mode saves power and allows for short wake-up times. 8.40.4 Power-down mode In Power-down mode, the LPC15xx is in Sleep-mode and all peripheral clocks and all clock sources are off except for watchdog oscillator if selected. In addition all analog blocks and the flash are shut down. In Power-down mode, the application can keep the BOD circuit running for BOD protection. The LPC15xx can wake up from Power-down mode via reset, selected GPIO pins, a watchdog timer interrupt, an interrupt generating USB port activity, an RTC interrupt, or any interrupts that the USART, SPI, or I2C interfaces can create in Power-down mode. The USART wake-up requires the 32 kHz mode, the synchronous mode, or the CTS interrupt to be set up. Power-down mode reduces power consumption compared to Deep-sleep mode at the expense of longer wake-up times. 8.40.5 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP pin and the always-on RTC power-domain. The LPC15xx can wake up from Deep power-down mode via the WAKEUP pin or a wake-up signal generated by the RTC interrupt. The LPC15xx can be blocked from entering Deep power-down mode by setting a lock bit in the PMU block. Blocking the Deep power-down mode enables the application to keep the watchdog timer or the BOD running at all times. If the WAKEUP pin is used in the application, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH while the part is in deep power-down mode. Pulling the WAKEUP pin LOW wakes up the part from deep power-down mode. In addition, pull the RESET pin HIGH to prevent it from floating while in Deep power-down mode. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 49 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.41 System control 8.41.1 Reset Reset has four sources on the LPC15xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. In Deep power-down mode, an external pull-up resistor is required on the RESET pin. The RESET pin is operational in active, sleep, deep-sleep, and power-down modes if the RESET function is selected through the switch matrix for pin PIO0_21 (this is the default). A LOW-going pulse as short as 50 ns executes the reset and thereby wakes up the part to its active state. The RESET pin is not functional in Deep power-down mode and must be pulled HIGH externally while the part is in Deep power-down mode. 9'' 9'' 9'' 5SX UHVHW (6' QV5& */,7&+),/7(5 3,1 (6' 966 DDD Fig 16. RESET pin configuration 8.41.2 Brownout detection The LPC15xx includes brown-out detection (BOD) with two levels for monitoring the voltage on the VDD pin. If this voltage falls below one of two selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. Two threshold levels can be selected to cause a forced reset of the chip. 8.41.3 Code security (Code Read Protection - CRP) CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 50 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller In addition, ISP entry the external pins can be disabled without enabling CRP. For details, see the LPC15xx user manual. There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected, fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using ISP pin as well. If necessary, the application must provide a flash update mechanism using IAP calls or using a call to the reinvoke ISP command to enable flash update via the USART. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of the ISP pins for valid user code can be disabled. For details, see the LPC15xx user manual. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 51 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.42 Emulation and debugging Debug functions are integrated into the ARM Cortex-M3. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M3 is configured to support up to four breakpoints and two watch points. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC15xx is in reset. To perform boundary scan testing, follow these steps: 1. Erase any user code residing in flash. 2. Power up the part with the RESET pin pulled HIGH externally. 3. Wait for at least 250 s. 4. Pull the RESET pin LOW externally. 5. Perform boundary scan operations. 6. Once the boundary scan operations are completed, assert the TRST pin to enable the SWD debug mode, and release the RESET pin (pull HIGH). Remark: The JTAG interface cannot be used for debug purposes. 9. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter VDD supply voltage (3.3 V) VDDA analog supply voltage Vref reference voltage VBAT battery supply voltage VI input voltage Conditions [2] on pin VREFP_DAC_VDDCMP Max Unit 0.5 VDDA V 0.5 +4.6 V 0.5 VDDA V 0.5 VDDA V 0.5 +4.6 V [3][4] 0.5 +5.5 V on I2C open-drain pins PIO0_22, PIO0_23 [5] 0.5 +5.5 V 3 V tolerant I/O pin without over-voltage protection. Applies to PIO0_12. [6] 0.5 VDDA V 0.5 VDD + 0.5 V 0.5 +4.6 V 0.5 +2.5 V on pin VREFP_ADC 5 V tolerant I/O pins; only valid when the VDD(IO) supply voltage is present USB_DM, USB_DP pins VIA Min [7][8] analog input voltage [9] crystal input voltage [2] Vi(rtcx) 32 kHz oscillator input voltage [2] 0.5 +4.6 V IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Vi(xtal) LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 52 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 9. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD); - 100 mA Tstg storage temperature 65 +150 C Tj(max) maximum junction temperature - +150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W Vesd electrostatic discharge voltage human body model; all pins - 5 kV Tj < 125 C [1] [10] [11] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 11) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] Applies to all 5 V tolerant I/O pins except true open-drain pins PIO0_22 and PIO0_23 and except the 3 V tolerant pin PIO0_12. [4] Including the voltage on outputs in 3-state mode. [5] VDD(IO) present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD(IO) is powered down. [6] Applies to 3 V tolerant pin PIO0_12. [7] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the ADC inputs for a long time affects the reliability of the device and reduces its lifetime. [8] If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below VDD without affecting the hysteresis range of the comparator function. [9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [10] Dependent on package type. [11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 10. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb + P D R th j - a (1) * Tamb = ambient temperature (C), * Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) * PD = sum of internal and I/O power dissipation LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 53 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 10. Symbol Thermal resistance value (C/W): 15 % Parameter Conditions Typ Unit thermal resistance junction-to-ambient JEDEC (4.5 in 4 in) 0 m/s 64 C/W 1 m/s 55 C/W 2.5 m/s 50 C/W 0 m/s 96 C/W 1 m/s 76 C/W LQFP48 ja 8-layer (4.5 in 3 in) 67 C/W jc thermal resistance junction-to-case 13 C/W jb thermal resistance junction-to-board 16 C/W 0 m/s 51 C/W 1 m/s 45 C/W 2.5 m/s 41 C/W 0 m/s 75 C/W 1 m/s 60 C/W 2.5 m/s 54 C/W 2.5 m/s LQFP64 ja thermal resistance junction-to-ambient JEDEC (4.5 in 4 in) 8-layer (4.5 in 3 in) jc thermal resistance junction-to-case 13 C/W jb thermal resistance junction-to-board 17 C/W 0 m/s 42 C/W 1 m/s 37 C/W 2.5 m/s 34 C/W 0 m/s 59 C/W 1 m/s 48 C/W LQFP100 ja thermal resistance junction-to-ambient JEDEC (4.5 in 4 in) 8-layer (4.5 in 3 in) 44 C/W jc thermal resistance junction-to-case 12 C/W jb thermal resistance junction-to-board 17 C/W 2.5 m/s LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 54 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. 11. Static characteristics Table 11. Static characteristics Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) VDDA analog supply voltage Vref reference voltage VBAT battery supply voltage IDD supply current Min Typ[1] Max Unit 2.4 3.3 VDDA V 2.4 3.3 3.6 V on pin VREFP_DAC_VDDCMP 2.4 - VDDA V on pin VREFP_ADC - - VDDA V 2.4 3.3 3.6 V - 4.3 - mA - 2.7 - mA - 19.3 - mA - 18 - mA - 2.1 - mA - 1.5 - mA - 8.0 - mA - 7.3 - mA Conditions [2] Active mode; code while(1){} executed from flash; system clock = 12 MHz; default mode; VDD = 3.3 V [3][4][5] system clock = 12 MHz; low-current mode; VDD = 3.3 V [3][4][5] system clock = 72 MHz; default mode; VDD = 3.3 V [3][4][7] system clock = 72 MHz; low-current mode; VDD = 3.3 V [3][4][7] [7][8] [7][8] [8][10] [8][10] Sleep mode; IDD supply current system clock = 12 MHz; default mode; VDD = 3.3 V [3][4][5] system clock = 12 MHz; low-current mode; VDD = 3.3 V [3][4][5] system clock = 72 MHz; default mode; VDD = 3.3 V [3][4][10] system clock = 72 MHz; low-current mode; VDD = 3.3 V [3][4][10] Deep-sleep mode; VDD = 3.3 V; [7][8] [7][8] [7][8] [7][8] [3][4][11] - Tamb = 25 C Tamb = 105 C IDD supply current Power-down mode; VDD = 3.3 V [3][4][11] LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 380 A 620 A 3.8 15 A - 163 A - Tamb = 25 C Tamb = 105 C 310 - - (c) NXP Semiconductors N.V. 2015. All rights reserved. 55 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics ...continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol IDD Parameter supply current Conditions Deep power-down mode; VDD = 3.3 V; VBAT = 0 or VBAT = 3.0 V Min Typ[1] Max Unit - 1.1 1.3[14] A - - 15 A - 560 - nA 0 - nA 1 - A [3][12][13] RTC oscillator running Tamb = 25 C Tamb = 105 C [3][12] RTC oscillator input grounded; Tamb = 25 C IBAT battery supply current Deep power-down mode; VDD = VDDA = 3.3 V; VBAT = 3.0 V [13] VDD and VDDA tied to ground; VBAT = 3.0 V [13] Standard port pins configured as digital pins, RESET; see Figure 17 IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10[14] nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10[14] nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10[14] nA VI input voltage VDD 2.4 V; 5 V tolerant pins except PIO0_12 0 - 5 V VDD 2.4 V; on 3 V tolerant pin PIO0_12 0 - VDDA VDD = 0 V 0 - 3.6 V output active 0 - VDD V V [16] [18] VO output voltage VIH HIGH-level input voltage 0.7VDD - - VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage 2.4 V <= VDD < 3.0 V 0.30 - - V 3.0 V <= VDD <= 3.6 V 0.35 - - V VOH HIGH-level output voltage IOH = 4 mA VDD 0.4 - - V VOL LOW-level output voltage IOL = 4 mA - - 0.4 V IOH HIGH-level output current VOH = VDD 0.4 V 4 - - mA IOL LOW-level output current VOL = 0.4 V 4 - - mA IOHS HIGH-level short-circuit VOH = 0 V output current [19] - - -45 mA IOLS LOW-level short-circuit output current VOL = VDD [19] - - 50 mA Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V; 10 50 85 A VDD < VI < 5 V 0 0 0 A LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 56 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics ...continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit High-drive output pin configured as digital pin (PIO0_24); see Figure 17 IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10[14] nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10[14] nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10[14] nA VI input voltage VDD 2.4 V 0 - 5.0 V VDD = 0 V 0 - 3.6 V output active [16] [18] VO output voltage 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage VOH HIGH-level output voltage 2.4 V <= VDD < 3.0 V 0.30 - - V 3.0 V <= VDD <= 3.6 V 0.35 - - V IOH = 20 mA; 2.7 V <= VDD < 3.6 V VDD 0.4 - - V IOH = 12 mA; 2.4 V <= VDD < 2.7 V VDD 0.4 - - V VOL LOW-level output voltage IOL = 4 mA - - 0.4 V IOH HIGH-level output current VOH = VDD 0.4 V; 2.7 V <= VDD < 3.6 V 20 - - mA VOH = VDD 0.4 V; 2.4 V <= VDD < 2.7 V 12 - - mA 4 - - mA IOL LOW-level output current VOL = 0.4 V IOLS LOW-level short-circuit output current VOL = VDD [19] - - 50 mA Ipd pull-down current VI = 5 V [20] 10 50 150 A Ipu pull-up current VI = 0 V [20] 10 50 85 A 0 0 0 A V VDD < VI < 5 V I2C-bus pins (PIO0_22 and PIO0_23); see Figure 17 VIH HIGH-level input voltage 0.7VDD - - VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.05VDD - V 3.5 - - mA IOL LOW-level output current LPC15XX Product data sheet I2C-bus VOL = 0.4 V; pins configured as standard mode pins All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 57 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 11. Static characteristics ...continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol IOL Parameter LOW-level output current ILI input leakage current Min Typ[1] Max Unit VOL = 0.4 V; pins configured as Fast-mode Plus pins; 2.7 V <= VDD < 3.6 V 20 - - mA VOL = 0.4 V; I2C-bus pins configured as Fast-mode Plus pins; 2.4 V <= VDD < 2.7 V 16 - - mA - 2 4 A - 10 22 A 0 - VDD V Conditions I2C-bus [21] VI = VDD VI = 5 V USB_DM and USB_DP pins [2] VI input voltage VIH HIGH-level input voltage 1.8 - - V VIL LOW-level input voltage - - 1.0 V Vhys hysteresis voltage 0.32 - - V Zout output impedance 28 - 44 VOH HIGH-level output voltage 2.9 - - V VOL LOW-level output voltage - - 0.18 V IOH HIGH-level output current VOH = VDD 0.3 V [22] 4.8 - - mA IOL LOW-level output current VOL = 0.3 V [22] 5.0 - - mA IOLS LOW-level short-circuit output current drive LOW; pad connected to ground - - 125 mA IOHS HIGH-level short-circuit drive HIGH; pad connected to output current ground - - 125 mA 0.5 1.8 1.95 V Oscillator pins Vi(xtal) crystal input voltage on pin XTALIN Vo(xtal) crystal output voltage on pin XTALOUT 0.5 1.8 1.95 V [23] 0.5 - 3.6 V [23] 0.5 - 3.6 V pins with analog and digital functions [24] - - 7.1 pF I2C-bus pins (PIO0_22 and PIO0_23) [24] - - 2.5 pF pins with digital functions only [24] - - 2.8 pF Vi(rtcx) 32 kHz oscillator input voltage on pin RTCXIN Vo(rtcx) 32 kHz oscillator output on pin RTCXOUT voltage Pin capacitance input/output capacitance Cio [1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. [2] For USB operation: 3.0 VVDD 3.6 V. [3] Tamb = 25 C. [4] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 58 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [5] IRC enabled; system oscillator disabled; system PLL disabled. [6] System oscillator enabled; IRC disabled; system PLL disabled. [7] BOD disabled. [8] All peripherals disabled in the SYSAHBCLKCTRL0/1 registers. Peripheral clocks to USART, CLKOUT, and IOCON disabled in system configuration block. [9] IRC enabled; system oscillator disabled; system PLL enabled. [10] IRC disabled; system oscillator enabled; system PLL enabled. [11] All oscillators and analog blocks turned off: Use API power_mode_configure() with mode parameter set to DEEP_SLEEP or POWER_DOWN and peripheral parameter set to 0xFF. [12] WAKEUP pin pulled HIGH externally. [13] RTC running or not running. [14] Characterized on samples. Not tested in production. [15] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [16] Including voltage on outputs in tri-state mode. [17] VDD supply voltage must be present. [18] Tri-state outputs go into tri-state mode in Deep power-down mode. [19] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [20] Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 17. [21] To VSS. [22] The parameter values specified are simulated and absolute values. [23] The input voltage of the RTC oscillator is limited as follows: Vi(rtcx), Vo(rtcx) < max(VBAT, VDD). [24] Including bonding pad capacitance. VDD IOL Ipd pin PIO0_n + A IOH Ipu pin PIO0_n - + A aaa-010819 Fig 17. Pin input/output current measurement LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 59 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.1 Power consumption Power measurements in Active, Sleep, Deep-sleep, and Power-down modes were performed under the following conditions: * Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. * Configure GPIO pins as outputs using the GPIO DIR register. * Write 1 to the GPIO CLR register to drive the outputs LOW. aaa-011384 20 IDD (mA) 72 MHz 16 60 MHz 12 48 MHz 36 MHz 8 24 MHz 4 12 MHz 6 MHz 1 MHz 0 2.4 2.6 2.8 3 3.2 3.4 VDD (V) 3.6 Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL0/1 registers; all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz to 72 MHz: IRC enabled; PLL enabled. Fig 18. Active mode: Typical supply current IDD versus supply voltage VDD LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 60 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-011385 20 IDD (mA) 72 MHz 16 60 MHz 12 48 MHz 36 MHz 8 24 MHz 4 12 MHz 6 MHz 1 MHz 0 -40 -10 20 50 80 temperature (C) 110 Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL0/1 registers; all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz to 72 MHz: IRC enabled; PLL enabled. Fig 19. Active mode: Typical supply current IDD versus temperature aaa-011386 8 IDD (mA) 72 MHz 6 60 MHz 48 MHz 4 36 MHz 24 MHz 2 12 MHz 6 MHz 1 MHz 0 -40 -10 20 50 80 temperature (C) 110 Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL0/1 registers; all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz to 72 MHz: IRC enabled; PLL enabled. Fig 20. Sleep mode: Typical supply current IDD versus temperature for different system clock frequencies LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 61 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-011234 400 IDD (A) 380 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V 360 340 320 300 280 -40 -10 20 50 80 temperature (C) 110 Conditions: BOD disabled; all oscillators and analog blocks disabled. Use API power_mode_configure() with mode parameter set to DEEP_SLEEP and peripheral parameter set to 0xFF. Fig 21. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD aaa-011235 80 IDD (A) 60 40 20 0 -40 -10 20 50 80 temperature (C) 110 Conditions: BOD disabled; all oscillators and analog blocks disabled; VDD = 2.4 V to 3.6 V. Use API power_mode_configure() with mode parameter set to POWER_DOWN and peripheral parameter set to 0xFF. Fig 22. Power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 62 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-011236 4 IDD (A) 3 2 3.6 V 3.3 V 1 2.4 V 0 -40 -10 20 50 80 temperature (C) 110 VBAT = 0 V. Fig 23. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD aaa-011333 4 IBAT (A) 3 2 1 0 -40 -10 20 50 80 temperature (C) 110 VBAT = 3.3 V; VDD floating. Fig 24. Deep power-down mode: Typical battery supply current IBAT versus temperature LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 63 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.2 CoreMark data aaa-011746 2.65 CM score 2.6 2.55 cpu 2.5 2.45 efficiency 2.4 default/low current 2.35 0 12 24 36 48 60 system clock frequency (MHz) 72 Conditions: VDD = 3.3 V; active mode; all peripherals except one UART and the SCT disabled in the SYSAHBCLKCTRL0/1 register; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision v.4.73.0.0, C compiler v.5.03.0.76. Fig 25. CoreMark score aaa-011747 30 IDD (mA) 25 20 15 default cpu efficiency low-current 10 5 0 0 12 24 36 48 60 system clock frequency (MHz) 72 Conditions: VDD = 3.3 V; Tamb = 25 C; active mode; all peripherals except one UART and the SCT disabled in the SYSAHBCLKCTRL0/1 registers; system clock derived from the IRC; system oscillator disabled; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision v.4.73.0.0, C compiler v.5.03.0.76. Fig 26. Active mode: CoreMark power consumption IDD LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 64 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code accessing the peripheral is executed. Measured on a typical sample at Tamb = 25 C. Unless noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of 12 MHz and 72 MHz. Table 12. Power consumption for individual analog and digital blocks Peripheral Typical supply current in mA Notes n/a 12 MHz 72 MHz IRC 0.008 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator at 12 MHz 0.220 - - IRC running; PLL off; independent of main clock frequency. Watchdog oscillator 0.002 - - System oscillator running; PLL off; independent of main clock frequency. BOD 0.045 - - Independent of main clock frequency. Main PLL - 0.085 - - USB PLL 0.100 SCT PLL 0.110 CLKOUT - 0.005 0.01 Main clock divided by 4 in the CLKOUTDIV register. ROM - 0.015 0.02 - GPIO + pin interrupt/pattern match - 0.55 0.60 GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. SWM - 0.04 0.29 - 0.05 0.30 INPUT MUX IOCON - 0.06 0.40 - SCTimer0/PWM - 0.18 1.10 - SCTimer1/PWM - 0.19 1.10 - SCTimer2/PWM - 0.13 0.70 - SCTimer3/PWM - - SCT IPU 0.16 0.90 0.02 0.1 RTC - 0.01 0.05 - MRT - 0.03 0.10 - WWDT - 0.01 0.10 Main clock selected as clock source for the WDT. RIT 0.07 0.20 QEI 0.12 0.80 I2C0 - 0.02 0.12 - SPI0 - 0.03 0.3 - SPI1 - 0.01 0.28 - LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 65 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 12. Power consumption for individual analog and digital blocks ...continued Peripheral Typical supply current in mA Notes n/a 12 MHz 72 MHz USART0 - 0.02 0.15 - USART1 - 0.02 0.16 - USART2 - 0.02 0.15 - C_CAN - 0.50 3.00 USB - 0.10 0.50 Comparator ACMP0/1/2/3 - 0.01 0.03 - ADC0 - 0.05 0.33 - ADC1 - 0.04 0.33 - temperature sensor - 0.03 0.03 internal voltage reference/band gap 0.03 0.04 DAC - 0.02 0.09 DMA - 0.36 1.5 CRC - 0.01 0.08 - 11.4 Electrical pin characteristics aaa-011257 3.3 VOH (V) 3.2 3.1 -40 C 25 C 90 C 105 C 3 2.9 2.8 2.7 0 10 20 30 40 IOH (mA) 50 Conditions: VDD = 3.3 V; on pin PIO0_24. Fig 27. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 66 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-011258 50 IOL OH (mA) 40 -40 C 25 C 90 C 105 C 30 20 10 0 0 0.1 0.2 0.3 0.4 VOL (V) 0.5 Conditions: VDD = 3.3 V; on pins PIO0_22 and PIO0_23. Fig 28. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL aaa-011263 10 VOL (V) 8 -40 C 25 C 90 C 105 C 6 4 2 0 0 0.1 0.2 0.3 0.4 IOL (mA) 0.5 Conditions: VDD = 3.3 V; standard port pins and high-drive pin PIO0_24. Fig 29. Typical LOW-level output current IOL versus LOW-level output voltage VOL LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 67 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-011276 3.3 IOH (mA) -40 C 25 C 90 C 105 C 3.1 2.9 2.7 0 3 6 9 VOH (V) 12 Conditions: VDD = 3.3 V; standard port pins. Fig 30. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH aaa-011277 0 Ipu pd (A) -20 105 C 90 C 25 C -40 C -40 -60 -80 0 1 2 3 4 VI (V) 5 Conditions: VDD = 3.3 V; standard port pins. Fig 31. Typical pull-up current Ipu versus input voltage VI LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 68 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller aaa-011278 80 Ipu (A) 60 -40 C 25 C 90 C 105 C 40 20 0 0 1 2 3 4 VI (V) 5 Conditions: VDD = 3.3 V; standard port pins. Fig 32. Typical pull-down current Ipd versus input voltage VI LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 69 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12. Dynamic characteristics 12.1 Flash/EEPROM memory Table 13. Flash characteristics Tamb = 40 C to +105 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as specified below. Symbol Parameter Nendu endurance Conditions tret retention time Min Typ Max Unit 10000 100000 - cycles powered 10 20 - years not powered 20 40 - years page or multiple consecutive pages, sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.05 ms [1] ter erase time tprog programming time [2] [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes to the flash. Tamb <= +85 C. Flash programming with IAP calls (see LPC15xx user manual). Table 14. EEPROM characteristics Tamb = 40 C to +85 C; VDD = 2.7 V to 3.6 V. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as specified below. Symbol Parameter Conditions Nendu endurance tret retention time programming time tprog Min Typ Max Unit 100000 1000000 - cycles powered 100 200 - years not powered 150 300 - years 64 bytes - 2.9 - ms 12.2 External clock for the oscillator in slave mode Remark: The input voltage on the XTALIN and XTALOUT pins must be 1.95 V (see Table 11). For connecting the oscillator to the XTAL pins, also see Section 14.3. Table 15. Dynamic characteristic: external clock (XTALIN input) Tamb = 40 C to +105 C; VDD over specified ranges.[1] Min Typ[2] Max Unit oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk) 0.4 - - ns tCLCX clock LOW time Tcy(clk) 0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns Symbol Parameter fosc [1] LPC15XX Product data sheet Conditions Parameters are valid over operating temperature range unless otherwise specified. All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 70 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. W&+&/ W&+&; W&/&+ W&/&; 7F\ FON DDD Fig 33. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) 12.3 Internal oscillators Table 16. Dynamic characteristics: IRC Tamb = 40 C to +105 C; 2.7 V VDD 3.6 V[1]. Typ[2] Max Unit 25 C Tamb +85 C 12 - 1% 12 12 + 1 % MHz 40 C Tamb < 25 C 12 - 2% 12 12 + 1 % MHz Symbol Parameter Conditions fosc(RC) internal RC oscillator frequency Min 85 C < Tamb 105 C 12 - 1.5 % 12 12 + 1.5 % MHz [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. aaa-011233 12.15 fosc(RC) (MHz) 12.1 3.6 V 3.3 V 3.0 V 2.7 V 12.05 12 11.95 11.9 11.85 -40 -10 20 50 80 temperature (C) 110 Conditions: Frequency values are typical values. 12 MHz 1 % accuracy is guaranteed for 2.7 V VDD 3.6 V and Tamb = 25 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz 1 % accuracy specification for voltages below 2.7 V. Fig 34. Typical Internal RC oscillator frequency versus temperature LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 71 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 17. Symbol fosc(int) Dynamic characteristics: Watchdog oscillator Parameter Conditions internal oscillator frequency - [2] Min Typ[1] Max Unit - 503 - kHz [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages. [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %. 12.4 I/O pins Table 18. Dynamic characteristics: I/O pins[1] Tamb = 40 C to +105 C; 3.0 V VDD 3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns [1] Applies to standard port pins and RESET pin. 12.5 I2C-bus Table 19. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +105 C; values guaranteed by design.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz tf [4][5][6][7] fall time Fast-mode 0 400 kHz Fast-mode Plus; on pins PIO0_22 and PIO0_23 0 1 MHz of both SDA and SCL signals - 300 ns Fast-mode 20 + 0.1 Cb 300 ns Fast-mode Plus; on pins PIO0_22 and PIO0_23 - 120 ns Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus; on pins PIO0_22 and PIO0_23 0.5 - s Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus; on pins PIO0_22 and PIO0_23 0.26 - s Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus; on pins PIO0_22 and PIO0_23 0 - s Standard-mode tLOW tHIGH tHD;DAT LPC15XX Product data sheet LOW period of the SCL clock HIGH period of the SCL clock data hold time [3][4][8] All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 72 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 19. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +105 C; values guaranteed by design.[2] Symbol Parameter tSU;DAT [1] [9][10] data set-up time Conditions Min Max Unit Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus; on pins PIO0_22 and PIO0_23 50 - ns See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. WI 6'$ W68'$7 W+''$7 WI 6&/ W9''$7 W+,*+ W/2: 6 I6&/ DDD Fig 35. I2C-bus pins clock timing LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 73 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.6 SPI interfaces The maximum data bit rate is 17 Mbit/s in master mode and in slave mode. Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for all digital pins except the open-drain pins PIO0_22 and PIO0_23. Table 20. SPI dynamic characteristics Tamb = 40 C to 105 C; 2.4 V <= VDD <= 3.6 V; CL = 10 pF; input slew = 1 ns. Simulated parameters sampled at the 50 % level of the rising or falling edge; values guaranteed by design. Symbol Parameter Min Max Unit tDS data set-up time 30 - ns tDH data hold time 0 - ns tv(Q) data output valid time - 4 ns th(Q) data output hold time 2 - ns tDS data set-up time 6 - ns tDH data hold time 0 - ns tv(Q) data output valid time - 29 ns th(Q) data output hold time 12 - ns SPI master SPI slave 7F\ FON 6&. &32/ 6&. &32/ WY 4 WK 4 '$7$9$/,' 026, '$7$9$/,' W'6 '$7$9$/,' 0,62 W'+ '$7$9$/,' WY 4 026, '$7$9$/,' WK 4 '$7$9$/,' W'+ W'6 0,62 '$7$9$/,' &3+$ &3+$ '$7$9$/,' DDD Tcy(clk) = CCLK/DIVVAL with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the LPC15xx User manual UM10736. Fig 36. SPI master timing LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 74 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7F\ FON 6&. &32/ 6&. &32/ W'6 026, '$7$9$/,' W'+ '$7$9$/,' WY 4 0,62 WK 4 '$7$9$/,' W'6 026, '$7$9$/,' W'+ '$7$9$/,' WY 4 0,62 '$7$9$/,' &3+$ '$7$9$/,' WK 4 &3+$ '$7$9$/,' DDD Fig 37. SPI slave timing LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 75 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.7 USART interface The maximum USART bit rate is 15 Mbit/s in synchronous mode master mode and 18 Mbit/s in synchronous slave mode. Remark: USART functions can be assigned to all digital pins. The characteristics are valid for all digital pins except the open-drain pins PIO0_22 and PIO0_23. Table 21. USART dynamic characteristics Tamb = 40 C to 105 C; 2.4 V <= VDD <= 3.6 V; CL = 10 pF; input slew = 10 ns. Simulated parameters sampled at the 50 % level of the falling or rising edge; values guaranteed by design. Symbol Parameter Min Max Unit USART master (in synchronous mode) tsu(D) data input set-up time 33 - ns th(D) data input hold time 0 - ns tv(Q) data output valid time - 7 ns th(Q) data output hold time 2 - ns USART slave (in synchronous mode) tsu(D) data input set-up time 13 - ns th(D) data input hold time 0 - ns tv(Q) data output valid time - 28 ns th(Q) data output hold time 12 - ns 7F\ FON 8QB6&/. &/.32/ 8QB6&/. &/.32/ WY 4 67$57 7;' WK 4 %,7 %,7 WVX ' WK ' 5;' 67$57 %,7 %,7 DDD In master mode, Tcy(clk) = U_PCLK/BRGVAL. See the LPC15xx User manual UM10736. Fig 38. USART timing LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 76 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.8 SCTimer/PWM output timing Table 22. SCTimer/PWM output dynamic characteristics Tamb = 40 C to 105 C; 2.4 V <= VDD <= 3.6 V Cl = 10 pF. Simulated skew (over process, voltage, and temperature) of any two SCT fixed-pin output signals; sampled at the 50 % level of the falling or rising edge; values guaranteed by design. Symbol Parameter Conditions Min Typ Max Unit tsk(o) output skew time SCTimer0/PWM - - 4 ns SCTimer1/PWM - - 3 ns SCTimer2/PWM - - 1 ns SCTimer3/PWM - - 2 ns 13. Characteristics of analog peripherals Table 23. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Vth threshold voltage interrupt level 2 Min Typ Max Unit assertion - 2.55 - V de-assertion - 2.69 - V assertion - 2.83 - V de-assertion - 2.96 - V assertion - 2.34 - V de-assertion - 2.49 - V assertion - 2.64 - V de-assertion - 2.79 - V interrupt level 3 reset level 2 reset level 3 [1] LPC15XX Product data sheet Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see the LPC15xx user manual. All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 77 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 24. 12-bit ADC static characteristics Tamb = 40 C to +105 C; VDD = 2.4 V to 3.6 V; VREFP = VDDA; VSSA = 0; VREFN = VSSA. Symbol Parameter Conditions [1] VIA analog input voltage Cia analog input capacitance fclk(ADC) ADC clock frequency VDDA 2.7 V fs sampling frequency VDDA 2.7 V Min Max 0 VDDA V - 0.32 pF 50 MHz VDDA 2.4 V VDDA 2.4 V 25 MHz - 2 Msamples/s - 1 Msamples/s - +/- 2 LSB ED differential linearity error [2] EL(adj) integral non-linearity [3] - +/- 2 LSB offset error [4] - +/- 3 LSB Verr(fs) full-scale error voltage [5] - +/- 0.12 % +/- 0.07 % Zi input impedance - M EO 2 Msamples/s 1 Msamples/s LPC15XX Product data sheet Unit fs = 2 Msamples/s [6][7] 0.1 [1] The input resistance of ADC channel 0 is higher than for all other channels. [2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 40. [3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 40. [4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 40. [5] The full-scale error voltage or gain error (EG) is the difference between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 40. [6] Tamb = 25 C; maximum sampling frequency fs = 2 Msamples/s and analog input capacitance Cia = 0.132 pF. [7] Input impedance Zi is inversely proportional to the sampling frequency and the total input capacity including Cia and Cio: Zi 1 / (fs Ci). See Table 11 for Cio. All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 78 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller ADC R1 = 0.25 k...2.5 k ADCn_0 Rsw = 5 ...25 Cio ADCn_[1:11] DAC CDAC Cio Cia aaa-011748 Fig 39. ADC input impedance LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 79 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) offset error EO 1 LSB = VREFP - VSS 4096 002aaf436 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 40. 12-bit ADC characteristics LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 80 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 25. DAC static and dynamic characteristics VDDA = 2.4 V to 3.6 V; Tamb = 40 C to +105 C unless otherwise specified; CL = 100 pF; RL = 10 k.. Symbol Parameter Conditions Min Typ Max Unit 500 kSamples/s [1] fc(DAC) DAC conversion frequency - - RO output resistance - 300 ts settling time - - 2.5 s ED differential linearity error - - +/-0.4 LSB EL(adj) integral non-linearity - - +/-3 LSB EO offset error VDDA = 3.3 V - - +/-9 LSB VDDA = 2.4 V - - +/-8 LSB - - +/- 0.1 % Output voltage range with less than 1 LSB deviation; with minimum RL connected to ground or power supply - - VDDA - 0.3 V EG gain error VO output voltage [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. LPCxxxx DVM DAC RL 10 k aaa-011964 Fig 41. DAC test circuit LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 81 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 26. Internal voltage reference static and dynamic characteristics Symbol Parameter Conditions VO output voltage Tamb = 40 C to +105 C ts(pu) power-up settling time to 99% of VO [1] Min Typ Max Unit 875 - 925 mV 125 s Tamb = 25 C [1] 905 - - mV Maximum and minimum values are measured on samples from the corners of the process matrix lot. aaa-011179 920 Voltage (V) 915 910 905 900 895 890 -40 -10 20 50 80 temperature (C) 110 VDDA = 3.3 V; averaged over process corners Fig 42. Average internal voltage reference output voltage LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 82 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 27. Temperature sensor static and dynamic characteristics VDDA = 2.4 V to 3.6 V Symbol Parameter Conditions DTsen sensor temperature accuracy Tamb = 40 C to +105 C EL linearity error Tamb = 40 C to +105 C power-up settling time ts(pu) [1] [2][3] to 99% of temperature sensor output value Min Typ Max Unit - - 5 C - - 5 C - 81 110 s [1] Absolute temperature accuracy. [2] Typical values are derived from nominal simulation (VDDA = 3.3 V; Tamb = 27 C; nominal process models). Maximum values are derived from worst case simulation (VDDA = 2.6 V; Tamb = 105 C; slow process models). [3] Internal voltage reference must be powered before the temperature sensor can be turned on. [4] Settling time applies to switching between comparator and ADC channels. Table 28. Temperature sensor Linear-Least-Square (LLS) fit parameters VDDA = 2.4 V to 3.6 V Fit parameter Range Min Typ Max Unit Tamb = 40 C to +105 C [1] LLS slope - -2.29 - mV/C Tamb = 40 C to +105 C [1] LLS intercept at 0 C - 577.3 - mV [2] 502 - 514 mV Value at 30 C [1] Measured over matrix samples. [2] Measured for samples over process corners. aaa-011334 800 VO (mV) LLS fit 600 400 Measured temperature sensor output measured 200 0 -40 -10 20 50 80 temperature (C) 110 VDDA = 3.3 V; measured on matrix samples. Fig 43. LLS fit of the temperature sensor output voltage LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 83 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 29. Comparator characteristics VDDA = 3.0 V. DLY = 0x0 in the analog comparator CTRL register for shortest propagation delay setting. See the LPC15xx user manual UM10736. Symbol Parameter Conditions Min Typ Max Unit VP > VM - 48 - A VM > VP - 38 - A Static characteristics supply current IDD VIC common-mode input voltage 0 - VDDA V DVO output voltage variation 0 - VDD V Voffset offset voltage VIC = 0.1 V - +/- 3 - mV VIC = 1.5 V - +/- 3 - mV VIC = 2.9 V - +/- 6 - mV - 4.5 6 s Dynamic characteristics tstartup start-up time nominal process tPD propagation delay HIGH to LOW; VDDA = 3.0 V; propagation delay tPD Vhys hysteresis voltage VIC = 0.1 V; 50 mV overdrive input [1] - 86 130 ns VIC = 0.1 V; rail-to-rail input [1] - 196 250 ns VIC = 1.5 V; 50 mV overdrive input [1] - 68 110 ns VIC = 1.5 V; rail-to-rail input [1] - 64 90 ns VIC = 2.9 V; 50 mV overdrive input [1] - 86 130 ns VIC = 2.9 V; rail-to-rail input [1] - 48 80 ns VIC = 0.1 V; 50 mV overdrive input [1] - 98 130 ns VIC = 0.1 V; rail-to-rail input [1] - 24 40 ns VIC = 1.5 V; 50 mV overdrive input [1] - 88 130 ns VIC = 1.5 V; rail-to-rail input [1] - 68 120 ns VIC = 2.9 V; 50 mV overdrive input [1] - 84 110 ns VIC = 2.9 V; rail-to-rail input [1] - 98 180 ns 5 mV 3 - 8 mV 10 mV 8 - 13 mV 17 - 25 mV LOW to HIGH; VDDA = 3.0 V; positive hysteresis; VDDA = 3.0 V; VIC = 1.5 V; settings: [2] 15 mV Vhys hysteresis voltage ladder resistance Rlad negative hysteresis; VDDA = 3.0 V; VIC = 1.5 V; settings: [1][2] 5 mV 3 - 9 mV 10 mV 8 - 18 mV 15 mV 18 - 27 mV - 1 - M - [1] CL = 10 pF; results from measurements on silicon samples over process corners and over the full temperature range Tamb = -40 C to +105 C. [2] Input hysteresis is relative to the reference input channel and is software programmable. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 84 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 30. Comparator voltage ladder dynamic characteristics Symbol Parameter Conditions Min Typ Max Unit ts(pu) power-up settling time to 99% of voltage ladder output value - - 30 s ts(sw) switching settling time to 99% of voltage ladder output value - - 20 s Table 31. Comparator voltage ladder reference static characteristics VDDA = 3.3 V; Tamb = -40 C to + 105C; external or internal reference. Symbol EV(O) LPC15XX Product data sheet Parameter Conditions output voltage error decimal code = 00 Min [2] Typ Max[1] Unit - 0 3 mV decimal code = 08 -1.5 0 +1.5 % decimal code = 16 -1.5 0 +1.5 % decimal code = 24 -1.5 0 +1.5 % decimal code = 30 -1.5 0 +1.5 % decimal code = 31 -1.5 0 +1.5 % [1] Measured over a polyresistor matrix lot with a 2 kHz input signal and overdrive < 100 V. [2] All peripherals except comparator, temperature sensor, and IRC turned off. All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 85 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 14. Application information 14.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 24: * The ADC input trace must be short and as close as possible to the LPC15xx chip. * The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. * If the ADC and the digital core share the same power supply, the power supply line must be adequately filtered. * To improve the ADC performance in a very noisy environment, put the device in Sleep mode during the ADC conversion. 14.2 Suggested USB interface solutions The USB device can be connected to the USB as self-powered device (see Figure 44) or bus-powered device (see Figure 45). On the LPC15xx, the PIO0_3/USB_VBUS pin is 5 V tolerant only when VDD is applied and at operating voltage level. Therefore, if the USB_VBUS function is connected to the USB connector and the device is self-powered, the USB_VBUS pin must be protected for situations when VDD = 0 V. If VDD is always greater than 0 V while VBUS = 5 V, the USB_VBUS pin can be connected directly to the VBUS pin on the USB connector. For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin, precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum allowable voltage on the USB_VBUS pin in this case. One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the USB connector. The voltage divider ratio should be such that the USB_VBUS pin will be greater than 0.7VDD to indicate a logic HIGH while below the 3.6 V allowable maximum voltage. For the following operating conditions VBUSmax = 5.25 V VDD = 3.6 V, the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 86 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC1xxx VDD USB_CONNECT R2 R3 USB R1 1.5 k USB_VBUS RS = 33 USB_DP RS = 33 USB_DM USB-B connector VSS aaa-010820 Fig 44. USB interface on a self-powered device where USB_VBUS = 5 V For a bus-powered device, the VBUS signal does not need to be connected to the USB_VBUS pin (see Figure 45). The USB_CONNECT function can additionally be enabled internally by setting the DCON bit in the DEVCMDSTAT register to prevent the USB from timing out when there is a significant delay between power-up and handling USB traffic. External circuitry is not required for the USB_CONNECT functionality. LPC1xxx VDD REGULATOR USB_CONNECT USB R1 1.5 k VBUS RS = 33 USB_DP RS = 33 USB_DM USB-B connector VSS aaa-010821 Fig 45. USB interface on a bus-powered device Remark: When a bus-powered circuit as shown in Figure 45 is used or, for a self-powered device, when the VBUS pin is not connected, configure the PIO0_3/USB_VBUS pin for GPIO (PIO0_3) in the IOCON block. This ties the VBUS signal HIGH internally. 14.2.1 USB Low-speed operation The USB device controller can be used in low-speed mode supporting 1.5 Mbit/s data exchange with a USB host controller. Remark: To operate in low-speed mode, change the board connections as follows: 1. Connect USB_DP to the D- pin of the connector. 2. Connect USB_DM to the D+ pin of the connector. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 87 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller External 10 resistors are recommended in low-speed mode to reduce over-shoots and accommodate for 5 m cable length required for USB-IF testing. 14.3 XTAL input and crystal oscillator component selection The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. LPC1xxx XTALIN Ci 100 pF Cg 002aae788 Fig 46. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 46), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 47 and in Table 32 and Table 33. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 47 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer (see Table 32). LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 88 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC1xxx L XTALIN XTALOUT CL = CP XTAL RS CX2 CX1 002aaf424 Fig 47. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 32. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 1 MHz to 5 MHz 10 pF < 300 18 pF, 18 pF 20 pF < 300 39 pF, 39 pF 30 pF < 300 57 pF, 57 pF 10 pF < 300 18 pF, 18 pF 20 pF < 200 39 pF, 39 pF 5 MHz to 10 MHz 10 MHz to 15 MHz 15 MHz to 20 MHz Table 33. 30 pF < 100 57 pF, 57 pF 10 pF < 160 18 pF, 18 pF 20 pF < 60 39 pF, 39 pF 10 pF < 80 18 pF, 18 pF Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180 18 pF, 18 pF 20 pF < 100 39 pF, 39 pF 10 pF < 160 18 pF, 18 pF 20 pF < 80 39 pF, 39 pF 20 MHz to 25 MHz 14.4 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plane. Loops must be made as small as possible in LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 89 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Smaller values of Cx1 and Cx2 should be chosen according to the increase in parasitics of the PCB layout. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 90 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 14.5 RTC oscillator component selection The 32 kHz crystal must be connected to the part via the RTCXIN and RTCXOUT pins as shown in Figure 48. If the RTC is not used, the RTCXIN pin can be grounded. LPC1xxx L RTCXIN RTCXOUT = CL CP XTAL RS CX2 CX1 aaa-010822 Fig 48. RTC oscillator components Select Cx1 and Cx2 based on the external 32 kHz crystal used in the application circuitry.The pad capacitance CP of the RTCXIN and RTCXOUT pad is 3 pF. If the external crystal's load capacitance is CL, the optimal Cx1 and Cx2 can be selected as: Cx1 = Cx2 = 2 x CL - CP 14.6 Connecting power, clocks, and debug functions Figure 49 shows the basic board connections used to power the LPC15xx, connect the external crystal and the 32 kHz oscillator for the RTC, and provide debug capabilities via the serial wire port. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 91 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 3.3 V 3.3 V SWD connector ~10 k - 100 k Note 6 SWDIO/PIO0_20/ SCT1_OUT6/TMS 1 2 3 4 5 6 n.c. 7 8 n.c. 9 10 SWCLK/PIO0_19/TCK XTALIN C1 n.c. Note 1 ~10 k - 100 k C2 XTALOUT DGND DGND RESET/PIO0_21 RTCXIN Note 2 C3 VSS C4 RTCXOUT DGND DGND DGND Note 3 VDD (3 to 6 pins) VSSA 0.1 F 3.3 V 0.01 F LPC15xx AGND DGND ISP_0 Note 4 3.3 V VDDA Note 8 ISP select pins ISP_1 10 F 0.1 F Note 7 pins with analog functions DGND Note 4 VREFP_ADC/VREFP_DAC_VDDCMP 3.3 V 10 F 0.1 F 0.1 F VREFN AGND AGND Note 5 3.3 V VBAT 0.1 F AGND DGND DGND aaa-018157 (1) See Section 14.3 "XTAL input and crystal oscillator component selection" for the values of C1 and C2. (2) See Section 14.5 "RTC oscillator component selection" for the values of C3 and C4. (3) Position the decoupling capacitors of 0.1 F and 0.01 F as close as possible to the VDD pin. Add one set of decoupling capacitors to each VDD pin. (4) Position the decoupling capacitors of 0.1 F as close as possible to the VREFN and VDDA pins. The 10 F bypass capacitor filters the power line. Tie VDDA and VREFP to VDD if the ADC is not used. Tie VREFN to VSS if ADC is not used. (5) Position the decoupling capacitor of 0.1 F as close as possible to the VBAT pin. Tie VBAT to VDD if not used. (6) Uses the ARM 10-pin interface for SWD. (7) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see Ref. 3. (8) ISP pin assignments is dependent on package type. See Table 7 "Pin assignments for ISP modes". Fig 49. Power, clock, and debug connections LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 92 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 14.7 Termination of unused pins Table 34 shows how to terminate pins that are not used in the application. In many cases, unused pins may should be connected externally or configured correctly by software to minimize the overall power consumption of the part. Unused pins with GPIO function should be configured as GPIO (switch matrix default) and setto outputs driving LOW with their internal pull-up disabled. To drive the output LOW, select output in the GPIO DIR register, and write a 0 to the GPIO PORT register for that pin. Disable the pull-up in the pin's IOCON register. In addition, it is recommended to configure all GPIO pins that are not bonded out on smaller packages as outputs driven LOW with their internal pull-up disabled. Table 34. Termination of unused pins Pin Default state[1] Recommended termination of unused pins RESET/PIO0_21 I; PU In an application that does not use the RESET pin or its GPIO function, the termination of this pin depends on whether Deep power-down mode is used: * Deep power-down used: Connect an external pull-up resistor and keep pin in default state (input, pull-up enabled) during all other power modes. * Deep power-down not used and no external pull-up connected: can be left unconnected if internal pull-up is disabled and pin is driven LOW and configured as output by software. all PIOn_m (not open-drain) I; PU Can be left unconnected if driven LOW and configured as GPIO output with pull-up disabled by software. PIOn_m (I2C open-drain) IA Can be left unconnected if driven LOW and configured as GPIO output by software. USB_DP/USB_DM F Can be left unconnected. When the USP PHY is disabled, the pins are LOW. RTCXIN - Connect to ground. When grounded, the RTC oscillator is disabled. RTCXOUT - Can be left unconnected. VREFP_DAC_VDDCMP - Tie to VDD. VREFP_ADC Tie to VDD. VREFN - Tie to VSS. VDDA - Tie to VDD. VBAT - Tie to VDD if no external battery connected. VSSA - Tie to VSS. [1] I = Input, O = Output, IA = Inactive (no pull-up/pull-down enabled), F = floating, PU = Pull-Up. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 93 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 14.8 Pin states in different power modes Table 35. Pin states in different power modes Pin Active Sleep Deep-sleep/Powerdown PIOn_m pins (not As configured in the IOCON[1]. Default: internal pull-up enabled. I2C) Deep power-down Floating. PIO0_22, PIO0_23 (open-drain I2C-bus pins) As configured in the IOCON[1]. Floating. RESET/PIO0_21 Reset function enabled. Default: input, internal pull-up enabled. Reset function disabled; floating; if the part is in deep power-down mode, addan external pull-up to the RESET pin to reduce power consumption. PIO0_17/ WAKEUP/TRST As configured in the IOCON[1]. WAKEUP function inactive. Wake-up function enabled; can be disabled by software. [1] Default and programmed pin states are retained in sleep, deep-sleep, and power-down modes. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 94 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 14.9 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for part LPC1549JBD100. Table 36. ElectroMagnetic Compatibility (EMC) for part LPC1549 (TEM-cell method) VDD = 3.3 V; Tamb = 25 C. Parameter Frequency band System clock = 12 MHz Unit 24 MHz 36 MHz 48 MHz 60 MHz 72 MHz Input clock: IRC (12 MHz) maximum peak level IEC level[1] 1 MHz to 30 MHz -5 -1 -5 -4 -3 0 dBV 30 MHz to 150 MHz -1 +3 +6 +8 +11 +14 dBV 150 MHz to 1 GHz -1 +2 +5 +10 +9 +11 dBV - O O O N N M - Input clock: crystal oscillator (12 MHz) maximum peak level 1 MHz to 30 MHz -2 0 -5 -2 -2 2 dBV 30 MHz to 150 MHz 0 +3 +6 +8 +12 +14 dBV 150 MHz to 1 GHz -1 +3 +5 +10 +10 +11 dBV - O O O N N M - IEC level[1] [1] IEC levels refer to Appendix D in the IEC61967-2 Specification. LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 95 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) 0.95 0.55 7o o 0 0.95 0.55 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT313-2 136E05 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 50. Package outline LQFP48 (SOT313-2) LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 96 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.5 HD HE 12.15 12.15 11.85 11.85 L Lp v w y 1 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT314-2 136E10 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 51. Package outline LQFP64 (SOT314-2) LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 97 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e E HE A A2 (A 3) A1 w M bp Lp pin 1 index L 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 14.1 13.9 0.5 HD HE 16.25 16.25 15.75 15.75 L Lp v w y 1 0.75 0.45 0.2 0.08 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT407-1 136E20 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-01 03-02-20 Fig 52. Package outline LQFP100 (SOT407-1) LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 98 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 16. Soldering Footprint information for reflow soldering of LQFP48 package SOT313-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8x) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 0.500 0.560 Ax Ay 10.350 10.350 Bx By C D1 D2 Gx 7.350 7.350 1.500 0.280 0.500 7.500 Gy Hx Hy 7.500 10.650 10.650 sot313-2_fr Fig 53. Reflow soldering for the LQFP48 package LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 99 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP64 package SOT314-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8x) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 13.300 13.300 10.300 10.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 10.500 10.500 13.550 13.550 sot314-2_fr Fig 54. Reflow soldering for the LQFP64 package LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 100 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP100 package SOT407-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8x) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 17.300 17.300 14.300 14.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 14.500 14.500 17.550 17.550 sot407-1 Fig 55. Reflow soldering for the LQFP100 package LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 101 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 17. References LPC15XX Product data sheet [1] LPC15xx User manual UM10736: http://www.nxp.com/documents/user_manual/UM10736.pdf [2] LPC15xx Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC15XX.pdf [3] Technical note ADC design guidelines: http://www.nxp.com/documents/technical_note/TN00009.pdf All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 102 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 18. Revision history Table 37. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC15XX v.1.1 20150429 Product data sheet - LPC15XX v.1 Modifications: LPC15XX v.1 LPC15XX Product data sheet * Pin description table updated for clarification (I2C-bus pins, VBAT, WAKEUP, RTCXIN/OUT). * * * * * * * Table note 11 added in Table 3. Section 14.1 "ADC usage notes" added. Section 14.6 "Connecting power, clocks, and debug functions" added. Section 14.7 "Termination of unused pins" added. Section 14.8 "Pin states in different power modes" added. Section 14.9 "ElectroMagnetic Compatibility (EMC)" added. Table 11 "Static characteristics": Changed the power-down max specification value: IDD Power-down mode; VDD = 3.3 V Tamb = 25 C from 8 A to 15 A. <tbd> Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 - (c) NXP Semiconductors N.V. 2015. All rights reserved. 103 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 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This document supersedes and replaces all information supplied prior to the publication hereof. LPC15XX Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 104 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP Semiconductors N.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 105 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 8 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Functional description . . . . . . . . . . . . . . . . . . 21 8.1 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 21 8.2 Memory Protection Unit (MPU). . . . . . . . . . . . 21 8.3 On-chip flash programming memory . . . . . . . 22 8.3.1 ISP pin configuration . . . . . . . . . . . . . . . . . . . 22 8.4 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.5 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.6 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.7 AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 25 8.8 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.9 Nested Vectored Interrupt controller (NVIC) . . 27 8.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.9.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 27 8.10 IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.10.2 Standard I/O pad configuration . . . . . . . . . . . . 27 8.11 Switch Matrix (SWM) . . . . . . . . . . . . . . . . . . . 28 8.12 Fast General-Purpose parallel I/O (GPIO) . . . 29 8.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.13 Pin interrupt/pattern match engine (PINT) . . . 29 8.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.14 GPIO group interrupts (GINT0/1) . . . . . . . . . . 30 8.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.15 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 30 8.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.16 Input multiplexing (Input mux) . . . . . . . . . . . . 31 8.17 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 31 8.17.1 Full-speed USB device controller . . . . . . . . . . 31 8.17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.18 USART0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.19 SPI0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.20 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 33 8.20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.21 C_CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.21.1 8.22 8.22.1 8.22.2 8.22.3 8.22.3.1 8.22.4 8.22.4.1 8.22.5 8.22.5.1 8.23 8.23.1 8.24 8.24.1 8.25 8.25.1 8.26 8.26.1 8.27 8.28 8.29 8.29.1 8.30 8.30.1 8.31 8.31.1 8.32 8.33 8.33.1 8.34 8.35 8.36 8.36.1 8.36.2 8.36.3 8.36.4 8.37 8.38 8.39 8.40 8.40.1 8.40.2 8.40.3 8.40.4 8.40.5 8.41 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PWM/timer/motor control subsystem . . . . . . . 34 SCtimer/PWM subsystem . . . . . . . . . . . . . . . 34 Timer controlled subsystem . . . . . . . . . . . . . . 35 SCTimer/PWM in the large configuration (SCT0/1) 36 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 State-Configurable Timers in the small configuration (SCT2/3). . . . . . . . . . . . . . . . . . 38 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SCT Input processing unit (SCTIPU) . . . . . . . 39 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Quadrature Encoder Interface (QEI) . . . . . . . 40 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Analog-to-Digital Converter (ADC). . . . . . . . . 40 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Digital-to-Analog Converter (DAC). . . . . . . . . 41 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Analog comparator (ACMP) . . . . . . . . . . . . . . 41 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Temperature sensor . . . . . . . . . . . . . . . . . . . . 42 Internal voltage reference . . . . . . . . . . . . . . . 42 Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 43 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Windowed WatchDog Timer (WWDT) . . . . . . 43 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 44 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 System tick timer . . . . . . . . . . . . . . . . . . . . . . 44 Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . 44 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Clock generation . . . . . . . . . . . . . . . . . . . . . . 45 Power domains . . . . . . . . . . . . . . . . . . . . . . . 46 Integrated oscillators . . . . . . . . . . . . . . . . . . . 46 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 47 System oscillator . . . . . . . . . . . . . . . . . . . . . . 47 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 47 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 47 System PLL, USB PLL, and SCT PLL . . . . . . 47 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 48 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 48 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 48 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 49 Power-down mode . . . . . . . . . . . . . . . . . . . . . 49 Deep power-down mode . . . . . . . . . . . . . . . . 49 System control . . . . . . . . . . . . . . . . . . . . . . . . 50 continued >> LPC15XX Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.1 -- 29 April 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 106 of 107 LPC15xx NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8.41.1 8.41.2 8.41.3 8.42 9 10 11 11.1 11.2 11.3 11.4 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 13 14 14.1 14.2 14.2.1 14.3 14.4 14.5 14.6 14.7 14.8 14.9 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Brownout detection . . . . . . . . . . . . . . . . . . . . . 50 Code security (Code Read Protection - CRP) 50 Emulation and debugging . . . . . . . . . . . . . . . . 52 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 52 Thermal characteristics . . . . . . . . . . . . . . . . . 53 Static characteristics. . . . . . . . . . . . . . . . . . . . 55 Power consumption . . . . . . . . . . . . . . . . . . . . 60 CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 64 Peripheral power consumption . . . . . . . . . . . . 65 Electrical pin characteristics . . . . . . . . . . . . . . 66 Dynamic characteristics . . . . . . . . . . . . . . . . . 70 Flash/EEPROM memory . . . . . . . . . . . . . . . . 70 External clock for the oscillator in slave mode 70 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 71 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 74 USART interface. . . . . . . . . . . . . . . . . . . . . . . 76 SCTimer/PWM output timing . . . . . . . . . . . . . 77 Characteristics of analog peripherals . . . . . . 77 Application information. . . . . . . . . . . . . . . . . . 86 ADC usage notes . . . . . . . . . . . . . . . . . . . . . . 86 Suggested USB interface solutions . . . . . . . . 86 USB Low-speed operation . . . . . . . . . . . . . . . 87 XTAL input and crystal oscillator component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 XTAL Printed-Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 RTC oscillator component selection . . . . . . . . 91 Connecting power, clocks, and debug functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Termination of unused pins. . . . . . . . . . . . . . . 93 Pin states in different power modes . . . . . . . . 94 ElectroMagnetic Compatibility (EMC) . . . . . . . 95 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 96 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Revision history . . . . . . . . . . . . . . . . . . . . . . . 103 Legal information. . . . . . . . . . . . . . . . . . . . . . 104 Data sheet status . . . . . . . . . . . . . . . . . . . . . 104 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 105 Contact information. . . . . . . . . . . . . . . . . . . . 105 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 April 2015 Document identifier: LPC15XX