2300 MHz to 3000 MHz Quadrature Modulator ADL5373 Output frequency range: 2300 MHz to 3000 MHz Modulation bandwidth: >500 MHz (3 dB) Output third-order intercept: 26 dBm @ 2500 MHz 1 dB output compression: 13.8 dBm @ 2500 MHz Noise floor: -157.1 dBm/Hz @ 2500 MHz Sideband suppression: -57 dBc @ 2500 MHz Carrier feedthrough: -32 dBm @ 2500 MHz Single supply: 4.75 V to 5.25 V 24-lead LFCSP FUNCTIONAL BLOCK DIAGRAM IBBP IBBN LOIP LOIN QUADRATURE PHASE SPLITTER QBBN QBBP APPLICATIONS WiMAX/broadband wireless access systems Satellite modems VOUT 06664-001 FEATURES Figure 1. GENERAL DESCRIPTION The ADL5373 supports a frequency of operation from 2300 MHz to 3000 MHz and is a pin-compatible member of the fixed gain quadrature modulator (F-MOD) family designed for use from 300 MHz to 4000 MHz. The ADL5373 provides excellent phase accuracy and amplitude balance enabling high performance intermediate frequency or direct radio frequency modulation for communications systems. The ADL5373 provides a >500 MHz, 3 dB baseband bandwidth, making it ideally suited for use in broadband zero IF or low IF-to-RF applications and in broadband digital predistortion transmitters. The ADL5373 accepts two differential baseband inputs that are mixed with a local oscillator (LO) to generate a singleended output. The ADL5373 is fabricated using the Analog Devices, Inc. advanced silicon-germanium bipolar process. It is available in a 24-lead, exposed paddle, Pb-free LFCSP. Performance is specified over a -40C to +85C temperature range. A Pb-free evaluation board is available. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007-2008 Analog Devices, Inc. All rights reserved. ADL5373 TABLE OF CONTENTS Features .............................................................................................. 1 RF Output.................................................................................... 12 Applications....................................................................................... 1 Optimization............................................................................... 13 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 14 General Description ......................................................................... 1 DAC Modulator Interfacing ..................................................... 14 Revision History ............................................................................... 2 Limiting the AC Swing .............................................................. 14 Specifications..................................................................................... 3 Filtering........................................................................................ 14 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Using the AD9779 Auxiliary DAC for Carrier Feedthrough Nulling ......................................................................................... 15 Pin Configuration and Function Descriptions............................. 6 WiMAX Operation .................................................................... 15 Typical Performance Characteristics ............................................. 7 LO Generation Using PLLs ....................................................... 16 Theory of Operation ...................................................................... 11 Transmit DAC Options ............................................................. 16 Circuit Description..................................................................... 11 Modulator/Demodulator Options ........................................... 16 Basic Connections .......................................................................... 12 Evaluation Board ............................................................................ 17 Power Supply and Grounding................................................... 12 Characterization Setup .................................................................. 18 Baseband Inputs.......................................................................... 12 Outline Dimensions ....................................................................... 20 LO Input ...................................................................................... 12 Ordering Guide .......................................................................... 20 REVISION HISTORY 2/08--Rev. 0 to Rev. A Changes to Features and General Description ............................. 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 5 Changes to Figure 3, Figure 4, and Figure 6 to Figure 8.............. 7 Changes to Figure 9 to Figure 14.................................................... 8 Changes to Figure 15 to Figure 20.................................................. 9 Changes to Figure 21 to Figure 23................................................ 10 Changes to Optimization Section and Figure 27 ....................... 13 Changes to Figure 35...................................................................... 15 Changes to WiMAX Operation Section and Figure 36............. 16 Changes to Evaluation Board Section.......................................... 17 Changes to Characterization Setup Section................................ 18 6/07--Revision 0: Initial Version Rev. A | Page 2 of 20 ADL5373 SPECIFICATIONS VS = 5 V, TA = 25C, LO = 0 dBm 1 , baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV dc bias, baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted. Table 1. Parameter OPERATING FREQUENCY RANGE LO = 2300 MHz Output Power Output P1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 WiMAX 802.16e LO = 2500 MHz Output Power Output P1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 Noise Floor WiMAX 802.16e LO = 2700 MHz Output Power Output P1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 WiMAX 802.16e LO INPUTS LO Drive Level1 Input Return Loss Conditions Low frequency High frequency Min VIQ = 1.4 V p-p differential POUT - P(fLO (2 x fBB)), POUT = 4.6 dBm POUT - P(fLO (3 x fBB)), POUT = 4.6 dBm f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = -1.5 dBm per tone f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = -1.5 dBm per tone 10 MHz carrier bandwidth (1024 subcarriers), 64 QAM signal, 30 MHz carrier offset, POUT = -10 dBm, PLO = 0 dBm VIQ = 1.4 V p-p differential POUT - P(fLO (2 x fBB)), POUT = 7.1 dBm POUT - P(fLO (3 x fBB)), POUT = 7.1 dBm f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = 1.1 dBm per tone f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = 1.1 dBm per tone I/Q inputs = 0 V differential with a 500 mV common-mode bias, 20 MHz carrier offset 10 MHz carrier bandwidth (1024 subcarriers), 64 QAM signal, 30 MHz carrier offset, POUT = -10 dBm, PLO = 0 dBm VIQ = 1.4 V p-p differential POUT - P(fLO (2 x fBB)), POUT = 7.7 dBm POUT - P(fLO (3 x fBB)), POUT = 7.7 dBm f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = 1.6 dBm per tone f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = 1.6 dBm per tone 10 MHz carrier bandwidth (1024 subcarriers), 64 QAM signal, 30 MHz carrier offset, POUT = -10 dBm, PLO = 0 dBm Characterization performed at typical level See Figure 9 for a plot of return loss vs. frequency Rev. A | Page 3 of 20 -6 Typ 2300 3000 Max Unit MHz MHz 4.2 11.0 -35 -57 <0.2 0.06 -58 -49 56 25 -158.6 dBm dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz 7.1 13.8 -32 -57 0.3 0.06 -57 -47 58 26 -157.1 dBm dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz -157.4 dBm/Hz 7.7 13.8 -33 -54 <0.2 0.07 -55 -47 57 25 -155.3 dBm dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz 0 -6 +6 dBm dB ADL5373 Parameter BASEBAND INPUTS I and Q Input Bias Level Input Bias Current Input Offset Current Differential Input Impedance Bandwidth 0.1 dB 1 dB POWER SUPPLIES Voltage Supply Current 1 2 Conditions Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN Min Current sourcing from each baseband input with a bias of 500 mV dc 2 fBB = 1 MHz LO = 2500 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc Typ Max Unit 500 45 mV A 0.1 40||1.5 A k||pF 70 350 MHz MHz Pin VPS1 and Pin VPS2 4.75 5.25 174 Driven through Johanson Technology balun (Model 2450BL15B050) See V-to-I Converter section for architecture information. Rev. A | Page 4 of 20 V mA ADL5373 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VPSx IBBP, IBBN, QBBP, and QBBN LOIP and LOIN Internal Power Dissipation JA (Exposed Paddle Soldered Down) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 0 V to 2 V 13 dBm 1119 mW 54C/W 150C -40C to +85C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. A | Page 5 of 20 ADL5373 24 23 22 21 20 19 QBBP QBBN COM4 COM4 IBBN IBBP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADL5373 TOP VIEW (Not to Scale) 18 17 16 15 14 13 VPS5 VPS4 VPS3 VPS2 VPS2 VOUT 06664-002 1 2 3 4 5 6 COM2 7 LOIP 8 LOIN 9 COM2 10 COM3 11 COM3 12 COM1 COM1 VPS1 VPS1 VPS1 VPS1 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 2, 7, 10 to 12, 21, 22 3 to 6, 14 to 18 Mnemonic COM1 to COM4 VPS1 to VPS5 8, 9 LOIP, LOIN 13 VOUT 19, 20, 23, 24 IBBP, IBBN, QBBN, QBBP Exposed Paddle Description Input Common Pins. Connect to ground plane via a low impedance path. Positive Supply Voltage Pins. All pins should be connected to the same supply (VS). To ensure adequate external bypassing, connect 0.1 F capacitors between each pin and ground. Adjacent power supply pins of the same name can share one capacitor (see Figure 25). 50 Differential Local Oscillator Input. Internally dc-biased. Pins must be ac-coupled. See Figure 8 for LO input impedance. Device Output. Single-ended RF output. Pin should be ac-coupled to the load. The output is ground referenced. Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be dc-biased to 500 mV dc and must be driven from a low impedance source. Nominal characterized ac signal swing is 700 mV p-p on each pin. This results in a differential drive of 1.4 V p-p with a 500 mV dc bias. These inputs are not self-biased and must be externally biased. Connect to the ground plane via a low impedance path. Rev. A | Page 6 of 20 ADL5373 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25C, LO = 0 dBm, baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV dc bias, baseband I/Q frequency (fBB) = 1 MHz, unless otherwise noted. 10 17 16 8 7 6 TA = +25C 5 TA = +85C 4 3 2 1 0 2300 2400 2500 2600 2700 2800 2900 TA = -40C 15 14 13 TA = +25C 12 11 TA = +85C 10 9 06664-006 1dB OUTPUT COMPRESSION (dBm) TA = -40C 06664-003 8 7 2300 3000 2400 LO FREQUENCY (MHz) 2700 2800 17 16 1dB OUTPUT COMPRESSION (dBm) VS = 5.0V 8 VS = 4.75V VS = 5.25V 6 5 4 3 06664-004 2 1 0 2300 2400 2500 2600 2700 2800 2900 VS = 5.25V VS = 5.0V 15 14 13 12 VS = 4.75V 11 10 9 06664-007 9 8 7 2300 3000 2400 LO FREQUENCY (MHz) 2500 2600 2700 2800 3000 2900 LO FREQUENCY (MHz) Figure 4. Single Sideband (SSB) Output Power (POUT) vs. fLO and Supply Figure 7. SSB Output P1dB Compression Point (OP1dB) vs. fLO and Supply 90 5 60 120 2300MHz 150 30 3000MHz 0 180 0 2300MHz 330 210 3000MHz -5 1 10 100 BASEBAND FREQUENCY (MHz) 1000 06664-005 OUTPUT POWER VARIANCE (dB) 3000 2900 Figure 6. SSB Output P1dB Compression Point (OP1dB) vs. fLO and Temperature 10 SSB OUTPUT POWER (dBm) 2600 LO FREQUENCY (MHz) Figure 3. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO) and Temperature 7 2500 Figure 5. I and Q Input Bandwidth Normalized to Gain @ 1 MHz (fLO = 2500 MHz) 240 S11 OF LO S22 OF OUTPUT 270 300 06664-008 SSB OUTPUT POWER (dBm) 9 Figure 8. Smith Chart of LOIP (LOIN AC-Coupled to Ground) S11 and VOUT S22 (fLO from 2300 MHz to 3000 MHz) Rev. A | Page 7 of 20 ADL5373 0 0 -10 SIDEBAND SUPPRESSION (dBc) -10 -15 -20 2600 2700 2800 2900 -50 -60 06664-012 -80 2300 3000 2400 2500 LO FREQUENCY (MHz) 0 0 -10 -10 TA = -40C -30 -40 TA = +25C TA = +85C -50 -60 2400 2500 2600 2700 2800 2900 -30 -40 TA = -40C TA = +85C -50 -60 -80 2300 3000 TA = +25C 2400 2500 2600 2700 2800 3000 2900 LO FREQUENCY (MHz) Figure 13. Sideband Suppression vs. fLO and Temperature after Nulling at 25C; Multiple Devices Shown Figure 10. Carrier Feedthrough vs. fLO and Temperature; Multiple Devices Shown 0 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, SIDEBAND SUPPRESSION -20 -10 CARRIER FEEDTHROUGH (dBm) 3000 2900 -20 LO FREQUENCY (MHz) -20 -30 -40 TA = -40C TA = +85C -50 -60 06664-011 -70 -80 2300 2800 -70 06664-010 -70 -80 2300 2700 Figure 12. Sideband Suppression vs. fLO and Temperature; Multiple Devices Shown SIDEBAND SUPPRESSION (dBc) CARRIER FEEDTHROUGH (dBm) Figure 9. Return Loss (S11) of LOIP with LOIN AC-Coupled to Ground vs. fLO -20 2600 LO FREQUENCY (MHz) 06664-013 2500 TA = +85C TA = -40C TA = +25C -40 TA = +25C 2400 2500 2600 2700 2800 2900 -30 15 CARRIER FEEDTHROUGH (dBm) -40 LO FREQUENCY (MHz) 5 SSB OUTPUT POWER (dBm) THIRD-ORDER DISTORTION (dBc) -50 0 -60 SECOND-ORDER DISTORTION (dBc) SIDEBAND SUPPRESSION (dBc) -70 -80 0.2 3000 10 -5 SSB OUTPUT POWER (dBm) 2400 -30 -70 06664-009 -25 2300 -20 -10 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 -15 BASEBAND INPUT VOLTAGE (V p-p) Figure 11. Carrier Feedthrough vs. fLO and Temperature after Nulling at 25C; Multiple Devices Shown Figure 14. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level (fLO = 2300 MHz) Rev. A | Page 8 of 20 06664-014 RETURN LOSS (dB) -5 ADL5373 5 SIDEBAND SUPPRESSION (dBc) -50 0 -60 -5 SECOND-ORDER DISTORTION (dBc) THIRD-ORDER DISTORTION (dBc) -80 0.2 0.6 1.0 -10 1.4 1.8 2.2 2.6 3.0 3.4 -15 BASEBAND INPUT VOLTAGE (V p-p) TA = -40C 25 TA = +25C TA = +85C 20 15 10 5 06664-018 10 -40 0 2300 2400 THIRD-ORDER THIRD-ORDER DISTORTION DISTORTION TA = -40C TA = +25C -50 SECOND-ORDER DISTORTION TA = +25C -70 2400 SECOND-ORDER DISTORTION TA = -40C 06664-016 SECOND-ORDER DISTORTION TA = +85C -80 2300 2500 2600 2700 2800 2900 70 TA = +25C 2900 3000 TA = +85C 50 40 30 20 10 0 2300 3000 TA = -40C 60 2400 2500 2600 2700 2800 LO FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 19. OIP2 vs. fLO and Temperature Figure 16. Second- and Third-Order Distortion vs. fLO and Temperature (Baseband I/Q Amplitude = 1.4 V p-p Differential) -20 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, SIDEBAND SUPPRESSION -20 CARRIER FEEDTHROUGH (dBm) SIDEBAND SUPPRESSION (dBc) -50 -60 SECOND-ORDER DISTORTION (dBc) 10M BASEBAND FREQUENCY (Hz) 100M Figure 17. Second-Order Distortion, Carrier Feedthrough, and Sideband Suppression vs. fBB (fLO = 2500 MHz) 5 -30 -40 4 SSB OUTPUT POWER (dBm) CARRIER FEEDTHROUGH (dBm) 3 THIRD-ORDER DISTORTION (dBc) 2 -50 SIDEBAND SUPPRESSION (dBc) 1 -60 SECOND-ORDER DISTORTION (dBc) -70 -6 06664-017 SECOND-ORDER DISTORTION, CARRIER FEEDTHROUGH, SIDEBAND SUPPRESSION 3000 SSB OUTPUT POWER (dBm) -60 -80 1M 2900 06664-019 OUTPUT SECOND-ORDER INTERCEPT (dBm) THIRD-ORDER DISTORTION TA = +85C -40 -70 2800 80 -30 -40 2700 Figure 18. OIP3 vs. fLO and Temperature -20 -30 2600 LO FREQUENCY (MHz) Figure 15. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level (fLO = 2700 MHz) SECOND-ORDER DISTORTION AND THIRD-ORDER DISTORTION (dBc) 2500 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 LO AMPLITUDE (dBm) Figure 20. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 2300 MHz) Rev. A | Page 9 of 20 06664-020 -70 OUTPUT THIRD-ORDER INTERCEPT (dBm) CARRIER FEEDTHROUGH (dBm) SSB OUTPUT POWER (dBm) -30 30 15 SSB OUTPUT POWER (dBm) 06664-015 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, SIDEBAND SUPPRESSION -20 ADL5373 25 fLO = 2500MHz 8 20 1 2 3 4 5 6 Figure 21. Second- and Third-Order Distortion, Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. LO Amplitude (fLO = 2700 MHz) 0.20 0.19 VS = 5.25V 0.17 VS = 5.0V 0.16 VS = 4.75V 0.15 0.14 0.13 0.12 06664-022 SUPPLY CURRENT (A) 0.18 0.11 0.10 -40 25 85 TEMPERATURE (C) Figure 22. Power Supply Current vs. Temperature Rev. A | Page 10 of 20 NOISE AT 20MHz OFFSET (dBm/Hz) -155.7 0 06664-023 -1 LO AMPLITUDE (dBm) -155.9 -2 -156.1 -3 -156.3 -4 -156.5 -5 0 3 -156.7 -70 -6 -156.9 SECOND-ORDER DISTORTION (dBc) -157.1 5 -157.3 4 -60 -157.5 SIDEBAND SUPPRESSION (dBc) 10 -157.7 5 15 -157.9 -50 6 -158.1 CARRIER FEEDTHROUGH (dBm) THIRD-ORDER DISTORTION (dBc) -40 QUANTITY 7 -30 SSB OUTPUT POWER (dBm) SSB OUTPUT POWER (dBm) 06664-021 SECOND-ORDER DISTORTION, THIRD-ORDER DISTORTION, CARRIER FEEDTHROUGH, SIDEBAND SUPPRESSION -20 Figure 23. 20 MHz Offset Noise Floor Distribution at fLO = 2500 MHz (I/Q Amplitude = 0 mV p-p with 500 mV dc Bias) ADL5373 THEORY OF OPERATION CIRCUIT DESCRIPTION V-to-I Converter Overview The differential baseband inputs (QBBP, QBBN, IBBN, and IBBP) consist of the bases of the PNP transistors, which present a high impedance. The voltages applied to these pins drive the V-to-I stage that converts baseband voltages into currents. The differential output currents of the V-to-I stages feed each of their respective Gilbert cell mixers. The dc common-mode voltage at the baseband inputs sets the currents in the two mixer cores. Varying the baseband common-mode voltage influences the current in the mixer and affects overall modulator performance. The recommended dc voltage for the baseband common-mode voltage is 500 mV dc. The ADL5373 can be divided into five circuit blocks: the LO interface, the baseband voltage-to-current (V-to-I) converter, the mixers, the differential-to-single-ended (D-to-S) stage, and the bias circuit. A detailed block diagram of the device is shown in Figure 24. LOIP LOIN PHASE SPLITTER Mixers IBBP IBBN 06664-024 QBBP VOUT QBBN Figure 24. Block Diagram The LO interface generates two LO signals in quadrature. These signals are used to drive the mixers. The I and Q baseband input signals are converted to currents by the V-to-I stages, which then drive the two mixers. The outputs of these mixers combine to feed the output balun, which provides a single-ended output. The bias cell generates reference currents for the V-to-I stage. LO Interface The LO interface consists of a polyphase quadrature splitter followed by a limiting amplifier. The LO input impedance is set by the polyphase. For optimal performance, the LO should be driven differentially. Each quadrature LO signal then passes through a limiting amplifier that provides the mixer with a limited drive signal. The ADL5373 has two double balanced mixers: one for the in-phase channel (I-channel) and one for the quadrature channel (Q-channel). Both mixers are based on the Gilbert cell design of four cross-connected transistors. The output currents from the two mixers sum together into a load. The signal developed across this load is used to drive the D-to-S stage. D-to-S Stage The output D-to-S stage consists of an on-chip balun that converts the differential signal to a single-ended signal. The balun presents high impedance to the output (VOUT); therefore, a matching network may be needed at the output for optimal power transfer. Bias Circuit An on-chip band gap reference circuit is used to generate a proportional-to-absolute temperature (PTAT) reference current for the V-to-I stage. Rev. A | Page 11 of 20 ADL5373 BASIC CONNECTIONS Figure 25 shows the basic connections for the ADL5373. The COM1, COM2, COM3, and COM4 pins should be tied to the same ground plane through low impedance paths. Solder the exposed paddle on the underside of the package to a low thermal and electrical impedance ground plane. If the ground plane spans multiple layers on the circuit board, they should be stitched together with nine vias under the exposed paddle. Application Note AN-772 describes the thermal and electrical grounding of the LFCSP in detail. IBBP C16 0.1F 19 IBBP 20 IBBN IBBN 21 COM4 QBBP 24 23 QBBN QBBN 22 COM4 QBBP BASEBAND INPUTS The baseband inputs QBBP, QBBN, IBBP, and IBBN must be driven from a differential source. Bias the nominal drive level of 1.4 V p-p differential (700 mV p-p on each pin) to a commonmode level of 500 mV dc. VPOS C15 0.1F COM1 1 COM1 2 VPS1 3 VPS1 4 VPS1 5 VPS1 18 Z1 F-MOD 17 16 VPS5 VPS4 C14 0.1F VPS3 VPS2 15 VPS2 14 EXPOSED PADDLE 6 C12 0.1F 13 VOUT C11 OPEN VOUT 12 C13 0.1F COM3 11 10 COM3 COM2 9 LOIN 8 LOIP COM2 7 COUT 100pF The dc common-mode bias level for the baseband inputs can range from 400 mV to 600 mV. This results in a reduction in the usable input ac swing range. The nominal dc bias of 500 mV allows for the largest ac swing, limited on the bottom end by the ADL5373 input range and on the top end by the output compliance range on most DACs from Analog Devices. VPOS LO INPUT GND CLOP 100pF RLOP OPEN The LO input should be driven differentially. The recommended balun for the ADL5373 is the Johanson Technology model 2450BL15B050. The LO pins should be ac-coupled to the balun. CLON 100pF 4 3 5 2 NC 6 1 RLON OPEN 06664-025 LO T1 JOHANSON TECHNOLOGY 2450BL15B050 Figure 25. Basic Connections for the ADL5373 POWER SUPPLY AND GROUNDING All the VPS pins must be connected to the same 5 V source. Adjacent pins of the same name can be tied together and decoupled with a 0.1 F capacitor. Locate these capacitors as close as possible to the device. The power supply can range between 4.75 V and 5.25 V. The nominal LO drive of 0 dBm can be increased to up to 6 dBm to realize an improvement in the noise performance of the modulator. If the LO source cannot provide the 0 dBm level, operation at a reduced power below 0 dBm is acceptable. Reduced LO drive results in slightly increased modulator noise. The effect of LO power on sideband suppression and carrier feedthrough is shown in Figure 20 and Figure 21. RF OUTPUT The RF output is available at the VOUT pin (Pin 13). The VOUT pin connects to an internal balun, which is capable of driving a 50 load. For applications requiring 50 output impedance, external matching is needed (see Figure 8 for S22 performance). The internal balun provides a low dc path to ground. In most situations, the VOUT pin should be ac-coupled to the load. Rev. A | Page 12 of 20 ADL5373 OPTIMIZATION The carrier feedthrough and sideband suppression performance of the ADL5373 can be improved by using optimization techniques. It is often desirable to perform a one-time carrier null calibration. This is usually performed at a single frequency. Figure 27 shows how carrier feedthrough varies with LO frequency over a range of 100 MHz on either side of a null at 2600 MHz. -30 -60 -40 -50 -60 -70 -80 -90 2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700 06664-041 Carrier feedthrough results from minute dc offsets that occur between each of the differential baseband inputs. In an ideal modulator, the quantities (VIOPP - VIOPN) and (VQOPP - VQOPN) are equal to zero, which results in no carrier feedthrough. In a real modulator, those two quantities are nonzero and, when mixed with the LO, they result in a finite amount of carrier feedthrough. The ADL5373 is designed to provide a minimal amount of carrier feedthrough. Should even lower carrier feedthrough levels be required, minor adjustments can be made to the (VIOPP - VIOPN) and (VQOPP - VQOPN) offsets. The I-channel offset is held constant while the Q-channel offset is varied until a minimum carrier feedthrough level is obtained. The Q-channel offset required to achieve this minimum is held constant, while the offset on the I-channel is adjusted until a new minimum is reached. Through two iterations of this process, the carrier feedthrough can be reduced to as low as the output noise. The ability to null is sometimes limited by the resolution of the offset adjustment. Figure 26 shows the relationship of carrier feedthrough vs. dc offset as null. CARRIER FEEDTHROUGH (dBm) Carrier Feedthrough Nulling LO FREQUENCY (MHz) Figure 27. Carrier Feedthrough vs. Frequency After Nulling at 2600 MHz Sideband Suppression Optimization Sideband suppression results from relative gain and relative phase offsets between the I channel and Q channel and can be suppressed through adjustments to those two parameters. Figure 28 illustrates how sideband suppression is affected by the gain and phase imbalances. 0 -10 -72 -76 -80 -88 -300 -240 -180 -120 06664-026 -84 -60 0 60 120 180 240 300 The same applies to the Q channel. -70 0dB 0.1 1 10 100 PHASE ERROR (Degrees) Note that throughout the nulling process, the dc bias for the baseband inputs remains at 500 mV. When no offset is applied, VIOPP = 500 mV + VIOS/2, and VIOPN = 500 mV - VIOS/2, such that VIOPP - VIOPN = VIOS -50 0.05dB 0.025dB -60 0.0125dB -90 0.01 Figure 26. Carrier Feedthrough vs. DC Offset Voltage at 2500 MHz When an offset of +VIOS is applied to the I-channel inputs, -30 0.5dB 0.25dB -40 0.125dB -80 VP - VN OFFSET (V) VIOPP = VIOPN = 500 mV, or VIOPP - VIOPN = VIOS = 0 V 2.5dB -20 1.25dB 06664-028 -68 SIDEBAND SUPPRESSION (dBc) CARRIER FEEDTHROUGH (dBm) -64 Figure 28. Sideband Suppression vs. Quadrature Phase Error for Various Quadrature Amplitude Offsets Figure 28 underlines the fact that adjusting only one parameter improves the sideband suppression only to a point, unless the other parameter is also adjusted. For example, if the amplitude offset is 0.25 dB, improving the phase imbalance better than 1 does not yield any improvement in the sideband suppression. For optimum sideband suppression, an iterative adjustment between phase and amplitude is required. The sideband suppression nulling can be performed either through adjusting the gain for each channel or through the modification of the phase and gain of the digital data coming from the digital signal processor. Rev. A | Page 13 of 20 ADL5373 APPLICATIONS INFORMATION AD9779 The ADL5373 is designed to interface with minimal components to members of the Analog Devices family of DACs. These DACs feature an output current swing from 0 mA to 20 mA, and the interface described in this section can be used with any DAC that has a similar output. F-MOD OUT1_P AD9779 OUT1_P F-MOD 93 19 IBBP RBIP 50 OUT1_N 92 RBIN 50 20 19 RBIP 50 OUT1_N Driving the ADL5373 with a TxDAC(R) An example of the interface using the AD9779 TxDAC is shown in Figure 29. The baseband inputs of the ADL5373 require a dc bias of 500 mV. The average output current on each of the outputs of the AD9779 is 10 mA. Therefore, a single 50 resistor to ground from each of the DAC outputs results in an average current of 10 mA flowing through each of the resistors, thus producing the desired 500 mV dc bias for the inputs to the ADL5373. 93 OUT2_N OUT2_P 92 IBBP RSLI 100 RBIN 50 20 84 23 RBQN 50 RBQP 50 83 IBBN QBBN RSLQ 100 24 06664-030 DAC MODULATOR INTERFACING QBBP Figure 30. AC Voltage Swing Reduction Through the Introduction of a Shunt Resistor Between a Differential Pair The value of this ac voltage swing limiting resistor is chosen based on the desired ac voltage swing. Figure 31 shows the relationship between the swing limiting resistor and the peakto-peak ac swing that it produces when 50 bias setting resistors are used. 2.0 IBBN RBQN 50 RBQP 50 83 23 24 QBBN QBBP Figure 29. Interface Between the AD9779 and ADL5373 with 50 Resistors to Ground to Establish the 500 mV DC Bias for the ADL5373 Baseband Inputs The AD9779 output currents have a swing that ranges from 0 mA to 20 mA. With the 50 resistors in place, the ac voltage swing going into the ADL5373 baseband inputs ranges from 0 V to 1 V. A full-scale sine wave out of the AD9779 can be described as a 1 V p-p single-ended (or 2 V p-p differential) sine wave with a 500 mV dc bias. 1.6 1.4 1.2 1.0 0.8 0.6 0.4 06664-031 OUT2_P 84 06664-029 OUT2_N DIFFERENTIAL SWING (V p-p) 1.8 0.2 0 10 100 1000 10000 RL () Figure 31. Relationship Between the AC Swing Limiting Resistor and the Peak-to-Peak Voltage Swing with 50 Bias Setting Resistors LIMITING THE AC SWING FILTERING There are situations in which it is desirable to reduce the ac voltage swing for a given DAC output current. This can be achieved through the addition of another resistor to the interface. This resistor is placed in the shunt between each side of the differential pair, as shown in Figure 30. It has the effect of reducing the ac swing without changing the dc bias already established by the 50 resistors. It is necessary to low-pass filter the DAC outputs to remove images when driving a modulator. The interface for setting up the biasing and ac swing that was described in the Limiting the AC Swing section lends itself well to the introduction of such a filter. The filter can be inserted between the dc bias setting resistors and the ac swing limiting resistor, which establishes the input and output impedances for the filter. Rev. A | Page 14 of 20 ADL5373 An example is shown in Figure 32 with a third-order, Bessel low-pass filter with a 3 dB frequency of 10 MHz. Matching input and output impedances makes the filter design easier, so the shunt resistor chosen is 100 , producing an ac swing of 1 V p-p differential. The frequency response of this filter is shown in Figure 33. AUX1_P AD9779 OUT1_P OUT1_N 93 RBIP 50 OUT1_N OUT2_N RBIN 92 50 53.62nF C1Q 350.1pF C2Q AUX1_N 92 RBIN 50 53.62nF C1I 350.1pF C2I 250 LNI 771.1nH 19 IBBP RSLI 100 20 IBBN 89 500 AUX2_N IBBN 500 OUT2_N LNQ 771.1nH RBQP 83 50 RBIP 50 F-MOD LPI 771.1nH 87 20 84 IBBP RSLI 100 350.1pF C2I LNI 771.1nH RBQN 50 OUT2_P 53.62nF C1I 19 250 93 23 RBQN 50 QBBN OUT2_P RSLQ 100 24 LPQ 771.1nH QBBP AUX2_P 250 LNQ 771.1nH 84 RBQP 83 50 86 53.62nF C1Q 350.1pF C2Q 250 LPQ 771.1nH 23 QBBN RSLQ 100 24 QBBP 06664-034 OUT1_P 500 F-MOD LPI 771.1nH 06664-032 AD9779 90 500 Figure 32. DAC Modulator Interface with 10 MHz Third-Order Bessel Filter Figure 34. DAC Modulator Interface with Auxiliary DAC Resistors WiMAX OPERATION 36 24 GROUP DELAY -30 18 -40 12 6 -50 -60 GROUP DELAY (ns) -20 1 10 0 100 FREQUENCY (MHz) 06664-033 MAGNITUDE (dB) 30 Figure 33. Frequency Response for DAC Modulator Interface with 10 MHz Third-Order Bessel Filter -62 -151 -64 -152 -66 The AD9779 features an auxiliary DAC that can be used to inject small currents into the differential outputs for each main DAC channel. This feature can be used to produce the small offset voltages necessary to null out the carrier feedthrough from the modulator. Figure 34 shows the interface required to use the auxiliary DACs, which adds four resistors to the interface. -153 -68 -154 -70 -155 30MHz OFFSET NOISE FLOOR -72 -78 -18 -156 -157 -74 -76 USING THE AD9779 AUXILIARY DAC FOR CARRIER FEEDTHROUGH NULLING ADJACENT CHANNEL POWER RATIO ALTERNATE CHANNEL POWER RATIO -16 -14 -12 -158 -10 -8 OUTPUT POWER (dBm) -6 -4 -159 -2 06664-035 MAGNITUDE -10 30MHz OFFSET NOISE FLOOR (dBm/Hz) Figure 35 shows the first and second adjacent channel power ratios (10 MHz offset and 20 MHz offset), and the 30 MHz offset noise floor vs. output power for a 10 MHz 1024-OFDMA waveform at 2600 MHz. ADJACENT AND ALTERNATE CHANNEL POWER RATIOS (dB) 0 Figure 35. Adjacent and Alternate Channel Power Ratios and 30 MHz Offset Noise Floor vs. Channel Power for a 10 MHz 1024-OFDMA Waveform at 2600 MHz; LO Power = 0 dBm Figure 35 illustrates that optimal performance is achieved when the output power from the modulator is -10 dBm or greater. The noise floor rises with increasing output power, but at less than half the rate at which ACPR degrades. Therefore, operating at powers greater than -10 dBm can improve the signal-tonoise ratio. Rev. A | Page 15 of 20 ADL5373 Figure 36 shows the error-vector magnitude (EVM) vs. output power for a 10 MHz, 1024-OFDMA waveform at 2600 MHz. 2.0 ERROR VECTOR MAGNITUDE (%) 1.8 1.6 1.4 1.2 0.8 0.6 0.4 -17 -15 -13 -11 -9 -7 -5 -3 OUTPUT POWER (dBm) 06664-036 0.2 Figure 36. Error Vector Magnitude (EVM) vs. Output Power for 10 MHz, 1024-OFDMA Waveform at 2600 MHz; LO Power = 0 dBm LO GENERATION USING PLLs Analog Devices has a line of PLLs that can be used for generating the LO signal. Table 4 lists the PLLs together with their maximum frequency and phase noise performance. Frequency fIN (MHz) 550 1200 3000 4000 550 1200 3000 Update Rate (MSPS Minimum) 125 40 125 125 125 160 160 160 1000 1000 1000 All DACs listed have nominal bias levels of 0.5 V and use the same simple DAC modulator interface that is shown in Figure 32. Table 7. Modulator/Demodulator Options The ADF4360 comes as a family of chips, with nine operating frequency ranges. A device is chosen depending on the local oscillator frequency required. Although the use of the integrated synthesizer may come at the expense of slightly degraded noise performance from the ADL5373, it can be a cheaper alternative to a separate PLL and VCO solution. Table 5 shows the options available. Part ADF4360-0 ADF4360-1 ADF4360-2 ADF4360-3 ADF4360-4 ADF4360-5 ADF4360-6 ADF4360-7 ADF4360-8 Resolution (Bits) 8 10 10 12 14 12 14 16 12 14 16 Table 7 lists other Analog Devices modulators and demodulators. Phase Noise @ 1 kHz Offset and 200 kHz PFD (dBc/Hz) -91 @ 540 MHz -87 @ 900 MHz -90 @ 900 MHz -91 @ 900 MHz -89 @ 540 MHz -87 @ 900 MHz -90 @ 900 MHz Table 5. ADF4360 Family Operating Frequencies Part AD9709 AD9761 AD9763 AD9765 AD9767 AD9773 AD9775 AD9777 AD9776 AD9778 AD9779 MODULATOR/DEMODULATOR OPTIONS Table 4. Analog Devices PLL Selection Table Part ADF4110 ADF4111 ADF4112 ADF4113 ADF4116 ADF4117 ADF4118 The AD9779 recommended in the previous sections of this data sheet is not the only DAC that can be used to drive the ADL5373. There are other appropriate DACs, depending on the level of performance required. Table 6 lists the dual TxDACs offered by Analog Devices. Table 6. Dual TxDAC Selection Table 1.0 0 -19 TRANSMIT DAC OPTIONS Part No. AD8345 AD8346 AD8349 ADL5390 Modulator/ Demodulator Modulator Modulator Modulator Modulator Frequency Range (MHz) 140 to 1000 800 to 2500 700 to 2700 20 to 2400 ADL5385 ADL5370 ADL5371 ADL5372 ADL5374 AD8347 AD8348 AD8340 AD8341 Modulator Modulator Modulator Modulator Modulator Demodulator Demodulator Vector modulator Vector modulator 50 to 2200 300 to 1000 500 to 1500 1500 to 2500 3000 to 4000 800 to 2700 50 to 1000 700 to 1000 1500 to 2400 Output Frequency Range (MHz) 2400 to 2725 2050 to 2450 1850 to 2150 1600 to 1950 1450 to 1750 1200 to 1400 1050 to 1250 350 to 1800 65 to 400 Rev. A | Page 16 of 20 Comments External quadrature ADL5373 EVALUATION BOARD IBBN IBBP RFPQ RFNQ CFNQ CFNI 0 0 OPEN OPEN RTQ CFPQ OPEN OPEN 2 VPS1 3 VPS1 VPS1 VPS1 RFPI 0 CFPI OPEN C16 0.1F L12 0 19 IBBP 20 IBBN 21 COM4 QBBN 23 QBBP 1 COM1 22 COM4 RTI OPEN 24 VPOS COM1 RFNI 0 18 Z1 F-MOD 17 16 C15 0.1F L11 0 VPS5 VPS4 C14 0.1F VPS3 VPS2 15 VPS2 14 4 5 EXPOSED PADDLE 6 C12 0.1F 13 VOUT C11 OPEN VOUT 12 C13 0.1F Figure 38. Evaluation Board Layout, Top Layer COM3 11 10 COM3 COM2 8 9 LOIN LOIP COM2 7 COUT 100pF 06664-038 QBBN VPOS QBBP Yuping Toh A populated RoHS-compliant evaluation board is available for evaluation of the ADL5373. The ADL5373 package has an exposed paddle on the underside. This exposed paddle must be soldered to the board (see the Power Supply and Grounding section). The evaluation board has no components on the underside so heat can be applied to the underside for easy removal and replacement of the ADL5373. GND CLOP 100pF RLOP OPEN CLON 100pF 4 3 5 2 NC 6 1 RLON OPEN LO 06664-037 T1 JOHANSON TECHNOLOGY 2450BL15B050 Figure 37. ADL5373 Evaluation Board Schematic Table 8. Evaluation Board Configuration Options Component VPOS, GND RFPI, RFNI, RFPQ, RFNQ, CFPI, CFNI, CFPQ, CFNQ, RTQ, RTI Description Power Supply and Ground Clip Leads. Baseband Input Filters. These components can be used to implement a low-pass filter for the baseband signals. See the Filtering section. Rev. A | Page 17 of 20 Default Condition Not applicable RFNQ, RFPQ, RFNI, RFPI = 0 (0402) CFNQ, CFPQ, CFNI, CFPI = open (0402) RTQ, RTI = open (0402) ADL5373 CHARACTERIZATION SETUP AEROFLEX IFR 3416 250kHz TO 6GHz SIGNAL GENERATOR R AND S SPECTRUM ANALYZER FSU 20Hz TO 8GHz RF OUT FREQ 4MHz LEVEL 0dBm BIAS 0.5V GAIN 0.7V BIAS 0.5V GAIN 0.7V LO CONNECT TO BACK OF UNIT I OUT I/AM Q OUT Q/FM 90 I +6dBm RF IN 0 Q AGILENT 34401A MULTIMETER F-MOD TEST SETUP 0.175 ADC IP VPOS +5V IN QP AGILENT E3631A POWER SUPPLY - OUT OUTPUT QN VPOS GND 0.175A 6V LO 25V + COM - 06664-039 5.000 + F-MOD Figure 39. Characterization Bench Setup The primary setup used to characterize the ADL5373 is shown in Figure 39. This setup was used to evaluate the product as a single-sideband modulator. The Aeroflex signal generator supplied the LO and differential I and Q baseband signals to the device under test, DUT. The typical LO drive was 0 dBm. The I-channel is driven by a sine wave, and the Q-channel is driven by a cosine wave. The lower sideband is the single-sideband (SSB) output. The majority of characterization for the ADL5373 was performed using a 1 MHz sine wave signal with a 500 mV common-mode voltage applied to the baseband signals of the DUT. The baseband signal path was calibrated to ensure that the VIOS and VQOS offsets on the baseband inputs were minimized, as close as possible, to 0 V before connecting to the DUT. Rev. A | Page 18 of 20 ADL5373 CH1 1MHz AMPL 700mV p-p PHASE 0 CH2 1MHz AMPL 700mV p-p PHASE 90 0 R AND S SMT 06 SIGNAL GENERATOR CH2 OUTPUT CH1 OUTPUT TEKTRONIX AFG3252 DUAL FUNCTION ARBITRARY FUNCTION GENERATOR I Q RF OUT FREQ 4MHz TO 4GHz LEVEL 0dBm LO 90 SINGLE-TO-DIFFERENTIAL CIRCUIT BOARD AGILENT E3631A POWER SUPPLY F-MOD TEST RACK 5.000 0.350A Q IN AC 25V 6V VPOS ++5V- +5V VPOS +5V F-MOD CHAR BD Q IN DCCM + COM - IP IP VPOSB VPOSA IN IN TSEN -5V GND AGND IN1 IN1 VN1 VP1 I IN DCCM I IN AC QP OUTPUT OUT QN GND VPOS QP QN AGILENT E3631A POWER SUPPLY 0.500 LO R AND S FSEA 30 SPECTRUM ANALYZER 0.010A + 6V RF IN 25V - + COM - 100MHz TO 4GHz +6dBm VCM = 0.5V AGILENT 34401A MULTIMETER 06664-040 0.200 ADC Figure 40. Setup for Baseband Frequency Sweep and Undesired Sideband Nulling The setup used to evaluate baseband frequency sweep and undesired sideband nulling of the ADL5373 is shown in Figure 40. The interface board has circuitry that converts the single-ended I input and Q input from the arbitrary function generator to differential I and Q baseband signals with a dc bias of 500 mV. Undesired sideband nulling was achieved through an iterative process of adjusting amplitude and phase on the Q-channel. See the Sideband Suppression Optimization section for detailed information on sideband nulling. Rev. A | Page 19 of 20 ADL5373 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ PIN 1 INDICATOR 0.60 MAX TOP VIEW 0.50 BSC 3.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 12 MAX SEATING PLANE 0.80 MAX 0.65 TYP 0.30 0.23 0.18 PIN 1 INDICATOR 19 18 24 1 *2.45 EXPOSED PAD 2.30 SQ 2.15 (BOTTOMVIEW) 13 12 7 6 0.23 MIN 2.50 REF 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08 *COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 41. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-24-2) Dimensions shown in millimeters ORDERING GUIDE Model ADL5373ACPZ-R7 1 ADL5373ACPZ-WP1 ADL5373-EVALZ1 1 Temperature Range -40C to +85C -40C to +85C Package Description 24-Lead LFCSP_VQ, 7" Tape and Reel 24-Lead LFCSP_VQ, Waffle Pack Evaluation Board Package Option CP-24-2 CP-24-2 Ordering Quantity 1,500 64 Z = RoHS Compliant Part. (c)2007-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06664-0-2/08(A) T T Rev. A | Page 20 of 20