RT9173D
1
www.richtek.com
DS9173D-07 April 2011
Pin Configurations
Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator
Ordering Information
General Description
The RT9173D is a simple, cost-effective and high-speed
linear regulator designed to generate termination voltage
in double data rate (DDR) memory system to comply with
the JEDEC SSTL_2 and SSTL_18 or other specific
interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices
requirements. The regulator is capable of actively sinking
or sourcing continuous 2A or up to 3A transient peak
current while regulating an output voltage to within 40mV.
The output termination voltage cab be tightly regulated to
track 1/2VDDQ by two external voltage divider resistors or
the desired output voltage can be pro-grammed by externally
forcing the REFEN pin voltage.
The RT9173D also incorporates a high-speed differential
amplifier to provide ultra-fast response in line/load transient.
Other features include extremely low initial offset voltage,
excellent load regulation, current limiting in bi-directions
and on-chip thermal shut-down protection.
The RT9173D are available in the SOP-8 (Exposed Pad)
surface mount packages.
Features
zz
zz
zIdeal for DDR-I, DDR-II and DDR-III VTT Applications
zz
zz
zSink and Source Current
``
``
` 2A Continuous Current
``
``
` Peak 3A for DDRI and DDRII
``
``
` Peak 2.5A for DDRIII
zz
zz
zIntegrated Power MOSFETs
zz
zz
zGenerates Termination Voltage for SSTL_2,
SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces
zz
zz
zHigh Accuracy Output Voltage at Full-Load
zz
zz
zOutput Adjustment by Two External Resistors
zz
zz
zLow External Component Count
zz
zz
zShutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
zz
zz
zCurrent Limiting Protection
zz
zz
zOn-Chip Thermal Protection
zz
zz
zAvailable in SOP-8 (Exposed Pad) Packages
zz
zz
zVIN and VCNTL No Power Sequence Issue
zz
zz
zRoHS Compliant and 100% Lead (Pb)-Free
Applications
zDesktop PCs, Notebooks, and Workstations
zGraphics Card Memory Termination
zSet Top Boxes, Digital TVs, Printers
zEmbedded Systems
zActive Termination Buses
zDDR-I, DDR-II and DDR-III Memory Systems
(TOP VIEW)
SOP-8 (Exposed Pad)
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
VIN
GND
REFEN
VOUT
NC
NC
NC
VCNTL
GND
2
3
45
6
7
8
9
Package Type
SP : SOP-8 (Exposed Pad-Option 1)
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
RT9173D
RT9173D
2
DS9173D-07 April 2011www.richtek.com
Typical Application Circuit
R1 = R2 = 100kΩ, RTT = 50Ω / 33Ω / 25Ω
COUT(MIN) = 10μF (Ceramic) + 1000μF under the worst case testing condition
CSS = 1μF, CIN = 470μF (Low ESR), CCNTL = 47μF
Test Circuit
Figure 1. Test Circuit for Typical Operating Characteristics Curves
VIN
REFEN
GND
VCNTL
VOUT
RT9173D
EN
2N7002
R1
R2
CSS
VIN = 2.5V/1.8V/1.5V
VCNTL = 3.3V
CCNTL
CIN
RTT
COUT
GND
VIN
REFEN
GND
VCNTL
VOUT
RT9173D
2.5V/1.8V/1.5V 3.3V
1.25V/0.9V/0.75V VOUT
RT9173D
3
www.richtek.com
DS9173D-07 April 2011
Functional Pin Description
VIN (Pin 1)
Input voltage which supplies current to the output pin.
Connect this pin to a well-decoupled supply voltage. To
prevent the input rail from dropping during large load
transient, a large, low ESR capacitor is recommended to
use. The capacitor should be placed as close as possible
to the VIN pin.
GND [Pin 2, Exposed pad (9)]
Common Ground (Exposed pad is connected to GND).
The GND pad area should be as large as possible and
using many vias to conduct the heat into the buried GND
plate of PCB layer.
REFEN (Pin 3)
Reference voltage input and active low shutdown control
pin. Two resistors dividing down the VIN voltage on the pin
to create the regulated output voltage. Pulling the pin to
ground turns off the device by an open-drain, such as
2N7002, signal N-MOSFET.
Function Block Diagram
GND
VCNTL
REFEN
Current Limit
Thermal Protection
VOUT
EA
+
-
VIN
VOUT (Pin 4)
Regulator output. VOUT is regulated to REFEN voltage
that is used to terminate the bus resistors. It is capable of
sinking and sourcing current while regulating the output
rail. To maintain adequate large signal transient response,
typical value of 1000μF AL electrolytic capacitor with 10μF
ceramic capacitors are recommended to reduce the effects
of current transients on VOUT.
VCNTL (Pin 6)
VCNTL supplies the internal control circuitry and provides
the drive voltage. The driving capability of output current is
proportioned to the VCNTL. Connect this pin to 3.3V bias
supply to handle large output current with at least 10μF
capacitor from this pin to GND.
NC (Pin 5, 7, 8)
No Internal Connect.
RT9173D
4
DS9173D-07 April 2011www.richtek.com
Electrical Characteristics
(VIN = 2.5V/1.8V/1.5V, VCNTL = 3.3V, VREFEN = 1.25V/0.9V/0.75V, COUT = 10μF (Ceramic), TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Input
VCNTL Operation Current ICNTL I
OUT = 0A -- 1 2.5 mA
Standby Current (Note 5) ISTBY VREFEN < 0.2V (Shutdown),
RLOAD = 180Ω -- 50 90 μA
Output (DDR / DDR II / DDR III)
Output Offset Voltage (Note 6) VOS I
OUT = 0A −20 -- +20 mV
IOUT = +2A
Load Regulation (Note 7) ΔVLOAD IOUT = −2A −20 -- +20 mV
Protection
Current limit ILIM V
IN = 2.5V/1.8V/1.5V -- 3.4 -- A
Thermal Shutdown Temperature TSD 3.3V ≤ VCNTL ≤ 5V 125 170 -- °C
Thermal Shutdown Hysteresis ΔTSD 3.3V ≤ VCNTL ≤ 5V -- 35 -- °C
REFEN Shutdown
VIH Enable 0.6 -- --
Shutdown Threshold VIL Shutdown -- -- 0.2
V
Absolute Maximum Ratings (Note 1)
zInput Voltage, VIN ---------------------------------------------------------------------------------------------------- 6V
zControl Voltage, VCNTL ---------------------------------------------------------------------------------------------- 6V
z Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------------------- 1.33W
zPackage Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------- 75°C/W
SOP-8 (Exposed Pad), θJC ---------------------------------------------------------------------------------------- 28°C/W
zJunction Temperature ----------------------------------------------------------------------------------------------- 125°C
zLead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260°C
zStorage Temperature Range --------------------------------------------------------------------------------------- –65°C to 150°C
zESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------ 200V
Recommended Operating Conditions (Note 4)
zInput Voltage, VIN ---------------------------------------------------------------------------------------------------- 2.5V to 1.5V ± 5%
zControl Voltage, VCNTL ---------------------------------------------------------------------------------------------- 5V or 3.3V ± 5%
zAmbient Temperature Range -------------------------------------------------------------------------------------- −40°C to 85°C
zJunction Temperature Range -------------------------------------------------------------------------------------- −40°C to 125°C
RT9173D
5
www.richtek.com
DS9173D-07 April 2011
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers,
2S2P) of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for SOP-8 (Exposed
Pad) package.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on
REFEN pin (VIL < 0.2V). It is measured with VIN = VCNTL = 5V.
Note 6. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.
Note 7. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load
regulation in the load range from 0A to 2A.
RT9173D
6
DS9173D-07 April 2011www.richtek.com
Typical Operating Characteristics
Vcntl Current vs. Temperature
0.3
0.35
0.4
0.45
0.5
0.55
0.6
-50-25 0 25 50 75100125
Temperature
Vcntl Current (mA)
(°C)
VIN = 2.5V, VCNTL = 5V
VIN = 2.5V, VCNTL = 3.3V
VIN = 1.8V, VCNTL = 3.3V
VIN = 1.8V, VCNTL = 5V
VIN = 1.5V, VCNTL = 5V
VIN = 1.5V, VCNTL = 3.3V
VIN Current vs. Temperature
2
2.5
3
3.5
4
4.5
5
-50 -25 0 25 50 75 100 125
Temperature
VIN
Current (mA)
(°C)
VIN = 2.5V, VCNTL = 5V
VIN = 2.5V, VCNTL = 3.3V
VIN = 1.8V, VCNTL = 3.3V
VIN = 1.8V, VCNTL = 5V
VIN = 1.5V, VCNTL = 5V
VIN = 1.5V, VCNTL = 3.3V
Shutdown Threshold vs. Temperature
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
-50-25 0 255075100125
Temperature
Shutdown Threshold (V)
(°C)
VCNTL = 3.3V, Turn On
VCNTL = 5V, Turn Off
VCNTL = 5V, Turn On
VCNTL = 3.3V, Turn Off
Output Voltage vs. Temperature
1.24
1.245
1.25
1.255
1.26
1.265
1.27
-50-25 0 25 50 75100125
Temperature
Output Voltage (V)
(°C)
VIN = 2.5V
Output Voltage vs. Temperature
0.89
0.895
0.9
0.905
0.91
0.915
0.92
-50 -25 0 25 50 75 100 125
Temperature
Output Voltage (V)
(°C)
VIN = 1.8V
Output Voltage vs. Temperature
0.74
0.745
0.75
0.755
0.76
0.765
0.77
-50 -25 0 25 50 75 100 125
Temperature
Output Voltage (V)
(°C)
VIN = 1.5V
RT9173D
7
www.richtek.com
DS9173D-07 April 2011
Source Current Limit vs. Temperature
2
2.5
3
3.5
4
4.5
-50 -25 0 25 50 75 100 125
Temperature
Source Current Limit (A)
(°C)
VIN = 2.5V, VCNTL = 5V
VIN = 2.5V,
VCNTL = 3.3V
VIN = 1.8V, VCNTL = 3.3V
VIN = 1.8V, VCNTL = 5V
VIN = 1.5V, VCNTL = 5V
VIN = 1.5V, VCNTL = 3.3V
Sink Current Limit vs. Temperature
2
2.5
3
3.5
4
4.5
-50-25 0 25 50 75100125
Temperature
Sink Current Limit (A)
(°C)
VIN = 2.5V, VCNTL = 5V
VIN = 2.5V, VCNTL = 3.3V
VIN = 1.8V, VCNTL = 3.3V
VIN = 1.8V, VCNTL = 5V
VIN = 1.5V, VCNTL = 5V
VIN = 1.5V, VCNTL = 3.3V
0.9VTT @ 2A Transient Response
Output Voltage
Transient (mV)
40
20
0
-20
Output Current
(A)
2
1
0
VIN = 1.8V, VCNTL = 3.3V, VOUT = 0.9V
Swing Frequency : 1kHz
Time (250μs/Div)
Sink
0.9VTT @ 2A Transient Response
Output Voltage
Transient (mV)
40
20
0
-20
Output Current
(A)
2
1
0
VIN = 1.8V, VCNTL = 3.3V, VOUT = 0.9V
Swing Frequency : 1kHz
Time (250μs/Div)
Source
0.75VTT @ 2A Transient Response
Output Voltage
Transient (mV)
40
20
0
-20
Output Current
(A)
2
1
0
VIN = 1.5V, VCNTL = 3.3V, VOUT = 0.75V
Swing Frequency : 1kHz
Time (250μs/Div)
Sink
0.75VTT @ 2A Transient Response
Output Voltage
Transient (mV)
40
20
0
-20
Output Current
(A)
2
1
0
VIN = 1.5V, VCNTL = 3.3V, VOUT = 0.75V
Swing Frequency : 1kHz
Time (250μs/Div)
Source
RT9173D
8
DS9173D-07 April 2011www.richtek.com
VIN = 1.5V, VCNTL = 3.3V
Output Short-Circuit Protection
Output Short Circuit (A)
12
10
8
6
4
2
0
Time (1ms/Div)
Source
VIN = 1.5V, VCNTL = 3.3V
Output Short-Circuit Protection
Output Short Circuit (A)
12
10
8
6
4
2
0
Sink
Time (1ms/Div)
VIN = 1.8V, VCNTL = 3.3V
Output Short-Circuit Protection
Output Short Circuit (A)
12
10
8
6
4
2
0
Sink
Time (1ms/Div)
VIN = 1.8V, VCNTL = 3.3V
Output Short-Circuit Protection
Output Short Circuit (A)
12
10
8
6
4
2
0
Time (1ms/Div)
Source
1.25VTT @ 2A Transient Response
Output Voltage
Transient (mV)
40
20
0
-20
Output Current
(A)
2
1
0
VIN = 2.5V, VCNTL = 3.3V, VOUT = 1.25V
Swing Frequency : 1kHz
Time (250μs/Div)
Sink
1.25VTT @ 2A Transient Response
Output Voltage
Transient (mV)
40
20
0
-20
Output Current
(A)
2
1
0
VIN = 2.5V, VCNTL = 3.3V, VOUT = 1.25V
Swing Frequency : 1kHz
Time (250μs/Div)
Source
RT9173D
9
www.richtek.com
DS9173D-07 April 2011
VIN = 2.5V, VCNTL = 3.3V
Output Short-Circuit Protection
Output Short Circuit (A)
12
10
8
6
4
2
0
Time (1ms/Div)
Source
VIN = 2.5V, VCNTL = 3.3V
Output Short-Circuit Protection
Output Short Circuit (A)
12
10
8
6
4
2
0
Sink
Time (1ms/Div)
RT9173D
10
DS9173D-07 April 2011www.richtek.com
General Regulator
The RT9173D could also serves as a general linear
regulator. The RT9173D accepts an external reference
voltage at REFEN pin and provides output voltage regulated
to this reference voltage as shown in Figure 3, where
VOUT = VEXT x R2/(R1+R2)
As other linear regulator, dropout voltage and thermal issue
should be specially considered. Figure 4 and 5 show the
RDS(ON) over temperature of RT9173D in PSOP-8 (Exposed
Pad) package. The minimum dropout voltage could be
obtained by the product of RDS(ON) and output current. For
thermal consideration, please refer to the relative sections.
Application Information
Consideration while designs the resistance of voltage
divider
Make sure the sinking current capability of pull-down NMOS
if the lower resistance was chosen so that the voltage on
VREFEN is below 0.2V.
In addition, the capacitor and voltage divider form the low-
pass filter. There are two reasons doing this design; one is
for output voltage soft-start while another is for noise
immunity.
How to reduce power dissipation on Notebook PC or
the dual channel DDR SDRAM application?
In notebook application, using RichTek's Patent
“Distributed Bus Terminator Topology” with choosing
RichTek's product is encouraged.
Distributed Bus Terminating Topology
Figure 2
Figure 4
Figure 5
R0
R9
R8
R7
R6
R5
R4
R3
R2
R1
R(2N)
R(2N+1)
RT9173D
RT9173D VOUT
VOUT
REFEN
BUS(0)
BUS(1)
BUS(2)
BUS(3)
BUS(4)
BUS(5)
BUS(6)
BUS(7)
BUS(8)
BUS(9)
BUS(2N)
BUS(2N+1)
Terminator Resistor
RDS(ON) vs. Temperature
0.10
0.15
0.20
0.25
0.30
0.35
0.40
-50 -25 0 25 50 75 100 125
Temperature
RDS(ON) (Ω)
(°C)
VCNTL = 5V
RDS(ON) vs. Temperature
0.10
0.15
0.20
0.25
0.30
0.35
0.40
-50-25 0 25 50 75100125
Temperature
RDS(ON) (Ω)
(°C)
VCNTL = 3.3V
Figure 3
VCNTL
REFEN
GND
VIN
VOUT
RT9173D
VEXT
R1
R2
VOUT
RT9173D
11
www.richtek.com
DS9173D-07 April 2011
Input Capacitor and Layout Consideration
Place the input bypass capacitor as close as possible to
the RT9173D. A low ESR capacitor larger than 470uF is
recommended for the input capacitor. Use short and wide
traces to minimize parasitic resistance and inductance.
Inappropriate layout may result in large parasitic inductance
and cause undesired oscillation between RT9173D and the
preceding power converter.
Thermal Consideration
RT9173D regulators have internal thermal limiting circuitry
designed to protect the device during overload conditions.
For continued operation, do not exceed maximum operation
junction temperature 125°C. The power dissipation
definition in device is:
PD = (VIN - VOUT) x IOUT + VIN x IQ
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula:
PD(MAX) = ( TJ(MAX) -TA ) /θJA
Where TJ(MAX) is the maximum operation junction
temperature 125°C, TA is the ambient temperature and the
θJA is the junction to ambient thermal resistance. The
junction to ambient thermal resistance (θJA is layout
dependent) for SOP-8 package (Exposed Pad) is 75°C/W
on standard JEDEC 51-7 (4 layers, 2S2P) thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by following formula:
PD(MAX) = (125°C - 25°C) / 75°C/W = 1.33W
Figure 6 show the package sectional drawing of SOP-8
(Exposed Pad). Every package has several thermal
dissipation paths. As show in Figure 7, the thermal
resistance equivalent circuit of SOP-8 (Exposed Pad). The
path 2 is the main path due to these materials thermal
conductivity. We define the exposed pad is the case point
of the path 2.
Ambient
Molding Compound
Gold Line Lead Frame
Die Pad
Case (Exposed Pad)
Figure 6. SOP-8 (Exposed Pad) Package Sectional
Drawing
Figure 7. Thermal Resistance Equivalent Circuit
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package design and the PCB design.
However, the package design has been decided. If possible,
it's useful to increase thermal performance by the PCB
design. The thermal resistance can be decreased by
adding copper under the expose pad of SOP-8 package.
About PCB layout, the Figure 8 show the relation between
thermal resistance θJA and copper area on a standard
JEDEC 51-7 (4 layers, 2S2P) thermal test board at
TA = 25°C.We have to consider the copper couldn't stretch
infinitely and avoid the tin overflow. We use the “dog-bone”
copper patterns on the top layer as Figure 9.
As shown in Figure 10, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard SOP-8
(Exposed Pad) pad of 2 oz. copper (Figure 10.a), θJA is
75°C/W. Adding copper area of pad under the SOP-8
(Exposed Pad) (Figure 10.b) reduces the θJA to 64°C/W.
Even further, increasing the copper area of pad to 70mm2
(Figure 10.e) reduces the θJA to 49°C/W.
Junction
RDIE RDIE-ATTACH RDIE-PAD
RGOLD-LINE RLEAD FRAME
Case
(Exposed Pad)
RPCB
RPCB
Ambient
RMOLDING-COMPOUND
path 1
path 2
path 3
RT9173D
12
DS9173D-07 April 2011www.richtek.com
θJA vs. Copper Area
30
40
50
60
70
80
90
100
0 10203040506070
Copper Area (mm2)
θJA (°C/W)
Figure 8
Figure 9.Dog-Bone layout
Figure 10. Thermal Resistance vs. Different Cooper Area
Layout Design
Figure 10 (a). Minimum Footprint, θJA = 75°C/W
Figure 10 (b). Copper Area = 10mm2, θJA = 64°C/W
Figure 10 (c). Copper Area = 30mm2, θJA = 54°C/W
Figure 10 (d). Copper Area = 50mm2, θJA = 51°C/W
Figure 10 (e). Copper Area = 70mm2, θJA = 49°C/W
Exposed Pad
W≦2.28mm
RT9173D
13
DS9173D-07 April 2011 www.richtek.com
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,
specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
Outline Information
A
B
J
F
H
M
C
D
I
Y
X
EXPOSED THERMAL PAD
(Bottom of Package)
8-Lead SOP (Exposed Pad) Plastic Package
Dimensions In Millimeters Dimensions In Inches
Symbol Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 4.000 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.510 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.000 0.152 0.000 0.006
J 5.791 6.200 0.228 0.244
M 0.406 1.270 0.016 0.050
X 2.000 2.300 0.079 0.091
Option 1 Y 2.000 2.300 0.079 0.091
X 2.100 2.500 0.083 0.098
Option 2 Y 3.000 3.500 0.118 0.138
