©2001 Integrated Device Technology, Inc.
NOVEMBER 2001
DSC 2674/11
1
IDT7052S/L
Functional Block Diagram
HIGH-SPEED
2K x 8 FourPortTM
STATIC RAM
Features
◆◆
◆◆
◆High-speed access
– Commercial: 20/25/35ns (max.)
– Industrial: 25ns (max.)
– Military: 25/35ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT7052S
Active: 750mW (typ.)
Standby: 7.5mW (typ.)
– IDT7052L
Active: 750mW (typ.)
Standby: 1.5mW (typ.)
◆◆
◆◆
◆True FourPort memory cells which allow simultaneous
access of the same memory locations
◆◆
◆◆
◆Fully asynchronous operation from each of the four ports:
P1, P2, P3, P4
◆◆
◆◆
◆Versatile control for write-inhibit: separate BUSY input to
control write-inhibit for each of the four ports
MEMORY
ARRAY
COLUMN
I/O
PORT 1
ADDRESS
DECODE
LOGIC
PORT 2
ADDRESS
DECODE
LOGIC
COLUMN
I/O
COLUMN
I/O
PORT 4
ADDRESS
DECODE
LOGIC
PORT 3
ADDRESS
DECODE
LOGIC
COLUMN
I/O
R/W
P1
I/O
0P1
-I/O
7P1
CE
P1
OE
P1
A
0P1
-A
10P1
BUSY
P2
R/W
P2
CE
P2
OE
P2
2674 drw 01
I/O
0P2
-I/O
7P2
A
0P2
-A
10P2
BUSY
P1
R/W
P4
I/O
0P4
-I/O
7P4
CE
P4
OE
P4
A
0P4
-A
10P4
BUSY
P3
R/W
P3
CE
P3
OE
P3
I/O
0P3
-I/O
7P3
A
0P3
-A
10P3
BUSY
P4
◆◆
◆◆
◆Battery backup operation—2V data retention
◆◆
◆◆
◆TTL-compatible; single 5V (±10%) power supply
◆◆
◆◆
◆Available in 120 pin and 132 pin Thin Quad Flatpacks and
108 pin PGA
◆◆
◆◆
◆Military product compliant to MIL-PRF-38535 QML
◆◆
◆◆
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Description
The IDT7052 is a high-speed 2K x 8 FourPort™ Static RAM designed
to be used in systems where multiple access into a common RAM is
required. This FourPort Static RAM offers increased system performance
in multiprocessor systems that have a need to communicate in real time and
also offers added benefit for high-speed systems in which multiple access
is required in the same cycle.
The IDT7052 is also designed to be used in systems where on-chip
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
2
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately 1.21 in x 1.21 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Configurations(1,2,3)
2674 drw 02
OE
P2
A
7
P2
A
8
P2
A
5
P2
80
I/O
2
P1
I/O
3
P1
I/O
6
P1 V
CC
GND I/O
2
P4
I/O
5
P4
A
3
P2
A
4
P2
A
5
P3
A
7
P3
A
8
P3
OE
P3
A
0
P2
A
1
P3
A
1
P2
A
0
P3
77 74 72 69 68 65 63 60
A
3
P3
A
4
P3
83 78 76 73 70 67 64 61 5984 56
8687
8890
9192
9495
9796
10099
103101
105104
2
1
5
4
7
8
10
12
13
17
16
21
19
25
22
28
24
32
31 34
35 37
39 40
44 43
48 46
52 49
55 51
IDT7052G
G108-1
(4)
108-Pin PGA
Top View
(5)
ABCDEFGHJKLM
81 57 54
53
82 79 75 71 66 62 58 50
R/W
P2
NC NC R/W
P3
BUSY
P2
BUSY
P3
A
6
P2
CE
P3
A
2
P3
A
2
P2
A
6
P3
A
2
P4
A
1
P4
A
9
P3
A
9
P2
CE
A
1
P1
A
2
P1
33
36
38
41
42
45
47
3 6 9 111415182023
29 30
26 27
85
89
93
98
102
106
107
108
NC
P1
GND
A
5
P1
A
3
P1
A
0
P1
A
6
P1
A
4
P1
V
CC
CE
P1
OE
P1
I/O
0
P1
A
8
P1
A
9
P1
A
7
P1
R/W
P1
BUSY I/O
1
P1
V
CC
V
CC
V
CC
GND I/O
6
P4
I/O
4
P1
I/O
7
P1
I/O
0
P2
I/O
2
P2
I/O
4
P2
I/O
6
P2
I/O
1
P3
I/O
3
P3
I/O
5
P3
I/O
7
P3
I/O
3
P4
I/O
4
P4
I/O
5
P1
NC I/O
1
P2
I/O
3
P2
I/O
5
P2
I/O
7
P2
I/O
0
P3
I/O
2
P3
I/O
4
P3
I/O
6
P3
I/O
0
P4
I/O
1
P4
A
0
P4
A
3
P4
A
5
P4
A
4
P4
A
6
P4
GND
P4
A
7
P4
A
8
P4 NC P4
A
9
P4
OE
P4
R/W
GND
P4
I/O
7
P4
BUSY
GND
CE
12
11
10
09
08
07
06
05
04
03
02
01
A
10
P1
A
10
P2
A
10
P3
A
10
P4
INDEX
11/07/01
hardware port arbitration is not needed. This part lends itself to those
systems which cannot tolerate wait states or are designed to be able to
externally arbitrate or withstand contention when all ports simultaneously
access the same FourPort RAM location.
The IDT7052 provides four independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. It is the user’s responsibility to
ensure data integrity when simultaneously accessing the same memory
location from all ports. An automatic power down feature, controlled by CE,
permits the on-chip circuitry of each port to enter a very low power standby
power mode.
Fabricated using IDT’s CMOS high-performance technology, this
FourPort SRAM typically operates on only 750mW of power. Low-power
(L) versions offer battery backup data retention capability, with each port
typically consuming 50µW from a 2V battery.
The IDT7052 is packaged in a ceramic 108-pin Pin Grid Array (PGA),
120-pin Thin Quad Flatpack (TQFP) and 132-pin Plastic Quad Flatpack
(PQF). Military grade product is manufactured in compliance with the latest
revision of MIL-PRF-38535 QML, making it ideally suited to military
temperature applications demanding the highest level of performance and
reliability.
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
N/C
N/C
OE
P2
BUSY
P2
A
0P1
A
1P1
A
2P1
A
3P1
A
4P1
A
5P1
A
6P1
A
10P1
V
CC
A
7P1
A
8P1
A
9P1
N/C
CE
P1
R/W
P1
OE
P1
BUSY
P1
I/O
0P1
I/O
1P1
I/O
2P1
I/O
3P1
GND
I/O
4P1
I/O
5P1
N/C
N/C
N/C
I/O
6P1
I/O
7P1
N/C
V
CC
I/O
0P2
I/O
1P2
I/O
2P2
GND
I/O
3P2
I/O
4P2
I/O
5P2
V
CC
I/O
6P2
I/O
7P2
N/C
I/O
0P3
I/O
1P3
V
CC
I/O
2P3
I/O
3P3
I/O
4P3
GND
I/O
5P3
I/O
6P3
I/O
7P3
V
CC
I/O
0P4
I/P
1P4
N/C
N/C
N/C
BUSY
P3
A
0P4
A
1P4
A
2P4
A
3P4
A
4P4
A
5P4
A
6P4
A
10P4
GND
A
7P4
A
8PR
A
9P4
N/C
CE
P4
R/W
P4
OE
P4
BUSY
P4
GND
I/O
7P4
I/O
6P4
I/O
5P4
GND
I/O
4P4
I/O
3P4
I/O
2PR
N/C
N/C
CE
P2
R/W
P2
N/C
A
9P2
A
8P2
A
7P2
A
10P2
A
6P2
A
5P2
A
4P2
A
3P2
A
2P2
A
1P2
A
0P2
N/C
A
0P3
A
1P3
A
2P3
A
3P3
A
4P3
A
5P3
A
6P3
A
10P3
A
7P3
A
8P3
A
9P3
N/C
OE
P3
CE
P3
R/W
P3
2674 drw 04
IDT7052PF
PN120-1
(4)
120-Pin Thin Quad Flatpack
Top View
(5)
11/07/01
Pin Configurations(1,2,3) (con't.)
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. PQ132-1 package body is approximately
.95 in x .95 in x .14 in.
PN120-1 package body is approximately
14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking
6. The side of the package containing pin1 may have a bevelled edge in place of the indicator dot..
IDT7052PQF
PQ132-1
(4)
132-Pin Plastic Quad Flatpack
Top View
(5,6)
1
17 117
116
18
50
51 83
84
N/C
OE
P2
BUSY
P2
N/C
A
0P1
A
1P1
A
2P1
A
3P1
A
4P1
A
5P1
A
6P1
A
7P1
A
8P1
A
9P1
N/C
V
CC
N/C
CE
P1
R/W
P1
OE
P1
BUSY
P1
N/C
I/O
0P1
I/O
1P1
I/O
2P1
I/O
3P1
I/O
4P1
I/O
5P1
N/C
GND
N/C
N/C
I/O
2P4
I/O
3P4
I/O
4P4
I/O
5P4
I/O
6P4
I/O
7P4
N/C
N/C
GND
N/C
GND
N/C
CE
P4
R/W
P4
OE
P4
BUSY
P4
N/C
A
0P4
A
1P4
A
2P4
A
3P4
A
4P4
A
5P4
A
6P4
A
7P4
A
8P4
A
9P4
GND
N/C
N/C
BUSY
P3
N/C
2674 drw 03
A
10P4
A
10P1
N/C
A
9P2
A
8P2
A
7P2
A
6P2
A
5P2
A
4P2
A
3P2
A
2P2
A
1P2
A
0P2
N/C
N/C
N/C
CE
P2
CE
P3
OE
P3
N/C
N/C
A
0P3
A
1P3
A
2P3
A
4P3
A
5P3
A
6P3
A
7P3
A
8P3
A
9P3
A
3P3
A
10P3
A
10P2
I/O
5P3
I/O
6P1
I/O
7P1
N/C
V
CC
N/C
I/O
0P2
I/O
1P2
I/O
2P2
I/O
3P2
I/O
4P2
I/O
5P2
GND
V
CC
I/O
0P3
I/O
1P3
I/O
2P3
I/O
3P3
I/O
4P3
I/O
6P3
I/O
7P3
I/O
0P4
I/O
1P4
N/C
V
CC
GND
N/C
N/C
V
CC
N/C
N/C
I/O
7P2
R/W
P2
R/W
P3
I/O
6P2
11/07/01
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
4
Pin Configurations(1,2)
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply
Absolute Maximum Ratings(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
Capacitance(1)
(TA = +25°C, f = 1.0MHz) TQFP only
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV references the interpolated capacitance when the input and
the output signals switch from 0V to 3V or from 3V to 0V.
Maximum Operating
Temperature and Supply Voltage(1)
Recommended DC Operating
Conditions
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Symbol Pin Name
A
0
P1 - A
10
P1 Add ress Lines - Po rt 1
A
0
P2 - A
10
P2 Add ress Lines - Po rt 2
A
0
P3 - A
10
P3 Add ress Lines - Po rt 3
A
0
P4 - A
10
P4 Add ress Lines - Po rt 4
I/O
0
P1 - I/O
7
P1 Data I/O - Port 1
I/O
0
P2 - I/O
7
P2 Data I/O - Port 2
I/O
0
P3 - I/O
7
P3 Data I/O - Port 3
I/O
0
P4 - I/O
7
P4 Data I/O - Port 4
R/ W P 1 Re a d / Write - Port 1
R/ W P 2 Re a d / Write - Port 2
R/ W P 3 Re a d / Write - Port 3
R/ W P 4 Re a d / Write - Port 4
GND Ground
CE P 1 Chi p E n able - Port 1
CE P 2 Chi p E n able - Port 2
CE P 3 Chi p E n able - Port 3
CE P 4 Chi p E n able - Port 4
OE P1 Outp ut Enable - P ort 1
OE P2 Outp ut Enable - P ort 2
OE P3 Outp ut Enable - P ort 3
OE P4 Outp ut Enable - P ort 4
BUSY P1 Write Dis able - Po rt 1
BUSY P2 Write Dis able - Po rt 2
BUSY P3 Write Dis able - Po rt 3
BUSY P4 Write Dis able - Po rt 4
V
CC
Power
2674 tbl 01
Symbol Rating Commercial
& Industri al Military Unit
V
TERM
(2)
Te rminal Voltage
with Res p e c t to
GND
-0.5 to +7.0 -0.5 to +7.0 V
T
BIAS
Temperature
Und e r B ias -55 to +125 -65 to +135
o
C
T
STG
Storage
Temperature - 65 to + 150 -65 to +150
o
C
I
OUT
DC O utp u t Cu rre n t 50 50 mA
2674 tbl 02
Grade Ambient
Temperature GND Vcc
Military -55
O
C to + 125
O
C0V5.0V + 10%
Commercial 0
O
C to + 70
O
C0V5.0V + 10%
Industrial -40
O
C to +85
O
C0V5.0V + 10%
2674 tbl 04
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Inp ut Cap ac i tanc e V
IN
= 0V 9 pF
C
OUT
Output Capacitance V
OUT
= 0V 10 p F
2674 tbl 03
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Inp ut Hi g h Vo l tag e 2. 2
____
6.0
(2)
V
V
IL
Inp ut Lo w Vo l tag e -0. 5
(1)
____
0.8 V
2674 tbl 05
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
5
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. VCC = 5V, TA = +25°C and are not production tested.
3. f = 0 means no address or control lines change.
4. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
5. For the case of one port, divide the appropriate current above by four.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,5) (VCC = 5.0V ± 10%)
Symbol Parameter Condition
7052X20
Com'l Only 7052X25
Com'l, Ind
& Mi l itary
7052X35
Com'l &
Military
UnitVersion Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max.
I
CC1
Operating Power
Supply Current
(All Ports Active)
CE = V
IL
Outputs Disabled
f =
0
(3)
COM'L. S
L150
150 300
250 150
150 300
250 150
150 300
250 mA
MIL. &
IND. S
L
____
____
____
____
150
150 360
300 150
150 360
300
I
CC2
Dy nami c Op era ti ng
Current
(All Ports Active)
CE = V
IL
Outputs Disabled
f =
f
MAX(4)
COM'L. S
L240
210 370
325 225
195 350
305 210
180 335
290 mA
MIL. &
IND. S
L
____
____
____
____
225
195 400
340 210
180 395
330
I
SB
Standby Current
(A ll Po rts - TTL Le v e l
Inputs)
CE = V
IH
f =
f
MAX(4)
COM'L. S
L70
60 95
80 45
40 85
70 40
35 75
60 mA
MIL. &
IND. S
L
____
____
____
____
45
40 115
85 40
35 110
80
I
SB1
Full Standby Current
(A ll Po rts - All CMOS
Le ve l Inp uts)
All Ports
CE > V
CC
- 0. 2V
V
IN
> V
CC
- 0.2V o r
V
IN
< 0.2V, f = 0
(3)
COM'L. S
L1.5
0.3 15
1.5 1.5
0.3 15
1.5 1.5
0.3 15
1.5 mA
MIL. &
IND. S
L
____
____
____
____
1.5
0.3 30
4.5 1.5
0.3 30
4.5
2674 tbl 06
Symbol Parameter Test Conditions
7052S 7052L
UnitMin. Max. Min. Max.
|I
LI
| Input Le akag e Curre nt
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
10
___
5µA
|I
LO
| Outp ut Le akag e Current CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5µA
V
OL
Outp ut Lo w Vo ltag e I
OL
= 4mA
___
0.4
___
0.4 V
V
OH
Outp ut Hig h Vol tage I
OH
= -4mA 2.4
___
2.4
___
V
2674 tbl 07
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
6
Low VCC Data Retention Waveform
Data Retention Characteristics Over All Temperature Ranges(4)
(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V
NOTES:
1. VCC = 2V, TA = +25°C
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
4. Industrial temperature: For other speeds, packages and powers contact your sales office.
AC Test Conditions
Figure 1. AC Output Test Load Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig
Symbol Parameter Test Condi tion Min. Typ.
(1)
Max. Unit
V
DR
V
CC
fo r Data Re tentio n V
CC
= 2
V
2.0
___ ___
V
I
CCDR
Data Re te ntio n Curre nt CE > V
HC
V
IN
> V
HC
or < V
LC
Com'l.
___
25 600 µA
Mil. & Ind.
___
25 1800
t
CDR
(3)
C hi p Des e le c t to Data Re te ntion Tim e 0
___ ___
ns
t
R
(3)
Op e ratio n Re co v ery Time t
RC
(2)
___ ___
ns
2674 tb l 08 a
DATA RETENTION MODE
V
CC
CE
2674 drw 05
4.5V
t
CDR
t
R
V
IH
V
DR
V
IH
4.5VV
DR
2V
≥
347Ω
893Ω
30pF
5V
2674 drw 06
DATA
OUT
347Ω
893Ω
5pF*
5V
DATA
OUT
,
Inp ut Pulse Le ve ls
Inp ut Ris e/Fall Tim es
Input Timing Refe re nc e Le ve ls
Outp ut Re fere nce Le ve ls
Outp ut Load
GND to 3.0V
5ns Max .
1.5V
1.5V
Figure s 1 and 2
2674 tbl 08b
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
7
2674 drw 08
t
AOE
t
LZ
t
HZ
DATA
OUT
CE
t
ACE
VALID DATA
OE
CURRENT
I
CC
I
SB
t
PU
50%
t
LZ
t
PD
50%
t
HZ
2674 drw 07
t
AA
t
OH
t
OH
DATA
OUT
ADDRESS
t
RC
DATA VALIDPREVIOUS DATA VALID
Timing Waveform of Read Cycle No. 1, Any Port(1)
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(3)
NOTES:
1. Transition is measured 0mV from Low or High-Impedance voltage with the Output Test Load (Figure 2)
2. This parameter is guaranteed by device characterization but is not production tested.
3. 'X' in part number indicates power rating (S or L)
Timing Waveform of Read Cycle No. 2, Any Port(1,2)
NOTES:
1. R/W = VIH, OE = VIL and CE = VIL.
NOTES:
1. R/W = VIH for Read Cycles.
2. Addresses valid prior to or coincident with CE transition LOW.
7052X20
Com 'l On ly 7052X25
Com'l, Ind
& Military
7052X35
Co m ' l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
READ CYCLE
t
RC
Re ad Cy c le Time 20
____
25
____
35
____
ns
t
AA
Address Access Time
____
20
____
25
____
35 ns
t
ACE
Chip Enable Access Time
____
20
____
25
____
35 ns
t
AOE
Outp ut E nabl e Acc e ss Tim e
____
10
____
15
____
25 ns
t
OH
Outp ut Ho ld from Ad d ress Chang e 0
____
0
____
0
____
ns
t
LZ
Outp ut Lo w-Z Time
(1,2)
5
____
5
____
5
____
ns
t
HZ
Outpu t Hig h-Z Tim e
(1,2)
____
12
____
15
.____
15 ns
t
PU
Chip E nab l e to P owe r Up Tim e
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disab le to Po we r Down Time
(2)
____
20
____
25
____
35 ns
267 4 tbl 09
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(7)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers
to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement
does not apply and the write pulse can be as short as the specified tWP. Specified for OE = VIH (refer to “Timing Waveform of Write Cycle”, Note 8).
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. To ensure that the write cycle is inhibited on port "A" during contention from Port "B". Port "A" may be any of the four ports and Port "B" is any other port.
6. To ensure that a write cycle is completed on port "A" after contention from Port "B". Port "A" may be any of the four ports and Port "B" is any other port.
7. 'X' in part number indicates power rating.
7052X20
Com 'l On ly 7052X25
Co m ' l &
Military
7052X35
Co m ' l &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
WR IT E CY CLE
t
WC
Write Cycle Time 20
____
25
____
35
____
ns
t
EW
Chip Enable to End-of-Write
(3)
15
____
20
____
30
____
ns
t
AW
Address Valid to End-of-Write 15
____
20
____
30
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WP
Write Pulse Width
(3)
15
____
20
____
30
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
15
____
20
____
ns
t
HZ
Outpu t Hig h-Z Tim e
(1,2)
____
15
____
15
____
15 ns
t
DH
Data Hol d Tim e 0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in Hig h-Z
(1,2)
____
12
____
15
____
15 ns
t
OW
Outpu t Ac ti v e from E nd -o f-Wr ite
(1,2)
0
____
0
____
0
____
ns
t
WDD
Write Pulse to Data Delay
(4)
____
35
____
45
____
55 ns
t
WDD
Write Data Valid to Read Data Del ay
(4)
____
30
____
35
____
45 ns
BUSY INPUT TIMI NG
t
WB
Write to BUSY
(5)
0
____
0
____
0
____
ns
t
WH
Write Ho ld Afte r BUSY
(6)
15
____
15
____
20
____
ns
2674 t bl 10
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
9
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5,8)
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1, 5)
NOTES:
1. R/W or CE = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL.
3. tWR is measured from the earlier of CE or R/W = VIH to the end of write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed but is not production
tested.
8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed
on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
CE
2674 drw 09
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
R/W
t
WP
DATA
OUT
t
WZ
(7)
(4) (4)
(2)
t
OW
OE
t
HZ
t
LZ
(7)
t
HZ
(6)
(3)
(9)
t
DH
(7)
CE
2674 drw 10
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
R/W
t
EW
t
DH
(9)
(6) (2) (3)
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
10
Timing Waveform of Write with Port-to-Port Read(1,2,3)
Functional Description
The IDT7052 provides four ports with separate control, address, and
I/O pins that permit independent access for reads or writes to any location
in memory. These devices have an automatic power down feature
controlled by CE. The CE controls on-chip power down circuitry that
permits the respective port to go into standby mode when not selected (CE
= VIH). When a port is enabled, access to the entire memory array is
permitted. Each port has its own Output Enable control (OE). In the read
mode, the port’s OE turns on the output drivers when set LOW. READ/
WRITE conditions are illustrated in the table below.
Timing Waveform of Write with BUSY Input
NOTES:
1. BUSY is asserted on Port "B" blocking R/W"B" until BUSY"B" goes HIGH.
Truth Table I – Read/Write Control(3)
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don’t Care, "Z "= High Impedance
2. If BUSY = VIL, write is blocked.
3 . For valid write operation, no more than one port can write to the same address
location at the same time.
NOTES:
1. Assume BUSY input = VIH and CE = VIL for the writing port.
2. OE = VIL for the reading ports.
3. All timing is the same for left and right ports. Port "A" may be either of the four ports and Port "B" is any other port.
2674 drw 11
ADDR
"A"
t
WC
DATA
"B"
MATCH
t
WP
R/W
"A"
DATA
IN"A"
ADDR
"B"
t
DH
VALID
MATCH
VALID
t
DDD
t
WDD
t
DW
2674 drw 12
R/W
"A"
BUSY
"B"
t
WP
t
WH
t
WB
R/W
"B"
(1)
,
Any Port
(1)
R/WCE OE D
0-7
Function
X H X Z Port Deselected: Power-Down
XHX Z CE
P1
=CE
P2
=CE
P3
=CE
P4
=V
IH
Power Down Mode I
SB
or I
SB1
LLXDATA
IN
Data o n p o rt writte n into m em o ry
(2)
HLLDATA
OUT
Data in memory output on port
X X H Z Outputs Disabled
2 674 tb l 1
1
6.42
IDT7052S/L
High-Speed 2K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges
11
Ordering Information
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and powers contact your sales office.
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I
(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML
G
PQF
PF
108-Pin Pin Grid Array (G108-1)
132-Pin Plastic Quad Flatpack (PQ132-1)
120-Pin Thin Quad Plastic Flatpack (PN120-1)
20
25
35
XXXX
Device
Type
IDT
Speed
in nanosecond
s
2674 drw 13
L
S
Low Power
Standard Power
7052 16K (2K x 8) FourPort RAM
Commercial Only
Commercial, Industrial & Military
Commercial & Military
,
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
1/18/99: Initiated datasheet document history
Converted to new format
Cosmetic typographical corrections
Added additional notes to pin configurations
6/4/99: Changed drawing format
Page1 Corrected DSC number
11/10/99: Replaced IDT logo
11/18/99: Page 10 Fixed typo in caption for BUSY Input waveform
5/23/00: Page 4 Increased storage temperature parameter
Clarified TA parameter
Page 5 DC Electrical parameters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
10/22/01: Pages 2 & 3 Added date revision for pin configurations
Page 5, 7 & 8 Added Industrial temp to column heading for 25ns speed to DC & AC Electrical Characteristics
Page 11 Added Industrial temp offering to 25ns ordering information
Page 4, 5, 7 & 8 Removed Industrial temp footnote from all tables
Page 1 & 11 Replace TM logo with ® logo
