64-Position OTP Digital Potentiometer
AD5273
Rev. H
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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FEATURES
64 positions
One-time programmable (OTP)1 set-and-forget
Resistance setting—low cost alternative over EEMEM
Unlimited adjustments prior to OTP activation
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ end-to-end terminal resistance
Compact 8-lead SOT-23 standard package
Ultralow power: IDD = 5 μA maximum
Fast settling time: tS = 5 μs typical during power-up
I2C-compatible digital interface
Computer software2 replaces microcontroller in
factory programming applications
Wide temperature range: −40°C to +105°C
Low operating voltage: 2.7 V to 5.5 V
OTP validation check function
APPLICATIONS
System calibrations
Electronics level settings
Mechanical potentiometers and trimmer replacement
Automotive electronics adjustments
Transducer circuit adjustments
Programmable filters up to 6 MHz BW3
GENERAL DESCRIPTION
The AD5273 is a 64-position, one-time programmable (OTP)
digital potentiometer4 that employs fuse link technology to
achieve permanent program setting. This device performs the
same electronic adjustment function as most mechanical
trimmers and variable resistors. It allows unlimited adjustments
before permanently setting the resistance values. The AD5273 is
programmed using a 2-wire, I2C-compatible digital control.
During write mode, a fuse blow command is executed after the
final value is determined, thereby freezing the wiper position at
a given setting (analogous to placing epoxy on a mechanical
trimmer). When the permanent setting is achieved, the value
does not change, regardless of the supply variations or environ-
mental stresses under normal operating conditions. To verify
the success of permanent programming, Analog Devices, Inc.,
patterned the OTP validation such that the fuse status can be
discerned from two validation bits in the read mode.
FUNCTIONAL BLOCK DIAGRAM
GND
I
2
C INTERFACE
AND
CONTROL LOGIC
A
W
B
WIPER
REGISTER
FUSE
LINK
V
DD
AD0
SDA
SCL
AD5273
03224-001
Figure 1.
In addition, for applications that program the AD5273 at the
factory, Analog Devices offers device programming software2
running on Windows® NT, Windows 2000, and Windows XP
operating systems. This software application effectively replaces
any external I2C controllers, which in turn enhances the user
system’s time-to-market.
The AD5273 is available in 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
resistances and in a compact 8-lead SOT-23 standard package.
It operates from −40°C to +105°C.
Along with its unique OTP feature, the AD5273 lends itself
well to general digital potentiometer applications due to its
effective resolution, array resistance options, small footprint,
and low cost.
An AD5273 evaluation kit and software are available. The kit
includes the connector and cable that can be converted for
factory programming applications.
For applications that require dynamic adjustment of resistance
settings with nonvolatile EEMEM, users should refer to the
AD523x and AD525x families of nonvolatile memory digital
potentiometers.
1 OTP allows unlimited adjustments before permanent setting.
2 Analog Devices cannot guarantee the software to be 100% compatible to all
systems due to the wide variation in computer configurations.
3 Applies to 1 kΩ parts only.
4 The terms digital potentiometer, VR, and RDAC are used interchangeably.
AD5273
Rev. H | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 13
One-Time Programming ........................................................... 13
Variable Resistance and Voltage for Rheostat Mode ............. 14
Variable Resistance and Voltage for Potentiometer Mode .... 14
ESD Protection ........................................................................... 15
Terminal Voltage Operating Range .......................................... 15
Power-Up/Power-Down Sequences ......................................... 15
Power Supply Considerations ................................................... 15
Controlling the AD5273 ................................................................ 16
Software Programming ............................................................. 16
I2C Controller Programming .................................................... 17
Controlling Two Devices on One Bus ..................................... 18
Applications Information .............................................................. 19
DAC .............................................................................................. 19
Programmable Voltage Source with Boosted Output ........... 19
Programmable Current Source ................................................ 19
Gain Control Compensation .................................................... 19
Programmable Low-Pass Filter ................................................ 20
Level Shift for Different Voltages Operation .......................... 20
RDAC Circuit Simulation Model ............................................. 20
Evaluation Board ............................................................................ 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
10/10—Rev. G to Rev. H
Changes to OTP Power Supply Parameter in Table 1 .................. 4
Changes to VDD Pin Description in Table 3................................... 7
Changes to One-Time Programming Section ............................ 13
Changes to Power Supply Considerations Section, Figure 38 .. 15
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
8/08—Rev. F to Rev. G
Changes to Power Supplies Parameter in Table 1 ......................... 3
Updated Fuse Blow Condition to 400 ms Throughout ............... 5
1/08—Rev. E to Rev. F
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 6
Changes to Table 3 ............................................................................ 7
Inserted Figure 28 ........................................................................... 12
Changes to One-Time Programming Section ............................ 13
Changes to Power Supply Considerations Section ..................... 15
Deleted Figure 35 ............................................................................ 15
Changes to Figure 36 ...................................................................... 15
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
1/05—Rev. D to Rev. E
Changes to Features .......................................................................... 1
Changes to Specifications ................................................................. 3
Changes to Table 3 ............................................................................. 6
Changes to Power Supply Considerations Section .................... 15
Changes to Figure 35 and Figure 37............................................. 15
Changes to DAC Section ............................................................... 19
Changes to Level Shift for Different Voltages
Operation Section........................................................................... 20
Deleted the Resistance Scaling Section ....................................... 20
Deleted the Resolution Enhancement Section ........................... 20
12/04—Rev. C to Rev. D
Updated Format .................................................................. Universal
Changes to Specifications ................................................................. 3
Changes to Theory of Operation Section.................................... 13
Changes to Power Supply Considerations Section .................... 15
Changes to Figure 35, Figure 36, and Figure 37 ......................... 15
11/03—Rev. B to Rev. C
Changes to SDA Bit Definitions and Descriptions .................... 10
Changes to One-Time Programming (OTP) Section................ 11
Changes to Table III ....................................................................... 11
Changes to Power Supply Considerations .................................. 13
Changes to Figure 8, Figure 9, and Figure 10 ............................. 13
AD5273
Rev. H | Page 3 of 24
10/03—Rev. A to Rev. B
Changes to Features .......................................................................... 1
Changes to Applications ................................................................... 1
Changes to Specifications ................................................................. 2
Changes to Absolute Maximum Ratings ........................................ 4
Changes to Pin Function Descriptions ........................................... 5
Changes to TPC 7, TPC 8, TPC 13, and TPC 14 Captions ......... 7
Deleted TPC 20; Renumbered Successive TPCs ........................... 9
Change to TPC 21 Caption .............................................................. 9
Change to the SDA Bit Definitions and Descriptions ................ 10
Replaced Theory of Operation Section ........................................ 11
Replaced Determining the Variable Resistance and
Voltage Section ................................................................................ 11
Replaced ESD Protection Section ................................................. 12
Replaced Terminal Voltage Operating Range Section ............... 12
Replaced Power-Up Sequence Section ......................................... 12
Replaced Power Supply Considerations Section ......................... 13
Changes to Application Section .................................................... 16
Change to Equation 9 ..................................................................... 17
Deleted Digital Potentiometer Family Selection Guide ............. 19
6/03—Rev. 0 to Rev. A
Change to Specifications .................................................................. 2
Change to Power Supply Considerations Section ....................... 12
Updated Outline Dimensions ........................................................ 20
12/02—Revision 0: Initial Version
AD5273
Rev. H | Page 4 of 24
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, VA < VDD, VB = 0 V, −40°C < TA < +105°C, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ1Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution N 6 Bits
Resistor Differential Nonlinearity2R-DNL
10 kΩ, 50 kΩ, 100 kΩ RWB, VA = NC −0.5 +0.05 +0.5 LSB
1 kΩ R
WB, VA = NC −1 +0.25 +1 LSB
Resistor Nonlinearity2
R-INL
10 kΩ, 50 kΩ, 100 kΩ RWB, VA = NC −0.5 +0.10 +0.5 LSB
1 kΩ RWB, VA = NC −5 +2 +5 LSB
Nominal Resistance Tolerance3ΔRAB/RAB T
A = 25°C
10 kΩ, 50 kΩ, 100 kΩ −30 +30 %
Nominal Resistance, 1 kΩ RAB 0.8 1.2 1.6 kΩ
Rheostat Mode Temperature
Coefficient4
(ΔRAB/RAB)/∆T Wiper = NC 300 ppm/°C
Wiper Resistance RW IW = VDD/R, VDD = 3 V or 5 V 60 100 Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Differential Nonlinearity5DNL −0.5 +0.1 +0.5 LSB
Integral Nonlinearity5
INL −0.5 +0.5 LSB
Voltage Divider4 Temperature Coefficient (ΔVW/VW)/ΔT Code = 0x20 10 ppm/°C
Full-Scale Error VWFSE Code = 0x3F −1 0 LSB
10 kΩ, 50 kΩ, 100 kΩ −1 0 LSB
1 kΩ −6 0 LSB
Zero-Scale Error VWZSE Code = 0x00 −6 0 LSB
10 kΩ, 50 kΩ, 100 kΩ 0 1 LSB
1 kΩ 0 5 LSB
RESISTOR TERMINALS
Voltage Range6VA, VB, VW GND VDD V
Capacitance7 A, B CA, CB f = 5 MHz, measured to GND,
code = 0x20
25 pF
Capacitance7 W CW f = 1 MHz, measured to GND,
code = 0x20
55 pF
Common-Mode Leakage ICM V
A = VB = VW 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High (SDA and SCL)8VIH 0.7 × VDD V
DD + 0.5 V
Input Logic Low (SDA and SCL)8 VIL −0.5 0.3 × VDD V
Input Logic High (AD0) VIH 3.0 VDD V
Input Logic Low (AD0) VIL V
IN = 0 V or 5 V 0 0.4 V
Input Logic Current IIL 0.01 1 μA
Input Capacitance7
CIL 3 pF
Output Logic Low (SDA) VOL 0.4 V
Three-State Leakage Current IOZ ±1 μA
Output Capacitance7
COZ 3 pF
POWER SUPPLIES
Power Supply Range VDD 2.7 5.5 V
OTP Power Supply8, 9VDD_OTP T
A = 25°C
1 kΩ (DD8), 10 kΩ (DD9) 5.0 5.25 5.5 V
50 kΩ (DYG), 100 kΩ (DYH) 4.75 5.0 5.25 V
Supply Current IDD V
IH = 5 V or VIL = 0 V 0.1 5 μA
OTP Supply Current8, 10,11 IDD_OTP T
A = 25°C, VDD_OTP = 5 V 100 mA
AD5273
Rev. H | Page 5 of 24
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
Power Dissipation12 P
DISS V
IH = 5 V or VIL = 0 V, VDD = 5 V 0.5 27.5 μW
Power Supply Sensitivity PSRR RAB = 1 kΩ −0.3 +0.3 %/%
PSRR RAB = 10 kΩ, 50 kΩ, 100 kΩ −0.05 +0.05 %/%
DYNAMIC CHARACTERISTICS7, 13, 14
Bandwidth, −3 dB BW_1 kΩ RAB = 1 kΩ, code = 0x20 6000 kHz
BW_10 kΩ RAB = 10 kΩ, code = 0x20 600 kHz
BW_50 kΩ RAB = 50 kΩ, code = 0x20 110 kHz
BW_100 kΩ RAB = 100 kΩ, code = 0x20 60 kHz
Total Harmonic Distortion THDW VA = 1 V rms, RAB = 1 kΩ, VB = 0 V,
f = 1 kHz
0.05 %
Adjustment Settling Time tS1 VA = 5 V ± 1 LSB error band,
VB = 0 V, measured at VW
5 μs
Power-Up Settling Time—
After Fuses Blown
tS2 VA = 5 V ± 1 LSB error band,
VB = 0 V, measured at VW, VDD = 5 V
5 μs
Resistor Noise Voltage eN_WB RAB = 1 kΩ, f = 1 kHz, code = 0x20 3 nV/√Hz
INTERFACE TIMING CHARACTERISTICS7, 14, 15 Applies to all parts
SCL Clock Frequency fSCL 400 kHz
tBUF Bus Free Time Between
Stop and Start
t1 1.3 μs
tHD; STA Hold Time
(Repeated Start)
t2 After this period, the first clock
pulse is generated
0.6 μs
tLOW Low Period of SCL Clock t3 1.3 μs
tHIGH High Period of SCL Clock t4 0.6 50 μs
tSU; STA Setup Time for
Start Condition
t5 0.6 μs
tHD; DAT Data Hold Time t6 0.9 μs
tSU; DAT Data Setup Time t7 0.1 μs
tF Fall Time of Both SDA and
SCL Signals
t8 0.3 μs
tR Rise Time of Both SDA and
SCL Signals
t9 0.3 μs
tSU; STO Setup Time for Stop Condition t10 0.6 μs
OTP Program Time t11 400 ms
1 Typical values represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 ∆RWB/∆T = ∆RWA/∆T. Temperature coefficient is code-dependent; see the Typical Performance Characteristics section.
5 INL and DNL are measured at VW. INL with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VW with the RDAC configured as a
potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating
conditions.
6 The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
7 Guaranteed by design; not subject to production test.
8 The minimum voltage requirement on the VIH is 0.7 × VDD. For example, VIH min = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.
However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
9 Different from the operating power supply; the power supply for OTP is used one time only.
10 Different from the operating current; the supply current for OTP lasts approximately 400 ms for the one time it is needed.
11 See Figure 28 for the energy plot during the OTP program.
12 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13 Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.
The highest R value results in the minimum overall power consumption.
14 All dynamic characteristics use VDD = 5 V.
15 See Figure 29 for the location of the measured values.
AD5273
Rev. H | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
VDD to GND −0.3 V +6.5 V
VA, VB, VW to GND GND, VDD
Maximum Current
IWB, IWA Pulsed ±20 mA
IWB Continuous (RWB ≤ 1 kΩ, A Open)1±4 mA
IWA Continuous (RWA ≤ 1 kΩ, B Open) ±4 mA
Digital Input and Output Voltage to GND 0 V, VDD
Operating Temperature Range −40°C to +105°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature −65°C to +150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Thermal Resistance θJA, SOT-232230°C/W
1 Maximum terminal current is bounded by the maximum current handling
of the switches, the maximum power dissipation of the package; the maxi-
mum applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJ max – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5273
Rev. H | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
W
1
V
DD 2
GND
3
SCL
4
A
8
B
7
AD0
6
SDA
5
AD5273
TOP VIEW
(Not to Scale)
03224-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 W Wiper Terminal W. GND ≤ VW ≤ VDD.
2 VDD Positive Power Supply. Specified for non-OTP operation from 2.7 V to 5.5 V. For OTP programming, VDD_OTP
must be set within the window of 5 V to 5.5 V for the 1 kΩ (DD8) and 10 kΩ (DD9) options, or within the
window of 4.75 V to 5.25 V for the 50 kΩ (DYG) and 100 kΩ (DYH) options, and be capable of sourcing 100 mA.
3 GND Common Ground.
4 SCL Serial Clock Input. Requires a pull-up resistor. If it is driven directly from a logic controller without the pull-up
resistor, ensure that the VIH minimum is 0.7 × VDD.
5 SDA Serial Data Input/Output. Requires a pull-up resistor. If it is driven directly from a logic controller without the
pull-up resistor, ensure that the VIH minimum is 0.7 × VDD.
6 AD0 I2C Device Address Bit. Allows a maximum of two AD5273 devices to be addressed.
7 B Resistor Terminal B. GND ≤ VB ≤ VDD.
8 A Resistor Terminal A. GND ≤ VA ≤ VDD.
AD5273
Rev. H | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
V
DD
= 3V
V
DD
= 5V
CODE (Decimal)
0.5
0.3
–0.5064
CODE (Decimal)
0.10
0.06
–0.10 068
POTENTIOMETER MODE DNL (LSB)
16 24 32 40 48 56
0.02
–0.02
–0.06
8
RHEOSTAT MODE INL (LSB)
16 24 32 40 48 56
0.1
–0.1
–0.3
4
03224-006
R
AB
= 10kΩ
T
A
= +85°C
T
A
= +25°C
T
A
= +125°C
T
A
= –40°C
R
AB
= 10kΩ
T
A
= 25°C
03224-003
Figure 3. RINL vs. Code vs. Supply Voltages Figure 6. DNL vs. Code vs. Temperature
CODE (Decimal)
0.25
0.15
–0.25 064
CODE (Decimal)
0.10
0.06
–0.10 068
POTENTIOMETER MODE INL (LSB)
16 24 32 40 48 56
0.02
–0.02
–0.06
4
03224-007
R
AB
= 10kΩ
T
A
= 25°C
3V
5V
8
RHEOSTAT MODE DNL (LSB)
16 24 32 40 48 56
0.05
–0.05
–0.15
03224-004
R
AB
= 10kΩ
T
A
= 25°C
V
DD
= 5V
V
DD
= 3V
Figure 4. RDNL vs. Code vs. Supply Voltages Figure 7. INL vs. Code vs. Supply Voltages
CODE (Decimal)
0.10
0.06
–0.10 064
CODE (Decimal)
0.10
0.06
–0.10 068
POTENTIOMETER MODE DNL (LSB)
16 24 32 40 48 56
0.02
–0.02
–0.06
4
03224-008
R
AB
= 10kΩ
T
A
= 25°C
3V
5V
8
POTENTIOMETER MODE INL (LSB)
16 24 32 40 48 56
0.02
–0.02
–0.06
03224-005
R
AB
= 10kΩ
T
A
= +85°C
T
A
= +25°C
T
A
= +125°C
T
A
= –40°C
Figure 5. INL vs. Code vs. Temperature Figure 8. DNL vs. Code vs. Supply Voltages
AD5273
Rev. H | Page 9 of 24
61234 5
SUPPLY VOLTAGE (V)
0.025
0.020
00
POTENTIOMETER MODE LINEARITY (LSB)
0.015
0.010
0.005
03224-009
T
A
= 25°C
R
AB
= 10kΩ
CODE = 0x20
Figure 9. INL vs. Supply Voltage
SUPPLY VOLTAGE (V)
0.4
0.3
–0.106
RHEOSTAT MODE LINEARITY (LSB)
1234 5
0.2
0.1
0
03224-010
T
A
= 25°C
R
AB
= 10kΩ
CODE = 0x20
Figure 10. RINL vs. Supply Voltage
TEMPERATURE (°C)
0
–1.0
–40 100–20
FSE (LSB)
020406080
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
–0.8
–0.7
–0.9
03224-011
RAB = 10kΩ
VDD = 3V
VDD = 5V
Figure 11. Full-Scale Error
TEMPERATURE (°C)
1.0
0
–40 100–20
ZSE (LSB)
020406080
0.4
0.5
0.6
0.7
0.8
0.9
0.2
0.3
0.1
03224-012
RAB = 10kΩ
VDD = 3V
VDD = 5V
Figure 12. Zero-Scale Error
TEMPERATURE (°C)
0.16
0.04
–55 115–35 –15
SUPPLY CURRENT (μA)
5 25456585105
0.08
0.10
0.12
0.14
0.06
03224-013
VDD = 5.5V
RAB = 10kΩ
Figure 13. Supply Current vs. Temperature
INPUT LOGIC VOLTAGE (V)
10
0.0001061
SUPPLY CURRENT (mA)
2345
0.001
0.01
0.1
1
03224-014
TA = 25°C
RAB = 10kΩ
ALL DIGITAL
PINS TIED
TOGETHER
VDD = 5V
VDD = 2.7V
Figure 14. Supply Current vs. Digital Input Voltage
AD5273
Rev. H | Page 10 of 24
CODE (Decimal)
500
400
300
200
100
–3000648
RHEOSTAT MODE TEMPCO (ppm/
°
C)
16 24 32 40 48 56
0
–100
–200
03224-015
VDD = 5.5V
TA = 25°C
1kΩ
100kΩ
50kΩ
10kΩ
Figure 15. Rheostat Mode Tempco (∆RWB/RWB)/∆T vs. Code
CODE ( Deci mal )
40
30
20
10
0
–400648
POTENTIOMETER MODE TEMPCO (p pm/°C)
16 24 32 40 48 56
–10
–20
–30
03224-016
V
DD
= 5. 5V
1kΩ
10kΩ10kΩ
10kΩ
Figure 16. Potentiometer Mode Tempco (∆VW/VW)/∆T vs. Code
FREQUENCY (Hz)
0
–6
–12
–24
–18
–54
100 10M
MAGNITUDE (dB)
1k 10k 100k 1M
–30
–42
–36
–48
03224-017
0x3F
0x20
0x10
0x08
0x02 0x01 0x00
0x04
Figure 17. Gain vs. Frequency vs. Code, RAB = 1 kΩ
FREQUENCY (Hz)
0
–6
–12
–24
–18
–54
100 1M
MAGNITUDE (dB)
1k 10k 100k
–30
–42
–36
–48
03224-018
0x3F
0x20
0x10
0x08
0x04
0x02
0x01
0x00
Figure 18. Gain vs. Frequency vs. Code, RAB = 10 kΩ
FREQUENCY (Hz)
0
–6
–12
–24
–18
–54
100 1M
MAGNITUDE (dB)
1k 10k 100k
–30
–42
–36
–48
03224-019
0x3F
0x20
0x10
0x08
0x04
0x02
0x01
0x00
Figure 19. Gain vs. Frequency vs. Code, RAB = 50 kΩ
FREQUENCY (Hz)
0
–6
–12
–24
–18
–54
100 1M
MAGNITUDE (dB)
1k 10k 100k
–30
–42
–36
–48
03224-020
0x3F
0x20
0x10
0x08
0x04
0x02
0x01
0x00
Figure 20. Gain vs. Frequency vs. Code, RAB = 100 kΩ
AD5273
Rev. H | Page 11 of 24
FREQUENCY (Hz)
12
6
0
–48 10M100
MAGNITUDE (dB)
1k 10k 100k 1M
–30
–24
–18
–12
–6
–36
–42
03224-021
1k
Ω
100k
Ω
50k
Ω
10k
Ω
Figure 21. −3 dB Bandwidth
FRE QUENC Y (Hz)
–
80
0100 1M1k
POWER SUP PLY REJECTI ON
R
A
TIO (dB)
10k 100k
–20
–40
–60
03224-022
T
A
= 25°C
CODE = 0x20
V
A
= 2.5V, V
B
= 0V
V
DD
= 5V DC ±1.0V p - p AC
V
DD
= 3V DC ±0.6V p-p AC
Figure 22. PSRR vs. Frequency
SCL = 5V/DIV
V
W
= 10mV/DI V
V
DD
= 5. 5V
V
A
= 5. 5V
V
B
= GND
10mV 5V 500ns
03224-023
fCLK
= 100kHz
Figure 23. Digital Feedthrough
SCL = 5V/DI
V
V
DD
= 5.5V
V
A
= 5.5V
V
B
= GND
f
CLK
= 400kHz
DATA 0x00 0x3F
5V 5V 5μs
V
W
= 5V/DIV
03224-024
Figure 24. Large Settling Time
SCL = 5V/DIV
V
W
= 50mV/DIV
V
DD
= 5.5V
V
A
= 5.5V
V
B
= GND
f
CLK
= 100kHz
DATA 0x20 0x1F
5V50mV 200ns
03224-025
Figure 25. Midscale Glitch Energy
V
DD
= 5V/DI
V
V
W
= 1V/DIV
5V1V
OTP PROG RAMMED AT M S
V
DD
= 5.5V
V
A
= 5.5V
R
AB
= 10kΩ
w
5µs
03224-026
Figure 26. Power-Up Settling Time After Fuses Blown
AD5273
Rev. H | Page 12 of 24
CODE ( D ecimal)
10
1
0.01064
03224-060
CH1 20.0mAΩM200ns A CH1 32.4mA
T 588. 000ns
1
8
THEORETIC
A
L I
WB_MAX
(mA)
16 24 32 40 48 56
0.1
03224-027
V
A
= V
B
= OPEN
T
A
= 25°C
R
AB
= 1kΩ
R
AB
= 10kΩ
R
AB
= 50kΩ
R
AB
= 100kΩ
Figure 28. OTP Program Energy Plot for Single Fuse
Figure 27. IWB_MAX vs. Code
SCL
S
D
A
PS P
t
1
t
3
t
4
t
2
t
8
t
9
t
5
t
7
t
10
t
8
t
9
t
6
03224-028
Figure 29. Interface Timing Diagram
AD5273
Rev. H | Page 13 of 24
THEORY OF OPERATION
The AD5273 is a one-time programmable (OTP), set-and-forget,
6-bit digital potentiometer. The AD5273 allows unlimited 6-bit
adjustments prior to the OTP. OTP technology is a proven cost-
effective alternative over EEMEM in one-time memory program-
ming applications. The AD5273 employs fuse link technology to
achieve the memory retention of the resistance setting function.
It comprises six data fuses, which control the address decoder for
programming the RDAC, one user mode test fuse for checking setup
error, and one programming lock fuse for disabling any further
programming once the data fuses are programmed correctly.
ONE-TIME PROGRAMMING
Prior to OTP activation, the AD5273 presets to midscale during
power-on. After the wiper is set to the desired position, the resis-
tance can be permanently set by programming the T bit and the
one-time VDD_OTP to high and by coding the part properly (see
Figure 31). To blow the fuses to achieve a given nonvolatile setting,
the fuse link technology of the AD5273 requires a VDD_OTP from
5 V to 5.5 V for the 1 kΩ (DD8) and 10 kΩ (DD9) options, or
from 4.75 V to 5.25 V for the 50 kΩ (DYG) and 100 kΩ (DYH)
options. During operation, however, VDD can be 2.7 V to 5.5 V.
Therefore, a system supply that is lower than VDD_OTP requires an
external supply for OTP. The user is allowed only one attempt
to blow the fuses. If the user fails to blow the fuses on the first
attempt, the fuse structure may change such that they can never
be blown, regardless of the energy applied during subsequent
events. For details, see the Power Supply Considerations section.
The device control circuit has two validation bits, E1 and E0,
that can be read back in the read mode to check the program-
ming status, as shown in Figure 32. Users should always read
back the validation bits to ensure that the fuses are properly
blown. After the fuses have been blown, all fuse latches are
enabled upon subsequent power-on; therefore, the output
corresponds to the stored setting. Figure 30 shows a detailed
functional block diagram.
SDA
SCL A
W
B
FUSES
EN
DAC
REG.
I
2
C INTERFACE
COMPARATOR
ONE-TIME
PROGRAM/TEST
CONTROL BLOCK
MUX DECODER
FUSE
REG.
03224-031
Figure 30. Detailed Functional Block Diagram
S010110AD00ATXXXXXXXAXXD5D4D3D2D1D0AP
SLAVE ADDRESS BYTE INSTRUCTION BYTE DATA BYTE
03224-029
Figure 31. SDA Write Mode Bit Format
S 0 1 0 1 1 0 AD0 1 A E1 E0 D5 D4 D3 D2 D1 D0 A P
SLAVE ADDRESS BYTE DATA BYTE
03224-030
Figure 32. SDA Read Mode Bit Format
SDA Bit Definitions and Descriptions
S = start condition.
P = stop condition.
A = acknowledge.
X = don’t care.
T = OTP programming bit. Logic 1 programs wiper position
permanently.
D5, D4, D3, D2, D1, D0 = data bits.
E1, E0 = OTP validation bits.
0, 0 = ready to program.
0, 1 = test fuse not blown successfully. (For factory setup
checking purpose only. Users should not see these
combinations.)
1, 0 = fatal error. Do not retry. Discard the unit.
1, 1 = programmed successfully. No further adjustments
possible.
AD0 = I2C device address bit. Allows maximum of two
AD5273s to be addressed.
AD5273
Rev. H | Page 14 of 24
VARIABLE RESISTANCE AND VOLTAGE FOR
RHEOSTAT MODE
If only the W-to-B or W-to-A terminals are used as variable
resistors, the unused A or B terminal can be opened or shorted
with W. This operation is called rheostat mode (see Figure 33).
03224-032
A
W
B
A
W
B
A
W
B
Figure 33. Rheostat Mode Configuration
The nominal resistance, RAB, of the RDAC has 64 contact points
accessed by the wiper terminal, plus the B terminal contact if
RWB is considered. The 6-bit data in the RDAC latch is decoded
to select one of the 64 settings. Assuming that a 10 kΩ part is
used, the wiper’s first connection starts at Terminal B for Data
Register 0x00. This connection yields a minimum of 60 Ω
resistance between Terminal W and Terminal B because of the
60 Ω wiper contact resistance. The second connection is the
first tap point, which corresponds to 219 Ω (RW = 1 × RAB/63 +
RW) for Data Register 0x01, and so on. Each LSB data value
increase moves the wiper up the resistor ladder until the last
tap point is reached at 10,060 Ω (63 × RAB/63 + RW). Figure 34
shows a simplified diagram of the equivalent RDAC circuit.
The general equation determining RWB is
()
W
AB
WB RR
D
DR +×= 63 (1)
where:
D is the decimal equivalent of the 6-bit binary code.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
Table 4. RWB vs. Codes; RAB = 10 kΩ; Terminal A Opened
D (Dec) RWB (Ω) Output State
63 10,060 Full scale (RAB + RW)
32 5139 Midscale
1 219 1 LSB
0 60 Zero scale (wiper contact resistance)
Because a finite wiper resistance of 60 Ω is present in the zero-
scale condition, care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
20 mA. Otherwise, degradation or possible destruction of the
internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the Wiper W and Terminal A also produces a
complementary resistance, RWA . When these terminals are used,
Terminal B can be opened or shorted to W. Setting the resistance
value for RWA starts at a maximum value of resistance and
decreases as the data loaded in the latch increases in value.
The general equation for this operation is
()
W
ABWA RR
D
DR +×
−
=63
63 (2)
Table 5. RWA vs. Codes; RAB =10 kΩ; Terminal B Opened
D (Dec) RWA (Ω) Output State
63 60 Full scale
32 4980 Midscale
1 9901
1 LSB
0 10,060 Zero scale
The typical distribution of the resistance tolerance from device
to device is process-lot dependent, and it is possible to have
±30% tolerance.
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
A
W
B
03224-033
Figure 34. AD5273 Equivalent RDAC Circuit
VARIABLE RESISTANCE AND VOLTAGE FOR
POTENTIOMETER MODE
If all three terminals are used, the operation is called the
potentiometer mode. The most common configuration is
the voltage divider operation (see Figure 35).
A
V
I
W
B
V
O
03224-034
Figure 35. Potentiometer Mode Configuration
Ignoring the effect of the wiper resistance, the transfer function
is simply
()
A
WV
D
DV 63
= (3)
A more accurate calculation, which includes the wiper
resistance effect, yields
()
A
W
AB
W
AB
WV
RR
RR
D
DV 2
63
+
+
= (4)
AD5273
Rev. H | Page 15 of 24
Unlike rheostat mode where the absolute tolerance is high,
potentiometer mode yields an almost ratiometric function of
D/63 with a relatively small error contributed by the RW terms.
Therefore, the tolerance effect is almost cancelled. Although the
step resistor, RS, and CMOS switch resistor, RW, have very differ-
ent temperature coefficients, the ratiometric adjustment also
reduces the overall temperature coefficient effect to 5 ppm/°C,
except at low value codes where RW dominates.
Potentiometer mode includes op amp feedback resistor networks
and other voltage scaling applications. Terminal A, Terminal W,
and Terminal B can in fact be input or output terminals, provided
that |VAB|, |VWA |, and |VWB| do not exceed VDD to GND.
ESD PROTECTION
Digital inputs SDA and SCL are protected with a series input
resistor and parallel Zener ESD structures (see Figure 36).
LOGIC
340Ω
03224-035
Figure 36. ESD Protection of Digital Pins
TERMINAL VOLTAGE OPERATING RANGE
There are also ESD protection diodes between VDD and the
RDAC terminals. The VDD of AD5273 therefore defines their
voltage boundary conditions (see Figure 37). Supply signals
present on Terminal A, Ter minal B, and Terminal W t hat excee d
VDD are clamped by the internal forward-biased diodes.
GND
A
W
B
V
DD
03224-036
Figure 37. Maximum Terminal Voltages Set by VDD
POWER-UP/POWER-DOWN SEQUENCES
Because of the ESD protection diodes, it is important to power
VDD first before applying any voltages to Terminal A, Terminal B,
and Terminal W. Otherwise, the diode is forward-biased such that
VDD is powered unintentionally and can affect the rest of the user’s
circuits. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and VA/VB/VW. The order of powering
VA, VB, VW, and digital inputs is not important as long as they are
powered after VDD. Similarly, VDD should be powered down last.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both OTP and normal opera-
ting voltage supplies are applied to the same VDD terminal of the
AD5273. The AD5273 employs fuse link technology that requires
from 5 V to 5.5 V for the 1 kΩ (DD8) and 10 kΩ (DD9) options,
or from 4.75 V to 5.25 V for the 50 kΩ (DYG) and 100 kΩ (DYH)
options, for blowing the internal fuses to achieve a given setting,
but normal VDD can be in the range of 2.7 V to 5.5 V after
completing the fuse programming process. As a result, dual
voltage supplies and isolation are needed if the system VDD is
outside the required VDD_OTP range. For successful OTP, the fuse
programming supply (either an on-board regulator or rack-mount
power supply) must be rated at 5 V to 5.5 V for the 1 kΩ (DD8)
and 10 kΩ (DD9) options, or at 4.75 V to 5.25 V for the 50 kΩ (DYG)
and 100 kΩ (DYH) options, and be capable of sourcing 100 mA
for 400 ms. When fuse programming is completed, the VDD_OTP
supply can be removed to allow normal operation of 2.7 V to 5.5 V;
the device then reduces the current consumption to the μA range.
When operating systems at 2.7 V, use of the bidirectional low
threshold P-Ch MOSFETs is recommended for the supply’s
isolation. As shown in Figure 38, this assumes that the 2.7 V
system voltage is applied first and that the P1 and P2 gates are
pulled to ground, thus turning on P1 first and then P2. As a
result, VDD of the AD5273 approaches 2.7 V. When the AD5273
setting is found, the factory tester applies the VDD_OTP to both
the VDD and the MOSFETs’ gates, thus turning off P1 and P2.
The OTP command should be executed at this time to program
the AD5273 while the 2.7 V source is protected. Once the fuse
programming is complete, the tester withdraws the VDD_OTP and
the AD5273’s setting is fixed permanently.
AD5273
V
DD
C2
0.1µF
A
PPLIES FOR OTP ONLY
C1
10mF
R1
10kΩ
2.7V
V
DD_OTP
P1 P2
P1 = P 2 = FDV302P, NDS 0610
03224-039
Figure 38. OTP Supply Isolated from the 2.7 V Normal Operating Supply
The AD5273 achieves the OTP function through blowing
internal fuses. Users should always apply the recommended
OTP programming voltage at the first fuse programming
attempt. Failure to comply with this requirement can lead to a
change in fuse structures, rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 × VDD and VDD. Refer to the Level Shift for
Different Voltages Operation section.
Poor PCB layout introduces parasitics that can affect fuse program-
ming. Therefore, it is recommended to add a 10 μF tantalum
capacitor in parallel with a 1 nF ceramic capacitor as close as
possible to the VDD pin. The type and value chosen for both capaci-
tors are important. This combination of capacitor values provides a
fast response and larger supply current handling with minimum
supply drop during transients. As a result, these capacitors increase
the OTP programming success by not inhibiting the proper energy
needed to blow the internal fuses. Additionally, C1 minimizes
transient disturbance and low frequency ripple, while C2 reduces
high frequency noise during normal operation.
AD5273
Rev. H | Page 16 of 24
CONTROLLING THE AD5273
To control the AD5273, users can program the device with
either computer software or with external I2C controllers.
SOFTWARE PROGRAMMING
Because of the OTP feature, users can program the AD5273 in
the factory before shipping it to end users. Therefore, Analog
Devices offers device programming software that can be imple-
mented in the factory on computers running Windows NT,
Windows 2000, and Windows XP platforms. The software,
which can be downloaded from the AD5273 product page at
www.analog.com, is an executable file that does not require any
programming languages or user programming skills. Figure 39
shows the software interface.
03224-040
Figure 39. Software Interface
Write
The AD5273 starts at midscale after power-up prior to any OTP
programming. To increment or decrement the resistance, move
the scrollbar on the left. Once the desired setting is found, click
Program Permanent to lock the setting permanently. To write
any specific values, use the bit pattern control in the upper
section and click Run. The format of writing data to the device
is shown in Figure 31. Once the desired setting is found, set the
T bit to 1 and click Run to program the setting permanently.
Read
To read the validation bits and data from the device, click Read.
The user can also set the bit pattern in the upper section and
click Run. The format of reading data from the device is shown
in Figure 32.
To control the device in both read and write operations, the
program generates the I2C digital signals through the parallel
port LPT1 Pin 2, Pin 3, Pin 15, and Pin 25 for SDA_write, SCL,
SDA_read, and DGND, respectively (see Figure 40).
To apply the device programming software in the factory, lay
out the AD5273 SCL and SDA pads on the PCB such that the
programming signals can be communicated to and from the
parallel port (see Figure 40). Figure 41 shows a recommended
AD5273 PCB layout into which pogo pins can be inserted for
factory programming. To prevent damaging the PC parallel
port, 100 Ω resistors should also be put in series to the SCL and
SDA pins. Pull-up resistors on SCL and SDA are also required.
03224-041
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
SCL
R3
100Ω
R1
100Ω
R2
100Ω
SDA
READ
WRITE
R4
10kΩR5
10kΩ
V
DD
Figure 40. Parallel Port Connection; Pin 2 = SDA_Write, Pin 3 = SCL,
Pin 15 = SDA_Read, and Pin 25 = DGND
W
V
DD
GND
SCL
B
AD0
SDA
03224-042
Figure 41. Recommended AD5273 PCB Layout
AD5273
Rev. H | Page 17 of 24
I2C CONTROLLER PROGRAMMING
Write Bit Patterns
ACK. BY
AD5273 ACK. BY
AD5273 ACK. BY
AD5273
SDA
FRAME 1
SLAVE ADDRESS BYTE
SCL
STOP BY
MASTER
S
TART B
Y
MASTER
0
0
1011
0AD0 R/W 0XXXXXXXXXD5
D4 D3 D2 D1 D0
80 80 8
FRAME 2
INSTRUCTION BYTE FRAME 1
DATA BYTE
03224-043
Figure 42. Writing to the RDAC Register
ACK. BY
AD5273 ACK. BY
AD5273 ACK. BY
AD5273
FRAME 1
SLAVE ADDRESS BYTE STOP BY
MASTER
S
TART B
Y
MASTER FRAME 2
INSTRUCTION BYTE FRAME 1
DATA BYTE
03224-044
SDA
SCL
0
0
1011
0AD0 R/W 1XXXXXXX XX D5D4D3D2D1D0
80808
Figure 43. Activating One-Time Programming
Read Bit Pattern
ACK. BY
AD5273 NO ACK. BY
AD5273
FRAME 1
SLAVE ADDRESS BYTE STOP BY
MASTER
S
TART B
Y
MASTER
FRAME 2
DATA BYTE FROM SELECTED
RDAC REGISTER
03224-059
SDA
SCL
01011
0AD0 R/W E1 E0 D5 D4 D3 D2 D1 D0
0808
Figure 44. Reading Data from the RDAC Register
For users who do not use the software solution, the AD5273 can
be controlled via an I2C-compatible serial bus and is connected
to this bus as a slave device. Referring to Figure 42, Figure 43,
and Figure 44, the 2-wire I2C serial bus protocol operates as
follows:
1. The master initiates data transfer by establishing a start
condition. A start condition is defined as a high-to-low
transition on the SDA line while SCL is high, as shown in
Figure 42. The byte following the start condition is the
slave address byte, which consists of six MSBs defined as
010110. The next bit is AD0; it is an I2C device address bit.
Depending on the states of the AD0 bits, two AD5273s can
be addressed on the same bus, as shown in Figure 45. The
last LSB is the R/W bit, which determines whether data is
read from or written to the slave device.
The slave address corresponding to the transmitted address
responds by pulling the SDA line low during the ninth
clock pulse (this is termed the acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register.
2. A write operation contains one more instruction byte than
the read operation. The instruction byte in the write mode
follows the slave address byte. The MSB of the instruction
byte labeled T is the OTP bit. After acknowledging the
instruction byte, the last byte in the write mode is the data
byte. Data is transmitted over the serial bus in sequences of
nine clock pulses (eight data bits followed by an acknowl-
edge bit). The transitions on the SDA line must occur during
the low period of SCL and remain stable during the high
period of SCL, as shown in Figure 42.
3. In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is trans-
mitted over the serial bus in sequences of nine clock pulses
(slight difference from write mode, there are eight data bits
followed by a no acknowledge bit). Similarly, the transitions
on the SDA line must occur during the low period of SCL
and remain stable during the high period of SCL, as shown
in Figure 44.
AD5273
Rev. H | Page 18 of 24
4. When all data bits have been read or written, a stop con-
dition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line
while SCL is high. In write mode, the master pulls the
SDA line high during the 10th clock pulse to establish a
stop condition, as shown in Figure 42 and Figure 43. In
read mode, the master issues a no acknowledge for the
ninth clock pulse, that is, the SDA line remains high. The
master then brings the SDA line low before the 10th clock
pulse, which goes high to establish a stop condition, as
shown in Figure 44.
A repeated write function gives the user flexibility to
update the RDAC output continuously, except after
permanent programming, when the part is addressed and
receives instructions only once. During the write cycle,
each data byte updates the RDAC output. For example,
after the RDAC has acknowledged its slave address and
instruction bytes, the RDAC output updates after these two
bytes. If another byte is written to the RDAC while it is still
addressed to a specific slave device with the same instruc-
tion, this byte updates the output of the selected slave device.
If different instructions are needed, the write mode must
be started again with a new slave address, instruction, and
data bytes. Similarly, a repeated read function of the RDAC
is also allowed.
CONTROLLING TWO DEVICES ON ONE BUS
Figure 45 shows two AD5273 devices on the same serial bus.
Each has a different slave address because the state of each AD0
pin is different. This allows each device to operate independently.
The master device output bus line drivers are open-drain pull-
down in a fully I2C-compatible interface.
MASTER
SDA SCL
AD0
AD5273
SDA SCL
AD0
AD5273
SDA
SCL
5
V
R
P
R
P
5V
03224-045
Figure 45. Two AD5273 Devices on One Bus
AD5273
Rev. H | Page 19 of 24
APPLICATIONS INFORMATION
DAC
It is common to buffer the output of the digital potentiometer as
a DAC. The buffer minimizes the load dependence and delivers
higher current to the load, if needed.
GND
VIN VOUT
1U1
5V
2
3
VO
AD8601
5V
AW
B
ADR03
U3
AD5273
U2
03224-046
Figure 46. Programmable Voltage Reference (DAC)
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
For applications that require high current adjustment, such as a
laser diode driver or tunable laser, consider a booster voltage
source, as shown in Figure 47.
+V
WSIGNAL
C
C
R
BIAS
LD
V
IN
A
B
V
OUT
U1
AD5273
U3 2N7002
AD8601
U2
–V
I
L
03224-047
Figure 47. Programmable Booster Voltage Source
In this circuit, the inverting input of the op amp forces the
VOUT to be equal to the wiper voltage set by the digital potenti-
ometer. The load current is then delivered by the supply via the
N-Channel FET, N1. N1 power handling must be adequate to
dissipate (VIN − VOUT) × IL power. This circuit can source a max-
imum of 100 mA with a 5 V supply. For precision applications,
a voltage reference, such as the ADR421, ADR03, or ADR370,
can be applied at Terminal A of the digital potentiometer.
PROGRAMMABLE CURRENT SOURCE
A programmable current source can be implemented with the
circuit shown in Figure 48. The load current is the voltage across
Terminal B to Terminal W of the AD5273 divided by RS. At zero
scale, Terminal A of the AD5273 is −2.048 V, which makes the
wiper voltage clamped at ground potential. Depending on the
load, Equation 5 is therefore valid only at certain codes. For
example, when the compliance voltage, VL, equals half of VREF,
the current can be programmed from midscale to full scale of
the AD5273.
I
L
GND
V
S
2U1
5
V
4
6
3SLEEP
0V TO ...
OUPUT
REF191
C1 1µF
B
A
W
R
S
102Ω
100Ω
R
L
V
L
–2.048 + V
L
–5V
OP1177
+5V
V+
V–
U2
U3
AD5273
03224-048
Figure 48. Programmable Current Source
(
)
6332|
64/ ≤≤
×
=D
R
DV
I
S
REF
L (5)
GAIN CONTROL COMPENSATION
As shown in Figure 49, the digital potentiometers are
commonly used in gain controls or sensor transimpedance
amplifier signal conditioning applications.
U1
C2
4.7pF
A
B
W
V
O
V
I
C1
R1
47kΩ
R2
100kΩ
03224-049
Figure 49. Typical Noninverting Gain Amplifier
In both applications, one of the digital potentiometer terminals
is connected to the op amp inverting node with finite terminal
capacitance, C1. It introduces a zero for the 1 βo term with
20 dB/dec, whereas a typical op amp GBP has −20 dB/dec
characteristics. A large R2 and finite C1 can cause this zero’s
frequency to fall well below the crossover frequency. Therefore,
the rate of closure becomes 40 dB/dec and the system has a 0°
phase margin at the crossover frequency. The output may ring,
or in the worst case, oscillate when the input is a step function.
Similarly, it is also likely to ring when switching between two
gain values because this is equivalent to a step change at the
input. To reduce the effect of C1, users should also configure
Terminal B or Terminal A rather than Terminal W at the
inverting node.
AD5273
Rev. H | Page 20 of 24
Depending on the op amp GBP, reducing the feedback resistor
may extend the zero’s frequency far enough to overcome the
problem. A better approach is to include a compensation
capacitor, C2, to cancel the effect caused by C1. Optimum
compensation occurs when R1 × C1 = R2 × C2, but this is not
an option because of the variation of R2. As a result, users can
use the relationship described and scale C2 as if R2 were at its
maximum value. However, doing so may overcompensate by
slowing down the settling time when R2 is set to low values. To
avoid this problem, C2 should be found empirically for a given
application. In general, setting C2 in the range of a few picofarads
to no more than a few tenths of a picofarad is usually adequate
for compensation.
There is also a Terminal W capacitance connected to the output
(not shown); its effect on stability is less significant; therefore,
compensation is not necessary unless the op amp is driving a
large capacitive load.
PROGRAMMABLE LOW-PASS FILTER
In ADC applications, it is common to include an antialiasing
filter to band-limit the sampling signal. To minimize various
system redesigns, users can use two 1 kΩ AD5273s to construct
a generic second-order Sallen-Key low-pass filter. Because the
AD5273 is a single-supply device, the input must be dc offset
when an ac signal is applied to avoid clipping at ground. This is
illustrated in Figure 50. The design equations are
2
2
2
O
O
O
I
O
S
Q
S
V
V
ω+
ω
+
ω
= (6)
1R2C1C2R
O
1
=ω (7)
R2C2R1C1
Q11 += (8)
Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth where Q = 0.707, let C1 be
twice the size of C2 and let R1 = R2. As a result, R1 and R2 can
be adjusted to the same setting to achieve the desired bandwidth.
VO
AD8601
+2.5V
U1 –2.5V
V+
V–
C1
C
R1 R2
AB
W
AB
WC2 C
ADJUSTED TO
SAME SETTINGS
VI
03224-050
Figure 50. Sallen Key Low-Pass Filter
LEVEL SHIFT FOR DIFFERENT VOLTAGES
OPERATION
If the SCL and SDA signals come from a low voltage logic
controller and are below the minimum VIH level (0.7 × VDD),
level-shift the signals for successful read/write communication
between the AD5273 and the controller. Figure 51 shows one of
the implementations. For example, when SDA1 is 2.5 V, M1
turns off, and SDA2 becomes 5 V. When SDA1 is 0 V, M1 turns
on, and SDA2 approaches 0 V. As a result, proper level-shifting
is established. M1 and M2 should be low threshold N-Channel
power MOSFETs, such as FDV301N.
2.5V
CONTROLLER 2.7V–5.5V
AD5273
Rp Rp Rp Rp
V
DD1
= 2. 5V
V
DD2
= 5
V
G
G
SD
M1 SD
M2
S
DA1
S
CL1
SDA2
SCL2
03224-051
Figure 51. Level Shift for Different Voltages Operation
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the digital potentio-
meters. Configured as a potentiometer divider, the −3 dB
bandwidth of the AD5273 (1 kΩ resistor) measures 6 MHz at
half scale. Figure 17 to Figure 20 provide the large signal BODE
plot characteristics of the four available resistor versions: 1 kΩ,
10 kΩ, 50 kΩ, and 100 kΩ. Figure 52 shows a parasitic simula-
tion model. The code following Figure 52 provides a macro
model net list for the 1 kΩ device.
55pF
C
A
2
5pF C
B
25pF
AB
1kΩ
W
C
W
03224-055
Figure 52. Circuit Simulation Model for RDAC = 1 kΩ
Macro Model Net List for RDAC
.PARAM D = 63, RDAC = 1E3
*
.SUBCKT DPOT (A,W,B)
*
CA A 0 25E-12
RWA A W {(1-D/63)*RDAC+60}
CW W 0 55E-12
RWB W B {D/63*RDAC+60}
CB B 0 25E-12
*
.ENDS DPOT
AD5273
Rev. H | Page 21 of 24
EVALUATION BOARD
W
V
DD
GND
SCL
SCL
SDA
A
8
7
1
2
3
4
8
7
6
5
6
5
4
3
2
1
B
AD0
C1
10mF
C9
10µF
C4
0.1µF
C8
0.1µF
C2
0.1µF C3
0.1µF
C5
0.1µF
R1
10kΩ
R2
10kΩ
SDA
TEMP
GND
V
IN
TRIM
V
OUT
V
REF
V
DD
V
CC
V
EE
AGND
JP2
JP1
OUT1
JP8
A
WV
IN
B
W
V
DD
GND
SCL
A
B
AD0
SDA
C7
10µF
C6
0.1µF
V
DD
V
DD
J1
U1
U4
AD5170
ADR03
AD5171/AD5273
1
2
3
4
67
5
281
4
3
8
7
6
5
1
2
3
5
4
U2
U3A
U3B
CP3
CP5
CP1
CP4
CP2
JP7
+IN1
V+
+IN2 OUT2
OUT1
–IN1
–IN1
–IN2
V–
JP4
JP6
JP5
JP3
CP6
CP7
03224-056
Figure 53. Evaluation Board Schematic
V
REF
V
REF
V
O
OUT1
AD822
A2
3
B
11
1
JP4
WA
B
U2 W
V+
V–
JP2
JP1 JP7
V
DD
CP2
JP3
U3A
4
03224-057
Figure 54. One Possible Configuration—
Programmable Voltage Reference
03224-058
Figure 55. Evaluation Board
AD5273
Rev. H | Page 22 of 24
OUTLINE DIMENSIONS
COMP LI ANT TO JEDE C STANDARDS MO-178- BA
121608-A
8°
4°
0°
SEATING
PLANE
1.95
BSC
0.65 BSC
0.60
BSC
76
1234
5
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0
.15 MAX
0
.05 MIN
1.45 MAX
0.95 MIN
0.22 MAX
0.08 MIN
0.38 MAX
0.22 MIN
0.60
0.45
0.30
PIN 1
INDICATOR
8
Figure 56. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2RAB (kΩ) Temperature Range Package Option Package Description Ordering Quantity Branding
AD5273BRJZ1-R2 1 −40°C to +105°C RJ-8 8-Lead SOT-23 250 DD8
AD5273BRJZ1-REEL7 1 −40°C to +105°C RJ-8 8-Lead SOT-23 3,000 DD8
AD5273BRJZ10-R2 10 −40°C to +105°C RJ-8 8-Lead SOT-23 250 DD9
AD5273BRJZ10-R7 10 −40°C to +105°C RJ-8 8-Lead SOT-23 3,000 DD9
AD5273BRJZ50-REEL7 50 −40°C to +105°C RJ-8 8-Lead SOT-23 3,000 DYG
AD5273BRJZ100-R2 100 −40°C to +105°C RJ-8 8-Lead SOT-23 250 DYH
AD5273BRJZ100-R7 100 −40°C to +105°C RJ-8 8-Lead SOT-23 3,000 DYH
AD5273EVAL Evaluation Board
1 Z = RoHS Compliant Part.
2 For the evaluation board, users should order samples because the evaluation kit comes with a socket, but does not include the parts.
AD5273
Rev. H | Page 23 of 24
NOTES
AD5273
Rev. H | Page 24 of 24
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03224-0-10/10(H)