LTC4355
1
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FEATURES
APPLICATIONS
DESCRIPTION
Positive High Voltage
Ideal Diode-OR with Input Supply
and Fuse Monitors
The LTC
®
4355 is a positive voltage ideal diode-OR control-
ler that drives two external N-channel MOSFETs. Forming
the diode-OR with N-channel MOSFETs instead of Schottky
diodes reduces power consumption, heat dissipation and
PC board area.
With the LTC4355, power sources can easily be ORed
together to increase total system reliability. The LTC4355
can diode-OR two positive supplies or the return paths of
two negative supplies, such as in a –48V system.
In the forward direction the LTC4355 controls the volt-
age drop across the MOSFET to ensure smooth current
transfer from one path to the other without oscillation. If
a power source fails or is shorted, fast turnoff minimizes
reverse current transients.
Power fault detection indicates if the input supplies are
not in regulation, the inline fuses are blown, or the volt-
ages across the MOSFETs are greater than the fault
threshold.
+48V Diode-OR
n Replaces Power Schottky Diodes
n Controls N-Channel MOSFETs
n 0.3μs Turn-Off Time Limits Peak Fault Current
n Wide Operating Voltage Range: 9V to 80V
n Smooth Switchover without Oscillation
n No Reverse DC Current
n Monitors VIN, Fuse, and MOSFET Diode
n Available in 14-Lead (4mm × 3mm) DFN,
16-Lead MS and SO Packages
n High Availability Systems
n AdvancedTCA
®
(ATCA) Systems
n +48V and –48V Distributed Power Systems
n Telecom Infrastructure
Power Dissipation vs Load Current
TYPICAL APPLICATION
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
4355 TA01
LTC4355
GND
GATE1 GATE2IN1 OUTIN2
MON1
MON2
SET
12.7k
340k
12.7k
340k
7A
22k 22k 22k
22k 22k
GREEN LEDs
PANASONIC LN1351C
7A
GND
FDB3632
FDB3632
TO
LOAD
VIN1 = +48V
VIN2 = +48V
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
CURRENT (A)
0
0
POWER DISSIPATION (W)
1
2
3
4
5
6
2468
4355 TA02
10
DIODE (MBR10100)
FET (FDB3632)
POWER
SAVED
LTC4355
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ABSOLUTE MAXIMUM RATINGS
Supply Voltages
IN1, IN2 ..................................................–1V to 100V
OUT ..................................................... –0.3V to 100V
Input Voltages
MON1, MON2, SET .................................. –0.3V to 7V
Output Voltages
GATE1 (Note 3) ................... VIN1 – 0.2V to VIN1 + 13V
GATE2 (Note 3) ................... VIN2 – 0.2V to VIN2 + 13V
PWRFLT1, PWRFLT2, VDSFLT,
FUSEFLT1, FUSEFLT2 ............................... –0.3V to 8V
(Notes 1, 2)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
15
MON1
PWRFLT1
FUSEFLT1
FUSEFLT2
PWRFLT2
MON2
SET
IN1
GATE1
OUT
GATE2
IN2
VDSFLT
GND
TOP VIEW
DE14 PACKAGE
14-LEAD
(
4mm s 3mm
)
PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 15) PCB GND CONNECTION OPTIONAL
1
2
3
4
5
6
7
8
IN1
GATE1
NC
OUT
NC
GATE2
IN2
VDSFLT
16
15
14
13
12
11
10
9
MON1
PWRFLT1
FUSEFLT1
FUSEFLT2
PWRFLT2
MON2
SET
GND
TOP VIEW
MS PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 125°C/W
MON1
PWRFLT1
FUSEFLT1
FUSEFLT2
PWRFLT2
MON2
SET
GND
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
GATE1
NC
OUT
NC
GATE2
IN2
NC
TJMAX = 125°C, θJA = 75°C/W
Operating Temperature Range
LTC4355C ................................................ 0°C to 70°C
LTC4355I..............................................–40°C to 85°C
Storage Temperature Range ...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS, SO Packages ............................................. 300°C
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4355CDE#PBF LTC4355CDE#TRPBF 4355 14-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC4355IDE#PBF LTC4355IDE#TRPBF 4355 14-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
LTC4355CS#PBF LTC4355CS#TRPBF LTC4355CS 16-Lead Plastic SO 0°C to 70°C
LTC4355IS#PBF LTC4355IS#TRPBF LTC4355IS 16-Lead Plastic SO –40°C to 85°C
LTC4355CMS#PBF LTC4355CMS#TRPBF 4355 16-Lead Plastic MSOP 0°C to 70°C
LTC4355IMS#PBF LTC4355IMS#TRPBF 4355 16-Lead Plastic MSOP –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *Temperature grades are identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
PIN CONFIGURATION
ORDER INFORMATION
LTC4355
3
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOUT Operating Supply Range l980V
IOUT Supply Current l23 mA
IINx INx Pin Input Current GATE High l0.5 0.6 1.2 mA
ΔVGATEx External N-Channel Gate Drive
(VGATEx – VINx)
VOUT = 20V to 80V
VOUT = 9V to 20V
l
l
10
4.5
14
6
18
18
V
V
IGATEx(UP) External N-Channel Gate Pull-Up Current VGATEx = VINx,
VINx – VOUT = 100mV
l–14 –20 –26 μA
IGATEx(DN) External N-Channel Gate Pull-Down in Fault
Condition
Gate Drive Off, VGATEx = VINx +5V l12 A
tOFF Gate Turn-Off Time VINx – VOUT = 55mV –|
––1V, CGATE = 0
VGATEx – VINx < 1V
l0.3 0.4 μs
VMONx(TH) MONx Pin Threshold Voltage VMONx Rising l1.209 1.227 1.245 V
VMONx(HYST) MONx Pin Hysteresis Voltage l10 30 45 mV
IMONx(IN) MONx Pin Input Current VMONx = 1.23V l0±1 μA
VINx(TH) INx Pin Threshold Voltage VINx Rising l3 3.5 4 V
VINx(HYST) INx Pin Hysteresis Voltage l25 75 150 mV
ΔVSD Source-Drain Regulation Voltage
(VINx – VOUT )
VGATEx – VINx = 2.5V l10 25 55 mV
ΔVSD(FLT) Short-Circuit Fault Voltage
(VINx – VOUT) Rising
SET = 0V
SET = 100kΩ
SET = Hi-Z
l
l
l
0.2
0.4
1.3
0.25
0.5
1.5
0.3
0.6
1.6
V
V
V
ΔVSD(FLT)(HYST) Short-Circuit Fault Hysteresis Voltage 30 mV
VFLT PWRFLTx, FUSEFLTx, VDSFLT Pins
Output Low
IPWRFLTx, IFUSEFLTx, IVDSFLT = 5mA l100 200 mV
IFLT PWRFLTx, FUSEFLTx, VDSFLT Pins
Leakage Current
VPWRFLTx, VFUSEFLTx, VVDSFLT = 5V l0±1 μA
RSET(L) SET Resistance Range for ΔVSD(FLT) = 0.25V l05
kΩ
RSET(M) SET Resistance Range for ΔVSD(FLT) = 0.5V l50 150 kΩ
RSET(H) SET Resistance Range for ΔVSD(FLT) = 1.5V l1MΩ
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. 9V < VOUT < 80V, unless otherwise noted.
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specifi ed.
Note 3: The GATEx pins are internally limited to a minimum of 13V above
INx. Driving these pins beyond the clamp may damage the part.
LTC4355
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TYPICAL PERFORMANCE CHARACTERISTICS
IOUT vs VOUT IIN vs VIN IGATE vs ΔVSD
ΔVGATE vs IGATE
Fault Output Low
vs Load Current
Fault Output Low
vs Temperature
FET Turn-Off Time
vs GATE Capacitance
FET Turn-Off Time
vs Initial Overdrive
FET Turn-Off Time
vs Final Overdrive
VOUT (V)
0
IOUT (mA)
1.0
1.5
80
0.5
020 40 60
2.0
4355 G01
VOUT = VIN
VIN (V)
0
IIN (mA)
0.5
0.75
80
0.25
020 40 60
1.0
4355 G02
VIN = VOUT
VSD (mV)
–50
IGATE (μA)
–20
0
150
–40
–60 050 100
20
4355 G03
VGATE = 2.5V
IGATE (μA)
0
0
$VGATE (V)
5
10
15
5101520
25
4355 G04
VIN > 18V
VIN = 12V
VIN = 9V
IFLT (mA)
0
VFLT (V)
0.1
0.2
15
0510
0.3
4355 G05
TEMPERATURE (°C)
–50
VFLT (V)
100
125
100
50 050
150
75
4355 G06
IFLT = 5mA
CGATE (nF)
0
tOFF (ns)
300
400
500
40
4355 G07
200
100
010 20 20 50
VGATE < VIN + 1V
$VSD = 50mV –1V
VINITIAL (V)
0
tPD (ns)
300
400
500
0.8
4355 G08
200
100
00.2 0.4 0.6 1.0
VIN = 48V
$VSD = VINITIAL –1V
VFINAL (V)
–1.0
tPD (ns)
1000
1500
2000
–0.2
4355 G09
500
0–0.8 –0.6 –0.4 0
VIN = 48V
$VSD = 50mV VFINAL
LTC4355
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PIN FUNCTIONS
Exposed Pad: Exposed pad may be left open or connected
to GND.
FUSEFLTx: Fuse Fault Outputs. Open-drain output that
pulls to GND when VINx < 3.5V, indicating that the fuse
has blown open. Otherwise, this output is high impedance.
Connect to GND if unused.
GATEx: Gate Drive Outputs. The GATE pins pull high,
enhancing the N-channel MOSFET when the load cur-
rent creates more than 25mV of voltage drop across
the MOSFET. When the load current is small, the
gates are actively driven to maintain 25mV across the
MOSFET. If the reverse current develops more than
–25mV of voltage drop across a MOSFET, a fast pull-down
circuit quickly connects the GATE pin to the IN pin, turning
off the MOSFET. Limit the capacitance between the GATE
and IN pins to less than 0.1μF.
GND: Device Ground.
INx: Input Voltages and GATE Fast Pull-Down Returns. The
IN pins are the anodes of the ideal diodes and connect to the
sources of the N-channel MOSFETs. The voltages sensed
at these pins are used to control the source-drain voltages
across the MOSFETs and are used by the fault detection
circuits that drive the PWRFLT, FUSEFLT, and VDSFLT pins.
The GATE fast pull-down current is returned through the IN
pins. Connect these pins as close to the MOSFET sources
as possible. Connect to OUT if unused.
MONx: Input Supply Monitors. These pins are used to
sense the input supply voltages. Connect these pins to
external resistive dividers between the input supplies and
GND. If VMONx falls below 1.23V, the PWRFLTx pin pulls
to GND. Connect to GND if unused.
NC: No Connection. Not internally connected. These
pins provide extra distance between high and low volt-
age pins.
OUT: Drain Voltage Sense and Positive Supply Input. OUT
is the diode-OR output of IN1 and IN2. It connects to the
common drain connection of the N-channel MOSFETs. The
voltage sensed at this pin is used to control the source-
drain voltages across the MOSFETs and is used by the
fault detection circuits that drive the PWRFLT and VDSFLT
pins. The LTC4355 is powered from the OUT pin.
PWRFLTx: Power Fault Outputs. Open-drain output
that pulls to GND when VMONx falls below 1.23V or
the forward voltage across the MOSFET exceeds
ΔVSD(FLT). When VMONx is above 1.23V and the
forward voltage across the MOSFET is less than
ΔVSD(FLT), PWRFLTx is high impedance. Connect to GND
if unused.
SET: ΔVSD(FLT) Threshold Confi guration Input. Tying SET
to GND, to a 100k resistor connected to GND, or leaving
SET open confi gures the ΔVSD(FLT) forward voltage fault
t h r e s h o l d t o 2 5 0 m V, 5 0 0 mV, o r 1. 5 V, r e s p e c t i v e l y. W h e n t h e
voltage across a MOSFET exceeds ΔVSD(FLT), the VSDFLT
pin and at least one of the PWRFLT pins pull to GND.
VDSFLT: MOSFET Fault Output. Open-drain output that
pulls to GND when the forward voltage across either
MOSFET exceeds ΔVSD(FLT). PWRFLT1 or PWRFLT2 also
pulls low to indicate which MOSFET’s forward voltage drop
exceeds ΔVSD(FLT). Otherwise, this pin is high impedance.
Connect to GND if unused.
LTC4355
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BLOCK DIAGRAM
–
+
4355 BD
–
+
–
+
–
+
+
–
+
–
+
–
+
–
–
+
–
+
–
+
–
+
+
–
+
–
+
–
+
–
GATE1
AMP
GATE2
AMP
3.5V 3.5V
FUSE1
FAULT
$VSD(FLT)
$VSD1(FLT)
FAULT
$VSD2(FLT)
FAULT
25mV 25mV
$VSD(FLT)
$VSD(FLT) =
0.25V, 0.5V OR 1.5V
GATE1 GATE2OUTIN1 IN2
VDSFLT
FUSEFLT1 FUSEFLT2
PWRFLT2
GND
1.23V 1.23V
SET
MON1
MON1
MON2
MON2
PWRFLT1
FUSE2
FAULT
17V 17V
LTC4355
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OPERATION
High availability systems often employ parallel-connected
power supplies or battery feeds to achieve redundancy
and enhance system reliability. ORing diodes have been
a popular means of connecting these supplies at the
point of load. The disadvantage of this approach is the
forward voltage drop and resulting effi ciency loss. This
drop reduces the available supply voltage and dissipates
signifi cant power. Using N-channel MOSFETs to replace
Schottky diodes reduces the power dissipation and
eliminates the need for costly heat sinks or large thermal
layouts in high power applications.
The LTC4355 is a positive voltage diode-OR controller
that drives two external N-channel MOSFETs as pass
transistors to replace ORing diodes. The IN and OUT
pins form the anodes and cathodes of the ideal diodes.
The source pins of the external MOSFETs are connected
to the IN pins. The drains of the MOSFETs are connected
together at the OUT pin, which is the positive supply of
the device. The gates of the external MOSFETs are driven
by the LTC4355 to regulate the voltage drop across the
pass transistors.
At power-up, the initial load current fl ows through the
body diode of the MOSFET with the higher INx voltage.
The associated GATEx pin immediately ramps up and
turns on the MOSFET. The amplifi er tries to regulate the
voltage drop across the source and drain connections to
25mV. If the load current causes more than 25mV of drop,
the MOSFET gate is driven fully on and the voltage drop
is equal to RDS(ON) • ILOAD.
When the power supply voltages are nearly equal, this
regulation technique ensures that the load current is
smoothly shared between the MOSFETs without oscil-
lation. The current fl owing through each pass trans-
istor depends on the RDS(ON) of each MOSFET and the
output impedances of the supplies.
In the event of a supply failure, such as if the supply that
is conducting most or all of the current is shorted to GND,
reverse current fl ows temporarily through the MOSFET that
is on. This current is sourced from any load capacitance
and from the second supply through the body diode of
the other MOSFET. The LTC4355 quickly responds to this
condition, turning off the MOSFET in about 500ns. This
fast turn-off prevents the reverse current from ramping
up to a damaging level.
In the case where the forward voltage drop exceeds the
confi gurable fault threshold, ΔVSD(FLT), the VDSFLT pin
pulls low. Using this pin to shunt current away from an
LED or opto-coupler provides an indication that a pass
transistor has either failed or has excessive forward current.
Additionally, in this condition the PWRFLT1 or PWRFLT2
pin pulls low to identify the faulting channel.
The PWRFLT pins also indicate if an input supply is within
regulation. When VMON1 < 1.23V or VMON2 < 1.23V, the
corresponding PWRFLT pin pulls low to indicate that the
input supply is low, turning off an optional LED or opto-
coupler.
The FUSEFLT pins indicate the status of input fuses. If
the voltage at one of the IN pins is less than 3.5V, the
corresponding FUSEFLT pin pulls low. The IN pins sink
a minimum of 0.5mA to guarantee that the IN pin will
pull low when the input fuse is blown open. Note that the
FUSEFLT pin will activate if the input supply is less than
3.5V even if the fuse is intact.
LTC4355
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APPLICATIONS INFORMATION
MOSFET Selection
The LTC4355 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
on-resistance RDS(ON), the maximum drain-source voltage
VDSS, and the threshold voltage.
The gate drive for the MOSFET is guaranteed to be greater
than 4.5V when the supply voltage at VOUT is between
9V and 20V. When the supply voltage at VOUT is greater
than 20V, the gate drive is guaranteed to be greater than
10V. The gate drive is limited to less than 18V. This allows
the use of logic level threshold N-channel MOSFETs and
standard N-channel MOSFETs above 20V. An external
Zener diode can be used to clamp the potential from the
MOSFET’s gate to source if the rated breakdown voltage
is less than 18V. See the Typical Applications section for
an example.
The maximum allowable drain-source voltage, BVDSS,
must be higher than the supply voltages. If an input is
connected to GND, the full supply voltage will appear
across the MOSFET.
If the voltage drop across either MOSFET exceeds the con-
fi g u r a b l e ΔVSD(FLT) fault threshold, the VDSFLT pin and the
PWRFLT pin corresponding to the faulting channel pull low.
The RDS(ON) should be small enough to conduct the maximum
load current while not triggering a fault, and to stay within
the MOSFET’s power rating at the maximum load current
(I2 • RDS(ON)).
Fault Conditions
The LTC4355 monitors fault conditions and shunts current
away from LEDs or opto-couplers, turning each one off to
indicate a specifi c fault condition (see Table 1).
When the voltage drop across the pass transistor is
higher than the confi gurable ΔVSD(FLT) fault threshold, the
internal pull-down at the VDSFLT pin and the PWRFLT1 or
PWRFLT2 pin corresponding to the faulting channel turns
on. The ΔVSD(FLT) threshold is confi gured by the SET pin.
Tying SET to GND, tying SET to a 100k resistor connected
to GND, or fl oating SET confi gures ΔVSD(FLT) to 250mV,
500mV, or 1.5V respectively.
Table 1. Fault Table
ΔVSD1
< ΔVSD(FLT)
VIN1
> 3.5V
VMON1
> 1.23V VDSFLT*FUSEFLT1 PWRFLT1
True True True Hi-Z Hi-Z Hi-Z
True True False Hi-Z Hi-Z Pull-Down
True False True Hi-Z Pull-Down Hi-Z
True False False Hi-Z Pull-Down Pull-Down
False True True Pull-Down Hi-Z Pull-Down
False True False Pull-Down Hi-Z Pull-Down
False False True Pull-Down Pull-Down Pull-Down
False False False Pull-Down Pull-Down Pull-Down
*ΔVSD2 < ΔVSD(FLT)
Fault conditions that may cause a high voltage across the
pass transistor include: a MOSFET open on the higher
supply, excessive MOSFET current due to overcurrent
on the load or a shorted MOSFET on the lower supply.
During startup or when a switchover between supplies
occurs, the VDSFLT pin and PWRFLT1 or PWRFLT2 pin
may momentarily indicate that the forward voltage has
exceeded the programmed threshold during the short
interval when the MOSFET gate ramps up and the body
diode conducts.
The PWRFLT pins are additionally used to indicate if either
input supply is below its normal regulation range. If the
voltage at the MON1 or MON2 pin is less than VMON(TH),
typically 1.23V, the corresponding PWRFLT1 or PWRFLT2
pin will pull low. A resistive divider connected to the input
supply drives the MON pin for the corresponding supply,
confi guring the PWRFLT threshold for that supply. Be sure
to account for the tolerance of the MON pin threshold,
the resistor tolerances, and the regulation range of the
supply being monitored. Also, ensure that the voltage on
the MON pin will not exceed 7V.
The FUSEFLT pins are used to indicate the status of the
input fuses. If one of the IN pins falls below VINx(TH), typi-
cally 3.5V, the FUSEFLT pin corresponding to that supply
will pull low. The IN pins each sink a minimum of 0.5mA,
enough to pull the pin low after an input fuse blows open.
If there is a possibility that the MOSFET leakage current
can be greater than 0.5mA, a resistor can be connected
between the IN pin and GND to sink more current. Note
that if the input supply voltage is less than VINx(TH) the
FUSEFLT pin will pull low.
LTC4355
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APPLICATIONS INFORMATION
System Power Supply Failure
The LTC4355 automatically supplies load current from the
system input supply with the higher voltage. If this supply
shorts to ground, reverse current begins to fl ow through
the pass transistor temporarily and the transistor begins
to turn off. When this reverse current creates –25mV of
voltage drop across the drain and source pins of the pass
transistor, a fast pull-down circuit engages to drive the
gate low faster.
The remaining system power supply delivers the load cur-
rent through the body diode of its pass transistor until the
channel turns on. The LTC4355 ramps the gate up with
20μA, turning on the N-channel MOSFET to reduce the
voltage drop across it.
Input Short-Circuit Faults
The dynamic behavior of an active, ideal diode entering
reverse bias is most accurately characterized by a delay
followed by a period of reverse recovery. During the delay
phase some reverse current is built up, limited by para-
sitic resistances and inductances. During the reverse re-
covery phase, energy stored in the parasitic inductances
is transferred to other elements in the circuit. Current
slew rates during reverse recovery may reach 100A/μs
or higher.
High slew rates coupled with parasitic inductances in se-
ries with the input and output paths may cause potentially
destructive transients to appear at the IN and OUT pins of
the LTC4355 during reverse recovery. A zero impedance
short-circuit directly across an input that is supplying
current is especially troublesome because it permits the
highest possible reverse current to build up during the
delay phase. When the MOSFET fi nally commutates the
reverse current the LTC4355 IN pin experiences a nega-
tive voltage spike, while the OUT pin spikes in the positive
direction.
To prevent damage to the LTC4355 under conditions of
input short-circuit, protect the IN pins and OUT pin as
shown in Figure 1. The IN pins are protected by clamping
to the GND pin in the negative direction. Protect the OUT
pin with a clamp, such as with a TVS or TransZorb, or with
a local bypass capacitor of at least 10μF. In low voltage
applications the MOSFET’s drain-source breakdown may
be suffi cient to protect the OUT pin, provided BVDSS +
VIN < 100V.
Parasitic inductance between the load bypass or the
second supply and the LTC4355 allows a zero impedance
input short to collapse the voltage at the OUT pin, which
increases the total turn-off time (tOFF). For applications
up to 30V, bypass the OUT pin with 39μF; above 30V use
at least 100μF. One capacitor serves to guard against OUT
collapse and also protect OUT from voltage spikes.
Figure 1. Reverse Recovery Produces Inductive Spikes at the IN and OUT Pins.
The Polarity of Step Recovery Spikes Is Shown Across Parasitic Inductances
LTC4355
GND
GATE1 GATE2IN1 OUTIN2
M1
FDS3672
REVERSE
RECOVERY
CURRENT
M2
FDS3672
VIN1 VOUT
VIN2 DIN2
SBR1U150SA
INPUT PARASITIC
INDUCTANCE
+ –
OUTPUT PARASITIC
INDUCTANCE
+ –
INPUT PARASITIC
INDUCTANCE
– +
COUT
10μF CLOAD
DCLAMP
SMAT70A
OR
REVERSE RECOVERY CURRENT
4355 F01
DIN1
SBR1U150SA
INPUT
SHORT
LTC4355
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APPLICATIONS INFORMATION
Loop Stability
The servo loop is compensated by the parasitic capaci-
tance of the power N-channel MOSFET. No further
compensation components are normally required. In
the case when a MOSFET with less than 1000pF gate
capacitance is chosen, a 1000pF compensation capacitor
connected across the gate and source pins might be
required.
Design Example
The following design example demonstrates the calculations
involved for selecting components in a 36V to 72V system
with 5A maximum load current (see Figure 2).
First, choose the N-channel MOSFET. The 100V, FDS3672
in the SO-8 package with RDS(ON) = 22mΩ(max) offers a
good solution. The maximum voltage drop across it is:
ΔV = 5A • 22mΩ = 110mV
The maximum power dissipation in the MOSFET is a mere:
P = 5A • 110mV = 0.55W
Next, select the resistive dividers that guarantee the
PWRFLT pins will not assert when the input supplies are
above 36V. The maximum VMONx(TH) is 1.245V and the
maximum IMONx(IN) is 1μA. Choose a 1% tolerance resistor
R1 = 12.7k. Then,
IR2 =VMONx(TH)
R1(MIN) +IMONx(TH)(MAX)
=1.245V
12.7kΩ(−1%) +1μA=100μA
Use IR2 to choose R2.
R2 =36V −1.245V
100μA=348kΩ
A dju st R2 do wn by 1% to 3 44 k t o ac co un t fo r i t s to ler an ce.
The next lower standard resistor value is R2 = 340k.
The LED D1, a Panasonic Green LN1351C, requires at least
1mA of current to fully turn on. Therefore, R5 is set to 33k
to accommodate the lowest input supply voltage of 36V.
4355 F02
LTC4355
GND
GATE1 GATE2IN1 OUTIN2
MON1
MON2
SET
R1
12.7k
R2
340k
R3
12.7k
R4
340k
R5
33k
R7
33k
R9
33k
R6
33k
R8
33k
D1 D3
D2 D4
D5
GND
M1
FDS3672
M2
FDS3672
TO
LOAD
VIN1 = +48V
VIN2 = +48V
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
F1
7A
F2
7A
GREEN LEDs
PANASONIC LN1351C
Figure 2. 36V to 72V/5A Design Example
LTC4355
11
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Figure 3. Layout Considerations
4355 F03
IN1
GATE1
OUT
GATE2
IN2
S
S
S
G
D
D
D
D
D
D
D
D
G
S
S
S
LTC4355
FET FET
Layout Considerations
The following advice should be considered when laying
out a printed circuit board for the LTC4355.
The inputs to the servo amplifi ers, IN1, IN2, and OUT
should be connected as closely as possible to the
MOSFETs’ terminals for good accuracy.
Keep the traces to the MOSFETs wide and short. The PCB
traces associated with the power path through the MOS-
FETs should have low resistance (see Figure 3).
For the DFN package, pin spacing may be a concern at
voltages greater than 30V. Check creepage and clearance
guidelines to determine if this is an issue. Use no-clean
solder to minimize PCB contamination.
APPLICATIONS INFORMATION
LTC4355
12
4355fe
–36V to –72V/10A with Positive Supply and Negative Supply Diode-ORing
4355 F04
LTC4355
LTC4354 FAULT
GND
GATE1 GATE2IN1 OUTIN2
MON1
MON2
SET
12.7k
340k
12.7k
1μF
340k
10A
33k
12k
33k
2k
33k 33k
33k 33k
GREEN LEDs
PANASONIC LN1351C
RED LED
PANASONIC
LN1251CLA
10A
15A
15A
IRF3710
IRF3710
IRF3710
IRF3710
RTNA
RTNB
VSS
VCC
GBGADBDA
VA = –48V
VB = –48V
2k
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
LOAD
TYPICAL APPLICATIONS
LTC4355
13
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–48V/5A with Positive Supply and Negative Supply Diode-ORing with Reverse Input Protection
4355 F05
LTC4355
LTC4354
GND
GATE1 GATE2IN1 OUTIN2
1μF
10A
12k
2k
10A
7A
7A
FDS3672
FDS3672
FDS3672
FDS3672
RTNA
RTNB
NOTE: MAXIMUM VOLTAGE BETWEEN ANY TWO INPUTS = 80VDC
VSS
VCC
GBGADBDA
VA = –48V
VB = –48V
2k
LOAD
= BAS21
SMBT70A
TYPICAL APPLICATIONS
+24V Diode-OR With Reverse Input Protection
4355 TA05
LTC4355
GND
GATE1 GATE2IN2IN1 OUT
GND
FDS3672
VIN1 = +24V
VIN2 = +24V FDS3672
LOAD
SMBT70A
= BAS21
LTC4355
14
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TYPICAL APPLICATIONS
Single 12V/15A Ideal Diode with Parallel Drivers
Single 36V to 72V/30A Ideal Diode Using Parallel MOSFETs
LTC4355
GND
GATE1 GATE2IN1 OUTIN2
MON1
MON2
SET
R2
12.7k
R1
86.6k
F1
15A
R3
10k
R4
10k
R5
10k
D1 D2 D3
TO LOAD
GREEN LEDs
PANASONIC
LN1351C
M1
HAT2165H
VIN = 12V
GND
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
4355 TA03
4355 TA04
LTC4355
GND
IN2 GATE2GATE1IN1 OUT
MON1
MON2
SET
R2
12.7k
R1
340k
F1
30A
R3
33k
R5
33k
R4
33k
D1 D3
D2
GREEN LEDs
PANASONIC
LN1351C
GND
M1
IRFS4710
M2
IRFS4710
TO
LOAD
VIN = +48V
VDSFLT
FUSEFLT1
PWRFLT1
FUSEFLT2
PWRFLT2
LTC4355
15
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TYPICAL APPLICATIONS
AdvancedTCA with High Side and Low Side Ideal Diode-OR
and Hot SwapTM Controller with I2C Current and Voltage Monitor
MON2
SET
MON1
IN1 GATE1 IN2
GND
GATE2 OUT
LTC4355
SENSE
LTC4261
VIN
VEE
TMR GATE DRAIN
IRF1310NS
330nF
47nF
1μF
1.1k
1.1k
1.1k
1.1k
1M
10nF
100V
33nF
–48VOUT
4355 TA06
–48VRTN(OUT)
1k
2.49k
8mΩ
10Ω
330nF
100nF
100nF100nF
SS
UVH
UVL
ADIN2
OV
ON
INTVCC
FLTIN
EN
ADR1
ADR0
PG
SCL
SDAI
SDAO
ALERT
PGIO
PGI
ADIN
RAMP
10.2k100k
D: 1N4148WS
HZS5C1
VSS
VSS
GB
FDS3672
2k
2k
LTC4354
GA
VCC
10k
DBDA
137k 107k
1μF
22nF
100V
SMBT70A
91Ω
100k
D
DD
D
FDS3672
100k
7A
–48V_A
–48V_B
MEDIUM LONG
7A
MEDIUM SHORT
10A
LONG
SHORT
SHORT
VRTN_A
ENABLE_B
ENABLE_A
VDA–
10A
LONG
VRTN_B
VDA–
FDS3672
FDS3672
100k
1M1M
100k
FMMT5401
FMMT5401
100nF
LTC4355
16
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TYPICAL APPLICATIONS
36V to 72V/10A with Positive Supply and Negative Supply Diode-ORing,
Combined Fault Outputs, and Zener Clamps on MOSFET Gates
4355 TA07
LTC4355
LTC4354 FAULT
GND
GATE1 GATE2IN1 OUTIN2
MON1
MON2
SET
12.7k
340k
12.7k
1μF
340k
10A
12k
2k
33k
GREEN LED
PANASONIC
LN1351C
10A
15A
15A
IRLR3110ZPbF
IRLR3110ZPbF
IRLR3110ZPbF
IRLR3110ZPbF
VA = 48V
VB = 48V
VSS
VCC
GBGADBDA
GNDA
GNDB
2k
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
LOAD
12V ZENER
CM4Z669-LTC
12V ZENER
CM4Z669-LTC
100k
2N2222
LTC4355
17
4355fe
PACKAGE DESCRIPTION
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
3.00 REF
1.70 ± 0.05
17
148
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DE14) DFN 0806 REV B
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.25 ± 0.05
0.50 BSC
3.30 ±0.05
3.30 ±0.10
0.50 BSC
LTC4355
18
4355fe
PACKAGE DESCRIPTION
S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0° – 8° TYP
.008 – .010
(0.203 – 0.254)
1
N
2345678
N/2
.150 – .157
(3.810 – 3.988)
NOTE 3
16 15 14 13
.386 – .394
(9.804 – 10.008)
NOTE 3
.228 – .244
(5.791 – 6.197)
12 11 10 9
S16 0502
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
.245
MIN
N
1 2 3 N/2
.160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
MSOP (MS16) 1107 REV Ø
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
16151413121110
12345678
9
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 p 0.038
(.0120 p .0015)
TYP
0.50
(.0197)
BSC
4.039 p 0.102
(.159 p .004)
(NOTE 3)
0.1016 p 0.0508
(.004 p .002)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0.280 p 0.076
(.011 p .003)
REF
4.90 p 0.152
(.193 p .006)
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
LTC4355
19
4355fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibilit y is assumed for its use. Linear Technology Corpor ation makes no representa-
t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s .
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
E 02/10 Updated Features section and removed patent 1
Revised tOFF conditions 3
Revised NC pin description 5
Revised Typical Application drawings 13, 15, 16
Corrected part number LTC4352 in Related Parts 20
(Revision history begins at Rev E)
LTC4355
20
4355fe
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 0210 REV E • PRINTED IN USA
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT1640AH/LT1640AL Negative High Voltage Hot Swap Controllers
in SO-8
Negative High Voltage Supplies From –10V to –80V
LT1641-1/LT1641-2 Positive High Voltage Hot Swap Controllers Active Current Limiting, Supplies From 9V to 80V
LTC1921 Dual –48V Supply and Fuse Monitor UV/OV Monitor, –10V to –80V Operation, MSOP Package
LT4250 –48V Hot Swap Controller Active Current Limiting, Supplies From –20V to –80V
LTC4251/LTC4251-1/
LTC4251-2
–48V Hot Swap Controllers in SOT-23 Fast Active Current Limiting, Supplies From –15V
LTC4252-1/LTC4252-2/
LTC4252-A1/LTC4252-A2
–48V Hot Swap Controllers in MS8/MS10 Fast Active Current Limiting, Supplies From –15V, Drain Accelerated
Response
LTC4253 –48V Hot Swap Controller with Sequencer Fast Active Current Limiting, Supplies From –15V, Drain Accelerated
Response, Sequenced Power Good Outputs
LT4256 Positive 48V Hot Swap Controller with
Open-Circuit Detect
Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output,
Up to 80V Supply
LTC4260 Positive High Voltage Hot Swap Controller With I2C and ADC, Supplies from 8.5V to 80V
LTC4261 Negative High Voltage Hot Swap Controller With I2C and 10-Bit ADC, Adjustable Inrush and Overcurrent Limits
LTC4350 Hot Swappable Load Share Controller Output Voltage: 1.2V to 20V, Equal Load Sharing
LTC4352 Ideal Diode Controller with Monitor Controls N-Channel MOSFET, 0V to 18V Operation
LTC4354 Negative Voltage Diode-OR Controller
and Monitor
Controls Two N-Channel MOSFETs, 1μs Turn-Off, 80V Operation
LTC4357 Positive High Voltage Ideal Diode Controller Controls Single N-Channel MOSFET, 0.5μs Turn-Off, 80V Operation
LTC4358 5A Ideal Diode Integrated N-Channel MOSFET, 0.5μs Turn-Off, 9V to 26.5V
200W AdvancedTCA Ideal Diode-OR
4355 TA08
LTC4355
LTC4354
GND
GATE1 GATE2IN1 OUTIN2
1μF
10A
12k
2k
10A
7A
7A
FDS3672
FDS3672
FDS3672
FDS3672
RTNA
RTNB
VSS
VCC
GBGADBDA
VA = –48V
VB = –48V
2k
LOAD
RELATED PARTS
