HMP112S6NFR8C-S5 - SK Hynix

This document is a general product description and is subject t o change without notice. Hynix Semiconductor do es not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1 / Feb. 2010 1

200pin Unbuffered DDR2 SDRAM SO-D IMMs based on 1Gb version N

This Hynix unbuffered Small Outline Dual In-Line Memory Module(DIMM) series consists of 1Gb version N DDR2

SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 1Gb version N based

Unbuffered D DR2 SO-DIMM series provide a high perf ormance 8 byte interf ace in 67.60mm width form f actor of indus-

try standard. It is suitable for easy interchange and addition.

FEATURES

ORDERING INFORMATION

Part Name Density Organization # of

DRAMs # of

ranks Materials

HMP112S6NFR8C-Y5/S5/S6 1GB 128Mx64 8 1 Halogen free

HMP125S6NFR8C-Y5/S5/S6 2GB 256Mx64 16 2 Halogen free

• JEDEC standard Double Data Rate 2 Synchronous

DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power

Supply

• All inputs and outputs are compatible with SS TL_1.8

interface

•Posted CAS

• Programmable CAS Latency 3 ,4 ,5, and 6

• OCD (Off-Chip Driver Impedance Adjustment) and

ODT (On-Die Termination)

• Fully differential clock operations (CK & CK)

• Programmable Burst Length 4 / 8 with both

sequential and interleave mode

• Auto refresh and self refresh supported

• 8192 refresh cycles / 64ms

• Serial presence detect with EEPROM

• DDR2 SDRAM Package: 60 ball(x8) FBGA

• 67.60 x 30.00 mm form factor

•RoHS compliant

Rev. 0.1 / Feb. 2010 2

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

SPEED GRADE & KEY PARAMETERS

ADDRESS TABLE

Y5

(DDR2-667) S6

(DDR2-800) S5

(DDR2-800) Unit

Speed@CL3 400 -400 Mbps

Speed@CL4 533 533 533 Mbps

Speed@CL5 667 667 800 Mbps

Speed@CL6 - 800 - Mbps

CL-tRCD-tRP 5-5-5 6-6-6 5-5-5 tCK

Density Organization Ranks SDRAMs # of

DRAMs # of row/bank/column Address Refresh

Method

1GB 128M x 64 1 128Mb x 8 8 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms

2GB 256M x 64 2 128Mb x 8 16 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms

Rev. 0.1 / Feb. 2010 3

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PIN DESCRIPTION

Symbol Type Polarity Pin Description

CK[1:0], CK[1:0] Input Cross

Point

The system clock inputs. All adress an co mmands lines are sampled on the cross point

of the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is

driven from the cloc k inputs an d output tim in g for read operations is synchronized to

the input clock.

CKE[1:0] Input Active

High

Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when

low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self

Refresh mode.

S[1:0] Input Active

Low

Enables the associated DDR2 SDRAM command decoder when low and disables the

command decoder when high. When the command decoder is disab led, new commands

are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is

selected by S1

RAS, CAS, WE Input Active

Low When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS,

RAS and WE define the operation to be excecuted by the SDRAM.

BA[2:0] Input Selects which DDR2 SDRAM internal bank of four or eight is activated.

ODT[1:0] Input Active

High Asserts on-die terminat io n for DQ , DM, DQS and DQS signals if enabled via the DDR2

SDRAM mode register.

A[9:0], A10/AP,

A[15:11] Input

During a Bank Activate command cycle, difines the row address when sampled at the

cross point of the rising edge of CK and falling edge of CK. During a Read or Write com-

mand cycle, defin e s th e co lumn address when sampled at the cross point of the rising

edge of CK and falling edge of CK. In addition to the colum n address, AP is used to

invoke autoprecharge operation at the end of the burst read or write cycle. If AP is

high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP

is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in

conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks

will be prechar ged regardless of the state of BA0-BAn inputs. If AP is lo w, then BA0-BAn

are used to define which bank to precharge.

DQ[63:0] In/Out Data Input/Output pins.

DM[7:0] Input Active

High

The data write masks, associated with one data byte. In Write mode, DM operates as a

byte mask by allowing input data to be written if it is low but blocks the write operation

if it is high. In Read mode, DM lines have no effect.

DQS[7:0], DQS[7:0] In/Out Cross

point

The data strobe, associat ed w ith one data byte, sourced w hit data transfers. In Write

mode, the data strobe is sourced by the controller and is centered in the data window.

In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading

edge of the data window. DQS signals are complements, and timing is relative to the

crosspoint of respective DQS and DQS. If the module is to be operated in single ended

strobe mode, all DQS signals must be tied on the system board to VSS and DDR2

SDRAM mode registers programmed approriately.

VDD, VDDSPD,VSS Supply Power supplies for core, I/O, Serial Presense Detect, and ground for the module.

SDA In/Out This is a bid irect ional pin used to transfer data into or out of the SPD EEPROM. A

resister must be connected to VDD to act as a pull up.

SCL Input This signals is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from SCL to VDD to act as a pull up.

SA[1:0] Input Address pins used to select the Serial Presence Detect base address.

TEST In/Out The TEST pin is reserved for bus analysis tools and is not connected on normal memory

modules(SODIMMs).

Rev. 0.1 / Feb. 2010 4

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PIN ASSIGNMENT

Pin Location

NO. Front

Side Pin

NO. Back

Side Pin

NO. Front

Side Pin

NO. Back

Side Pin

NO. Front

Side Pin

NO. Back

Side Pin

NO. Front

Side Pin

NO. Back

Side

1 VREF 2 VSS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46

3 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47

5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS

7 DQ1 8 VSS 57 DQ19 58 DQ23 107 BA0 108 RAS 157 DQ48 158 DQ52

9 VSS 10 DM0 59 VSS 60 VSS 109 WE 110 S0 159 DQ49 160 DQ53

11 DQS0 12 VSS 61 DQ24 62 DQ28 111 VDD 112 VDD 161 VSS 162 VSS

13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 CAS 114 ODT0 163 NC,TEST 164 CK1

15 VSS 16 DQ7 65 VSS 66 VSS 115 NC/S1 116 A13 165 VSS 166 CK1

17 DQ2 18 VSS 67 DM3 68 DQS3 117 VDD 118 VDD 167 DQS6 168 VSS

19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC/ODT1 120 NC 169 DQS6 170 DM6

21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS

23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54

25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55

27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS

29 DQS1 30 CK0 79 CKE0 80 NC/CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60

31 DQS1 32 CK0 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61

33 VSS 34 VSS 83 NC 84 NC/A15 133 VSS 134 DQ38 183 VSS 184 VSS

35 DQ10 36 DQ14 85 BA2 86 NC/A14 135 DQ34 136 DQ39 185 DM7 186 DQS7

37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7

39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS

41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62

43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63

45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 DQS5 195 SDA 196 VSS

47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0

49 DQS2 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1

Front Side

Pin #1 Pin #39 Pin #41 Pin #99

Back Side

Pin #2 Pin #40 Pin #42 Pin #200

Rev. 0.1 / Feb. 2010 5

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

FUNCTIONAL BLOCK DIAGRAM

1GB(128Mbx64): HMP112S6NFR8C

DQ0

DQS0

/DQS0

DM0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS

I/O 7

D0

DQS

/DQS

DM

/S0

3

Ω

+/-5%

ODT0

CKE0

ODT CKE

DQ8

DQS1

/DQS1

DM1

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS

I/O 7

D1

DQS

/DQS

DM

ODT CKE

DQ16

DQS2

/DQS2

DM2

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS0

I/O 7

D2

DQS

/DQS

DM

ODT CKE

DQ24

DQS3

/DQS3

DM3

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS

I/O 7

D3

DQS

/DQS

DM

ODT CKE

DQ32

DQS4

/DQS4

DM4

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS

I/O 7

D4

DQS

/DQS

DM

ODT CKE

DQ40

DQS5

/DQS5

DM5

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS

I/O 7

D5

DQS

/DQS

DM

ODT CKE

DQ48

DQS6

/DQS6

DM6

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS

I/O 7

D6

DQS

/DQS

DM

ODT CKE

DQ56

DQS7

/DQS7

DM7

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS

I/O 7

D7

DQS

/DQS

DM

ODT CKE

BA0-BA2

A0-AN

/RAS

/CAS

/WE

SDRAMS D0-D7

CK0

/CK0 4 loads

CK1

/CK1

4 loads

SDA

SCL

WP

A0

A1

A2

Serial PD

SCL SDA

SA0

SA1

V

REF

V

DD

V

DD

SPD Serial PD

V

SS

SDRAMS D0-D7, SPD

SDRAMS D0-D7, V

DD

and V

DD

Q

SDRAMS D0-D7

Note:

1.Resisto r values are 22 ohm +/-5%

unless otherwide stated.

3

Ω

+/-5%

Rev. 0.1 / Feb. 2010 6

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

FUNCTIONAL BLOCK DIAGRAM

2GB(256Mbx64) : HMP125S6NFR8C

DQ0

CKE1

DQS0

/DQS0

DM0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS0

I/O 7

D0

DQS

/DQS

DM

ODT1

/S0

3

Ω

+/-5%

ODT0

CKE0

/S1

ODT0 CKE0

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS1

I/O 7

D8

DQS

/DQS

DM

ODT1 CKE1

DQ8

DQS1

/DQS1

DM1

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS0

I/O 7

D2

DQS

/DQS

DM

ODT0 CKE0

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS1

I/O 7

D10

DQS

/DQS

DM

ODT1 CKE1

DQ16

DQS2

/DQS2

DM2

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS0

I/O 7

D4

DQS

/DQS

DM

ODT0 CKE0

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS1

I/O 7

D12

DQS

/DQS

DM

ODT1 CKE1

DQ24

DQS3

/DQS3

DM3

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS0

I/O 7

D6

DQS

/DQS

DM

ODT0 CKE0

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS1

I/O 7

D14

DQS

/DQS

DM

ODT1 CKE1

DQ32

DQS4

/DQS4

DM4

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS0

I/O 7

D1

DQS

/DQS

DM

ODT0 CKE0

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS1

I/O 7

D9

DQS

/DQS

DM

ODT1 CKE1

DQ40

DQS5

/DQS5

DM5

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS0

I/O 7

D3

DQS

/DQS

DM

ODT0 CKE0

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS1

I/O 7

D11

DQS

/DQS

DM

ODT1 CKE1

DQ48

DQS6

/DQS6

DM6

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS0

I/O 7

D5

DQS

/DQS

DM

ODT0 CKE0

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS1

I/O 7

D13

DQS

/DQS

DM

ODT1 CKE1

DQ56

DQS7

/DQS7

DM7

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS0

I/O 7

D7

DQS

/DQS

DM

ODT0 CKE0

I/O 5

I/O 6

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

/CS1

I/O 7

D15

DQS

/DQS

DM

ODT1 CKE1

BA0-BA2

A0-AN

/RAS

/CAS

/WE

SDRAMS D0-15

CK0

/CK0 8 loads

CK1

/CK1

8 loads

SDA

SCL

WP

A0

A1

A2

Serial PD

SCL SDA

SA0

SA1

V

REF

V

DD

V

DD

SPD Serial PD

V

SS

SDRAMS D0-D15, SPD

SDRAMS D0-D15, V

DD

and V

DD

Q

SDRAMS D0-D15

Note:

1.Resisto r values are 22 ohm +/-5%

unless otherwide stated.

10

Ω

+/-5%

5.6pF

Rev. 0.1 / Feb. 2010 7

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

ABSOLUTE MAXIMUM RATINGS

Operating Conditions and Environmental Parameters

Notes:

1. Stress greater than those listed may cause permanent dama ge to the device. This is a stress r ating only, and device

functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating con

ditions for extended periods may affect reliability.

2. Up to 9850 ft.

3. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to

tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.

DC OPERATING CONDITIONS (SSTL_1.8)

Note:

1. Min. Typ. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option.

2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD.

3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the

value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track varia-

tions in VDDQ.

4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).

5. VTT of transmitting device must track VREF of receiving device.

Parameter Symbol Value Unit Note

Voltage on VDD pin relative to Vss VDD - 1.0 V ~ 2.3 V V 1

Voltage on VDDQ pin relative to Vss VDDQ - 0.5 V ~ 2.3 V V 1

Voltage on VDDL pin relati ve to Vss VDDL -0.5V ~ 2.3 V V 1

Voltage on any pin relative to Vss VIN, VOUT - 0.5 V ~ 2.3 V V 1

Parameter Symbol Rating Units Notes

DIMM Operating temperature(ambient) TOPR 0 ~ +65 oC

Storage Temperature TSTG -50 ~ +100 oC1

Storage Humidity(without condensation) HSTG 5 to 95 % 1

DIMM Barometric Pressure(ope rating & storage) PBAR 105 to 69 K Pascal 2

DRAM Component Case Temperature Range TCASE 0 ~+95 oC3

Symbol Parameter Rating Units Notes

Min. Typ. Max.

VDD Supply Voltage 1.7 1.8 1.9 V 1

VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 1,2

VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 1,2

VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 3,4

VTT Termination Voltage VREF-0.04 VREF VREF+0.04 V 5

VDDSPD EEPROM Supply Voltage 1.8 - 3.3 V

Rev. 0.1 / Feb. 2010 8

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

INPUT DC LOGIC LEVEL

INPUT AC LOGIC LEVEL

AC INPUT TEST CONDITIONS

Notes:

1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device

under test.

2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges

and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions

and VIH(ac) to VIL(ac) on the negative transitions.

Parameter Symbol Min Max Unit Note

dc Input logic HIGH VIH(DC) VREF + 0.125 VDDQ + 0.3 V

dc Input logic LOW VIL(DC) -0.30 VREF - 0.125 V

Parameter Symbol DDR2 667/800 Unit

Min Max

AC Input logic HIGH VIH(AC) VREF + 0.200 - V

AC Input logic LOW VIL(AC) -V

REF - 0.200 V

Symbol Condition Value Units Notes

VREF Input reference voltage 0.5 * VDDQ V1

VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1

SLEW Input signal minimum slew rate 1.0 V/ns 2, 3

VDDQ

VIH(ac) min

VIH(dc) min

VREF

VIL(dc) max

VIL(ac) max

VSS

V

SWING(MAX)

delta TRdelta TF

VREF

-

VIL

(ac)

max

delta TF

Falling Slew = Rising Slew =

VIH

(ac)

min

- V

REF

delta TR

< Figure : AC Input Test Signal Waveform>

Rev. 0.1 / Feb. 2010 9

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

Differential Input AC logic Level

1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,

LDQS, UDQS and UDQS.

2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input

(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level.

The minimum value is equal to VIH(DC) - VIL(DC).

Notes:

1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal

(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).

The minimum value is equal to V IH(AC) - VIL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to

track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.

DIFFERENTIAL AC OUTPUT PARAMETERS

Notes:

1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to

track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.

Symbol Parameter Min. Max. Units Note

VID (ac) ac differential input voltage 0.5 VDDQ + 0.6 V 1

VIX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2

Symbol Parameter Min. Max. Units Note

VOX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1

Crossing point

VSSQ

VTR

VCP

VID VIX or VOX

< Differential signal levels >

Rev. 0.1 / Feb. 2010 10

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

OUTPUT BUFFER LEVELS

OUTPUT AC TEST CONDITIONS

Notes:

1. The VDDQ of the device under test is referenced.

OUTPUT DC CURRENT DRIVE

Notes:

1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and

VDDQ - 280 mV.

2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.

3. The dc value of VREF applied to the receiving device is set to VTT

4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device

drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an

SSTL_18 receiver.

The actual current values are derived by shifting the desired driver oper ating point along a 21 ohm load line to define

a convenient driver current for measurement.

Symbol Parameter SSTL_18 Units Notes

VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V1

Symbol Parameter SSTl_18 Units Notes

IOH(dc) Output Minimum Source DC Current - 13.4 mA 1, 3, 4

IOL(dc) Output Minimum Sink DC Current 13.4 mA 2, 3, 4

Rev. 0.1 / Feb. 2010 11

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25°…)

1GB : HMP112S6NFR8C

2GB : HMP125S6NFR8C

Notes:

1. Pins not under test are tied to GND.

2. These value are guaranteed by design and tested on a sample basis only.

Pin Symbol Min Max Unit

CK, CK CCK 17 20 pF

CKE, ODT,CS CI1 22 25 pF

Address, RAS, CAS, WE CI2 28.5 37 pF

DQ, DM, DQS, DQS CIO 10 12 pF

Pin Symbol Min Max Unit

CK, CK CCK 17 29 pF

CKE, ODT,CS CI1 24 38 pF

Address, RAS, CAS, WE CI2 31 56 pF

DQ, DM, DQS, DQS CIO 7 12 pF

Rev. 0.1 / Feb. 2010 12

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

IDD SPECIFICATIONS (TCASE : 0 to 95oC)

1GB, 128M x 64 SO-DIMM : HMP112S6NFR8C

2GB, 256M x 64 SO-DIMM : HMP125S6NFR8C

Notes:

1. IDD6 current values are guaranteed up to Tcase of 85°C max.

Symbol Y5

(DDR2 667@CL5) S5/S6

(DDR2 800@C L5&6) Unit Note

IDD0 560 600 mA

IDD1 640 680 mA

IDD2P 80 80 mA

IDD2Q 240 256 mA

IDD2N 320 360 mA

IDD3P(F) 200 200 mA

IDD3P(S) 96 96 mA

IDD3N 400 440 mA

IDD4R 1240 1440 mA

IDD4W 1200 1360 mA

IDD5B 1400 1440 mA

IDD6 80 80 mA 1

IDD6(L) 40 40 mA 1

IDD7 1600 1880 mA

Symbol Y5

(DDR2 667@CL5) S5/S6

(DDR2 800@CL5&6) Unit Note

IDD0 880 960 mA

IDD1 960 1040 mA

IDD2P 160 160 mA

IDD2Q 480 512 mA

IDD2N 640 720 mA

IDD3P(F) 400 400 mA

IDD3P(S) 192 192 mA

IDD3N 800 880 mA

IDD4R 1560 1800 mA

IDD4W 1520 1720 mA

IDD5B 1720 1800 mA

IDD6 160 160 mA 1

IDD6(L) 80 80 mA 1

IDD7 1920 2240 mA

Rev. 0.1 / Feb. 2010 13

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

IDD Measurement Cond itions

Notes:

1. IDD specifications are tested after the device is properly initialized

2. Input slew rate is specified by AC Parametric Test Condition

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combina-

tions of EMRS bits 10 and 11.

5. Definitions for IDD

LOW is defined as Vin £ VILAC(max)

HIGH is defined as Vin Š VIHAC(min)

STABLE is defined as inputs stable at a HIGH or LOW level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and

control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)

for DQ signals not including masks or strobes.

Symbol Conditions Units

IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS-

min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus

inputs are SWITCHING mA

IDD1 Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH

between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W mA

IDD2P Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address

bus inputs are STABLE; Data bus inputs are FLOATING mA

IDD2Q Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING mA

IDD2N Precharge standby current; All ban ks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and

address bus inputs are SWITCHING; Data bu s inputs are SWITCHING mA

IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is L OW ;

Other control and address bus inputs are STABLE; Data bus inputs are FLOAT-

ING

Fast PDN Exit MRS(12) = 0 mA

Slow PDN Exit MRS(12) = 1 mA

IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is

HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus

inputs are SWITCHING mA

IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK

= tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bu s inputs are SWITCHING mA

IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),

AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid com-

mands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W mA

IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is

HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING mA

IDD6 Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING;

Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85 ℃ max. mA

IDD7

Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),

AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is

HIGH, CS is HIGH between valid commands; Address bus inputs are ST ABLE during DESELECTs; Data pattern is

same as IDD4R; - Refer to the following page for detailed timing conditions

mA

Rev. 0.1 / Feb. 2010 14

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

Electrical Characteristics & AC Timings

Speed Bins and CL,tRCD,tRP,tRC and tRAS for Correspond ing Bin

Speed DDR2-800 (S5) DDR2-800 (S6) DDR2-667 (Y5) Unit

Bin(CL-tRCD-tRP) 5-5-5 6-6-6 5-5-5

Parameter min min min

CAS Latency 5 6 5 tCK

tRCD 12.5 15 15 ns

tRP 12.5 15 15 ns

tRAS 45 45 45 ns

tRC 57.5 60 60 ns

Rev. 0.1 / Feb. 2010 15

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

AC Timing Parameters by Speed Grade

Parameter Symbol DDR2-667 DDR2-800 Unit Note

min max min max

DQ output access time from CK/CK tAC -450 +450 -400 +400 ps

DQS output access time from CK/CK tDQSCK -400 +400 -350 +350 ps

CK high-level width tCH 0.45 0.55 0.48 0.52 tCK

CK low-level width tCL 0.45 0.55 0.48 0.52 tCK

CK half period tHP min(tCL,

tCH) -min(tCL,

tCH) -ps

Clock cycle time, CL=x tCK 3000 8000 2500 8000 ps

DQ and DM input setup time

(differential strobe) tDS 100 - 50 - ps 1

DQ and DM input hold time

(differential strobe) tDH 175 - 125 - ps 1

Control & Address input pulse width for each

input tIPW 0.6 - 0.6 - tCK

DQ and DM input pulse width for each input tDIPW 0.35 - 0.35 - tCK

Data-out high-impedance time from CK/CK tHZ - tAC max tAC max ps

DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps

DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps

DQS-DQ skew for DQS and associated DQ

signals tDQSQ - 240 - 240 ps

DQ hold skew factor tQHS - 340 - 300 ps

DQ/DQS output hold time from DQS tQH tHP - tQHS -tHP - tQHS -ps

First DQS latching transition to associated

clock edge tDQSS -0.25 +0.25 -0.25 +0.25 tCK

DQS input high pulse width tDQSH 0.35 -0.35 -tCK

DQS input low pulse width tDQSL 0.35 -0.35 -tCK

DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK

DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK

Mode register set command cycle time tMRD 2 - 2 - tCK

Write preamble tWPRE 0.35 -0.35 -tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK

Address and control input setup time tIS 200 -175 -ps

Address and control input hold time tIH 275 -250 -ps

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

Activate to precharge command tRAS 45 70000 45 70000 ns

Row Active to Row Active Delay for 1KB

page size tRRD 7.5 -7.5 -ns

Row Active to Row Active Delay for 2KB

page size tRRD 10 - 10 - ns

Four Active Window for 1KB page size

products tFAW 37.5 -35 -ns

Four Active Window for 2KB page size

products tFAW 50 -45 -ns

Rev. 0.1 / Feb. 2010 16

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

- contin ued -

Notes:

1. For details and notes, please refer to the relevant Hynix component datasheet(H5PS1G8NFR).

2. 0°C ≤ TCASE ≤ 85°C

3. 85°C ＜ TCASE ≤ 95°C

Parameter Symbol DDR2-667 DDR2-800 Unit Note

min max min max

CAS to CAS command delay tCCD 2 2 - tCK

Write recovery ti me tWR 15 -15 -ns

Auto precharge write re covery + precharge

time tDAL WR+tRP -WR+tRP -tCK

Internal write to read command delay tWTR 7.5 -7.5 -ns

Internal read to precharge command delay tRTP 7.5 7.5 -ns

Exit self refresh to a non-read command tXSNR tRFC + 10 -tRFC + 10 -ns

Exit self refresh to a read command tXSRD 200 -200 -tCK

Exit precharge power down to any non-

read command tXP 2 - 2 - tCK

Exit active power down to read command tXARD 2 - 2 - tCK

Exit active power down to read command

(Slow exit, Lower power) tXARDS 7 - AL -8 - AL -tCK

CKE minimum pulse width

(high and low pulse width) tCKE 3 - 3 - tCK

ODT turn-on delay tAOND 2 2 2 2 tCK

ODT turn-on tAON tAC(min) tAC(max)+0.7 tAC(min) tAC(max)+0.7 ns

ODT turn-on(Power-Down mode) tAONPD tAC(min)+2 2tCK+

tAC(max)+1 tAC(min)+2 2tCK+

tAC(max)+1 ns

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF tAC(min) tAC(max)+ 0.6 tAC(min) tAC(max)+ 0.6 ns

ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5tCK+

tAC(max)+1 tAC(min)+2 2.5tCK+

tAC(max)+1 ns

ODT to power down entry latency tANPD 3 - 3 - tCK

ODT power down exit latency tAXPD 8 8 tCK

OCD drive mode output delay tOIT 0 12 0 12 ns

Minimum time clocks remains ON after CKE

asynchronously drops LO W tDelay tIS+tCK+tIH - tIS+tCK+tIH - ns

Average periodic Refresh Interval tREFI - 7.8 - 7.8 us 2

tREFI -3.9 - 3.9 us 3

Rev. 0.1 / Feb. 2010 17

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PACKAGE OUTLINE

128Mx64 - HMP112S6NFR8C

47.40

PIN 199

PIN 1 PIN 39 PIN 41

67.60

2.00 Min

2.15

4.00

±

0.10

11.40

1.80

±

0

.10

4.20

30.00

20.00

6.00

Detail B Detail A

1.50 ±0.10

2.45 11.40 47.40

PIN 200

PIN 2 PIN 40 PIN42

0.20

±

0.15

2.55

0.60

Detail of Contacts A

1.0

±

0.05

Detail of Contacts B (Front)

4.20

4.0

±

0.10

2.70

±

0.10

4.20

2.40

±

0.10

1.50

1.80

Detail of Contacts B (Back)

0.45

±

0.03

Note:

1. All dimensions are in millimeters.

2. All outline dimensions and tolerances follow the JEDEC standard.

Detail B

Front

Back

3.8MAX

1.00 ±0.10

SIDE

Rev. 0.1 / Feb. 2010 18

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PACKAGE OUTLINE

256Mx64 - HMP125S6NFR8C

47.40

PIN 1

67.60

2.00 Min

2.15

4.00

±

0.10

11.40

1.80

±

0

.10

4.20

30.00

20.00

6.00

Detail B

Front

PIN 41

PIN 39 Detail A

1.50

±

0.10

2.45 11.40 47.40

PIN 2

Back

Detail B

PIN 200

PIN42

PIN 40

PIN 199

0.20

±

0.15

2.55

0.60

0.45

±

0.03

Detail of Contacts A

1.0

±

0.05

Detail of Contacts B (Front)

4.20

2.70

±

0.10

4.20

2.40

±

0.10

1.50

1.80

Detail of Contacts B (Back)

Note:

1. All dimensions are in millimeters.

2. All outline dimensions and tolerances follow the JEDEC standard.

3.8MAX

1.00 ±0.10

SIDE

4.0

±

0.10

Rev. 0.1 / Feb. 2010 19

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

REVISION HISTORY

Revision History Date

0.1 Initial data sheet released Feb. 2010