Rev. 1.0 4/15 Copyright © 2015 by Silicon Laborato ries Si5351A/B/C-B
Si5351A/B/C-B
I2C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK
GENERATOR + VCXO
Features
Applications
Description
The Si5351 is an I2C configurable clock generator that is ideally suited for replacing
crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in
cost-sensitive applications. Based on a PLL/VCXO + hi gh re solutio n MultiSynth fractional
divider architecture, the Si5351 can generate any frequency up to 200 MHz on each of its
outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide
variety of applications. The Si5351A generates up to 8 free-running clocks using an
internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an
internal VCXO and provides the flexibility to replace both free-running clocks and
synchronous clocks. It elimin ates the need fo r higher cost, custom pullable crystals while
providing reliable operation over a wide tuning range. The Si5351C offers the same
flexibility but synchronizes to an external reference clock (CLKIN).
Functional Block Diagram
www.silabs.com/custom-timing
Generates up to 8 non-integer-relate d
frequencies from 2.5 kHz to 200 MHz
I2C user definable configuration
Exact frequency synthesis at each output
(0 ppm error)
Highly linear VCXO
Optional clock input (CLKIN)
Low output period jitter: < 70 ps pp, typ
Configurable spread spectrum selectable
at each output
Operates from a low-cost, fixed frequency
crystal: 25 or 27 MHz
Supports static phase offset
Programmable rise/fall time control
Glitchless frequency changes
Separate voltage supply pins provide
level translation:
Core VDD: 2.5 or 3.3 V
Output VDDO : 1.8, 2.5, or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
Adjustable output delay
Available in 2 packages types:
10-MSOP: 3 outpu ts
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compatible
Supports HCSL compatible swing
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Handheld Instrumentation
Residential gateways
Networking/communication
Servers, storage
XO replacement
R0
R1
CLK0
CLK1
VDDOA
R2
R3
CLK2
CLK3
VDDOB
R4
R5
CLK4
CLK5
VDDOC
R6
R7
CLK6
CLK7
VDDOD
MultiSynth
0
MultiSynth
1
MultiSynth
2
MultiSynth
3
MultiSynth
4
MultiSynth
5
MultiSynth
6
MultiSynth
7
PLL
A
PLL
B
XA
XB OSC
CLKIN
SCL
SDA
Control
Logic
INTR
OEB
I2C
Si5351C (20-QFN)
OSC
XA
XB
PLL
VCXO
R0
R1
CLK0
CLK1
VDDOA
R2
R3
CLK2
CLK3
VDDOB
R4
R5
CLK4
CLK5
VDDOC
R6
R7
CLK6
CLK7
VDDOD
MultiSynth
0
MultiSynth
1
MultiSynth
2
MultiSynth
3
MultiSynth
4
MultiSynth
5
MultiSynth
6
MultiSynth
7
VC
SCL
SDA
Control
Logic
OEB
SSEN
I2C
Si5351B (20-QFN)
Ordering Information:
See page 29
10-MSOP
20-QFN
Si5351A/B/C-B
2 Rev. 1.0
Table 1. The Complete Si5350/51 Clock Generator Family
Part Number I2C or Pin Frequency Reference Programmed? Output s Dat ash eet
Si5351A-B-GT I2C XTAL only Blank 3 Si5351-B
Si5351A-B-GM I2C XTAL only Blank 8 Si5351-B
Si5351B-B-GM I2C XTAL and/or Voltage Blank 8 Si5351-B
Si5351C-B-GM I2C XTAL and/or CLKIN Blank 8 Si5351-B
Si5351A-Bxxxxx-GT I2C XTAL only Factory Pre-Programmed 3 Si5351-B
Si5351A-Bxxxxx-GM I2C XTAL only Factory Pre-Programmed 8 Si5351-B
Si5351B-Bxxxxx-GM I2C XTAL and/or Voltage Factory Pre-Programmed 8 Si5351-B
Si5351C-Bxxxxx-GM I2C XTAL and/or CLKIN Factory Pre-Programmed 8 Si5351-B
Si5350A-Bxxxxx-GT Pin XTAL only Factory Pre-Programmed 3 Si5350A-B
Si5350A-Bxxxxx-GM Pin XTAL only Factory Pre-Programmed 8 Si5350A-B
Si5350B-Bxxxxx-GT Pin XTAL and/or Voltage Factory Pre-Programmed 3 Si5350B-B
Si5350B-Bxxxxx-GM Pin XTAL and/or Voltage Factory Pre-Programmed 8 Si5350B-B
Si5350C-Bxxxxx-GT Pin XTAL and/or CLKIN Factory Pre-Programmed 3 Si5350C-B
Si5350C-Bxxxxx-GM Pin XTAL and/or CLKIN Factory Pre-Programmed 8 Si5350C-B
Notes:
1. XTAL = 25/27 MHz, Voltage = 0 to VDD, CLKIN = 10 to 100 MHz. "xxxxx" = unique custom code.
2. Create custom, factory pre-programmed parts at www.silabs.com/ClockBuilder.
Si5351A/B/C-B
Rev. 1.0 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.3. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.4. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.5. Control Pins (OEB, SSEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5. Configuring the Si5351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.1. Writing a Custom Configuration to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.2. Si5351 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.3. Replacing Crystals and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.4. Replacing Crystals, Crystal Oscillators, and VCXOs . . . . . . . . . . . . . . . . . . . . . . . .20
5.5. Replacing Crystals, Crystal Oscillators, and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.6. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.7. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.1. Power Supply Decoupling/Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.3. External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.4. External Crystal Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.5. Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.6. Trace Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
8. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
9. Si5351 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
9.1. Si5351A 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
9.2. Si5351B 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
9.3. Si5351C 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
9.4. Si5351A 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
11. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
11.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
12. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
12.1. 10-Pin MSOP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
13. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
14.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
14.3. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Si5351A/B/C-B
4 Rev. 1.0
14.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Si5351A/B/C-B
Rev. 1.0 5
1. Electrical Specifications
Table 2. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Temperature TA–402585°C
Core Supply Voltage VDD 3.0 3.3 3.60 V
2.25 2.5 2.75 V
Output Buffer Voltage VDDOx
1.71 1.8 1.89 V
2.25 2.5 2.75 V
3.0 3.3 3.60 V
Notes:All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
VDD and VDDOx can be operated at independent voltages.
Power supply sequencing for VDD and VDDOx requires that all VDDOx be powered up eithe r before or at the same
time as VDD.
Table 3. DC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Core Supply Current IDD Enabled 3 outputs — 22 35 mA
Enabled 8 outputs — 27 45 mA
Output Buffer Supply Current
(Per Output)* IDDOx CL= 5 pF — 2.2 5.6 mA
Input Current ICLKIN CLKIN, SDA, SCL
Vin < 3.6 V ——10 µA
IVC VC — — 30 µA
Output Impedance ZO3.3 V VDDO, default high
drive —50—
*Note: Output clocks less than or equal to 100 MHz.
Si5351A/B/C-B
6 Rev. 1.0
Table 4. AC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Power-up Time TRDY
From VDD =V
DDmin to valid
output clock, CL=5pF,
fCLKn >1MHz —210ms
Power-up Time, PLL Bypa ss
Mode TBYP
From VDD =V
DDmin to valid
output clock, CL=5pF,
fCLKn >1MHz —0.5 1 ms
Output Enable Time TOE
From OEB pulled low to valid
clock output, CL=5pF,
fCLKn >1MHz ——10 µs
Output Frequency Transition
Time TFREQ fCLKn >1MHz — — 10 µs
Output Phase Offset PSTEP — 333 — ps/step
Spread Spectrum Frequency
Deviation SSDEV
Down spread. Selectable in 0.1%
steps. –0.1 — –2.5 %
Center spread. Selectable in
0.1% steps. ±0.1 — ±1.5 %
Spread Spectrum Modulation
Rate SSMOD 30 31.5 33 kHz
VCXO Specifications (Si5351B only)
VCXO Control Voltage Range Vc 0 VDD/2 VDD V
VCXO Gain (configurable) Kv Vc = 10–90% of VDD, VDD = 3.3 V 18 — 150 ppm/V
VCXO Control Voltage Linear ity KVL Vc = 10–90% of VDD –5 — +5 %
VCXO Pull Range
(configurable) PR VDD = 3.3 V* ±30 0 ±240 ppm
VCXO Modulation Bandwidth — 10 — kHz
*Note: Contact Silicon Labs for 2.5 V VCXO operation.
Table 5. Input Clock Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Crystal Frequency fXTAL 25 — 27 MHz
CLKIN Input Low Voltage VIL –0.1 — 0.3 x VDD V
CLKIN Input High Voltage VIH 0.7 x VDD —3.60V
CLKIN Frequency Range fCLKIN 10 — 100 MHz
Si5351A/B/C-B
Rev. 1.0 7
Table 6. Output Clock Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Frequency Range1FCLK 0.0025 — 200 MHz
Load Capacitance CL——15pF
Duty Cycle DC
FCLK < 160 MHz, Measured
at VDD/2 45 50 55 %
FCLK > 160 MHz, Measured
at VDD/2 40 50 60 %
Rise/Fall Time tr20%–80%, CL=5pF,
Default high drive strength —11.5ns
tf—11.5ns
Output High Voltage VOH CL=5pF VDD – 0.6 — — V
Output Low Voltage VOL ——0.6V
Period Jitter2,3 JPER
20-QFN, 4 outp uts runnin g,
1 per VDDO —4095
ps, pk-
pk
10-MSOP or 20-QFN,
all outputs running — 70 155 ps, pk-
pk
Cycle-to-Cycle Jitter2,3 JCC
20-QFN, 4 outp uts runnin g,
1 per VDDO —5090ps, pk
10-MSOP or 20-QFN,
all outputs running — 70 150 ps, pk
Period Jitter VC XO2,3 JPER_VCXO
20-QFN, 4 outp uts runnin g,
1 per VDDO —5095
ps, pk-
pk
10-MSOP or 20-QFN,
all outputs running — 70 155 ps, pk-
pk
Cycle-to-Cycle Jitter
VCXO2,3 JCC_VCXO
20-QFN, 4 outp uts runnin g,
1 per VDDO —5090ps, pk
10-MSOP or 20-QFN,
all outputs running — 70 150 ps, pk
Notes:
1. Only two unique frequencies above 112.5 MHz can be simultaneously output.
2. Measured over 10K cycles. Jitter is only specified at the default high drive strength (50 output impedance).
3. Jitter is highly dependent on device frequency configuration. Speci fica tions represent a “worst case, real world”
frequency plan; actual performance may be substantially better. Three-output 10 MSOP package measured with clock
outputs of 74.25, 24.576, and 48 MHz. Eight-output 20 QFN package measured with clock outputs of 33.333, 74.25,
27, 24.576, 22.5792, 28.322, 125, and 48 MHz.
Si5351A/B/C-B
8 Rev. 1.0
Table 7. Crystal Requirements1,2
Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL 25 — 27 MHz
Load Capacitance CL6—12pF
Equivalent Series Resistance rESR ——150
Crystal Max Drive Level dL100 — — µW
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF
capacitors on XA and XB).
2. Refer to “AN551: Crystal Selection Guide” for more details.
Table 8. I2C Specifications (SCL,SDA)1
Parameter Symbol Test Condition Standard Mode
100 kbps Fast Mode
400 kbps Unit
Min Max Min Max
LOW Level
Input Voltage VILI2C –0.5
0.3 x VDDI2
C –0.5 0.3 x VDDI2C2V
HIGH Level
Input Voltage VIHI2C 0.7 x VDDI2
C3.6 0.7 x VDDI2C23.6 V
Hysteresis of
Schmitt Trigger
Inputs VHYS ——0.1 —V
LOW Level
Output Voltage
(open drain or
open collector)
at 3 mA Sink
Current
VOLI2C2 V
DDI2C2= 2.5/3.3 V 0 0.4 0 0.4 V
Input Current III2C –10 10 –10 10 µA
Capacit ance for
Each I/O Pin CII2C V
IN = –0.1 to VDDI2C —4 — 4pF
I2C Bus
Timeout TTO Timeout Enabled 25 35 25 35 ms
Notes:
1. Refer to NXP’s UM10204 I2C-bus specification and user manual, revision 03, for further details, go to:
www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
2. Only I2C pullup voltages (VDDI2C) of 2.25 to 3.63 V are supported.
Si5351A/B/C-B
Rev. 1.0 9
Table 9. Thermal Characteristics
Parameter Symbol Test Condition Package Value Unit
Thermal Resistance
Junction to Ambient JA Still Air 10-MSOP 131 °C/W
20-QFN 119 °C/W
Thermal Resistance
Junction to Case JC Still Air 20-QFN 16 °C/W
Table 10. Absolute Maximum Ratings1
Parameter Symbol Test Condition Value Unit
DC Supply Voltage VDD_max –0.5 to 3.8 V
Input Voltage
VIN_CLKIN CLKIN, SCL, SDA –0.5 to 3.8 V
VIN_VC VC –0.5 to (VDD+0.3) V
VIN_XA/B Pins XA, XB –0.5 to 1.3 V V
Junction Temperature TJ–55 to 150 °C
Soldering Temperature (Pb-free
profile)2TPEAK 260 °C
Soldering Temperature Time at
TPEAK (Pb-free profile)2 TP20–40 Sec
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020.
Si5351A/B/C-B
10 Rev. 1.0
2. Detailed Block Diagrams
Figure 1. Block Diagrams of 3-Output and 8-Output Si5351A Devices
PLL
B
PLL
A
SDA
SCL
OSC
XA
XB
VDDO
R0
R1
CLK0
CLK1
R2 CLK2
M u ltiSynth
0
M u ltiSynth
1
M u ltiSynth
2
VDD
GND 10-MSOP
Si5351A 3-Output
R0
R1
CLK0
CLK1
VDDOA
R2
R3
CLK2
CLK3
VDDOB
R4
R5
CLK4
CLK5
VDDOC
R6
R7
CLK6
CLK7
VDDOD
M u ltiSyn th
0
M u ltiSyn th
1
M u ltiSyn th
2
M u ltiSyn th
3
M u ltiSynth
4
M u ltiSynth
5
M u ltiSynth
6
M u ltiSynth
7
VDD
GND 20-QFN
SCL
A0
SDA
Control
Logic
OEB
SSEN
I2C
Interface
Si5351A 8-Output
I2C
Interface
PLL
B
PLL
A
OSC
XA
XB
Si5351A/B/C-B
Rev. 1.0 11
Figure 2. Block Diagrams of Si5351B and Si5351C 8-Output Devices
OSC
XA
XB
PLL
VCXO
R0
R1
CLK0
CLK1
VDDOA
R2
R3
CLK2
CLK3
VDDOB
R4
R5
CLK4
CLK5
VDDOC
R6
R7
CLK6
CLK7
VDDOD
MultiSynth
0
MultiSynth
1
MultiSynth
2
MultiSynth
3
MultiSynth
4
MultiSynth
5
MultiSynth
6
MultiSynth
7
VC
VDD
GND
Si5351B
SCL
SDA
Control
Logic
OEB
SSEN
I2C
Interface
20-QFN
R0
R1
CLK0
CLK1
VDDOA
R2
R3
CLK2
CLK3
VDDOB
R4
R5
CLK4
CLK5
VDDOC
R6
R7
CLK6
CLK7
VDDOD
MultiSyn th
0
MultiSyn th
1
MultiSyn th
2
MultiSyn th
3
Mu ltiSynth
4
Mu ltiSynth
5
Mu ltiSynth
6
Mu ltiSynth
7
VDD
GND
Si5351C
PLL
A
PLL
B
XA
XB OSC
CLKIN
SCL
SDA
Control
Logic
INTR
OEB
I2C
Interface
20-QFN
Si5351A/B/C-B
12 Rev. 1.0
3. Functional Description
The Si5351 is a versatile I2C programmable clock generator that is ideally suited for replacing crystals, crystal
oscillators, VCXOs, PLLs, and buffers. A block diagram showing the general architecture of the Si5351 is shown in
Figure 3. The device consists of an input stage, two synthesis stages, and an output stage.
The input stage accepts an external crystal (XTAL), a control voltage input (VC), or a clock input (CLKIN)
depending on the version of the device (A/B/C). The first stage of synthesis multiplies the input frequencies to an
high-frequency intermediate clock, while the second stage of synthesis uses high resolution MultiSynth fractional
dividers to generate the desired output frequencies. Additional integer division is provided at the output stage for
generating output frequencies as low as 2.5 kHz. Crosspoint switches at each of the synthesis stages allows total
flexibility in routing any of the inputs to any of the outputs.
Because of this high resolution and flexible synthesis architecture, the Si5351 is capable of generating
synchronous or free-running non-integer related clock frequencies at each of its outputs, enabling one device to
synthesize clocks for multiple clock domains in a design.
Figure 3. Si5351 Block Diagram
Input
Stage Synthesis
Stage 1
PLL B
(VCXO)
PLL A
(SSC)
VC VCXO
XA
XB
OSC
XTAL
CLKIN Div
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
Multi
Synth
7
Synthesis
Stage 2
R0
R1
R2
R3
R4
R5
R6
R7
Output
Stage
CLK0
CLK1
VDDOA
CLK2
CLK3
VDDOB
CLK4
CLK5
VDDOC
CLK6
CLK7
VDDOD
Si5351A/B/C-B
Rev. 1.0 13
3.1. Input Stage
3.1.1. Crystal Inputs (XA, XB)
The Si5351 uses a fixed-frequency standard AT-cut crystal as a reference to the internal oscillator. The output of
the oscillator can be used to provide a free-running reference to one or both of the PLLs for generating
asynchronous clocks. Th e output frequency of the oscillator will operate at the crystal frequency, either 25 MHz or
27 MHz. The crystal is also used as a reference to the VCXO to help maintain its frequency accuracy.
Internal load capacitors are provided to eliminate the need for external components when connecting a crystal to
the Si5351. The total internal XTAL load capacitance (CL) can be selected to be 0, 6, 8, or 10 pF. Crystals with
alternate load capacitance requirements are supported using additional external load capacitance 2 pF (e.g., by
using 4 pF capacitors on XA and XB) as shown in Figure 4. Refer to application note AN551 for crystal
recommendations.
Figure 4. External XTAL with Optional Load Capacitors
3.1.2. External Clock Input (CLKIN)
The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs.
CLKIN can accept any frequency from 10 to 10 0 MHz. A divider at the input stage limits the PLL input frequency to
30 MHz.
3.1.3. Voltage Control Input (VC)
The VCXO architecture of the Si5351B eliminates the need for an external pullable crystal. Only a standard, low-
cost, fixed-frequency ( 25 or 27 MHz) AT-cut crystal is required.
The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the
VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and
reliable startup and operation. Refer to Table 4 on page 6 for VCXO specification details.
A unique feature of the Si5351B is its ability to generate multiple output frequencies controlled by the same control
voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
reference. An example is illustrated in Figure 5 on page 14.
XA
XB
Optional internal
load capacitance
0, 6, 8,10 pF
Optional additional
external load
capacitance
(< 2 pF)
Si5351A/B/C-B
14 Rev. 1.0
3.2. Synthesis Stages
The Si5351 uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply
the lower frequency input references to a high-frequency intermediate clock. The second stage uses high-
resolution MultiSynth fractional dividers to generate the required output frequencies. Only two unique frequencies
above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz
(CLKx) is not allowed. Note that multiple copies of frequencies above 112.5 MHz can be provided, for example,
125 MHz could be provided on four outputs (CLKS0-3) simultaneously with 130 MHz on four different outputs
(CLKS4-7).
A crosspoint switch at the input of the first stage allows each of the PLLs to lock to the CLKIN or the XTAL input.
This allows each of th e PLLs to lock to a dif ferent source fo r generatin g independen t free-run ning and synchrono us
clocks. Alternatively, both PLLs could lock to the same source. The crosspoint switch at the input of the second
stage allows any of the MultiSynth dividers to connect to PLLA or PLLB. This flexible synthesis architecture allows
any of the outputs to generate synchronous or non-synchronous clocks, with spread spectrum or without spread
spectrum, and with the flexibility of generating non-integer related clock frequencies at each output.
All VCXO outputs are generated by PLLB only. The Multisynth high-resolution dividers synthesizes the VCXO
output’s center frequency up to 112.5 MHz. The center frequency is then controlled (or pulled) by the VC input. An
interesting feature of the Si5351 is that the VCXO output can be routed to more than one MultiSynth divider. This
creates a VCXO with multiple output frequencies controlled from one VC input as shown in Figure 5.
Frequencies down to 2.5 kHz can be generated by applying the R divider at the output of the Multisynth (see
Figure 5 below).
Figure 5. Using the Si5351 as a Multi-Output VCXO
Si5351A/B/C-B
Rev. 1.0 15
3.3. Output Stage
An additional level of division ( R) is availab le a t th e outpu t st age fo r gener ating clocks as low as 2.5 kHz. All output
drivers generate CMOS level outputs with separate o utput volt age supply pins ( VDDOx) allowing a d iffer ent volt age
signal level (1.8, 2.5, or 3.3 V) at each of the four 2-output banks.
3.4. Spread Spectrum
Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is
useful for reducin g el ectromag netic interf er ence (EMI). E nabling sp read spectru m on a n output clo ck modulates its
frequency, which effectively reduces the overall amplitude of its radiated energy. Note that spread spectrum is not
available on clocks synchronized to PLLB or to the VCXO.
The Si5351 supports several levels of spread spectrum allowing the designer to chose an ideal compromise
between syste m pe rf or m an ce and EMI comp lia nce .
Figure 6. Available Spread Spectrum Profiles
3.5. Control Pins (OEB, SSEN)
The Si5351 offers control pins for enabling/disabling clock outputs and spread spectrum.
3.5.1. Output Enable (OEB)
The output enable pin allows enabling or disabling outputs clocks. Output clocks are enabled when the OEB pin is
held low, and disabled when pulled high. Wh en disabled, the output st ate is configurable as output high, output low,
or high-impedance.
The output enable control circuitry ensu res glitchless oper ation by st arting the outpu t clock cycle on the first leading
edge after OEB is pulled low. When OEB is pulled high, the clock is allowed to complete its full clock cycle before
going into a disabled st ate.
3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only
This control pin allows disabling the spread spectrum feature for all outputs that were configured with spread
spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient method of
evaluating the effect of using spread spectrum clocks during EMI compliance testing.
fc
Reduced
Amplitude
and EMI
Down Spread
fc
Reduced
Amplitude
and EMI
Center Spread
fc
No Spread
Spectrum
Center
Frequency
Amplitude
Si5351A/B/C-B
16 Rev. 1.0
4. I2C Interface
Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the
I2C interface. The following is a list of the common features that are controllable through the I2C interface. For a
complete listing of available I2C registers and programming steps, please see “AN619: Manually Generating an
Si5351 Register Ma p.”
Read Status Indicators
Crystal Reference Loss of signal, LOS_XTAL, reg0[3]
CLKIN Loss of signal , LO S_CLKIN, reg0[ 4]
PLLA and/or PLLB Loss of lock, LOL_A or LOL_B, reg0[6:5]
Configuration of multiplication and divider values for the PLLs, MultiSynth dividers
Configuration of the Spread Spectrum profile (down or center spread, modulation percentage)
Control of the cross point switch selection for eac h of the PLL s an d M ultiSynth dividers
Set output clock options
Enable/disable for each clock output
Invert/non-invert for each clock output
Output divider values (2n, n=1.. 7)
Output state when disabled (stop hi, stop low, Hi-Z)
Output phase offset
The I2C interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or
Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.
The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 7.
Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the
I2C specification.
Figure 7. I2C and Control Signals
The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed address plus a user selectable LSB bit as
shown in Figure 8. The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful for applica t ions that
require more than one Si5351 on a single I2C bus.
Figure 8. Si5351 I2C Slave Address
SCL
VDD
SDA
I2C Bus
INTR
A0
I2C Address Select:
Pull-up to VDD (A0 = 1)
Pull-down to GND (A0 = 0)
Si5351
>1k >1k
4.7 k
Slave Address 1 1 0 0 0 0 0/1
A0
0123456
Si5351A/B/C-B
Rev. 1.0 17
Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7-
bit device (sla ve) address + a write bit, a n 8-bit register address, and 8 bits of data as show n in Figure 9. A write
burst operation is also shown where every additional data word is written using to an auto-incremented address.
Figure 9. I2C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
Figure 10.
Figure 10. I2C Read Operation
AC and DC electrical specifications for the SCL and SDA pins are shown in Table 8. The timing specifications and
timing diagram for the I2C bus is compatible with the I2C-Bus Standard. SDA timeout is supported for compatibility
with SMBus interfaces.
1 – Read
0 – W rite
A – Acknowledge (SDA LO W )
N – Not Acknowledge (SDA HIGH)
S – START condition
P – ST OP c o n ditio n
From slave to master
From m aster to slave
W rite Operation – Single Byte
S 0 A R e g Addr [7 :0 ]Slv Addr [6:0] ADa ta [7:0 ] PA
W rite Operation - Burst (Auto Address Increment)
Reg Addr +1
S 0 A R e g Addr [7 :0 ]S lv A d d r [6 :0 ] ADa ta [7:0 ] ADa ta [7:0 ] PA
1 – Read
0 – W rite
A – Acknowledge (SDA LO W )
N – Not Acknowledge (SDA HIGH)
S – START condition
P – ST OP c o n ditio n
From slave to master
From m aster to slave
R e a d Ope r a tio n – S in g le Byte
S 0 A R e g Addr [7 :0 ]Slv Addr [6:0] A P
R e a d O p e r atio n - B u r s t (A u to A d dres s In c re men t)
Reg Addr +1
S 1 AS lv Ad dr [6:0 ] D a ta [7 :0 ] PN
S 0 A R e g Addr [7 :0 ]S lv A d d r [6 :0 ] A P
S 1 AS lv Ad dr [6:0 ] D a ta [7 :0 ] A PND ata [7 :0 ]
Si5351A/B/C-B
18 Rev. 1.0
5. Configuring the Si5351
The Si5351 is a highly flexible clock generator which is entirely configurable through its I2C interface. The device’s
default configuration is stored in non-volatile memory (NVM) as shown in Figure 11. The NVM is a one time
programmable memory (OTP) which can store a custom user configuration at power-up. This is a useful featu re for
applications that need a clock present at power-up (e.g., for providin g a clock to a pr oc es so r).
Figure 11. Si5351 Memory Configuration
During a power cycle the contents of the NVM are copied into random access memory (RAM), which sets the
device configuration that will be used during normal operation. Any changes to the device configuration after
power-up are made by reading and writing to registers in the RAM space through the I2C interface.
5.1. Writing a Custom Configuration to RAM
To simplify device configuration, Silicon Labs has released the ClockBuilder Desktop. The software serves two
purposes: to configure the Si5351 with optimal configuration based on the desired frequencies and to control the
EVB when connected to a host PC.
The optimal configuration can be saved from the software in text files that can be used in any system, which
configures the device over I2C. ClockBuilder Desktop can be downloaded from www.silabs.com/ClockBuilder and
runs on Windows XP, Windows Vista, and Windows 7.
Once the configuration file has bee n saved, the de vice can be pr ogram med via I 2C by following the steps shown in
Figure 12.
Power-Up
I2C
RAM
NVM
(OTP)
Def ault
Config
Si5351A/B/C-B
Rev. 1.0 19
Figure 12. I2C Programming Procedure
Disable Outputs
Set CLKx_DIS high; Reg. 3 = 0xFF
Powerdown all output drivers
Reg. 16, 17, 18, 19, 20, 21, 22, 23 =
0x80
Set inte rrupt masks
(see register 2 des cription)
Write new config uration to device using
the contents of the register map
generated by ClockBuilder Desktop. This
step also powers up the output drivers.
(Registers 15-92 and 149-170)
Apply PLLA and PLLB soft reset
Reg. 177 = 0xAC
Enable desired outputs
(see Register 3)
Use ClockBuilder
Desktop v 3.1 or later
Register
Map
, 149-1 70 and 183)
Si5351A/B/C-B
20 Rev. 1.0
5.2. Si5351 Application Examples
The Si5351 is a versatile clock generator which serves a wide variety of applications. The following examples show
how it can be used to replace crystals, crystal oscillators, VCXOs, and PLLs.
5.3. Replacing Crystals and Crystal Oscillators
Using an inexpensive external crystal, the Si5351A can generate up to 8 different free-running clock frequencies
for replacing crystals and crystal oscillators. A 3-output version packaged in a small 10-MSOP is also available for
applications that require fewer clocks. An example is shown in Figure 13.
Figure 13. Using the Si5351A to Replace Multiple Crystals, Crystal Oscillators, and PLLs
5.4. Replacing Crystals, Crystal Oscillators, and VCXOs
The Si5351B combines free-running clock generation and a VCXO in a single package for cost sensitive video
applications. An example is shown in Figure 14.
Figure 14. Using the Si5351B to Replace Crystals, Crystal Oscillators, VCXOs, and PLLs
48 MHz USB
Controller
28.322 MHz
125 MHz
Video/Audio
Processor
74.25/1 .001 MHz
24.576 MHz
OSC
XA
XB
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
PLL
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
74.25 MHz
27 MHz
Si5351A
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Mu lt i
Synth
7
HDMI
Port
Ethernet
PHY
Mu lt i
Synth
6
22.5792 MHz
CLK6
33.3333 MHz
CLK7 CPU
Note: Si5351A replaces crystals, X Os, and PLLs.
Ethernet
PHY
USB
Controller
HDMI
Port
28.322 MHz
48 MHz
125 MHz
Video/Audio
Processor
74.25/1.001 MHz
24.576 MHz
OSC
XA
XB
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
PLL
VCXO
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
74.25 MHz
VC
27 MHz
Si5351B
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Free-running
Clocks
VCXO Clock
Outputs
Note: FBW = 10 kHz
Si5351A/B/C-B
Rev. 1.0 21
5.5. Replacing Crystals, Crystal Oscillators, and PLLs
The Si5351C generates synchronous clocks for applications that require a fully integrated PLL instead of a VCXO.
Because of its dual PLL architecture, the Si5351C is capable of generating both synchronous and free-running
clocks. An example is shown in Figure 15.
Figure 15. Using the Si5351C to Replace Crystals, Crystal Oscillators, and PLLs
5.6. Applying a Reference Clock at XTAL Input
The Si5351 can be driven with a clock signal through the XA input pin. This is especially useful when in need of
generating clo ck outputs in two sync hronization doma ins. With the Si5351C, one reference clock can be provided
at the CLKIN pin and at XA.
Figure 16. Si5351 Driven by a Clock Signal
Ethernet
PHY
USB
Controller
HDMI
Port
28.322 MHz
48 MHz
125 MHz
Video/Audio
Processor
74.25/1.001 MHz
24.576 MHz
OSC
XA
XB
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
PLL
PLL
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
74.25 MHz
CLKIN
25 MHz
Si5351C
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
54 MHz
Free-running
Clocks
Synchronous
Clocks
Multi
Synth
N
Multi
Synth
0
Multi
Synth
1
PLLB
PLLA
XA
XB
OSC
VIN = 1 VPP
25/27 MHz
Note: Float the XB input while driving
the XA input with a clock
0.1 µF
Si5351A/B/C-B
22 Rev. 1.0
5.7. HCSL Compatible Outputs
The Si5351 can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is
set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB mus t be 2.5 V for CLK2/3 and so on).
The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair
must also be inverted to generate a differential pair. See register setting CLKx_INV.
Figure 17. Si5351 Output is HCSL Compatible
Multi
Synth
N
Multi
Synth
0
Multi
Synth
1
PLLB
PLLA
OSC
Note: The complementary -180 degree
out of phase output clock is generated
using the INV function
R1
511
240 R2
ZO = 50
0
HCSL
CLKIN
R1
511
240 R2
ZO = 50
0
Si5351A/B/C-B
Rev. 1.0 23
6. Design Considerations
The Si5351 is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure op timum pe rforman c e. Refer to “AN55 4: Si5350/51 PCB Layout Guide” for
additional layout recommendations.
6.1. Power Supply Decoupling/Filtering
The Si5351 has built-in power supply filtering circuitry and extensive internal Low Drop Out (LDO) voltage
regulators to help minimize the number of external bypass components. All that is recommended is one 0.1 to
1.0 µF decoupling capacitor per power supply pin. This capacitor should be mounted as close to the VDD and
VDDOx pins as possible without using vias.
6.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. Power supply sequencing for VDD and VDDOx requires that all VDDOx be
powered up either before or at the same time as VDD. Unused VDDOx pins should be tied to VDD.
6.3. External Crystal
The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
details.
6.4. External Crystal Load Capacitors
The Si5351 provides the option of using intern al and external cryst al load capacitors. If internal load capacit ance is
insufficient, capacitors of value < 2 pF may be used to increased equivalent load capacitance. If external load
capacitors are u sed, they should be pla ced as close to the XA/XB p ads a s possible. See “A N551: Cr yst al Sele ction
Guide” for more details.
6.5. Unused Pins
Unused voltage control pin should be tied to GND.
Unused CLKIN pin should be tied to GND.
Unused XA/XB pins should be left floating. Refer to "5.6. Applying a Reference Clock at XTAL Input" on page 21
when using XA as a clock input pin.
Unused output pins (CLK0–CLK7) should be left floating.
Unused VDDOx pins should be tied to VDD.
6.6. Trace Characteristics
The Si5351A/B/C features various output current drive strengths. It is recommended to configure the trace
characterist ics as sh own in Figure 18 when the default high driv e str en gt h is use d.
Figure 18. Recommended Trace Characteristics with Default Drive Strength Setting
ZO = 50 o hm s
CLK
(Op tional resistor for
EMI management)
R = 0 ohms
Si5351A/B/C-B
24 Rev. 1.0
7. Register Map Summary
For many applications, the Si5351's register values are easily configured using ClockBuilder Desktop software.
However, for customers interested in using the Si5351 in operating modes beyond the capabilities available with
ClockBuilder™, refer to “AN619: Manually Generating an Si5351 Register Map” for a detailed description of the
Si5351 registers and their usage.
8. Register Descriptions
Refer to “AN619: Manually Generating an Si5351 Register Map” for a detailed descri ption of Si5351 registers.
Si5351A/B/C-B
Rev. 1.0 25
9. Si5351 Pin Descriptions
9.1. Si5351A 20-pin QFN
Figure 19. Si5351A 20-QFN Top View
Table 11. Si5351A Pin Descriptions
Pin Name Pin
Number Pin Type1Function
XA 1 I Input pin for external crystal.
XB 2 I Input pin for external crystal.
CLK0 13 O Output clock 0.
CLK1 12 O Output clock 1.
CLK2 9 O Output clock 2.
CLK3 8 O Output clock 3.
CLK4 19 O Output clock 4.
CLK5 17 O Output clock 5.
CLK6 16 O Output clock 6.
CLK7 15 O Output clock 7.
A0 3 I I2C addr ess bit.
SCL 4 I I2C bus serial clock input. Pull-up to VDD core with 1 k
SDA 5 I/O I2C bus serial data input. Pull-up to VDD core with 1 k
SSEN 6 I Spread spectrum enable. High = enabled, Low = disabled.
OEB 7 I Output driver enable. Low = enabled, High = disabled.
VDD 20 P Core voltage su pply pin. See 6.2.
VDDOA 11 P Output voltage supply pin for CLK0 and CLK1. See 6.2.
VDDOB 10 P Output voltage supply pin for CLK2 and CLK3. See 6.2.
VDDOC 18 P Output voltage supply pin for CLK4 and CLK5. See 6.2.
VDDOD 14 P Output voltage supply pin for CLK6 and CLK7. See 6.2.
GND Center Pad P Ground. Use multiple vias to ensure a solid path to GND.
1. I = Input, O = Output, P = Power.
2. Input pins are not internally pulled up.
1
2
3
4
5
6
7
8
9
10
15
14
13
12
11
20
19
18
17
16
XA
XB
A0
SCL
SDA
OEB
CLK3
CLK2
VDDOB
SSEN
GND
PAD
CLK6
CLK5
VDDOC
CLK4
VDD
VDDOA
CLK1
CLK0
VDDOD
CLK7
Si5351A/B/C-B
26 Rev. 1.0
9.2. Si5351B 20-Pin QFN
Figure 20. Si5351B 20-QFN Top View*
Table 12. Si5351B Pin Descriptions
Pin Name Pin
Number Pin Type1Function
XA 1 I Input pin for external crystal
XB 2 I Input pin for external crystal
CLK0 13 O Output clo ck 0
CLK1 12 O Output clo ck 1
CLK2 9 O Output clock 2
CLK3 8 O Output clock 3
CLK4 19 O Output clo ck 4
CLK5 17 O Output clo ck 5
CLK6 16 O Output clo ck 6
CLK7 15 O Output clo ck 7
VC 3 I VCXO control voltage input
SCL 4 I I2C bus serial clock input. Pull-up to VDD core with 1 k
SDA 5 I/O I2C bus serial data input. Pull-up to VDD core with 1 k
SSEN 6 I Spread spectrum enable. High = enabled, Low = disabled.
OEB 7 I Output driver enable. Low = enabled, High = disabled.
VDD 20 P Cor e voltage supply pin
VDDOA 11 P Output voltage supply pin for CLK0 and CLK1. See 6.2
VDDOB 10 P Output voltage supply pin for CLK2 and CLK3. See 6.2
VDDOC 18 P Output voltage supply pin for CLK4 and CLK5. See 6.2
VDDOD 14 P Output voltage supply pin for CLK6 and CLK7. See 6.2
GND Center Pad P Ground
1. I = Input, O = Output, P = Power
2. Input pins are not internally pulled up.
1
2
3
4
5
6
7
8
9
10
15
14
13
12
11
20
19
18
17
16
XA
XB
VC
SCL
SDA
OEB
CLK3
CLK2
VDDOB
SSEN
GND
PAD
CLK6
CLK5
VDDOC
CLK4
VDD
VDDOA
CLK1
CLK0
VDDOD
CLK7
Si5351A/B/C-B
Rev. 1.0 27
9.3. Si5351C 20-Pin QFN
Table 13. Si5351C Pin Descriptions
Pin Name Pin
Number Pin Type1Function
20-QFN
XA 1 I Input pin for external crystal.
XB 2 I Input pin for external crystal.
CLK0 13 O Output clock 0.
CLK1 12 O Output clock 1.
CLK2 9 O Output clock 2.
CLK3 8 O Output clock 3.
CLK4 19 O Output clock 4.
CLK5 17 O Output clock 5.
CLK6 16 O Output clock 6.
CLK7 15 O Output clock 7.
INTR 3 O Interrupt pin. Open drain active low output, requires a pull-up
resistor greater than 1 k
SCL 4 I I2C bus serial clock input. Pull-up to VDD core with 1 k 
SDA 5 I/O I2C bus serial data input. Pull-up to VDD core with 1 k
CLKIN 6 I PLL clock input.
OEB 7 I Output driver enable. Low = enabled, High = disabled.
VDD 20 P Cor e voltage supply pin
VDDOA 11 P Output voltage supply pin for CLK0 and CLK1. See 6.2
VDDOB 10 P Output voltage supply pin for CLK2 and CLK3. See 6.2
VDDOC 18 P Output voltage supply pin for CLK4 and CLK5. See 6.2
VDDOD 14 P Output voltage supply pin for CLK6 and CLK7. See 6.2
GND Center Pad P Ground.
Notes:
1. I = Input, O = Output, P = Power.
2. Input pins are not internally pulled up.
1
2
3
4
5
6
7
8
9
10
15
14
13
12
11
20
19
18
17
16
XA
XB
INTR
SCL
SDA
OEB
CLK3
CLK2
VDDOB
CLKIN
GND
PAD
CLK6
CLK5
VDDOC
CLK4
VDD
VDDOA
CLK1
CLK0
VDDOD
CLK7
Si5351A/B/C-B
28 Rev. 1.0
9.4. Si5351A 10-Pin MSOP
Figure 21. Si5351A 10-MSOP Top View
Table 14. Si5351A 10-MSOP Pin Descriptions
Pin Name
Pin
Number Pin Type* Function
10-MSOP
XA 2 I Input pin for external crystal.
XB 3 I Input pin for external crystal.
CLK0 10 O Output clock 0.
CLK1 9 O Output clock 1.
CLK2 6 O Output clock 2.
SCL 4 I Serial clock input for the I2C bus. This pin must be pulled-up using a pull-
up resistor of at least 1 k.
SDA 5 I/O Serial data input for the I 2C bus. This pin must be pulled -up using a pull-up
resistor of at least 1 k.
VDD 1 P Core voltage supply pin.
VDDO 7 P Output voltage supply pin for CLK0, CLK1, and CLK2. See "6.2. Power
Supply Sequencing" on page 23.
GND 8 P Ground.
*Note: I = Input, O = Output, P = Power
XA
VDD
SCL
XB
2
1
4
3
CLK1
CLK0
VDDO
GND
9
10
7
8
SDA 5CLK2
6
Si5351A/B/C-B
Rev. 1.0 29
10. Ordering Information
Factory pre-programmed Si5351 devices (e.g., with bootup frequencies) can be requested using the ClockBuilder
web-based utility available at: www.silabs.com/ClockBuilder. A unique part number is assigned to each custom
configuration as indicated in Figure 22. Blank, un-programmed Si5351 devices (with no boot-up frequency) do not
contain a custom code.
Figure 22. Device Part Numbers
An evaluation kit containing ClockBuilder Desktop software and hardware enable easy evaluation of the Si5351A/B/
C. The orderable part numbers for the evaluation kits are provided in Figure 23.
Figure 23. Si5351A/B/C Evaluation Kit
Si5351A/B/C-B
30 Rev. 1.0
11. Package Outlines
Figure 24 shows the package details for the Si5351 in a 20-QFN package. Table 15 lists the values for the
dimensions shown in the illustration.
11.1. 20-pin QFN
Figure 24. 20-pin QFN Package Drawing
BD
E
A
A1
e
b
Seating Plane
L
D2
E2
D2/2
E2/2
C
A
Si5351A/B/C-B
Rev. 1.0 31
Table 15. Package Dimensions
Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 — 0.05
b 0.20 0.25 0.30
D 4.00 BSC
D2 2.65 2.70 2.75
e 0.50 BSC
E 4.00 BSC
E2 2.65 2.70 2.75
L 0.35 0.40 0.45
aaa — — 0.10
bbb — — 0.10
ccc — — 0.08
ddd — — 0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MO-220, variation VGGD-5.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Si5351A/B/C-B
32 Rev. 1.0
12. Land Pattern: 20-Pin QFN
Figure 25 shows the recommended land pattern details for the Si5351 in a 20-Pin QFN package. Table 16 lists the
values for the dimensions shown in the illustration.
Figure 25. 20-Pin QFN Land Pattern
Si5351A/B/C-B
Rev. 1.0 33
Table 16. PCB Land Pattern Dimensions
Symbol Millimeters
C1 4.0
C2 4.0
E 0.50 BSC
X1 0.30
X2 2.70
Y1 0.80
Y2 2.70
Notes:
General
1. All dimensions shown are in millimeters
(mm) unless otherwise noted.
2. This land pattern design is based on IPC-
7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask
defined (NSMD). Clearance between the
solder mask and the metal pad is to be
60 µm minimum, all the way around the pad.
Stencil D es ign
4. A stainless steel, laser-cut and electro-
polished stencil with trapezoidal walls should
be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm
(5 mils).
6. The ratio of stencil aperture to land pad size
should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 x 1.10 mm openings on
1.30 mm pitch should be used for the center
ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is
recommended.
9. The recommended card reflow profile is per
the JEDEC/IPC J-STD-020 specification for
Small Body components.
Si5351A/B/C-B
34 Rev. 1.0
12.1. 10-Pin MSOP Package Outline
Figure 26 illustrates the package details for the Si5351 in a 10-pin MSOP p ackage. Table 17 lists th e values for the
dimensions shown in the illustration.
Figure 26. 10-pin MSOP Package Drawing
Si5351A/B/C-B
Rev. 1.0 35
Table 17. 10-MSOP Package Dimensions
Dimension Min Nom Max
A——1.10
A1 0.00 — 0.15
A2 0.75 0.85 0.95
b 0.17 — 0.33
c 0.08 — 0.23
D 3.00 BSC
E 4.90 BSC
E1 3.00 BSC
e 0.50 BSC
L 0.400.600.80
L2 0.25 BSC
q0—8
aaa — — 0.20
bbb — — 0.25
ccc — — 0.10
ddd — — 0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioni ng and Tolerancing per ANSI Y14.5M-1994.
3. This drawing co nforms to the JEDEC Solid State Outline MO-137, Variation C
4. Recommended card reflow profile is per th e JEDEC/IPC J-STD-020 specification for Small Body
Components.
Si5351A/B/C-B
36 Rev. 1.0
13. Land Pattern: 10-Pin MSOP
Figure 27 shows the recommended land pattern details for the Si5351 in a 10-Pin MSOP package. Table 18 lists
the values for the dimensions shown in the illustration.
Figure 27. 10-Pin MSOP Land Pattern
Si5351A/B/C-B
Rev. 1.0 37
Table 18. PCB Land Pattern Dimensions
Symbol Millimeters
Min Max
C1 4.40 REF
E 0.50 BSC
G1 3.00 —
X1 — 0.30
Y1 1.40 REF
Z1 — 5.80
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication
Allowance of 0.05mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-
020C specification for Small Body components.
Si5351A/B/C-B
38 Rev. 1.0
14. Top Marking
14.1. 20-Pin QFN Top Marking
Figure 28. 20-Pin QFN Top Marking
14.2. Top Marking Explanation
Mark Method: Laser
Pin 1 Mark: Filled Circle = 0.50 mm Diameter
(Bottom-Left Corner)
Font Size: 0.60 mm (24 mils)
Line 1 Mark Format Device Part Number Si5351
Line 2 Mark Format: TTTTTT = Mfg Code* Manufacturing Code from the Assembly Purchase
Order Form.
Line 3 Mark Format: YY = Year
WW = Work Week Assigned by the Assembly House. Cor responds to
the year and work week of the assembly date.
*Note: The code shown in the “TTTTTT” line does not correspond to the orderable part number or frequency plan. It is used
for package assembly quality tracking purposes only.
Si5351A/B/C-B
Rev. 1.0 39
14.3. 10-Pin MSOP Top Marking
Figure 29. 10-Pin MSOP Top Marking
14.4. Top Marking Explanation
Mark Method: Laser
Pin 1 Mark: Mold Dimple (Bottom-Left Corner)
Font Size: 0.60 mm (24 mils)
Line 1 Mark Format Device Part Number Si5351
Line 2 Mark Format: TTTT = Mfg Code* Line 2 from the “Markings” section of the Assemb ly
Purchase Order form.
Line 3 Mark Format: YWW = Date Code Assigned by the Assembly House.
Y = Last Digit of Current Year (Ex: 2013 = 3)
WW = Work Week of Assembly Date.
*Note: The code shown in the “TTTT” line does not correspond to the orderable part number or frequency plan. It is used for
package assembly quality tracking purposes only.
Si5351A/B/C-B
40 Rev. 1.0
DOCUMENT CHANGE LIST
Revision 0.75 to Revision 1.0
Extended frequency range from 8 MHz-160 MHz to
2.5 kHz-200 MHz.
Updated block diagrams for clarity.
Added complete Si5350/1 family table, Table 1.
Added top mark info rm at ion .
Added land pattern dr awings.
Added PowerUp Time, PLL Bypass mode, Table 4.
Clarified Down Spread step sizes in Table 4.
Updated max jitter specs (typ unchanged) in Table 6.
Clarified power supply sequencing requirement,
Section 6.2.
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
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circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
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