IMI145158 FREQUENCY SYNTHESIZER
Preliminary
CMOS LSI
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.2 9/3/98
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Page 1 of 10
PRODUCT DESCRIPTION
The IMI145158 is a member of a family of phaselock loop
synthesizer ICs from International Microcircuits. This part is a
single PLL in a small package for low cost VHF applications.
The IMI145158 is programmed with standard 3-wire serial
lines: data, clock, and enable.
Blocks in the IMI145158 include a dual modulus feedback
divider for control of an external dual modulus prescaler.
Prescaler ratios up to 128:129. Also included are an “N”
counter, reference divider, phase detector, and charge
pump. The reference divider is programmable from 1 to
16383. Both divider inputs are biased for high sensitivity to
sinewave input signals, and the reference divider input can
be configured to operate as a crystal oscillator if desired. A
buffered reference signal output is also provided. The phase
detector is a Type IV phase-frequency design, which has
inherently eliminated the “dead zone” crossover distortion.
The loop error signal is provided by both a single-ended
charge pump output and standard differential logic outputs.
Performance improvements of the IMI145158 over other
single loop CMOS PLL devices are in the operating
bandwidth and phase detector noise floor. W ith its extremely
low phase noise floor and wider input bandwidth, prescaler
ratios can be minimized to allow wide loop bandwidths for
faster settling and lower phase noise.
PRODUCT FEATURES
>145 MHz typical input frequency.
-160 dBc/Hz total phase detector noise floor.
No dead zone by design.
Two phase detector outputs:
Current mode charge pump
Differential logic
Unambiguous PLL acquisition.
3-line serial programming: data, clock, & enable.
Compatible with the SPI (Serial Peripheral
Interface) on CMOS MCUs.
10-bit N counter: Divider range = 1 to 1023.
7-bit A counter: Divider range = 0 to 127.
14-bit R counter: Divider range = 1 to 16383.
On- or off-chip reference oscillator operation.
Buffered & filtered ref output is provided.
Packaging options: 16 PDIP or 16 SOIC or 20
PLCC.
BLOCK DIAGRAM
14 Bit Shift Register
14 Bit Latch
14 Bit /R Counter
Control Logic
7 Bit /A Counter 10 Bit /N Counter
7 Bit Latch 10 Bit Latch
7 Bit Shift Register 10 Bit Shift Register
1-Bit
Contro
l S/R
2 312
1
1
2
14
8
11
10
9
32
1
Lock
Detect
Phase
Detector
A
Phase
Detector
B
VDD = PIN 4
VSS = PIN 6
7
13
5
16
15
3
12
OSCin
OSCout
REFout
Fin
Enable
Data
Clock
LD
Fr
PDout
Phir
Phiv
Fv
Mod
Cntrl
IMI145158
FREQUENCY SYNTHESIZER
Preliminary
CMOS LSI
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.2 9/3/98
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Page 2 of 10
MAXIMUM RATINGS
Voltage Relative to VSS: -0.3V to 7V
Voltage Relative to VDD 0.3V
Storage Temperature: -65ºC to 150ºC
Ambient Temperature: -40ºC to 85 ºC
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)< VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
PIN DESCRIPTIONS
Pin Number Name Description
1Xin Xtal in (or reference signal input ) to the reference oscillator / buffer.
2Xout Xtal out (or Reference signal output ) of the reference oscillator / buffer.
14 REFout Buffered reference signal.
10 DATA Positive logic shift register input data. The first 14 bits are the reference or
feedback divider programming information, sent MSB first. The final programming
bit (control bit) selects which divider this programming information will be loaded
into:
1 = the reference divider, and 0 = the feedback divider.
÷ A and÷ N Entry Format (Control Bit = 0)
÷ A Counter Bits ÷ N Counter Bits
Last Data Bit In
(
Bit No. 18
)
First Data Bit in (Bit No. 1)
IMI145158 FREQUENCY SYNTHESIZER
Preliminary
CMOS LSI
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.2 9/3/98
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Page 3 of 10
PIN DESCRIPTIONS (continued)
Pin Number Name Description
9CLOCK On each low-to-high transition, clocks one bit into the on-chip shift register from
the data input.
11 ENABLE This signal, when HIGH, latches the information in the shift register into the
selected divider.
12 Mod Cntrl This output generates a signal by the on-chip control logic circuitry for controlling
an external dual-modulus prescaler.
8fin Feedback divider input signal. Applied to the positive edge triggered counter, this
signal is intended to be AC coupled. For CMOS logic level input signals, DC
coupling can be used.
4VDD Circuit positive power supply.
6VSS Circuit ground.
5PDout Single-ended charge pump output, usually used with passive loop filters. This
signal operated according to this table:
Frequency fv > fr at the phase detector: negative pulses.
Frequency fv < fr at the phase detector: positive pulses.
Frequency fv = fr at the phase detector: high-impedance state.
16 φR Phase detector output. This signal goes LOW when the feedback frequency is
too low.
15 φV Phase detector output. This signal goes LOW when the feedback frequency is
too high.
7LD Lock detect output. When the PLL is locked, this signal will be essentially HIGH,
with very narrow negative spikes at the phase detection frequency. If the PLL is
out of lock, this signal will pulse LOW.
3fv Output of the feedback divider N.
13 fr Output of the reference divider R.
Last Data Bit In
(
Bit No. 15
)
First Data Bit in
(
Bit No. 1
)
÷ R Counter Bits
IMI145158
FREQUENCY SYNTHESIZER
Preliminary
CMOS LSI
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.2 9/3/98
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Page 4 of 10
PLL OPERATING CHARACTERISTICS
VDD = 5 VOLTS
-40ºC 25ºC 85ºC
Characteristics Symbol Min Max Min Typ Max Min Max Unit Conditions
Max Operating fin, Sine* 160 typ
225 120 170 110 typ
155 MHz + 4 dBm
1.0V p-p
Frequency fosc Sine* 75 typ
105 85 120 55 typ 80 MHz +4 of Bm
1.0 V p-p
Modulus Control P rop. Del ay MCpd - 10 - 7.5 10.5 - 12 ns
Dynamic Synthesizer P hase Noise
Floor PDNF -
160 dBc/Hz @100kHz
Pin Cin - 6 - 4 6 - 6 pF
Capacitances Cout - 8 - 6 8 - 8 pF
Phase Det 1 gai n Kd - - 0.65 - ma/ Rad
Phase Det 2 gai n Kd - - 0.8 - v / Rad
Input VIL 1 1.5 - 2.75 1.5 - 1.5 Vdc
Voltages VIH 3.5 - 4.95 5.0 - 3.5 -
Output VOL - 0.05 - 0.0 0.05 - 0.05 Vdc
Voltages VOH 4.95 - 4.95 5.0 - 4.95 -
IOL Logic 2.4 - 2.0 2.8 - 1.6 -
Static Output OSCout 1.2 - 1.0 1.4 - 0.8 - mA VOL = 0.40
Current IOH Logic -2.4 - -2.0 -2.8 - -1.6 - mA VOH = 4. 0
OSCout -1.2 - -1.0 -1.4 - -0.8 - mA VOH = 4.4
Icp CPcur 4.0 mA for 2Pi Radians
Supply IDD mA fosc=fin-10 MHz
Currents ISB - 150 - 40 150 - 150 µA fosc=fin=0
IPU 50 µA VIL = 0
* Sine wave input is not recomended below 10 MHz.
IMI145158 FREQUENCY SYNTHESIZER
Preliminary
CMOS LSI
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.2 9/3/98
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Page 5 of 10
PLL OPERATING CHARACTERISTICS
VDD = 3 VOLTS
-40ºC 25ºC 85ºC
Characteristics Symbol Min Max Min Typ Max Min Max Unit Conditions
Max Operating fin, Sine* 100 80 115 70 MHz +4 dBm
1.0V p-p
Frequency fosc S i ne* 60 65 95 50 MHz +4 dB m
1.0V p-p
Modulus Control P rop. Del ay MCpd - 12 - 11 15 - 17 ns
Dynamic Synthesizer P hase Noise
Floor PDNF -
160 dBc/Hz
Pin Cin - 10 - 6 10 - 10 pF
Capacitances Cout - 10 - 6 10 - 10 pF
Phase Det 1 gai n Kd - - 0.3
5-ma/Ra
d
Phase Det 2 gai n Kd - - 0.4
8- v / Rad
Input VIL - .0.9 - 1.3
50.9 - 0.9 Vdc
Voltages VIH 2.1 - 2.1 1.6
5-2.1-
Output VOL - 0.05 - 0.0 0.05 - 0.05 Vdc
Voltages VOH 2.95 - 2.95 3.0 - 2.95 -
IOL Logic 1.6 - 1.4 2.0 - 0.8 -
Static Output OSCout 0.8 - 0.7 1.0 - 0.4 - mA VOL = 0.30
Current IOH Logic -1.6 - -1.4 -2.0 - -0.8 - mA VOH = 2.4
OSCout -0.8 - -0.7 -1.0 - -0.4 - mA VOH = 2.4
Icp CP cur 2.2 mA for 2Pi Radian
Supply IDD mA fosc=fin-10
MHz
Currents ISB - 150 - 40 150 - 150 µA fosc=fin=0
* Sine wave input is not recomended below 10 MHz.
IMI145158
FREQUENCY SYNTHESIZER
Preliminary
CMOS LSI
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.2 9/3/98
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Page 6 of 10
IMI145158 Typical Current Vs
F
0.00
5.00
10.00
15.00
20.00
25.00
10 30 50 70 90 110 130 150 170 190
Frequency in MHz.
Cu rrent in M a.
5V Min Sig
5V Max Sig
3V Min Sig
3V Max Sig
IMI145158 Typical RF S ensivity Vdd = 3V
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0 20 40 60 80 100 120 140
-40 3V
25° 3V
85° 3V
Frequency MHz
IMI145158 Typical RF Sensitivity Vdd = 5V
-35
-30
-25
-20
-15
-10
-5
0
0 50 100 150 200 250
Frequency MHz
dBm
-40 5V
25° 5V
85° 5V
IMI145158 Typi cal Reference Sensitivity V dd = 3V
-35
-30
-25
-20
-15
-10
-5
0
5
0 20 40 60 80 100 120
Frequency MHz
dBm
-40 3V
25° 3V
85° 3V
145158 Typical Reference Sensi ti vi ty V dd = 5V
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
0 20 40 60 80 100 120 140 160 180 200
Fre
q
uenc
y
MHz
dBm
-40 5V
25° 5V
85° 5V
IMI145158 FREQUENCY SYNTHESIZER
Preliminary
CMOS LSI
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.2 9/3/98
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Page 7 of 10
DUAL MODULUS PRESCALING
Dual Modulus prescaling is a wide spread method used to
effectively extend the operating frequency of a digital counter
without sacrificing any frequency resolution. The key to
understanding this method is to remember the basics of division:
W hen any t wo integers are divi ded, a quot ient and a rem ai nder will
result.
W hen used here in a PLL, the numerator is the required PLL total
feedback divider ratio, called Ntot. The denominator is the base
modulus of the dual modulus prescal er, P. The quot ient is applied
directly to the N counter, and the remainder is applied directly to
the A counter. Both counters count down together toward zero.
While the A counter counts, the MC (modulus control) output
signal is LOW , setti ng the prescaler to di vide by P + 1. W hen t he
A counter reaches zero, the MC output is set HIGH while the N
counter continues to count down to zero. When the N counter
reaches zero, both counters are reset to the programmed inputs
and the cycl e i s repeated.
Two particular things should be noticed about this process. First,
the remainder counts are spread among an equal number of
quotient c ounts by the use of t he prescaler modulus P +1. W hen
the remainder has been counted, any rem aining quot ient count s are
handled normal ly by prescaling by m odulus P. This c ounter is thus
performing
Ntot = A(P+1) + (N-A)P
Some al gebra on this relation yields
Ntot = AP+A + NP-AP
= NP + A
which is just the definition of integer division. Second, for this to
work, there must be m ore quotient count s t han rem ainder c ounts for
all poss ible values of Ntot i n the synthesizer design. I f this were not
true, then the N count er will reach zero and cause the entire divider
to be reset before the A counter is finished. There is a minimum
value for Ntot for which this requirement will always hold:
Ntot > P2 - P.
PROGRAMMING GUIDELINES APPLICABLE TO THE IMI145158
The system total divide value (Ntotal) will be dictated by the
application: frequency i nto the pres caler
frequency int o the phase detector
N is the num ber programm ed into the ÷ N counter; A i s the number
programmed into ÷ A counter. P and P + 1 are two selectable
divide ratios available in the two modulus prescalers. To have a
range of Ntotal values in sequence, the ÷ A counter is programmed
from zero through P-1 for a parti cular value N i n the ÷ N counter. N
is then increm ented to N + 1k, and the ÷ A is s equenced from zero
through P - 1 again.
To maximize system frequency capability, the dual modulus
prescaler’ s output mus t go from low to high aft er each group of P or
P + 1 input cycles. The prescaler should divide by P when its
modulus control line i s high, and by P + 1 when it s m odulus cont rol
is low.
For the maximum frequency into the prescaler (FVCO max), the
value used for P must be large enough so t hat :
A. FVCO max divided by P may not exceed the frequency
capability of P in 8 of the IMI145158.
B. The period of FVCO divided by P m ust be greater than the sum
of the ti mes:
a. Propagation delay t hrough the dual m odul us prescal er.
b. Prescaler setup or release time relative to its modulus
control signal.
c. Propagati on tim e from f in to the modulus control s i gnal .
A useful simplification in the IMI145158 programming code can be
achieved by choosing the values for P or 8, 16, 32, or 64, or 128.
For these c ases, the des ired value for Ntotal in binary is used as the
program c ode t o the ÷ A counters in t he following manner:
A. Assume the ÷ N counter and ÷ A counter contains “b” bits
where 2b = P.
B. Always program all higher order ÷ A counter bits above “b” to
zero.
C. Assume the ÷ N counter and ÷ A counter (with all the higher
order bits above “b” ignored) combined into a single binary
counter of 10+b bits in length. The MSB of this hypothetical
counter is to correspond o t he LSB of ÷ A. The system divide
value, Ntotal, now results when the value of Ntotal in binary is
used to program the “new” 10+b bit counter.
Ntotal == N*P+A
IMI145158
FREQUENCY SYNTHESIZER
Preliminary
CMOS LSI
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.2 9/3/98
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Page 8 of 10
CONNECTION DIAGRAM
SOIC AND PDIP PACKAGE PLCC PACKAGE
DATA
CLOCK
NC
fin
LD
18
17
16
15
14
f V
f R
NC
Xin
Xout
fv
VDD
NC
PDout
VSS
REFout
f
R
NC
Mod Cntrl
ENABLE
19
20
1
2
3
4
5
6
7
8
13
12
11
10
9
Pin No. 1
Index
TYPICAL APPLICATION CIRCUIT
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1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Xin
Xout
Fv
VDD
PDout
VSS
LD
fin
φ R
φ V
REFout
Fr
Mod Cntrl
ENABLE
DATA
CLOCK
IMI145158 FREQUENCY SYNTHESIZER
Preliminary
CMOS LSI
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.2 9/3/98
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Page 9 of 10
PACKAGE DRAWING AND DIMENSIONS
.
045 X 45 DEG
CHAMFER
A
Q
a
E
2
b
1
b
1
E
D
E
1
D
1
PIN 1 IDENT.
.070 DIA X .023 DP
.045 X 45 DEGREE
CORNER CHAMFER
b
e
20-PIN PLCC DIMENSIONS
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A0.147 .152 0.157 3.733 3.86 3.987
b0.003 0.007 0.011 0.076 0.177 0.279
b10.026 0.029 0.032 0.660 0.736 0.812
D0.385 0.390 0.395 9.779 9.906 10.033
D10.385 0.390 0.395 9.779 9.906 10.033
E0.343 0.348 0.353 8.712 8.839 8.966
E10.343 0.348 0.353 8.712 8.839 8.966
E20.310 0.320 0.330 7.874 8.128 8.382
e.050 BSC 1.27 BSC
a5°7°9°5°7°9°
Q0.0085 0.010 0.0115 0.216 .0.254 0.292
16-PIN PLASTIC DIP DIMENSIONS
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A0.150 0.160 0.170 3.81 4.06 4.318
A10.015 - - 0.381 - -
B0.016 0.018 0.020 0.40 0.45 0.50
B10.056 0.059 0.062 1.47 1.52 1.57
B20.046 0.049 0.052 1.17 1.24 1.32
C0.008 0.010 0.012 0.20 0.25 0.30
D0.748 0.750 0.752 19.00 19.05 19.10
E0.300 0.312 0.325 7.62 7.924 8.255
E10.240 0.252 0.260 6.096 6.49 6.604
E20.335 0.345 0.355 8.51 8.76 9.01
e10.100 BSC 2.54 BSC
L0.25 0.230 0.135 3.175 3.30 3.429
a0°7°15°0°7°15°
Q10.059 0.060 0.061 1.50 1.53 1.55
Q20.128 0.130 0.132 3.25 3.30 3.35
S0.073 0.075 0.077 1.85 1.90 1.95
E2
C
a
EE1
D
A1 A
L
B
B1
e1
S
QQ2 B2
IMI145158
FREQUENCY SYNTHESIZER
Preliminary
CMOS LSI
SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev 1.2 9/3/98
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Page 10 of 10
PACKAGE DRAWING AND DIMENSIONS
16 PIN SOIC DIMENSIONS
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A 0.097 0.101 0.104 2.46 2.56 2.64
A10.0050 0.009 0.0115 0.127 0.22 0.29
A2 0.090 0.092 0.094 2.29 2.34 2.39
B 0.014 0.016 0.019 0.35 0.41 0.48
C 0.0091 0.010 0.0125 0.23 0.25 0.32
D 0.402 0.407 0.412 10.21 10.34 10.46
E 0.292 0.296 0.299 7.42 7.52 7.59
e 0.050 BS C 0.127 BSC
H 0.400 0.406 0.410 10.16 10.31 10.41
L 0.024 0.032 0.040 0.61 0.81 1.02
a0º5º8º0º5º8º
ORDERING INFORMATION
Part Number Package Type Production Flow
IMI145158FPB 16 PIN Plastic Dip Industrial, -40°C to +85°C
IMI145158FXB 16 PIN SOIC Industrial, -40°C to +85°C
IMI145158FQB 20 PIN PLCC Industrial, -40°C to +85°C
* Please contact factory for other options.
Note: The “x” following the IMI Device Number denotes the device revision. The ordering part number is formed by a
combination of device number, device revision, package style, and screening as shown below.
Marking: Example:IMI
145158FPB
Date Code, Lot #
IMI145158FPB Flow
B = Industrial, -40°C to +85°C
Package
P = Plastic Dip
X = Small Outline
Q = PLCC
Revision
IMI Device Number
Be
A
A1
A2
E
H
a
L
C
D