IMI145158 FREQUENCY SYNTHESIZER Preliminary CMOS LSI SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER PRODUCT DESCRIPTION PRODUCT FEATURES The IMI145158 is a member of a family of phaselock loop synthesizer ICs from International Microcircuits. This part is a single PLL in a small package for low cost VHF applications. The IMI145158 is programmed with standard 3-wire serial lines: data, clock, and enable. Blocks in the IMI145158 include a dual modulus feedback divider for control of an external dual modulus prescaler. Prescaler ratios up to 128:129. Also included are an "N" counter, reference divider, phase detector, and charge pump. The reference divider is programmable from 1 to 16383. Both divider inputs are biased for high sensitivity to sinewave input signals, and the reference divider input can be configured to operate as a crystal oscillator if desired. A buffered reference signal output is also provided. The phase detector is a Type IV phase-frequency design, which has inherently eliminated the "dead zone" crossover distortion. The loop error signal is provided by both a single-ended charge pump output and standard differential logic outputs. Performance improvements of the IMI145158 over other single loop CMOS PLL devices are in the operating bandwidth and phase detector noise floor. With its extremely low phase noise floor and wider input bandwidth, prescaler ratios can be minimized to allow wide loop bandwidths for faster settling and lower phase noise. >145 MHz typical input frequency. -160 dBc/Hz total phase detector noise floor. No dead zone by design. Two phase detector outputs: * Current mode charge pump * Differential logic Unambiguous PLL acquisition. 3-line serial programming: data, clock, & enable. Compatible with the SPI (Serial Peripheral Interface) on CMOS MCUs. 10-bit N counter: Divider range = 1 to 1023. 7-bit A counter: Divider range = 0 to 127. 14-bit R counter: Divider range = 1 to 16383. On- or off-chip reference oscillator operation. Buffered & filtered ref output is provided. Packaging options: 16 PDIP or 16 SOIC or 20 PLCC. BLOCK DIAGRAM VDD = PIN 4 VSS = PIN 6 14 Bit Shift Register 3 2 14 Bit Latch Lock Detect 1 OSCin OSCout REFout 1 13 14 Bit /R Counter 2 Phase Detector A 14 Control Logic Fin Enable Data Clock 7 5 LD Fr PDout 8 11 10 9 7 Bit /A Counter 1-Bit Contro l S/R 10 Bit /N Counter Phase Detector B 1 2 1 7 Bit Latch 10 Bit Latch 2 3 16 15 3 7 Bit Shift Register 10 Bit Shift Register INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Rev 1.2 12 Phir Phiv Fv Mod Cntrl 9/3/98 Page 1 of 10 FREQUENCY SYNTHESIZER IMI145158 CMOS LSI SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER Preliminary MAXIMUM RATINGS Voltage Relative to VSS: -0.3V to 7V Voltage Relative to VDD 0.3V Storage Temperature: This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: -65C to 150C VSS<(Vin or Vout)< VDD Ambient Temperature: -40C to 85 C Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). PIN DESCRIPTIONS Pin Number 1 Name Xin Description Xtal in (or reference signal input ) to the reference oscillator / buffer. 2 Xout Xtal out (or Reference signal output ) of the reference oscillator / buffer. 14 REFout Buffered reference signal. 10 DATA Positive logic shift register input data. The first 14 bits are the reference or feedback divider programming information, sent MSB first. The final programming bit (control bit) selects which divider this programming information will be loaded into: 1 = the reference divider, and 0 = the feedback divider. / A and/ N Entry Format (Control Bit = 0) / A Counter Bits / N Counter Bits Last Data Bit In (Bit No. 18) First Data Bit in (Bit No. 1) INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Rev 1.2 9/3/98 Page 2 of 10 IMI145158 FREQUENCY SYNTHESIZER Preliminary CMOS LSI SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER PIN DESCRIPTIONS (continued) Pin Number Name Description / R Counter Bits Last Data Bit In (Bit No. 15) First Data Bit in (Bit No. 1) 9 CLOCK On each low-to-high transition, clocks one bit into the on-chip shift register from the data input. 11 ENABLE This signal, when HIGH, latches the information in the shift register into the 12 Mod Cntrl This output generates a signal by the on-chip control logic circuitry for controlling selected divider. an external dual-modulus prescaler. 8 fin Feedback divider input signal. Applied to the positive edge triggered counter, this signal is intended to be AC coupled. For CMOS logic level input signals, DC coupling can be used. 4 VDD Circuit positive power supply. 6 VSS Circuit ground. 5 PDout Single-ended charge pump output, usually used with passive loop filters. This signal operated according to this table: Frequency fv > fr at the phase detector: negative pulses. Frequency fv < fr at the phase detector: positive pulses. Frequency fv = fr at the phase detector: high-impedance state. 16 R Phase detector output. This signal goes LOW when the feedback frequency is too low. 15 V Phase detector output. This signal goes LOW when the feedback frequency is too high. 7 LD Lock detect output. When the PLL is locked, this signal will be essentially HIGH, with very narrow negative spikes at the phase detection frequency. If the PLL is out of lock, this signal will pulse LOW. 3 fv Output of the feedback divider N. 13 fr Output of the reference divider R. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Rev 1.2 9/3/98 Page 3 of 10 FREQUENCY SYNTHESIZER IMI145158 Preliminary CMOS LSI SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER PLL OPERATING CHARACTERISTICS VDD = 5 VOLTS -40C Characteristics Dynamic Symbol Max Min Typ 85C Max Min Max Unit Conditions Max Operating fin, Sine* 160 typ 225 120 170 110 typ 155 MHz + 4 dBm 1.0V p-p Frequency fosc Sine* 75 typ 105 85 120 55 typ 80 MHz +4 of Bm 1.0 V p-p Modulus Control Prop. Delay MCpd - 10 - 7.5 - 12 ns Synthesizer Phase Noise Floor PDNF Pin Cin - 6 - 4 6 - 6 pF Capacitances Cout - 8 - 6 8 - 8 pF Phase Det 1 gain Kd - - 0.65 - ma/Rad Phase Det 2 gain Kd - - 0.8 - v / Rad Input VIL 1 1.5 - 2.75 1.5 - 1.5 Voltages VIH 3.5 - 4.95 5.0 - 3.5 - Output VOL - 0.05 - 0.0 0.05 - 0.05 Voltages VOH 4.95 - 4.95 5.0 - 4.95 - Logic 2.4 - 2.0 2.8 - 1.6 - OSCout 1.2 - 1.0 1.4 - 0.8 - mA VOL = 0.40 Logic -2.4 - -2.0 -2.8 - -1.6 - mA VOH = 4.0 OSCout -1.2 - -1.0 -1.4 - -0.8 - mA VOH = 4.4 mA for 2Pi Radians mA fosc=fin-10 MHz A fosc=fin=0 A VIL = 0 IOL Static 25C Min Output Current IOH Icp Supply IDD Currents ISB 10.5 160 CPcur dBc/Hz 4.0 - 150 - IPU 40 150 - 50 150 @100kHz Vdc Vdc * Sine wave input is not recomended below 10 MHz. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Rev 1.2 9/3/98 Page 4 of 10 IMI145158 FREQUENCY SYNTHESIZER Preliminary CMOS LSI SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER PLL OPERATING CHARACTERISTICS VDD = 3 VOLTS -40C Characteristics Dynamic Symbol Min Typ Unit Conditions fin, Sine* 100 80 115 70 MHz +4 dBm 1.0V p-p Frequency fosc Sine* 60 65 95 50 MHz +4 dBm 1.0V p-p Modulus Control Prop. Delay MCpd - 11 Synthesizer Phase Noise Floor PDNF Pin Cin - 10 - 6 10 - 10 pF Capacitances Cout - 10 - 6 10 - 10 pF Phase Det 1 gain Kd - - 0.3 5 - ma/Ra d Phase Det 2 gain Kd - - 0.4 8 - v / Rad Input VIL - .0.9 - 1.3 5 0.9 - 0.9 Voltages VIH 2.1 - 2.1 1.6 5 - 2.1 - Output VOL - 0.05 - 0.0 0.05 - 0.05 Voltages VOH 2.95 - 2.95 3.0 - 2.95 - Static Output Current IOH Icp Supply Currents - Max 85C Max Operating IOL Min 25C 12 Max 15 Min - Max 17 160 dBc/Hz Vdc Vdc Logic 1.6 - 1.4 2.0 - 0.8 - OSCout 0.8 - 0.7 1.0 - 0.4 - mA VOL = 0.30 Logic -1.6 - -1.4 -2.0 - -0.8 - mA VOH = 2.4 OSCout -0.8 - -0.7 -1.0 - -0.4 - mA VOH = 2.4 mA for 2Pi Radian mA fosc=fin-10 MHz A fosc=fin=0 CP cur 2.2 IDD ISB ns - 150 - 40 150 - 150 * Sine wave input is not recomended below 10 MHz. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Rev 1.2 9/3/98 Page 5 of 10 FREQUENCY SYNTHESIZER IMI145158 CMOS LSI SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER Preliminary IMI145158 Typical Current Vs F 25.00 5V Min Sig 5V Max Sig 20.00 3V Min Sig 3V Max Sig 15.00 10.00 Current in Ma. 5.00 0.00 10 30 50 70 90 110 130 150 170 190 Frequency in MHz. IMI145158 Typical RF Sensivity Vdd = 3V IMI145158 Typical Reference Sensitivity Vdd = 3V 0 5 -5 0 -10 -5 -15 -10 -20 -40 3V -40 3V 25 3V 85 3V -25 25 3V -15 85 3V dBm -30 -20 -35 -25 -40 -30 -45 0 20 40 60 80 100 120 140 -35 0 20 40 Frequency MHz 60 80 100 120 Frequency MHz IMI145158 Typical RF Sensitivity Vdd = 5V 145158 Typical Reference Sensitivity Vdd = 5V 0 15 10 -5 5 -10 0 -5 -15 -40 5V -10 -40 5V dBm-15 85 5V 25 5V 85 5V dBm -20 25 5V -20 -25 -25 -30 -30 -35 -35 0 50 100 150 200 250 -40 0 Frequency MHz INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 20 40 60 80 100 120 140 160 180 200 Frequency MHz Rev 1.2 9/3/98 Page 6 of 10 IMI145158 FREQUENCY SYNTHESIZER Preliminary CMOS LSI SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER DUAL MODULUS PRESCALING Dual Modulus prescaling is a wide spread method used to effectively extend the operating frequency of a digital counter without sacrificing any frequency resolution. The key to understanding this method is to remember the basics of division: When any two integers are divided, a quotient and a remainder will result. When used here in a PLL, the numerator is the required PLL total feedback divider ratio, called Ntot. The denominator is the base modulus of the dual modulus prescaler, P. The quotient is applied directly to the N counter, and the remainder is applied directly to the A counter. Both counters count down together toward zero. While the A counter counts, the MC (modulus control) output signal is LOW, setting the prescaler to divide by P + 1. When the A counter reaches zero, the MC output is set HIGH while the N counter continues to count down to zero. When the N counter reaches zero, both counters are reset to the programmed inputs and the cycle is repeated. Two particular things should be noticed about this process. First, the remainder counts are spread among an equal number of quotient counts by the use of the prescaler modulus P +1. When the remainder has been counted, any remaining quotient counts are handled normally by prescaling by modulus P. This counter is thus performing Ntot = A(P+1) + (N-A)P Some algebra on this relation yields Ntot = AP+A + NP-AP = NP + A which is just the definition of integer division. Second, for this to work, there must be more quotient counts than remainder counts for all possible values of Ntot in the synthesizer design. If this were not true, then the N counter will reach zero and cause the entire divider to be reset before the A counter is finished. There is a minimum value for Ntot for which this requirement will always hold: 2 Ntot > P - P. PROGRAMMING GUIDELINES APPLICABLE TO THE IMI145158 The system total divide value (Ntotal) will be dictated by the application: frequency into the prescaler = N*P+A Ntotal = frequency into the phase detector N is the number programmed into the / N counter; A is the number programmed into / A counter. P and P + 1 are two selectable divide ratios available in the two modulus prescalers. To have a range of Ntotal values in sequence, the / A counter is programmed from zero through P-1 for a particular value N in the / N counter. N is then incremented to N + 1k, and the / A is sequenced from zero through P - 1 again. To maximize system frequency capability, the dual modulus prescaler's output must go from low to high after each group of P or P + 1 input cycles. The prescaler should divide by P when its modulus control line is high, and by P + 1 when its modulus control is low. For the maximum frequency into the prescaler (FVCO max), the value used for P must be large enough so that: A. FVCO max divided by P may not exceed the frequency capability of Pin 8 of the IMI145158. B. The period of FVCO divided by P must be greater than the sum of the times: a. Propagation delay through the dual modulus prescaler. b. Prescaler setup or release time relative to its modulus control signal. c. Propagation time from fin to the modulus control signal. A useful simplification in the IMI145158 programming code can be achieved by choosing the values for P or 8, 16, 32, or 64, or 128. For these cases, the desired value for Ntotal in binary is used as the program code to the / A counters in the following manner: A. Assume the / N counter and / A counter contains "b" bits where 2b = P. B. Always program all higher order / A counter bits above "b" to zero. C. Assume the / N counter and / A counter (with all the higher order bits above "b" ignored) combined into a single binary counter of 10+b bits in length. The MSB of this hypothetical counter is to correspond o the LSB of / A. The system divide value, Ntotal, now results when the value of Ntotal in binary is used to program the "new" 10+b bit counter. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Rev 1.2 9/3/98 Page 7 of 10 FREQUENCY SYNTHESIZER IMI145158 CMOS LSI SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER Preliminary CONNECTION DIAGRAM PLCC PACKAGE SOIC AND PDIP PACKAGE Pin No. 1 Index VSS 8 19 7 f V PDout 20 6 f R NC 1 5 NC 4 2 fv VDD Xin R V REFout Fr Mod Cntrl ENABLE DATA CLOCK 3 18 REFout 17 fR 16 NC 15 Mod Cntrl ENABLE 14 CLOCK DATA 12 NC 13 11 fin LD 10 9 16 15 14 13 12 11 10 9 Xout 1 2 3 4 5 6 7 8 Xin Xout Fv VDD PDout VSS LD fin TYPICAL APPLICATION CIRCUIT ,0, /' 8+) 3' IRXW 9&2 '$7$ ' &/2&. & (1$%/( ( 0RG &QWUO 9'' 966 S) S) 33 )LQ . S) 9'' X) S) '8$/ 02'8/86 35(6&$/(5 9 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 9 0D[LPXP 9DOXHV IRU I 9&2 0+] Rev 1.2 9/3/98 Page 8 of 10 IMI145158 FREQUENCY SYNTHESIZER Preliminary CMOS LSI SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER PACKAGE DRAWING AND DIMENSIONS D1 20-PIN PLCC DIMENSIONS E1 e .0 4 5 X 4 5 D E G b INCHES CHAMFER PIN 1 IDENT. .070 DIA X .023 DP E D .045 X 45 DEGREE CORNER CHAMFER a MILLIMETERS SYMBOL MIN NOM MAX MIN NOM MAX A 0.147 .152 0.157 3.733 3.86 3.987 b 0.003 0.007 0.011 0.076 0.177 0.279 b1 0.026 0.029 0.032 0.660 0.736 0.812 D 0.385 0.390 0.395 9.779 9.906 10.033 D1 0.385 0.390 0.395 9.779 9.906 10.033 E 0.343 0.348 0.353 8.712 8.839 8.966 E1 0.343 0.348 0.353 8.712 8.839 8.966 E2 0.310 0.320 0.330 7.874 8.128 8.382 b1 .050 BSC A e 1.27 BSC Q b1 E2 a 5 7 9 5 7 9 Q 0.0085 0.010 0.0115 0.216 .0.254 0.292 16-PIN PLASTIC DIP DIMENSIONS INCHES C E2 a E E1 D Q2 B2 Q A1 B1 S e1 B A L MILLIMETERS SYMBOL MIN NOM MAX MIN NOM MAX 4.318 A 0.150 0.160 0.170 3.81 4.06 A1 0.015 - - 0.381 - - B 0.016 0.018 0.020 0.40 0.45 0.50 B1 0.056 0.059 0.062 1.47 1.52 1.57 B2 0.046 0.049 0.052 1.17 1.24 1.32 C 0.008 0.010 0.012 0.20 0.25 0.30 D 0.748 0.750 0.752 19.00 19.05 19.10 E 0.300 0.312 0.325 7.62 7.924 8.255 E1 0.240 0.252 0.260 6.096 6.49 6.604 E2 0.335 0.345 0.355 8.51 8.76 9.01 0.100 BSC e1 2.54 BSC L 0.25 0.230 0.135 3.175 3.30 a 0 7 15 0 7 15 Q1 0.059 0.060 0.061 1.50 1.53 1.55 Q2 0.128 0.130 0.132 3.25 3.30 3.35 S 0.073 0.075 0.077 1.85 1.90 1.95 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Rev 1.2 3.429 9/3/98 Page 9 of 10 FREQUENCY SYNTHESIZER IMI145158 CMOS LSI SERIAL PROGRAMMED PLL FREQUENCY SYNTHESIZER Preliminary PACKAGE DRAWING AND DIMENSIONS 16 PIN SOIC DIMENSIONS INCHES C SYMBOL L H E D a A2 A B NOM MAX MIN NOM MAX A 0.097 0.101 0.104 2.46 2.56 2.64 A1 0.0050 0.009 0.0115 0.127 0.22 0.29 A2 0.090 0.092 0.094 2.29 2.34 2.39 B 0.014 0.016 0.019 0.35 0.41 0.48 C 0.0091 0.010 0.0125 0.23 0.25 0.32 D 0.402 0.407 0.412 10.21 10.34 10.46 E 0.292 0.296 0.299 7.42 7.52 7.59 e A1 e MILLIMETERS MIN 0.050 BSC 0.127 BSC H 0.400 0.406 0.410 10.16 10.31 10.41 L 0.024 0.032 0.040 0.61 0.81 1.02 0 5 8 a 0 5 8 ORDERING INFORMATION Part Number Package Type Production Flow IMI145158FPB 16 PIN Plastic Dip Industrial, -40C to +85C IMI145158FXB 16 PIN SOIC Industrial, -40C to +85C IMI145158FQB 20 PIN PLCC Industrial, -40C to +85C * Please contact factory for other options. Note: The "x" following the IMI Device Number denotes the device revision. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI 145158FPB Date Code, Lot # IMI145158FPB Flow B = Industrial, -40C to +85C Package P = Plastic Dip X = Small Outline Q = PLCC Revision IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 276 FAX 408-263-6571 Rev 1.2 9/3/98 Page 10 of 10