Freescale Semiconductor Document Number: MMA955xL
Data Sheet: Technical Data Rev. 3.1, 5/2015
An Energy Efficient Solution by Freescale
© 2011, 2013, 2015 Freescale Semiconductor, Inc. All rights reserved.
MMA955xL Intelligent
Motion-Sensing Platform
The MMA955xL device an intelligent sensor, incorporating dedicated
accelerometer MEMS transducers, signal conditioning, data conversion, and a
32-bit programmable microcontroller.
This unique blend transfor ms Freescale’s MMA955xL into an intelligent, high-
precision, motion-sensing platform able to manage multiple sensor inputs. This
device can make system-level decisions required for sophisticated applications
such as gesture recognition, pedometer functionality, tilt compensation and
calibration, and activity monitoring.
The MMA955xL device is programmed and configured with the CodeWarrior
Development Studio for Microcontrollers software, version 10.1 or later. This
standard integrated design environment enables customers to quickly
implement custom algorithms and features to exactly match their application
needs.
Using the master I2C port, the MMA955xL device can manage secondary
sensors, such as pressure sensors, magnetometers, or gyroscopes. This
allows sensor initialization, calibration, data compensation, and computation
functions to be off-loaded from the system application processor. The
MMA955xL device also acts as an intelligent se nsing hub and a highly
configurable decision engine. Total system power consumption is significantly
reduced because the application processor stays powered down until
absolutely needed.
Hardware Features
Three accelerometer operating ranges:
–±2g suits most hand gestures (orientation detection and tilt control) and
freefall. For tap detection, ±4 g and ±8 g are supported.
–±4g covers most regular human dynamics (walking and jogging)
–±8g detects most abrupt activities (gaming)
Integrated temperature sensor
One slave SPI or I2C interface operating at up to 2 Mbps, dedicated to
communication with the host processor. Default value of the I2C, 7-bit
address is 0x4C. (This can be customized by firmware.)
One master I2C interface operating at up to 400 kbps that can be used to
communicate with external sensors
Eight selectable output data rates (ODR), from 488 Hz to 3.8 Hz (extending
farther from 3906 Hz to 0.24 Hz with MMA9559L Firmware version)
10, 12, 14, and 16-bit trimmed ADC data formats available
1.8 V supply voltage
32-bit CPU with MAC unit
Extensive set of power-management features and low-power modes
Integrated 16-bit resolution ADC can be used to convert external analog
signals
Single-Wire, Background-Debug Mode (BDM) pin interface
16-KB flash memory
2-KB Random Access Memory
ROM-based flash controller and slave-port, command-line interpreter
Two-channel timer with input capture, output capture, or edge-aligned PWM
Programmable delay block for scheduling events relative to start of frame
A 16-bit, modulo timer for scheduling periodic events
Minimal external component requirements
RoHS compliant (–40ºC to +85ºC), 16-pin, 3 x 3 x 1-mm LGA package
16-pin LGA
3 mm x 3 mm x 1 mm
Case 2094-01
MMA9550L
MMA9551L
MMA9553L
MMA9559L
Top and bottom view
Top view
Pin connection s
1
2
3
4
5678 9
13
12
11
10
16 15 14
VDD RGPIO7/AN1/
TPMCH1
RGPIO8/PDB_B
SDA0/RGPIO1/SDI
BKGD-MS
/RGPIO9
RESETB
SCL0/RGPIO0
SCLK
VSS
RGPIO2/SCL1/SDO
RGPIO3/SDA1/SSB
RGPIO6/AN0
TPMCH0
RGPIO5/PDB_A/
INT_O
VSS
RGPIO4/INT
VDDA
VSSA
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2Freescale Semiconductor, Inc.
Sof t wa re Fe atures
This device can be programmed to provide any of th e following:
Orientation detection (portrait/landscape)
High-g/Low-g threshold detection
Pulse detection (single, double and directional tap)
Tilt detection
Auto wake/ s le e p
Embedded, smart FIFO
Power management
Pedometer
A selection of the software features are included in the factory-programmed firmware for some devices. Users may add their own
features with user firmware.The power and flexibility of the embedded ColdFire V1 MCU core associated with the high perfor-
mance 3-axis accelerometer give new and unprecedented capabilities to the MMA955xL devices family.
Table 1. Ordering information
Part number Firmware Temperature range Package description Shipping
MMA9550LR1 Motion –40°C to +85°C LGA-16 Tape and reel
MMA9551LR1 Gesture –40°C to +85°C LGA-16 Tape and reel
MMA9553LR1 Pedometer –40°C to +85°C LGA-16 Tape and reel
MMA9559LR1 Foundation –40°C to +85°C LGA-16 Tape and reel
MMA955xL
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Contents
1 Variations of MMA955xL Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Typical Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1. . Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2. . Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.1 Package diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.2 Sensing Direction and Output Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.3 Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3. . Pin Function Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4. . System Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.1 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.2 Layout Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.3 MMA955xL Platform as an Intelligent Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4.4 MMA955xL Platform as a Sensor Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Mechanical and Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1. . Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2. . Pin Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3. . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4. . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5. . Electrostatic Discharge (ESD) and Latch-up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6. . General DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7. . Supply Current Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.8. . Accelerometer Transducer Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.9. . ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.10. ADC Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.11. AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.12. General Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.13. I2C Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13.1 Slave I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13.2 Master I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14. Slave SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.15. Flash Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1. . Footprint and pattern informa tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2. . Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3. . Tape and reel information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Related Documentation
The MMA955xL device features and operations are described in a variety of reference manuals, user guides, and application
notes. To find the most-current versions of these documents:
1. Go to the Freescale homepage at freescale.com.
2. In the Keyword search box at the top of the page, enter the device number MMA955xL.
3. In the Refine Yo ur Result pane on the left, click on the Documentation link.
MMA955xL
Sensors
4Freescale Semiconductor, Inc.
1 Variations of MMA955xL Device
Freescale offers a variet y of firmwar e versi ons for th e MMA9 55xL devices. The dif f erent versions of the device are identified by
the fourth digit in the part number (for example MMA9559L). Information and specifications provided in this data sheet are inde-
pendent of the Freescale firmware versions.
The following table lists some of the variations among the MMA955xL-platform devices.
Table 2. Features of product-line devices
Feature - Device MMA9550L MMA9551L MMA9553L MMA9559L
Key elements Motion sensing Gesture sensing Pedometer High flexibility
User flash available 6.5 KB 4.5 KB 1.0 KB 14 KB
User RAM available 576 bytes 452 bytes 420 bytes 1664 bytes
ADC resolution (bits) 10,12,14,16 bits 10,12,14,16 bits 10,12,14,16 bits 10,12,14,16 bits
g measurement ranges 2 g, 4 g, 8 g2 g, 4 g, 8 g2 g, 4 g, 8 g2 g, 4 g, 8 g
Real-time and preemptive scheduling Yes Yes Yes No
Event management No No No Yes
Slave Port Command Interpreter
Normal mode Yes Yes Yes No
Legacy mode Yes Yes Yes No
Streaming mode Yes Yes Yes No
Front-end processing
100-Hz BW anti-aliasing Yes Yes Yes No
50-Hz BW anti-aliasing Yes Yes Yes No
g-mode-dependent resol ution YesYesYesYes
Absolute value Yes Yes Yes No
Low-pass filter Yes Yes Yes No
High-pass filter Yes Yes Yes No
Data-ready interrupt YesYesYesYes
Gesture applications
High g/Low gNo Yes No No
•Tilt No Yes No No
Portrait/Landscape No Yes No No
Programmable orientation No Yes No No
Tap/Double-tap No Yes No No
Freefall No Yes No No
•Motion No Yes No No
MMA955xL
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Freescale Semiconductor, Inc. 5
The only difference between the various device configurations is the firmware content that is loaded into the flash memory at the
factory. The user still can add custom software using the remaining portion of flash memory.
MMA9555L is described on a separate data sheet due to the device’s configuration.
The MMA9550L, MMA9551L, and MMA9553L devices can function immediately as they are. They have an internal command
interpreter and applications scheduler and can interact directly with the users’ host system.
The MMA9559L device provides the most flexibility and is for users who need to design their own control loop and system. The
device needs to be programmed with custom user code.
Data-storage modules
Data FIFO Yes Yes Yes No
Event queue Yes Yes Yes No
Inter-process FIFO No No No Yes
Power-control module
Run and Stop on idle YesYesYesYes
Run and No stop YesYesYesYes
•Stop NC YesYesYesYes
Auto-Wake / Auto-Sleep / Doze Yes Yes Yes No
Data-management daemons Yes Yes Yes Yes
Pedometer applications
Step count No No Yes No
Distance No No Yes No
Adaptive distance No No Yes No
Activity monitor No No Yes No
Table 2. Features of product-line devices (Continued)
Feature - Device MMA9550L MMA9551L MMA9553L MMA9559L
MMA955xL
Sensors
6Freescale Semiconductor, Inc.
2 Typical Applications
This low-power, intelligent sensor platform is optimized for use in portable and mobile consumer products such as:
Tablets/PMPs/PDAs/digital cameras
Orientation detection (portrait/landscape)
Image stability
Tilt-control enabled with higher resolution
Gesture recognition
Tap to control
Auto wake/sleep for low power consumption
Smartbooks/ereaders/netbooks/laptops
Anti-theft
Freefall detection for hard-disk drives
Orientation detection
Tap detection
Pedometers
Gaming and toys
Activity monitoring in medical applications
•Security
Anti-theft
Shock detection
–Tilt
Fleet monitoring, tracking
System auto-wake on movement
Detection
Shock recording
Anti-theft
Power tools and small appliances
–Tilt
Safety shut-off
MMA955xL
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Freescale Semiconductor, Inc. 7
3 General Description
3.1 Functional Overview
The MMA955xL device consists of a 3-axis, MEMS accelerometer and a mixed-signal ASIC with an integrated, 32-bit CPU. The
mixed-signal ASIC can be utilized to measure and condition the outputs of the MEMS accelerometer, internal temperature sensor,
or a differential analog signal from an external device.
The calibrated, measured sensor outputs can be read via the slave I2C or SPI port or utilized internally within the MMA955xL
platform.
Figure 1. Platfo rm block diagram
A block level view is shown in the preceding figure and can be summarized at a high level as an analog/mixed-mode subsystem
associated with a digital engine:
The analog subsystem is composed of:
A 3-axis transducer that is an entirely passive block including the MEMS structures.
An Analog Front End (AFE) with the following:
A capacitance-to-voltage converter (CVC)
An analog-to-digital converter
A temperature sensor
The digital subsystem is composed of:
A 32-bit, CPU with a Background-Debug Module (BDM)
Memory: RAM, ROM, and flash
Rapid GPIO (RGPIO) port-control logic
Timer functions include:
Modulo timer module (MTIM16)
Programmable Delay Timer (PDB)
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MMA955xL
Sensors
8Freescale Semiconductor, Inc.
General-Purpose Timer/PWM Module (TPM)
–I
2C master interface
–I
2C or SPI slave interface
System Integration Module (SIM)
Clock-Generation Module
The slave interfaces (either SPI or I2C) operate independently of the CPU subsystem. They can be accessed at any time, includ-
ing while the device is in low-powe r, deep-sleep mode.
3.2 Packaging Information
All pins on the device are utilized and many are multiplexed.
The following sections describe the pinout. Users can select from multiple pin functions via the SIM pin mux-control registers.
3.2.1 Package diagrams
Figure 2. Device pinout (top view) and package frame conven tion
1
2
3
4
5
678
9
13
12
11
10
16 15 14
VDD RGPIO7/AN1/TPMCH1
RGPIO8/PDB_B
SDA0/RGPIO1/SDI
BKGD-MS/RGPIO9
RESETB
SCL0/RGPIO0/SCLK
VSS
RGPIO2/SCL1/SDO
RGPIO3/SDA1/SSB
RGPIO6/AN0/TPMCH0
RGPIO5/PDB_A/INT_O
VSS
RGPIO4/INT
VDDA
VSSA
Direction of the
detectable accelerations
X
Y
Z
1
(TOP VIEW)
MMA955xL
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Freescale Semiconductor, Inc. 9
3.2.2 Sensing Direction and Output Response
The following figure shows the device’s default sensing direction when measuring gravity in a static manner. Also included are
the standard abbreviations or names for the six different orientation modes: portrait up/down, landscape left/right and back/front.
Figure 3. Se nsing direction and output response
3.2.3 Pin Functions
The following table summarizes functional options for each pin on this device.
Table 3. Pin functions
Pin # Pin Function #1(1)
1. Pin function #1 represents the reset state of the hardware. Pin functions can be changed via the SIM pin, mux-control registers in Freesc al e or us er firm wa re .
Pin Function #2 Pin Function #3 Description
1VDD Digital power supply
2BKGD/MS RGPIO9 Background-debug / Mode select / RGPIO9
3RESETB(2)
2. RESETB is an open-drain, bidirectional pin. Reset must be pul led high at startup. After st artup, Reset may be asserted to reset the device.
Active-low reset
4SCL0 RGPIO0 SCLK Serial clock for slave I2C / RGPIO0 / Serial clock for slave SPI
5VSS Digital ground
6SDA0 RGPIO1 SDI Serial data for slave I2C / RGPIO1 / SPI serial data input
7RGPIO2 SCL1 SDO
RGPIO2 / Serial clock for master I2C / SPI serial data output
8(3) RGPIO3 SDA1 SSB RGPIO3 / Serial data for master I2C / SPI slave select
9 RGPIO4 INT RGPIO4 / Interrupt input
10 RESERVED (Connect to VSS) Must be grounded externally
11 RGPIO5 PDB_A INT_O
RGPIO5 / PDB_A / INT_O slave-port interrupt output.INT_O can
only output interrupts from the COCO bit. Other than for the
MMA9559, use RGPIO6–RGPIO9 for setting sensor data
output interrupts.
12 RGPIO6 AN0 TPMCH0 RGPIO6 / ADC Input 0 / TPM Channel 0
13 RGPIO7 AN1 TPMCH1 RGPIO7 / ADC Input 1 / TPM Channel 1
14 VDDA Analog power
15 RGPIO8 PDB_B RGPIO8 / PDB_B
16 VSSA Analog ground
Top View
PU
Gravity
Pin 1
Xout @ 0 g
Yout @ -1 g
Zout @ 0 g
Xout @ 1 g
Yout @ 0 g
Zout @ 0 g
Xout @ 0 g
Yout @ 1 g
Zout @ 0 g
Xout @ -1 g
Yout @ 0 g
Zout @ 0 g
LL
PD
LR Side View
FRONT
Xout @ 0 g
Yout @ 0 g
Zout @ 1 g
BACK
Xout @ 0 g
Yout @ 0 g
Zout @ -1 g
MMA955xL
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10 Freescale Semiconductor, Inc.
3.3 Pin Function Descriptions
This section provides a brief description of the various pin functions available on the MMA955xL platform. Ten of the device pins
are multiplexed with Rapi d GPIO (RGPIO) functions. The “Pin Function #1” column in Table 3 on page 9 lists which function is
active when the hardware exits the Reset state. Freescale or user firmware can use the pin mux-control registers in the System
Integration Module (SIM) to change pin assignments for each pin after reset. For detailed information about these registers, see
the MMA955xL Three-Axis Accelerometer Reference Manual (MMA955xLRM).
VDD and VSS: Digital power and ground. VDD is nominally 1.8 V.
VDDA and VSSA: Analog power and ground. VDDA is nominally 1.8 V. To optimize performance, the VDDA line can be filtered to
remove any digital noise that can be present on the 1.8 V supply. (See Figure 5 and Figure 6 on page 16.)
RESETB: The RESETB pin is an open-drain, bidirectional pin with an internal, weak, pullup resistor. At start-up, it is configured
as an input pin, but also can be programmed to become bidirectional. Using this feature, the MMA955xL device can reset external
devices for any purpose other than power-on reset. Reset must be pulled high at power up to boot to Application code space. If
low, it will boot to ROM code. After startup, Reset may be asserted to reset the device. The total external capacitance to ground
has to be limited when using RESETB-pin, output-drive capability . For more details, see the “System Integration Module” chapter
of the MMA955xL Three-Axis Accelerometer Reference Manual (MMA955xLRM).
Slave I2C port: SDA0 and SCL0: These are the slave-I2C data and clock signa ls, respectively. The MMA955xL device can be
controlled via the serial port or via the slave SPI interface.
Master I2C: SDA1 and SCL1: These ar e th e ma ster-I2C data and clock signals, respectively.
Analog-to-Digital Conversion: AN0, AN1: The on-chip ADC can be used to perform a differential, analog-to-digital conversion
based on the voltage present across pins AN0(-) and AN1(+). Conversions for these pins are at the same Output Data Rate
(ODR) as the MEMS transducer signals. Input levels are limited to 1.8 V differential.
Rapid General Purpose I/O: RGPIO[9:0]: The CPU has a feature called Rapid GPIO (RGPIO). This is a 16-bit, input/output port
with single-cycle write, set, clear, and toggle functions available to the CPU. The MMA955xL device brings out the lower 10 bits
of that port as pins of the device. At reset, All of the RGPIO pins are configured as input pins, although pin muxing does reassign
some pins to non-RGPIO function blocks. Pull-ups are disabled.
RGPIO[9] is connected to BKGD/MS. RGPIO[9:6] can be set as interrupt pins for most interrupt sources.
RGPIO[1:0] SDA0 and SCL0 are connected at reset.
Interrupt s: INT: This input pin can be used to wake the CPU from a deep-sleep mode. It can be programmed to trigger on either
rising or falling edge , or high or low level. This pin operates as a Level-7 (high-priority) interrupt.
Debug/Mode Control: BKGD/MS: At start-up, this pin operates as mode select. If this pin is pulled high during start up, the CPU
will boot normally and run code. If this pin is pulled low during start-up, the CPU will boot into active Background -Debug Mode
(BDM). In BDM, this pin operates as a bidirectional, single-wire, background-debug port. It can be used by development tools for
downloading code into on-chip RAM and flash and to debug that code. There is an internal pullup resistor on this pin. It may be
left floating.
Timer: PDB_A and PDB_B: These are the two outputs of the programmab le delay block.
Slave SPI Interface: SCLK, SDI, SDO and SSB: These pi ns control the slave SPI clock, data in, data out, and slave-select
signals, respectively. The MMA955xL platform can be controlled via this serial port or via the slave-I2C interface. SSB has a spe-
cial function at startup that selects the Slave interface mode. Low at startup selects SPI and high selects I2C.
INT_O: The slave-port output interrupt pin. This pin can be used to flag the host when a response to a command is available to
read on the slave port. This Interrupt pin can only output the COCO bit interrupt. Other than for the MMA9559, use RGPIO6–
RGPIO9 for full interrupt capability.
TPMCH0 and TPMCH1: The I/O pin associated with 16-bit, TPM channel 0 and 1.
3.4 System Connections
3.4.1 Power Sequencing
An internal circuit powered by VDDA provides the device with a power-on-reset signal. In order for this signal to be properly rec-
ognized, it is important that VDD is powered up before or simultaneously with VDDA. The voltage potential between VDD and VDDA
must not be allowed to exceed the value specified in Table 7 on page 16.
3. RGPIO3/SDA1/SSB = Low at startup selects SPI. High at startup selects I2C. This is a function of the application boot code, not of the hardware.
MMA955xL
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Freescale Semiconductor, Inc. 11
3.4.2 Layout Recommendations
Provide a low-impedance path from the boa rd power supply to each power pin (VDD and VDDA) on the device and from the
board ground to each ground pin (VSS and VSSA).
Place 0.01 to 0.1 µF capacitors as close as possible to the package supply pins to meet the minimum bypass requirement.
The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs. VDDA/VSSA ceramic
and tantalum capacitors tend to provide better tolerances.
Ensure that capacitor leads and associated printed-circuit traces that connect to the chip VDD and VSS (GND) pins are as
short as possible.
Bypass the power and ground with a capacitor of approximately 1 µF and a number of 0.1-µF ceramic capacitors.
Minimize PCB trace lengths for high-frequency signals. This is especially critical in systems with higher capacitive loads that
could create higher transient currents in the VDD and VSS circuits.
Take special care to minimize noise levels on the VDDA and VSSA pins.
Use separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA. Connect the separate analog
and digital power and ground pla nes as close as possible to power supply outputs. If both analog circuit and digital circuits
are powered by the same power supply , it is advisable to connect a small inductor or ferrite bead in series with both the VDDA
and VSSA traces.
Physically separate the analog components from noisy digital components by ground planes. Do not place an analog trace
in parallel with digital traces. It is also desirable to place an analog ground trace around an analog signal trace to isolate it
from digital traces.
Provide an interface to the BKGD/MS pin if in-circuit debug capability is desired.
Ensure that resistors RP1 and RP2, in the following figure, match the requirements stated in the I2C standard. For the shown
configuration, the value of 4.7 kΩ would be ap propriate.
3.4.3 MMA955xL Platform as an Intelligent Slave
I2C pullup resistors, a ferrite bead, and a few bypass capacitors are all that are required to attach this device to a host platform.
The basic configurations are shown in the following two figures. In addition, the RGPIO pins can be programmed to generate
interrupts to a host platform in response to the occurrence of real-time application events. In this case, the pins should be routed
to the external interrupt pins of the CPU.
NOTE
Immediately after a device reset, the state of pin number 8 (RGPIO3/SDA1/SSB functions) is used to select the slave port inter-
face mode. This implies important rules in the way the host controller or , more generally , the complete system should be handling
this pin.
First of all, whenever a reset occurs on the MMA955xL, the RGPIO3 pin level shall be consistent with the interface mode of op-
eration. This is particularly important if this pin is driven from external devices. If the RGPIO3 level does not match the current
mode of operation, an alternate mode is selected and communication with the host is lost.
If I2C mode is used, a good practice is to tie RGPIO3 to a pull-up resistor so that it defaults to high level. Note that such a con-
nection exist s whe n the Master I 2C interface is used (SDA1 function for pin 8). When using I2C mode for the slave interface, the
RGPIO3 pin plays two roles: RGPIO3 and mode selection. When the MMA955xL is powered on and the mode selection is I2C,
the RGPIO3 pin is released as a GPIO pin. The default setting of RGPIO3 is as an output pin and output low. In order to reduce
the leakage current on the pull-up resistor, a large resistor value can be used or RGPIO3 can be set as an input pin.
When using SPI mode for the slave interface, the situation is more complex as the same pin plays two roles: SSB and mode
selection. Moreover , af ter a SPI read or write operation, the SSB line returns to high level. Consequently, if the host is sending a
command to the MMA955xL that induces a subsequent reset, immediately after the write transaction, the host shall force the
SSB line to low level so that SPI mode is still selected after reset. Keeping the duration for the SSB line low typically depends on
the latency between the write transaction and the execution of the reset command. Such latency can be significant for the
MMA9553L pedometer firmware as the Command Interpreter and Scheduler Application are running at 30 Hz, which gives a 33
ms typical latency. The MMA9550L and MMA9551L firmware, on the other hand, operate the Command Interpreter and Sched-
uler Applications at 488 Hz, which gives a 2 ms typical latency.
The rule obviously applies also when a hardware reset is issued by the host through MMA955xL pin number 3 (RESETB active
low). Again the host has to drive the SSB line low prior to release of the hardware reset line to high level, which triggers immediate
MMA955xL reset and boot sequence. Keeping the SSB line low for a 1 ms duration (after RESETB is released) is enough for the
MMA955xL slave device to reboot into SPI mode.
MMA955xL
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12 Freescale Semiconductor, Inc.
Figure 4. Platform as an I2C slave
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Figure 5. Platform as an SPI slave
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MMA955xL
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14 Freescale Semiconductor, Inc.
3.4.4 MMA955xL Platform as a Sensor Hub
The MMA955xL device includes:
a powerful 32-bit CPU
a second I2C bus
one external analog input
These features can all be monitored using the on-chip ADC.
The combination of low power consumption and po werful features means that the MMA955xL platform can effectively operate
as a power controller for handheld units such as industrial scanners, PDAs, and games. The host platform can put itself to sleep
with confidence that the MMA9 55xL device will issue a wake request should any external event require its attention.
The following figure illustrates the MMA9 55xL device being used in this configuration. Observe how all that is required is a few
bypass capacitors, a ferrite bead, and some pullup resistors for the I2C buses.
Figure 6. Platfo rm as sensor hub
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MMA955xL
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Freescale Semiconductor, Inc. 15
4 Mechanical and Electrical Specifications
This section contains electrical specification tables and reference timing diagrams for the MMA955xL device, including detailed
information on power considerations, DC/AC electrical characteristics, and AC timing specifications.
4.1 Definitions
Cross-axis sensitivity The proportionality constant that relates a variation of accelerometer output to cross acceleration. This
sensitivity varies with the direction of cross acceleration and is primarily due to misalignment.
Full range The algebraic difference between the up per and lower values of the input range. Refer to the input/
output characteristics.
Hardware compensated Sensor modules on this device incl ude hardware-correction factors for gain and offset errors that are
calibrated during factory test using a least-squares fit of the raw sensor data.
Linearity error The deviation of the sensor output from a least-squares linear fit of the input/outpu t data.
Nonlinearity The systematic deviation from the straight line that defines the nominal input/output relationship.
Pin group the clustering of device pins into a number of logical pin groupings to simplify and standardize electrical
data sheet parameters. Pin groups are defined in Section 4.2, “Pin Groups”.
Software compensated Freescale’s advanced non-linear calibration functions that—with the first-order hardware gain and off-
set calibration features—improve sensor performance.
W arm-up time The time from the initial application of power for a sensor to reach its specified performance under the
documented operating conditions.
4.2 Pin Groups
The following pin groups are used throughout the remainder of this section.
Group 1 RESETB
Group 2 RESERVED
Group 3 RGPIO[9:0]
4.3 Absolute Maximum Ratings
Absolute maximum ratings are the limits the device can be exposed to without permanently damaging it. Absolute maximum rat-
ings are stress ratings only; functional operation at these ratings is not guaranteed. Exposure to absolute maximum ratings con-
ditions for extended periods may affect reliability.
This device contains circuitry to protect against damage due to high static volt age or electrical fields. It is advised, however, that
normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS
or VDD).
Table 4. Absolu te maximum ratings
Rating Symbol Minimum Maximum Unit
Digital supply voltage VDD -0.3 2.0 V
Analog supply voltage VDDA -0.3 2.0 V
Voltage difference, VDD to VDDA VDD - VDDA -0.1 0.1 V
Voltage difference, VSS to VSSA VSS - VSSA -0.1 0.1 V
Input voltage VIn -0.3 VDD + 0.3 V
Input/Output pin-clamp current IC-20 20 mA
Output voltage range (Open-Drain Mode) VOUTOD -0.3 VDD + 0.3 V
Storage temperature Tstg -40 125 °C
Mechanical shock SH 5k g
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16 Freescale Semiconductor, Inc.
4.4 Operating Conditions
4.5 Electrostatic Discharge (ESD) and Latch-up Protection Characteristics
4.6 General DC Characteristics
Table 5. Nominal operating conditions
Rating Symbol Min Typ Max Unit
Digital supply voltage VDD 1.71 1.8 1.89 V
Analog supply voltage VDDA 1.71 1.8 1.89 V
Voltage difference, VDD to VDDA VDD - VDDA -0.1 0.1 V
Voltage difference, VSS to VSSA VSS - VSSA -0.1 0.1 V
Input voltage high VIH 0.7*VDD —V
DD+0.1 V
Input voltage low VIL VSS - 0.3 0.3*VDD V
Operating temperature TA-40 25 85 °C
Table 6. ESD and latch-up protection characteristics
Rating Symbol Min Max Unit
Human Body Model (HBM) VHBM ±2000 V
Machine Model (MM) VMM ±200 V
Charge Device Model (CDM) VCDM ±500 V
Latch-up current at 85°C ILAT ±100 mA
Table 7. DC characteristics(1)
1.All conditions at nominal supply: VDD = VDDA = 1.8 V.
Characteristic Symbol Condition(s)(2)
2.Pin groups are defined in “Pin Groups” on page 15.
Min Typ Max Unit
Output voltage high
Low-drive strength
High-drive strength VOH
Pin Groups 1 and 3
ILOAD = –2 mA
ILOAD = –3 mA VDD – 0.5 V
Output voltage low
Low-drive strength
High-drive strength VOL
Pin Groups 1 and 3
ILOAD = 2 mA
ILOAD = 3 mA ——0.5V
Output-low current
Max total IOL for all ports IOLT —— 24mA
Output-high current
Max total IOH for all ports IOHT —— 24mA
Input-leakage current |IIN|Pin Group 2
Vin = VDD or VSS —0.1 1 µA
Hi-Z (off-state) leakage current |IOZ|Pin Group 3 input
resistors disabled
Vin = VDD or VSS
—0.1 1 µA
Pullup resistor RPU when enabled 17.5 52.5 KΩ
Power-on-reset voltage VPOR 1.50 V
Power-on-reset hysteresis VPOR-hys 100 mV
Input-pin capacitance CIN ——7pF
Output-pin capacitance COUT ——7pF
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4.7 Supply Current Characteristics
4.8 Accelerometer Transducer Mechanical Characteristics
4.9 ADC Characteristics
Table 8. Supply current characteristics(1)
1. All conditions at nominal supply: VDD = VDDA = 1.8V.
Characteristic Symbol Condition(s) Min Typ Max Unit
Supply current in STOPNC mode IDD-SNC Internal clocks disabled 2 µ A
Supply current in STOPSC mode IDD-SSC Internal clock in
slow-speed mode —15—µA
Supply current in RUN mode(2)
2. Total current with the analog section active, 16 bits ADC resolution selected, MAC unit used and all peripheral clocks enab led.
IDD-R Internal clock in
fast mode —3.1—mA
Table 9. Accelerometer characteristics
Characteristic Symbol Condition(s) Min Typ Max Unit
Full range AFR
2 g±1.8 ±2 ±2.2 g4 g±3.6 ±4 ±4.4
8 g±7.2 ±8 ±8.8
Sensitivity/resolution ASENS
2 g 0.061 mg/LSB4 g 0.122
8 g 0.244
Zero-g level offset accuracy
(Pre-board mount) OFFPBM
2 g–100 +100 mg4 g
8 g
Nonlinearity
Best-fit stra ight line ANL
2 g—±0.25— % AFR
4 g—±0.5—
8 g—±1—
Sensitivity change vs.temperature TCSA 2 g—±0.17— %/°C
Zero-g level change vs. temperature(1)
1. Relative to 25°C.
TCOff ——±1.9mg/°C
Zero-g Level offset accuracy
(Post-board mount) OFFBM
2 g–100 +100 mg4 g
8 g
Output data bandwidth BW ODR/2 Hz
Output noise Noise 2 g, ODR = 488 Hz 100 µg/sqrt(Hz)
8 gg, ODR = 488 Hz 120 µg/sqrt(Hz)
Cross-axis sensitivity ——55%
Table 10. ADC characteristics(1)
Characteristic Symbol Condition(s) Min Typ Max Unit
Input voltage VAI Voltage at AN0 or AN1 0.2 1.1 V
Differential input voltage VADI AN1 - AN0 -0.9 0.9 V
Full-scale range VFS ——1.8V
Programmable resolution RES —101416Bits
Conversion time @ 14-bits resolution
(Three-sample frame) tc 207 µs
Integral nonlinearity INL Full Scale ±15 LSB
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18 Freescale Semiconductor, Inc.
4.10 ADC Sample Rates
The MMA955xL platform supports the following sample rate s:
488.28 frames per second (fps)
244.14 fps
122.07 fps
61.04 fps
30.52 fps
15.26 fps
•7.63 fps
•3.81 fps
In addition to the previous list, additi onal sample rates are available with the MMA9559L device.
3906.25 fps (for 10- and 12-bit mode only)
1953.13 fps
976.56 fps
•1.91 fps
•0.95 fps
•0.48 fps
•0.24 fps
Note: The highest rate has a restriction in terms of ADC resolution selection as time available for data conversion is much
reduced.
Differential nonlinearity DNL ±2 LSB
Input leakage IIA ——±2µA
1. All conditions at nominal supply: VDD = VDDA = 1.8 V and RES = 14, unless otherwise noted.
Table 10. ADC characteristics(1)
Characteristic Symbol Condition(s) Min Typ Max Unit
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Freescale Semiconductor, Inc. 19
4.11 AC Electrical Characteristics
Tests are conducted using the input levels specified in Table 5 on page 16. Unless otherwise specified, propagation delays are
measured from the 50-percent to 50-percent point. Rise and fall times are measured between the 10-percent and 90-percent
points, as shown in the following figure.
Figure 7. Input signal measurement references
The subsequent figure shows the definitions of the following signal states:
Active state, when a bus or signal is driven and enters a low-impedance state
Three-stated, when a bus or signal is placed in a high-impedance state
Data Valid state, when a signal level has rea ch ed VOL or VOH
Data Invalid state, when a signal level is in transition between VOL and VOH
Figure 8. Signal states
4.12 General Timing Control
Table 1 1. General timing characteristics(1)
1. All conditions at nominal supply: VDD = VDDA = 1.8 V
Characteristic Symbol Condition(s) Min Typ Max Unit
VDD rise time Trvdd 10% to 90% 1 ms
POR release delay(2)
2. This is the time measured from VDD = VPOR until the internal reset signal is released.
TPOR Power-up 0.35 1.5 ms
Warm-up time TWU From STOPNC —7—
sample
periods
Frequency of operation FOPH Full Speed Clock 8 MHz
FOPL Slow Clock 62.5 KHz
System clock period tCYCH Full Speed Clock 125 ns
tCYCL Slow Clock 16 μs
Full/Slow clock ratio 128
Oscillator frequency absolute accuracy @ 25°C Full Speed Clock -5 +5 %
Oscillator frequency variation over temperature
(-40°C to 85°C vs. ambient) —Slow Clock-6+6%
Minimum RESET assertion duration tRA —4T
(3)
3. In the formulas, T = 1 system clock cycle. In full speed mode, T is nominally 125 ns. In slow speed mode, T is nominally 16 μs.
——
VIH
VIL
Fall Time
Input Signal
Note: The midpoint is VIL + (VIH – VIL)/2.
Midpoint1
Low High 90%
50%
10%
Rise Time
Data Invalid State
Data1
Data
3-stated
Data3 Valid
Data2 Data3
Data1 Valid
Data Active Data Active
Data1 Valid
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20 Freescale Semiconductor, Inc.
4.13 I2C Timing
This device includes a slave I2C module that can be used to control the sensor and can be active 100 percent of the time. It also
includes a master/slave I2C module that should be used only during CPU run mode (ΦD).
Figure 9. I2C standard and fast-mode timing
4.13.1 Slave I2C
4.13.2 Master I2C Timing
The master I2C module should only be used when the system clock is running at full rate. The master I 2C should not be used
across frames when a portion of time is spent in low speed mode.
Table 12. I2C Speed Ranges
Mode Max Baud
Rate (fSCL)Min
Bit Time Min SCL Low
(tLOW)Min SCL High
(tHIGH)Min Data setup Time
(tSU; DAT)Min/Max Data Hold Time
(tHD; DAT)
Standard 100 KHz 10 μs4.7 μs4 μs 250 ns 0 μs/3.45 μs(1)
1. The maximum tHD; DAT must be at least a transmission time less than tVD;DAT or tVD;ACK. For details, see the I2C standard.
Fast 400 KHz 2.5 μs 1.3 μs0.6 μs 100 ns 0 μs/0.9 μs(1)
Fast + 1 MHz 1 μs 500 ns 260 ns 50 ns 0 μs/0.45 μs(1)
High-speed
supported 2.0 MHz 0.5 μs 200 ns 200 ns 10 ns(2) 0 ns/70 ns (100 pf)(2)
2. Timing met with IFE = 0, DS = 1, and SE = 1. See the “Port Controls” chapter in the MMA955xL Three-Axis Accelerometer Reference Manual
(MMA955xLRM).
Table 13. Master I2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Min Max Min Max
SCL clock frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START condition. After this period, the first
clock pulse is generated. tHD; STA 4.0 0.6 μs
LOW period of the SCL clock tLOW 4.7 1.3 μs
HIGH period of the SCL clock tHIGH 4.0 0.6 μs
Setup time for a repeated START condition tSU; STA 4.7 0.6 μs
Data hold time for I2C-bus devices tHD; DAT 0(1)
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling ed ge of SCL. If no slaves acknowledge t his address byte, a n eg-
ative hold time can result, depending on the edge rates of the SDA and SCL lines.
3.45(2)
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
0(1) 0.9(2) μs
Data setup time tSU; DAT 250(3)
3. Setup time in slave-transmitter mode is one IPBus clock period, if the TX FIFO is empty.
100(3) (4)
4. A fast-mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT 250 ns must then be met. This will automat-
ically be the case if th e devi ce doe s not str etch th e LOW pe riod of t he SCL sign al. If such a devi ce doe s stre tch the LOW per iod o f the SCL signal , it must
output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C bus specification) before the SCL
line is released.
—ns
Setup time for STOP condition tSU; STO 4.0 0.6 µs
Bus-free time between STOP and START condition tBUF 4.7 1.3 µs
Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns
SDA
SCL
tHD; STA tHD; DAT
tLOW tSU; DAT
tHIGH tSU; STA SR PS
S
tHD; STA tSP
tSU; STO
tBUF
tftrtftr
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Freescale Semiconductor, Inc. 21
4.14 Slave SPI Ti ming
The following table describes the timing requirements for the SPI system. The “#” column refers to the numbered time period in
Figure 10.
Figure 10. SPI slave timing
Table 14. Slave SPI timing
# Function Symbol Min Max Unit
Operating frequency fop 0F
OPH/4 Hz
1SCLK period tSCLK 4—t
CYCH
2Enable lead time tLead 0.5 tCYCH
3Enable lag time tLag 0.5 tCYCH
4Clock (SCLK) high or low time tWSCLK 200 ns
5Data-setup time (inputs) tSU 15 ns
6Data-hold time (inputs) tHI 25 ns
7Access time ta—25ns
8SDO-disable time tdis —25ns
9Data valid (after SCLK edge) tv—25ns
10 Data-hold time (outputs) tHO 0—ns
11 Rise time
Input
Output tRI
tRO
25
25 ns
ns
12 Fall time
Input
Output tFI
tFO
25
25 ns
ns
SCLK
(INPUT)
SDI
(INPUT)
SDO
(OUTPUT)
SS
(INPUT)
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LSB OUT
BIT 6 . . . 1
NOTE:
SLAVE SEE
NOTE
1. Not defined but normally MSB of character just received.
121
<
11 3
424
7
56
9
8
10
10
MMA955xL
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22 Freescale Semiconductor, Inc.
4.15 Flash Parameters
The MMA955xL platform has 16 KB of internal flash memory. There are ROM functions that allow reading, erasin g, and
programming of that memory. Chip supply voltage of 1.8 V is sufficient for the flash programming voltage.
The lower portion of the flash memory is occupied by Freescale factory firmware and is protected so that a user cannot erase it.
The size of the available flash memory varies between the different devices in the MMA955xL pr oduct family, as shown in the
following figure.
The smallest block of memory that can be written is 4 bytes and those 4 bytes must be aligned on a 4-byte boundary . The largest
block of memory that can be programmed is 128 bytes and the block must start at a 128-byte boundary.
Flash programming blocks must start on a 4-byte boundary and cannot cross a 128-byte page boundary.
Figure 11. Flash memo ry map for devic es
Table 15. Flash parameters
Parameter Value
Word depth 4096
Row size 128 bytes
Page erase size (Erase block size) 4 rows = 512 bytes
Maximum page programming size 1 row = 128 bytes
Minimum word programming size 4 bytes
Memory organization 4096 x 32 bits = 16 KB total
Endurance 20,000 cycles minimum
Data retention > 100 years, at room temperature
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MMA955xL
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Freescale Semiconductor, Inc. 23
5 Package Information
The MMA955xL platform uses a 16-lead LGA package, case number 2094.Use the following link for the latest diagram of the
package: www.freescale.com/files/shared/doc/package_info/98ASA00287D.pdf
5.1 Footprint and pattern information
Figure 12. Package bottom view
Figure 13. Package overlaid on PCB footprint diagra m (top view)
Package pad size
0.24mm x 0.35 mm
Pin 16
Pin 1 ID
Pin 1
Package size (Measurements in mm)
PCB land extension
From the edge of the package
PCB land pad
PCB pad distance
to package edge
MMA955xL
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24 Freescale Semiconductor, Inc.
Figure 14. Recomme nded PCB footprint
5.2 Marking
Solder mask opening Sol der stencil opening
0.777 mm x 1.377 mm 0.62 mm x 0.22 mm
(PCB land + 0.0637 mm (PCB land - 0.015 mm
larger all around. smaller all around)
Remove slivers between pads.)
PCB land pad size
0.65 mm x 0.25 mm
MMA955xL
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Freescale Semiconductor, Inc. 25
5.3 Tape and reel information
Figure 15. Tape dimensions
The devices are oriented on the tape as shown in Figure 16. The dot marked on each device indicates pin 1.
Figure 16. Tape and re e l orie ntation
Barcode label
side of reel
Pin 1
Direction
to unreel
MMA955xL
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26 Freescale Semiconductor, Inc.
6 Revision History
Revision
number Revision
date Description of changes
0 06/2011 Initial rele ase of document.
1 10/2011 Added the MMA9559L device.
Added a features table and a package lan d diagram figure.
Modified block diagram
Inserted flash memory map figure
2 5/2013 Removed MMA9550LT and MMA9551LT from Ordering Information table
Added Pedometer to MMA9553LR throughout
Added list of links to Related Documentation
User RAM available for MMA9553 was 200 bytes
Removed mobile phones from Typical Applications
Removed Dead reckoning from Typical Applications/Fleet monitoring, tracking
Added a pull-up resistor to Pin 2 of Figures 7, 8, and 9
Removed the Conditions column from Table 5
3 9/2013 Added Marking, Tape and reel, and Package dimensions
Moved Footprint and pattern info rmation from Package diagrams to Package Information
3.1 5/2015 Changed part number from MMA955xL to MMA9550L, MMA9551L, MMA9553L, and MMA9559L
Table 2, MMA9553L, User flash available changed from 1.5 KB to 1.0 KB
Table 2, MMA9553L, changed 304 bytes to 420 bytes in user RAM available
Section 1, Added sentence stating that MMA9555L data and functions are in a separate data
sheet
Section 3.3, Master I2C: SDA1 and SCL1: was ...master-I2C clock and data signals...
Figures 4, 5, and 6, Changed SBB to SSB
Section 3.4.3, added note
Document Number: MMA955xL
Rev. 3.1, 5/2015
Information in this document is provided solely to enable system and software
implementers to use Freescale produ cts. There are no express or implied copyright
licenses granted here under to design or f abri ca te any integr ate d circuit s b ased on the
information in this document.
Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representati on, or guarantee regarding the
suitability of its products for any particular purpose, nor does Freescale assume any
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disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in Freescale data sheets and/or
specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including “typicals,” must be validated for
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