34 .80 7IRELESS IMPORTANT NOTICE Dear customer, As from August 2nd 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document. Company name - Philips Semiconductors is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of each page "(c) Koninklijke Philips Electronics N.V. 200x. All rights reserved", shall now read: "(c) ST-NXP Wireless 200x All rights reserved". Web site - http://www.semiconductors.philips.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices previously obtained by sending an email to sales.addresses@www.semiconductors.philips.com, is now found at http://www.stnwireless.com under Contacts. If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless 34 .80 7IRELESS www.stnwireless.com ISP1160 Embedded Universal Serial Bus Host Controller Rev. 05 -- 24 December 2004 Product data 1. General description The ISP1160 is an embedded Universal Serial Bus (USB) Host Controller (HC) that complies with Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1160 provides two downstream ports. Each downstream port has an overcurrent (OC) detection input pin and power supply switching control output pin. The downstream ports for the HC can be connected with any USB compliant USB devices and USB hubs that have USB upstream ports. The ISP1160 is well suited for embedded systems and portable devices that require a USB host. The ISP1160 brings high flexibility to the systems that have it built-in. For example, a system that has the ISP1160 built-in allows it to be connected to a device that has a USB upstream port, such as a USB printer, USB camera, USB keyboard, USB mouse, among others. 2. Features Complies with Universal Serial Bus Specification Rev. 2.0 Supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) Adapted from Open Host Controller Interface Specification for USB Release 1.0a Selectable one or two downstream ports for HC High-speed parallel interface to most of the generic microprocessors and Reduced Instruction Set Computer (RISC) processors such as: Hitachi(R) SuperHTM SH-3 and SH-4 MIPS-basedTM RISC ARM7TM, ARM9TM, and StrongARM(R) Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC Supports single-cycle and burst mode DMA operations Built-in FIFO buffer RAM for the HC (4 kbytes) Endpoints with double buffering to increase throughput and ease real-time data transfer for isochronous (ISO) transactions 6 MHz crystal oscillator with integrated PLL for low EMI Built-in software selectable internal 15 k pull-down resistors for HC downstream ports Dedicated pins for suspend sensing output and wake-up control input for flexible applications Operation at either +5 V or +3.3 V power supply voltage Operating temperature range from -40 C to +85 C Available in two LQFP64 packages (SOT314-2 and SOT414-1). ISP1160 Philips Semiconductors Embedded USB Host Controller 3. Applications Personal Digital Assistant (PDA) Digital camera Third-generation (3-G) phone Set-Top Box (STB) Information Appliance (IA) Photo printer MP3 jukebox Game console. 4. Ordering information Table 1: Ordering information Type number ISP1160BD Package Name Description Version LQFP64 plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 LQFP64 plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm SOT414-1 ISP1160BD/01[1] ISP1160BM ISP1160BM/01[2] [1] [2] Improvement in performance as compared to ISP1160BD. Improvement in performance as compared to ISP1160BM. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 2 of 88 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x NDP_SEL ITL0 (PING RAM) 16 2 to 7, 9 to 14, 16, 17, 63, 64 Rev. 05 -- 24 December 2004 RD_N CS_N WR_N A0 DACK_N EOT DREQ INT RESET_N VCC ITL1 (PONG RAM) 47 OVERCURRENT DETECTION 54 55 50 USB TRANSCEIVER MICROPROCESSOR BUS INTERFACE HOST CONTROLLER USB TRANSCEIVER H_PSW2_N H_OC1_N H_OC2_N 51 52 53 H_DM1 H_DP1 H_DM2 USB bus downstream ports H_DP2 4x 15 k 32 POWER-ON RESET 56 internal reset VOLTAGE REGULATOR CLOCK RECOVERY 3.3 V internal supply PLL GND 7 DGND AGND 58 24 VREG(3V3) VHOLD2 44 19 XTAL2 VHOLD1 6 MHz 43 20, 26, 30, 31, 36, 38, 41, 48, 49, 61 XTAL1 10 n.c. 004aaa059 ISP1160 3 of 88 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 57 Embedded USB Host Controller CLOCK RECOVERY 1, 8, 15, 18, 35, 45, 62 Fig 1. Block diagram. H_PSW1_N ISP1160 D0 to D15 22 21 23 59 27 34 25 29 46 POWER SWITCHING ATL RAM 33 Philips Semiconductors 42 H_SUSPEND 5. Block diagram 9397 750 13963 Product data 40 H_WAKEUP ISP1160 Philips Semiconductors Embedded USB Host Controller 6. Pinning information 49 n.c. 50 H_DM1 51 H_DP1 52 H_DM2 53 H_DP2 54 H_OC1_N 55 H_OC2_N 56 VCC 57 AGND 58 VREG(3V3) 59 A0 60 LOW_PW 61 n.c. 62 DGND 63 D0 64 D1 6.1 Pinning DGND 1 48 n.c. D2 2 47 H_PSW2_N D3 3 46 H_PSW1_N D4 4 45 DGND D5 5 44 XTAL2 D6 6 43 XTAL1 ISP1160BD ISP1160BM ISP1160/01 1160/01(1) D7 7 DGND 8 D8 9 42 H_SUSPEND 41 n.c. 40 H_WAKEUP D9 10 39 TEST_LOW D10 11 38 n.c. D11 12 37 TEST_LOW D12 13 36 n.c. D13 14 35 DGND DGND 15 34 EOT D14 16 RESET_N 32 n.c. 31 n.c. 30 INT 29 TEST_HIGH 28 DACK_N 27 n.c. 26 DREQ 25 VHOLD2 24 WR_N 23 RD_N 22 CS_N 21 n.c. 20 DGND 18 VHOLD1 19 D15 17 33 NDP_SEL 004aaa060 (1) ISP1160/01 is the marking on the IC for the ISP1160BD/01 and 1160/01 is the marking on the IC for the ISP1160BM/01. Fig 2. Pin configuration LQFP64. 6.2 Pin description Table 2: Pin description LQFP64 Symbol[1] Pin Type Description DGND 1 - digital ground D2 2 I/O bit 2 of bidirectional data; slew-rate controlled; TTL input; three-state output D3 3 I/O bit 3 of bidirectional data; slew-rate controlled; TTL input; three-state output (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 4 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 2: Pin description LQFP64...continued Symbol[1] Pin Type Description D4 4 I/O bit 4 of bidirectional data; slew-rate controlled; TTL input; three-state output D5 5 I/O bit 5 of bidirectional data; slew-rate controlled; TTL input; three-state output D6 6 I/O bit 6 of bidirectional data; slew-rate controlled; TTL input; three-state output D7 7 I/O bit 7 of bidirectional data; slew-rate controlled; TTL input; three-state output DGND 8 - digital ground D8 9 I/O bit 8 of bidirectional data; slew-rate controlled; TTL input; three-state output D9 10 I/O bit 9 of bidirectional data; slew-rate controlled; TTL input; three-state output D10 11 I/O bit 10 of bidirectional data; slew-rate controlled; TTL input; three-state output D11 12 I/O bit 11 of bidirectional data; slew-rate controlled; TTL input; three-state output D12 13 I/O bit 12 of bidirectional data; slew-rate controlled; TTL input; three-state output D13 14 I/O bit 13 of bidirectional data; slew-rate controlled; TTL input; three-state output DGND 15 - digital ground D14 16 I/O bit 14 of bidirectional data; slew-rate controlled; TTL input; three-state output D15 17 I/O bit 15 of bidirectional data; slew-rate controlled; TTL input; three-state output DGND 18 - digital ground VHOLD1 19 - voltage holding pin 1; internally connected to the VREG(3V3) and VHOLD2 pins. When VCC is connected to 5 V, this pin will output 3.3 V, hence do not connect it to 5 V. When VCC is connected to 3.3 V, this pin can either be connected to 3.3 V or left unconnected. In all cases, decouple this pin to DGND. n.c. 20 - no connection; leave this pin open CS_N 21 I chip select input RD_N 22 I read strobe input WR_N 23 I write strobe input VHOLD2 24 - voltage holding pin 2; internally connected to the VREG(3V3) and VHOLD1 pins. When VCC is connected to 5 V, this pin will output 3.3 V, hence do not connect it to 5 V. When VCC is connected to 3.3 V, this pin can either be connected to 3.3 V or left unconnected. In all cases, decouple this pin to DGND. DREQ 25 O HC DMA request output (programmable polarity); signals to the DMA controller that the ISP1160 wants to start a DMA transfer; see Section 10.4.1 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 5 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 2: Pin description LQFP64...continued Symbol[1] Pin Type Description n.c. 26 - no connection; leave this pin open DACK_N 27 I HC DMA acknowledge input; when not in use, this pin must be connected to VCC via an external 10 k resistor TEST_HIGH 28 - this pin must be connected to VCC via an external 10 k resistor INT 29 O HC interrupt output; programmable level, edge triggered and polarity; see Section 10.4.1 n.c. 30 - no connection; leave this pin open n.c. 31 O no connection; leave this pin open RESET_N 32 I reset input (Schmitt trigger); a LOW level produces an asynchronous reset (internal pull-up resistor) NDP_SEL 33 I indicates to the HC software the Number of Downstream Ports (NDP) present: 0 -- select 1 downstream port 1 -- select 2 downstream ports only changes the value of the NDP field in the HcRhDescriptorA register; both ports will always be enabled; see Section 10.3.1 (internal pull-up resistor) EOT 34 I DMA master device to inform the ISP1160 of end of DMA transfer; active level is programmable; when not in use, this pin must be connected to VCC via an external 10 k resistor; see Section 10.4.1 DGND 35 - digital ground n.c. 36 - no connection; leave this pin open TEST_LOW 37 - this pin must be connected to DGND via an external 10 k resistor n.c. 38 - no connection; leave this pin open TEST_LOW 39 - this pin must be connected to DGND via a 1 M resistor H_WAKEUP 40 I HC wake-up input; generates a remote wake-up from the suspend state (active HIGH); when not in use, this pin must be connected to DGND via an external 10 k resistor (internal pull-down resistor) n.c. 41 - no connection; leave this pin open H_SUSPEND 42 O HC suspend state indicator output; active HIGH XTAL1 43 I crystal input; connected directly to a 6 MHz crystal; when this pin is connected to an external clock source, pin XTAL2 must be left open XTAL2 44 O crystal output; connected directly to a 6 MHz crystal; when pin XTAL1 is connected to an external clock source, this pin must be left open DGND 45 - digital ground H_PSW1_N 46 O power switching control output for downstream port 1; open-drain output (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 6 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 2: Pin description LQFP64...continued Symbol[1] Pin Type Description H_PSW2_N 47 O power switching control output for downstream port 2; open-drain output n.c. 48 - no connection; leave this pin open n.c. 49 - no connection; leave this pin open H_DM1 50 AI/O USB D- data line for HC downstream port 1 H_DP1 51 AI/O USB D+ data line for HC downstream port 1 H_DM2 52 AI/O USB D- data line for HC downstream port 2; when not in use, this pin must be left open H_DP2 53 AI/O USB D+ data line for HC downstream port 2; when not in use, this pin must be left open H_OC1_N 54 I overcurrent sensing input for HC downstream port 1 H_OC2_N 55 I overcurrent sensing input for HC downstream port 2 VCC 56 - digital power supply input (3.0 V to 3.6 V or 4.75 V to 5.25 V). This pin supplies the internal 3.3 V regulator input. When connected to 5 V, the internal regulator will output 3.3 V to pins VREG(3V3), VHOLD1 and VHOLD2. When connected to 3.3 V, it will bypass the internal regulator. AGND 57 - analog ground VREG(3V3) 58 - internal 3.3 V regulator output; when pin VCC is connected to 5 V, this pin outputs 3.3 V. When pin VCC is connected to 3.3 V, connect this pin to 3.3 V. A0 59 I address input; selects command (A0 = 1) or data (A0 = 0) LOW_PW 60 I if low-current consumption (range of s) is needed during suspend, connect this pin to address A2; otherwise, connect to DGND n.c. 61 - no connection; leave this pin open DGND 62 - digital ground D0 63 I/O bit 0 of bidirectional data; slew-rate controlled; TTL input; three-state output D1 64 I/O bit 1 of bidirectional data; slew-rate controlled; TTL input; three-state output [1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 7 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 7. Functional description 7.1 PLL clock multiplier A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external components are required for the operation of the PLL. 7.2 Bit clock recovery The bit clock recovery circuit recovers the clock from the incoming USB data stream by using a 4 times oversampling principle. It is able to track jitter and frequency drift as specified in Universal Serial Bus Specification Rev. 2.0. 7.3 Analog transceivers Two sets of transceivers are embedded in the chip for downstream ports with USB connector type A. The integrated transceivers are compliant with the Universal Serial Bus Specification Rev. 2.0. These transceivers interface directly with the USB connectors and cables through external termination resistors. 7.4 Philips Serial Interface Engine (SIE) The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel to serial conversion, bit (de)stuffing, CRC checking and generation, Packet IDentifier (PID) verification and generation, address recognition, and handshake evaluation and generation. 8. Microprocessor bus interface 8.1 Programmed I/O (PIO) addressing mode A generic PIO interface is defined for speed and ease-of-use. It also allows direct interfacing to most microcontrollers. To a microcontroller, the ISP1160 appears as a memory device with a 16-bit data bus and uses the A0 address line to access internal control registers and FIFO buffer RAM. Therefore, the ISP1160 occupies only two I/O ports or two memory locations of a microprocessor. External microprocessors can read from or write to the ISP1160's internal control registers and FIFO buffer RAM through the Programmed I/O (PIO) operating mode. Figure 3 shows the Programmed I/O interface between a microprocessor and the ISP1160. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 8 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller P bus I/F D [15:0] D [15:0] MICROPROCESSOR RD_N RD_N WR_N WR_N CS_N CS_N ISP1160 A0 A1 INT IRQ1 004aaa061 Fig 3. Programmed I/O interface between a microprocessor and the ISP1160. 8.2 DMA mode The ISP1160 also provides the DMA mode for external microprocessors to access its internal FIFO buffer RAM. Data can be transferred by the DMA operation between a microprocessor's system memory and the ISP1160's internal FIFO buffer RAM. Remark: The DMA operation must be controlled by the external microprocessor system's DMA controller (Master). Figure 4 shows the DMA interface between a microprocessor system and the ISP1160. The ISP1160 provides a DMA channel controlled by DREQ for DACK_N signals for the DMA transfer between a microprocessor's system memory and the ISP1160 HC's internal FIFO buffer RAM. The EOT signal is an external end-of-transfer signal used to terminate the DMA transfer. Some microprocessors may not have this signal. In this case, the ISP1160 provides an internal EOT signal to terminate the DMA transfer as well. Setting the HcDMAConfiguration register (21H to read, A1H to write) enables the ISP1160's HC internal DMA counter for the DMA transfer. When the DMA counter reaches the value set in the HcTransferCounter register (22H to read, A2H to write), an internal EOT signal will be generated to terminate the DMA transfer. P bus I/F MICROPROCESSOR D [15:0] D [15:0] RD_N RD_N WR_N WR_N ISP1160 DACK1_N DREQ1 EOT DACK_N DREQ EOT 004aaa062 Fig 4. DMA interface between a microprocessor and the ISP1160. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 9 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 8.3 Control registers access by PIO mode 8.3.1 I/O port addressing Table 3 shows the ISP1160's I/O port addressing. Complete decoding of the I/O port address should include the chip select signal CS_N and the address line A0. However, the direction of access of I/O ports is controlled by the RD_N and WR_N signals. When RD_N is LOW, the microprocessor reads data from the ISP1160's data port. When WR_N is LOW, the microprocessor writes a command to the command port, or writes data to the data port. Table 3: I/O port addressing Port CS_N A0 Access Data bus width (bits) Description 0 0 0 R/W 16 HC data port 1 0 1 W 16 HC command port Figure 5 illustrates how an external microprocessor accesses the ISP1160's internal control registers. CMD/DATA SWITCH 1 command port Host bus I/F data port Commands 0 Command register .. . A0 Control registers 004aaa075 When A0 = 0, microprocessor accesses the data port. When A0 = 1, microprocessor accesses the command port. Fig 5. Access to internal control registers. 8.3.2 Register access phases The ISP1160's register structure is a command-data register pair structure. A complete register access cycle comprises a command phase followed by a data phase. The command (also known as the index of a register) points the ISP1160 to the next register to be accessed. A command is 8 bits long. On a microprocessor's 16-bit data bus, a command occupies the lower byte, with the upper byte filled with zeros. Figure 6 shows a complete 16-bit register access cycle for the ISP1160. The microprocessor writes a command code to the command port, and then reads from or writes the data word to the data port. Take the example of a microprocessor attempting to read the ISP1160's ID, which is saved in the HC's HcChipID register (index 27H, read only). The 16-bit register access cycle is therefore: 1. The microprocessor writes the command code of 27H (0027H in 16-bit width) to the HC command port 2. The microprocessor reads the data word of the chip's ID from the HC data port. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 10 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 16-bit register access cycle write command (16 bits) read/write data (16 bits) t MGT937 Fig 6. 16-bit register access cycle. Most of the ISP1160's internal control registers are 16-bit wide. Some of the internal control registers, however, are 32-bit wide. Figure 7 shows how the ISP1160's 32-bit internal control register is accessed. The complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. In the two data phases, the microprocessor first reads or writes the lower 16-bit data, followed by the upper 16-bit data. 32-bit register access cycle write command (16 bits) read/write data (lower 16 bits) read/write data (upper 16 bits) t MGT938 Fig 7. 32-bit register access cycle. To further describe the complete access cycles of the internal control registers, the status of some pins of the microprocessor bus interface are shown in Figure 8. Signals CS_N A0 Valid status Valid status Valid status 0 0 0 1 0 0 RD_N, WR_N RD_N = 1, WR_N = 0 RD_N = 0 (read) or WR_N = 0 (write) RD_N = 0 (read) or WR_N = 0 (write) data bus Command code Register data (lower word) Register data (upper word) 004aaa370 Fig 8. Accessing HC control registers. 8.4 FIFO buffer RAM access by PIO mode Since the ISP1160's internal memory is structured as a FIFO buffer RAM, the FIFO buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal FIFO buffer RAM is similar to accessing the internal control registers in multiple data phases. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 11 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller FIFO buffer RAM access cycle (transfer counter = 2N) write command (16 bits) read/write data #1 (16 bits) read/write data #2 (16 bits) read/write data #N (16 bits) t MGT941 Fig 9. Internal FIFO buffer RAM access cycle. Figure 9 shows a complete access cycle of the HC internal FIFO buffer RAM. For a write cycle, the microprocessor first writes the FIFO buffer RAM's command code to the command port, and then writes the data words one by one to the data port until half of the transfer's byte count is reached. The HcTransferCounter register (22H to read, A2H to write) is used to specify the byte count of a FIFO buffer RAM's read cycle or write cycle. Every access cycle must be in the same access direction. The read cycle procedure is similar to the write cycle. 8.5 FIFO buffer RAM access by DMA mode The DMA interface between a microprocessor and the ISP1160 is shown in Figure 4. When doing a DMA transfer, at the beginning of every burst the ISP1160 outputs a DMA request to the microprocessor via pin DREQ. After receiving this signal, the microprocessor will reply with a DMA acknowledge to the ISP1160 via pin DACK_N, and at the same time, execute the DMA transfer through the data bus. In the DMA mode, the microprocessor must issue a read or write signal to the ISP1160's pins RD_N or WR_N. The ISP1160 will repeat the DMA cycles until it receives an EOT signal to terminate the DMA transfer. The ISP1160 supports both external and internal EOT signals. The external EOT signal is received as input on pin EOT, and generally comes from the external microprocessor. The internal EOT signal is generated inside the ISP1160. To select either EOT method, set the appropriate DMA configuration register (see Section 10.4.2). For example, setting DMACounterSelect (bit 2) of the HcDMAConfiguration register (21H to read, A1H to write) to logic 1 will enable the DMA counter for DMA transfer. When the DMA counter reaches the value of the HcTransferCounter register, the internal EOT signal will be generated to terminate the DMA transfer. The ISP1160 supports either single-cycle DMA operation or burst mode DMA operation; see Figure 10 and Figure 11. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 12 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller DREQ DACK_N RD_N or WR_N D [15:0 ] data #1 data #2 data #N EOT 004aaa368 N = 1/2 byte count of transfer data. Fig 10. DMA transfer in single-cycle mode. DREQ DACK_N RD_N or WR_N D [15:0 ] data #1 data #K data #(K+1) data #2K data #(N-K+1) data #N EOT 004aaa369 N = 1/2 byte count of transfer data, K = number of cycles/burst. Fig 11. DMA transfer in burst mode. In Figure 10 and Figure 11, the DMA transfer is configured such that DREQ is active HIGH and DACK_N is active LOW. 8.6 Interrupts The ISP1160 has an interrupt request pin INT. 8.6.1 Pin configuration The interrupt output signals have four configuration modes: Mode 0 Mode 0 level trigger, active LOW Mode 1 Mode 1 level trigger, active HIGH Mode 2 Mode 2 edge trigger, active LOW Mode 3 Mode 3 edge trigger, active HIGH. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 13 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Figure 12 shows these four interrupt configuration modes. They are programmable through the HcHardware Configuration register (see Section 10.4.1), which is also used to disable or enable the signals. INT active clear or disable INT INT Mode 0 level triggered, active LOW INT active clear or disable INT INT Mode 1 level triggered, active HIGH INT active INT 166 ns Mode 2 edge triggered, active LOW INT active INT 166 ns MGT944 Mode 3 edge triggered, active HIGH Fig 12. Interrupt pin operating modes. 8.6.2 Interrupt output pin (INT) To program the four configuration modes of the HC's interrupt output signal (INT), set InterruptPinTrigger and InterruptOutputPolarity (bits 1 and 2) of the HcHardwareConfiguration register (20H to read, A0H to write). InterruptPinEnable (bit 0) is used as the master enable setting for pin INT. INT has many associated interrupt events as shown as in Figure 13. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 14 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller ClkReady OPR_Reg HCSuspended ATLInt SOFITLInt ClkReady OPR_Reg HcPInterruptEnable register AllEOTInterrupt MIE HCSuspended ATLInt HcInterruptEnable register AllEOTInterrupt SOFITLInt HcPInterrupt register RHSC FNO UE OR RD SF group 1 SO RHSC group 2 OR FNO HcHardwareConfiguration register UE RD SF LE INT LATCH SO InterruptPinEnable 004aaa102 HcInterruptStatus register Fig 13. HC interrupt logic. There are two groups of interrupts represented by group 1 and group 2 in Figure 13. A pair of registers control each group. Group 2 contains six possible interrupt events (recorded in the HcInterruptStatus register). On occurrence of any of these events, the corresponding bit would be set to logic 1; and if the corresponding bit in the HcInterruptEnable register is also logic 1, the 6-input OR gate would output a logic 1. This output is AND-ed with the value of MIE (bit 31 of HcInterruptEnable). Logic 1 at the AND gate will cause the OPR bit in the HcPInterrupt register to be set to logic 1. Group 1 contains six possible interrupt events, one of which is the output of group 2 interrupt sources. The HcPInterrupt and HcPInterruptEnable registers work in the same way as the HcInterruptStatus and HcInterruptEnable registers in the interrupt group 2. The output from the 6-input OR gate is connected to a latch, which is controlled by InterruptPinEnable (bit 0 of the HcHardwareConfiguration register). In the event in which the software wishes to temporarily disable the interrupt output of the ISP1160 Host Controller, the following procedure should be followed: 1. Make sure that the InterruptPinEnable bit in the HcHardwareConfiguration register is set to logic 1. 2. Clear all bits in the HcPInterrupt register. 3. Set the InterruptPinEnable bit to logic 0. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 15 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller To re-enable the interrupt generation: 1. Set all bits in the HcPInterrupt register. 2. Set the InterruptPinEnable bit to logic 1. Remark: The InterruptPinEnable bit in the HcHardwareConfiguration register latches the interrupt output. When this bit is set to logic 0, the interrupt output will remain unchanged, regardless of any operations on the interrupt control registers. If INT1 is asserted, and the Host Controller Driver (HCD) wishes to temporarily mask off the INT signal without clearing the HcPInterrupt register, the following procedure should be followed: 1. Make sure that the InterruptPinEnable bit is set to logic 1. 2. Clear all bits in the HcPInterruptEnable register. 3. Set the InterruptPinEnable bit to logic 0. To re-enable the interrupt generation: 1. Set all bits in the HcPInterruptEnable register according to the HCD requirements. 2. Set the InterruptPinEnable bit to logic 1. 9. Host Controller (HC) 9.1 HC's four USB states The ISP1160's USB HC has four USB states--USBOperational, USBReset, USBSuspend and USBResume--that define the HC's USB signalling and bus states responsibilities. The signals are visible to the Host Controller Driver (HCD) via the ISP1160 USB HC's control registers. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 16 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller USBOperational USBReset write USBOperational write USBReset write USBOperational write USBResume USBReset USBSuspend write hardware or software reset USBResume write or remote wake-up USBReset write MGT947 USBSuspend Fig 14. The ISP1160 HC's USB states. The USB states are reflected in the HostControllerFunctionalState field of the HcControl register (01H to read, 81H to write), which is located at bits 7 and 6 of the register. The HCD can perform only the USB state transitions shown in Figure 14. Remark: The Software Reset in Figure 14 is not caused by the HcSoftwareReset command. It is caused by the HostControllerReset field of the HcCommandStatus register (02H to read, 82H to write). 9.2 Generating USB traffic USB traffic can be generated only when the ISP1160 USB HC is in the USBOperational state. Therefore, the HCD must set the HostControllerFunctionalState field of the HcControl register before generating USB traffic. A simplistic flow diagram showing when and how to generate USB traffic is shown in Figure 15. For greater accuracy, refer to the Universal Serial Bus Specification Rev. 2.0 for the USB protocol and the ISP1160 USB HC's register usage. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 17 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Reset Exit no Initialize HC Entry HC state = USBOperational Need USB traffic? HC informs HCD of USB traffic results yes Prepare PTD data in P system RAM Transfer PTD data into HC FIFO buffer RAM HC performs USB transactions via USB bus I/F HC interprets PTD data MGT948 Fig 15. ISP1160 HC USB transaction loop. Description of Figure 15: 1. Reset This includes hardware reset by pin RESET_N and software reset by the HcSoftwareReset command (A9H). The reset function will clear all the HC's internal control registers to their reset status. After reset, the HCD must initialize the ISP1160 USB HC by setting some registers. 2. Initialize HC It includes: a. Setting the physical size for the HC's internal FIFO buffer RAM by setting the HcITLBufferLength register (2AH to read, AAH to write) and the HcATLBufferLength register (2BH to read, ABH to write). b. Setting the HcHardwareConfiguration register according to requirements. c. Clearing interrupt events, if required. d. Enabling interrupt events, if required. e. Setting the HcFmInterval register (0DH to read, 8DH to write). f. Setting the HC's Root Hub registers. g. Setting the HcControl register to move the HC into the USBOperational state. See also Section 9.5. 3. Entry The normal entry point. The microprocessor returns to this point when there are HC requests. 4. Need USB traffic USB devices need the HC to generate USB traffic when they have USB traffic requests such as: a. Connecting to or disconnecting from downstream ports b. Issuing the Resume signal to the HC. To generate USB traffic, the HCD must enter the USB transaction loop. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 18 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 5. Prepare PTD data in P system RAM The communication between the HCD and the ISP1160 HC is in the form of Philips Transfer Descriptor (PTD) data. The PTD data provides USB traffic information about the commands, status and USB data packets. The physical storage media of PTD data for the HCD is the microprocessor's system RAM. For the ISP1160's HC, the storage media is the internal FIFO buffer RAM. The HCD prepares PTD data in the microprocessor's system RAM for transfer to the ISP1160's HC internal FIFO buffer RAM. 6. Transfer PTD data into HC's FIFO buffer RAM When PTD data is ready in the microprocessor's system RAM, the HCD must transfer the PTD data from the microprocessor's system RAM into the ISP1160's internal FIFO buffer RAM. 7. HC interprets PTD data The HC determines what USB transactions are required based on the PTD data that has been transferred into the internal FIFO buffer RAM. 8. HC performs USB transactions via USB bus interface The HC performs the USB transactions with the specified USB device endpoint through the USB bus interface. 9. HC informs HCD of the USB traffic results The USB transaction status and the feedback from the specified USB device endpoint will be put back into the ISP1160's HC internal FIFO buffer RAM in PTD data format. The HCD can read back the PTD data from the internal FIFO buffer RAM. 9.3 PTD data structure The Philips Transfer Descriptor (PTD) data structure provides communication between the HCD and the ISP1160's USB HC. The PTD data contains information required by the USB traffic. PTD data consists of a PTD followed by its payload data, as shown in Figure 16. FIFO buffer RAM top PTD PTD data #1 payload data PTD PTD data #2 payload data PTD PTD data #N payload data bottom MGT949 Fig 16. PTD data in FIFO buffer RAM. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 19 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller The PTD data structure is used by the HC to define a buffer of data that will be moved to or from an endpoint in the USB device. This data buffer is set up for the current frame (1 ms frame) by the HCD. The payload data for every transfer in the frame must have a PTD as the header to describe the characteristic of the transfer. The PTD data is DWORD (double-word or 4-byte) aligned. 9.3.1 PTD data header definition The PTD forms the header of the PTD data. It tells the HC the transfer type, where the payload data should go, and the actual size of the payload data. A PTD is an 8-byte data structure that is very important for HCD programming. Table 4: Philips Transfer Descriptor (PTD): bit allocation Bit 7 6 5 Byte 0 Byte 1 Active EndpointNumber[3:0] Byte 4 Byte 7 1 0 Toggle ActualBytes[9:8] Last Speed MaxPacketSize[9:8] TotalBytes[7:0] reserved Format B5_5 reserved DirectionPID[1:0] TotalBytes[9:8] FunctionAddress[6:0] reserved (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data 2 MaxPacketSize[7:0] Byte 3 Byte 6 3 CompletionCode[3:0] Byte 2 Byte 5 4 ActualBytes[7:0] Rev. 05 -- 24 December 2004 20 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 5: Philips Transfer Descriptor (PTD): bit description Symbol Access Description ActualBytes[9:0] R/W Contains the number of bytes that were transferred for this PTD. CompletionCode[3:0] R/W 0000 NoError General TD or isochronous data packet processing completed with no detected errors. 0001 CRC Last data packet from endpoint contained a CRC error. 0010 BitStuffing Last data packet from endpoint contained a bit stuffing violation. 0011 DataToggleMismatch Last packet from endpoint had data toggle PID that did not match the expected value. 0100 Stall TD was moved to the Done queue because the endpoint returned a STALL PID. 0101 DeviceNotResponding Device did not respond to token (IN) or did not provide a handshake (OUT). 0110 PIDCheckFailure Check bits on PID from endpoint failed on data PID (IN) or handshake (OUT). 0111 UnexpectedPID Received PID was not valid when encountered or PID value is not defined. 1000 DataOverrun The amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint (found in the MaximumPacketSize field of endpoint descriptor) or the remaining buffer size. 1001 DataUnderrun The endpoint returned is less than MaximumPacketSize and that amount was not sufficient to fill the specified buffer. 1010 reserved - 1011 reserved - 1100 BufferOverrun During an IN, the HC received data from an endpoint faster than it could be written to system memory. 1101 BufferUnderrun During an OUT, the HC could not retrieve data from the system memory fast enough to keep up with the USB data rate. Active R/W Set to logic 1 by firmware to enable the execution of transactions by the HC. When the transaction associated with this descriptor is completed, the HC sets this bit to logic 0, indicating that a transaction for this element will not be executed when it is next encountered in the schedule. Toggle R/W Used to generate or compare the data PID value (DATA0 or DATA1). It is updated after each successful transmission or reception of a data packet. MaxPacketSize[9:0] R The maximum number of bytes that can be sent to or received from the endpoint in a single data packet. EndpointNumber[3:0] R USB address of the endpoint within the function. Last R Last PTD of a list (ITL or ATL). Logic 1 indicates that the PTD is the last PTD. Speed R Speed of the endpoint: 0 -- full speed 1 -- low speed TotalBytes[9:0] R Specifies the total number of bytes to be transferred with this data structure. For Bulk and Control only, this can be greater than MaximumPacketSize. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 21 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 5: Philips Transfer Descriptor (PTD): bit description...continued Symbol Access DirectionPID[1:0] R Description 00 SETUP 01 OUT 10 IN 11 reserved B5_5 R/W This bit is logic 0 at power-on reset. When this feature is not used, software used for the ISP1160 is the same for the ISP1161 and the ISP1161A. When this bit is set to logic 1 in this PTD for interrupt endpoint transfer, only one PTD USB transaction will be sent out in 1 ms. Format R The format of this data structure. If this is a Control, Bulk or Interrupt endpoint, then Format = 0. If this is an Isochronous endpoint, then Format = 1. FunctionAddress[6:0] R This is the USB address of the function containing the endpoint that this PTD refers to. 9.4 HC's internal FIFO buffer RAM structure 9.4.1 Partitions According to the Universal Serial Bus Specification Rev. 2.0, there are four types of USB data transfers: Control, Bulk, Interrupt and Isochronous. The HC's internal FIFO buffer RAM has a physical size of 4 kbytes. This internal FIFO buffer RAM is used for transferring data between the microprocessor and USB peripheral devices. This on-chip buffer RAM can be partitioned into two areas: Acknowledged Transfer List (ATL) buffer and Isochronous (ISO) Transfer List (ITL) buffer. The ITL buffer is a Ping-Pong structured FIFO buffer RAM that is used to keep the payload data and their PTD header for Isochronous transfers. The ATL buffer is a non Ping-Pong structured FIFO buffer RAM that is used for the other three types of transfers. The ITL buffer can be further partitioned into ITL0 and ITL1 for the Ping-Pong structure. The ITL0 and ITL1 buffers always have the same size. The microprocessor can put ISO data into either the ITL0 buffer or the ITL1 buffer. When the microprocessor accesses an ITL buffer, the HC can take over the other ITL buffer at the same time. This architecture improves the ISO transfer performance. The HCD can assign the logical size for the ATL buffer and ITL buffers at any time, but normally at initialization after power-on reset. This is done by setting the HcATLBufferLength register (2BH to read, ABH to write) and the HcITLBufferLength register (2AH to read, AAH to write), respectively. The total length (ATL buffer + ITL buffer) should not exceed the maximum RAM size of 4 kbytes. Figure 17 shows the partitions of the internal FIFO buffer RAM. When assigning buffer RAM sizes, follow this formula: ATL buffer length + 2 x (ITL buffer size) 1000H (that is, 4 kbytes) where: ITL buffer size = ITL0 buffer length = ITL1 buffer length The following assignments are examples of legal uses of the internal FIFO buffer RAM: * ATL buffer length = 800H, ITL buffer length = 400H. This is the maximum use of the internal FIFO buffer RAM. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 22 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller * ATL buffer length = 400H, ITL buffer length = 200H. This is insufficient use of the internal FIFO buffer RAM. * ATL buffer length = 1000H, ITL buffer length = 0H. This will use the internal FIFO buffer RAM for only ATL transfers. FIFO buffer RAM top ITL0 ISO_A ITL1 ISO_B ITL buffer programmable sizes ATL buffer ATL control/bulk/interrupt data not used bottom 4 kbytes MGT950 Fig 17. HC internal FIFO buffer RAM partitions. The actual requirement for the buffer RAM needs to reach not the maximum size. You can make your selection based on your application. The following are some calculations of the ISO_A or ISO_B space for a frame of data: * Maximum number of useful data sent during one USB frame is 1280 bytes (20 ISO packets of 64 bytes). The total RAM size needed is: 20 x 8 + 1280 = 1440 bytes. * Maximum number of packets for different endpoints sent during one USB frame is 150 (150 ISO packets of 1 byte). The total RAM size needed is: 150 x 8 + 150 x 1 = 1350 bytes. * The Ping buffer RAM (ITL0) and the Pong buffer RAM (ITL1) have a maximum size of 2 kbytes each. All data needed for one frame can be stored in the Ping or the Pong buffer RAM. When the embedded system wants to initiate a transfer to the USB bus, the data needed for one frame is transferred to the ATL buffer or the ITL buffer. The microprocessor detects the buffer status through interrupt routines. When the HcBufferStatus register (2CH to read only) indicates that the buffer is empty, then the microprocessor writes data into the buffer. When the HcBufferStatus register indicates that the buffer is full, the data is ready on the buffer, and the microprocessor needs to read data from the buffer. For every 1 ms, there might be many events to generate interrupt requests to the microprocessor for data transfer or status retrieval. However, each of the interrupt types defined in this specification can be enabled or disabled by setting HcPInterruptEnable register bits accordingly. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 23 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller The data transfer can be done via the PIO mode or the DMA mode. The data transfer rate can go up to 15 Mbyte/s. In the DMA operation, the single-cycle or multi-cycle burst modes are supported. Multi-cycle burst modes of 1, 4 or 8 cycles per burst are supported for the ISP1160. 9.4.2 Data organization PTD data is used for every data transfer between a microprocessor and the USB bus, and the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the payload data is placed just after the PTD, after which the next PTD is placed. For an IN transfer, RAM space is reserved for receiving a number of bytes that is equal to the total bytes of the transfer. After this, the next PTD and its payload data are placed (see Figure 18). Remark: The PTD is defined for both the ATL and ITL type data transfer. For ITL, the PTD data is put into ITL buffer RAM, and the ISP1160 takes care of the Ping-Pong action for the ITL buffer RAM access. RAM buffer top 000H PTD of OUT transfer payload data of OUT transfer PTD of IN transfer empty space for IN total data PTD of OUT transfer payload data of OUT transfer bottom 7FFH MGT952 Fig 18. Buffer RAM data organization. The PTD data (PTD header and its payload data) is a structure of DWORD alignment. This means that the memory address is organized in blocks of 4 bytes. Therefore, the first byte of every PTD and the first byte of every payload data are located at an address that is a multiple of 4. Figure 19 illustrates an example in which the first payload data is 14 bytes long, meaning that the last byte of the payload data is at the location 15H. The next addresses (16H and 17H) are not multiples of 4. Therefore, the first byte of the next PTD will be located at the next multiple-of-four address (18H). (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 24 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller RAM buffer top 00H PTD (8 bytes) 08H payload data (14 bytes) 15H 18H PTD (8 bytes) 20H payload data MGT953 Fig 19. PTD data with DWORD alignment in buffer RAM. 9.4.3 Operation and C program example Figure 20 shows the block diagram for internal FIFO buffer RAM operations in the PIO mode. The ISP1160 provides one register as the access port for each buffer RAM. For the ITL buffer RAM, the access port is the ITLBufferPort register (40H to read, C0H to write). For the ATL buffer RAM, the access port is the ATLBufferPort register (41H to read, C1H to write). The buffer RAM is an array of bytes (8 bits) while the access port is a 16-bit register. Therefore, each read/write operation on the port accesses two consecutive memory locations, incrementing the pointer of the internal buffer RAM by two. The lower byte of the access port register corresponds to the data byte at the even location of the buffer RAM, and the upper byte corresponds to the next data byte at the odd location of the buffer RAM. Regardless of the number of data bytes to be transferred, the command code must be issued merely once, and it will be followed by a number of accesses of the data port (see Section 8.4). When the pointer of the buffer RAM reaches the value of the HcTransferCounter register, an internal EOT signal will be generated to set bit 2, AllEOTInterrupt, of the HcPInterrupt register and update the HcBufferStatus register, to indicate that the whole data transfer has been completed. For ITL buffer RAM, every start of frame (SOF) signal (1 ms) will cause toggling between ITL0 and ITL1 but this depends on the buffer status. If both ITL0BufferFull and ITL1BufferFull of the HcBufferStatus register are already logic 1, meaning that both ITL0 and ITL1 buffer RAMs are full, the toggling will not happen. In this case, the microprocessor will always have access to ITL1. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 25 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 1 command port Host bus I/F Control registers data port Commands 0 Command register A0 22H/A2H TransferCounter EOT 24H/A4H PInterrupt 2 2CH BufferStatus = 40H/C0H ITLBufferPort 41H/C1H ATLBufferPort 0 1 internal EOT (16-bit width) toggle SOF T 000H 000H BufferStatus 000H Pointer automatically increments by 2 001H 001H 001H 3FFH 3FFH 7FFH ITL0 buffer RAM (8-bit width) ITL1 buffer RAM (8-bit width) ATL buffer RAM (8-bit width) MGT951 Fig 20. PIO access to internal FIFO buffer RAM. Following is an example of a C program that shows how to write data into the ATL buffer RAM. The total number of data bytes to be transferred is 80 (decimal) that will be set into the HcTransferCounter register as 50H. The data consists of four types of PTD data: 1. The first PTD header (IN) is 8 bytes, followed by 16 bytes of space reserved for its payload data; 2. The second PTD header (IN) is also 8 bytes, followed by 8 bytes of space reserved for its payload data; 3. The third PTD header (OUT) is 8 bytes, followed by 16 bytes of payload data with values beginning from 0H to FH incrementing by 1; 4. The fourth PTD header (OUT) is also 8 bytes, followed by 8 bytes of payload data with values beginning from 0H to EH incrementing by 2. In all PTDs, we have assigned device address as 5 and endpoint 1. ActualBytes is always zero (0). TotalBytes equals the number of payload data bytes transferred. However, note that for bulk and control transfers, TotalBytes can be greater than MaxPacketSize. Table 6 shows the results after running this program. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 26 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller However, if communication with a peripheral USB device is desired, the device should be connected to the downstream port and pass enumeration. //The example program for writing ATL buffer RAM #include <conio.h> #include <stdio.h> #include <dos.h> //Define register commands #define wHcTransferCounter 0x22 #define wHcuPInterrupt 0x24 #define wHcATLBufferLength 0x2b #define wHcBufferStatus 0x2c // Define I/O Port Address for HC #define HcDataPort 0x290 #define HcCmdPort 0x292 //Declare external functions to be used unsigned int HcRegRead(unsigned int wIndex); void HcRegWrite(unsigned int wIndex,unsigned int wValue); void main(void) { unsigned int i; unsigned int wCount,wData; // Prepare PTD data to be written into HC ATL buffer RAM: unsigned int PTDData[0x28]= { 0x0800,0x1010,0x0810,0x0005, //PTD header for IN token #1 //Reserved space for payload data of IN token #1 0x0000,0x0000,0x0000,0x0000, 0x0000,0x0000,0x0000,0x0000, 0x0800,0x1008,0x0808,0x0005, //PTD header for IN token #2 //Reserved space for payload data of IN token #2 0x0000,0x0000,0x0000,0x0000, 0x0800,0x1010,0x0410,0x0005, //PTD header for OUT token #1 0x0100,0x0302,0x0504,0x0706, //Payload data for OUT token #1 0x0908,0x0b0a,0x0d0c,0x0f0e, 0x0800,0x1808,0x0408,0x0005, //PTD header for OUT token #2 0x0200,0x0604,0x0a08,0x0e0c //Payload data for OUT token #2 }; HcRegWrite(wHcuPInterrupt,0x04); //Clear EOT interrupt bit //HcRegWrite(wHcITLBufferLength,0x0); HcRegWrite(wHcATLBufferLength,0x1000); //RAM full use for ATL //Set the number of bytes to be transferred HcRegWrite(wHcTransferCounter,0x50); wCount = 0x28; //Get word count outport (HcCmdPort,0x00c1); //Command for ATL buffer write (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 27 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller //write 80 (0x50) bytes of data into ATL buffer RAM for (i=0;i<wCount;i++) { outport(HcDataPort,PTDData[i]); }; //Check EOT interrupt bit wData = HcRegRead(wHcuPInterrupt); printf("\n HC Interrupt Status = %xH.\n",wData); //Check Buffer status register wData = HcRegRead(wHcBufferStatus); printf("\n HC Buffer Status = %xH.\n",wData); } // // Read HC 16-bit registers // unsigned int HcRegRead(unsigned int wIndex) { unsigned int wValue; outport(HcCmdPort,wIndex & 0x7f); wValue = inport(HcDataPort); return(wValue); } // // Write HC 16-bit registers // void HcRegWrite(unsigned int wIndex,unsigned int wValue) { outport(HcCmdPort,wIndex | 0x80); outport(HcDataPort,wValue); } Table 6: Run results of the C program example Observed items HC not initialized and not in HC initialized and in USBOperational state USBOperational state Comments HcPInterrupt register Bit 1 (ATLInt) 0 1 microprocessor must read ATL Bit 2 (AllEOTInterrupt) 1 1 transfer completed Bit 2 (ATLBufferFull) 1 1 transfer completed Bit 5 (ATLBufferDone) 0 1 PTD data processed by HC USB traffic on USB Bus no yes HcBufferStatus register OUT packets can be seen 9.5 HC operational model Upon power up, the HCD sets up all operational registers (32-bit). The FSLargestDataPacket field (bits 30 to 16) of the HcFmInterval register (0DH to read, 8DH to write) and the HcLSThreshold register (11H to read, 91H to write) determine (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 28 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller the end of the frame for full-speed and low-speed packets. By programming these fields, the effective USB bus usage can be changed. Furthermore, the size of the ITL buffers (HcITLBufferLength, 2AH to read, AAH to write) is programmed. If a USB frame contains both ISO and AT packets, two interrupts will be generated per frame. One interrupt is issued concurrently with the SOF. This interrupt (ITLInt is set in the HcPInterrupt register) triggers reading and writing of the ITL buffer by the microprocessor, after which the interrupt is cleared by the microprocessor. Next the programmable ATL Interrupt (bit ATLInt is set in the HcPInterrupt register) is issued, which triggers reading and writing of the ATL buffer by the microprocessor, after which the interrupt is cleared by the microprocessor. If the microprocessor cannot handle the ISO interrupt before the next ISO interrupt, disrupted ISO traffic can result. To be able to send more than one packet to the same Control or Bulk endpoint in the same frame, the Active bit and the TotalBytes field are introduced (see Table 5). Bit Active is cleared only if all data of the Philips Transfer Descriptor (PTD) have been transferred or if a transaction at that endpoint contained a fatal error. If all PTDs of the ATL are serviced once and the frame is not over yet, the HC starts looking for a PTD with bit Active still set. If such a PTD is found and there is still enough time in this frame, another transaction is started on the USB bus for this endpoint. For ISO processing, the HCD also has to take care of the BufferStatus register (2CH, read only) for the ITL buffer RAM operations. After the HCD writes ISO data into ITL buffer RAM, the ITL0BufferFull or ITL1BufferFull bit (depending on whether it is ITL0 or ITL1) will be set to logic 1. After the HC processes the ISO data in the ITL buffer RAM, the corresponding ITL0BufferDone or ITL1BufferDone bit will automatically be set to logic 1. The HCD can clear the buffer status bits by a read of the ITL buffer RAM. This must be done within the 1 ms frame from which ITL0BufferDone or ITL1BufferDone was set. Failure to do so will cause the ISO processing to stop and a power-on reset or software reset will have to be applied to the HC, a USB reset to the USB bus must not be made. For example, the HCD writes ISO_A data into the ITL0 buffer in the first frame. This will cause the HcBufferStatus register to show that the ITL0 buffer is full by setting bit ITL0BufferFull to logic 1. At this stage, the HCD cannot write ISO data into the ITL0 buffer RAM again. In the second frame, the HC will process the ISO_A data in the ITL0 buffer. At the same time, the HCD can write ISO_B data into the ITL1 buffer. When the next SOF comes (the beginning of the third frame), both ITL1BufferFull and ITL0BufferDone are automatically set to logic 1. In the third frame, the HCD has to read at least two bytes (one word) of the ITL0 buffer to clear both the ITL0BufferFull and ITL0BufferDone bits. If both are not cleared, when the next SOF comes (the beginning of the fourth frame) the (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 29 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller ITL0BufferDone and ITL0BufferFull bits will be cleared automatically. This also applies to the ITL1 buffer because ITL0 and ITL1 are Ping-Pong structured buffers. To recover from this state, a power-on reset or software reset will have to be applied. 9.5.1 Time domain behavior In example 1 (Figure 21), the CPU is fast enough to read back and download a scenario before the next interrupt. Note that on the ISO interrupt of frame N: * The ISO packet for frame N + 1 will be written * The AT packet for frame N + 1 will be written. AT interrupt traffic on USB SOF (frame N) (frame N + 1) (frame N + 2) (frame N + 3) MGT954 ISO interrupt read ISO_A(N - 1) write ISO_A(N + 1) read AT(N) write AT(N + 1) Fig 21. HC time domain behavior: example 1. In example 2 (Figure 22), the microprocessor is still busy transferring the AT data when the ISO interrupt of the next frame (N + 1) is raised. As a result, there will be no AT traffic in frame N + 1. The HC does not raise an AT interrupt in frame N + 1. The AT part is simply postponed until frame N + 2. On the AT N + 2 interrupt, the transfer mechanism is back to the normal operation. This simple mechanism ensures, among other things, that Control transfers are not dropped systematically from the USB in case of an overloaded microprocessor. (frame N) (frame N + 1) (frame N + 2) (frame N + 3) MGT955 Fig 22. HC time domain behavior: example 2. In example 3 (Figure 23), the ISO part is still being written while the Start of Frame (SOF) of the next frame has occurred. This will result in undefined behavior for the ISO data on the USB bus in frame N + 1 (depending on whether the exact timing data is corrupted or not). The HC should not raise an AT interrupt in frame N + 1. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 30 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller (frame N) (frame N + 1) (frame N + 2) (frame N + 3) MGT956 Fig 23. HC time domain behavior: example 3. 9.5.2 Control transaction limitations The different phases of a Control transfer (SETUP, Data and Status) should never be put in the same ATL. 9.6 Microprocessor loading The maximum amount of data that can be transferred for an endpoint in one frame is 1023 bytes. The number of USB packets that are needed for this batch of data depends on the maximum packet size that is specified. The HCD has to schedule the transactions in a frame. On the other hand, the microprocessor must have the ability to handle the interrupts coming from the HC every 1 ms. It must also be able to do the scheduling for the next frame, reading the frame information from and writing the next frame information to the buffer RAM in the time between the end of the current frame and the start of the next frame. 9.7 Internal pull-down resistors for downstream ports There are four internal 15 k pull-down resistors built in the ISP1160 for the two downstream ports: two resistors for each port. These resistors are software selectable by programming bit 12 (2_DownstreamPort15Kresistorsel) of the HcHardwareConfiguration register (20H to read, A0H to write). When bit 12 is logic 0, external 15 k pull-down resistors are used. When bit 12 is logic 1, internal 15 k pull-down resistors are used. See Figure 24. This feature is a cost-saving option. However, the power-on reset default value of bit 12 is logic 0. If using the internal resistors, the HCD must check this bit status after every reset, because a reset action (hardware or software) will clear this bit. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 31 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller VBUS USB connector ISP1160 D- 22 D+ 22 HcHardware Configuration bit 12 47 pF (2x) external 15 k (2x) internal 15 k (2x) 004aaa064 Using either internal or external 15 k resistors. Fig 24. Use of 15 k pull-down resistors on downstream ports. 9.8 Overcurrent detection and power switching control A downstream port provides 5 V power supply to VBUS. The ISP1160 has built-in hardware functions to monitor the downstream ports loading conditions and control their power switching. These hardware functions are implemented by the internal power switching control circuit and overcurrent detection circuit. H_PSW1_N and H_PSW2_N are power switching control output pins (active LOW, open-drain) for downstream ports 1 and 2, respectively. H_OC1_N and H_OC2_N are overcurrent detection input pins for downstream ports 1 and 2, respectively. Figure 25 shows the ISP1160 downstream port power management scheme. regulator HC CORE V CC (+5 V or +3.3 V) OC detect H_OCn_N HcHardware Configuration OC select bit 10 1 0 Reg PSW H_PSWn_N C/L ISP1160 004aaa065 'n' represents the downstream port numbers (n = 1 or 2). Fig 25. Downstream port power management scheme. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 32 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 9.8.1 Using an internal OC detection circuit The internal OC detection circuit can be used only when VCC (pin 56) is connected to a 5 V power supply. The HCD must set AnalogOCEnable, bit 10 of the HcHardwareConfiguration register, to logic 1. An application using the internal OC detection circuit and internal 15 k pull-down resistors is shown in Figure 26. In this example, the HCD must set both AnalogOCEnable and DownstreamPort15Kresistorsel to logic 1. They are bit 10 and bit 12 of the HcHardwareConfiguration register, respectively. When H_OCn_N detects an overcurrent status on a downstream port, H_PSWn_N will output HIGH, a logic 1 to turn off the 5 V power supply to the downstream port VBUS. When there is no such detection, H_PSWn_N will output LOW, a logic 0 to turn on the 5 V power supply to the downstream port VBUS. In general applications, a P-channel MOSFET can be used as the power switch for VBUS. Connect the 5 V power supply to the source of the P-channel MOSFET, VBUS to the drain, and H_PSWn_N to the gate. Call the voltage drop across the drain and source, the overcurrent detection voltage (VOC). For the internal overcurrent detection circuit, a voltage comparator has been designed-in, with a nominal voltage threshold (Vtrip) of 75 mV. When VOC exceeds Vtrip, H_PSWn_N will output a HIGH level, logic 1 to turn off the P-channel MOSFET. If the P-channel MOSFET has a RDSon of 150 m, the overcurrent threshold will be 500 mA. The selection of a P-channel MOSFET with a different RDSon will result in a different overcurrent threshold. regulator P-Channel MOSFET +5 V VOC = + 5 V - VBUS HC CORE VCC OC detect H_OCn_N OC select HcHardware Configuration bit 10 1 0 Reg VBUS PSW H_PSWn_N USB downstream port connector C/L 22 H_DMn 22 H_DPn 47 pF (2x) ATX bit 12 15 k (2x) SIE HcHardware Configuration ISP1160 004aaa066 'n' represents the downstream port number (n = 1 or 2). Fig 26. Using an internal OC detection circuit. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 33 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 9.8.2 Using an external OC detection circuit When VCC (pin 56) is connected to a 3.3 V instead of the 5 V power supply, the internal OC detection circuit cannot be used. An external OC detection circuit must be used instead. Regardless of the VCC value, an external OC detection circuit can always be used. To use an external OC detection circuit, AnalogOCEnable, bit 10 of the HcHardwareConfiguration register, should be logic 0. By default after reset, this bit is already logic 0; therefore, the HCD does not need to clear this bit. Figure 27 shows how to use an external OC detection circuit. + 3.3 V or + 5 V regulator HC CORE VCC +5 V VBUS OC detect external OC detect Vo Vi H_OCn_N OC select HcHardware Configuration bit 10 1 OC 0 Reg EN PSW H_PSWn_N C/L USB downstream port connector 22 H_DMn 22 H_DPn ATX bit 12 47 pF (2x) 15 k (2x) SIE HcHardware Configuration ISP1160 004aaa067 'n' represents the downstream port number (n = 1 or 2). Fig 27. Using an external OC detection circuit. 9.9 Suspend and wake-up 9.9.1 HC suspended state The HC can be put into suspended state by setting the HcControl register (01H to read, 81H to write). See Figure 14 for the HC's flow of USB state changes. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 34 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller XOSC_6MHz PLL_Lock XOSC HC_ClkOk DIGITAL CLOCK SWITCH HC PLL On On PLL_ClkOut HC_RawClk48M HC_Clk48MOut On HC CORE HC_EnableClock HcHardware Configuration On bit 11 (SuspendClkNotStop) HC_NeedClock VOLTAGE REGULATOR H_WAKEUP (pin) CS_N (pin) 004aaa375 Fig 28. ISP1160 suspend and resume clock scheme. In the suspended state, the device will consume considerably less power by turning off the internal 48 MHz clock, PLL and crystal, and setting the internal regulator to power-down mode. The ISP1160 suspend and resume clock scheme is shown in Figure 28. Pin H_SUSPEND is the sensing output pin for the HC's suspended state. When the HC goes into the USBSuspend state, this pin will output a HIGH level (logic 1). This pin is cleared to LOW (logic 0) level only when the HC is put into a USBReset state or USBOperational state (refer to the HcControl register bits 7 to 6; 01H to read, 81H to write). Bit 11, SuspendClkNotStop, of the HcHardwareConfiguration register (20H to read, A0H to write), defines if the HC internal clock is stopped or kept running when the HC goes into the USBSuspend state. After the HC enters the USBSuspend state for 1.3 ms, the internal clock will be stopped if bit SuspendClkNotStop is logic 0. For details on power consumption, refer to Philips Application Note AN10022 ISP1160x Low Power Consumption. 9.9.2 HC wake-up from suspended state There are three methods to wake up the HC from the USBSuspend state: hardware wake-up, software wake-up, and USB bus resume. They are described as follows. Wake-up by pin H_WAKEUP: Pins H_SUSPEND and H_WAKEUP provide hardware wake-up, a way of remote wake-up control for the HC without the need to access the HC internal registers. H_WAKEUP is an external wake-up control input pin for the HC. After the HC goes into the USBSuspend state, it can be woken up by sending a HIGH level pulse to pin H_WAKEUP. This will turn on the HC's internal clock, and set bit 6, ClkReady, of the HcPInterrupt register (24H to read, A4H to write). Under the USBSuspend state, once pin H_WAKEUP goes HIGH, after 160 s, the internal clock will be up. If pin H_WAKEUP continues to be HIGH, then the internal clock will be kept running, and the microprocessor can set the HC into USBOperational state during this time. If H_WAKEUP goes LOW for more than 1.14 ms, the internal clock stops and the HC goes back into the USBSuspend state. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 35 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Wake-up by pin CS_N (software wake-up): During the USBSuspend state, an external microprocessor issues a chip select signal through pin CS_N to the ISP1160. This method of access to the ISP1160 internal registers is a software wake-up. Wake-up by USB devices: For the USB bus resume, a USB device attached to the root hub port issues a resume signal to the HC through the USB bus, switching the HC from the USBSuspend state to the USBResume state. This will also set bit ResumeDetected of the HcInterruptStatus register (03H to read, 83H to write). No matter which method is used to wake up the HC from the USBSuspend state, the corresponding interrupt bits must be enabled before the HC goes into the USBSuspend state so that the microprocessor can receive the correct interrupt request to wake up the HC. 10. HC registers The HC contains a set of on-chip control registers. These registers can be read or written by the Host Controller Driver (HCD). The Control and Status register sets, Frame Counter register sets, and Root Hub register sets are grouped under the category of HC Operational registers (32 bits). These operational registers are made compatible to OpenHCI (Host Controller Interface) operational registers. This allows the OpenHCI HCD to be easily ported to the ISP1160. Reserved bits may be defined in future releases of this specification. To ensure interoperability, the HCD must not assume that a reserved field contains logic 0. Furthermore, the HCD must always preserve the values of the reserved field. When a R/W register is modified, the HCD must first read the register, modify the bits desired, and then write the register with the reserved bits still containing the original value. Alternatively, the HCD can maintain an in-memory copy of previously written values that can be modified and then written to the HC register. When a `write to set' or `clear the register' is performed, bits written to reserved fields must be logic 0. As shown in Table 7, the addresses (the commands for reading registers) of these 32-bit operational registers are similar to the offsets defined in the OHCI specification with the addresses being equal to offset divided by 4. Table 7: HC registers summary Address (Hex) Register Width Reference Functionality N/A HcRevision 32 Section 10.1.1 on page 37 HC control and status registers 01 81 HcControl 32 Section 10.1.2 on page 38 02 82 HcCommandStatus 32 Section 10.1.3 on page 39 03 83 HcInterruptStatus 32 Section 10.1.4 on page 40 04 84 HcInterruptEnable 32 Section 10.1.5 on page 42 05 85 HcInterruptDisable 32 Section 10.1.6 on page 43 0D 8D HcFmInterval 32 Section 10.2.1 on page 44 0E N/A HcFmRemaining 32 Section 10.2.2 on page 45 0F N/A HcFmNumber 32 Section 10.2.3 on page 46 11 91 HcLSThreshold 32 Section 10.2.4 on page 47 Read Write 00 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data HC frame counter registers Rev. 05 -- 24 December 2004 36 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 7: HC registers summary...continued Address (Hex) Register Width Reference Functionality 92 HcRhDescriptorA 32 Section 10.3.1 on page 48 HC Root Hub registers 13 93 HcRhDescriptorB 32 Section 10.3.2 on page 50 14 94 HcRhStatus 32 Section 10.3.3 on page 51 15 95 HcRhPortStatus[1] 32 Section 10.3.4 on page 53 16 96 HcRhPortStatus[2] 32 Section 10.3.4 on page 53 20 A0 HcHardwareConfiguration 16 Section 10.4.1 on page 57 21 A1 HcDMAConfiguration 16 Section 10.4.2 on page 58 22 A2 HcTransferCounter 16 Section 10.4.3 on page 59 24 A4 HcPInterrupt 16 Section 10.4.4 on page 59 25 A5 HcPInterruptEnable 16 Section 10.4.5 on page 61 27 N/A HcChipID 16 Section 10.5.1 on page 62 28 A8 HcScratch 16 Section 10.5.2 on page 63 N/A A9 HcSoftwareReset 16 Section 10.5.3 on page 63 2A AA HcITLBufferLength 16 Section 10.6.1 on page 64 2B AB HcATLBufferLength 16 Section 10.6.2 on page 64 2C N/A HcBufferStatus 16 Section 10.6.3 on page 65 2D N/A HcReadBackITL0Length 16 Section 10.6.4 on page 65 2E N/A HcReadBackITL1Length 16 Section 10.6.5 on page 66 40 C0 HcITLBufferPort 16 Section 10.6.6 on page 66 41 C1 HcATLBufferPort 16 Section 10.6.7 on page 67 Read Write 12 HC DMA and interrupt control registers HC miscellaneous registers HC buffer RAM control registers 10.1 HC control and status registers 10.1.1 HcRevision register (R: 00H) Code (Hex): 00 -- read only Table 8: HcRevision register: bit allocation Bit 31 30 29 28 Symbol Reset 27 26 25 24 0 0 0 0 reserved 0 0 0 0 Access R R R R R R R R Bit 23 22 21 20 19 18 17 16 0 0 0 0 Symbol Reset reserved 0 0 0 0 Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 37 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 1 0 0 0 0 Access R R R R R R R R Symbol REV[7:0] Table 9: 10.1.2 HcRevision register: bit description Bit Symbol Description 31 to 8 - reserved 7 to 0 REV[7:0] Revision: This read-only field contains the BCD representation of the version of the HCI specification that is implemented by this HC. All HC implementations that are compliant with this specification will have a value of 10H. HcControl register (R/W: 01H/81H) The HcControl register defines the operating modes of the HC. RemoteWakeupEnable (RWE) is modified only by the HCD. Code (Hex): 01 -- read Code (Hex): 81 -- write Table 10: HcControl register: bit allocation Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Access 24 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 RWE RWC reserved reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol Reset 25 0 Symbol Reset 26 reserved Symbol Reset 27 HCFS[1:0] reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 38 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 11: HcControl register: bit description Bit Symbol Description 31 to 11 - reserved 10 RWE RemoteWakeupEnable: This bit is used by the HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. When this bit is set and the ResumeDetected bit in HcInterruptStatus is set, a remote wake-up is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt. 9 RWC RemoteWakeupConnected: This bit indicates whether the HC supports remote wake-up signaling. If remote wake-up is supported and used by the system, it is the responsibility of system firmware to set this bit during POST. The HC clears the bit upon a hardware reset but does not alter it upon a software reset. Remote wake-up signaling of the host system is host-bus-specific and is not described in this specification. 8 - reserved 7 to 6 HCFS HostControllerFunctionalState for USB: 00B -- USBReset 01B -- USBResume 10B -- USBOperational 11B -- USBSuspend A transition to USBOperational from another state causes start-of-frame (SOF) generation to begin 1 ms later. The HCD may determine whether the HC has begun sending SOFs by reading the StartofFrame field of HcInterruptStatus. This field can be changed by the HC only when in the USBSuspend state. The HC can move from the USBSuspend state to the USBResume state after detecting the resume signaling from a downstream port. The HC enters USBReset after a software reset and a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. 5 to 0 10.1.3 - reserved HcCommandStatus register (R/W: 02H/82H) The HcCommandStatus register is used by the HC to receive commands issued by the HCD, and it also reflects the HC's current status. To the HCD, it appears to be a `write to set' register. The HC must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register. The HCD may issue multiple distinct commands to the HC without concern for corrupting previously issued commands. The HCD has normal read access to all bits. The SchedulingOverrunCount field indicates the number of frames with which the HC has detected the scheduling overrun error. This occurs when the Periodic list does not complete before EOF. When a scheduling overrun error is detected, the HC increments the counter and sets the SchedulingOverrun field in the HcInterruptStatus register. Code (Hex): 02 -- read (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 39 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Code (Hex): 82 -- write Table 12: HcCommandStatus register: bit allocation Bit 31 30 29 28 Symbol 27 26 25 24 reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 23 22 21 20 19 18 17 16 Symbol reserved SOC[1:0] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Symbol Reset Access Bit reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol Reset Access reserved HCR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 13: 10.1.4 HcCommandStatus register: bit description Bit Symbol Description 31 to 18 - reserved 17 to 16 SOC[1:0] SchedulingOverrunCount: The field is incremented on each scheduling overrun error. It is initialized to 00B and wraps around at 11B. It will be incremented when a scheduling overrun is detected even if SchedulingOverrun in HcInterruptStatus has already been set. This is used by HCD to monitor any persistent scheduling problems. 15 to 1 - reserved 0 HCR HostControllerReset: This bit is set by the HCD to initiate a software reset of the HC. Regardless of the functional state of the HC, it moves to the USBSuspend state in which most of the operational registers are reset, except those stated otherwise, and no Host bus accesses are allowed. This bit is cleared by the HC upon the completion of the reset operation. The reset operation must be completed within 10 s. This bit, when set, does not cause a reset to the Root Hub and no subsequent reset signaling should be asserted to its downstream ports. HcInterruptStatus register (R/W: 03H/83H) This register provides the status of the events that cause hardware interrupts. When an event occurs, the HC sets the corresponding bit in this register. When a bit is set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register (see Section 10.1.5) and bit MasterInterruptEnable is set. The HCD can clear individual bits in this register by writing logic 1 to the bit positions to be cleared, but cannot set any of these bits. Conversely, the HC can set bits in this register, but cannot clear these bits. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 40 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Code (Hex): 03 -- read Code (Hex): 83 -- write Table 14: HcInteruptStatus register: bit allocation Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Symbol Reset Access 24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 reserved RHSC FNO UE RD SF reserved SO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 15: HcInterruptStatus register: bit description Bit Symbol Description 31 to 7 - reserved 6 RHSC RootHubStatusChange: This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[1:2] has changed. 5 FNO FrameNumberOverflow: This bit is set when the MSB of HcFmNumber (bit 15) changes value. 4 UE UnrecoverableError: This bit is set when the HC detects a system error not related to USB. The HC does not proceed with any processing nor signaling before the system error has been corrected. The HCD clears this bit after the HC has been reset. OHCI: Always set to logic 0. 3 RD ResumeDetected: This bit is set when the HC detects that a device on the USB is asserting resume signaling from a state of no resume signaling. This bit is not set when HCD enters the USBResume state. 2 SF StartOfFrame: At the start of each frame, this bit is set by the HC and an SOF generated. 1 - reserved 0 SO SchedulingOverrun: This bit is set when USB schedules for current frame overruns. A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be incremented. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data 25 R/W Symbol Reset 26 reserved Symbol Reset 27 Rev. 05 -- 24 December 2004 41 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 10.1.5 HcInterruptEnable register (R/W: 04H/84H) Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. A hardware interrupt is requested on the host bus when three conditions occur: * A bit is set in the HcInterruptStatus register * The corresponding bit in the HcInterruptEnable register is set * Bit MasterInterruptEnable is set. Writing a logic 1 to a bit in this register sets the corresponding bit, whereas writing a logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the current value of this register is returned. Code (Hex): 04 -- read Code (Hex): 84 -- write Table 16: HcInterruptEnable register: bit allocation Bit Symbol Reset Access Bit 31 30 29 28 MIE Access Bit Access Bit Symbol Reset Access 24 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 reserved RHSC FNO UE RD SF reserved SO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data 25 0 Symbol Reset 26 reserved Symbol Reset 27 Rev. 05 -- 24 December 2004 42 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 17: HcInterruptEnable register: bit description Bit Symbol Description 31 MIE MasterInterruptEnable by the HCD: A logic 0 is ignored by the HC. A logic 1 enables interrupt generation by events specified in other bits of this register. 30 to 7 - reserved 6 RHSC 0 -- ignore 1 -- enable interrupt generation due to Root Hub Status Change 5 FNO 4 UE 0 -- ignore 1 -- enable interrupt generation due to frame Number Overflow 0 -- ignore 1 -- enable interrupt generation due to Unrecoverable Error 3 RD 0 -- ignore 1 -- enable interrupt generation due to Resume Detect 2 SF 0 -- ignore 1 - reserved 0 SO 0 -- ignore 1 -- enable interrupt generation due to Start of frame 1 -- enable interrupt generation due to Scheduling Overrun 10.1.6 HcInterruptDisable register (R/W: 05H/85H) Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register. Thus, writing a logic 1 to a bit in this register clears the corresponding bit in the HcInterruptEnable register, whereas writing a logic 0 to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a read, the current value of the HcInterruptEnable register is returned. Code (Hex): 05 -- read Code (Hex): 85 -- write Table 18: HcInterruptDisable register: bit allocation Bit Symbol Reset Access Bit 31 30 29 28 MIE Access Bit Access 24 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data 25 0 Symbol Reset 26 reserved Symbol Reset 27 Rev. 05 -- 24 December 2004 43 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Bit Symbol Reset Access 7 6 5 4 3 2 1 0 reserved RHSC FNO UE RD SF reserved SO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 19: HcInterruptDisable register: bit description Bit Symbol Description 31 MIE A logic 0 is ignored by the HC. A logic 1 disables interrupt generation due to events specified in other bits of this register. This field is set after a hardware or software reset. 30 to 7 - reserved 6 RHSC 0 -- ignore 1 -- disable interrupt generation due to Root Hub Status Change 5 FNO 0 -- ignore 1 -- disable interrupt generation due to Frame Number Overflow 4 UE 3 RD 0 -- ignore 1 -- disable interrupt generation due to Unrecoverable Error 0 -- ignore 1 -- disable interrupt generation due to Resume Detect 2 SF 0 -- ignore 1 -- disable interrupt generation due to Start of Frame 1 - reserved 0 SO 0 -- ignore 1 -- disable interrupt generation due to Scheduling Overrun 10.2 HC frame counter registers 10.2.1 HcFmInterval register (R/W: 0DH/8DH) The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a frame (that is, between two consecutive SOFs), and a 15-bit value indicating the full-speed maximum packet size that the HC may transmit or receive without causing a scheduling overrun. The HCD may carry out minor adjustments on the FrameInterval by writing a new value at each SOF. This allows the HC to synchronize with an external clock resource and to adjust any unknown clock offset. Code (Hex): 0D -- read Code (Hex): 8D -- write Table 20: HcFmInterval register: bit allocation Bit 31 Symbol FIT Reset Access 30 29 28 27 25 24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data 26 FSMPS[14:8] Rev. 05 -- 24 December 2004 44 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Bit 23 22 21 20 18 17 16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 0 0 1 0 1 1 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 1 1 0 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Symbol 19 FSMPS[7:0] Reset Access Bit Symbol reserved Reset Access Bit FI[13:8] Symbol FI[7:0] Reset Access Table 21: 10.2.2 HcFmInterval register: bit description Bit Symbol Description 31 FIT FrameIntervalToggle: The HCD toggles this bit whenever it loads a new value to FrameInterval. 30 to 16 FSMPS [14:0] FSLargestDataPacket: Specifies a value which is loaded into the Largest Data Packet Counter at the beginning of each frame. The counter value represents the largest amount of data in bits which can be sent or received by the HC in a single transaction at any given time without causing a scheduling overrun. The field value is calculated by the HCD. 15 to 14 - reserved 13 to 0 FI[13:0] FrameInterval: Specifies the interval between two consecutive SOFs in bit times. The default value is 11999. The HCD must save the current value of this field before resetting the HC. Setting the HostControllerReset field of the HcCommandStatus register will cause the HC to reset this field to its default value. HCD may choose to restore the saved value upon completing the reset sequence. HcFmRemaining register (R: 0EH) The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current frame. Code (Hex): 0E -- read Table 22: HcFmRemaining register: bit allocation Bit Symbol 31 30 29 28 FRT 27 26 25 24 reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 45 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Bit 15 Symbol 14 13 12 11 reserved 10 9 8 FR[13:8] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Symbol FR[7:0] Table 23: 10.2.3 HcFmRemaining register: bit description Bit Symbol Description 31 FRT FrameRemainingToggle: This bit is loaded from the FrameIntervalToggle field of the HcFmInterval register whenever FrameRemaining reaches 0. This bit is used by the HCD for synchronization between FrameInterval and FrameRemaining. 30 to 14 - reserved 13 to 0 FR[13:0] FrameRemaining: This counter is decremented at each bit time. When it reaches zero, it is reset by loading the FrameInterval value specified in the HcFmInterval register at the next bit time boundary. When entering the USBOperational state, the HC reloads it with the content of the FrameInterval part of the HcFmInterval register and uses the updated value from the next SOF. HcFmNumber register (R: 0FH) The HcFmNumber register is a 16-bit counter. It provides a timing reference for events happening in the HC and the HCD. The HCD may use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to the register. Code (Hex): 0F -- read Table 24: HcFmNumber register: bit allocation Bit 31 30 29 28 Symbol 27 26 25 24 reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Symbol FN[15:8] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 46 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Symbol FN[7:0] Table 25: 10.2.4 HcFmNumber register: bit description Bit Symbol Description 31 to 16 - reserved 15 to 0 FN[15:0] FrameNumber: This is incremented when HcFmRemaining is reloaded. It rolls over to 0000H after FFFFH. When the USBOperational state is entered, this will be incremented automatically. The HC will set bit StartofFrame in the HcInterruptStatus register. HcLSThreshold register (R/W: 11H/91H) The HcLSThreshold register contains an 11-bit value used by the HC to determine whether to commit to the transfer of a maximum of 8-byte LS packet before EOF. Neither the HC nor the HCD is allowed to change this value. Code (Hex): 11 -- read Code (Hex): 91 -- write Table 26: HcLSThreshold register: bit allocation Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Access 24 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved LST[10:8] 0 0 0 0 0 1 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol Reset 25 0 Symbol Reset 26 reserved Symbol Reset 27 LST[7:0] 0 0 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 47 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 27: HcLSThreshold register: bit description Bit Symbol Description 31 to 11 - reserved 10 to 0 LST[10:0] LSThreshold: Contains a value that is compared to the FrameRemaining field before a low-speed transaction is initiated. The transaction is started only if FrameRemaining this field. The value is calculated by the HCD, which considers transmission and set-up overhead. 10.3 HC Root Hub registers All registers included in this partition are dedicated to the USB Root Hub, which is an integral part of the HC although it is functionally a separate entity. The Host Controller Driver (HCD) emulates USBD accesses to the Root Hub via a register interface. The HCD maintains many USB-defined hub features that are not required to be supported in hardware. For example, the Hub's Device, Configuration, Interface, and Endpoint Descriptors, as well as some static fields of the Class Descriptor, are maintained only in the HCD. The HCD also maintains and decodes the Root Hub's device address as well as other minor operations more suited for software than hardware. The Root Hub registers were developed to match the bit organization and operation of typical hubs found in the system. Four 32-bit registers have been defined: * * * * HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus[1:NDP] Each register is read and written as a DWORD. These registers are only written during initialization to correspond with the system implementation. The HcRhDescriptorA and HcRhDescriptorB registers are writeable regardless of the HC's USB states. HcRhStatus and HcRhPortStatus are writeable during the USBOperational state only. 10.3.1 HcRhDescriptorA register (R/W: 12H/92H) The HcRhDescriptorA register is the first register of two describing the characteristics of the Root Hub. Reset values are implementation-specific (IS). The descriptor length (11), descriptor type and hub controller current (0) fields of the hub Class Descriptor are emulated by the HCD. All other fields are located in registers HcRhDescriptorA and HcRhDescriptorB. Remark: IS denotes an implementation-specific reset value for that field. Code (Hex): 12 -- read Code (Hex): 92 -- write (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 48 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 28: HcRhDescriptorA register: bit description Bit 31 30 29 28 Symbol Reset Access Bit Access Bit 26 25 24 POTPGT[7:0] IS IS IS IS IS IS IS IS R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Symbol Reset 27 reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 NOCP OCPM DT NPS PSM Symbol reserved Reset 0 0 0 IS IS 0 IS IS Access R R R R/W R/W R R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol reserved NDP[1:0] Reset 0 0 0 0 0 0 IS IS Access R R R R R R R R Table 29: HcRhDescriptorA register: bit description Bit Symbol Description 31 to 24 POTPGT [7:0] PowerOnToPowerGoodTime: This byte specifies the duration HCD has to wait before accessing a powered-on port of the Root Hub. The unit of time is 2 ms. The duration is calculated as POTPGT x 2 ms. 23 to 13 - reserved 12 NOCP NoOverCurrentProtection: This bit describes how the overcurrent status for the Root Hub ports are reported. When this bit is cleared, the OverCurrentProtectionMode field specifies global or per-port reporting. 0 -- overcurrent status is reported collectively for all downstream ports 1 -- no overcurrent reporting supported 11 OCPM OverCurrentProtectionMode: This bit describes how the overcurrent status for the Root Hub ports is reported. At reset, this field reflects the same mode as PowerSwitchingMode. This field is valid only if the NoOverCurrentProtection field is cleared. 0 -- overcurrent status is reported collectively for all downstream ports 1 -- overcurrent status is reported on a per-port basis. On power-up, clear this bit and then set it to logic 1. 10 DT DeviceType: This bit specifies that the Root Hub is not a compound device--it is not permitted. This field should always read/write 0. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 49 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 29: HcRhDescriptorA register: bit description...continued Bit Symbol Description 9 NPS NoPowerSwitching: This bit is used to specify whether power switching is supported or ports are always powered. When this bit is cleared, bit PowerSwitchingMode specifies global or per-port switching. 0 -- ports are power switched 1 -- ports are always powered on when the HC is powered on 8 PSM PowerSwitchingMode: This bit is used to specify how the power switching of the Root Hub ports is controlled. This field is valid only if the NoPowerSwitching field is cleared. 0 -- all ports are powered at the same time 1 -- each port is powered individually. This mode allows port power to be controlled by either the global switch or per-port switching. If bit PortPowerControlMask is set, the port responds to only port power commands (Set/ClearPortPower). If the port mask is cleared, then the port is controlled only by the global power switch (Set/ClearGlobalPower). 10.3.2 7 to 2 - reserved 1 to 0 NDP[1:0] NumberDownstreamPorts: These bits specify the number of downstream ports supported by the Root Hub. The maximum number of ports supported by the ISP1160 is 2. HcRhDescriptorB register (R/W: 13H/93H) The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are written during initialization to correspond with the system implementation. Reset values are implementation-specific (IS). Code (Hex): 13 -- read Code (Hex): 93 -- write Table 30: HcRhDescriptorB register: bit allocation Bit 31 30 29 28 Symbol Reset 27 26 25 24 reserved N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R Bit 23 22 21 20 19 18 17 16 Symbol Reset reserved PPCM[2:0] N/A N/A N/A N/A N/A IS IS IS Access R R R R R R/W R/W R/W Bit 15 14 13 12 11 10 9 8 Symbol Reset Access reserved N/A N/A N/A N/A N/A N/A N/A N/A R R R R R R R R (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 50 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Bit 7 6 N/A N/A R R Symbol 5 4 3 2 N/A N/A N/A IS IS IS R R R R/W R/W R/W reserved Reset Access Table 31: 1 0 DR[2:0] HcRhDescriptorB register: bit description Bit Symbol Description 31 to 19 - reserved 18 to 16 PPCM[2:0] PortPowerControlMask: Each bit indicates whether a port is affected by a global power control command when PowerSwitchingMode is set. When set, the port's power state is only affected by per-port power control (Set/ClearPortPower). When cleared, the port is controlled by the global power switch (Set/ClearGlobalPower). If the device is configured to global switching mode (PowerSwitchingMode = 0), this field is not valid. Bit 0 -- reserved Bit 1 -- Ganged-power mask on Port #1 Bit 2 -- Ganged-power mask on Port #2 15 to 3 - reserved 2 to 0 DR[2:0] DeviceRemovable: Each bit is dedicated to a port of the Root Hub. When cleared, the attached device is removable. When set, the attached device is not removable. Bit 0 -- reserved Bit 1 -- Device attached to Port #1 Bit 2 -- Device attached to Port #2 10.3.3 HcRhStatus register (R/W: 14H/94H) The HcRhStatus register is divided into two parts. The lower word of a DWORD represents the Hub Status field and the upper word represents the Hub Status Change field. Reserved bits should always be written as logic 0. Code (Hex): 14 -- read Code (Hex): 94 -- write Table 32: HcRhStatus register: bit allocation Bit Symbol 31 30 29 28 CRWE 27 26 25 24 reserved Reset 0 0 0 0 0 0 0 0 Access W R R R R R R R Bit 23 22 21 20 19 18 17 16 OCIC LPSC Symbol reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R/W R/W (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 51 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Bit 14 13 12 0 0 0 0 R/W R R 7 6 5 Reset 0 0 Access R R Symbol Reset Access Bit 15 10 9 8 0 0 0 0 R R R R R 4 3 2 1 0 OCI LPS 0 0 0 0 0 0 R R R R R R/W DRWE 11 reserved Symbol reserved Table 33: HcRhStatus register: bit description Bit Symbol Description 31 CRWE On write--ClearRemoteWakeupEnable: Writing a logic 1 clears DeviceRemoveWakeupEnable. Writing a logic 0 has no effect. 30 to 18 - reserved 17 OCIC OverCurrentIndicatorChange: This bit is set by hardware when a change has occurred to the OCI field of this register. The HCD clears this bit by writing a logic 1. Writing a logic 0 has no effect. 16 LPSC On read--LocalPowerStatusChange: The Root Hub does not support the local power status feature. Therefore, this bit is always read as logic 0. On write--SetGlobalPower: In global power mode (PowerSwitchingMode = 0), this bit is written to logic 1 to turn on power to all ports (clear PortPowerStatus). In per-port power mode, it sets PortPowerStatus only on ports whose bit PortPowerControlMask is not set. Writing a logic 0 has no effect. 15 DRWE On read--DeviceRemoteWakeupEnable: This bit enables the bit ConnectStatusChange as a resume event, causing a state transition USBSuspend to USBResume and setting the ResumeDetected interrupt. 0 -- ConnectStatusChange is not a remote wake-up event 1 -- ConnectStatusChange is a remote wake-up event On write--SetRemoteWakeupEnable: Writing a logic 1 sets DeviceRemoveWakeupEnable. Writing a logic 0 has no effect. 14 to 2 - reserved 1 OCI OverCurrentIndicator: This bit reports overcurrent conditions when global reporting is implemented. When set, an overcurrent condition exists. When clear, all power operations are normal. If per-port overcurrent protection is implemented this bit is always logic 0. 0 LPS On read--LocalPowerStatus: The Root Hub does not support the local power status feature. Therefore, this bit is always read as logic 0. On write--ClearGlobalPower: In global power mode (PowerSwitchingMode = 0), this bit is written to logic 1 to turn off power to all ports (clear PortPowerStatus). In per-port power mode, it clears PortPowerStatus only on ports whose bit PortPowerControlMask is not set. Writing a logic 0 has no effect. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 52 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 10.3.4 HcRhPortStatus[1:2] (R/W [1]:15H/95H, [2]: 16H/96H) The HcRhPortStatus[1:2] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port status, whereas the upper word reflects the status change bits. Some status bits are implemented with special write behavior. If a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. Reserved bits should always be written logic 0. Code (Hex): [1] = 15, [2] = 16 -- read Code (Hex): [1] = 95, [2] = 96 -- write Table 34: HcRhPortStatus[1:2] register: bit allocation Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Access 24 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 22 21 23 reserved 20 19 18 17 16 PRSC OCIC PSSC PESC CSC 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 reserved 9 8 LSDA PPS 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 6 5 7 Symbol Reset 25 0 Symbol Reset 26 0 Symbol Reset 27 reserved reserved 4 3 2 1 0 PRS POCI PSS PES CCS 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 35: HcRshPortStatus[1:2] register: bit description Bit Symbol Description 31 to 21 - reserved 20 PRSC PortResetStatusChange: This bit is set at the end of the 10 ms port reset signal. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. 0 -- port reset is not complete 1 -- port reset is complete 19 OCIC PortOverCurrentIndicatorChange: This bit is valid only if overcurrent conditions are reported on a per-port basis. This bit is set when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. 0 -- no change in PortOverCurrentIndicator 1 -- PortOverCurrentIndicator has changed (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 53 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 35: HcRshPortStatus[1:2] register: bit description...continued Bit Symbol Description 18 PSSC PortSuspendStatusChange: This bit is set when the full resume sequence has been completed. This sequence includes the 20 s resume pulse, LS EOP, and 3 ms resynchronization delay. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. This bit is also cleared when ResetStatusChange is set. 0 -- resume is not completed 1 -- resume is completed 17 PESC PortEnableStatusChange: This bit is set when hardware events cause the PortEnableStatus bit to be cleared. Changes from HCD writes do not set this bit. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. 0 -- no change in PortEnableStatus 1 -- change in PortEnableStatus 16 CSC ConnectStatusChange: This bit is set whenever a connect or disconnect event occurs. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. If CurrentConnectStatus is cleared when a SetPortReset, SetPortEnable, or SetPortSuspend write occurs, this bit is set to force the driver to reevaluate the connection status since these writes should not occur if the port is disconnected. 0 -- no change in CurrentConnectStatus 1 -- change in CurrentConnectStatus Remark: If bit DeviceRemovable[NDP] is set, this bit is set only after a Root Hub reset to inform the system that the device is attached. 15 to 10 - reserved 9 LSDA On read--LowSpeedDeviceAttached: This bit indicates the speed of the device connected to this port. When set, a low-speed device is connected to this port. When clear, a full-speed device is connected to this port. This field is valid only when the CurrentConnectStatus is set. 0 -- full-speed device attached 1 -- low-speed device attached On write--ClearPortPower: The HCD clears bit PortPowerStatus by writing a logic 1 to this bit. Writing a logic 0 has no effect. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 54 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 35: HcRshPortStatus[1:2] register: bit description...continued Bit Symbol Description 8 PPS On read--PortPowerStatus: This bit reflects the port power status, regardless of the type of power switching implemented. This bit is cleared if an overcurrent condition is detected. The HCD sets this bit by writing SetPortPower or SetGlobalPower. The HCD clears this bit by writing ClearPortPower or ClearGlobalPower. Which power control switches are enabled is determined by PowerSwitchingMode. In the global switching mode (PowerSwitchingMode = 0), only Set/ClearGlobalPower controls this bit. In per-port power switching (PowerSwitchingMode = 1), if bit PortPowerControlMask[NDP] for the port is set, only Set/ClearPortPower commands are enabled. If the mask is not set, only Set/ClearGlobalPower commands are enabled. When port power is disabled, CurrentConnectStatus, PortEnableStatus, PortSuspendStatus, and PortResetStatus should be reset. 0 -- port power is off 1 -- port power is on On write--SetPortPower: The HCD writes a logic 1 to set bit PortPowerStatus. Writing a logic 0 has no effect. Remark: This bit always reads logic 1 if power switching is not supported. 7 to 5 - reserved 4 PRS On read--PortResetStatus: When this bit is set by a write to SetPortReset, port reset signaling is asserted. When reset is completed, this bit is cleared when PortResetStatusChange is set. This bit cannot be set if CurrentConnectStatus is cleared. 0 -- port reset signal is not active 1 -- port reset signal is active On write--SetPortReset: The HCD sets the port reset signaling by writing a logic 1 to this bit. Writing a logic 0 has no effect. If CurrentConnectStatus is cleared, this write does not set PortResetStatus but instead sets ConnectStatusChange. This informs the driver that it attempted to reset a disconnected port. 3 POCI On read--PortOverCurrentIndicator: This bit is valid only when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. If per-port overcurrent reporting is not supported, this bit is set to logic 0. If cleared, all power operations are normal for this port. If set, an overcurrent condition exists on this port. This bit always reflects the overcurrent input signal. 0 -- no overcurrent condition 1 -- overcurrent condition detected (write) ClearSuspendStatus: The HCD writes a logic 1 to initiate a resume. Writing a logic 0 has no effect. A resume is initiated only if PortSuspendStatus is set. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 55 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 35: HcRshPortStatus[1:2] register: bit description...continued Bit Symbol Description 2 PSS On read--PortSuspendStatus: This bit indicates whether the port is suspended or in the resume sequence. It is set by a SetSuspendState write and cleared when PortSuspendStatusChange is set at the end of the resume interval. This bit cannot be set if CurrentConnectStatus is cleared. This bit is also cleared when PortResetStatusChange is set at the end of the port reset or when the HC is placed in the USBResume state. If an upstream resume is in progress, it should propagate to the HC. 0 -- port is not suspended 1 -- port is suspended On write--SetPortSuspend: The HCD sets bit PortSuspendStatus by writing a logic 1 to this bit. Writing a logic 0 has no effect. If CurrentConnectStatus is cleared, this write does not set PortSuspendStatus; instead it sets ConnectStatusChange. This informs the driver that it attempted to suspend a disconnected port. 1 PES On read--PortEnableStatus: This bit indicates whether the port is enabled or disabled. The Root Hub may clear this bit when an overcurrent condition, disconnect event, switched-off power, or operational bus error such as babble is detected. This change also causes PortEnabledStatusChange to be set. The HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable. This bit cannot be set when CurrentConnectStatus is cleared. This bit is also set at the completion of a port reset when ResetStatusChange is set or port is suspended when SuspendStatusChange is set. 0 -- port is disabled 1 -- port is enabled On write--SetPortEnable: The HCD sets PortEnableStatus by writing a logic 1. Writing a logic 0 has no effect. If CurrentConnectStatus is cleared, this write does not set PortEnableStatus, but instead sets ConnectStatusChange. This informs the driver that it attempted to enable a disconnected port. 0 CCS On read--CurrentConnectStatus: This bit reflects the current state of the downstream port. 0 -- no device connected 1 -- device connected On write--ClearPortEnable: The HCD writes a logic 1 to this bit to clear bit PortEnableStatus. Writing a logic 0 has no effect. CurrentConnectStatus is not affected by any write. Remark: This bit always reads logic 1 when the attached device is nonremovable (DeviceRemoveable[NDP]). (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 56 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 10.4 HC DMA and interrupt control registers 10.4.1 HcHardwareConfiguration register (R/W: 20H/A0H) Code (Hex): 20 -- read Code (Hex): A0 -- write Table 36: HcHardwareConfiguration register: bit allocation Bit 15 Symbol Reset Access Bit Symbol Reset Access 14 13 reserved 12 11 10 9 8 2_Down stream Port15K resistorsel Suspend ClkNotStop AnalogOC Enable reserved DACKMode 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 EOTInput Polarity DACKInput Polarity DREQ Output Polarity Interrupt Output Polarity Interrupt PinTrigger InterruptPin Enable 0 0 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 37: Bit DataBusWidth[1:0] HcHardwareConfiguration register: bit description Symbol 15 to 13 - Description reserved 12 2_DownstreamPort15K 0 -- use external 15 k resistors for downstream ports resistorsel 1 -- use built-in resistors for downstream ports 11 SuspendClkNotStop 0 -- clock can be stopped 1 -- clock can not be stopped 10 AnalogOCEnable 0 -- use external OC detection; digital input 1 -- use on-chip OC detection; analog input 9 - reserved 8 DACKMode 0 -- normal operation; pin DACK_N is used with read and write signals 1 -- reserved 7 EOTInputPolarity 0 -- active LOW 1 -- active HIGH 6 DACKInputPolarity 0 -- active LOW 1 -- reserved 5 DREQOutputPolarity 0 -- active LOW 1 -- active HIGH 4 to 3 DataBusWidth[1:0] These bits are fixed at logic 0 and logic 1 for the ISP1160. 01 -- 16 bits Others -- reserved (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 57 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 37: HcHardwareConfiguration register: bit description...continued Bit Symbol Description 2 InterruptOutputPolarity 0 -- active LOW 1 -- active HIGH 1 InterruptPinTrigger 0 -- interrupt is level-triggered 1 -- interrupt is edge-triggered 0 InterruptPinEnable This bit is used as pin INT's master interrupt enable and should be used together with register HcPInterruptEnable to enable pin INT. 0 -- pin INT is disabled 1 -- pin INT is enabled 10.4.2 HcDMAConfiguration register (R/W: 21H/A1H) Code (Hex): 21 -- read Code (Hex): A1 -- write Table 38: HcDMAConfiguration register: bit allocation Bit 15 14 13 12 Symbol Reset Access Bit Symbol Reset Access 11 10 9 8 reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 reserved BurstLen[1:0] 4 3 2 1 0 DMA Enable reserved DMA Counter Select ITL_ATL_ DataSelect DMARead WriteSelect 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 39: Bit HcDMAConfiguration register: bit description Symbol Description 15 to 7 - reserved 6 to 5 BurstLen[1:0] 00 -- single-cycle burst DMA 01 -- 4-cycle burst DMA 10 -- 8-cycle burst DMA 11 -- reserved 4 DMAEnable 0 -- DMA is terminated 1 -- DMA is enabled This bit will be reset to logic 0 when DMA transfer is completed. 3 - reserved (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 58 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 39: 10.4.3 HcDMAConfiguration register: bit description...continued Bit Symbol Description 2 DMACounter Select 0 -- DMA counter not used. External EOT must be used 1 ITL_ATL_ DataSelect 0 -- ITL buffer RAM selected for ITL data 0 DMARead WriteSelect 0 -- read from the HC FIFO buffer RAM 1 -- enables the DMA counter for DMA transfer. HcTransferCounter register must be filled with non-zero values for DREQ to be raised after bit DMA Enable is set. 1 -- ATL buffer RAM selected for ATL data 1 -- write to the HC FIFO buffer RAM HcTransferCounter register (R/W: 22H/A2H) This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer, the number of bytes being read or written to the Isochronous Transfer List (ITL) or Acknowledged Transfer List (ATL) buffer RAM must be written into this register. For a DMA transfer, the number of bytes must be written into this register as well. However, for this counter to be read into the DMA counter, the HCD must set bit 2 (DMACounterSelect) of the HcDMAConfiguration register. The counter value for ATL must not be greater than 1000H, and for ITL it must not be greater than 800H. When the byte count of the data transfer reaches this value, the HC will generate an internal EOT signal to set bit 2 (AllEOTInterrupt) of the HcPInterrupt register, and also update the HcBufferStatus register. Code (Hex): 22 -- read Code (Hex): A2 -- write Table 40: HcTransferCounter register: bit allocation Bit 15 14 13 Symbol Reset Access Bit Access 11 10 9 8 Counter value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol Reset 12 Counter value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 41: 10.4.4 HcTransferCounter register: bit description Bit Symbol Description 15 to 0 Counter value The number of data bytes to be read to or written from RAM. HcPInterrupt register (R/W: 24H/A4H) All the bits in this register will be active on power-on reset. However, none of the active bits will cause an interrupt on the interrupt pin (INT) unless they are set by the respective bits in the HcPInterruptEnable register, and together with bit 0 of the HcHardwareConfiguration register. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 59 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller After this register (24H to read) is read, the bits that are active will not be reset, until logic 1 is written to the bits in this register (A4H to write) to clear it. To clear all the enabled bits in this register, the HCD must write FFH to this register. Code (Hex): 24 -- read Code (Hex): A4 -- write Table 42: HcPInterrupt register: bit allocation Bit 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 reserved ClkReady HC Suspended OPR_Reg reserved AIIEOT Interrupt ATLInt SOFITLInt 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Symbol Reset Access Bit Symbol Reset Access reserved Table 43: HcPInterrupt register: bit description Bit Symbol Description 15 to 7 - reserved 6 ClkReady 0 -- no event 1 -- clock is ready. After a wake-up is sent, there is a wait for clock ready. Maximum is 1 ms, and typical is 160 s. 5 HC 0 -- no event Suspended 1 -- the HC has been suspended and no USB activity is sent from the microprocessor for each ms. When the microprocessor wants to suspend the HC, the microprocessor must write to the HcControl register. And when all downstream devices are suspended, then the HC stops sending SOF; the HC is suspended by having the HcControl register written into. 4 OPR_Reg 0 -- no event 1 -- there are interrupts from HC side. Need to read HcControl and HcInterrupt registers to detect type of interrupt on the HC (if the HC requires the operational register to be updated). 3 - reserved (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 60 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 43: HcPInterrupt register: bit description...continued Bit Symbol Description 2 AllEOT Interrupt 0 -- no event ATLInt 0 -- no event 1 1 -- implies that data transfer has been completed via PIO transfer or DMA transfer. Occurrence of internal or external EOT will set this bit. 1 -- implies that the microprocessor must read ATL data from the HC. This requires that the HcBufferStatus register must first be read. The time for this interrupt depends on the number of clocks bit set for USB activities in each ms. 0 SOFITLInt 0 -- no event 1 -- implies that SOF indicates the 1 ms mark. The ITL buffer that the HC has handled must be read. To know the ITL buffer status, the HcBufferStatus register must first be read. This is for the microprocessor to get ISO data to or from the HC. For more information, see the 6th paragraph in Section 9.5. 10.4.5 HcPInterruptEnable register (R/W: 25H/A5H) The bits 6:0 in this register are the same as those in the HcPInterrupt register. They are used together with bit 0 of the HcHardwareConfiguration register to enable or disable the bits in the HcPInterrupt register. On power-on, all bits in this register are masked with logic 0. This means no interrupt request output on the interrupt pin INT can be generated. When the bit is set to logic 1, the interrupt for the bit is not masked but enabled. Code (Hex): 25 -- read Code (Hex): A5 -- write Table 44: HcPInterruptEnable register: bit allocation Bit 15 14 13 12 Symbol Reset Access Bit Symbol Reset Access 11 9 8 reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 reserved ClkReady HC Suspended Enable OPR Interrupt Enable reserved EOT Interrupt Enable ATL Interrupt Enable SOF Interrupt Enable 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data 10 Rev. 05 -- 24 December 2004 61 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 45: HcPInterruptEnable register: bit description Bit Symbol Description 15 to 7 - reserved 6 ClkReady 0 -- power-up value 5 HC 0 -- power-up value Suspended 1 -- enables HC suspended interrupt. When the microprocessor Enable wants to suspend the HC, the microprocessor must write to the HcControl register. And when all downstream devices are suspended, then the HC stops sending SOF; the HC is suspended by having the HcControl register written into. 4 OPR Interrupt Enable 0 -- power-up value 3 - reserved 2 EOT Interrupt Enable 0 -- power-up value ATL Interrupt Enable 0 -- power-up value SOF Interrupt Enable 0 -- power-up value 1 -- enables ClkReady interrupt 1 0 1 -- enables the 32-bit operational register's interrupt (if the HC requires the operational register to be updated) 1 -- enables the EOT interrupt which indicates an end of a read/write transfer 1 -- enables ATL interrupt. The time for this interrupt depends on the number of clock bits set for USB activities in each ms. 1 -- enables the interrupt bit due to SOF (for the microprocessor DMA to get ISO data from the HC by first accessing the HcDMAConfiguration register) 10.5 HC miscellaneous registers 10.5.1 HcChipID register (R: 27H) Read this register to get the ID of the ISP1160 silicon chip. The higher byte stands for the product name. The lower byte indicates the revision number of the product including engineering samples. Code (Hex): 27 -- read Table 46: HcChipID register: bit allocation Bit 15 14 13 Symbol 12 11 10 9 8 ChipID[15:8] Reset 0 1 1 0 0 0 0 1 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Symbol ChipID[7:0] Reset 0 0 1 0 0 0 1 X[1] Access R R R R R R R R [1] X is logic 0 for ISP1160BD and ISP1160BM; X is logic 1 for ISP1160BD/01 and ISP1160BM/01. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 62 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 47: 10.5.2 HcChipID register: bit description Bit Symbol Description 15 to 0 ChipID[15:0] ISP1160's chip ID HcScratch register (R/W: 28H/A8H) This register is for the HCD to save and restore values when required. Code (Hex): 28 -- read Code (Hex): A8 -- write Table 48: HcScratch register: bit allocation Bit 15 14 13 12 Symbol 11 10 9 8 Scratch[15:8] Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol Scratch[7:0] Reset Access 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 49: 10.5.3 HcScratch register: bit description Bit Symbol Description 15 to 0 Scratch[15:0] Scratch register value HcSoftwareReset register (W: A9H) This register provides a means for software reset of the HC. To reset the HC, the HCD must write a reset value of F6H to this register. Upon receiving the reset value, the HC resets all the registers except its buffer memory. Code (Hex): A9 -- write Table 50: HcSoftwareReset register: bit allocation Bit 15 14 13 12 Symbol 11 10 9 8 Reset[15:8] Reset 0 0 0 0 0 0 0 0 Access W W W W W W W W Bit 7 6 5 4 3 2 1 0 Symbol Reset[7:0] Reset 0 0 0 0 0 0 0 0 Access W W W W W W W W Table 51: HcSoftwareReset register: bit description Bit Symbol Description 15 to 0 Reset[15:0] Writing a reset value of F6H will cause the HC to reset all the registers except its buffer memory. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 63 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 10.6 HC buffer RAM control registers 10.6.1 HcITLBufferLength register (R/W: 2AH/AAH) Write to this register to assign the ITL buffer size in bytes: ITL0 and ITL1 are assigned the same value. For example, if HcITLBufferLength register is set to 2 kbytes, then ITL0 and ITL1 would be allocated 2 kbytes each. Must follow the formula: ATL buffer length + 2 x (ITL buffer size) 1000H (that is, 4 kbytes) where: ITL buffer size = ITL0 buffer length = ITL1 buffer length. Code (Hex): 2A -- read Code (Hex): AA -- write Table 52: HcITLBufferLength register: bit allocation Bit 15 14 13 Symbol 12 11 10 9 8 ITLBufferLength[15:8] Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol ITLBufferLength[7:0] Reset Access 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 53: 10.6.2 HcITLBufferLength register: bit description Bit Symbol Description 15 to 0 ITLBufferLength[15:0] Assign ITL buffer length HcATLBufferLength register (R/W: 2BH/ABH) Write to this register to assign ATL buffer size. Code (Hex): 2B -- read Code (Hex): AB -- write Remark: The maximum total RAM size is 1000H (4096 in decimal) bytes. That means ITL0 (length) + ITL1 (length) + ATL (length) 1000H bytes. For example, if ATL buffer length has been set to be 800H, then the maximum ITL buffer length can only be set as 400H. Table 54: HcATLBufferLength register: bit allocation Bit 15 14 13 0 0 0 0 R/W R/W R/W R/W Symbol Reset Access 12 11 10 9 8 0 0 0 0 R/W R/W R/W R/W ATLBufferLength[15:8] (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 64 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Bit 7 6 5 4 0 0 0 0 R/W R/W R/W R/W Symbol 3 2 1 0 0 0 0 0 R/W R/W R/W R/W ATLBufferLength[7:0] Reset Access Table 55: 10.6.3 HcATLBufferLength register: bit description Bit Symbol Description 15 to 0 ATLBufferLength[15:0] Assign ATL buffer length HcBufferStatus register (R: 2CH) Code (Hex): 2C -- read Table 56: HcBufferStatus register: bit allocation Bit 15 14 13 12 Symbol 11 10 9 8 reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 ATLBuffer Done ITL1Buffer Done ITL0Buffer Done ATLBuffer Full ITL1Buffer Full ITL0Buffer Full Symbol reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Table 57: Bit Symbol Description 15 to 6 - reserved 5 ATLBuffer Done 0 -- ATL Buffer not read by HC yet 4 ITL1Buffer Done 0 -- ITL1 Buffer not read by HC yet 3 ITL0Buffer Done 0 -- 1TL0 Buffer not read by HC yet ATLBuffer Full 0 -- ATL Buffer is empty 1 ITL1Buffer Full 0 -- 1TL1 Buffer is empty 0 ITL0Buffer Full 0 -- ITL0 Buffer is empty 2 10.6.4 HcBufferStatus register: bit description 1 -- ATL Buffer read by HC 1 -- ITL1 Buffer read by HC 1 -- 1TL0 Buffer read by HC 1 -- ATL Buffer is full 1 -- 1TL1 Buffer is full 1 -- ITL0 Buffer is full HcReadBackITL0Length register (R: 2DH) This register's value stands for the current number of data bytes inside an ITL0 buffer to be read back by the microprocessor. The HCD must set the HcTransferCounter equivalent to this value before reading back the ITL0 buffer RAM. Code (Hex): 2D -- read (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 65 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 58: HcReadBackITL0Length register: bit allocation Bit 15 14 13 Symbol 12 11 10 9 8 RdITL0BufferLength[15:8] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Symbol RdITL0BufferLength[7:0] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Table 59: 10.6.5 HcReadBackITL0Length register: bit description Bit Symbol Description 15 to 0 RdITL0BufferLength[15:0] The number of bytes for ITL0 data to be read back by the microprocessor HcReadBackITL1Length register (R: 2EH) This register's value stands for the current number of data bytes inside the ITL1 buffer to be read back by the microprocessor. The HCD must set the HcTransferCounter equivalent to this value before reading back the ITL1 buffer RAM. Code (Hex): 2E -- read Table 60: HcReadBackITL1Length register: bit allocation Bit 15 14 13 Symbol 12 11 10 9 8 RdITL1BufferLength[15:8] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Symbol RdITL1BufferLength[7:0] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Table 61: 10.6.6 HcReadBackITL1Length register: bit description Bit Symbol 15 to 0 RdITL1BufferLength[15:0] The number of bytes for ITL1 data to be read back by the microprocessor. Description HcITLBufferPort register (R/W: 40H/C0H) This is the ITL buffer RAM read/write port. The bits 15:8 contain the data byte that comes from the ITL buffer RAM's even address. The bits 7:0 contain the data byte that comes from the ITL buffer RAM's odd address. Code (Hex): 40 -- read Code (Hex): C0 -- write (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 66 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 62: HcITLBufferPort register: bit allocation Bit 15 14 13 Symbol 12 11 10 9 8 DataWord[15:8] Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol DataWord[7:0] Reset Access 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 63: HcITLBufferPort register: bit description Bit Symbol Description 15 to 0 DataWord[15:0] Read/write ITL buffer RAM's two data bytes. The HCD must set the byte count into the HcTransferCounter register and check the HcBufferStatus register before reading from or writing to the buffer. The HCD must write the command (40H to read, C0H to write) once only, and then read or write both bytes of the data word. After every read/write, the pointer of ITL buffer RAM will be automatically increased by two to point to the next data word until it reaches the value of the HcTransferCounter register; otherwise, an internal EOT signal is not generated to set bit 2 (AllEOTInterrupt) of the HcPInterrupt register and update the HcBufferStatus register. The HCD must take care of the fact that the internal buffer RAM is organized in bytes. The HCD must write the byte count into the HcTransferCounter register, but the HCD reads or writes the buffer RAM by 16 bits (by 1 word). 10.6.7 HcATLBufferPort register (R/W: 41H/C1H) This is the ATL buffer RAM read/write port. Bits 15 to 8 contain the data byte that comes from the Acknowledged Transfer List (ATL) buffer RAM's odd address. Bits 7 to 0 contain the data byte that comes from the ATL buffer RAM's even address. Code (Hex): 41 -- read Code (Hex): C1 -- write Table 64: HcATLBufferPort register: bit allocation Bit 15 14 13 10 9 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Symbol Reset Access Bit Access 11 DataWord[15:8] Symbol Reset 12 DataWord[7:0] Table 65: HcATLBufferPort register: bit description Bit Symbol Description 15 to 0 DataWord[15:0] Read/write ATL buffer RAM's two data bytes. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 67 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller The HCD must set the byte count into the HcTransferCounter register and check the HcBufferStatus register before reading from or writing to the buffer. The HCD must write the command (41H to read, C1H to write) once only, and then read or write both bytes of the data word. After every read/write, the pointer of ATL buffer RAM will be automatically increased by two to point to the next data word until it reaches the value of the HcTransferCounter register; otherwise, an internal EOT signal is not generated to set bit 2 (AllEOTInterrupt) of the HcPInterrupt register and update the HcBufferStatus register. The HCD must take care of the difference: the internal buffer RAM is organized in bytes, so the HCD must write the byte count into the HcTransferCounter register, but the HCD reads or writes the buffer RAM by 16 bits (by 1 data word). (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 68 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 11. Power supply The ISP1160 can operate at either 5 V or 3.3 V. When using 5 V as the ISP1160's power supply input, only VCC (pin 56) can be connected to the 5 V power supply. An application with a 5 V power supply input is shown in Figure 29. The ISP1160 has an internal DC/DC regulator to provide 3.3 V for its internal core. This internal 3.3 V can also be obtained from VREG(3V3) (pin 58). When using 3.3 V as the power supply input, the internal DC/DC regulator will be bypassed. All four power supply pins (VCC, VREG(3V3), VHOLD1 and VHOLD2) can be used as power supply input. It is recommended that you connect all four power supply pins to the 3.3 V power supply, as shown in Figure 30. If, however, you have board space (routing area) constraints, you must connect at least VCC and VREG(3V3) to the 3.3 V power supply. For both 3.3 V and 5 V operation, all four power supply pins should be connected to a decoupling capacitor. +3.3 V +5 V ISP1160 ISP1160 VCC VCC VREG(3V3) VREG(3V3) VHOLD1 VHOLD1 VHOLD2 VHOLD2 GND GND 004aaa068 004aaa069 Fig 29. Using a 5 V supply. Fig 30. Using a 3.3 V supply. 12. Crystal oscillator The ISP1160 has a crystal oscillator designed for a 6 MHz parallel-resonant crystal (fundamental). A typical circuit is shown in Figure 31. Alternatively, an external clock signal of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open. See Figure 32. The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL. VCC ISP1160 6 MHz ISP1160 Out 18 pF OSC XTAL2 6 MHz XTAL2 n.c. XTAL1 18 pF XTAL1 004aaa071 004aaa070 Fig 31. Oscillator circuit with external crystal. Fig 32. Oscillator circuit using external oscillator. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 69 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 13. Power-on reset (POR) When VCC is directly connected to the RESET_N pin, the internal pulse width (tPORP) will be typically (600 ns to 1000 ns) + X, when VCC is 3.3 V. The time X depends on how fast VCC is rising with respect to Vtrip (2.03 V). The time X is decided by the external power supply circuit. To give a better view of the functionality, Figure 33 shows a possible curve of VCC(POR) with dips at t2-t3 and t4-t5. If the dip at t4-t5 is too short (that is, <11 s), the internal POR pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1, the detector will see the passing of the trip level and a delay element will add another tPORP before it drops to 0. The internal POR pulse will be generated whenever VCC(POR) drops below Vtrip for more than 11 s. Even if VCC is 5.0 V, Vtrip still remains at 2.03 V. This is because the 5 V tolerant pads and on-chip voltage regulator ensure that 3.3 V is going to the internal POR circuitry by clipping the voltage above 3.3 V. V BAT(POR) V trip t0 t1 t t2 t4 t3 t PORP t5 PORP (1) PORP 004aaa389 (1) PORP = power-on reset pulse. Fig 33. Internal POR timing. The RESET_N pin can be either connected to VCC (using the internal POR circuit) or externally controlled (by the microprocessor, ASIC, and so on). Figure 34 shows the availability of the clock with respect to the external POR. POR EXTERNAL CLOCK 004aaa365 A Stable external clock is available at A. Fig 34. Clock with respect to the external POR. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 70 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 14. Limiting values Table 66: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC(5V0) Min Max Unit supply voltage to pin VCC -0.5 +6.0 V VCC(3V3) supply voltage to pin VREG(3V3) -0.5 +4.6 V VI input voltage Ilu latch-up current VI < 0 or VI > VCC Vesd electrostatic discharge voltage ILI < 1 A Tstg storage temperature [1] Conditions [1] -0.5 +6.0 V - 100 mA -2000 +2000 V -60 +150 C Equivalent to discharging a 100 pF capacitor via a 1.5 k resistor (Human Body Model). 15. Recommended operating conditions Table 67: Recommended operating conditions Symbol Parameter Conditions Min VCC supply voltage with internal regulator 4.0 5.0 5.5 V internal regulator bypass 3.0 3.3 3.6 V 0 VCC 5.5 V 0 - 3.6 V [1] Typ Max Unit VI input voltage VI(AI/O) input voltage on analog I/O pins D+ and D- VO(od) open-drain output pull-up voltage 0 - VCC V Tamb ambient temperature -40 - +85 C [1] Maximum value is 5 V tolerant. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 71 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 16. Static characteristics Table 68: Static characteristics; supply pins VCC = 3.0 V to 3.6 V or 4.0 V to 5.5 V; VGND = 0 V; Tamb = -40 C to +85 C; typical values at Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VCC = 5 V [1] VREG(3V3) internal regulator output 3.0 3.3 3.6 V ICC operating supply current - 47 - mA ICC(susp) suspend supply current - 40 500 A VCC = 3.3 V ICC operating supply current ICC(susp) suspend supply current [1] [2] [2] - 50 - mA - 150 500 A In the suspend mode, the minimum voltage is 2.7 V. For details on power consumption, refer to Philips Application Note AN10022 ISP1160x Low Power Consumption. Table 69: Static characteristics: digital pins VCC = 3.0 V to 3.6 V or 4.0 V to 5.5 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Input levels VIL LOW-level input voltage - - 0.8 V VIH HIGH-level input voltage 2.0 - - V Schmitt trigger inputs Vth(LH) positive-going threshold voltage 1.4 - 1.9 V Vth(HL) negative-going threshold voltage 0.9 - 1.5 V Vhys hysteresis voltage 0.4 - 0.7 V - - 0.4 V - - 0.1 V 2.4 - - V VREG(3V3) - 0.1 - - V -5 - +5 A - - 5 pF -5 - +5 A Output levels VOL LOW-level output voltage IOL = 4 mA VOH HIGH-level output voltage IOH = 4 mA IOL = 20 A [1] IOH = 20 A Leakage current ILI input leakage current CIN pin capacitance [2] pin to GND Open-drain outputs OFF-state output current IOZ [1] [2] Not applicable for open-drain outputs. The maximum and minimum values are applicable to transistor input only. The value will be different if internal pull-up or pull-down resistors are used. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 72 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Table 70: Static characteristics: analog I/O pins D+ and D- VCC = 3.0 V to 3.6 V or 4.0 V to 5.5 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VDI differential input sensitivity |VI(D+) - VI(D-)| 0.2 - - V VCM differential common mode voltage includes VDI range 0.8 - 2.5 V VIL LOW-level input voltage - - 0.8 V VIH HIGH-level input voltage 2.0 - - V Input levels [1] Output levels VOL LOW-level output voltage RL = 1.5 k to +3.6 V - - 0.3 V VOH HIGH-level output voltage RL = 15 k to GND 2.8 - 3.6 V -10 - +10 A Leakage current OFF-state leakage current ILZ Capacitance transceiver capacitance pin to GND - - 10 pF RPD pull-down resistance on HC's D+/D- enable internal resistors 10 - 20 k ZDRV driver output impedance steady-state drive 29 - 44 ZINP input impedance 10 - - M CIN Resistance [1] [2] [2] D+ is the USB positive data pin; D- is the USB negative data pin. Includes external resistors of 18 1 % on both pins H_D+ and H_D-. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 73 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 17. Dynamic characteristics Table 71: Dynamic characteristics VCC = 3.0 V to 3.6 V or 4.0 V to 5.5 V; VGND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 160 - - s - - - ms Reset tW(RESET_N) pulse width on input RESET_N crystal oscillator running crystal oscillator stopped [1] Crystal oscillator fXTAL crystal frequency - 6 - MHz RS series resistance - - 100 CLOAD load capacitance - 18 - pF Cx1, Cx2 = 22 pF External clock input tJ external clock jitter - - 500 ps tDUTY clock duty cycle 45 50 55 % tCR, tCF rise time and fall time - - 3 ns [1] Dependent on the crystal oscillator start-up time. Table 72: Dynamic characteristics: analog I/O pins D+ and D- VCC = 3.0 V to 3.6 V or 4.0 V to 5.5 V; VGND = 0 V; Tamb = -40 C to +85 C; CL = 50 pF; see Figure 42 for test circuit; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Driver characteristics tFR rise time CL = 50 pF; 10 % to 90 % of |VOH - VOL| 4 - 20 ns tFF fall time CL = 50 pF; 90 % to 10 % of |VOH - VOL| 4 - 20 ns FRFM differential rise/fall time matching (tFR/tFF) 90 - 111.11 % VCRS output signal crossover voltage 1.3 - 2.0 V [1] [2] [1] [1][2] Excluding the first transition from Idle state. Characterized only, not tested. Limits guaranteed by design. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 74 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 17.1 Programmed I/O timing Table 73: Dynamic characteristics: programmed interface timing Symbol Parameter tAS tAH Conditions Min Typ Max Unit address set-up time before WR_N HIGH 5 - - ns address hold time after WR_N HIGH 8 - - ns tSHSL first RD_N/WR_N after A0 HIGH 300 - - ns tSLRL CS_N LOW to RD_N LOW 0 - - ns tRHSH RD_N HIGH to CS_N HIGH 0 - - ns tRLRH RD_N LOW pulse width 33 - - ns tRHRL RD_N HIGH to next RD_N LOW 110 - - ns TRC RD_N cycle 143 - - ns tRHDZ RD_N data hold time 3 - 22 ns tRLDV RD_N LOW to data valid - - 32 ns tWL WR_N LOW pulse width 26 - - ns tWHWL WR_N HIGH to next WR_N LOW 110 - - ns TWC WR_N cycle 136 - - ns tSLWL CS_N LOW to WR_N LOW 0 - - ns tWHSH WR_N HIGH to CS_N HIGH 0 - - ns tWDSU WR_N data set-up time 5 - - ns tWDH WR_N data hold time 8 - - ns Read timing Write timing (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 75 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller CS_N t SLWL t SLRL t SHSL t RLRH A0 t WHSH t RHSH t RHRL T RC RD_N t RLDV t RHDZ D [15:0] data valid tAS data valid data valid data valid t WHWL t AH t WL TWC WR_N t WDH data valid D [15:0] data valid t WDSU data valid data valid data valid 004aaa367 Fig 35. Programmed interface timing. 17.2 DMA timing 17.2.1 Table 74: Single-cycle DMA timing Dynamic characteristics: single-cycle DMA timing Symbol Parameter Conditions Min Typ Max Unit Read/write timing tRLRH RD_N pulse width 33 - - ns tRLDV read process data set-up time 26 - - ns tRHDZ read process data hold time 0 - 20 ns tWSU write process data set-up time 5 - - ns tWHD write process data hold time 0 - - ns tAHRH DACK_N HIGH to DREQ HIGH 72 - - ns tALRL DACK_N LOW to DREQ LOW - - 21 ns - - - ns [1] TDC DREQ cycle tSHAH RD_N/WR_N HIGH to DACK_N HIGH 0 - - ns tRHAL DREQ HIGH to DACK_N LOW 0 - - ns tDS DREQ pulse spacing 146 - - ns [1] TDC = tRHAL + tDS + tALRL (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 76 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller T DC DREQ t DS t ALRL t SHAH t RHAL DACK_N t AHRH t RLDV D [15:0] (read) t RHDZ data valid D [15:0] (write) data valid t WSU RD_N or WR_N 004aaa371 t WHD Fig 36. Single-cycle DMA timing. 17.2.2 Table 75: Burst mode DMA timing Dynamic characteristics: burst mode DMA timing Symbol Parameter Conditions Min Typ Max Unit Read/write timing (for 4-cycle and 8-cycle burst mode) tRLRH WR_N/RD_N LOW pulse width 42 - - ns tRHRL WR_N/RD_N HIGH to next WR_N/RD_N LOW 60 - - ns TRC WR_N/RD_N cycle 102 - - ns tSLRL RD_N/WR_N LOW to DREQ LOW 22 - 64 ns tSHAH RD_N/WR_N HIGH to DACK_N HIGH 0 - - ns tSLAL DREQ HIGH to DACK_N LOW 0 - - ns - - - ns - - ns [1] TDC DREQ cycle tDS(read) DREQ pulse spacing (read) 4-cycle burst mode 105 tDS(read) DREQ pulse spacing (read) 8-cycle burst mode 150 - - ns tDS(write) DREQ pulse spacing (write) 4-cycle burst mode 72 - - ns tDS(write) DREQ pulse spacing (write) 8-cycle burst mode 167 - - ns tRLIS RD_N/WR_N LOW to EOT LOW 0 - - ns [1] TDC = tSLAL + (4 or 8)TRC + tDS (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 77 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller t DS DREQ t RHSH t SLRL t SLAL DACK_N t SHAH t RHRL RD_N or WR_N 004aaa372 T RC t RLRH Fig 37. Burst mode DMA timing. 17.2.3 External EOT timing for single-cycle DMASETUP DREQ DACK_N RD_N or WR_N EOT t RLIS > 0 ns 004aaa373 Fig 38. External EOT timing for single-cycle DMA. 17.2.4 External EOT timing for burst mode DMA DREQ DACK_N RD_N or WR_N EOT t RLIS > 0 ns 004aaa374 Fig 39. External EOT timing for burst mode DMA. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 78 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 18. Application information 18.1 Typical interface circuit +5 V +3.3 V VDD +5 V +3.3 V +5 V MOSFET (2x) SH7709 ISP1160 Vbus_DN2 Vbus_DN1 VCC +3.3 V +5 V D[15:0] D[15:0] A1 A0 CS5 RD_N RD/WR_N CS_N RD_N WR_N DREQ0 DACK0_N DREQ DACK_N H_OC1_N H_OC2_N H_PSW2_N H_PSW1_N H_DM1 H_DP1 H_DM2 H_DP2 EXTAL CLKOUT Vreg FB3 22 (2x) VHOLD1 VHOLD2 INT PTC0 PTC1 H_WAKEUP NDP_SEL H_SUSPEND USB downstream port #2 VDD 47 pF (2x) XTAL EXTAL2 FB2 +3.3 V EOT IRQ2 USB downstream port #1 47 pF (2x) VREG(3V3) +5 V FB1 22 (2x) FB4 32 kHz XTAL2 RESET_N RSTOUT XTAL2 6 MHz XTAL1 GND 7 DGND AGND 22 pF 22 pF 004aaa072 For MOSFET, RDSon = 150 m. Fig 40. Typical interface circuit to Hitachi SH-3 (SH7709) RISC processor. 18.2 Interfacing a ISP1160 to a SH7709 RISC processor This section shows a typical interface circuit between the ISP1160 and a RISC processor. The Hitachi SH-3 series RISC processor SH7709 is used as the example. The main ISP1160 signals to be taken into consideration for connecting to a SH7709 RISC processor are: * A 16-bit data bus: D[15:0] for the ISP1160. The ISP1160 is `little endian' compatible. * The address line A0 is needed for a complete addressing of the ISP1160 internal registers: - A0 = 0 will select the Data Port of the Host Controller - A0 = 1 will select the Command Port of the Host Controller * The CS_N line is used for chip selection of the ISP1160 in a certain address range of the RISC system. This signal is active LOW. * RD_N and WR_N are common read and write signals. These signals are active LOW. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 79 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller * There is a DMA channel standard control line: DREQ and DACK_N. The DREQ signal has programmable active levels. * An interrupt line INT is used by the HC. It has programmable level/edge and polarity (active HIGH or LOW). * The internal 15 k pull-down resistors are used for the HC's two USB downstream ports. * The RESET_N signal is active LOW. Remark: SH7709's system clock input is for reference only. Refer to SH7709's specification for its actual use. The ISP1160 can work under either 3.3 V or 5.0 V power supply; however, its internal core works at 3.3 V. When using 3.3 V as the power supply input, the internal DC/DC regulator will be bypassed. It is best to connect all four power supply pins (VCC, VREG(3V3), VHOLD1 and VHOLD2) to the 3.3 V power supply (for more information, see Section 11). All of the ISP1160's I/O pins are 5 V-tolerant. This feature allows the ISP1160 the flexibility to be used in an embedded system under either a 3.3 V or a 5 V power supply. A typical SH7709 interface circuit is shown in Figure 40. 18.3 Typical software model This section shows a typical software requirement for an embedded system that incorporates the ISP1160. The software model for a Digital Still Camera (DSC) is used as the example for illustration (as shown in Figure 41). The host stack provides API for Class driver and device driver, both of which provide API for application tasks for host function. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 80 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Application layer MECHANISM CONTROL TASK IMAGE PROCESSING TASKS FILE MANAGEMENT PRINTER UI/CONTROL OS DEVICE DRIVERS Class driver MASS STORAGE CLASS DRIVER PRINTING CLASS DRIVER USB host stack HOST STACK ISP1160 HAL USB Upstream Printer RISC LEN CONTROL ROM ISP1160 RAM Flash card Reader/ Writer USB Downstream 004aaa073 Digital Still Camera Fig 41. The ISP1160 software model for DSC application. 19. Test information The dynamic characteristics of the analog I/O pins D+ and D- as listed in Table 72 were determined using the circuit shown in Figure 42. test point 22 D.U.T. 15 k CL 50 pF MGT967 Full-speed mode: load capacitance CL = 50 pF. Full-speed mode only: internal 1.5 k pull-up resistor on pin D+. Fig 42. Load impedance. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 81 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 20. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.5 HD HE 12.15 12.15 11.85 11.85 L Lp v w y 1 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT314-2 136E10 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 43. LQFP64 (SOT314-2) package outline. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 82 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm SOT414-1 c y X 48 A 33 49 32 ZE e A A2 E HE (A 3) A1 wM bp pin 1 index Lp L 64 17 1 detail X 16 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.15 0.05 1.45 1.35 0.25 0.23 0.13 0.20 0.09 7.1 6.9 7.1 6.9 0.4 9.15 8.85 9.15 8.85 1 0.75 0.45 0.2 0.08 0.08 Z D (1) Z E (1) 0.64 0.36 0.64 0.36 o 7 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT414-1 136E06 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-20 Fig 44. LQFP64 (SOT414-1) package outline. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 83 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 21. Soldering 21.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. In these situations reflow soldering is recommended. 21.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 21.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 84 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 21.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 21.5 Package related soldering information Table 76: Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] Soldering method BGA, HTSSON..T[3], LBGA, LFBGA, SQFP, SSOP..T[3], TFBGA, USON, VFBGA Reflow[2] not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable[4] HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS suitable PLCC[5], SO, SOJ suitable suitable recommended[5][6] suitable LQFP, QFP, TQFP not SSOP, TSSOP, VSO, VSSOP not recommended[7] suitable CWQCCN..L[8], not suitable not suitable [1] [2] PMFP[9], WQCCN..L[8] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Wave Rev. 05 -- 24 December 2004 85 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages. [4] [5] [6] [7] [8] [9] 22. Revision history Table 77: Revision history Rev Date 05 CPCN 20041224 200412019 Description Product data (9397 750 13963) Modifications: * * Figure 2 "Pin configuration LQFP64.": added a figure note. * Section 9.8.1 "Using an internal OC detection circuit": fourth paragraph, second sentence, changed source to drain and drain to source. Table 2 "Pin description LQFP64": in the description for pin 60, changed address A1 to A2. 04 20030704 - Product data (9397 750 11371) 03 20030227 - Product data (9397 750 10765) 02 20020912 - Product data (9397 750 09628) 01 20020104 - Objective data (9397 750 09161) (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Product data Rev. 05 -- 24 December 2004 86 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller 23. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 24. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 25. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 26. Trademarks ARM7 and ARM9 -- are trademarks of ARM Ltd. GoodLink -- is a trademark of Koninklijke Philips Electronics N.V. Hitachi -- is a registered trademark of Hitachi Ltd. MIPS-based -- is a trademark of MIPS Technologies, Inc. SoftConnect -- is a trademark of Koninklijke Philips Electronics N.V. StrongARM -- is a registered trademark of ARM Ltd. SuperH -- is a trademark of Hitachi Ltd. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. Product data Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 13963 Rev. 05 -- 24 December 2004 87 of 88 ISP1160 Philips Semiconductors Embedded USB Host Controller Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10 10.1 10.2 10.3 10.4 10.5 10.6 11 12 13 14 15 16 17 17.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 8 PLL clock multiplier. . . . . . . . . . . . . . . . . . . . . . 8 Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . . 8 Analog transceivers . . . . . . . . . . . . . . . . . . . . . 8 Philips Serial Interface Engine (SIE). . . . . . . . . 8 Microprocessor bus interface. . . . . . . . . . . . . . 8 Programmed I/O (PIO) addressing mode . . . . . 8 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Control registers access by PIO mode . . . . . . 10 FIFO buffer RAM access by PIO mode . . . . . 11 FIFO buffer RAM access by DMA mode. . . . . 12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Host Controller (HC) . . . . . . . . . . . . . . . . . . . . 16 HC's four USB states . . . . . . . . . . . . . . . . . . . 16 Generating USB traffic . . . . . . . . . . . . . . . . . . 17 PTD data structure . . . . . . . . . . . . . . . . . . . . . 19 HC's internal FIFO buffer RAM structure . . . . 22 HC operational model . . . . . . . . . . . . . . . . . . . 28 Microprocessor loading. . . . . . . . . . . . . . . . . . 31 Internal pull-down resistors for downstream ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Overcurrent detection and power switching control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Suspend and wake-up . . . . . . . . . . . . . . . . . . 34 HC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 HC control and status registers . . . . . . . . . . . 37 HC frame counter registers. . . . . . . . . . . . . . . 44 HC Root Hub registers . . . . . . . . . . . . . . . . . . 48 HC DMA and interrupt control registers . . . . . 57 HC miscellaneous registers . . . . . . . . . . . . . . 62 HC buffer RAM control registers . . . . . . . . . . . 64 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 69 Power-on reset (POR) . . . . . . . . . . . . . . . . . . . 70 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 71 Recommended operating conditions. . . . . . . 71 Static characteristics. . . . . . . . . . . . . . . . . . . . 72 Dynamic characteristics . . . . . . . . . . . . . . . . . 74 Programmed I/O timing. . . . . . . . . . . . . . . . . . 75 (c) Koninklijke Philips Electronics N.V. 2004. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 24 December 2004 Document order number: 9397 750 13963 17.2 18 18.1 18.2 18.3 19 20 21 21.1 21.2 21.3 21.4 21.5 22 23 24 25 26 DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Typical interface circuit . . . . . . . . . . . . . . . . . . Interfacing a ISP1160 to a SH7709 RISC processor. . . . . . . . . . . . . . . . . . . . . . . Typical software model . . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 79 79 79 80 81 82 84 84 84 84 85 85 86 87 87 87 87