ADVANCED AND EVER ADVANCING MITSUBISHI ELECTRIC MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER 7700 FAMILY / 7700 SERIES 7733 Group 7735 Group 7736 Group User's Manual MITSUBISHI ELECTRIC keep safety first in your circuit designs ! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Preface This manual describes the hardware of the Mitsubishi CMOS 16-bit microcomputers 7733/7735/7736 Group. After reading this manual, the user will be able to understand the functions, so that the capabilities of the microcomputers can fully be utilized. For details concerning the software for the 7733/7735/ 7736 Group, refer to the 7700 Family Software Manual. BEFORE USING THIS MANUAL 1. INTRODUCTION This manual consists of the following: PART 1: 7733 Group, PART 2: 7735 Group, and PART 3: 7736 Group. The peripheral functions are common to all of these groups, but the external bus mode differs according to the group, as follows: * 7733 Group: external bus mode A is assigned. * 7735 Group: external bus mode B is assigned. * 7736 Group: external bus mode A or B is selectable. In parts 2 and 3, only the differences occurring between the 7735/7736 Group and the 7733 Group are described. Also, the chapter, section, table and figure numbers are the same as those in part 1 and the differences are described by the section. PART 1: 7733 Group Chapter 1. OVERVIEW through Chapter 17. APPLICATIONS The common functions of the 7733 Group microcomputers are described. The M37733MHBXXXFP is used as a typical microcomputer in this group to describe all common functions. Chapter 18. LOW VOLTAGE VERSION Read this chapter when using the microcomputers with the electrical characteristics indicated by "L." (See page 1-2 in part 1.) Ex.: M37733MHLXXXHP The differences between the M37733MHLXXXHP, which is a typical low voltage version of the 7733 Group, and the M37733MHBXXXFP are described. Chapter 19. BUILT-IN PROM VERSION Read this chapter when using the microcomputers with the memory type indicated by "E." (See page 1-2 in part 1.) Ex.: M37733EHBXXXFP The differences between the M37733EHBXXXFP, which is a typical built-in PROM version of the 7733 Group, and the M37733MHBXXXFP are described. Chapter 20. EXTERNAL ROM VERSION Read this chapter when using the microcomputers with the memory type indicated by "S." (See page 1-2 in part 1.) Ex.: M37733S4BFP The differences between the M37733S4BFP, which is a typical external ROM version of the 7733 Group, and the M37733MHBXXXFP are described. APPENDIX Practical information for using the 7733 Group is described . PART 2: 7735 Group, PART 3: 7736 Group Refer to the table on the next page. I BEFORE USING THIS MANUAL PART 1 7733 Group PART 2 (Note 1) PART 3 (Note 1) 7735 Group 7736 Group CHAPTER 1. OVERVIEW Refer to part 2: 7735 Group CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) Refer to part 3: 7736 Group CHAPTER 3. PROGRAMMABLE I/O PORTS CHAPTER 4. INTERRUPTS CHAPTER 5. KEY INPUT INTERRUPTS Refer to part 1: 7733 Group CHAPTER 6. TIMER A Refer to part 1: 7733 Group CHAPTER 7. TIMER B CHAPTER 8. SERIAL I/O CHAPTER 9. A-D CONVERTER CHAPTER 10. WATCHDOG TIMER CHAPTER 11. STOP AND WAIT MODES Refer to part 1: 7733 Group CHAPTER 12. CONNECTING EXTERNAL DEVICES CHAPTER 13. RESET Refer to part 2: 7735 Group Refer to part 3: 7736 Group (Note 2) CHAPTER 14. CLOCK GENERATING CIRCUIT CHAPTER 15. ELECTRICAL CHARACTERISTICS CHAPTER 16. STANDARD CHARACTERISTICS Refer to part 1: 7733 Group CHAPTER 17. APPLICATIONS CHAPTER 18. LOW VOLTAGE VERSION CHAPTER 19. BUILT-IN PROM VERSION Refer to part 2: 7735 Group CHAPTER 20. EXTERNAL ROM VERSION APPENDIX Refer to part 3: 7736 Group Note 1: In part 2 and 3, when there is no reference provided about the part, refer to the corresponding chapter/section in that part. 2: When referring to the chapters and sections listed below, use the following guide: External bus mode A: refer to part 1, External bus mode B: refer to part 2. * Chapter 11. STOP AND WAIT MODES * Chapter 12. CONNECTING EXTERNAL DEVICES" * Chapter 15. ELECTRICAL CHARACTERISTICS" (electrical characteristics related to the external bus mode) * Paragraph 17.1 Memory expansion * Chapter 18. LOW VOLTAGE VERSION (electrical characteristics related to the external bus mode) * Paragraph 18.6 Applications 2. NOTES For product expansion information, refer to the latest catalog and data book, or contact the appropriate office, as listed in "CONTACT ADDRESSES FOR FURTHER INFORMATION" on the last page. Always refer to the latest data book for electrical characteristics. This manual does not include the forms listed below. When necessary, copy the corresponding page of the latest data book, or contact the appropriate office, as listed in "CONTACT ADDRESSES FOR FURTHER INFORMATION": * MASK ROM ORDER CONFIRMATION FORM * PROM ORDER CONFIRMATION FORM * MARK SPECIFICATION FORM For details concerning development support tools, refer to the latest data book of development support tools. For details concerning software, refer to the 7700 Family Software Manual. II BEFORE USING THIS MANUAL 3. REGISTER STRUCTURE Below is the structure diagram for all registers. 1 b7 b6 b5 b4 b3 b2 b1 b0 XXX register (address XX 16) 0 2 Bit name Bit Functions 0 ... select bit 0 : ... 1 : ... 1 ... select bit 0 : ... 1 : ... The value is "0" at reading. 2 ... flag 0 : ... 1 : ... 3 At reset RW 0 RW Undefined WO 0 RO 3 Fix this bit to "0." 0 RW 4 This bit is ignored in ... mode. 0 RW Undefined - 7 to 5 Not implemented. 4 1 Blank 0 1 2 : Set to "0" or "1" according to the usage. : Set to "0" at writing. : Set to "1" at writing. : Ignored depending on the mode or state. It may be "0" or "1." : Not implemented. 0 1 Undefined : "0" immediately after reset. : "1" immediately after reset. : Undefined immediately after reset. 3 RW RO WO -- : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written value may be "0" or "1." : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading. However, when ["0" at reading] is indicated in the "Function" or "Note" column, the bit is always "0" at reading.(See to 4 above.) : It is impossible to read the bit state. The value is undefined at reading. However, when ["0" at reading] is indicated in the "Function" or "Note" column, the bit is always "0" at reading.(See to 4 above.) The written value becomes invalid. Accordingly, the written value may be "0" or "1." III Table of contents Table of contents PART 1 7733 Group CHAPTER 1. OVERVIEW 1.1 Performance overview........................................................................................................... 1-3 1.2 Pin configuration.................................................................................................................... 1-4 1.3 Pin description ....................................................................................................................... 1-5 1.3.1 Examples of handling unused pins .............................................................................. 1-8 1.4 Block diagram ....................................................................................................................... 1-11 CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit ........................................................................................................ 2-2 2.1.1 Accumulator (Acc) .......................................................................................................... 2-3 2.1.2 Index register X (X) ........................................................................................................ 2-3 2.1.3 Index register Y (Y) ........................................................................................................ 2-3 2.1.4 Stack pointer (S) ............................................................................................................. 2-4 2.1.5 Program counter (PC) .................................................................................................... 2-5 2.1.6 Program bank register (PG) .......................................................................................... 2-5 2.1.7 Data bank register (DT) ................................................................................................. 2-6 2.1.8 Direct page register (DPR) ............................................................................................ 2-6 2.1.9 Processor status register (PS) ...................................................................................... 2-8 2.2 Bus interface unit ................................................................................................................ 2-10 2.2.1 Overview ........................................................................................................................ 2-10 2.2.2 Functions of bus interface unit (BIU) ........................................................................ 2-12 2.2.3 Operation of bus interface unit (BIU) ........................................................................ 2-14 2.3 Accessible area .................................................................................................................... 2-16 2.3.1 Banks ............................................................................................................................. 2-17 2.3.2 Direct page .................................................................................................................... 2-17 2.4 Memory allocation ................................................................................................................ 2-18 2.4.1 Memory allocation in internal area .............................................................................2-18 2.5 Processor modes ................................................................................................................. 2-24 2.5.1 Single-chip mode .......................................................................................................... 2-25 2.5.2 Memory expansion and Microprocessor modes ....................................................... 2-25 2.5.3 Setting of processor modes ........................................................................................ 2-28 CHAPTER 3. PROGRAMMABLE I/O PORTS 3.1 Programmable I/O ports ....................................................................................................... 3-2 3.1.1 Port Pi direction register ................................................................................................ 3-3 3.1.2 Port Pi register ................................................................................................................ 3-4 3.2 Port peripheral circuits ......................................................................................................... 3-6 3.3 Pull-up function ...................................................................................................................... 3-8 ___ ___ 3.3.1 Pull-up function for ports P5 4 to P57 ( KI 0 to KI 3) ...................................................... 3-8 ____ ____ 3.3.2 Pull-up function for ports P62 to P6 4 ( INT0 to INT 2) ................................................. 3-8 3.4 Internal peripheral devices' I/O functions (Ports P42 and P5 to P8) ...................... 3-10 7733 Group User's Manual i Table of contents CHAPTER 4. INTERRUPTS 4.1 Overview .................................................................................................................................. 4-2 4.2 Interrupt sources .................................................................................................................... 4-4 4.3 Interrupt control ..................................................................................................................... 4-6 4.3.1 Interrupt disable flag (I) .................................................................................................4-8 4.3.2 Interrupt request bit ........................................................................................................ 4-8 4.3.3 Interrupt priority level selection bits and Processor interrupt priority level (IPL) .. 4-8 4.4 Interrupt priority level ......................................................................................................... 4-10 4.5 Interrupt priority level detection circuit ......................................................................... 4-11 4.6 Interrupt priority level detection time ............................................................................. 4-13 4.7 How interrupts are processed (from acceptance of interrupt request until execution of interrupt routine) ........................................................................................ 4-14 4.7.1 Change in IPL at acceptance of interrupt request ................................................... 4-15 4.7.2 How to push registers .................................................................................................. 4-16 4.8 Return from interrupt routine............................................................................................ 4-17 4.9 Multiple interrupts ................................................................................................................ 4-17 ____ 4.10 External interrupts (INTi interrupt) ................................................................................. 4-19 ____ 4.10.1 INTi interrupt request bit's function .......................................................................... 4-21 ____ 4.10.2 How to switch INTi interrupt request occurrence condition ................................... 4-22 4.11 Precautions for interrupts ................................................................................................ 4-23 CHAPTER 5. KEY INPUT INTERRUPT FUNCTION 5.1 Overview .................................................................................................................................. 5-2 5.2 Block description ................................................................................................................... 5-3 ___ ___ ____ 5.2.1 Pins KI 0 to KI 3 and P6 4/ INT 2 ................................................................................................................................ 5-3 5.2.2 Port function control register ......................................................................................... 5-4 5.2.3 Interrupt function ............................................................................................................. 5-6 5.3 Initial setting example for related registers ....................................................................5-7 CHAPTER 6. TIMER A 6.1 Overview .................................................................................................................................. 6-2 6.2 Block description ................................................................................................................... 6-3 6.2.1 Counter and reload register (Timer Ai register) ........................................................ 6-4 6.2.2 Count start flag ............................................................................................................... 6-5 6.2.3 Timer Ai mode register .................................................................................................. 6-6 6.2.4 Timer Ai interrupt control register ................................................................................ 6-7 6.2.5 Port P5 and port P6 direction registers ......................................................................6-8 6.3 Timer mode (Bits 1 and 0 of timer Ai mode register = "00 2") .................................. 6-9 6.3.1 Setting for timer mode ................................................................................................. 6-11 6.3.2 Count source ................................................................................................................. 6-13 6.3.3 Operation in timer mode .............................................................................................. 6-14 6.3.4 Selectable functions ..................................................................................................... 6-15 6.4 Event counter mode (Bits 1 and 0 of timer Ai mode register = "012") ................. 6-19 6.4.1 Setting for event counter mode .................................................................................. 6-23 6.4.2 Operation in event counter mode ............................................................................... 6-25 6.4.3 Selectable functions ..................................................................................................... 6-27 ii 7733 Group User's Manual Table of contents 6.5 One-shot pulse mode (Bits 1 and 0 of timer Ai mode register = "102") ............... 6-32 6.5.1 Setting for one-shot pulse mode ................................................................................6-34 6.5.2 Count source ................................................................................................................. 6-36 6.5.3 Trigger ............................................................................................................................ 6-37 6.5.4 Operation in one-shot pulse mode .............................................................................6-38 6.6 Pulse width modulation (PWM) mode (Bits 1 and 0 of timer Ai mode register = "112") .................. 6-41 6.6.1 Setting for PWM mode ................................................................................................ 6-43 6.6.2 Count source ................................................................................................................. 6-45 6.6.3 Trigger ............................................................................................................................ 6-46 6.6.4 Operation in PWM mode ............................................................................................. 6-47 CHAPTER 7. TIMER B 7.1 Overview .................................................................................................................................. 7-2 7.2 Block description ................................................................................................................... 7-3 7.2.1 Counter and Reload register (Timer Bi register) ....................................................... 7-4 7.2.2 Count start flag ............................................................................................................... 7-5 7.2.3 Timer Bi mode register .................................................................................................. 7-6 7.2.4 Timer Bi interrupt control register ................................................................................ 7-7 7.2.5 Port P6 direction register .............................................................................................. 7-8 7.2.6 Port function control register ......................................................................................... 7-9 7.3 Timer mode (Bits 1 and 0 of timer Bi mode register = "00 2") ................................ 7-10 7.3.1 Setting for timer mode ................................................................................................. 7-12 7.3.2 Count source ................................................................................................................. 7-14 7.3.3 Operation in timer mode .............................................................................................. 7-15 7.4 Event counter mode (Bits 1 and 0 of timer Bi mode register = "012") ................. 7-17 7.4.1 Setting for event counter mode .................................................................................. 7-19 7.4.2 Operation in event counter mode ...............................................................................7-21 7.4.3 Selectable functions ..................................................................................................... 7-22 7.5 Pulse period/Pulse width measurement mode (Bits 1 and 0 of timer Bi mode register = "102 ") ... 7-25 7.5.1 Setting for pulse period/pulse width measurement mode ...................................... 7-27 7.5.2 Count source ................................................................................................................. 7-29 7.5.3 Operation in pulse period/pulse width measurement mode ................................... 7-30 7.6 Clock timer ............................................................................................................................ 7-34 7.6.1 Setting for clock timer .................................................................................................. 7-37 7.6.2 Operation of clock timer .............................................................................................. 7-38 CHAPTER 8. SERIAL I/O 8.1 Overview .................................................................................................................................. 8-2 8.2 Block description ................................................................................................................... 8-4 8.2.1 UARTi transmit/receive mode register ......................................................................... 8-5 8.2.2 UARTi transmit/receive control register 0 ...................................................................8-8 8.2.3 UARTi transmit/receive control register 1 ................................................................ 8-10 8.2.4 Serial transmit control register .................................................................................... 8-12 8.2.5 UARTi transmission register and UARTi transmission buffer register .................. 8-13 8.2.6 UARTi receive register and UARTi receive buffer register .................................... 8-15 8.2.7 UARTi baud rate register (BRGi) ...............................................................................8-17 8.2.8 Interrupt control register related to UARTi ............................................................... 8-18 8.2.9 Ports P7 and P8 direction registers ...........................................................................8-20 7733 Group User's Manual iii Table of contents 8.3 Clock synchronous serial I/O mode ................................................................................ 8-21 8.3.1 Transfer clock (sync clock) ......................................................................................... 8-22 8.3.2 Transfer data format..................................................................................................... 8-26 8.3.3 Method of transmission ................................................................................................ 8-27 8.3.4 Transmit operation ........................................................................................................ 8-32 8.3.5 Method of reception ..................................................................................................... 8-35 8.3.6 Receive operation ......................................................................................................... 8-39 8.3.7 Processing when an overrun error is detected ....................................................... 8-42 8.3.8 Precautions for clock synchronous serial I/O .......................................................... 8-43 8.4 Clock asynchronous serial I/O (UART) mode ............................................................... 8-44 8.4.1 Transfer rate (Baud rate: transfer clock frequency) ................................................ 8-45 8.4.2 Transfer data format..................................................................................................... 8-47 8.4.3 Method of transmission ................................................................................................ 8-49 8.4.4 Transmit operation ........................................................................................................ 8-53 8.4.5 Method of reception ..................................................................................................... 8-56 8.4.6 Receive operation ......................................................................................................... 8-59 8.4.7 Processing when error is detected .............................................................................8-61 8.4.8 Precautions for UART .................................................................................................. 8-61 8.4.9 Sleep mode (UART0 and UART1) .............................................................................8-62 CHAPTER 9. A-D CONVERTER 9.1 Overview .................................................................................................................................. 9-2 9.2 Block description ................................................................................................................... 9-3 9.2.1 A-D control register 0 .................................................................................................... 9-4 9.2.2 A-D control register 1 .................................................................................................... 9-6 9.2.3 A-D register i (i = 0 to 7) .............................................................................................. 9-7 9.2.4 A-D/UART2 trans./rece. interrupt control register ...................................................... 9-8 9.2.5 Port P7 direction register ............................................................................................ 9-10 9.3 A-D conversion method ...................................................................................................... 9-11 9.4 Absolute accuracy and Differential non-linearity error .............................................. 9-14 9.4.1 Absolute accuracy ........................................................................................................ 9-14 9.4.2 Differential non-linearity error ...................................................................................... 9-15 9.4.3 Comparison voltage when resolution = 8 bits ......................................................... 9-16 9.5 One-shot mode ..................................................................................................................... 9-17 9.5.1 Setting for one-shot mode ........................................................................................... 9-17 9.5.2 Operation in one-shot mode........................................................................................ 9-19 9.6 Repeat mode ......................................................................................................................... 9-20 9.6.1 Setting example for repeat mode ............................................................................... 9-20 9.6.2 Operation in repeat mode ........................................................................................... 9-22 9.7 Single sweep mode ............................................................................................................. 9-23 9.7.1 Setting for single sweep mode ................................................................................... 9-23 9.7.2 Operation in single sweep mode ................................................................................ 9-25 9.8 Repeat sweep mode ............................................................................................................ 9-27 9.8.1 Setting for repeat sweep mode .................................................................................. 9-27 9.8.2 Operation in repeat sweep mode ............................................................................... 9-29 9.9 Precautions for A-D converter .......................................................................................... 9-31 CHAPTER 10. WATCHDOG TIMER 10.1 Block description ............................................................................................................... 10-2 10.1.1 Watchdog timer ........................................................................................................... 10-3 10.1.2 Watchdog timer frequency selection flag ................................................................ 10-4 iv 7733 Group User's Manual Table of contents 10.2 Operation description ....................................................................................................... 10-5 10.2.1 Basic operation ........................................................................................................... 10-5 10.2.2 Operation in stop mode ............................................................................................. 10-6 10.2.3 Operation in wait mode ............................................................................................. 10-7 10.2.4 Operation in hold state .............................................................................................. 10-8 10.3 Precautions for watchdog timer ................................................................................... 10-10 CHAPTER 11. STOP AND WAIT MODES 11.1 Overview .............................................................................................................................. 11-2 11.2 Clock generating circuit ................................................................................................... 11-3 11.3 Stop mode ........................................................................................................................... 11-6 11.3.1 Output levels of external bus and bus control signals in stop mode ................. 11-7 11.3.2 Stop mode terminating operation by interrupt request occurrence (when using watchdog timer) 11-9 11.3.3 Stop mode terminating operation by interrupt request occurrence (when not using watchdog timer) .............................................................................................. 11-10 11.3.4 Stop mode terminating operation by hardware reset .......................................... 11-12 11.3.5 Precautions for stop mode ......................................................................................11-12 11.4 Wait mode .......................................................................................................................... 11-13 11.4.1 State of clocks f 2 to f512 in wait mode ................................................................ 11-15 11.4.2 Output levels of external bus and bus control signals in wait mode ............... 11-15 11.4.3 Wait mode terminating operation by interrupt request occurrence ................... 11-17 11.4.4 Wait mode terminating operation by hardware reset .......................................... 11-17 CHAPTER 12. CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices ...................................................... 12-2 12.1.1 External bus (A 0 to A7 , A 8/D 8 to A 15/D 15, and A 16/D 0 to A 23 /D 7) ..................... 12-5 12.1.2 External data bus width selection signal (Pin BYTE's level) ................................ 12-6 __ 12.1.3 Enable signal (E) ........................................................................................................ 12-6 __ 12.1.4 Read/Write signal (R/W) ............................................................................................ 12-6 ____ 12.1.5 Byte high enable signal (BHE) ................................................................................. 12-7 12.1.6 Address latch enable signal (ALE) ...........................................................................12-7 ____ 12.1.7 Signal related to ready function (RDY) .................................................................. 12-7 _____ _____ 12.1.8 Signals related to hold function (HOLD, HLDA) .................................................... 12-7 12.1.9 Clock 1 ....................................................................................................................... 12-7 12.1.10 Operation of bus interface unit (BIU) ................................................................. 12-10 12.2 Software wait .................................................................................................................... 12-13 12.3 Ready function ................................................................................................................. 12-16 12.3.1 Operation in ready state ..........................................................................................12-17 12.4 Hold function .................................................................................................................... 12-19 12.4.1 Operation in hold state ..........................................................................................12-20 CHAPTER 13. RESET 13.1 Hardware reset ................................................................................................................... 13-2 13.1.1 Pin state ...................................................................................................................... 13-3 13.1.2 State of CPU, SFR area, and internal RAM area ................................................. 13-4 13.1.3 Internal processing sequence after a reset ______ ........................................................... 13-9 13.1.4 Time required for applying "L" level to pin RESET ............................................ 13-10 13.2 Software reset................................................................................................................... 13-12 7733 Group User's Manual v Table of contents CHAPTER 14. CLOCK GENERATING CIRCUIT 14.1 Overview .............................................................................................................................. 14-2 14.2 Oscillation circuit example .............................................................................................. 14-3 14.2.1 Main-clock oscillation circuit example ..................................................................... 14-3 14.2.2 Sub-clock oscillation circuit example ...................................................................... 14-4 14.3 Clock control ...................................................................................................................... 14-5 14.3.1 Clock generated in clock generating circuit ........................................................... 14-6 14.3.2 System clock switching procedure ........................................................................ 14-11 14.3.3 Clock transition ......................................................................................................... 14-14 14.3.4 Clock prescaler reset ............................................................................................... 14-15 CHAPTER 15. ELECTRICAL CHARACTERISTICS 15.1 Absolute maximum ratings ............................................................................................. 15-2 15.2 Recommended operating conditions ............................................................................ 15-3 15.3 Electrical characteristics ................................................................................................. 15-4 15.4 A-D converter characteristics ......................................................................................... 15-5 15.5 Internal peripheral devices .............................................................................................. 15-6 15.6 Ready and Hold ............................................................................................................... 15-11 15.7 Single-chip mode ............................................................................................................. 15-13 15.8 Memory expansion mode and microprocessor mode : with no wait ................. 15-15 15.9 Memory expansion mode and microprocessor mode : with wait 1 ................... 15-17 15.10 Memory expansion mode and microprocessor mode : with wait 0 ................. 15-19 _ 15.11 Testing circuit for ports P0 to P8, 1, and E ....................................................... 15-21 CHAPTER 16. STANDARD CHARACTERISTICS 16.1 Standard characteristics .................................................................................................. 16-2 16.1.1 Programmable I/O port (CMOS output) standard characteristics: P0 to P3, P4 0 to P43 , P54 to P57, P6, P7, and P8 ......................................................................................................................................... 16-2 16.1.2 Programmable I/O port (CMOS output) standard characteristics: P44 to P47 and P5 0 to P53 ..... 16-3 16.1.3 Icc-f(XIN) standard characteristics ........................................................................... 16-4 16.1.4 A-D converter standard characteristics .................................................................... 16-5 CHAPTER 17. APPLICATIONS 17.1 Memory expansion ............................................................................................................. 17-2 17.1.1 Memory expansion model .......................................................................................... 17-2 17.1.2 Calculation ways for timing ....................................................................................... 17-4 17.1.3 Points in memory expansion ..................................................................................... 17-7 17.1.4 Memory expansion example ................................................................................... 17-19 17.1.5 I/O expansion example ............................................................................................ 17-25 17.2 Serial I/O ............................................................................................................................ 17-28 17.2.1 Connection examples with external device (Clock synchronous serial I/O mode) .......................17-28 17.2.2 Examples of transmission for several peripheral ICs (Clock synchronous serial I/O mode) ..... 17-30 17.2.3 Transmission/Reception example (UART mode, transfer data length = 8 bits) ........................... 17-33 17.2.4 8-bit transmission example (Clock synchronous serial I/O mode) .................... 17-38 17.3 Watchdog timer ................................................................................................................ 17-41 17.3.1 Program runaway detection example .................................................................... 17-41 vi 7733 Group User's Manual Table of contents 17.4 Power saving .................................................................................................................... 17-44 17.4.1 Power saving example with stop mode used ...................................................... 17-44 17.4.2 Power saving example with wait mode used ....................................................... 17-49 17.5 Timer B............................................................................................................................... 17-54 17.5.1 Application example of clock timer ....................................................................... 17-54 CHAPTER 18. LOW VOLTAGE VERSION 18.1 Performance overview ...................................................................................................... 18-3 18.2 Pin configuration ............................................................................................................... 18-4 18.3 Functional description...................................................................................................... 18-5 18.3.1 Power-on reset condition ........................................................................................... 18-6 18.4 Electrical characteristics ................................................................................................. 18-7 18.4.1 Absolute maximum ratings ........................................................................................ 18-7 18.4.2 Recommended operating conditions ....................................................................... 18-8 18.4.3 Electrical characteristics ............................................................................................ 18-9 18.4.4 A-D converter characteristics ................................................................................. 18-10 18.4.5 Internal peripheral devices ......................................................................................18-11 18.4.6 Ready and Hold ........................................................................................................ 18-16 18.4.7 Single-chip mode ...................................................................................................... 18-18 18.4.8 Memory expansion mode and microprocessor mode : with no wait ................ 18-20 18.4.9 Memory expansion mode and microprocessor mode : with wait 1 .................. 18-22 18.4.10 Memory expansion mode and microprocessor mode : with wait 0 ................ 18-24 _ 18.4.11 Testing circuit for ports P0 to P8, 1 , and E ................................................... 18-26 18.5 Standard characteristics ................................................................................................ 18-27 18.5.1 Programmable I/O port (CMOS output) standard characteristics: P0 to P3, P4 0 to P43 , P54 to P57 , P6, P7, and P8 ...................................................................................................................................... 18-27 18.5.2 Programmable I/O port (CMOS output) standard characteristics: P44 to P4 7 and P50 to P5 3 .. 18-28 18.5.3 Icc-f(X IN) standard characteristics ........................................................................ 18-29 18.5.4 A-D converter standard characteristics ................................................................. 18-30 18.6 Application ........................................................................................................................ 18-32 18.6.1 Memory expansion .................................................................................................... 18-32 18.6.2 Memory expansion example in minimum model .................................................. 18-34 18.6.3 Memory expansion example in medium model A ............................................... 18-36 18.6.4 Memory expansion example in maximum model ................................................. 18-38 18.6.5 Ready generation circuit example ......................................................................... 18-40 CHAPTER 19. BUILT-IN PROM VERSION 19.1 EPROM mode ..................................................................................................................... 19-3 19.1.1 Pin functions in EPROM mode ................................................................................. 19-3 19.1.2 Read/Program from and to built-in PROM ............................................................. 19-4 19.1.3 Programming algorithm to built-in PROM ............................................................... 19-8 19.1.4 Electrical characteristics of the programming algorithm ....................................... 19-9 19.2 Usage precaution ............................................................................................................ 19-10 CHAPTER 20. EXTERNAL ROM VERSION 20.1 20.2 20.3 20.4 Performance overview ...................................................................................................... 20-3 Pin configuration ............................................................................................................... 20-4 Pin description ................................................................................................................... 20-5 Block description ............................................................................................................... 20-7 7733 Group User's Manual vii Table of contents 20.5 Memory allocation ............................................................................................................. 20-8 20.6 Processor modes ............................................................................................................. 20-11 20.7 Timer A ............................................................................................................................... 20-12 20.7.1 Overview .................................................................................................................... 20-12 20.7.2 Pulse output port mode ...........................................................................................20-13 20.8 Reset ................................................................................................................................... 20-26 20.9 Electrical characteristics ................................................................................................ 20-29 20.10 Low voltage version ...................................................................................................... 20-30 20.10.1 Performance overview ............................................................................................ 20-30 20.10.2 Pin configuration ..................................................................................................... 20-31 20.10.3 Functional description ............................................................................................ 20-32 20.10.4 Electrical characteristics ........................................................................................20-32 APPENDIX Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix viii 1. 2. 3. 4. 5. 6. 7. 8. 9. Memory allocation of 7733 Group ................................................................... 21-2 Memory allocation in SFR area ........................................................................ 21-6 Control registers ................................................................................................21-10 Package outlines ............................................................................................... 21-38 Hexadecimal instruction code table ............................................................. 21-41 Machine instructions ........................................................................................21-44 Examples of handling unused pins ............................................................. 21-58 Countermeasure examples against noise ................................................... 21-61 Q & A ................................................................................................................... 21-71 7733 Group User's Manual Table of contents PART 2 7735 Group CHAPTER 1. OVERVIEW 1.1 Performance overview........................................................................................................... 1-2 1.2 Pin configuration.................................................................................................................... 1-3 1.3 Pin description ....................................................................................................................... 1-4 1.3.1 Examples of handling unused pins .............................................................................. 1-6 1.4 Block diagram ..................................................................................................... 1-11 in part 1 CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) 2.1 2.2 2.3 2.4 2.5 Central processing unit ...................................................................................... 2-2 in part 1 Bus interface unit .................................................................................................................. 2-2 Accessible area ...................................................................................................................... 2-5 Memory allocation.............................................................................................. 2-18 in part 1 Processor modes ................................................................................................................... 2-6 ____ ____ 2.5.4 Relationship between access addresses and chip select signals CS0 to CS4 .......... 2-9 CHAPTER 3. PROGRAMMABLE I/O PORTS 3.1 3.2 3.3 3.4 Programmable I/O ports ..................................................................................... 3-2 in part 1 Port peripheral circuits ......................................................................................................... 3-2 Pull-up function .................................................................................................... 3-8 in part 1 Internal peripheral devices' I/O functions (Ports P42 and P5 to P8) ..... 3-10 in part 1 CHAPTER 4. INTERRUPTS 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Overview ................................................................................................................... 4-2 in part 1 Interrupt sources..................................................................................................... 4-4 in part 1 Interrupt control ...................................................................................................... 4-6 in part 1 Interrupt priority level .......................................................................................... 4-10 in part 1 Interrupt priority level detection circuit ..........................................................4-11 in part 1 Interrupt priority level detection time .............................................................. 4-13 in part 1 How interrupts are processed (from acceptance of interrupt request until execution of interrupt routine) .......................................................................... 4-14 in part 1 4.8 Return from interrupt routine ............................................................................. 4-17 in part 1 4.9 Multiple interrupts ................................................................................................. 4-17 in part 1 ____ 4.10 External interrupts (INTi interrupt) .................................................................. 4-19 in part 1 4.11 Precautions for interrupts................................................................................. 4-23 in part 1 CHAPTER 5. KEY INPUT INTERRUPT FUNCTION 5.1 Overview .................................................................................................................5-2 in part 1 5.2 Block description ................................................................................................. 5-3 in part 1 5.3 Initial setting example for related registers .................................................. 5-7 in part 1 7735 Group User's Manual ix Table of contents CHAPTER 6. TIMER A 6.1 6.2 6.3 6.4 6.5 6.6 Overview .................................................................................................................6-2 in part Block description ................................................................................................. 6-3 in part Timer mode (Bits 1 and 0 of timer Ai mode register = "00 2") ................. 6-9 in part Event counter mode (Bits 1 and 0 of timer Ai mode register = "012") ............................ 6-19 in part One-shot pulse mode (Bits 1 and 0 of timer Ai mode register = "102 ") ......................... 6-32 in part Pulse width modulation (PWM) mode (Bits 1 and 0 of timer Ai mode register = "11 2") ................................................................................................... 6-41 in part 1 1 1 1 1 1 CHAPTER 7. TIMER B 7.1 7.2 7.3 7.4 7.5 Overview .................................................................................................................7-2 Block description ................................................................................................. 7-3 Timer mode (Bits 1 and 0 of timer Bi mode register = "00 2") ............... 7-10 Event counter mode (Bits 1 and 0 of timer Bi mode register = "012") 7-17 Pulse period/Pulse width measurement mode (Bits 1 and 0 of timer Bi mode register = "10 2") ..................................................................................... 7-25 7.6 Clock timer .......................................................................................................... 7-34 in in in in part part part part 1 1 1 1 in part 1 in part 1 CHAPTER 8. SERIAL I/O 8.1 8.2 8.3 8.4 Overview .................................................................................................................8-2 Block description ................................................................................................. 8-4 Clock synchronous serial I/O mode .............................................................. 8-21 Clock asynchronous serial I/O (UART) mode.............................................. 8-44 in in in in part part part part 1 1 1 1 in in in in in in in in in part part part part part part part part part 1 1 1 1 1 1 1 1 1 CHAPTER 9. A-D CONVERTER 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Overview .................................................................................................................9-2 Block description ................................................................................................. 9-3 A-D conversion method .................................................................................... 9-11 Absolute accuracy and Differential non-linearity error ............................. 9-14 One-shot mode ................................................................................................... 9-17 Repeat mode ....................................................................................................... 9-20 Single sweep mode ........................................................................................... 9-23 Repeat sweep mode .......................................................................................... 9-27 Precautions for A-D converter ........................................................................ 9-31 CHAPTER 10. WATCHDOG TIMER 10.1 Block description ................................................................................................ 10-2 in part 1 10.2 Operation description ....................................................................................................... 10-2 10.3 Precautions for watchdog timer .................................................................... 10-10 in part 1 CHAPTER 11. STOP AND WAIT MODES 11.1 11.2 11.3 11.4 x Overview ............................................................................................................ 11-2 in part 1 Clock generating circuit ................................................................................................... 11-2 Stop mode ........................................................................................................................... 11-3 Wait mode ............................................................................................................................ 11-6 7735 Group User's Manual Table of contents CHAPTER 12. CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices ...................................................... 12-3 ____ ____ 12.1.1 External bus (A0/D0 to A 15/D15, A16 and A17) and chip select signals (CS0 to CS4) .................... 12-6 12.1.2 External data bus width selection signal (Pin BYTE's ____ level) ................................ 12-8 ____ ____ 12.1.3 Read enable signal (RDE) and Write enable signals (WEL, WEH) ................... 12-8 12.1.4 Address latch enable signal (ALE) ____ ...........................................................................12-8 _____ 12.1.5 Signals related to ready function _____ (RDY, RSMP) ................................................... 12-8 _____ 12.1.6 Signals related to hold function (HOLD, HLDA) .................................................... 12-8 12.1.7 Clock 1 ....................................................................................................................... 12-8 12.1.8 Operation of bus interface unit (BIU) ................................................................... 12-12 12.2 Software wait .................................................................................................................... 12-16 12.3 Ready function ................................................................................................................. 12-19 12.3.1 Operation in ready state ..........................................................................................12-20 12.4 Hold function .................................................................................................................... 12-23 12.4.1 Operation in hold state ............................................................................................ 12-24 CHAPTER 13. RESET 13.1 Hardware reset ................................................................................................................... 13-2 13.2 Software reset................................................................................................. 13-12 in part 1 CHAPTER 14. CLOCK GENERATING CIRCUIT 14.1 Overview ............................................................................................................ 14-2 in part 1 14.2 Oscillation circuit example ............................................................................ 14-3 in part 1 14.3 Clock control ...................................................................................................................... 14-2 CHAPTER 15. ELECTRICAL CHARACTERISTICS 15.1 Absolute maximum ratings ........................................................................... 15-2 in part 1 15.2 Recommended operating conditions .......................................................... 15-3 in part 1 15.3 Electrical characteristics ............................................................................... 15-4 in part 1 15.4 A-D converter characteristics ....................................................................... 15-5 in part 1 15.5 Internal peripheral devices ............................................................................ 15-6 in part 1 15.6 Ready and Hold ................................................................................................................. 15-3 15.7 Single-chip mode ........................................................................................... 15-13 in part 1 15.8 Memory expansion mode and microprocessor mode : with no wait ................... 15-5 15.9 Memory expansion mode and microprocessor mode : with wait 1 ..................... 15-7 15.10 Memory expansion mode and microprocessor mode : with wait 0 ................... 15-9 _ 15.11 Testing circuit for ports P0 to P8, 1 , and E ...................................... 15-21 in part 1 CHAPTER 16. STANDARD CHARACTERISTICS 16.1 Standard characteristics ................................................................................... 16-2 in part 1 7735 Group User's Manual xi Table of contents CHAPTER 17. APPLICATIONS 17.1 Memory expansion ............................................................................................................. 17-2 17.1.1 Memory expansion model .......................................................................................... 17-2 17.1.2 Calculation ways for timing ....................................................................................... 17-4 17.1.3 Points in memory expansion ..................................................................................... 17-7 17.1.4 Memory expansion example ................................................................................... 17-19 17.1.5 I/O expansion example ............................................................................................ 17-21 17.2 Serial I/O .......................................................................................................... 17-28 in part 1 17.3 Watchdog timer .............................................................................................. 17-41 in part 1 17.4 Power saving .................................................................................................................... 17-22 17.5 Timer B ............................................................................................................. 17-54 in part 1 CHAPTER 18. LOW VOLTAGE VERSION 18.1 Performance overview ...................................................................................................... 18-2 18.2 Pin configuration ............................................................................................................... 18-3 18.3 Functional description ...................................................................................................... 18-4 18.4 Electrical characteristics .................................................................................................. 18-5 18.4.6 Ready and Hold .......................................................................................................... 18-5 18.4.8 Memory expansion mode and microprocessor mode : with no wait .................. 18-7 18.4.9 Memory expansion mode and microprocessor mode : with wait 1 .................... 18-9 18.4.10 Memory expansion mode and microprocessor mode : with wait 0 ................ 18-11 18.5 Standard characteristics .............................................................................. 18-27 in part 1 18.6 Application ........................................................................................................................ 18-13 18.6.1 Memory expansion .................................................................................................... 18-13 18.6.2 Memory expansion example ................................................................................... 18-15 18.6.3 Ready generation circuit example ......................................................................... 18-17 CHAPTER 19. BUILT-IN PROM VERSION 19.1 EPROM mode ..................................................................................................................... 19-2 19.2 Usage precaution ........................................................................................... 19-10 in part 1 CHAPTER 20. EXTERNAL ROM VERSION 20.1 Performance overview ...................................................................................................... 20-3 20.2 Pin configuration ............................................................................................................... 20-4 20.3 Pin description ................................................................................................................... 20-5 20.4 Block description ............................................................................................................... 20-7 20.5 Memory allocation ............................................................................................................. 20-8 20.6 Processor modes ............................................................................................................. 20-11 20.7 Timer A ............................................................................................................................... 20-12 20.8 Reset ................................................................................................................................... 20-12 20.9 Electrical characteristics ................................................................................................ 20-15 20.10 Low voltage version ...................................................................................................... 20-16 20.10.1 Performance overview ............................................................................................ 20-16 20.10.2 Pin configuration ..................................................................................................... 20-17 20.10.3 Functional description ............................................................................................ 20-18 20.10.4 Electrical characteristics ........................................................................................20-18 xii 7735 Group User's Manual Table of contents APPENDIX Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix 1. 2. 3. 4. 5. 6. 7. 8. 9. Memory allocation of 7735 Group .................................................................. 21-3 Memory allocation in SFR area ....................................................................... 21-7 Control registers .................................................................................................. 21-9 Package outlines ............................................................................. 21-38 in part 1 Hexadecimal instruction code table ............................................ 21-41 in part 1 Machine instructions ...................................................................... 21-44 in part 1 Examples of handling unused pins ............................................................. 21-11 Countermeasure examples against noise .................................. 21-61 in part 1 Q & A ................................................................................................. 21-71 in part 1 7735 Group User's Manual xiii Table of contents PART 3 7736 Group CHAPTER 1. OVERVIEW 1.1 Performance overview ........................................................................................................... 1-2 1.2 Pin configuration .................................................................................................................... 1-3 1.3 Pin description ....................................................................................................................... 1-4 1.3.1 Examples of handling unused pins .............................................................................. 1-8 1.4 Block diagram ....................................................................................................................... 1-13 CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit ........................................................................................ 2-2 in part 1 2.2 Bus interface unit External bus mode A ........................................................................................... 2-10 in part 1 External bus mode B ............................................................................................. 2-2 in part 2 2.3 Accessible area External bus mode A ........................................................................................... 2-16 in part 1 External bus mode B ............................................................................................. 2-5 in part 2 2.4 Memory allocation................................................................................................ 2-18 in part 1 2.5 Processor modes ................................................................................................................... 2-2 CHAPTER 3. PROGRAMMABLE I/O PORTS 3.1 Programmable I/O ports and Output-only ports ............................................................ 3-2 3.1.1 Port Pi direction register ............................................................................................... 3-3 3.1.2 Port Pi register ............................................................................................................... 3-4 3.2 Port peripheral circuits ........................................................................................................ 3-6 3.3 Pull-up function ..................................................................................................................... 3-8 ___ ___ 3.3.1 Pull-up function for ports P104 to P10 7____ (KI0 to____ KI 3) ................................................ 3-8 3.3.2 Pull-up function for ports P62 to P6 4 (INT 0 to INT 2) ................................................ 3-8 3.4 Internal peripheral devices' I/O functions (Ports P42 , P5 to P8, P90 to P93 and P104 to P107) ..... 3-10 CHAPTER 4. INTERRUPTS 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Overview ................................................................................................................... 4-2 in part 1 Interrupt sources ..................................................................................................... 4-4 in part 1 Interrupt control ...................................................................................................... 4-6 in part 1 Interrupt priority level .......................................................................................... 4-10 in part 1 Interrupt priority level detection circuit ..........................................................4-11 in part 1 Interrupt priority level detection time .............................................................. 4-13 in part 1 How interrupts are processed (from acceptance of interrupt request until execution of interrupt routine) ................................................................. 4-14 in part 1 4.8 Return from interrupt routine ............................................................................. 4-17 in part 1 4.9 Multiple interrupts ................................................................................................. 4-17 in part 1 ____ 4.10 External interrupts (INTi interrupt) .................................................................. 4-19 in part 1 4.11 Precautions for interrupts ................................................................................. 4-23 in part 1 xiv 7736 Group User's Manual Table of contents CHAPTER 5. KEY INPUT INTERRUPT FUNCTION 5.1 Overview ................................................................................................................................. 5-2 5.2 Block description .................................................................................................................. 5-3 ___ ___ ____ 5.2.1 Pins KI 0 to KI 3 and P64/INT 2 ............................................................................................................ 5-3 5.2.2 Port function control register ........................................................................................ 5-4 5.2.3 Interrupt function ............................................................................................................ 5-6 5.3 Initial setting example for related registers ................................................................... 5-7 CHAPTER 6. TIMER A 6.1 6.2 6.3 6.4 6.5 6.6 Overview .................................................................................................................6-2 in part Block description ................................................................................................. 6-3 in part Timer mode (Bits 1 and 0 of timer Ai mode register = "00 2") ................. 6-9 in part Event counter mode (Bits 1 and 0 of timer Ai mode register = "012 ") .............................. 6-19 in part One-shot pulse mode (Bits 1 and 0 of timer Ai mode register = "102 ") ........................... 6-32 in part Pulse width modulation (PWM) mode (Bits 1 and 0 of timer Ai mode register = "11 2") ................................................................................................... 6-41 in part 1 1 1 1 1 1 CHAPTER 7. TIMER B 7.1 7.2 7.3 7.4 7.5 Overview .................................................................................................................7-2 Block description ................................................................................................. 7-3 Timer mode (Bits 1 and 0 of timer Bi mode register = "00 2") ............... 7-10 Event counter mode (Bits 1 and 0 of timer Bi mode register = "012 ") ............................ 7-17 Pulse period/Pulse width measurement mode (Bits 1 and 0 of timer Bi mode register = "10 2") ..................................................................................... 7-25 7.6 Clock timer .......................................................................................................... 7-34 in in in in part part part part 1 1 1 1 in part 1 in part 1 CHAPTER 8. SERIAL I/O 8.1 Overview ................................................................................................................... 8-2 in part 1 8.2 Block description .................................................................................................................. 8-2 8.2.9 Port P8 direction register ............................................................................................. 8-3 8.3 Clock synchronous serial I/O mode ................................................................................. 8-4 8.4 Clock asynchronous serial I/O (UART) mode................................................................. 8-5 CHAPTER 9. A-D CONVERTER 9.1 Overview ................................................................................................................... 9-2 in part 1 9.2 Block description ................................................................................................................... 9-2 9.2.5 Port P7 direction register .............................................................................................. 9-3 9.3 A-D conversion method ....................................................................................... 9-11 in part 1 9.4 Absolute accuracy and Differential non-linearity error ............................... 9-14 in part 1 9.5 One-shot mode ...................................................................................................... 9-17 in part 1 9.6 Repeat mode .......................................................................................................... 9-20 in part 1 9.7 Single sweep mode .............................................................................................. 9-23 in part 1 9.8 Repeat sweep mode ............................................................................................. 9-27 in part 1 9.9 Precautions for A-D converter ........................................................................... 9-31 in part 1 7736 Group User's Manual xv Table of contents CHAPTER 10. WATCHDOG TIMER 10.1 Block description ................................................................................................ 10-2 in part 1 10.2 Operation description ....................................................................................................... 10-2 10.3 Precautions for watchdog timer .................................................................... 10-10 in part 1 CHAPTER 11. STOP AND WAIT MODES 11.1 Overview External bus modes A .......................................................................................... 11-2 in part 1 External bus modes B .......................................................................................... 11-2 in part 2 11.2 Clock generating circuit External bus mode A ............................................................................................ 11-3 in part 1 External bus mode B ............................................................................................ 11-2 in part 2 11.3 Stop mode External bus mode A ............................................................................................ 11-6 in part 1 External bus mode B ............................................................................................ 11-3 in part 2 11.4 Wait mode External bus mode A .......................................................................................... 11-13 in part 1 External bus mode B ............................................................................................ 11-6 in part 2 CHAPTER 12. CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices External bus mode A ............................................................................................ 12-2 in part 1 External bus mode B ............................................................................................ 12-3 in part 2 12.2 Software wait External bus mode A .......................................................................................... 12-13 in part 1 External bus mode B .......................................................................................... 12-16 in part 2 12.3 Ready function External bus mode A .......................................................................................... 12-16 in part 1 External bus mode B .......................................................................................... 12-19 in part 2 12.4 Hold function External bus mode A .......................................................................................... 12-19 in part 1 External bus mode B .......................................................................................... 12-23 in part 2 CHAPTER 13. RESET 13.1 Hardware reset ................................................................................................................... 13-2 13.2 Software reset .................................................................................................... 13-12 in part 1 CHAPTER 14. CLOCK GENERATING CIRCUIT 14.1 Overview ............................................................................................................... 14-2 in part 1 14.2 Oscillation circuit example ............................................................................... 14-3 in part 1 14.3 Clock control ...................................................................................................................... 14-2 xvi 7736 Group User's Manual Table of contents CHAPTER 15. ELECTRICAL CHARACTERISTICS 15.1 Absolute maximum ratings ............................................................................................ 15-2 15.2 Recommended operating conditions ............................................................................ 15-3 15.3 Electrical characteristics ................................................................................................. 15-4 15.4 A-D converter characteristics ....................................................................... 15-5 in part 1 15.5 Internal peripheral devices ............................................................................ 15-6 in part 1 15.6 Ready and Hold External bus mode A ........................................................................................ 15-11 in part 1 External bus mode B .......................................................................................... 15-3 in part 2 15.7 Single-chip mode .............................................................................................................. 15-6 15.8 Memory expansion mode and Microprocessor mode : with no wait External bus mode A ........................................................................................15-15 in part 1 External bus mode B .......................................................................................... 15-5 in part 2 15.9 Memory expansion mode and Microprocessor mode : with wait 1 External bus mode A ........................................................................................15-17 in part 1 External bus mode B .......................................................................................... 15-7 in part 2 15.10 Memory expansion mode and Microprocessor mode : with wait 0 External bus mode A ........................................................................................15-19 in part 1 External bus mode B ........................................................................................... 15-9 in part 2 _ 15.11 Measuring circuit for ports P0 to P10 and pins 1 and E .................................... 15-8 CHAPTER 16. STANDARD CHARACTERISTICS 16.1 Standard characteristics .................................................................................................. 16-3 16.1.1 Programmable I/O port (CMOS output) standard characteristics: P0 to P3, P4 0 to P4 3 , P5 to P9, and P10 4 to P10 7 ............................................................... 16-3 16.1.2 Programmable I/O port (CMOS output) standard characteristics: P4 4 to P47 and P100 to P10 3 ................................................................................................................................ 16-4 16.1.3 Icc-f(X IN) standard characteristics ............................................................. 16-4 in part 1 16.1.4 A-D converter standard characteristics ......................................................16-5 in part 1 CHAPTER 17. APPLICATIONS 17.1 Memory expansion External bus mode A ........................................................................................... 17-2 in part 1 External bus mode B ........................................................................................... 17-2 in part 2 17.2 Serial I/O ............................................................................................................ 17-28 in part 1 17.3 Watchdog timer ................................................................................................ 17-41 in part 1 17.4 Power saving ...................................................................................................................... 17-3 17.4.1 Power saving example with stop mode used ......................................................... 17-3 17.4.2 Power saving example with wait mode used .......................................................... 17-8 17.5 Timer B............................................................................................................... 17-54 in part 1 CHAPTER 18. LOW VOLTAGE VERSION 18.1 Performance overview ..................................................................................................... 18-3 18.2 Pin configuration .............................................................................................................. 18-4 18.3 Functional description ..................................................................................................... 18-5 7736 Group User's Manual xvii Table of contents 18.4 Electrical characteristics ................................................................................................. 18-6 18.4.1 Absolute maximum ratings ....................................................................................... 18-7 18.4.2 Recommended operating conditions ....................................................................... 18-8 18.4.3 Electrical characteristics ........................................................................................... 18-9 18.4.4 A-D converter characteristics ................................................................... 18-10 in part 1 18.4.5 Internal peripheral devices ....................................................................... 18-11 in part 1 18.4.6 Ready and Hold External bus mode A ................................................................................ 18-16 in part 1 External bus mode B .................................................................................. 18-5 in part 2 18.4.7 Single-chip mode ...................................................................................................... 18-11 18.4.8 Memory expansion mode and microprocessor mode : with no wait External bus mode A ................................................................................ 18-20 in part 1 External bus mode B .................................................................................. 18-7 in part 2 18.4.9 Memory expansion mode and microprocessor mode : with wait 1 External bus mode A ................................................................................ 18-22 in part 1 External bus mode B .................................................................................. 18-9 in part 2 18.4.10 Memory expansion mode and microprocessor mode : with wait 0 External bus mode A ................................................................................ 18-24 in part 1 External bus mode B ................................................................................ 18-11 in part 2 _ 18.4.11 Measuring circuit for ports P0 to P10 and pins 1 and E .................................. 18-13 18.5 Standard characteristics ............................................................................................... 18-14 18.5.1 Programmable I/O port (CMOS output) standard characteristics : Ports P0 to P3, P4 0 to P4 3 , P5 to P9 and P10 4 to P10 7 .......................................................................... 18-14 18.5.2 Programmable I/O port (CMOS output) standard characteristics : Ports P44 to P47 and P5 0 to P5 3 ................................................................................................................................ 18-15 18.6 Applications ..................................................................................................................... 18-16 External bus mode A .......................................................................................... 18-32 in part 1 External bus mode B .......................................................................................... 18-13 in part 2 CHAPTER 19. BUILT-IN PROM VERSION 19.1 EPROM mode ...................................................................................................................... 19-2 19.2 Usage precaution .............................................................................................. 19-10 in part 1 APPENDIX Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix 1. 2. 3. 4. 5. 6. 7. 8. 9. Memory allocation of 7736 Group ................................................................... 20-3 Memory allocation in SFR area ........................................................................ 20-6 Control registers .................................................................................................. 20-8 Package outlines ............................................................................................... 20-12 Hexadecimal instruction code table ............................................. 21-41 in part 1 Machine instructions ........................................................................ 21-44 in part 1 Examples of handling unused pins .............................................................. 20-14 Countermeasure examples against noise ................................... 21-61 in part 1 Q & A ................................................................................................... 21-71 in part 1 GLOSSARY xviii 7736 Group User's Manual PART 1 7733 Group CHAPTER 1 OVERVIEW CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) CHAPTER 3 PROGRAMMABLE I/O PORTS CHAPTER 4 INTERRUPTS CHAPTER 5 KEY INPUT INTERRUPT FUNCTION CHAPTER 6 TIMER A CHAPTER 7 TIMER B CHAPTER 8 SERIAL I/O CHAPTER 9 A-D CONVERTER CHAPTER 10 WATCHDOG TIMER CHAPTER 11 STOP AND WAIT MODES CHAPTER 12 CONNECTING EXTERNAL DEVICES CHAPTER 13 RESET CHAPTER 14 CLOCK GENERATING CIRCUIT CHAPTER 15 ELECTRICAL CHARACTERISTICS CHAPTER 16 STANDARD CHARACTERISTICS CHAPTER 17 APPLICATIONS CHAPTER 18 LOW VOLTAGE VERSION CHAPTER 19 BUILT-IN PROM VERSION CHAPTER 20 EXTERNAL ROM VERSION APPENDIX PART 1 7733 Group The 7733 Group is described in part 1. For the 7735 Group, refer to part "2. 7735 Group." In part 2, the differences between the 7735 Group and the 7733 Group are mainly described. For the 7736 Group, refer to part "3. 7736 Group." In part 3, the differences between the 7736 Group and the 7733 Group are mainly described. 2 7733 Group User's Manual CHAPTER 1 OVERVIEW 1.1 1.2 1.3 1.4 Performance overview Pin configuration Pin description Block diagram OVERVIEW The 7733 Group is a 16-bit single-chip microcomputer designed with high-performance CMOS silicon gate technology. It is housed in an 80-pin plastic molded flat package. This single-chip microcomputer has a large 16-Mbyte accessible space, three instruction queue buffers, and two data buffers for high-speed instruction execution. The CPU is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. This microcomputer is suitable for communication and office equipment controllers. About details concerning each microcomputer's development state of the 7733 Group, inquire "CONTACT ADDRESSES FOR FURTHER INFORMATION" described last. Functional codes of the 7733 Group are described below. M 3 77 33 M H B XXX FP Represents Mitsubishi integrated prefix Represents uses and operating temperature range Represents circuit type and family name Represents group name 2-digit numerals (Running number) Represents memory type M:Mask ROM E:EPROM S:External ROM Represents memory size 1-digit alphanumeric Represents electrical characteristics Represents ROM's contents 3-digit numerals Package type FP: Molded plastic flat package GP: Molded plastic flat package HP: Molded fine-pitch plastic flat package SP: Molded plastic SDIP FS: Ceramic flat package 1-2 7733 Group User's Manual OVERVIEW 1.1 Performance overview 1.1 Performance overview Table 1.1.1 lists the M37733MHBXXXFP's performance overview. Table 1.1.1 M37733MHBXXXFP's performance overview Items Number of basic instructions The minimum instruction execution time Performance 103 160 ns (When f(XIN) = 25 MHz and the main clock is the system clock) Main-clock frequency f(XIN) 25 MHz (Max.) (Note 3) Sub-clock frequency f(XCIN) 32.768 kHz (Typ.) Memory size ROM 124 Kbytes RAM 3968 bytes Programmable I/O ports Ports P0-P2, P4-P8 8 bits 8 Port P3 4 bits 1 Multifunction timers Timers A0-A4 16 bits 5 Timers B0-B2 16 bits 3 Serial I/O UART0-UART2 (UART or clock synchronous serial I/O) 3 A-D converter (10-bit successive approximation method) 1 (8 channels) Watchdog timer 12 bits 1 Interrupts 3 external, 16 internal (By software, one of interrupt priority levels 0 to 7 can be set for each interrupt) Clock generating circuits Main-clock oscillation Built-in (externally connected to a ceramic resonator or a circuit quartz-crystal oscillator.) Sub-clock oscillation Built-in (externally connected to a quartz-crystal oscillator) circuit Power source voltage 5 V 10% (When the main clock is the system clock) 2.7 V to 5.5 V (When the sub clock is the system clock) Power consumption in single-chip mode 47.5 mW (When f(X IN) = 25 MHz, V CC = 5 V, and the main clock is the system clock, Typ.) 250 W (When f(XCIN) = 32 kHz, VCC = 5 V, the sub clock is the system clock, and the main clock is stopped, Typ.) Port input/output Input/Output withstand 5 V characteristics voltage Output current 5 mA Memory expansion Possible (Maximum of 16 Mbytes) Operating temperature range -20 C to +85 C Device structure High-performance CMOS silicon gate process Package 80-pin plastic molded QFP Notes 1: All of the 7733 Group microcomputers are the same except for package type, memory type, memory size, and electrical characteristics. 2: For the low voltage version, refer to chapter "18. LOW VOLTAGE VERSION." 3: When the main clock division selection bit = "1," the maximum value of f(X IN) = 12.5 MHz. 7733 Group User's Manual 1-3 OVERVIEW 1.2 Pin configuration 1.2 Pin configuration P71/AN1 P72/AN2/CTS2 P73/AN3/CLK2 P74/AN4/RXD2 P75/AN5/ADTRG/TXD2 P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RXD0/CLKS0 P83/TXD0 Figure 1.2.1 shows the M37733MHBXXXFP pin configuration. Note: For the low voltage version, refer to chapter "18. LOW VOLTAGE VERSION." 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 64 2 63 3 62 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 M37733MHBXXXFP P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 P42/ f 1 P41/RDY 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 23 42 24 41 P40/HOLD BYTE CNVSS RESET XIN XOUT E VSS P33/HLDA P32/ALE P31/BHE P30/R/W P27/A23/D7 P26/A22/D6 P25/A21/D5 P24/A20/D4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Outline 80P6N-A Fig. 1.2.1 M37733MHBXXXFP pin configuration (Top view) 1-4 61 7733 Group User's Manual P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 P22/A18/D2 P23/A19/D3 OVERVIEW 1.3 Pin description 1.3 Pin description Tables 1.3.1-1.3.3 list the pin description. Note that the pin description of the built-in PROM version in the EPROM mode is described in section "19.1 EPROM mode." Table 1.3.1 Pin description (1) Pin VCC , VSS Name Power source input CNVSS CNV SS Input RESET Reset input Input XIN Clock input Input XOUT Clock output Output Enable output Output ______ _ E Input/Output Functions To pin V CC , apply 5 V10% (Note) (When the main clock is the system clock) or 2.7 V to 5.5 V (When the sub clock is the system clock). To pin VSS, apply 0 V. This pin switches the processor mode. [Single-chip Mode] [Memory Expansion Mode] Connect to pin V SS. [Microprocessor Mode] Connect to pin V CC. The microcomputer is reset when "L" level is input to this pin. Pins X IN and X OUT are the I/O pins of the clock generating circuit, respectively. Connect these pins via a ceramic resonator or a quartz-crystal oscillator. When an external clock is used, the clock should be input to pin X IN , and pin X OUT should be left open. _ _ This pin outputs signal E. When E's level is "L," the microcomputer reads data and instruction codes or _ writes data. Also, output of signal E can be stopped BYTE External data bus width selection input AV CC Analog power source input Input AVSS VREF Reference voltage input Input by software. [Single-chip Mode] Connect to pin V SS. [Memory Expansion Mode] [Microprocessor Mode] Input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. A 16-bit width is selected when the level is "L," and an 8-bit width is selected when the level is "H." Power source input for the A-D converter. Connect to pin V CC. Power source input for the A-D converter. Connect to pin V SS . This is the reference voltage input pin for the A-D converter. Note: In the low voltage version, it is 2.7 V to 5.5 V. 7733 Group User's Manual 1-5 OVERVIEW 1.3 Pin description Table 1.3.2 Pin description (2) Pin Name P0 0-P07 I/O port P0 A0-A 7 P1 0-P17 Input/Output Functions I/O [Single-chip Mode] P0 is an 8-bit CMOS I/O port and has an I/O direction register. Each pin can be programmed for input or output. [Memory Expansion Mode] [Microprocessor Mode] Address's low-order 8 bits (A0-A7 ) are output. [Single-chip Mode] P1 is an 8-bit I/O port with the same function as port P0. [Memory Expansion Mode] [Microprocessor Mode] When the external data bus width = 8 bits (Pin BYTE is at "H" level) Address's middle-order 8 bits (A8-A15) are output. When the external data bus width = 16 bits (Pin BYTE is at "L" level) Input/Output of data (D8-D15) and output of address's middle-order 8 bits (A8-A15) are performed with the time sharing method. [Single-chip Mode] P2 is an 8-bit I/O port with the same function as port P0. [Memory Expansion Mode] [Microprocessor Mode] Input/Output of data (D 0-D 7) and output of address's high-order 8 bits (A16-A23) are performed with the time sharing method. [Single-chip Mode] P3 is a 4-bit I/O port with the same function as port P0. [Memory Expansion Mode] [Microprocessor Mode] __ ____ These pins respectively output signals R/W, BHE, ALE, _____ and HLDA . __ Signal R/ W This signal indicates the data bus state. When this signal level is "H," a data bus is in the read state. When this signal level is "L," a data bus is in the write state. ____ Signal BHE This signal's level is "L" when the microcomputer accesses an odd address. Signal ALE This signal is used to separate the multiplexed signal which consists of an address and data to the address and the data. _____ Signal HLDA This signal informs the external whether this microcomputer enters the Hold state or not. _____ In Hold state, pin HLDA outputs "L" level. Output I/O port P1 I/O I/O port P2 I/O I/O port P3 I/O A8/D8- A15/D15 P2 0-P27 A16/D0- A23/D7 P3 0-P33 __ R/W, ____ BHE , ALE, _____ HLDA 1-6 Output 7733 Group User's Manual OVERVIEW 1.3 Pin description Table 1.3.3 Pin description (3) Pin P4 0-P4 7 Name I/O port P4 Input/Output Functions I/O [Single-chip Mode] P4 is an 8-bit I/O port with the same function as port P0. P42 can also be programmed as the clock 1 output pin. (Refer to chapter "14. CLOCK GENERATING CIRCUIT.") [Memory Expansion Mode] _____ ____ P4 0 functions as pin HOLD , and P4 1 as pin RDY. _____ The microcomputer is in Hold state while pin HOLD 's ____ input level is "L" and is in Ready state while pin RDY's input level is "L." P42 -P47 function as I/O ports with the same function as port P0. P42 can also be programmed as the clock 1 output pin. (Refer to chapter "14. CLOCK GENERATING CIRCUIT.") [Microprocessor Mode] _____ HOLD , Input ____ RDY , Input P4 2-P4 7 I/O _____ HOLD , Input ____ RDY , Input Output 1, P4 3-P4 7 P5 0-P5 7 I/O I/O port P5 I/O _____ _____ P6 0-P6 7 I/O port P6 I/O P7 0-P7 7 I/O port P7 I/O P8 0-P8 7 I/O port P8 I/O ____ P4 0 functions as pin HOLD, P4 1 as pin RDY, and P4 2 as the clock 1 output pin. (Refer to "[Memory Expansion Mode].") P4 3-P4 7 function as I/O ports with the same function as port P0. P5 is an 8-bit I/O port with the same function as port P0 and can be programmed as I/O pins for timers A0- A3 and input pins ( KI0- KI 3) for the key input interrupt. P6 is an 8-bit I/O port with the same function as port P0 and can be programmed as I/O pins for timer A4, external interrupt input pins, and input pins for timers B0-B2. P67 also functions as an output pin for the sub clock ( SUB). P7 is an 8-bit I/O port with the same function as port P0 and can be programmed as analog input pins for the A-D converter. P7 6 and P7 7 can be programmed as I/O pins (X COUT, X CIN) for the sub-clock (32 kHz) oscillation circuit. When using P7 6 and P7 7 as pins X COUT and X CIN, connect a quartz-crystal oscillator between them. When inputting an external clock, input the clock from pin X CIN . P7 2 -P7 5 also function as UART2's I/O pins. P8 is an 8-bit I/O port with the same function as port P0 and can be programmed as serial I/O's I/O pins. 7733 Group User's Manual ______ 1-7 OVERVIEW 1.3 Pin description 1.3.1 Examples of handling unused pins The following are examples of handling unused pins. These are, however, just examples. In actual use, make the necessary adaptations and properly evaluate performance according to the user's application. (1) In single-chip mode Table 1.3.4 Examples of handling unused pins in single-chip mode Pins E Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Note 1). Leave this pin open. XOUT (Note 2) AVcc AVss, V REF, BYTE Connect this pin to pin Vcc. Connect these pins to pin Vss. P0-P8 __ Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 2: This is applied when an external clock is input to pin XIN. N When setting ports to input mode N When setting ports to output mode P0-P8 M37733MHBXXXFP M37733MHBXXXFP E XOUT P0-P8 Left open VCC AVcc AVss VREF BYTE Vss Fig. 1.3.1 Examples of handling unused pins in single-chip mode 1-8 7733 Group User's Manual E XOUT Left open Left open Vcc AVcc AVss VREF BYTE Vss OVERVIEW 1.3 Pin description (2) In memory expansion mode Table 1.3.5 Examples of handling unused pins in memory expansion mode Pins Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Notes 1, 2, and 7). Leave this pin open. (Note 5) P4 2-P4 7, P5-P8 ____ BHE (Note 3) ALE (Note 4) _____ HLDA X OUT (Note 6) _____ ____ HOLD , RDY Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. AVcc AVss, V REF Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: This is applied when "H" level is input to pin BYTE. 4: This is applied when "H" level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: this pin functions as an input port from reset until the processor mode is switched to the memory expansion mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: This is applied when an external clock is input to pin XIN . 7: Set pin P4 2 / 1 as pin P4 2 . (Clock 1 output is disabled.) And then, for this pin, do the same handling as that for pins P4 3 to P4 7 and P5 to P8. N When setting ports to input mode P42-P47, P5-P8 M37733MHBXXXFP M37733MHBXXXFP Left open HLDA XOUT When setting ports to output mode P42-P47, P5-P8 BHE ALE N Left open Vcc HOLD RDY AVcc AVss VREF Left open BHE ALE Left open HLDA XOUT Left open Vcc HOLD RDY AVcc AVss VREF Vss Vss Fig. 1.3.2 Examples of handling unused pins in memory expansion mode 7733 Group User's Manual 1-9 OVERVIEW 1.3 Pin description (3) In microprocessor mode Table 1.3.6 Examples of handling unused pins in microprocessor mode Pins Handling example P4 3-P4 7, P5-P8 Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Notes 1 and 2). ____ BHE (Note 3) Leave this pin open. (Note 5) ALE (Note 4) _____ HLDA , 1 XOUT (Note 6) Leave this pin open. _____ ____ HOLD, RDY Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) AVcc Connect this pin to pin Vcc. AVss, VREF Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: This is applied when "H" level is input to pin BYTE. 4: This is applied when "H" level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: this pin functions as an input port from reset until the processor mode is switched to the microprocessor mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: This is applied when an external clock is input to pin XIN. N When setting ports to input mode P43-P47, P5-P8 M37733MHBXXXFP M37733MHBXXXFP Left open HLDA f1 XOUT When setting ports to output mode P43-P47, P5-P8 BHE ALE N Left open Vcc HOLD RDY AVcc AVss VREF BHE ALE Left open HLDA f1 XOUT Left open Vcc HOLD RDY AVcc AVss VREF Vss Fig. 1.3.3 Examples of handling unused pins in microprocessor mode 1-10 Left open 7733 Group User's Manual Vss OVERVIEW 1.4 Block diagram 1.4 Block diagram Figure 1.4.1 shows the M37733MHBXXXFP block diagram. Fig.1.4.1 M37733MHBXXXFP block diagram 7733 Group User's Manual 1-11 OVERVIEW 1.4 Block diagram MEMO 1-12 7733 Group User's Manual CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) 2.1 2.2 2.3 2.4 2.5 Central processing unit Bus interface unit Accessible area Memory allocation Processor modes CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1 Central processing unit The CPU of the 7733 Group has ten registers as shown in Figure 2.1.1. Each of these registers is described below. b15 b8 b0 b7 AH AL b15 b8 b0 b7 BH BL b15 b8 Accumulator B (B) b0 b7 XH XL b15 b8 Index register X (X) b0 b7 YH YL b15 b8 Index register Y (Y) b0 b7 SH b7 Accumulator A (A) SL Stack pointer (S) b0 DT Data bank register (DT) b8 b16 b15 b23 PG b7 PCH b7 b0 Program counter (PC) PCL b0 Program bank register (PG) b15 b8 DPRH DPRL b15 b8 0 b10 0 0 0 0 b0 PSL b9 b8 b7 b6 IPL Direct page register (DPR) b7 PSH b15 b0 b7 N V Processor status register (PS) b5 b4 b3 b2 b1 b0 m Z x D I C Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag Processor interrupt priority level Fig. 2.1.1 CPU registers structure 2-2 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.1 Accumulator (Acc) Accumulators A and B are available. (1) Accumulator A (A) Data processing such as calculation, data transfer, or data input/output is executed mainly through accumulator A. It consists of 16 bits and its low-order 8 bits can also be used separately. The data length flag (m), which is a part of the processor status register, specifies whether accumulator A is used as a 16-bit register or an 8-bit register. When the data length is 8 bits wide, only the low-order 8 bits of accumulator A are used and the contents of the high-order 8 bits is unchanged. (2) Accumulator B (B) Accumulator B has the same function as accumulator A and can be used instead of accumulator A. Note that, except for some instructions, the use of accumulator B requires more instruction bytes and execution cycles than that of accumulator A. Accumulator B consists of 16 bits and is also affected by the data length flag (m) just as for accumulator A. 2.1.2 Index register X (X) Index register X consists of 16 bits and its low-order 8 bits can also be used separately. The index register length flag (x), which is a part of the processor status register, specifies whether index register X is used as a 16-bit register or an 8-bit register. When the index register length is 8 bits wide, only the low-order 8 bits of index register X are used and the contents of the high-order 8 bits is unchanged. In an addressing mode where index register X is used as an index register, the address obtained by adding the contents of index register X to the operand is accessed. In execution of a block transfer instruction (MVP or MVN), the contents of index register X is the low-order 16 bits of the source address and the third byte of the instruction is the high-order 8 bits of the address. Refer to "7700 Family Software Manual" for addressing modes. 2.1.3 Index register Y (Y) Index register Y has the same function as index register X. Index register Y consists of 16 bits and is also affected by the index register length flag (x) just as for index register X. In execution of a block transfer instruction (MVP or MVN), the contents of index register Y is the low-order 16 bits of the destination address and the second byte of the instruction is the high-order 8 bits of the address. 7733 Group User's Manual 2-3 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.4 Stack pointer (S) The stack pointer (S) consists of 16 bits and is used for an interrupt, a subroutine call, or execution of an addressing mode where a stack is used. The contents of S indicates a store address for a register and so on during an interrupt or a subroutine call (stack area). The stack area is set in bank 016. (Refer to section "2.1.6 Program bank register (PG).") When an interrupt request is accepted, the microcomputer stores the contents of the program bank register (PG) into an address indicated by the contents of S and decrements the contents of S by 1. Then the microcomputer stores the contents of the program counter (PC) and the processor status register (PS). After acceptance of an interrupt request, the contents of S becomes [S] - 5. ([S] is the initial address that the stack pointer (S) indicates when an interrupt request is accepted.) (Refer to Figure 2.1.2.) After processing in an interrupt routine is finished, processing for return to the original routine is performed as follows. When the RTI instruction is executed, the contents of registers which were stored in the stack area are restored into the original registers. (The contents are restored PS, PC, and PG in that order.) The contents of S is also returned to the state before acceptance of an interrupt request. During a subroutine call, the same processing as for an interrupt is performed. The contents of PS, however, are not automatically stored. (The contents of PG may not be stored. This depends on the addressing mode.) During an interrupt or a subroutine call, registers other than the above registers are not automatically stored. Therefore, be sure to store necessary registers by software. The contents of S is undefined at reset. Therefore, be sure to initialize S at the start of a program. Furthermore, a stack area changes according to subroutine's nesting or acceptance of multiple interrupts' requests. Therefore, give careful consideration to subroutine's nesting depth not to destroy the necessary data. Refer to "7700 Family Software Manual" for addressing modes. Stack area Address [S] - 5 [S] - 4 Processor status register's low-order byte (PSL) [S] - 3 Processor status register's high-order byte (PSH) [S] - 2 Program counter's low-order byte (PCL) [S] - 1 Program counter's high-order byte (PCH) [S] Program bank register (PG) [S] is the initial address that the stack pointer (S) indicates when an interrupt request is accepted. S's contents is "[S] - 5" after all of the above registers are pushed. Fig. 2.1.2 Stored registers in stack area 2-4 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.5 Program counter (PC) The program counter consists of 16 bits. This counter indicates the low-order 16 bits of a store address, which consists of 24 bits, of an instruction to be executed next, in other words an instruction which is read from an instruction queue buffer. At reset, value "FF16" is set to the high-order byte (PCH) of the program counter and value "FE16" is set to the low-order byte (PCL ) of the counter. And then, immediately after reset, the contents of the reset's vector addresses (addresses FFFE 16 , FFFF 16) are set to the counter. Figure 2.1.3 shows the program counter and the program bank register. (b23) b7 (b16) b0 b15 PG b8 b7 PCH b0 PCL Fig. 2.1.3 Program counter and program bank register 2.1.6 Program bank register (PG) The program bank register consists of 8 bits. (Refer to Figure 2.1.3.) This register indicates the high-order 8 bits of a store address, which consists of 24 bits, of an instruction to be executed next, in other words an instruction which is read from an instruction queue buffer. These 8 bits indicate "bank." The contents of the program bank register is automatically incremented by 1 when a carry occurs in the following cases: *When a certain value is added to the contents of the program counter *When the displacement is added to the program counter by executing a branch instruction and others The contents of the program bank register is automatically decremented by 1 when a borrow occurs in the following case: *When a certain value is subtracted from the contents of the program counter Therefore, when normally programming, it is not necessary to give consideration to bank boundaries. At reset, this register is cleared to "0016." 7733 Group User's Manual 2-5 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.7 Data bank register (DT) The data bank register consists of 8 bits. In an addressing mode where the data bank register is used, the contents of this register is processed as the high-order 8 bits (bank) of an address to be accessed, which consists of 24 bits. When setting a certain value to this register, execute the LDT instruction. At reset, this register is cleared to "0016." Addressing modes where the data bank register is used are listed below: Direct * indirect Direct * indexed X * indirect Direct * indirect * indexed Y Absolute Absolute * bit Absolute * indexed X Absolute * indexed Y Absolute * bit * relative Stack pointer * relative * indirect * indexed Y 2.1.8 Direct page register (DPR) The direct page register consists of 16 bits. The contents of this register specifies a direct page area to bank 016 or an area which extends banks 0 16 and 1 16. The direct page area can be accessed with two bytes (Note) by using the direct page addressing mode. The contents of the direct page register indicates the base address (the lowest address) of a direct page area which is extended to 256 bytes above this address. Values from 000016 to FFFF16 can be set to the direct page register. When a certain value equal to or more than "FF0116" is set to the direct page register, the direct page area is specified to an area which extends banks 016 and 116 . When the contents of low-order 8 bits of the direct page register is cleared to "0016," the number of cycles required to generate the address to be accessed is decremented by 1. Therefore, efficient access is possible. At reset, this register is cleared to "0000 16. " Figure 2.1.4 shows a setting example of direct page areas. Note: For the DIV and MPY instructions, the direct page area is accessed with 3 bytes. When accumulator B is used, for each instruction, the number of instruction bytes is incremented by 1. Addressing modes where the direct page register is used are listed below: Direct Direct * bit Direct * indexed X Direct * indexed Y Direct * indirect Direct * indexed X * indirect Direct * indirect * indexed Y Direct * indirect long Direct * indirect long * indexed Y Direct * bit * relative 2-6 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 016 016 AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AA AA AA Bank 016 When DPR = 000016 FF16 12316 When DPR = 012316 22216 FFFF16 FF1016 1000016 1000F16 When DPR = FF1016 Bank 116 Notes 1: When the low-order 8 bits of DPR = "0016," the number of cycles required to generate the address to be accessed is decremented by 1. 2: When DPR = "FF0116" or more, the direct page area is specified to the area which extends banks 016 and 116. Fig. 2.1.4 Setting example of direct page area 7733 Group User's Manual 2-7 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit 2.1.9 Processor status register (PS) The processor status register consists of 11 bits. Figure 2.1.5 shows the structure of the processor status register. b15 b14 b13 b12 b11 b10 b9 b8 0 0 0 0 0 IPL b7 b6 b5 b4 b3 b2 N V m x D I b1 b0 Z C Processor status register (PS) Note: "0" is always read from bits 11 to 15. Fig. 2.1.5 Structure of processor status register (1) Bit 0: Carry flag (C) This flag retains a carry or borrow which occur in the Arithmetic Logic unit (ALU) during an arithmetic or logic operation. This flag is also affected by a shift or rotate instruction. When the BCC or BCS instruction is executed, the program branches according to this flag's state. When setting this flag to "1," execute the SEC or SEP instruction; when clearing this flag to "0," execute the CLC or CLP instruction. (2) Bit 1: Zero flag (Z) This flag is set to "1" when the result of an arithmetic operation or data transfer is "0" and cleared to "0" when otherwise. When the BNE or BEQ instruction is executed, the program branches according to this flag's state. This flag is ignored for an addition and subtraction instructions (the ADC and the SBC instructions) in the decimal mode. When setting this flag to "1," execute the SEP instruction; when clearing this flag to "0," execute the CLP instruction. (3) Bit 2: Interrupt disable flag (I) This flag disables all maskable interrupts, in other words interrupts other than watchdog timer, the BRK instruction, and zero division interrupts. Interrupts are disabled when this flag is "1." When an interrupt request is accepted, this flag is automatically set to "1" and disables multiple interrupts. When setting this flag to "1," execute the SEI or SEP instruction; when clearing this flag to "0," execute the CLI or CLP instruction. At reset, this flag is set to "1." (4) Bit 3: Decimal mode flag (D) This flag determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic is performed when this flag is "0." When it is "1," decimal arithmetic is performed. At this time, each word is processed as 2- or 4-digit decimal data. (The digit's number is determined by the data length flag (m)). Decimal adjust is automatically performed. (Note that a decimal operation is enabled only in execution of the ADC or SBC instruction.) When setting this flag to "1," execute the SEP instruction; when clearing this flag to "0," execute the CLP instruction. At reset, this flag is cleared to "0." 2-8 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (5) Bit 4: Index register length flag (x) This flag determines whether index register X or index register Y is used as a 16-bit register or an 8-bit register. The register is used as a 16-bit register when this flag is "0" and as an 8-bit register when this flag is "1." When setting this flag to "1," execute the SEP instruction; when clearing this flag to "0," execute the CLP instruction. At reset, this flag is cleared to "0." Note: When data is transferred between registers which are different in bit length, the data is transferred with the bit length of the destination register. But this is not applied to the case where the TXA, TYA, TXB, or TYB instruction is executed. Refer to "7700 Family Software Manual" for details. (6) Bit 5: Data length flag (m) This flag determines whether data is used as 16-bit data or 8-bit data. Data is used as 16-bit data when this flag is "0" and as 8-bit data when this flag is "1." When setting this flag to "1," execute the SEM or SEP instruction; when clearing this flag to "0," execute the CLM or CLP instruction. At reset, this flag is cleared to "0." Note: When data is transferred between registers which are different in bit length, the data is transferred with the data length of the destination register. But this is not applied to the case where the TXA, TYA, TXB, or TYB instruction is executed. Refer to "7700 Family Software Manual" for details. (7) Bit 6: Overflow flag (V) This flag is valid when addition or subtraction is executed for each word which is processed as signed binary data. If the data length flag (m) is "0," the overflow flag is set to "1" when the result of addition or subtraction exceeds the range between -32768 and +32767 and cleared to "0" in the other cases. If the data length flag (m) is "1," the overflow flag is set to "1" when the result of addition or subtraction exceeds the range between -128 and +127 and cleared to "0" in the other cases. Also, the overflow flag is set to "1" when the length of the division result obtained by the DIV instruction is longer than that of a register where the result is to be stored. When the BVC or BVS instruction is executed, the program branches according to this flag's state. This flag is ignored in the decimal mode. When setting this flag to "1," execute the SEP instruction; when clearing this flag to "0," execute the CLV or CLP instruction. (8) Bit 7: Negative flag (N) This flag is set to "1" when the result of an arithmetic operation or data transfer is negative. (Bit 15 of the result is "1" when the data length flag (m) is "0," or bit 7 of the result is "1" when the data length flag (m) is "1.") It is cleared to "0" in the other cases. When the BPL or BMI instruction is executed, the program branches according to this flag's state. This flag is ignored in the decimal mode. When setting this flag to "1," execute the SEP instruction; when clearing this flag to "0," execute the CLP instruction. (9) Bits 8 to 10: Processor interrupt priority level (IPL) These bits can specify one of levels 0 to 7 as the processor interrupt priority level. An interrupt is enabled when its interrupt priority level, which is set in the interrupt control register, is higher than IPL. When the interrupt request is accepted, the contents of IPL is stored into the stack area and the interrupt priority level of the accepted interrupt is set in IPL. No instruction can directly set or clear each of these bits. When changing these bits, store a desired processor interrupt priority level into the stack area. And then, change the contents of the processor status register by executing the PUL or PLP instruction. At reset, the contents of IPL is cleared to "0002." 7733 Group User's Manual 2-9 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit 2.2 Bus interface unit The microcomputer has a bus interface unit (BIU) between the central processing unit (CPU) and memory * I/O unit. The BIU's function and operation are described below. When connecting external devices, refer to chapter "12. CONNECTING EXTERNAL DEVICES," also. 2.2.1 Overview Transfer operation between the CPU and memory * I/O unit is always performed via the BIU. The BIU reads an instruction from the memory before the CPU executes it. When the CPU reads data from the memory * /O unit, the CPU informs the BIU of the address where the data resides. The BIU reads the data from the address and pass it to the CPU. When the CPU writes data to the memory * I/O unit, the CPU informs the BIU of the address where the data resides. The BIU writes the data to the address. In order to realize operations to , the BIU inputs and outputs bus control signals and controls the buses. Figure 2.2.1 shows the buses and bus interface unit (BIU). 2-10 7733 Group User's Manual 7733 Group User's Manual (BIU) (CPU) Internal control signals Internal bus A23 to A0 Internal bus D7 to D0 Internal bus D15 to D8 Internal bus Bus conversion circuit Internal peripheral devices (SFR) Internal memory External bus Control signals A23/D7 to A16/D0 A15/D15 to A8/D8 A7 to A0 Register Functionbus, : Special and external bus are independent of each other. bus, internal 1: CPU NotesSFR 2: For details about signals on the external buses, refer to chapter "12. CONNECTING EXTERNAL DEVICES." Bus interface unit Central processing unit CPU bus M37733MHBXXXFP External devices CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit Fig. 2.2.1 Buses and bus interface unit (BIU) 2-11 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit 2.2.2 Functions of bus interface unit (BIU) The bus interface unit (BIU) consists of four registers shown in Figure 2.2.2. Table 2.2.1 lists each register's function. b23 b0 Program address register PA b7 b0 Q0 Instruction queue buffer Q1 Q2 b23 b0 Data address register DA b15 DBH b0 DBL Data buffer Fig. 2.2.2 Registers' structure of which bus interface unit (BIU) consists Table 2.2.1 Each register's function Name Program address register Instruction queue buffer Data address register Data buffer 2-12 Functions Indicates a store address for an instruction which is next fetched into an instruction queue buffer. Temporarily stores an instruction which was fetched. Indicates an address for data which is next read or written. Temporarily stores data which was read from the memory * I/O unit by the BIU or which is to be written to the memory * I/O unit by the CPU. 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit The CPU and buses operate on the basis of different signals (Note). Between the CPU and buses, therefore, data is passed or received via the BIU. Owing to the BIU's operation, the CPU can operate at high speed without waiting for the access by the low-speed memory * I/O unit. When an external device is connected, it is necessary to secure an access time according to the external device's timing specifications. In this case, in order to secure an access time, the BIU extends the duration of signals required for the access. period of CPU _is normally the same as that of . Note: The CPU operates on the basis of CPU . The _ The internal buses operate on the basis of E. The period of E is at least twice that of . The BIU's functions are described below. (1) Reading out instruction (Instruction prefetch) When the CPU does not request to read or write data, that is, when buses are not in use, the BIU reads instructions from the memory and stores them in an instruction queue buffer. This is called "instruction prefetch." The CPU reads instructions from the instruction queue buffer and executes them. Therefore, the CPU can operate at high speed without waiting for the access by the low-speed memory. When the instruction queue buffer becomes empty or stores only 1 byte of an instruction, the BIU prefetches a new instruction code. The instruction queue buffer can store instructions up to 3 bytes. The contents of the instruction queue buffer is initialized when a branch or jump instruction is executed and the BIU reads a new instruction code from the destination address. If instructions in the instruction queue buffer are insufficient for the CPU's request, the BIU extends the "L"-level duration of clock CPU in order to keep the CPU waiting until the BIU fetches the requested number of instructions or more. (2) Writing data to memory * I/O The CPU informs the BIU's data address register of an address to which data is written and writes the data to the data buffer. The BIU outputs the address received from the CPU to the address bus and writes the data in the data buffer to the specified address. While the BIU is writing data to the specified address, the CPU advances to the next process without waiting for completion of BIU's write operation. Note that while the BIU uses buses for instruction prefetch, the BIU keeps the CPU waiting even when the CPU requests to write data. (3) Signal input/output for access to external device When accessing external devices, the BIU inputs and outputs signals required for the access. (For details, refer to chapter "12. CONNECTING EXTERNAL DEVICES.") 7733 Group User's Manual 2-13 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit 2.2.3 Operation of bus interface unit (BIU) Figure 2.2.3 shows the basic operating waveforms of the bus interface unit (BIU). When accessing external devices, some signals which are input or output to or from the external are required. For details about these signals, refer to chapter "12. CONNECTING EXTERNAL DEVICES." (1) When fetching an instruction into an instruction queue buffer When an instruction which is next fetched resides at an even address The BIU fetches two bytes of the instruction with waveform (a). Note that when an external device which is connected by an 8-bit external data bus (BYTE = "H") is accessed, only one byte of the instruction is fetched. When an instruction which is next fetched resides at an odd address The BIU fetches only one byte of the instruction with waveform (a). The contents at an even address is not fetched into an instruction queue buffer. (2) When reading or writing data from or to memory * I/O When accessing 16-bit data which starts from an even address, waveform (a) is applied. The 16bit data is accessed at a time. When accessing 16-bit data which starts from an odd address, waveform (b) is applied. The 16-bit data is accessed by the 8 bits. Invalid data is not fetched into a data buffer. When accessing 8-bit data at an even address, waveform (a) is applied. Data at an odd address is not fetched into a data buffer. When accessing 8-bit data at an odd address, waveform (a) is applied. Data at an even address is not fetched into a data buffer. For instructions which are affected by the data length flag (m) or index register length flag (x), an operation is applied as follows: * When "m" or "x" = "0," operation or is applied. * When "m" or "x" = "1," operation or is applied. 2-14 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (a) E Internal address bus (A0 to A23) Address Internal data bus (D0 to D7) Data (Even address) Internal data bus (D8 to D15) Data (Odd address) (b) E Internal address bus (A0 to A23) Internal data bus (D0 to D7) Internal data bus (D8 to D15) Address (Odd address) Invalid data Data (Odd address) Address (Even address) Data (Even address) Invalid data Fig. 2.2.3 Basic operating waveforms of bus interface unit (BIU) 7733 Group User's Manual 2-15 CENTRAL PROCESSING UNIT (CPU) 2.3 Accessible area 2.3 Accessible area Figure 2.3.1 shows the M37733MHBXXXFP's accessible area. Although the program counter (PC) consists of 16 bits, it can access the 16-Mbyte area at addresses 0 16 to FFFFFF16, combined with the program bank register (PG). For details about access to the external, refer to chapter "12. CONNECTING EXTERNAL DEVICES." The memories and I/O units are allocated in the same accessible area. Therefore, operations such as data transfer, arithmetic, and others can be performed with the same instructions. (It is not necessary to distinguish the memories and I/O units.) * SFR : Special Function Register 00000016 SFR area 00007F16 00008016 Internal RAM area 000FFF16 Bank 016 00100016 00FFFF16 01000016 Internal ROM area Bank 116 01FFFF16 02000016 FE000016 Bank FE16 FF000016 Bank FF16 represents the memory allocation of internal areas. indicates that nothing is allocated. FFFFFF16 Note: Memory allocation of the internal area in bank 016 depends on the microcomputer's type and settings of the memory allocation selection bits. The above diagram shows the M37733MHBXXXFP's accessible area immediately after reset. For the other microcomputers of the 7733 Group, refer to section "Appendix 1. Memory allocation of 7733 Group." For settings of the memory allocation selection bits, refer to section "2.4 Memory allocation ." Fig. 2.3.1 M37733MHBXXXFP's accessible area 2-16 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.3 Accessible area 2.3.1 Banks The accessible area is divided by the 64 Kbytes. This 64-Kbyte area is called "bank." The high-order 8 bits of an address, which consists of 24 bits, indicate the bank. A bank is specified by the program bank register (PG) or data bank register (DT). Each bank can be accessed efficiently by using an addressing mode where the data bank register (DT) is used. At each bank's boundary, when an overflow occurs in the program counter (PC), the contents of the program bank register (PG) is incremented by 1; when a borrow occurs in the program counter (PC), the contents of the program bank register (PG) is decremented by 1. Accordingly, when normally programming, it is not necessary to give consideration to bank boundaries. 2.3.2 Direct page A 256-byte area specified by the direct page register (DPR) is called "direct page." When setting a direct page, set the base address (the lowest address) of an area which is to be specified as a direct page to the direct page register (DPR). (Refer to section "2.1.8 Direct page register (DPR).") By using a direct page addressing mode, a direct page can be accessed with less instruction cycles. 7733 Group User's Manual 2-17 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory allocation 2.4 Memory allocation The internal area's memory allocation is described below. For the external area, refer to section "2.5 Processor modes." 2.4.1 Memory allocation in internal area SFR (Special Function Register), internal RAM, and internal ROM are allocated in the internal area. (1) SFR (Special Function Register) area Registers required for setting internal peripheral devices are allocated to addresses 016 to 7F16. This area is called "SFR (Special Function Register) area." Figure 2.4.4 shows the SFR area's memory map. For each register in the SFR area, refer to the corresponding functional description. For the state of the SFR area immediately after reset, refer to section "13.1.2 State of CPU, SFR area and internal RAM area." (2) Internal RAM area In the M37733MHBXXXFP, a 3968-byte static RAM is allocated to addresses 8016 to FFF 16 (Note). The internal RAM area is used as a data store area and as a stack area. Therefore, it is necessary to give careful consideration to nesting levels in subroutines and multiple interrupts' levels not to destroy necessary data. (3) Internal ROM area In the M37733MHBXXXFP, a 124-Kbyte mask ROM is allocated to addresses 100016 to 1FFFF 16 immediately after reset (Note). The internal ROM's size and area can be changed by the memory allocation selection bits (bits 0 to 2 at address 6316). Figure 2.4.1 shows the structure of the memory allocation control register and its setting method. Figures 2.4.2 and 2.4.3 show the M37733MHBXXXFP's memory map. (Refer to section "Appendix 9. Q & A.") Vector addresses for reset and interrupts (interrupt vector table) are allocated to addresses FFD6 16 to FFFF 16 in the internal ROM. In the microprocessor mode, where the internal ROM area is inhibited from use, the ROM must be allocated to addresses FFD6 16 to FFFF 16. Note: For the other microcomputers of the 7733 Group, refer to section "Appendix 1. Memory allocation of 7733 Group." 2-18 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.4 Memory allocation b7 b6 b5 b4 b3 b2 b1 b0 0 0 Memory allocation control register (address 63 16) (Note 3) Bit 0 Bit name Memory allocation selection bits (Notes 1 and 2) 1 Functions ROM size 0 0 0: 124 Kbytes, 0 0 1: 120 Kbytes, 0 1 0: 60 Kbytes, 0 1 1: Do not select. 1 0 0: 32 Kbytes, 1 0 1: 16 Kbytes, 1 1 0: 96 Kbytes, 1 1 1: Do not select. b2b1b0 At reset RW ROM size 3968 bytes 3968 bytes 2048 bytes 0 RW 2048 bytes 2048 bytes 3968 bytes 0 RW 0 RW 2 3 Must be fixed to "0." (Note 1) 4 7 to 5 0 RW 0 RW Undefined Not implemented. | Notes 1: The case where value "55 16" is written in of the procedure listed below is not included. 2: When changing these bits, this change must be performed in an area which is internal ROM area before and after this change, for example addresses 00C000 16 to 00FFFF 16. Also, when changing these bits, be sure to follow the procedure listed below. 3: This figure is applied only to the M37733MHBXXXFP. For the other microcoputers, please refer to the latest datasheets on the English document CD-ROM or our Web site. Procedure By using the LDM instruction, write value "55 16" to address 63 16. (By this, writing to the memory allocation selection bits is enabled.) By using the LDM instruction, write value "00000XXX 2" to address 63 16. (Values of b2, b1, and b0 shown in the above Figure) Writing is performed by the next instruction. Note: When changing bits 2 to 0, be sure to follow this procedure. Fig. 2.4.1 Structure of memory allocation control register and its setting method 7733 Group User's Manual 2-19 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory allocation * Memory allocation selection bits (b2, b1, b0)=(0, 0, 0) * ROM size: 124 Kbytes * RAM size: 3.9 Kbytes 00000016 00007F16 00008016 SFR area Internal RAM area 3968 bytes 000FFF16 00100016 00000016 00007F16 00008016 000FFF16 * Memory allocation selection bits (b2, b1, b0)=(0, 0, 1) * ROM size: 120 Kbytes * RAM size: 3.9 Kbytes SFR area 00000016 Internal RAM area 3968 bytes Peripheral device control registers (SFR) (4 Kbytes) 00200016 Refer to Appendix 2. Bank 016 Internal ROM area 60 Kbytes 00FFFF16 01000016 Internal ROM area 56 Kbytes 00007F16 Interrupt vector table 00FFFF16 01000016 00FFD616 A-D/UART2 trans./rece. UART1 transmission UART1 reception Bank 116 Internal ROM area 64 Kbytes Internal ROM area 64K bytes UART0 transmission UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 01FFFF16 02000016 Timer A3 01FFFF16 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Bank 216 Watchdog timer DBC BRK instruction Zero divide 00FFFE16 RESET 02FFFF16 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode FF000016 Bank FF16 FFFFFF16 FFFFFF16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes.") 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. (Refer to section "Appendix 1 in part 2.") Fig. 2.4.2 M37733MHBXXXFP's memory map (1) 2-20 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.4 Memory allocation * Memory allocation selection bits (b2, b1, b0)=(0, 1, 0) * ROM size: 60 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 2048 bytes 00087F16 (1.9 Kbytes) 00100016 * Memory allocation selection bits (b2, b1, b0)=(1, 0, 0) * ROM size: 32 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 2048 bytes 00087F16 00000016 Peripheral device control registers (SFR) Refer to Appendix 2. (29.9 Kbytes) Bank 016 Internal ROM area 60 Kbytes 00FFFF16 01000016 00800016 Internal ROM area 32 Kbytes 00FFFF16 01000016 00007F16 Interrupt vector table 00FFD616 A-D/UART2 trans./rece. UART1 transmission UART1 reception UART0 transmission UART0 reception Bank 116 Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 01FFFF16 02000016 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Bank 216 Watchdog timer DBC BRK instruction Zero divide 00FFFE16 RESET 02FFFF16 FF000016 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Bank FF16 FFFFFF16 FFFFFF16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes.") 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Fig. 2.4.3 M37733MHBXXXFP's memory map (2) 7733 Group User's Manual 2-21 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory allocation * Memory allocation selection bits (b2, b1, b0)=(1, 0, 1) * ROM size: 16 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 2048 bytes 00087F16 00000016 00007F16 00008016 000FFF16 00100016 Bank 016 * Memory allocation selection bits (b2, b1, b0)=(1, 1, 0) * ROM size: 96 Kbytes * RAM size: 3968 bytes SFR area 00000016 Internal RAM area 3968 bytes Peripheral device control registers (SFR) Refer to Appendix 2. (28 Kbytes) (45.9 Kbytes) 00800016 Internal ROM area 32 Kbytes 00C00016 Internal ROM area 16 Kbytes 00FFFF16 01000016 00FFFF16 01000016 00007F16 Interrupt vector table 00FFD616 A-D/UART2 trans./rece. UART1 transmission UART1 reception UART0 transmission UART0 reception Internal ROM area 64 Kbytes Bank 116 Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 01FFFF16 02000016 01FFFF16 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Bank 216 Watchdog timer DBC BRK instruction Zero divide 00FFFE16 RESET 02FFFF16 FF000016 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Bank FF16 FFFFFF16 FFFFFF16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes.") 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Fig. 2.4.4 M37733MHBXXXFP's memory map (3) 2-22 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.4 Memory allocation Address (Hexadecimal notation) 000000 000001 000002 Port P0 register 000003 Port P1 register 000004 Port P0 direction register 000005 Port P1 direction register 000006 Port P2 register 000007 Port P3 register 000008 Port P2 direction register 000009 Port P3 direction register 00000A Port P4 register 00000B Port P5 register 00000C Port P4 direction register 00000D Port P5 direction register 00000E Port P6 register 00000F Port P7 register 000010 Port P6 direction register 000011 Port P7 direction register 000012 Port P8 register 000013 000014 Port P8 direction register 000015 000016 000017 000018 000019 00001A 00001B 00001C Reserved area (Note) 00001D Reserved area (Note) 00001E A-D control register 0 00001F A-D control register 1 000020 A-D register 0 000021 000022 A-D register 1 000023 000024 A-D register 2 000025 000026 A-D register 3 000027 000028 A-D register 4 000029 00002A A-D register 5 00002B 00002C A-D register 6 00002D 00002E A-D register 7 00002F 000030 UART 0 transmit/receive mode register 000031 UART 0 baud rate register (BRG0) 000032 UART 0 transmission buffer register 000033 000034 UART 0 transmit/receive control register 0 000035 UART 0 transmit/receive control register 1 000036 UART 0 receive buffer register 000037 000038 UART 1 transmit/receive mode register 000039 UART 1 baud rate register (BRG1) 00003A UART 1 transmission buffer register 00003B 00003C UART 1 transmit/receive control register 0 00003D UART 1 transmit/receive control register 1 00003E UART 1 receive buffer register 00003F Address (Hexadecimal notation) 000040 000041 000042 000043 000044 000045 000046 000047 000048 000049 00004A 00004B 00004C 00004D 00004E 00004F 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005A 00005B 00005C 00005D 00005E 00005F 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006A 00006B 00006C 00006D 00006E 00006F 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007A 00007B 00007C 00007D 00007E 00007F Count start flag One-shot start flag Up-down flag Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Watchdog timer frequency selection flag Reserved area (Note) Memory allocation control register UART2 transmit/receive mode register UART2 baud rate register (BRG2) UART2 transmission buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Oscillation circuit control register 0 Port function control register Serial transmit control register Oscillation circuit control register 1 A-D/UART2 trans./rece. interrupt control register UART 0 transmission interrupt control register UART 0 receive interrupt control register UART 1 transmission interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2/Key input interrupt control register Note: Writing to reserved area is disabled. Fig. 2.4.5 SFR area's memory map 7733 Group User's Manual 2-23 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes 2.5 Processor modes The M37733MHBXXXFP can operate in the following three processor modes: single-chip mode, memory expansion mode, and microprocessor mode. In the M37733MHBXXXFP, some pins' functions, memory allocation, and accessible area differ according to processor modes. These differences according to processor modes are described below. Figure 2.5.1 shows the memory map in each processor mode. Single-chip mode Memory expansion mode Microprocessor mode SFR area SFR area SFR area Internal RAM area Internal RAM area Internal RAM area Internal ROM area (Note 2) Internal ROM area (Note 2) 00000016 00008016 000FFF16 00100016 01FFFF16 02000016 FFFFFF16 Notes 1: represents external memory area. By accessing this area, an external device connected to the M37733MHBXXXFP can be accessed. 2: This is applied when the contents of memory allocation selection bits (bits 2 to 0 at address 6316) = "0002." 3: For the 7733 Group's microcomputers other than the M37733MHBXXXFP, refer to section "Appendix 1. Memory allocation of 7733 Group." Fig. 2.5.1 Memory map in each processor mode (M37733MHBXXXFP) 2-24 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes 2.5.1 Single-chip mode When not using an external device, this mode is used. In this mode, ports P0 to P8 function as programmable I/O ports. (When using internal peripheral devices, they function as I/O pins.) Only the internal area (SFR, internal RAM, and internal ROM) can be accessed. _ Output of E can be stopped by software. (Refer to section "12.1 Signals required for accessing external devices.") 2.5.2 Memory expansion and Microprocessor modes When connecting an external device, these modes are used. In these modes, an external device can be connected to an arbitrary area in the 16-Mbyte accessible area. For access to an external device, refer to chapter "12. CONNECTING EXTERNAL DEVICES." The memory expansion and microprocessor modes have the same functions except for the followings: In the microprocessor mode, access to the internal ROM area is forcibly disabled. This area is handled as the external area. In the microprocessor mode, port P42 functions as a clock 1 output pin. (Note) In the memory expansion and microprocessor modes, pins P0 to P3, P40, and P4 1 function as I/O pins for signals required for access to an external device. Therefore, these pins cannot be used as programmable I/O ports. If an external device is connected to a certain area which is allocated to the internal area, when this area is read, data in the internal area is fetched into the central processing unit (BIU) but data in the external area is not fetched; when data is written to this area, the data is written to the internal area and signals are output to the external at the same timing as writing to the internal area. Note: Output of clock 1 can be stopped by software. (For details, refer to section "12.1 Signals required for accessing external devices.") Figure 2.5.2 shows the pin configuration in each processor mode. Table 2.5.1 lists the relationship between processor modes and functions of P0 to P4. For each pin's function, refer to section "1.3 Pin description," chapters "3. PROGRAMMABLE I/O PORTS" to "9. A-D CONVERTER" and "12. CONNECTING EXTERNAL DEVICES." 7733 Group User's Manual 2-25 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 <Single-chip mode> 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG/TXD2 P74/AN4/RXD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 65 40 66 39 67 38 68 37 69 36 70 35 71 34 74 31 75 30 76 29 77 28 78 27 79 26 P24 P25 P26 P27 P30 P31 P32 P33 VSS E XOUT XIN RESET CNVSS 1 BYTE 1 80 25 P40 M37733MHBXXXFP 72 73 2 3 4 5 6 7 8 32 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P70/AN0 P67/TB2IN/f SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 P42/f 1 P41 1 33 1 Connect this pin to Vss in the single-chip mode. : These pins' functions in the single-chip mode differ from those in the memory expansion or microprocessor mode. P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 A0 A1 A2 A3 A4 A5 A6 A7 A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 A16/D0 A17/D1 A18/D2 A19/D3 <Memory expansion and Microprocessor modes> 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 39 67 38 68 37 69 36 70 35 71 34 M37733MHBXXXFP 72 73 33 32 74 31 75 30 76 29 77 28 78 27 79 26 80 25 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P70/AN0 P67/TB2IN/f SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 2 P42/f 1 1 A20/D4 A21/D5 A22/D6 A23/D7 R/W BHE ALE HLDA VSS E XOUT XIN RESET CNVSS BYTE HOLD RDY P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG/TXD2 P74/AN4/RXD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 2 f 1 in the microprocessor mode : These pins' functions in the single-chip mode differ from those in the memory expansion or microprocessor mode. Fig. 2.5.2 Pin configuration in each processor mode (Top view) 2-26 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes Table 2.5.1 Relationship between processor modes and functions of P0 to P4 Processor mode Memory expansion and Microprocessor modes Single-chip mode Pin name A7 to A0 P P0 P: Functions as a programmable I/O port. When external data bus is 16 bits wide (BYTE = "L") P P1 A15 to A8 P: Functions as a programmable I/O port. D(odd) D(odd): Data at odd address When external data bus is 8 bits wide (BYTE = "H") A15 to A8 When external data bus is 16 bits wide (BYTE = "L") P A23 to A16 P: Functions as a programmable I/O port. D(even) D(even): Data at even address P2 When external data bus is 8 bits wide (BYTE = "H") A23 to A16 D D: Data P P3 P33 P: Functions as a programmable I/O port. HLDA ALE P32 P31 BHE P30 R/W P47 to P43 P P: Functions as a programmable I/O port. (Note 1) P P: Functions as a programmable I/O port. P42 f1 (Note 2) P4 P41 RDY P40 HOLD Notes 1: Pin P42 can also function as a clock f 1 output pin. (Refer to chapter "12. CONNECTING EXTERNAL DEVICES.") 2: In the memory expansion mode, this pin functions as a programmable I/O port. Furthermore, it can be switched to be a clock f 1 output pin when selected by software. In the microprocessor mode, this pin is affected by the signal output disable selection bit (bit 6 at address 6C16 ). (Refer to chapter"12. CONNECTING EXTERNAL DEVICES.") 3: The above table indicates the change of pin functions owing to the switching of the processor mode. For each signal's I/O timing in the memory expantion or microprocessor mode, refer to chapters"12. CONNECTING EXTERNAL DEVICES"and "15. ELECTRICAL CHARACTERISTICS." 7733 Group User's Manual 2-27 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes 2.5.3 Selection of processor mode A processor mode can be selected by setting a voltage applied to pin CNVSS and the processor mode bits (bits 1 and 0 at address 5E16). When V SS level is applied to pin CNV SS After reset, the microcomputer starts operating in the single-chip mode. After the microcomputer starts operating, the processor mode can be switched by the processor mode bits. When the contents of the processor mode bits = "012," the memory expansion mode is selected; when the contents of these bits = "10 2," the microprocessor mode is selected. After the_ processor mode bits are set, the processor mode is actually switched at the rising edge of signal E. Figure 2.5.3 shows the pin function switch timing when the processor mode is switched from the single-chip mode to the memory expansion or microprocessor mode by setting the processor mode bits. Note that, when the processor mode is switched during the program execution, the contents of the instruction queue buffer is not initialized. (Refer to section "Appendix 9. Q & A.") When V CC level is applied to pin CNV SS After reset, the microcomputer starts operating in the microprocessor mode. In this case, the microcomputer cannot operate in the other modes. (Fix the processor mode bits to "102.") Table 2.5.2 lists the method of selecting the processor mode. Figure 2.5.4 shows the structure of the processor mode register 0. Writing to the processor mode bits E P07 Programmable I/O port P07 External address bus A7 Note: Functions of pins P00 to P06, P1 to P3, P40 to P42 are switched at the timing shown above. Function of pin P42 is, however, switched only when the processor mode is switched to microprocessor mode. Fig. 2.5.3 Pin function switch timing 2-28 7733 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes Table 2.5.2 Method of selecting processor mode Processor mode Processor mode bits Pin CNV SS's level Single-chip mode Memory expansion mode Microprocessor mode V SS V SS V SS V CC (0 (0 (0 (5 V) V) V) V) (Note (Note (Note (Note 1) 1) 1) 2) b1 b0 0 0 0 1 1 0 Notes 1: The microcomputer starts operating in the single-chip mode after reset. By setting the processor mode bits, the processor mode of the microcomputer can be switched from the single-chip mode to the other modes. 2: The microcomputer starts operating in the microprocessor mode after reset. The microcomputer cannot operate in the other modes. Accordingly, so fix the processor mode bits (bits 1 and 0 at address 5E 16) to "102." b7 b6 0 b5 b4 b3 b2 b1 b0 Processor mode register 0 (address 5E16) Bit name Bit Processor mode bits 0 Functions b1 b0 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Microprocessor mode 1 1: Do not select. 1 At reset RW 0 RW 0 RW (Note 1) 2 Wait bit 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. 0 RW 3 Software reset bit Microcomputer is reset by setting this bit to "1." This bit is "0" at reading. 0 WO 4 Interrupt priority detection time selection bits 0 RW 0 RW 0 RW 0 RW 5 6 Must be fixed to "0." 7 Clock f 1 output selection bit (Note 2) b5 b4 0 0: 7 cycles of f 0 1: 4 cycles of f 1 0: 2 cycles of f 1 1: Do not select. 0: Clock f 1 output is disabled. (P42 functions as a programmable I/O port.) 1: Clock f 1 output is enabled. (Port P42 functions as a clock f 1 output pin.) Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to "1" after reset. (When read, this bit is always "0.") 2: This bit is ignored in the microprocessor mode. (It may be "0" or "1.") 3: represents that bits 2 to 7 are not used for selecting a processor mode. Fig. 2.5.4 Structure of processor mode register 0 7733 Group User's Manual 2-29 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes [Precautions on selecting processor mode] 1. The external ROM version can operate only in the microprocessor mode. Therefore, be sure to set as follows: *Connect pin CNVss to Vcc. *Fix the processor mode bits (b1, b0) to "10 2." 2-30 7733 Group User's Manual CHAPTER 3 PROGRAMMABLE I/O PORTS 3.1 3.2 3.3 3.4 Programmable I/O ports Port peripheral circuits Pullup function Internal peripheral devices' I/O functions (Ports P42 and P5 to P8) PROGRAMMABLE I/O PORTS 3.1 Programmable I/O ports Functions of all ports in the single-chip mode and that of ports P4 3 to P4 7 and P5 to P8 in the memory expansion and the microprocessor modes are described below. For more information about ports P0 to P4, whose functions depend on the processor mode, refer to section "2.5 Processor modes" and chapter "12. CONNECTING EXTERNAL DEVICES." 3.1 Programmable I/O ports The 7733 Group has 68 programmable I/O ports (P0 to P8). Each of ports P0 to P8 has a port direction register and a port register in the SFR area. Each input-only port has a port register in the SFR area. Figure 3.1.1 shows the memory map of port direction registers and port registers. Note that ports P42 and P5 to P8 also function as I/O pins for internal peripheral devices. For details, refer to section "3.4 Internal peripheral devices' I/O functions" and the corresponding functional description. addresses 216 Port P0 register 316 Port P1 register 416 Port P0 direction register 516 Port P1 direction register 616 Port P2 register 716 Port P3 register 816 Port P2 direction register 916 Port P3 direction register A16 Port P4 register B16 Port P5 register C16 Port P4 direction register D16 Port P5 direction register E16 Port P6 register F16 Port P7 register 1016 Port P6 direction register 1116 Port P7 direction register 1216 Port P8 register 1316 1416 Port P8 direction register Fig. 3.1.1 Memory map of port direction registers and port registers 3-2 7733 Group User's Manual PROGRAMMABLE I/O PORTS 3.1 Programmable I/O ports 3.1.1 Port Pi direction register This register determines the direction of programmable I/O ports. Each bit of this register corresponds to one specified pin. Figure 3.1.2 shows the structure of the port Pi (i = 0 to 8) direction register. b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 0 to 8) (addresses 416,516,816,916,C16,D16,1016,1116,1416) Bit Bit name Functions At reset RW 0 RW 0 RW 0 RW 0 Port Pi0 direction selection bit 1 Port Pi1 direction selection bit 2 Port Pi2 direction selection bit 3 Port Pi3 direction selection bit 0 RW 4 Port Pi4 direction selection bit 0 RW 5 Port Pi5 direction selection bit 0 RW 6 Port Pi6 direction selection bit 0 RW 7 Port Pi7 direction selection bit 0 RW 0: Input mode (The port functions as an input port.) 1: Output mode (The port functions as an output port.) Note: Writing to bits 4 to 7 of the port P3 direction register is invalid and these bits are fixed to "0" when they are read. Bit b7 b6 b5 b4 b3 b2 b1 b0 Corresponding pin Pi7 Pi6 Pi5 Pi4 Pi3 Pi2 Pi1 Pi0 Fig. 3.1.2 Structure of port Pi (i = 0 to 8) direction register 7733 Group User's Manual 3-3 PROGRAMMABLE I/O PORTS 3.1 Programmable I/O ports 3.1.2 Port Pi register Data is input from or output to an external device by writing/reading data to/from a port register. A port register consists of a port latch, which holds the output data, and a circuit, which reads the pin state. Each bit of the port register corresponds to one specified pin. Figure 3.1.3 shows the structure of the port Pi (i = 0 to 8) register. (1) How to output data from programmable I/O port Set the corresponding bit of the port direction register to the output mode. Write data to the corresponding bit of the port register, and then the data is written into the port latch. Data set in the port latch is output. When a bit of a port register which corresponds to a port set for the output mode is read out, the contents of the port latch, instead of pin state, is read out. Accordingly, output data can correctly be read out without influence of external load, etc. (Refer to Figures 3.2.1 and 3.2.2) (2) How to input data from programmable I/O port Set the corresponding bit of the port direction register to the input mode. The pin enters a floating state. When reading the corresponding bit of the port register in state , data input from the pin can be read in. When data is written to a port register which corresponds to a port set for the input mode, the data is written only into the port latch and not output to the external devices. Pins retain a floating state. 3-4 7733 Group User's Manual PROGRAMMABLE I/O PORTS 3.1 Programmable I/O ports b7 b6 b5 b4 b3 b2 b1 b0 Port Pi register (i = 0 to 8) (addresses 216,316,616,716,A16,B16,E16,F16,1216) Bit Bit name Functions At reset RW Undefined RW Undefined RW Undefined RW Undefined RW 0 Port Pi0's pin 1 Port Pi1's pin 2 Port Pi2's pin 3 Port Pi3's pin 4 Port Pi4's pin Undefined RW 5 Port Pi5's pin Undefined RW 6 Port Pi6's pin Undefined RW 7 Port Pi7's pin Undefined RW Data is input from or output to a pin by reading from or writing to the corresponding bit. 0: "L" level 1: "H" level Note: Writing to bits 4 to 7 of the port P3 register is invalid and these bits are fixed to "0" when they are read. Fig. 3.1.3 Structure of port Pi (i = 0 to 8) register 7733 Group User's Manual 3-5 PROGRAMMABLE I/O PORTS 3.2 Port peripheral circuits 3.2 Port peripheral circuits Figures 3.2.1 and 3.2.2 show the port peripheral circuits. * Ports P00 to P07, P10 to P17, P20 to P27, P30 to P33, P43 to P46 (Inside dotted-line not included) Ports P40/HOLD, P41/RDY, P47, P51/TA0IN, P53/TA1IN, P61/TA4IN, P65/TB0IN to P67/TB2IN/ f SUB, P86/RxD1 (Inside dotted-line included) Port direction register Data bus Port latch * Ports P83/TxD0, P87/TxD1 (Inside dotted-line not included, and shaded area included) Ports P50/TA0OUT, P52/TA1OUT , P60/TA4OUT, P75/AN5/ADTRG/TxD2, P82/RxD0/CLKS0 (Inside dotted-line included, and shaded area not included) Port P42/ 1 (Inside dotted-line not included, and shaded area not included) Notes 1: Valid only when used as pin N-channel open-drain TxDj for Serial I/O. selection (Note 1) 2: Analog input is present only in port P75. Port direction register "1" Output Data bus Port latch Analog input (Note 2) * Ports P54/TA2OUT/KI0, P56/TA3OUT/KI2 Pull-up selection Port direction register "1" Pull-up transistor Output Data bus Port latch * Ports P55/TA2IN/KI1, P57/TA3IN/KI3 , P62/INT0 to P64/INT2 Pull-up selection Port direction register Pull-up transistor Data bus Port latch Fig. 3.2.1 Port peripheral circuits (1) 3-6 7733 Group User's Manual PROGRAMMABLE I/O PORTS 3.2 Port peripheral circuits * Ports P70/AN0, P71/AN1, P76/AN6/XCOUT, P77/AN7/XCIN (Inside dotted-line not included) Ports P72/AN2/CTS2, P74/AN4/RxD2 (Inside dotted-line included) Port direction register Data bus Port latch (Note 1) Sub-clock oscillation circuit Analog input Note 1: The sub-clock oscillation circuit is present only in ports P76 and P77 * Ports P73/AN3/CLK2, P80/CTS0/RTS0/CLKS1, P81/CLK0, P84/CTS1/RTS1, P85/CLK1 "1" Port direction register "0" AA AA Output Data bus Port latch Analog input (Note 2) Note 2: Analog input is present only in port P73 *E Fig. 3.2.2 Port peripheral circuits (2) 7733 Group User's Manual 3-7 PROGRAMMABLE I/O PORTS 3.3 Pull-up function 3.3 Pull-up function ___ ___ 3.3.1 Pull-up function for ports P54 to P5 7 ( KI0 to KI 3) ___ ___ Ports P54 to P57 (KI0 to KI3) can be pulled high by setting the port P5 pull-up selection bit (bit 6 at address 6D 16). Figure 3.3.1 shows the structure of the port function control register. When pulling ports P5 4 to P5 7 high, clear bits 4 to 7 at address D 16 (Port P5 direction register) to "0." ____ ____ 3.3.2 Pull-up function for ports P62 to P6 4 (INT 0 to INT2 ) ____ ____ Ports P6 2 and P63 ( INT0 and____ INT1 ) can be pulled high by setting the port P6 pull-up selection bit 0 (bit 3 at address 6D 16 ). Port P64 ( INT2 ) can be pulled high by setting the port P6 pull-up selection bit 1 (bit 5 at address 6D 16). Figure 3.3.1 shows the structure of the port function control register. When pulling ports P6 2 to P6 4 high, clear bits 2 to 4 at address 10 16 (port P6 direction register) to "0." 3-8 7733 Group User's Manual PROGRAMMABLE I/O PORTS 3.3 Pull-up function b7 b6 b5 b4 0 b3 b2 b1 b0 Port function control register (address 6D16) At reset RW 0 RW Sub-clock output selection bit/ *Port-XC selection bit = "0" (when the sub clock is not used) Timer B2 clock source selection Timer B2 (event counter mode) bit clock source selection (Note 1) 0: TB2IN input (event counter mode) 1: Main clock divided by 32 (clock timer) *Port-XC selection bit = "1" (when the sub clock is used) Sub-clock output selection 0: Pin P67/TB2IN/f SUB functions as a programmable I/O port. 1: Sub clock f SUB is output from pin P67/TB2IN/f SUB. 0 RW 2 Timer B1 internal connect selection bit (Note 2) 0: No internal connection 1: Internal connection with timer B2 0 RW 3 Port P6 pull-up selection bit 0 0: No pull-up for pins P62/INT0 and P63/INT1 1: With pull-up for pins P62/INT0 and P63/INT1 0 RW 4 Must be fixed to "0." 0 RW 5 Port P6 pull-up selection bit 1 *Key input interrupt selection bit = "0" 0: No pull-up for pin P64/INT2 1: With pull-up for pin P64/INT2 *Key input interrupt selection bit = "1" 0: Pin P64/INT2 is a port with no pull-up. 1: Pin P64/INT2 is an input pin with pull-up and is used for the key input interrupt. 0 RW 6 Port P5 pull-up selection bit 0: No pull-up for pins P54/TA2OUT/KI0 to P57/TA3IN/KI3 1: With pull-up for pins P54/TA2OUT/KI0 to P57/TA3IN/KI3 0 RW 7 Key input interrupt selection bit 0: INT2 interrupt 1: Key input interrupt 0 RW Bit 0 1 Bit name Standby state selection bit Functions 0: Pins P0 to P3 are used for the external bus output. 1: Pins P0 to P3 are used for the port output. Port-Xc selection bit : Bit 4 of the oscillation circuit control register 0 (address 6C16) Notes 1: When the port-Xc selection bit = "0" and timer B2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: When timer B1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 to 2, 4, and 7 are not used for the pull-up function. Fig. 3.3.1 Structure of port function control register 7733 Group User's Manual 3-9 PROGRAMMABLE I/O PORTS 3.4 Internal peripheral devices' I/O functions (Ports P42 and P5 to P8) 3.4 Internal peripheral devices' I/O functions (Ports P42 and P5 to P8) Ports P4 2 and P5 to P8 also function as I/O pins for the internal peripheral devices. Table 3.4.1 lists correspondence between each port and internal peripheral devices' I/O pin. For internal peripheral devices' I/O functions, refer to the corresponding functional description. For the clock 1 output pin, refer to chapter "12. CONNECTING EXTERNAL DEVICES." For the sub-clock oscillation circuit's I/O pins, refer to chapter "14. CLOCK GENERATING CIRCUIT." Table 3.4.1 Correspondence between each port and internal peripheral devices' I/O pin Port Internal peripheral devices' I/O pin P42 Clock 1 output pin P5 0 to P5 3 Timer A's I/O pins P5 4 to P5 7 P60, P6 1 Timer A's I/O pins/Key input interrupt function's input pins P6 2 to P6 4 Input pins for external interrupts P65, P6 6 P67 Timer B's input pins Timer B's input pin/Clock P70, P7 1 A-D converter's input pins P7 2 to P7 5 P76, P7 7 A-D converter's input pins/I/O pins for serial I/O P8 I/O pins for serial I/O 3-10 Timer A's I/O pins SUB output pin Sub-clock oscillation circuit's I/O pins/A-D converter's input pins 7733 Group User's Manual CHAPTER 4 INTERRUPTS 4.1 4.2 4.3 4.4 4.5 Overview Interrupt sources Interrupt control Interrupt priority level Interrupt priority level detection circuit 4.6 Interrupt priority level detection time 4.7 How interrupts are processed (from acceptance of interrupt request till execution of interrupt routine) 4.8 Return from interrupt routine 4.9 Multiple interrupts ____ 4.10 External interrupts ( INTi interrupt) 4.11 Precautions for interrupts INTERRUPTS 4.1 Overview The 7733 Group provides 19 interrupt sources to generate interrupt requests. 4.1 Overview Figure 4.1.1 shows how interrupts are processed. When an interrupt request is accepted, a program branches to the start address of an interrupt routine which is set in the interrupt vector table (addresses FFD6 16 to FFFF16 ). Set the start address of each interrupt routine to the corresponding interrupt vector address in the interrupt vector table. Routine in progress ress add art . t s o e es t utin nch upt ro a r B terr of in Interrupt request is accepted. Interrupt routine Interrupt processing Processing is suspended. Retu rns t Processing is resumed. o ori ginal routi Fig. 4.1.1 How interrupts are processed 4-2 7733 Group User's Manual ne. RTI instruction INTERRUPTS 4.1 Overview When an interrupt request is accepted, the following registers' contents immediately before acceptance of an interrupt request are automatically pushed onto the stack area , , and in that order: Program bank register (PG) Program counter (PC L, PC H) Processor status register (PSL, PSH) Figure 4.1.2 shows the state of the stack area immediately before the program branches to an interrupt routine. At the end of the interrupt routine, execute the RTI instruction, which is an instruction for returning to the routine that was executed before acceptance of an interrupt request. By executing the RTI instruction, the above registers' contents, which were pushed onto the stack area, are popped , , and in that order. Then, execution of the suspended routine is resumed from where it left off. When an interrupt request is accepted and the RTI instruction is executed, above registers ( to ) are automatically pushed and popped. For other registers whose contents are necessary, be sure to push and pop them by software. Stack area Address [S] - 5 [S] - 4 Processor status register's low-order byte (PS L) [S] - 3 Processor status register's high-order byte (PS H) [S] - 2 Program counter's low-order byte (PC L) [S] - 1 Program counter's high-order byte (PC H) [S] Program bank register (PG) [S] is the initial address that the stack pointer (S) indicates when an interrupt request is accepted. S's contents is "[S] - 5" after all of the above registers are pushed. Fig. 4.1.2 State of stack area immediately before program branches to interrupt routine 7733 Group User's Manual 4-3 INTERRUPTS 4.2 Interrupt sources 4.2 Interrupt sources Table 4.2.1 lists interrupt sources and their vector addresses. When programming, set the start address of each interrupt routine to the vector addresses listed below. Table 4.2.1 Interrupt sources and Interrupt vector addresses Interrupt source Interrupt vector addresses Low-order High-order address address Remarks Reset 00FFFF16 00FFFE16 Non-maskable Zero division 00FFFD 16 00FFFC 16 Non-maskable software interrupt BRK instruction 00FFFB16 00FFFA16 DBC (Note 1) 00FFF9 16 00FFF8 16 Non-maskable software interrupt Not used usually Watchdog timer 00FFF6 16 00FFF4 16 Non-maskable interrupt INT0 00FFF7 16 00FFF5 16 INT1 00FFF3 16 00FFF2 16 External interrupt by signal input from pin INT1 INT2/Key input (Note 2) ____ External interrupt by signal input from pin INT0 00FFF1 16 00FFF0 16 External interrupt by signal input from pin INT2 or by key input Timer A0 00FFEF16 00FFEE 16 Timer A1 00FFED16 00FFEC16 Internal interrupt from Timer A0 Internal interrupt from Timer A1 Timer A2 00FFEB 16 00FFE916 00FFEA 16 00FFE816 Internal interrupt from Timer A2 Timer A3 Timer A4 Internal interrupt from Timer A3 00FFE716 00FFE616 Internal interrupt from Timer A4 Timer B0 00FFE516 00FFE416 Timer B1 00FFE316 00FFE216 Internal interrupt from Timer B0 Internal interrupt from Timer B1 Timer B2 UART0 reception UART0 transmission 00FFE116 00FFDF 16 00FFE016 00FFDE16 00FFDD 16 00FFDC16 UART1 reception 00FFDB16 00FFDA16 UART1 transmission 00FFD916 00FFD816 Internal interrupt from Timer B2 Internal interrupt from UART0 Internal interrupt from UART1 A-D/UART2 trans./ 00FFD616 Internal interrupt from A-D converter or UART2 00FFD716 /rece. (Note 3) Notes 1: This is only for debugger control and is not used usually. 2: When the key input interrupt selection bit (bit 7 at address 6D 16) = "1," the key input interrupt function is selected. For details, refer to chapter "5 KEY INPUT INTERRUPT FUNCTION." 3: The A-D conversion interrupt and the UART2 transmission/reception interrupt share the same interrupt vector addresses and interrupt control register. By setting the serial I/O mode selection bits (bits 0 to 2 at address 6416 ), the A-D conversion interrupt or UART2 transmission/reception interrupt is selected. 4-4 7733 Group User's Manual INTERRUPTS 4.2 Interrupt sources Table 4.2.2 lists occurrence conditions of internal interrupt requests, which occur because of internal operations. Table 4.2.2 Occurrence conditions of internal interrupt requests Interrupt Occurrence conditions of interrupt requests Zero division Occurs when divider is "0" in execution of DIV instruction (Division instruction). interrupt (Refer to "7700 Family Software Manual.") BRK instruction Occurs when the BRK instruction is executed. interrupt (Refer to "7700 Family Software Manual.") Watchdog timer interrupt Occurs when the most significant bit of the watchdog timer becomes "0." (Refer to chapter "10 WATCHDOG TIMER.") Timer Ai interrupt Occurrence condition depends on Timer Ai's operating modes. (i = 0 to 4) (Refer to chapter "6 TIMER A.") Timer Bi interrupt Occurrence condition depends on Timer Bi's operating modes. (i = 0 to 2) (Refer to chapter "7 TIMER B.") UARTi reception interrupt (i = 0,1) Occurs at serial data reception. (Refer to chapter "8 SERIAL I/O.") UARTi transmission Occurs at serial data transmission. interrupt (i = 0,1) (Refer to chapter "8 SERIAL I/O.") UART2 Occurs at serial data transmission/reception. transmission (Refer to chapter "8 SERIAL I/O.") /reception interrupt A-D conversion Occurs when A-D conversion is completed. interrupt (Refer to chapter "9 A-D CONVERTER.") For external interrupts, refer to section "4.10 External interrupts." For the key input interrupt, refer to chapter "5 KEY INPUT INTERRUPT FUNCTION." 7733 Group User's Manual 4-5 INTERRUPTS 4.3 Interrupt control 4.3 Interrupt control Maskable interrupts are enabled or disabled by setting the following: Interrupt request bit Interrupt priority level selection bits Processor interrupt priority level (IPL) Interrupt disable flag (I) The interrupt disable flag (I) and processor interrupt priority level (IPL) are allocated to the processor status register (PS). An interrupt request bit and the interrupt priority level selection bits are allocated to the interrupt control register for the corresponding interrupt. Figure 4.3.1 shows the memory map of interrupt control registers and Figure 4.3.2 shows their structures. Maskable interrupts : By software, acceptance of these interrupts' requests can be disabled. Non-maskable interrupts (Zero division, BRK instruction, and watchdog timer interrupts) : When an interrupt request occurs, it is certain to be accepted. They do not have interrupt control registers and are not affected by the interrupt disable flag (I). Address 7016 A-D /UART2 trans./rece. interrupt control register 7116 UART0 transmission interrupt control register 7216 UART0 receive interrupt control register 7316 UART1 transmission interrupt control register 7416 UART1 receive interrupt control register 7516 Timer A0 interrupt control register 7616 Timer A1 interrupt control register 7716 Timer A2 interrupt control register 7816 Timer A3 interrupt control register 7916 Timer A4 interrupt control register 7A16 Timer B0 interrupt control register 7B16 Timer B1 interrupt control register 7C16 Timer B2 interrupt control register 7D16 INT 0 interrupt control register 7E16 INT 1 interrupt control register 7F16 INT 2/Key input interrupt control register Fig. 4.3.1 Interrupt control registers' memory map 4-6 7733 Group User's Manual INTERRUPTS 4.3 Interrupt control b7 b6 b5 b4 b3 b2 b1 b0 A-D/UART2 trans./rece., UART0 and 1 transmission, UART0 and 1 receive, Timers A0 to A4, Timers B0 to B2 interrupt control registers (addresses 7016 to 7C16) Bit Bit name Interrupt priority level 0 selection bits 1 2 Interrupt request bit 3 Functions b2b1b0 0 0 0 : Level 0 (Interrupt is disabled.) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: No interrupt request has occurred. 1: Interrupt request has occurred. At reset RW 0 RW 0 RW 0 RW 0 RW Undefined -- 4 Not implemented. 5 6 7 b7 b6 b5 b4 b3 b2 b1 b0 INT0, INT1, and INT2/Key input interrupt control registers (addresses 7D16 to 7F16) Bit Bit name Interrupt priority level 0 selection bits 1 2 3 Interrupt request bit (Note) 0: No interrupt request has occurred. 1: Interrupt request has occurred. Polarity selection bit 0: Interrupt request bit is set to "1" at "H" level when level sense is selected; this bit is set to "1" at falling edge when edge sense is selected. 1: Interrupt request bit is set to "1" at "L" level when level sense is selected; this bit is set to "1" at rising edge when level sense is selected. 4 5 Functions b2b1b0 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Level sense/Edge sense selection bit 0: Edge sense 1: Level sense 6 Not implemented. 7 At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW Undefined -- Note: The interrupt request bits of INT0 to INT2/Key input interrupts are ignored when the level sense is selected. Fig. 4.3.2 Interrupt control registers' structures 7733 Group User's Manual 4-7 INTERRUPTS 4.3 Interrupt control 4.3.1 Interrupt disable flag (I) This flag can disable all maskable interrupts. When this flag is set to "1," all maskable interrupts are disabled; when this flag is cleared to "0," all maskable interrupts are enabled. Because this flag is set to "1" at reset, clear this flag to "0" when enabling interrupts. This flag is allocated to the processor status register (PS). 4.3.2 Interrupt request bit When an interrupt request occurs, this bit is set to "1." And then, this bit remains set to "1" until the interrupt request is accepted; this bit is cleared to "0" when the interrupt request is accepted. This bit can be set____ to "1" or cleared to "0" by software, also. ____ Note that when an INT i interrupt is used with the level sense selected, the INTi interrupt request bit (i = 0 to 2) is ignored. 4.3.3 Interrupt priority level selection bits and Processor interrupt priority level (IPL) The interrupt priority level selection bits are used to set the priority level of an interrupt. When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority level (IPL). Only when the comparison result satisfies the following relationship, the interrupt request is enabled. Therefore, by setting the interrupt priority level to 0, the interrupt can be disabled. The processor interrupt priority level (IPL) is allocated to the processor status register (PS). Interrupt priority level > Processor interrupt priority level (IPL) Table 4.3.1 lists the settings of interrupt priority levels. Table 4.3.2 lists the relationship between the IPL's contents and enabled interrupt priority levels. The interrupt disable flag (I), interrupt request bit, interrupt priority level selection bits, and processor interrupt priority level (IPL) are independent of each other; they do not affect each other. Interrupt requests are accepted only when the following conditions are satisfied. Interrupt disable flag (I) = "0" Interrupt request bit = "1" Interrupt priority level > Processor interrupt priority level (IPL) 4-8 7733 Group User's Manual INTERRUPTS 4.3 Interrupt control Table 4.3.1 Settings of interrupt priority levels Interrupt priority level selection bits Interrupt priority level b2 b1 b0 0 0 0 Level 0 (Interrupt is disabled.) 0 0 1 Level 1 0 0 1 1 0 Level 2 1 Level 3 1 0 0 0 1 Level 4 1 1 1 0 Level 5 Level 6 1 1 1 Level 7 Priority -- Low High Table 4.3.2 Relationship between IPL's contents and enabled interrupt priority levels IPL2 IPL1 IPL0 Enabled interrupt priority levels 0 0 0 Level 1 and above levels 0 0 1 Level 2 and above levels 0 0 1 1 0 1 Level 3 and above levels Level 4 and above levels 1 0 0 Level 5 and above levels 1 0 1 Levels 6 and 7 1 1 0 Level 7 only 1 1 1 All maskable interrupts are IPL 0: IPL 1: IPL2 : disabled. Bit 8 in the processor status register (PS) Bit 9 in the processor status register (PS) Bit 10 in the processor status register (PS) 7733 Group User's Manual 4-9 INTERRUPTS 4.4 Interrupt priority level 4.4 Interrupt priority level When the interrupt disable flag (I) = "0" (in other words, when interrupts are enabled), if multiple interrupt requests reside at the same sampling timing, where the presence of an interrupt request is checked, these requests are accepted in order of priority levels. In this case, an interrupt request which has the highest priority is accepted first. For 16 interrupt sources other than software interrupts (the zero division and BRK instruction) and a watchdog timer interrupt, an arbitrary priority level can be set by specifying the interrupt priority level selection bits. Note that the priority level for reset (handled as an interrupt which has the highest priority) or a watchdog timer interrupt is set by hardware. Figure 4.4.1 shows the interrupt priority level set by hardware. Note that software interrupts are not affected by the interrupt priority level. When the zero division or BRK instruction is executed, a program branches to an interrupt routine. Reset Watchdog timer interrupt 16 interrupt sources other than software interrupts and watchdog timer interrupt Inside of dotted-line, an arbitrary priority level can be set. High Interrupt priority level Fig. 4.4.1 Interrupt priority level set by hardware 4-10 7733 Group User's Manual Low INTERRUPTS 4.5 Interrupt priority level detection circuit 4.5 Interrupt priority level detection circuit The interrupt priority level detection circuit is used to select an interrupt with the highest priority from multiple interrupts which reside at the same sampling timing. Figure 4.5.1 shows the interrupt priority level detection circuit. Interrupt priority level of each interrupt Level 0 (Initial value) Interrupt priority level of each interrupt Timer A4 A-D/UART2 trans. /rece. UART1 transmission Timer A3 UART1 reception Timer A2 UART0 transmission Timer A1 UART0 reception Timer A0 Timer B2 INT2/Key input Timer B1 INT 1 Timer B0 INT 0 Interrupt with the highest priority IPL Processor interrupt priority level Interrupt disable flag (I) Watchdog timer interrupt Interrupt request is accepted. Reset Fig. 4.5.1 Interrupt priority level detection circuit 7733 Group User's Manual 4-11 INTERRUPTS 4.5 Interrupt priority level detection circuit Figure 4.5.2 shows the operation of the interrupt priority detection circuit. The interrupt priority level of a requested interrupt ("Y" in Figure 4.5.2) is compared with the priority level which is sent from the preceding comparator ("X" in Figure 4.5.2), and then the interrupt with the higher priority level is sent to the next comparator ("Z" in Figure 4.5.2). (Initial value of "X" is "0.") For an interrupt which is not requested, the comparison is not performed and the priority level which is sent from the preceding comparator is forwarded to the next comparator as it is. After comparison, if the two priority levels are the same, the priority level which is sent from the preceding comparator is forwarded to the next comparator. Therefore, if the same priority is set by software, the interrupt priority levels are handled as follows: A-D conversion > UART2 transmission/reception > UART1 transmission > UART1 reception > UART0 transmission > UART0 reception > Timer B2 > Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > ____ ____ ____ Timer A0 > INT 2/Key input > INT 1 > INT 0 By the above comparison, among the multiple interrupt requests which reside at the same sampling timing, one request with the highest priority level is detected. And then, the highest priority level detected by the above comparison is compared with the processor interrupt priority level (IPL). When this interrupt priority level is higher than the processor interrupt priority level (IPL) and the interrupt disable flag (I) = "0," the corresponding interrupt request is accepted. An interrupt request which is not accepted at this time is held until it is accepted or the corresponding interrupt request bit is cleared to "0" by software (CLB instruction). The interrupt priority level is detected synchronously with the CPU's op-code fetch cycle. However, when an op-code fetch cycle starts during the interrupt priority detection, a new interrupt priority detection does not start. (Refer to "Figure 4.6.1") Because the interrupt request bit's state and interrupt priority level are latched during interrupt priority detection, if they change, the interrupt priority detection is performed for the previous state before the change occurred. X Y Time Interrupt source Y Comparison of priority level Comparator X : Priority level which is sent from the preceding comparator (Highest priority at this time) Y : Priority level of interrupt source Y Z : Highest priority at this time Z When X Y, Z = X When X < Y, Z = Y Fig. 4.5.2 Interrupt priority level detection model 4-12 7733 Group User's Manual INTERRUPTS 4.6 Interrupt priority level detection time 4.6 Interrupt priority level detection time When the interrupt priority level detection time has passed after sampling starts, an interrupt request is accepted. The interrupt priority level detection time can be selected by software. Figure 4.6.1 shows the interrupt priority level detection time. Usually, select "2 cycles of " as the interrupt priority level detection time. (1) Interrupt priority detection time selection bits b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 0 (address 5E 16) 0 Processor mode bits Wait bit Software reset bit b5, b4 Interrupt priority detection time selection bits 00 7 cycles of clock 01 4 cycles of clock [(b) shown below] 10 2 cycles of clock [(c) shown below] 11 Do not select. [(a) shown below] Must be fixed to "0." Clock 1 output selection bit (2) Interrupt priority level detection time Op-code fetch cycle (Note) Sampling pulse (a) 7 cycles Interrupt priority level detection time (b) 4 cycles (c) 2 cycles Note: This pulse resides when "2 cycles of " is selected. Fig. 4.6.1 Interrupt priority level detection time 7733 Group User's Manual 4-13 INTERRUPTS 4.7 How interrupts are processed 4.7 How interrupts are processed (from acceptance of interrupt request until execution of interrupt routine) How interrupts are processed from accepting of an interrupt request until execution of the interrupt routine is described below. When an interrupt request is accepted, the interrupt request bit which corresponds to the accepted interrupt is cleared to "0." And then, execution of an interrupt routine begins at the cycle immediately after the instruction execution which was in progress at acceptance of the interrupt request is completed. Figure 4.7.1 shows how interrupts are processed from acceptance of an interrupt request until execution of the interrupt routine. When the instruction execution which was in progress at acceptance of the interrupt request is completed, the INTACK (Interrupt acknowledge) sequence is executed and the program branches to the start address of the interrupt routine allocated in addresses 016 to FFFF 16. In the INTACK sequence, the following procedure is automatically performed in this order. The contents of the program bank register (PG) immediately before the INTACK sequence is pushed onto the stack. The contents of the program counter (PC) immediately before the INTACK sequence is pushed onto the stack. The contents of the processor status register (PS) immediately before the INTACK sequence is pushed onto the stack. The interrupt disable flag (I) is set to "1." The interrupt priority level of the accepted interrupt is set to IPL. The contents of the program bank register (PG) is cleared to "0016" and the contents of the interrupt vector address is set into the program counter (PC). The INTACK sequence requires at least 13 cycles of . Figure 4.7.2 shows the INTACK sequence's timing. After the INTACK sequence is completed, the instruction execution begins at the start address of an interrupt routine. Interrupt request is accepted. Interrupt request is generated. @ @ Instruction Instruction 1 2 INTACK sequence Time Instructions in interrupt routine Interrupt response time @ : Interrupt priority level detection time Time from when an interrupt request occurs until the instruction execution which is in progress at that time is completed. Time from when execution of an instruction next to begins (Note) until the instruction execution which is in progress at completion of interrupt priority level detection. Note : At this time, detection of interrupt priority level begins. at the shortest) Time required to execute the INTACK sequence (13 cycles of Fig. 4.7.1 How interrupts are processed from acceptance of interrupt request until execution of interrupt routine 4-14 7733 Group User's Manual INTERRUPTS 4.7 How interrupts are processed When stack pointer (S)'s contens is even CPU AP PG 00 00 AH PCH 00 [S]H AL PCL 00 [S]L DH FF16 DL 16 00 00 00 ([S]-1)H ([S]-2)H ([S]-3)H ([S]-4)H ([S]-5)H ([S]-5)H FF16 ADH ([S]-1)L ([S]-2)L ([S]-3)L ([S]-4)L ([S]-5)L ([S]-5)L 16 ADL PG 00 00 00 00 00 PCH PSH ADH Op-code PCL PSL ADL Op-code Interrupt disable flag (I) INTACK sequence CPU: CPU's standard clock AP : High-order 8 bits of CPU address bus AH : Middle-order 8 bits of CPU address bus AL : Low-order 8 bits of CPU address bus DH : Data bus for CPU's odd address DL : Data bus for CPU's even address : Not used [S] : Contents of stack pointer (S) 16 : Low-order 8 bits of vector address ADH : Contents of vector address (High-order address) ADL : Contents of vector address (Low-order address) Fig. 4.7.2 INTACK sequence's timing 4.7.1 Change in IPL at acceptance of interrupt request When an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set to the processor interrupt priority level (IPL). This operation makes the processing for multiple interrupts easy. (Refer to section "4.9 Multiple interrupts." At reset or when a watchdog timer interrupt or software interrupt is accepted, a value listed in Table 4.7.1 is set into IPL. Table 4.7.1 Change in IPL at acceptance of interrupt request Change in IPL Interrupt source Reset Level 0 (000 2) is set. Watchdog timer interrupt Level 7 (111 2) is set. Zero division interrupt Not changed BRK instruction interrupt Not changed Other interrupts Accepted interrupt's priority level is set. 7733 Group User's Manual 4-15 INTERRUPTS 4.7 How interrupts are processed 4.7.2 How to push registers The way to push registers depends on whether the stack pointer (S)'s contents at interrupt request acceptance is even or odd. When the stack pointer (S)'s contents is even, each of the program counter (PC)'s contents and processor status register (PS)'s contents is simultaneously pushed by the 16 bits. When the stack pointer (S)'s contents is odd, each of these registers is pushed by the 8 bits. Figure 4.7.3 shows how the registers are pushed. In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and processor status register (PS) are pushed onto the stack area. Make sure to push other necessary registers by software at the beginning of an interrupt routine. By executing the PSH instruction, all CPU registers other than the stack pointer can be pushed. (1) When stack pointer (S)'s contents is even Address S-5 (odd) Order for push S-4 (even) Processor status register's low-order byte (PS L ) S-3 (odd) Processor status register's high-order byte (PS H ) S-2 (even) Program counter's low-order byte (PC L ) Pushes 16 bits at a time. Pushes 16 bits at a time. S-1 (odd) Program counter's high-order byte (PC H ) S (even) Program bank register (PG) Pushed in 3 times (2) Stack Pointer (S)'s contents is odd Address Order for push S-5 (even) S-4 (odd) Processor status register's low-order byte (PS L ) S-3 (even) Processor status register's high-order byte (PS H ) S-2 (odd) Program counter's low-order byte (PC L) S-1 (even) Program counter's high-order byte (PC H ) S (odd) Program bank register (PG) Pushes by the 8 bits. Pushed in 5 times "S" is the initial address that the stack pointer (S) indicates when an interrupt request is accepted. S's contents is "S-5" after the above registers are pushed. Fig. 4.7.3. How registers are pushed 4-16 7733 Group User's Manual INTERRUPTS 4.8 Return from interrupt routine, 4.9 Multiple interrupts 4.8 Return from interrupt routine When the RTI instruction is executed at the end of an interrupt routine, the contents of the program bank register (PG), program counter (PC), and processor status register (PS) which were pushed onto the stack area immediately before the INTACK sequence are automatically pulled. And then, a program returns to the original routine and the suspended process is resumed. Before the RTI instruction is executed, by executing the PUL instruction or others, make sure to pull registers which were pushed by software in an interrupt routine. Make sure that the data length and register length for the pull operation are equal to those for the push operation. 4.9 Multiple interrupts When a program branches to an interrupt routine, the following occurs: Interrupt disable flag (I) = "1" (Interrupts are disabled.) Interrupt request bit of accepted interrupt = "0" Processor interrupt priority level (IPL) = Interrupt priority level of accepted interrupt Therefore, as long as the IPL remains unchanged, by clearing the interrupt disable flag (I) to "0" in an interrupt routine, an interrupt request whose priority level is higher than the priority level of the interrupt which is in progress can be accepted. In this way, multiple interrupts are processed. Figure 4.9.1 shows how multiple interrupts are processed. An interrupt request which is not accepted because its priority level is lower is held. When the RTI instruction is executed, the interrupt priority level of the routine which was in progress at acceptance of an interrupt request is pulled to the IPL. Therefore, if the following relationship is satisfied when interrupt priority level detection is performed next, the held interrupt request is accepted. Held interrupt request's priority level > Processor interrupt priority level (IPL) which is pulled 7733 Group User's Manual 4-17 INTERRUPTS 4.9 Multiple interrupts Interrupt request generated Time Reset Nesting Main routine I=1 IPL = 0 Interrupt 1 I=0 Interrupt priority level = 3 Interrupt 1 I=1 IPL = 3 Interrupt 2 Multiple interrupts I=0 Interrupt priority level = 5 Interrupt 2 I=1 IPL = 5 Interrupt 3 RTI Interrupt priority level = 2 I=0 IPL = 3 Interrupt 3 RTI I=0 Cannot be accepted because its priority level is low. IPL = 0 Interrupt 3 Instruction in main routine is not executed. I=1 IPL = 2 RTI I=0 IPL = 0 I : Interrupt disable flag IPL : Processor interrupt priority level : Automatically be set. : Must be set by software. Fig. 4.9.1 How multiple interrupts are processed 4-18 7733 Group User's Manual INTERRUPTS ____ 4.10 External interrupts (INT i interrupt) ____ 4.10 External interrupts ( INTi interrupt) ____ An external interrupt request occurs by input signal from pin INT i (i = 0 to 2). The occurrence condition of an external interrupt request can be selected by the level sense/edge sense selection bit and the polarity selection bit (bits 5 and____ 4 at addresses 7D 16 to 7F 16 ) shown in Figure 4.10.2. Table 4.10.1 lists the occurrence condition of INT i interrupt request. ____ ____ When using pins P62/INT0 to P64/INT2 as external interrupt input pins, set their corresponding bits at address 10 16 (Port P6 direction register) to "0." (Refer to "Figure 4.10.1.") These pins can be pulled high by ____ ____ software. (Refer to section "3.3 Pull-up function of P6 2 to P6 4 pins ( INT 0 to INT 2)." ____ The INT2 interrupt is invalid when the key input interrupt selection bit (bit 7 at address 6D16) = "1." (Refer ____ to chapter "5 KEY INPUT INTERRUPT FUNCTION.") When using the INT2 interrupt function, clear the key input interrupt selection bit to "0." ____ A signal which is input to pin INT i requires a "H"/"L"-level duration of 250 ns or more independent of the system clock frequency (Note 1). ____ ____ Note that even when pins P6 2 / INT0 to P6 4/ INT2 are used as external interrupt input pins, these pins' state can be read in by reading bits 2 to 4 at address E 16 (Port P6 register). Note 1: When the falling edge or "L" level is selected as the interrupt occurrence condition, make sure that "L"-level duration must be at least 250 ns: when the rising edge or "H" level is selected as the interrupt occurrence condition, make sure that "H"-level duration must be at least 250 ns. ____ Table 4.10.1 Occurrence condition of INTi interrupt request ____ b5 (Note 2) b4 (Note 2) INTi interrupt request occurrence condition ____ 0 0 Occurs at the falling edge of an input signal to pin INT i (Edge sense). ____ 0 1 Occurs at the rising edge of an input signal to pin INTi (Edge sense). ____ 1 0 Occurs when pin INT i is at "H" level (Level sense). ____ 1 1 Occurs when pin INT i is at "L" level (Level sense). ____ ____ Note 2: "b5" and "b4" represent bits 5 and 4 of the INT0 to INT 2/key input interrupt control register. (Refer to "Figure 4.10.2.") ____ ____ In an INTi interrupt, pin INTi's state is always ____ checked, and then an interrupt request is generated ____ according to the state. Therefore, when an INT i interrupt is not used, clear the INT i interrupt's priority level to "0." 7733 Group User's Manual 4-19 INTERRUPTS ____ 4.10 External interrupts (INTi interrupt) b7 b6 b5 b4 b3 b2 b1 b0 Port P6 direction register (address 10 16) Bit Corresponding pin's name 0 Pin TA4 OUT 1 Pin TA4 IN 2 Pin INT0 3 Functions At reset RW 0 RW 0 RW 0 RW Pin INT1 0 RW 4 Pin INT2/Key input 0 RW 5 Pin TB0 IN 0 RW 6 Pin TB1 IN 0 RW 7 Pin TB2 IN 0 RW 0 : Input mode 1 : Output mode When using a pin as an input pin for an external interrupt, clear the corresponding bit to "0." represents that bits 0, 1 and bits 5 to 7 are not used for external interrupts. Fig. 4.10.1 Correspondence between port P6 direction register and input pins for external interrupts b7 b6 b5 b4 b3 b2 b1 b0 INT0, INT1, and INT2/Key input interrupt control registers (addresses 7D16 to 7F16) Bit Bit name Interrupt priority level 0 selection bits 1 2 3 Functions b2b1b0 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Interrupt request bit (Note) 0: No interrupt request has occurred. 1: Interrupt request has occurred. polarity selection bit 0: Interrupt request bit is set to "1" at "H" level when level sense is selected; this bit is set to "1" at falling edge when edge sense is selected. 1: Interrupt request bit is set to "1" at "L" level when level sense is selected; this bit is set to "1" at rising edge when level sense is selected. 4 Level sense/Edge sense 5 selection bit 0: Edge sense 1: Level sense 6 Not implemented. 7 At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW Undefined -- Note: The interrupt request bits of INT0 to INT2/Key input interrupts are ignored when the level sense is selected. ____ ____ Fig. 4.10.2 INT0 to INT2 interrupt control register's structure 4-20 7733 Group User's Manual INTERRUPTS ____ 4.10 External interrupts (INT i interrupt) ____ 4.10.1 INTi interrupt request bit's function (1) Functions when edge sense is selected By clearing the level sense/edge sense selection bit to "0," the edge sense is selected. (Refer to Figure 4.10.3.) The interrupt request bit has the same functions as those for the interrupt request bit of internal interrupts. When an interrupt occurs, the interrupt request bit is set to "1" and retains this state until the interrupt request is accepted. When the interrupt request bit is cleared to "0" by software, an interrupt request is cancelled; when the interrupt request bit is set to "1" by software, an interrupt request can be generated. (2) Functions when level sense is selected By setting the level sense/edge sense selection bit to "1," the level sense is selected. (Refer to Figure 4.10.3.) ____ The interrupt request bit is ignored. In this case, interrupt requests occur sequentially while pin INT i ____ is at the valid level 1; when pin INTi's level changes to the invalid level 2 with the interrupt request not accepted, the interrupt request is not held. (Refer to Figure 4.10.4.) Valid level1: The level selected by the polarity selection bit (bit 4 at addresses 7D16 to 7F16) Invalid level 2: The reverse level to "valid level" Data bus Edge sense Edge detection circuit Pin INT i Interrupt request bit "0" Level sense/Edge sense selection bit Interrupt request "1" Level sense ____ Fig. 4.10.3 INTi Interrupt request Interrupt request is accepted. Return to main routine Valid Pin INT i's level Invalid Main routine Main routine 1st interrupt routine 2nd interrupt routine 3rd interrupt routine ____ Fig. 4.10.4 Re-occurrence of INTi interrupt request when level sense is selected 7733 Group User's Manual 4-21 INTERRUPTS ____ 4.10 External interrupts (INTi interrupt) ____ 4.10.2 How to switch ____ INTi interrupt request occurrence condition The way to switch the INTi interrupt request occurrence condition from the level sense to the edge sense is shown in Figure 4.10.5 (1). The way to switch the polarity is shown in Figure 4.10.5 (2). (1) How to switch the INTi interrupt request occurrence condition from level sense to edge sense (2) How to switch the polarity Set interrupt priority level to 0. ( INTi interrupt is disabled. ) Set interrupt priority level to 0. ( INTi interrupt is disabled. ) Clear the level sense/edge sense selection bit to "0." ( Edge sense selected ) Set the polarity selection bit. Clear the interrupt request bit to "0." Clear the interrupt request bit to "0." Set the interrupt priority level to one of levels 1 to 7. Set the interrupt priority level to one of levels 1 to 7. ( INTi interrupt request is acceptable. ) ( INT i interrupt request is acceptable. ) ____ Fig. 4.10.5 How to switch INTi interrupt request occurrence condition 4-22 7733 Group User's Manual INTERRUPTS 4.11 Precautions for interrupts 4.11 Precautions for interrupts When the contents of the interrupt priority level selection bits (bits 0 to 2 at addresses 70 16 to 7F 16) is changed, 2 to 7 cycles of are required. Therefore, when the interrupt priority level of the same interrupt source is changed twice or more in a very short time, which consists of a few instructions, it is necessary to secure the required time by software. Figure 4.11.1 shows an program example to secure the time required for the change of an interrupt priority level. Note that the time required for the change depends on the contents of the interrupt priority level selection bits (bits 4 and 5 at address 5E 16). Table 4.11.1 lists the correspondence between the number of instructions inserted in a program example and the interrupt priority level selection bits. (Refer to Figure 4.11.1, also.) : LDM .B #0XH, 007XH NOP NOP NOP LDM .B #0XH, 007XH ; The write instruction for the interrupt priority level selection bits ; The NOP instruction is inserted (Note) ; ; ; The write instruction for the interrupt priority level selection bits Note: Other instructions whose cycle number corresponds to that of the NOP instruction (other than the write instructions for address 7X 16) can be inserted. For number of the NOP instructions which are to be inserted, refer to Table 4.11.1. Fig. 4.11.1 Program example to secure time required for change of interrupt priority level Table 4.11.1 Correspondence between number of instructions to be inserted in Figure 4.11.1 and interrupt priority detection time selection bits Interrupt priority detection time selection bits (Note) Time required for change of Number of inserted NOP instruction interrupt priority level b5 b4 0 0 7 cycles of 4 or more 0 1 4 cycles of 1 0 1 1 2 cycles of Do not select. 2 or more 1 or more Set as follows, if possible: [b5 = "1," b4 = "0"] 7733 Group User's Manual 4-23 INTERRUPTS 4.11 Precautions for interrupts MEMO 4-24 7733 Group User's Manual CHAPTER 5 KEY INPUT INTERRUPT FUNCTION 5.1 Overview 5.2 Block description 5.3 Initial setting example for related registers KEY INPUT INTERRUPT FUNCTION 5.1 Overview The key input interrupt function is used to generate an interrupt request when one of the input levels of four or five pins falls. By using this function when terminating the stop or wait mode, the key-on wakeup can be realized. For the way to terminate the stop or wait mode, refer to section "17.4 Power saving." For the stop and wait modes, refer to chapter "11. STOP AND WAIT MODES." 5.1 Overview ___ ___ A key input interrupt request occurs when one of the input levels of pins KI 0 to KI 3 falls. Therefore, by configuring an external key___ matrix shown in Figure 5.1.1, an interrupt request can be generated only by ___ pushing a key. Pins KI0 to KI3 can be pulled high by software and the same function can also be___ selected ___ for port P64. Therefore, when using the key input interrupt function, whether to use four pins (pins KI0 to KI3) ___ ___ or five pins (pins KI0 to KI3 and____ P64 ) can be selected. The key input interrupt and the INT2 interrupt share the same interrupt vector addresses and interrupt control register. M37733MHBXXXFP Key matrix KI3 KI2 KI1 KI0 P64/INT2 P63 P62 P61 P60 Fig. 5.1.1 Key matrix example when key input interrupt function is used 5-2 7733 Group User's Manual KEY INPUT INTERRUPT FUNCTION 5.2 Block description 5.2 Block description Figure 5.2.1 shows the block diagram for the key input interrupt function. Port P6 pull-up selection bit 1 Port P6 4 direction register P64/INT2 INT2/Key input interrupt control register Port P6 pull-up selection bit 1 When key input interrupt is selected, it is necessary to select edge sense which uses falling edge. Port P5 pull-up selection bit Pull-up transistor Port P5 7 direction register 0 P57/KI3 (address 7F 16) 0 Pull-up transistor 1 P56/KI2 Interrupt control register request 1 Pull-up transistor INT2/Key input interrupt Key input interrupt selection bit P55/KI1 Pull-up transistor P54/KI0 Fig. 5.2.1 Block diagram for key input interrupt function ___ ___ ____ 5.2.1 Pins KI 0 to KI3 and P6 4 /INT 2 When the___ key input interrupt function is selected, pins P5 4 to P5 7 become input pins for the key input ___ interrupt (KI 0 to KI 3). When selecting the key input interrupt function, clear all of bits 4 to 7 at address D16 (Port P5 direction register) to "0." ___ ___ When bits 4 to 7 at address B16 (Port P5 register) are read out, the status of pins KI0 to KI3 can be read ____ in. When using pin P64/ INT2 as an input pin for the key input interrupt, set both of bits 5 and 7 at address 6D16 to "1" and bit 4 at address 1016 (Port P6 ____ direction register) to "0." When bit 4 at address E616 (Port P6 register) is read out, the status of pin P64/ INT 2 can be read in. b7 b6 b5 b4 0 0 0 0 b3 b2 b1 b0 Port P5 direction register (address D 16) 0: Must be set to "0." b7 b6 b5 b4 b3 b2 0 b1 b0 Port P6 direction register (address 10 16) 0: Must be set to "0." Fig. 5.2.2 Port P5 and P6 direction registers when key input interrupt function is selected 7733 Group User's Manual 5-3 KEY INPUT INTERRUPT FUNCTION 5.2 Block description 5.2.2 Port function control register Figure 5.2.3 shows the structure of the port function control register. b7 b6 b5 b4 0 b3 b2 b1 b0 Port function control register (address 6D 16) Bit 0 1 Bit name Standby state selection bit Functions 0: Pins P0 to P3 are used for the external bus output. 1: Pins P0 to P3 are used for the port output. Sub-clock output selection bit/ *Port-XC selection bit = "0" (when the sub clock is not used) Timer B2 clock source selection Timer B2 (event counter mode) bit clock source selection (Note 1) 0: TB2IN input (event counter mode) 1: Main clock divided by 32 (clock timer) *Port-XC selection bit = "1" (when the sub clock is used) Sub-clock output selection 0: Pin P6 7/TB2 IN/ f SUB functions as a programmable I/O port. 1: Sub clock f SUB is output from pin P6 7/TB2IN/f SUB. At reset RW 0 RW 0 RW 2 Timer B1 internal connect selection bit (Note 2) 0: No internal connection 1: Internal connection with timer B2 0 RW 3 Port P6 pull-up selection bit 0 0: No pull-up for pins P6 2/INT0 and P63/INT1 1: With pull-up for pins P6 2/INT0 and P63/INT1 0 RW 4 Must be fixed to "0." 0 RW 5 Port P6 pull-up selection bit 1 *Key input interrupt selection bit = "0" 0: No pull-up for pin P6 4/INT2 1: With pull-up for pin P6 4/INT2 *Key input interrupt selection bit = "1" 0: Pin P6 4/INT2 is a port with no pull-up. 1: Pin P6 4/INT2 is an input pin with pull-up and is used for the key input interrupt. 0 RW 6 Port P5 pull-up selection bit 0: No pull-up for pins P5 4/TA2OUT/KI0 to P57/TA3IN/KI3 1: With pull-up for pins P5 4/TA2OUT/KI0 to P57/TA3IN/KI3 0 RW 7 Key input interrupt selection bit 0: INT 2 interrupt 1: Key input interrupt 0 RW Port-Xc selection bit : Bit 4 of the oscillation circuit control register 0 (address 6C 16) Notes 1: When the port-Xc selection bit = "0" and timer B2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: When timer B1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 to 4 are not used for the key input interrupt function. Fig. 5.2.3 Structure of port function control register 5-4 7733 Group User's Manual KEY INPUT INTERRUPT FUNCTION 5.2 Block description (1) Port P6 pull-up selection bit (bit 5) ____ When using pin P64/ INT 2 as an input pin for the key input interrupt, set this bit to "1." When this bit ____ is set to "1," pin P64 / INT 2 is pulled high. (2) Port P5 pull-up selection bit ___ (bit 6) ___ This is a bit to pull pins KI0 to KI 3 high. When configuring a key matrix,___ there ___ is no need to connect pull-up transistors externally if this bit is set to "1," in other words, if pins KI0 to KI3 are set to be pulled high. (3) Key input interrupt selection bit (bit 7) This is a bit to select the key input interrupt function. ____ The key input interrupt and the INT2 interrupt share the same interrupt vector addresses and interrupt control register. When this bit is set to "1," the key input interrupt function is selected. When this bit ____ = "1" and ____ bit 5 (Port P6 pull-up selection bit) = "0," pin P6 4/ INT 2 is a programmable I/O port. (At this time, the INT2 interrupt cannot be used.) When both of this bit and bit 5 (Port P6 pull-up selection bit ____ 1) are "1," pin P6 4/ INT2 can be used for the key input interrupt. 7733 Group User's Manual 5-5 KEY INPUT INTERRUPT FUNCTION 5.2 Block description 5.2.3 Interrupt function ____ The key input interrupt and the INT 2 interrupt share the same interrupt vector addresses and interrupt ____ control register. Specify addresses FFF016 and FFF116 (in other words, the vector addresses for the INT2/ ____ key input interrupt) as the interrupt vector addresses; specify the INT 2/key input interrupt control register ____ (address 7F 16 ) as the interrupt control register. Figure 5.2.4 shows the structure of the INT 2 /key input interrupt control register when the key input interrupt function is selected. ____ The operation at accepting a key input interrupt request is the same as that at accepting an INT2 interrupt request. b7 b6 b5 b4 0 0 b3 b2 b1 b0 INT2/key input interrupt control register (address 7F Bit 0 Bit name Interrupt priority level selection bits 1 2 3 Interrupt request bit 4 Must be fixed to "0." Functions At reset RW 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 0 RW 0 RW 0 RW 0: No interrupt request has occurred. 1: Interrupt request has occurred. 0 RW 0 RW 0 RW Undefined - Undefined - b2 b1 b0 5 6 16) Not implemented. 7 ____ Fig. 5.2.4 Structure of INT2/key input interrupt control register when key input interrupt function is selected 5-6 7733 Group User's Manual KEY INPUT INTERRUPT FUNCTION 5.3 Initial setting example for related registers 5.3 Initial setting example for related registers Figure 5.3.1 shows an initial setting example for registers related to the key input interrupt function. Selection of the key input interrupt function Pull-up selection for pins KI0 to KI3 b7 1 b0 0 Port function control register (address 6D 16) Port P6 pull-up selection bit 1 0: Port P6 4 is a programmable I/O port with no pull-up. 1: Port P6 4 is an input pin with pull-up and is used for the key input interrupt. Port P5 pull-up selection bit 0: No pull-up 1: Pull-up Selection of the key input interrupt function Setting of interrupt priority level b7 b0 0 0 0 INT2/Key input interrupt control register (address 7F 16) Interrupt priority level selection bits One of levels 1 to 7 must be set. Interrupt request bit Setting of port P5 and P6 direction registers b7 b0 0 0 0 0 Port P5 direction register (address D 16) P54 to P57 are set to the input mode. (Must be set to "0000.") b7 b0 0 Port P6 direction register (address 10 16) When setting P6 4 as an input pin for the key input interrupt, set this bit to "0." In order to enable the key input interrupt, the interrupt disable flag (I) must be set to "0" and the processor interrupt priority level (IPL) must be a value smaller than the INT 2/key input interrupt's priority level. (Refer to chapter "4. INTERRUPTS." ) Fig. 5.3.1 Initial setting example for registers related to key input interrupt function 7733 Group User's Manual 5-7 KEY INPUT INTERRUPT FUNCTION 5.3 Initial setting example for related registers MEMO 5-8 7733 Group User's Manual CHAPTER 6 TIMER A 6.1 6.2 6.3 6.4 6.5 6.6 Overview Block description Timer mode Event counter mode One-shot pulse mode Pulse width modulation (PWM) mode TIMER A 6.1 Overview 6.1 Overview Timer has a Timer to A4 A is used mainly for output to the external. It consists of five counters (Timers A0 to A4), and each 16-bit reload function. Timers A0 to A4 operate independently of each other. Ai (i = 0 to 4) has four operating modes listed below. Except for the event counter mode, timers A0 all have the same functions. Timer mode Timer A counts a count source internally generated, and the following functions can be used: Gate function Pulse output function Event counter mode Timer A counts an external signal, and the following functions can be used: Free-run count function (Timers A2, A3, and A4) Pulse output function Two-phase pulse signal processing function (Timers A2, A3, and A4) One-shot pulse mode Timer A outputs a pulse which has an arbitrary width once. Pulse width modulation (PWM) mode Timer A outputs pulses which have an arbitrary width in succession and functions as one of the following pulse width modulators: 16-bit pulse width modulator 8-bit pulse width modulator 6-2 7733 Group User's Manual TIMER A 6.2 Block description 6.2 Block description Figure 6.2.1 shows the timer A block diagram. Registers related to timer A are described below. f2 Clock source selection Data bus (Odd) f 16 f 64 Data bus (Even) f 512 (Low-order 8 bits) *Timer mode *One-shot pulse mode *PWM mode Timer Ai reload register (16) Timer mode (Gate function) TAiIN (i = 0 to 4) Polarity switching (High-order 8 bits) Timer Ai counter (16) Event counter mode Count start flag (address 4016 ) External trigger Countdown Countup/Countdown switching "Countdown" is selected when not in the event counter mode. Timer Ai interrupt request bit TimerA0 TimerA1 TimerA2 TimerA3 TimerA4 addresses 4716 46 16 4916 48 16 4B16 4A16 4D16 4C16 4F16 4E16 Up-down flag (address 4416 ) Pulse output function selection bit TAiOUT (i = 0 to 4) Clocks f2, f16, f64, and f512:Refer Toggle F.F. to chapter "14. CLOCK GENERATING CIRCUIT." Fig. 6.2.1 Timer A block diagram 7733 Group User's Manual 6-3 TIMER A 6.2 Block description 6.2.1 Counter and reload register (Timer Ai register) Each of timer Ai counter and its reload register consists of 16 bits. The counter performs countdown each time a count source is input. In the event counter mode, it can also function as an up-counter. The reload register is used to memorize the initial value of a counter. When an underflow/overflow occurs in the counter, the reload register's contents is reloaded into the counter. However, when the free-run count function is used, the reload register's contents is not reloaded into the counter. Values are set to the counter and reload register by writing the values to the timer Ai register. Table 6.2.1 lists the memory allocation of the timer Ai register. A value written into the timer Ai register while counting is stopped is set to the counter and reload register. A value written into the timer Ai register while counting is in progress is set only to the reload register. In this case, the reload register's updated contents is transferred to the counter at the next reload time. A value obtained by reading out the timer Ai register depends on the operating mode. Table 6.2.2 lists reading and writing from and to the timer Ai register. Table 6.2.1 Memory allocation of timer Ai register Timer Ai register High-order byte Low-order byte Timer A0 register Timer A1 register Address 4716 Address 4916 Address 4616 Address 4816 Timer A2 register Address 4B 16 Address 4A 16 Timer A3 register Address 4D 16 Address 4C16 Timer A4 register Address 4F16 Address 4E 16 Note: At reset, the contents of the timer Ai register is undefined. Table 6.2.2 Reading and writing from and to timer Ai register Operating mode Timer mode Event counter mode One-shot pulse mode Pulse width modulation (PWM) mode Read Write Counter value is read out. (Note 1) <While counting is in progress> Written only to the reload register. Undefined value is read out. <While counting is stopped> Written to both of the counter and reload register. Notes 1: Also refer to "Precautions in timer mode" and "Precautions in event counter mode." 2: Perform reading or writing by the 16 bits. 6-4 7733 Group User's Manual TIMER A 6.2 Block description 6.2.2 Count start flag This register is used to start or stop counting. Each bit of this register corresponds to each timer, respectively. Figure 6.2.2 shows the structure of the count start flag. b7 b6 b5 b4 b3 b2 b1 b0 Count start flag (address 4016) Bit Bit name Functions At reset RW 0 RW 0 RW 0 Timer A0 count start flag 1 Timer A1 count start flag 2 Timer A2 count start flag 0 RW 3 Timer A3 count start flag 0 RW 4 Timer A4 count start flag 0 RW 5 Timer B0 count start flag 0 RW 6 Timer B1 count start flag 0 RW 7 Timer B2 count start flag 0 RW 0: Counting is stopped. 1: Counting is started. represents that bits 7 to 5 are not used for timer A. Fig. 6.2.2 Structure of count start flag 7733 Group User's Manual 6-5 TIMER A 6.2 Block description 6.2.3 Timer Ai mode register Figure 6.2.3 shows the structure of the timer Ai mode register. The operating mode selection bits are used to select an operating mode of timer Ai. Bits 7 to 2 have different functions according to the operating mode. These bits are described in a section of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) Bit Functions At reset RW 0 0: Timer mode 0 1: Event counter mode 1 0: One-shot pulse mode 1 1: Pulse width modulation (PWM) mode 0 RW 0 RW 0 RW 3 0 RW 4 0 RW 5 0 RW 6 0 RW 7 0 RW 0 Bit name Operating mode selection bits 1 2 b1 b0 These bits have different functions according to the operating mode. Fig. 6.2.3 Structure of timer Ai mode register 6-6 7733 Group User's Manual TIMER A 6.2 Block description 6.2.4 Timer Ai interrupt control register Figure 6.2.4 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer to chapter "4. INTERRUPTS." b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai interrupt control register (i = 0 to 4) (addresses 7516 to 7916) Bit 0 Bit name Interrupt priority level selection bits Functions b2 b1 b0 1 2 3 7 to 4 Interrupt request bit Not implemented. 0 0 0: Level 0 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 (Interrupt is disabled.) Priority is low. Priority is high. 0: No interrupt request has occurred. 1: Interrupt request has occurred. At reset RW 0 RW 0 RW 0 RW 0 RW Undefined - Fig. 6.2.4 Structure of timer Ai interrupt control register (1) Interrupt priority level selection bits (bits 2 to 0) These bits select a timer Ai interrupt's priority level. When using timer Ai interrupts, select one priority level from levels 1 to 7. If a timer Ai interrupt request is generated, its priority level is compared with the processor interrupt priority level (IPL), and then the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this is applied when the interrupt disable flag (I) = "0.") When disabling timer Ai interrupts, set these bits to "0002" (Level 0). (2) Interrupt request bit (bit 3) This bit is set to "1" when a timer Ai interrupt request is generated. This bit is automatically cleared to "0" when the timer Ai interrupt request is accepted. This bit can be set to "1" or cleared to "0" by software. 7733 Group User's Manual 6-7 TIMER A 6.2 Block description 6.2.5 Port P5 and port P6 direction registers I/O pins of timers A0 to A3 are multiplexed with port P5, and I/O pins of timer A4 are multiplexed with port P6. When using these pins as timer Ai's input pins, set the corresponding bits of the port P5 and port P6 direction registers to "0" in order to set these ports for the input mode. When using these pins as timer Ai's output pins, these pins are forcibly set to output pins of timer Ai independent of the direction registers' contents. Figure 6.2.5 shows the relationship between the port P5 and port P6 direction registers and the timer Ai's I/O pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (address D16) Bit b7 b6 b5 b4 b3 b2 b1 Corresponding pin name 0 Pin P50/TA0OUT 1 Pin P51/TA0IN Functions 0: Input mode 1: Output mode When using these pins as timer Ai's input pins, set the corresponding bits to "0." At reset RW 0 RW 0 RW 0 RW 0 RW 2 Pin P52/TA1OUT 3 Pin P53/TA1IN 4 Pin P54/TA2OUT 0 RW 5 Pin P55/TA2IN 0 RW 6 Pin P56/TA3OUT 0 RW 7 Pin P57/TA3IN 0 RW At reset RW 0: Input mode 1: Output mode 0 RW 0 RW When using these pins as timer Ai's input pins, set the corresponding bits to "0." 0 RW 0 RW 0 RW b0 Port P6 direction register (address 1016) Bit Corresponding pin name 0 Pin P60/TA4OUT 1 Pin P61/TA4IN Functions 2 Pin P62/INT0 3 Pin P63/INT1 4 Pin P64/INT2 5 Pin P65/TB0IN 0 RW 6 Pin P66/TB1IN 0 RW 7 Pin P67/TB2IN/f 0 RW SUB represents that bits 2 to 7 are not used for timer A. Fig. 6.2.5 Relationship between port P5 and port P6 direction registers and timer Ai's I/O pins 6-8 7733 Group User's Manual TIMER A 6.3 Timer mode 6.3 Timer mode (Bits 1 and 0 of timer Ai mode register = "00 2") In this mode, a count source internally generated is counted. (Refer to Table 6.3.1.) Figure 6.3.1 shows the structures of the timer Ai mode register and timer Ai register in the timer mode. Table 6.3.1 Specifications of timer mode Item Count source Clock f 2, f 16, f64 , or f 512 Specifications Count operation Countdown Division ratio At an underflow, the reload register's contents is reloaded, and counting is continued. 1 (n + 1) Count start condition n: Set value in the timer Ai register When the count start flag is set to "1." When the count start flag is cleared to "0." Interrupt request occurrence timing At an underflow Programmable I/O port or gate input Pin TAi IN's function Programmable I/O port or pulse output Pin TAi OUT's function Count stop condition Read from timer Write to timer A counter value can be read out by reading the timer Ai register. While counting is stopped When a value is written to the timer Ai register, it is written to both of the reload register and counter. While counting is in progress When a value is written to the timer Ai register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Clocks f 2 , f16, f 64, and f 512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." 7733 Group User's Manual 6-9 TIMER A 6.3 Timer mode b7 b6 b5 b4 b3 0 b2 b1 b0 0 0 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) Bit 0 Bit name Functions Operating mode selection bits b1 b0 0 0: Timer mode 1 0: No pulse is output. (Pin TAiOUT functions as a programmable I/O port.) 1: Pulse is output. (Pin TAiOUT functions as a pulse output pin.) 2 Pulse output function selection bit 3 Gate function selection bits 0 X: No gate function (Pin TAiIN functions as a programmable I/O port.) 1 0: Counter counts only while pin TAiIN's input signal level is "L." 1 1: Counter counts only while pin TAiIN's input signal level is "H." At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW At reset RW Undefined RW b4 b3 4 5 6 Must be fixed to "0" in the timer mode. Count source selection bits 7 b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Bit Functions 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Fig. 6.3.1 Structures of timer Ai mode register and timer Ai register in timer mode 6-10 7733 Group User's Manual TIMER A 6.3 Timer mode 6.3.1 Setting for timer mode Figures 6.3.2 and 6.3.3 show an initial setting example for registers related to the timer mode. Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter "4. INTERRUPTS." Selection of the timer mode and each function b7 b0 0 0 0 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) Timer mode is selected. Pulse output function selection bit 0: No pulse is output. 1: Pulse is output. Gate function selection bits b4 b3 0 X: No gate function 1 0: Counter counts only while pin TAiIN's input signal level is "L." 1 1: Counter counts only while pin TAiIN's input signal level is "H." Count source selection bits b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 X: It may be either "0" or "1." Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Setting of the division ratio (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Values 000016 to FFFF16 (n) can be set. Counter divides the count source frequency by (n + 1). Continued to "Initial setting example for registers related to timer mode (2)" on the next page Fig. 6.3.2 Initial setting example for registers related to timer mode (1) 7733 Group User's Manual 6-11 TIMER A 6.3 Timer mode Continued from "Initial setting example for registers related to timer mode (1)" on the preceding page Setting of the interrupt priority level b7 b0 Timer Ai interrupt control register (addresses 7516 to 7916) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Setting of the port P5 and port P6 direction registers b7 b0 Port P5 direction register (address D16) Pin TA0IN Pin TA1IN Pin TA2IN Pin TA3IN b7 b0 Port P6 direction register (address 1016) Pin TA4IN When the gate function is selected, set the bit corresponding to pin TAiIN to "0." Setting of the count start flag to "1." b7 b0 Count start flag (address 4016) Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag AAAA AAAA AAAA Timer A4 count start flag Counting is started. Fig. 6.3.3 Initial setting example for registers related to timer mode (2) 6-12 7733 Group User's Manual TIMER A 6.3 Timer mode 6.3.2 Count source In the timer mode, by the count source selection bits (bits 6 and 7 at addresses 5616 to 5A 16), a count source can be selected. Table 6.3.2 lists the relationship between the count source selection bits and count source. Table 6.3.2 Relationship between count source selection bits and count source b7 b6 Count source Frequency of count source When system clock = 25 MHz 0 0 f2 0 1 f16 12.5 MHz 1.5625 MHz 1 0 f64 390.625 kHz When system clock = 16 MHz 8 MHz When system clock = 8 MHz 4 MHz 500 kHz 1 MHz 125 kHz 250 kHz f512 1 1 48.8281 kHz 31.25 kHz 15.625 kHz Clocks f 2 , f16, f 64, f 512, and system clock: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: This is applied when the system clock selection bit (bit 3 at address 6C16) = "0" and the main clock division selection bit (bit 0 at address 6F16) = "0." (For details, refer to chapter "14. CLOCK GENERATING CIRCUIT.") 7733 Group User's Manual 6-13 TIMER A 6.3 Timer mode 6.3.3 Operation in timer mode When the count start flag is set to "1," the counter starts counting of the count source. When an underflow occurs, the reload register's contents is reloaded, and then counting is continued. The timer Ai interrupt request bit is set to "1" when the underflow occurs in . After this, the interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Figure 6.3.4 shows an operation example in the timer mode. n = Reload register's contents Counter contents (Hex.) FFFF16 Counting is started. 1 / fi (n + 1) Counting is stopped. n Counting is restarted. 000016 Time Set to "1" by software Count start flag Cleared to "0" by software Set to "1" by software "1" "0" Timer Ai interrupt "1" request bit "0" fi = Frequency of count source (f2, f16, f64, f512) Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software Fig. 6.3.4 Operation example in timer mode (without pulse output and gate functions) 6-14 7733 Group User's Manual TIMER A 6.3 Timer mode 6.3.4 Selectable functions The gate and pulse output functions are described below. (1) Gate function The gate function is selected by setting the gate function selection bits (bits 4 and 3 at addresses 5616 to 5A16) to "102" or "11 2." When the gate function is selected, counting can be started or stopped by pin TAi IN's input signal. Table 6.3.3 lists the count valid levels. Figure 6.3.5 shows an operation example when the gate function is selected. When selecting the gate function, set the port P5 and port P6 direction registers' bits which correspond to pin TAiIN for the input mode. Also make sure that pin TAi IN's input signal has a pulse width equal to or greater than two cycles of the count source. Table 6.3.3 Count valid levels Gate function selection bits b3 b4 0 1 1 1 Count valid level (Duration of counting) While pin TAiIN 's input signal level is "L" While pin TAiIN 's input signal level is "H" Note: The counter does not count while pin TAi IN's input signal is not at the count valid level. 7733 Group User's Manual 6-15 TIMER A 6.3 Timer mode n = Reload register's contents FFFF16 Counting is started. Counter contents (Hex.) n Counting is stopped. 000016 Time Set to "1" by software Count start flag Pin TAiIN's input signal "1" "0" Count valid level Timer Ai interrupt "1" request bit "0" Counting is performed while the count start flag = "1" and pin TAiIN's input signal is at the count valid level. Counter stops counting while pin TAiIN's input signal is not at the count valid level, and counter value is retained. Fig. 6.3.5 Operation example when gate function is selected 6-16 7733 Group User's Manual Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software TIMER A 6.3 Timer mode (2) Pulse output function The pulse output function is selected by setting the pulse output function selection bit (bit 2 at addresses 5616 to 5A 16) to "1." When this function is selected, pin TAi OUT is forcibly set as the pulse output pin independent of the corresponding bits of the port P5 and port P6 direction registers. And then, pin TAiOUT outputs the signal of which polarity is inverted each time an underflow occurs. When the count start flag (address 40 16) = "0," in other words, when counting is stopped, pin TAi OUT outputs "L" level. Figure 6.3.6 shows an operation example when the pulse output function is selected. n = Reload register's contents Counter contents (Hex.) FFFF16 Counting is started. Counting is stopped. n Counting is restarted. 000016 Time Set to "1" by software Count start flag Cleared to "0" by software Set to "1" by software "1" "0" Pulse output from "1" pin TAiOUT "0" Timer Ai interrupt "1" request bit "0" Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software Fig. 6.3.6 Operation example when pulse output function is selected 7733 Group User's Manual 6-17 TIMER A 6.3 Timer mode [Precautions in timer mode] While counting is in progress, by reading out the timer Ai register, the counter value can be read at an arbitrary timing. However, when reading is performed at the reload timing shown in Figure 6.3.7, value "FFFF16" is read out. If reading is performed in the period from when a value is set into the timer Ai register with the counter stopped until the counter starts counting, the set value is correctly read out. Reload Counter value (Hex.) 2 1 0 Read value (Hex.) 2 1 0 n FFFF n - 1 n = Reload register's contents Fig. 6.3.7 Timer Ai register read out 6-18 n-1 7733 Group User's Manual Time TIMER A 6.4 Event counter mode 6.4 Event counter mode (Bits 1 and 0 of timer Ai mode register = "012") In this mode, an external signal is counted. (Refer to Tables 6.4.1 and 6.4.2.) Figures 6.4.1 and 6.4.2 show the structures of the timer Ai mode register and timer Ai register in the event counter mode. Table 6.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing function) Specifications Item External signal input to pin TAi IN Count source Count operation "Falling edge" or "Rising edge" can be selected as the valid edge of the count source by software. "Countup" or "countdown" can be selected by the external signal or software At an overflow or underflow, the reload register's contents is reloaded, and counting is continued (Note). Division ratio < While counting down> 1 (n + 1) < While counting up> 1 Count start condition Count stop condition n: Set value in the timer Ai register (FFFF 16 - n + 1) When the count start flag is set to "1." When the count start flag is cleared to "0." Interrupt request occurrence timing At an overflow or underflow Count source input Pin TAi IN's function Pin TAi OUT's function Programmable I/O port, pulse output, or countup/countdown switch signal input Read from timer A counter value can be read out by reading the timer Ai register. While counting is stopped Write to timer When a value is written to the timer Ai register, it is written to both of the reload register and counter. While counting is in progress When a value is written to the timer Ai register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Note: This is applied when not using the free-run count function. 7733 Group User's Manual 6-19 TIMER A 6.4 Event counter mode Table 6.4.2 Specifications of event counter mode (when using two-phase pulse signal processing function in timers A2, A3, and A4) Specifications Item Count source External signal (two-phase pulse) input to pin TAj IN or TAj OUT (j = 2 to 4) Count operation "Countup" or "countdown" can be selected by the external signal (two-phase pulse). At an overflow or underflow, the reload register's contents is reloaded, and counting is continued. (Note) Division ratio < While counting down> 1 (n + 1) < While counting up> 1 Count start condition n: Set value in the timer Aj register (FFFF 16 - n + 1) When the count start flag is set to "1." Count stop condition Interrupt request occurrence timing When the count start flag is cleared to "0." Pin TAjIN, TAjOUT 's (j = 2 to 4) function Two-phase pulse input Read from timer A counter value can be read out by reading the timer A2, A3, or A4 register. Write to timer While counting is stopped When a value is written to the timer A2, A3, or A4 register, it is written to both of the reload register and counter. At an overflow or underflow While counting is in progress When a value is written to the timer A2, A3, or A4 register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Note: This is applied when not using the free-run count function. 6-20 7733 Group User's Manual TIMER A 6.4 Event counter mode b7 5 5 b6 b5 0 b4 b3 b2 b1 b0 0 1 Timer A0 mode register (address 5616) Timer A1 mode register (address 5716) Bit Bit name Functions 0 RW 0 RW 2 Pulse output function selection bit 0: No pulse is output. (Pin TA0OUT or TA1OUT functions as a programmable I/O port.) 1: Pulse is output. (Pin TA0OUT or TA1OUT functions as a pulse output pin.) 0 RW 3 Count polarity selection bit 0: Counts at falling edge of external signal 1: Counts at rising edge of external signal 0 RW 4 Up-down switching factor selection bit 0: Contents of the up-down flag 1: A signal which is input to pin TA0OUT or TA1OUT 0 RW 5 Must be fixed to "0" in the event counter mode. 0 RW 6 These bits are ignored in the event counter mode. 0 RW 0 RW 0 1: Event counter mode 1 7 (b8) b0 b7 RW Operating mode selection bits 0 (b15) b7 At reset b1 b0 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Bit Functions 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1) in down-counting, or by (FFFF16 - n + 1) in upcounting. At reading this register, the counter value is read out. At reset RW Undefined RW Fig. 6.4.1 Structures of timer A0 and A1 mode registers and timer A0 and A1 registers in event counter mode 7733 Group User's Manual 6-21 TIMER A 6.4 Event counter mode b7 b6 b5 0 b4 b3 b2 b1 b0 0 1 Timer A2 mode register (address 5816) Timer A3 mode register (address 5916) Timer A4 mode register (address 5A16) Bit Bit name Functions At reset RW 0 RW 0 RW Operating mode selection bits b1 b0 2 Pulse output function selection bit 0: No pulse is output. (Pin TA2OUT, TA3OUT, or TA4OUT functions as a programmable I/O port.) 1: Pulse is output. (Pin TA2OUT, TA3OUT, or TA4OUT functions as a pulse output pin.) 0 RW 3 Count polarity selection bit 0: Counting is performed at the falling edge of the external signal. 1: Counting is performed at the rising edge of the external signal. 0 RW 4 Up-down switching factor selection bit 0: Contents of the up-down flag 1: A signal which is input to pin TA2OUT, TA3OUT, or TA4OUT 0 RW 0 RW 0 1 0 1: Event counter mode 5 Must be fixed to "0" in the event counter mode. 6 Count type selection bit 0: Reload count type 1: Free-run count type 0 RW 7 Two-phase pulse signal processing type selection bit (Note) 0: Normal processing 1: Quadruple processing 0 RW Note: This bit is valid only for the timer A3 mode register. For the timer A2 and A4 mode registers, this bit is ignored. (It may be "0" or "1.") (b15) b7 (b8) b0 b7 b0 Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Bit Functions 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1) in down-counting, or by (FFFF16 - n + 1) in up-counting. At reading this register, the counter value is read out. At reset RW Undefined RW Fig. 6.4.2 Structures of timer A2, A3, and A4 mode registers and timer A2, A3, and A4 registers in event counter mode 6-22 7733 Group User's Manual TIMER A 6.4 Event counter mode 6.4.1 Setting for event counter mode Figure 6.4.3 and 6.4.4 show an initial setting example for registers related to the event counter mode. Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter "4. INTERRUPTS." Selection of the event counter mode and each function b7 b0 0 0 1 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) Event counter mode is selected. Pulse output function selection bit 0: No pulse is output. 1: Pulse is output. Count polarity selection bit 0: Counts at falling edge of external signal. 1: Counts at rising edge of external signal. Up-down switching factor selection bit 0: Contents of the up-down flag 1: Input signal to pin TAiOUT Count type selection bit (Valid only for i = 2 to 4) 0: Reload count type 1: Free-run count type Two-phase pulse signal processing type selection bit (Valid only for i = 3) 0: Normal processing 1: Quadruple processing Setting of the up-down flag b7 b0 Up-down flag (address 4416) Timer A0 up-down flag *When up-down flag is selected as up-down switching Timer A1 up-down flag factor, set corresponding up-down flag. Timer A2 up-down flag 0: Countdown Timer A3 up-down flag 1: Countup Timer A4 up-down flag Timer A2 two-phase pulse signal *Selection of the two-phase pulse signal processing function processing selection bit Set the corresponding bit to "1." Timer A3 two-phase pulse signal 0: Two-phase pulse signal processing function is disabled. processing selection bit 1: Two-phase pulse signal processing function is enabled. Timer A4 two-phase pulse signal processing selection bit Setting of the division ratio (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Values 000016 to FFFF16 (n) can be set. Counter divides the count source frequency by (n + 1) while counting down or by (FFFF16 - n + 1) while counting up. Continued to "Initial setting example for registers related to event counter mode (2)" on the next page Fig. 6.4.3 Initial setting example for registers related to event counter mode (1) 7733 Group User's Manual 6-23 TIMER A 6.4 Event counter mode Continued from "Initial setting example for registers related to event counter mode (1)" on the preceding page Setting of the interrupt priority level b7 b0 Timer Ai interrupt control register (addresses 7516 to 7916) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Setting of the port P5 and port P6 direction registers b7 b0 Port P5 direction register (address D16) Pin TA0OUT Pin TA0IN Pin TA1OUT Pin TA1IN Pin TA2OUT Pin TA2IN Pin TA3OUT Pin TA3IN b7 b0 Port P6 direction register (address 1016) Pin TA4OUT Pin TA4IN Set a bit corresponding to pin TAiIN to "0." When the two-phase pulse signal processing function is selected, or when pin TAiOUT's input signal is selected as the up-down switching factor, set a bit corresponding to pin TAiOUT to "0." Setting of the count start flag to "1" b7 b0 Count start flag (address 4016) Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag AAA AAA AAA Counting is started. Fig. 6.4.4 Initial setting example for registers related to event counter mode (2) 6-24 7733 Group User's Manual TIMER A 6.4 Event counter mode 6.4.2 Operation in event counter mode When the count start flag is set to "1," the counter starts counting of the count source. The counter counts the count source's valid edges. When an underflow or overflow occurs, the reload register's contents is reloaded, and then counting is continued. The timer Ai interrupt request bit is set to "1" when the underflow or overflow occurs in . After this, the interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Figure 6.4.5 shows an operation example in the event counter mode. n = Reload register's contents FFFF16 Counter contents (Hex.) Counting is started. n 000016 Time Set to "1" by software Count start "1" flag "0" Set to "1" by software Up-down flag "1" "0" Timer Ai interrupt "1" request bit "0" Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software The above is applied when the up-down flag's content is selected as the up-down switching factor (i.e., up-down switching factor selection bit = "0"). Fig. 6.4.5 Operation example in event counter mode (without free-run count function, pulse output function, and two-phase pulse signal processing function) 7733 Group User's Manual 6-25 TIMER A 6.4 Event counter mode (1) Switching between countup and countdown A register named "up-down flag" (address 44 16 ) or pin TAi OUT 's input signal switches countup from and to countdown. This switching is performed by an up-down flag when the up-down switching factor selection bit (bit 4 at addresses 5616 to 5A16) = "0" and by pin TAiOUT's input signal when the up-down switching factor selection bit = "1." When the switching between countup and countdown is set while counting is in progress, this switching is realized at the next valid edge of the count source. When switching by up-down flag Countdown is performed when the up-down flag = "0," and countup is performed when the up-down flag = "1." Figure 6.4.6 shows the structure of the up-down flag. When switching by pin TAiOUT 's input signal Countdown is performed when pin TAi OUT's input signal level is "L" and countup is performed when it is "H." When switching countup from and to countdown by pin TAi OUT's input signal, set a port P5 or P6 direction register's bit which corresponds to pin TAi OUT for the input mode. b7 b6 b5 b4 b3 b2 b1 b0 Up-down flag (address 4416) Bit name Bit 0 Timer A0 up-down flag 1 Timer A1 up-down flag Functions 0: Countdown 1: Countup This bits is valid when the contents of the up-down flag is selected as the up-down switching factor. RW 0 RW 0 RW 0 RW 0 RW 2 Timer A2 up-down flag 3 Timer A3 up-down flag 4 Timer A4 up-down flag 0 RW 5 Timer A2 two-phase pulse signal 0: Two-phase pulse signal processing selection bit processing function is disabled. 1: Two-phase pulse signal Timer A3 two-phase pulse signal processing function is enabled. processing selection bit 0 WO 0 WO When not using the two-phase pulse Timer A4 two-phase pulse signal signal processing function, be sure processing selection bit to set this bit to "0." This bit is "0" at reading. 0 WO 6 7 Note: When writing to bits 5 to 7, use the LDM or STA instruction. Fig. 6.4.6 Structure of up-down flag 6-26 At reset 7733 Group User's Manual TIMER A 6.4 Event counter mode 6.4.3 Selectable functions The free-run count, pulse output, and two-phase pulse signal processing functions are described below. (1) Free-run count function (Timers A2 to A4) For timers A2 to A4, when the count type selection bit (bit 6 at addresses 5816 to 5A16) is set to "1," the free-run count function is selected. When the free-run count function is selected, although a timer A2/A3/A4 interrupt request is generated at an overflow or underflow, the reload register's contents is not reloaded into the counter. Figure 6.4.7 shows an operation example when the free-run count function is selected. n = Reload register's contents FFFF16 Counter contents (Hex.) Counting is started. n 000016 Time Set to "1" by software Count start "1" flag "0" Set to "1" by software Up-down flag "1" "0" Timer A2/A3/A4 "1" interrupt request bit "0" Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software After an underflow, counter starts counting from FFFF16. After an overflow, counter starts counting from 000016. The above is applied when the up-down flag's contents is selected as the up-down switching factor (i.e., up-down switching factor selection bit = "0"). Fig. 6.4.7 Operation example when free-run count function is selected (without pulse output function and two-phase pulse signal processing function) 7733 Group User's Manual 6-27 TIMER A 6.4 Event counter mode (2) Pulse output function The pulse output function is selected by setting the pulse output function selection bit (bit 2 at addresses 56 16 to 5A16) to "1." When this function is selected, pin TAiOUT is forcibly set as the pulse output pin independent of the corresponding bit of the port P5 or port P6 direction register. And then, pin TAi OUT outputs a signal of which polarity is inverted each time an underflow or overflow occurs (Refer to Figure 6.3.6). When the count start flag (address 40 16) = "0," in other words, when counting is stopped, pin TAi OUT outputs "L" level. (3) Two-phase pulse signal processing function (Timers A2 to A4) For timers A2 to A4, the two-phase pulse signal processing function is selected by setting the twophase pulse signal processing selection bits (bits 5 to 7 at address 4416 ) to "1." (Refer to Figure 6.4.6.) Figure 6.4.8 shows the timer A2, A3, and A4 mode registers when the two-phase pulse signal processing function is selected. In a timer with the two-phase pulse signal processing function selected, two kinds of pulses of which phases differ by 90 degrees are counted. There are two types of the two-phase pulse signal processing: normal processing and quadruple processing. In timer A2, normal processing is performed; in timer A4, quadruple processing is performed. In timer A3, either normal processing or quadruple processing can be selected by the two-phase pulse signal processing type selection bit (bit 7 at address 59 16). Some bits of the port P5 and P6 direction registers correspond to pins used for the two-phase pulse input. Set these bits for the input mode. b7 b6 b5 b4 0 1 0 b3 b2 b1 b0 0 0 1 Timer A2 mode register (address 5816) Timer A3 mode register (address 5916) Timer A4 mode register (address 5A16) 0: Reload count type 1: Free-run count type : Bit 7 of the timer A3 mode register is used to select the two-phase pulse signal processing type of timer A3. Normal processing is selected when this bit = "0," and quadruple processing is selected when this bit = "1." Bit 7 of the timer A2/A4 mode register is ignored. (It may be "0" or "1.") Fig. 6.4.8 Timer A2, A3, and A4 mode registers when two-phase pulse signal processing function is selected 6-28 7733 Group User's Manual TIMER A 6.4 Event counter mode Normal processing Countup is performed at the rising edges of pin TAkIN (k = 2 and 3) if the phase relationship is such that pin TAkIN's input signal level changes from "L" to "H" while pin TAk OUT's input signal level is "H." Countdown is performed at the falling edges of pin TAkIN if the phase relationship is such that pin TAkIN's input signal level changes from "H" to "L" while pin TAkOUT's input signal level is "H." (Refer to Figure 6.4.9.) "H" TAkOUT "L" "H" TAkIN (k = 2, 3) "L" Counted up Counted up Counted up Counted down Counted down Counted down +1 +1 +1 -1 -1 -1 Fig. 6.4.9 Normal processing Quadruple processing Countup is performed at the rising and falling edges of pins TAIOUT (l = 3 and 4) and TAIIN if the phase relationship is such that pin TAI IN 's input signal level changes from "L" to "H" while pin TAI OUT's input signal level is "H." Countdown is performed at the rising and falling edges of pins TAIOUT and TAI IN if the phase relationship is such that pin TAIIN's input signal level changes from "H" to "L" while pin TAI OUT's input signal level is "H." (Refer to Figure 6.4.10.) Table 6.4.3 lists input signals of pins TAIOUT and TAIIN when the quadruple processing is selected. "H" TAlOUT "L" Counted up at all edges +1 +1 +1 +1 Counted down at all edges -1 +1 -1 -1 -1 -1 "H" TAlIN (l = 3, 4) "L" Counted up at all edges +1 +1 +1 +1 +1 Counted down at all edges -1 -1 -1 -1 -1 Fig. 6.4.10 Quadruple processing 7733 Group User's Manual 6-29 TIMER A 6.4 Event counter mode Table 6.4.3 Pin TAIOUT and TAI IN's input signals when quadruple processing is selected Input signal of pin TAI OUT Countup Countdown 6-30 Input signal of pin TAI IN "H" level Rising edge "L" level Rising edge Falling edge "H" level "L" level Rising edge Falling edge Falling edge 7733 Group User's Manual "L" level "H" level Falling edge Rising edge "H" level "L" level TIMER A 6.4 Event counter mode [Precautions in event counter mode] 1. While counting is in progress, by reading out the timer Ai register, the counter value can be read at an arbitrary timing. However, when reading is performed at the reload timing shown in Figure 6.4.11, value "FFFF16" is read out at an underflow and value "000016" is read out at an overflow. If reading is performed in the period from when a value is set into the timer Ai register with the counter stopped until the counter starts counting, the set value is correctly read out. (1) While counting down (2) While counting up Reload Reload Counter value (Hex.) 2 1 0 Read value (Hex.) 2 1 0 n-1 Counter value (Hex.) FFFF n - 1 Read value (Hex.) n FFFD FFFE FFFF n+1 FFFD FFFE FFFF 0000 n + 1 Time n = Reload register's contents n Time n = Reload register's contents Fig. 6.4.11 Timer Ai register read out 2. Pin TAiOUT is used for all functions listed below. Therefore, only one of the following functions can be used for one timer. Switching between countup and countdown by pin TAiOUT 's input signal Pulse output function Two-phase pulse signal processing function (Timers A2 to A4) 7733 Group User's Manual 6-31 TIMER A 6.5 One-shot pulse mode 6.5 One-shot pulse mode (Bits 1 and 0 of timer Ai mode register = "102") In this mode, a pulse which has an arbitrary width is output once. (Refer to Table 6.5.1.) After a trigger occurs, "H" level is output from pin TAi OUT for an arbitrary time. Figure 6.5.1 shows the structures of the timer Ai mode register and timer Ai register in the one-shot pulse mode. Table 6.5.1 Specifications of one-shot pulse mode Item Specifications Count source Clock f2 , f 16, f 64, or f 512 Count operation Countdown When the counter value reaches "000016," the reload register's contents is reloaded, and counting stops. When a trigger occurs while counting is in progress, the reload register's contents is reloaded, and counting is continued. Output pulse width ("H") n fi [s] n: Set value in the timer Ai register Count start condition When a trigger occurs. (Note) Count stop condition Internal or external trigger can be selected by software. When the counter value reaches "0000 16." When the count start flag is cleared to "0." Interrupt request occurrence timing When counting stops. Programmable I/O port or trigger input Pin TAi IN's function Pin TAi OUT's function One-shot pulse output Read from timer An undefined value is read out by reading the timer Ai register. While counting is stopped Write to timer When a value is written to the timer Ai register, it is written to both of the reload register and counter. While counting is in progress When a value is written to the timer Ai register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Clocks f 2, f 16, f 64, and f 512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: A trigger occurs when the count start flag = "1." 6-32 7733 Group User's Manual TIMER A 6.5 One-shot pulse mode b7 b6 b5 0 b4 b3 b2 b1 b0 1 1 0 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) Bit 0 1 2 Bit name Functions Operating mode selection bits At reset RW 0 RW 0 RW 0 RW 0 X: Writing "1" to the one-shot start flag (Pin 0 TAiIN functions as a programmable I/O @ @ @ port.) 1 0: Falling edge of the pin TAiIN's input signal 0 1 1: Rising edge of the pin TAiIN's input signal RW 0 RW 0 RW 0 RW At reset RW Undefined WO b1 b0 1 0: One-shot pulse mode Must be fixed to "1" in the one-shot pulse mode. b4 b3 3 Trigger selection bits 4 5 Must be fixed to "0" in the one-shot pulse mode. 6 Count source selection bits 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 7 b7 b6 RW Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Bit Functions 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, "H" level width of the one-shot pulse output from pin TAiOUT is n/fi. fi: Frequency of the count source (f2, f16, f64, or f512) Fig. 6.5.1 Structures of timer Ai mode register and timer Ai register in one-shot pulse mode 7733 Group User's Manual 6-33 TIMER A 6.5 One-shot pulse mode 6.5.1 Setting for one-shot pulse mode Figures 6.5.2 and 6.5.3 show an initial setting example for registers related to the one-shot pulse mode. Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter "4. INTERRUPTS." Selection of the one-shot pulse mode and each function b7 b0 0 1 1 0 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) One-shot pulse mode is selected. Trigger selection bits b4 b3 0 X: Writing "1" to the one-shot start flag: Internal trigger 1 0: Falling edge of pin TAiIN's input signal: External trigger 1 1: Rising edge of pin TAiIN's input signal: External trigger Count source selection bits b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 X: It may be "0" or "1." Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Setting of the one-shot pulse's "H" level width (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Values 000016 to FFFF16 (n) can be set. "H" level width = n/fi fi = Frequency of the count source (f2, f16, f64, or f512) However, if n = 000016, the counter does not operate and pin TAiOUT outputs "L" level. At this time, no timer Ai interrupt request is generated. Setting of the interrupt priority level b7 b0 Timer Ai interrupt control register (addresses 7516 to 7916) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Continued to "Initial setting example for registers related to one-shot pulse mode (2)" on the next page Fig. 6.5.2 Initial setting example for registers related to one-shot pulse mode (1) 6-34 7733 Group User's Manual TIMER A 6.5 One-shot pulse mode Continued from "Initial setting example for registers related to one-shot pulse mode (1)" on the preceding page When the external trigger is selected When the internal trigger is selected Setting of port P5 and port P6 direction registers b7 Setting of count start flag to "1" b7 b0 b0 Port P5 direction register (address D16) Count start flag (address 4016) Timer A0 count start flag Pin TA0IN Pin TA1IN Timer A1 count start flag Timer A2 count start flag Pin TA2IN Pin TA3IN b7 Timer A3 count start flag b0 Port P6 direction register (address 1016) Timer A4 count start flag Pin TA4IN Clear the corresponding bit to "0." Setting of count start flag to "1" Setting of one-shot start flag to "1" b7 b7 b0 Count start flag (address 4016 ) Timer A0 count start flag b0 One-shot start flag (address 4216) Timer Timer Timer Timer Timer Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag A0 A1 A2 A3 A4 one-shot one-shot one-shot one-shot one-shot start start start start start flag flag flag flag flag Timer A4 count start flag Trigger input to pin TAiIN Trigger is generated. Counting is started. Fig. 6.5.3 Initial setting example for registers related to one-shot pulse mode (2) 7733 Group User's Manual 6-35 TIMER A 6.5 One-shot pulse mode 6.5.2 Count source In the one-shot pulse mode, by the count source selection bits (bits 7 and 6 at addresses 5616 to 5A 16), a count source can be selected. Table 6.5.2 lists the relationship between the count source selection bits and count source. Table 6.5.2 Relationship between count source selection bits and count source b7 b6 Count Frequency of count source source When system clock = 25 MHz When system clock = 16 MHz When system clock = 8 MHz f2 0 0 12.5 MHz 8 MHz 4 MHz f16 0 1 1.5625 MHz 1 MHz 500 kHz f64 1 0 390.625 kHz 250 kHz 125 kHz f512 1 1 48.8281 kHz 15.625 kHz 31.25 kHz Clocks f 2 , f16 , f64 , f512, and system clock: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: The above is applied when the system clock selection bit (bit 3 at address 6C16) = "0" and the main clock division selection bit (bit 0 at address 6F16) = "0." (For details, refer to chapter "14. CLOCK GENERATING CIRCUIT.") 6-36 7733 Group User's Manual TIMER A 6.5 One-shot pulse mode 6.5.3 Trigger The counter enters the count enable state when the count start flag (address 40 16) is set to "1." And then, the counter starts counting when a trigger occurs. An internal or external trigger can be selected as this trigger. An internal trigger is selected when the trigger selection bits (bits 4 and 3 at addresses 56 16 to 5A16) are "00 2 " or "01 2"; an external trigger is selected when the trigger selection bits are "10 2" or "11 2." When a trigger occurs during counting, the reload register's contents is reloaded and the counter continues counting. When generating a trigger during counting, make sure that a certain time which is equivalent to two cycles of the timer's count source or more has passed between the trigger previously generated and a new trigger. (1) When internal trigger is selected A trigger is generated when the one-shot start flag (address 4216 ) is set to "1." Figure 6.5.4 shows the structure of the one-shot start flag. (2) When external trigger is selected A trigger is generated at the falling edge of pin TAiIN's input signal when bit 3 at addresses 5616 to 5A 16 = "0" or at the rising edge of pin TAi IN 's input signal when bit 3 = "1." When using an external trigger, set the port P5 or P6 direction register's bit which corresponds to pin TAi IN 's for the input mode. b7 b6 b5 b4 b3 b2 b1 b0 One-shot start flag (address 4216) Bit Bit name Functions At reset RW 0 WO 0 WO 0 WO 0 Timer A0 one-shot start flag 1 Timer A1 one-shot start flag 1: One-shot pulse output is started. (Valid when the internal trigger is selected). 2 Timer A2 one-shot start flag "0" at reading. 3 Timer A3 one-shot start flag 0 WO 4 Timer A4 one-shot start flag 0 WO Undefined - 7 to 5 Not implemented. Fig. 6.5.4 Structure of one-shot start flag 7733 Group User's Manual 6-37 TIMER A 6.5 One-shot pulse mode 6.5.4 Operation in one-shot pulse mode When the one-shot pulse mode is selected by the operating mode selection bits, pin TAiOUT outputs "L" level. When the count start flag is set to "1," the counter enters the count enable state, and then it starts counting if a trigger occurs. When the counter starts counting, pin TAi OUT's output level becomes "H." (However, if value "0000 16 " is set in the timer Ai register, the counter does not operate and the output level of pin TAi OUT remains "L." Nor is a timer Ai interrupt request generated.) When the counter value reaches "0000 16," the output level of pin TAi OUT becomes "L." And then, the reload register's contents is reloaded, and the counter stops counting. Simultaneously with , a timer Ai interrupt request bit is set to "1." After this, the interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Figure 6.5.5 shows an operation example in the one-shot pulse mode. When a trigger occurs after above, the counter and pin TAi OUT perform the same operations beginning from again. When a trigger occurs during counting, the counter down-counts once after this new trigger occurs. And then, the reload register's contents is reloaded and counting is continued. When generating a trigger during counting, make sure that a certain time which is equivalent to two cycles of the timer's count source or more has passed between the trigger previously generated and a new trigger. The one-shot pulse output from pin TAiOUT can be disabled by clearing the timer Ai mode register's bit 2 to "0." Therefore, timer Ai can be used as an internal one-shot timer that does not output the pulse. (In this case, pin TAi OUT functions as a programmable I/O port.) 6-38 7733 Group User's Manual TIMER A 6.5 One-shot pulse mode FFFF16 n = Reload register's contents Counter contents (Hex.) Counting is started. Counting is stopped. Counting is started. Counting is stopped. n Reloaded Reloaded 000116 Time Set to "1" by software Count start "1" flag "0" Trigger during counting Pin TAiIN's "H" input signal "L" 1 / fi (n) 1 / fi (n + 1) One-shot pulse "H" output from pin "L" TAiOUT Timer Ai interrupt "1" request bit "0" fi = Frequency of count source (f2,f16,f64,f512) Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software When the count start flag = "0," in other words, when counting is stopped, pin TAiOUT outputs "L" level. When a trigger occurs during counting, the counter counts the count source (n + 1) times after a new trigger occurs. The above is applied when an external trigger (Rising edge of pin TAiIN's input signal) is selected. Fig. 6.5.5 Operation example in one-shot pulse mode (when external trigger selected) 7733 Group User's Manual 6-39 TIMER A 6.5 One-shot pulse mode [Precautions in one-shot pulse mode] 1. When the count start flag is cleared to "0" during counting, the followings are performed. *The counter stops counting, and the reload register's contents is reloaded. *Pin TAi OUT's output level becomes "L." *An interrupt request is generated, and a timer Ai interrupt request bit is set to "1." 2. A one-shot pulse is output synchronously with an internally generated count source. Therefore, when an external trigger is selected, in the period from when a trigger is input to pin TAi IN until a one-shot pulse is output, there will be a delay equivalent to one cycle of the count source at maximum. Pin TAiIN's "H" input signal "L" Trigger input Count source One-shot pulse output from pin TAiOUT One-shot pulse output is started. The above is applied when an external trigger (Falling edge of pin TAiIN's input signal) is selected. Fig. 6.5.6 Delay in one-shot pulse output 3. When a timer's operating mode is set by the procedure listed below, a timer Ai interrupt request bit is set to "1." When the one-shot pulse mode is selected after reset When the operating mode is switched from the timer mode to the one-shot pulse mode When the operating mode is switched from the event counter mode to the one-shot pulse mode Therefore, when using a timer Ai interrupt (Interrupt request bit), be sure to clear the timer Ai interrupt request bit to "0" after setting the above. 6-40 7733 Group User's Manual TIMER A 6.6 Pulse width modulation (PWM) mode 6.6 Pulse width modulation (PWM) mode (Bits 1 and 0 of timer Ai mode register = "112") In this mode, a pulse which has an arbitrary width is output in succession. (Refer to Table 6.6.1.) Figure 6.6.1 shows the structures of the timer Ai mode register and timer Ai register in the PWM mode. Table 6.6.1 Specifications of PWM mode Item Specifications Count source Clock f 2, f 16, f 64, or f 512 Count operation Countdown (Operates as an 8-bit or 16-bit pulse width modulator) Reload register's contents is reloaded at the rising edge of PWM pulse, and counting is continued. A trigger generated during counting does not affect the counting. PWM period and "H" level width <16-bit pulse width modulator> Period = 2 16 - 1 fi "H" level width = [s] K fi [s] K: Set value in the timer Ai register <8-bit pulse width modulator> Period = (m + 1)(2 8 - 1) fi "H" level width = [s] n(m + 1) [s] fi m: Set value in the low-order 8 bits of the timer Ai register n: Set value in the high-order 8 bits of the timer Ai register Count start condition When a trigger occurs. Internal or external trigger can be selected by software. Count stop condition When the count start flag is cleared to "0." Interrupt request occurrence timing At the falling edge of PWM pulse Pin TAi IN's function Programmable I/O port or trigger input Pin TAi OUT's function PWM pulse output Read from timer An undefined value is read out by reading the timer Ai register. Write to timer While counting is stopped When a value is written to the timer Ai register, it is written to both of the reload register and counter. While counting is in progress When a value is written to the timer Ai register, it is written only to the reload register. Clocks f 2 , f16, f 64, and f 512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." 7733 Group User's Manual 6-41 TIMER A 6.6 Pulse width modulation (PWM) mode b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) Bit 0 1 2 Bit name Functions At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW At reset RW 15 to 0 Values 000016 to FFFE16 can be set. UnAssuming that the set value = n, "H" level defined width of the PWM pulse which is output from pin TAiOUT is n/fi. WO Operating mode selection bits b1 b0 1 1: PWM mode Must be fixed to "1" in the PWM mode. b4 b3 3 0 X: Writing "1" to the count start flag (Pin TAiIN functions as a programmable I/O port.) 1 0: Falling edge of the pin TAiIN's input signal 1 1: Rising edge of the pin TAiIN's input signal Trigger selection bits 4 0: The counter operates as a 16-bit pulse width modulator. 1: The counter operates as an 8-bit pulse width modulator. 5 16/8-bit PWM mode selection bit 6 Count source selection bits 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 7 b7 b6 Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." When operating as a 16-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Bit Functions fi: Frequency of the count source (f2, f16, f64, or f512) When operating as an 8-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Bit Functions At reset RW Undefined WO 15 to 8 Values 0016 to FE16 can be set. UnAssuming that the set value = n, "H" level defined width of the PWM pulse which is output from pin TAiOUT is n(m +1)/fi. WO 7 to 0 Values 0016 to FF16 can be set. Assuming that the set value = m, period of the PWM pulse which is output from pin TAiOUT is (m + 1)(28 - 1)/fi. fi: Frequency of the count source (f2, f16, f64, or f512) Fig. 6.6.1 Structures of timer Ai mode register and timer Ai register in PWM mode 6-42 7733 Group User's Manual TIMER A 6.6 Pulse width modulation (PWM) mode 6.6.1 Setting for PWM mode Figures 6.6.2 and 6.6.3 show an initial setting example for registers related to the PWM mode. Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter "4. INTERRUPTS." Selection of PWM mode and each function b7 b0 1 1 1 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) PWM mode selected Trigger selection bits b4 b3 0 X: Writing "1" to the count start flag: Internal trigger 1 0: Falling edge of pin TAiIN's input signal: External trigger 1 1: Rising edge of pin TAiIN's input signal: External trigger 16/8-bit PWM mode selection bit 0: The counter operates as 16-bit pulse width modulator. 1: The counter operates as 8-bit pulse width modulator. Count source selection bits b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 X: It may be "0" or "1." Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Setting of PWM pulse's period and "H" level width When operating as a 16-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Values 000016 to FFFE16 (n) can be set. When operating as an 8-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Values 0016 to FF16 (m) can be set. Values 0016 to FE16 (n) can be set. When operating as an 8-bit pulse width modulator Period = (m+1) (28 - 1)/fi "H" level width = n(m + 1)/fi fi: Frequency of the count source (f2, f16, f64, or f512) However, if n = 0016, the pulse width modulator does not operate and pin TAiOUT outputs "L" level. At this time, no timer Ai interrupt request is generated. When operating as a 16-bit pulse width modulator Period = (216 - 1)/fi fi: Frequency of the count source (f2, f16, f64, or f512) However, if n = 000016, the pulse width modulator does not operate and pin TAiOUT outputs "L" level. At this time, no timer Ai interrupt request is generated. Continued to "Initial setting example for registers related to PWM mode (2)" on the next page Fig. 6.6.2 Initial setting example for registers related to PWM mode (1) 7733 Group User's Manual 6-43 TIMER A 6.6 Pulse width modulation (PWM) mode Continued from "Initial setting example for registers related to PWM mode (1)" on the preceding page Setting of the interrupt priority level b7 b0 Timer Ai interrupt control register (addresses 7516 to 7916) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. When the external trigger is selected When the internal trigger is selected Setting of the port P5 and port P6 direction registers b7 b0 Port P5 direction register (address D16) Setting of the count start flag to "1" b7 b0 Count start flag (address 4016) Pin TA0IN Pin TA1IN Pin TA2IN Pin TA3IN b7 b0 Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Port P6 direction register (address 1016) Timer A4 count start flag Pin TA4IN Clear the corresponding bit to "0." Setting of the count start flag to "1" b7 b0 Count start flag (address 4016) Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Trigger input to pin TAiIN AAA AAA AAA Trigger is generated. Counting is started. Fig. 6.6.3 Initial setting example for registers related to PWM mode (2) 6-44 7733 Group User's Manual TIMER A 6.6 Pulse width modulation (PWM) mode 6.6.2 Count source In the PWM mode, by the count source selection bits (bits 7 and 6 at addresses 5616 to 5A 16 ), a count source can be selected. Table 6.6.2 lists the relationship between the count source selection bits and count source. Table 6.6.2 Relationship between count source selection bits and count source b7 b6 Frequency of count source Count source 0 0 f2 0 1 1 0 f 16 f 64 When system clock = 25 MHz 12.5 MHz When system clock = 16 MHz 8 MHz 1.5625 MHz 1 MHz 390.625 kHz 48.8281 kHz 250 kHz When system clock = 8 MHz 4 MHz 500 kHz 125 kHz 15.625 kHz 1 1 31.25 kHz f512 Clocks f 2, f16 , f64 , f512, and system clock: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: The above is applied when the system clock selection bit (bit 3 at address 6C16) = "0" and the main clock division selection bit (bit 0 at address 6F 16) = "0." (For details, refer to chapter "14. CLOCK GENERATING CIRCUIT.") 7733 Group User's Manual 6-45 TIMER A 6.6 Pulse width modulation (PWM) mode 6.6.3 Trigger When a trigger occurs, pin TAi OUT starts the PWM pulse output. An internal or external trigger can be selected as this trigger. An internal trigger is selected when the trigger selection bits (bits 4 and 3 at addresses 56 16 to 5A16) are "002 " or "01 2"; an external trigger is selected when the trigger selection bits are "10 2 " or "11 2." A trigger generated during PWM pulse output is invalid and does not affect the pulse output operation. (1) When internal trigger is selected A trigger is generated when the count start flag (address 40 16 ) is set to "1." (2) When external trigger is selected A trigger is generated at the falling edge of the pin TAiIN's input signal when bit 3 at addresses 56 16 to 5A 16 = "0" or at the rising edge of the pin TAiIN's input signal when bit 3 = "1." However, a trigger input is accepted only when the count start flag = "1." When using an external trigger, set the port P5 or P6 direction register's bit which corresponds to pin TAi IN for the input mode. 6-46 7733 Group User's Manual TIMER A 6.6 Pulse width modulation (PWM) mode 6.6.4 Operation in PWM mode When the PWM mode is selected by the operating mode selection bits, pin TAi OUT outputs "L" level. When a trigger occurs, the counter (Pulse width modulator) starts counting and pin TAi OUT outputs a PWM pulse (Notes 1 and 2). A timer Ai interrupt request bit is set to "1" each time the PWM pulse level changes from "H" to "L." After this, the interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Each time a PWM pulse is output for one period, the reload register's contents is reloaded and counting is continued. Operation of the pulse width modulator is described below. [16-bit pulse width modulator] When the 16/8-bit PWM mode selection bit is set to "0," the counter operates as a 16-bit pulse width modulator. Each of Figures 6.6.4 and 6.6.5 shows an operation example of the 16-bit pulse width modulator. [8-bit pulse width modulator] When the 16/8-bit PWM mode selection bit is set to "1," the counter is divided into 8-bit halves. Then, the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as an 8-bit prescaler. Each of Figures 6.6.6 and 6.6.7 shows an operation example of the 8-bit pulse width modulator. Notes 1: If a value of "0000 16 " is set in the timer Ai register when the counter operates as a 16-bit pulse width modulator, the pulse width modulator does not operate and the output level of pin TAi OUT remains "L." Nor is a timer Ai interrupt request generated. These operations are also applied to the case where a value of "0016" is set in high-order 8 bits of the timer Ai register when the counter operates as an 8-bit pulse width modulator. 2: When the counter operates as an 8-bit pulse width modulator, after a trigger occurs, pin TAi OUT outputs "L" level of which width is the same as the PWM pulse's "H" level width which was set. And then, pin TAiOUT starts the PWM pulse output. 7733 Group User's Manual 6-47 TIMER A 6.6 Pulse width modulation (PWM) mode 1 / fi (216 - 1) Count source Pin TAiIN's input signal "H" "L" Trigger is not generated by this signal. 1 / fi (n) PWM pulse output from pin TAiOUT "H" "L" Timer Ai interrupt "1" request bit "0" fi: Frequency of the count source (f2, f16, f64, or f512) Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software The above is applied when the reload register = 000316 and an external trigger (Rising edge of pin TAiIN's input signal) is selected. Fig. 6.6.4 Operation example of 16-bit pulse width modulator n = Reload register's contents Counter contents (Hex.) (1 / fi) (216 - 1) (1 / fi) (216 - 1) (1 / fi) (216 - 1) FFFE16 200016 (216 - 1) - n n 000116 Counting is stopped. Pin TAiIN's "H" input signal "L" Time PWM pulse output from "H" pin TAiOUT "L" fi: Frequency of the count source (f2, f16, f64, or f512) Counting is restarted. Value "FFFE16" is set to the timer Ai register. Value "000016" is set to the timer Ai register. Value "200016" is set to the timer Ai register. When an arbitrary value is reset to the timer Ai register after value "000016" is set to it, the rising timing of PWM pulse depends on this reset timing. The above is applied when an external trigger (Rising edge of pin TAiIN's input signal) is selected. Fig. 6.6.5 Operation example of 16-bit pulse width modulator (when counter value is updated during pulse output) 6-48 7733 Group User's Manual TIMER A 6.6 Pulse width modulation (PWM) mode 1 / fi (m + 1) (28 - 1) Count source Pin TAiIN's "H" input signal "L" 1 / fi (m + 1) 8-bit prescaler's "H" underflow signal "L" 1 / fi (m + 1) (n) PWM pulse output "H" from pin TAiOUT "L" Timer Ai interrupt "1" request bit "0" fi: Frequency of the count source (f2, f16, f64, or f512) Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software 8-bit prescaler counts the count source. 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. The above is applied when the following conditions are satisfied: *Reload register's high-order 8 bits = "0216" *Reload register's low-order 8 bits = "0216" *When an external trigger (Falling edge of pin TAiIN's input signal) is selected. Fig. 6.6.6 Operation example of 8-bit pulse width modulator 7733 Group User's Manual 6-49 Prescaler contents (Hex.) 7733 Group User's Manual 0116 0416 0A16 0016 0216 Value "040216" is set to the timer Ai register. m: Contents of the reload register's low-order 8 bits Value "000216" is set to the timer Ai register. (1 / fi) (m + 1) (28 - 1) Counting is restarted. Value "0A0216" is set to the timer Ai register. Counting is stopped. (1 / fi) (m + 1) (28 - 1) Time Time The above is applied when an external trigger (Falling edge of pin TAiIN's input signal) is selected. When an arbitrary value is reset to the timer Ai register after value "0016" is set to the timer Ai register's high-order 8 bits, the rising timing of the PWM pulse depends on this reset timing. fi: Frequency of the count source (f2, f16, f64, or f512) PWM pulse output "H" from pin TAiOUT "L" Counter contents (Hex.) 6-50 Pin TAiIN's "H" input signal "L" Count source (1 / fi) (m + 1) (28 - 1) TIMER A 6.6 Pulse width modulation (PWM) mode Fig. 6.6.7 Operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) TIMER A 6.6 Pulse width modulation (PWM) mode [Precautions in PWM mode] 1. When the count start flag is cleared to "0" while a PWM pulse is output, the counter stops counting. At this time, if pin TAi OUT outputs "H" level, the output level becomes "L" and a timer Ai interrupt request bit is set to "1." If pin TAiOUT outputs "L" level, the output level does not change and a timer Ai interrupt request is not generated. 2. When a timer's operating mode is set by the procedure listed below, a timer Ai interrupt request bit is set to "1." When the PWM mode is selected after reset When the operating mode is switched from the timer mode to the PWM mode When the operating mode is switched from the event counter mode to the PWM mode Therefore, when using a timer Ai interrupt (Interrupt request bit), be sure to clear the timer Ai interrupt request bit to "0" after setting the above. 7733 Group User's Manual 6-51 TIMER A 6.6 Pulse width modulation (PWM) mode MEMO 6-52 7733 Group User's Manual CHAPTER 7 TIMER B 7.1 7.2 7.3 7.4 7.5 Overview Block description Timer mode Event counter mode Pulse period/Pulse width measurement mode 7.6 Clock timer TIMER B 7.1 Overview 7.1 Overview Timer B consists of three counters (Timers B0 to B2), and each has a 16-bit reload function. Timers B0 to B2 operate independently of each other. Timer Bi (i = 0 to 2) has three operating modes listed below. Furthermore, timer B2 can function as a clock timer. Except that timer B2 functions as a clock timer and timer B1 has an internal connect function, timers B0 to B2 have the same functions. Timer mode Timer B counts a count source internally generated. Event counter mode Timer B counts an external signal, and the following functions can be used: Internal connect function (Timer B1 only) Pulse period/Pulse width measurement mode Timer B measures an external signal's pulse period/pulse width. Clock timer (Timer B2) 7-2 7733 Group User's Manual TIMER B 7.2 Block description 7.2 Block description Figure 7.2.1 shows the timer B block diagram. Registers related to timer B are described below. Data bus (Odd) Clock source selection f2 f16 f64 Data bus (Even) (Low-order 8 bits) f512 *Timer mode *Pulse period/Pulse width measurement mode TBiIN (i = 0 to 2) Polarity switching and Edge pulse generating circuit (High-order 8 bits) Timer Bi reload register (16) Event counter mode Timer Bi counter (16) fc32 (Note 1) TB2 overflow signal (Note 2) Count start flag (address 4016) Counter reset circuit Timer Bi interrupt request bit Timer Bi overflow flag addresses Timer B0 5116 5016 Timer B1 5316 5216 Timer B2 5516 5416 Notes 1: Clock source for clock timer Can be selected only for TB2 (Refer to Figure 14.3.1.) 2: Can be selected only for TB1 (Internal connect mode) Clocks f2, f16, f64, and f512 : Refer to chapter "14. CLOCK GENERATING CIRCUIT." Fig. 7.2.1 Timer B block diagram 7733 Group User's Manual 7-3 TIMER B 7.2 Block description 7.2.1 Counter and Reload register (Timer Bi register) Each of timer Bi counter and its reload register consists of 16 bits and has the following functions. (1) Functions in timer mode, event counter mode, and clock timer The counter performs countdown each time a count source is input. The reload register is used to memorize the initial value of a counter. When an underflow occurs in the counter, the reload register's contents is reloaded into the counter. Values are set to the counter and reload register by writing the values to the timer Bi register. Table 7.2.1 lists the memory allocation of the timer Bi register. A value written into the timer Bi register while counting is stopped is set to the counter and reload register. A value written into the timer Bi register while counting is in progress is set only to the reload register. In this case, the reload register's updated contents is transferred to the counter when the next underflow occurs. A value obtained by reading out the timer Bi register is the counter value. Note: Perform reading or writing from/to the timer Bi register by the 16 bits. For a value read from the timer Bi register, refer to "Precautions in timer mode" and "Precautions in event counter mode." (2) Functions in pulse period/pulse width measurement mode The counter performs countup each time a count source is input. The reload register is used to hold the pulse period or pulse width measurement result. When a valid edge is input to pin TBiIN , the counter value is transferred to the reload register. In this mode, a value obtained by reading out the timer Bi register is the reload register's contents, and the measurement result can be obtained. Note: Perform reading from the timer Bi register by the 16 bits. Table 7.2.1 Memory allocation of timer Bi register Timer Bi register High-order byte Low-order byte Timer B0 register Address 51 16 Address 5016 Timer B1 register Address 53 16 Address 5216 Timer B2 register Address 55 16 Address 5416 Note: At reset, the contents of the timer Bi register is undefined. 7-4 7733 Group User's Manual TIMER B 7.2 Block description 7.2.2 Count start flag This register is used to start or stop counting. Each bit of this register corresponds to each timer, respectively. Figure 7.2.2 shows the structure of the count start flag. b7 b6 b5 b4 b3 b2 b1 b0 Count start flag (address 4016) Bit Functions Bit name At reset RW 0 RW 0 Timer A0 count start flag 1 Timer A1 count start flag 0 RW 2 Timer A2 count start flag 0 RW 3 Timer A3 count start flag 0 RW 4 Timer A4 count start flag 0 RW 5 Timer B0 count start flag 0 RW 6 Timer B1 count start flag 0 RW 7 Timer B2 count start flag 0 RW 0: Counting is stopped. 1: Counting is started. represents that bits 0 to 4 are not used for timer B. Fig. 7.2.2 Structure of count start flag 7733 Group User's Manual 7-5 TIMER B 7.2 Block description 7.2.3 Timer Bi mode register Figure 7.2.3 shows the structure of the timer Bi mode register. The operating mode selection bits are used to select an operating mode of timer Bi. Bits 7 to 5 and bits 3 and 2 have different functions according to the operating mode. These bits are described in a section of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Bit 0 Bit name At reset RW 0 RW 0 RW 0 RW 0 RW Must be fixed to "0" (i = 0). 0 RW Not implemented (i = 1, 2). Undefined -- These bits have different functions according to the operating mode. UnRO defined (Note) Operating mode selection bits 1 2 Functions b1 b0 0 0: Timer mode 0 1: Event counter mode 1 0: Pulse period/Pulse width measurement mode 1 1: Do not select. These bits have different functions according to the operating mode. 3 @ 4 5 6 0 RW 7 @ 0 RW Note: In the timer and event counter modes, bit 5 is ignored and undefined at reading. Fig. 7.2.3 Structure of timer Bi mode register 7-6 7733 Group User's Manual TIMER B 7.2 Block description 7.2.4 Timer Bi interrupt control register Figure 7.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer to chapter "4. INTERRUPTS" b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi interrupt control register (i = 0 to 2) (addresses 7A16 to 7C16) Bit Bit name 0 Interrupt priority level selection bits 1 2 3 7 to 4 Interrupt request bit Functions b2 b1 b0 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 Priority is low. 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Priority is high. 0: No interrupt request has occurred. 1: Interrupt request has occurred. Not implemented. At reset RW 0 RW 0 RW 0 RW 0 RW Undefined -- Fig. 7.2.4 Structure of timer Bi interrupt control register (1) Interrupt priority level selection bits (bits 2 to 0) These bits select a timer Bi interrupt's priority level. When using timer Bi interrupts, select one priority level from levels 1 to 7. If a timer Bi interrupt request is generated, its priority level is compared with the processor interrupt priority level (IPL), and then the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this is applied when the interrupt disable flag (I) = "0.") When disabling timer Bi interrupts, set these bits to "0002" (Level 0). (2) Interrupt request bit (bit 3) This bit is set to "1" when a timer Bi interrupt request is generated. This bit is automatically cleared to "0" when the timer Bi interrupt request is accepted. This bit can be set to "1" or cleared to "0" by software. 7733 Group User's Manual 7-7 TIMER B 7.2 Block description 7.2.5 Port P6 direction register I/O pins of timer Bi are multiplexed with port P6. When using these pins as timer Bi's input pins, set the corresponding bits of the port P6 direction register to "0" in order to set these ports for the input mode. Figure 7.2.5 shows the relationship between the port P6 direction register and the timer Bi's input pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P6 direction register (address 1016) Bit Corresponding pin name 0 Pin P60/TA4OUT 1 Pin P61/TA4IN Functions 0: Input mode 1: Output mode When using these pins as timer Bi's input pins, set the corresponding bits to "0." At reset RW 0 RW 0 RW 0 RW 0 RW 2 Pin P62/INT0 3 Pin P63/INT1 4 Pin P64/INT2 0 RW 5 Pin P65/TB0IN 0 RW 6 Pin P66/TB1IN 0 RW 7 Pin P67/TB2IN/ 0 RW SUB represents that bits 0 to 4 are not used for timer B. Fig. 7.2.5 Relationship between port P6 direction register and timer Bi's input pins 7-8 7733 Group User's Manual TIMER B 7.2 Block description 7.2.6 Port function control register Figure 7.2.6 shows the structure of the port function control register. b7 b6 b5 b4 0 b3 b2 b1 b0 Port function control register (address 6D16) At reset RW 0 RW Sub-clock output selection bit/ *Port-XC selection bit = "0" (when the sub clock is not used) Timer B2 clock source selection Timer B2 (event counter mode) bit clock source selection (Note 1) 0: TB2IN input (event counter mode) 1: Main clock divided by 32 (clock timer) *Port-XC selection bit = "1" (when the sub clock is used) Sub-clock output selection 0: Pin P67/TB2IN/ SUB functions as a programmable I/O port. 1: Sub clock SUB is output from pin P67/TB2IN/ SUB. 0 RW 2 Timer B1 internal connect selection bit (Note 2) 0: No internal connection 1: Internal connection with timer B2 0 RW 3 Port P6 pull-up selection bit 0 0: No pull-up for pins P62/INT0 and P63/INT1 1: With pull-up for pins P62/INT0 and P63/INT1 0 RW 4 Must be fixed to "0." 0 RW 5 Port P6 pull-up selection bit 1 *Key input interrupt selection bit = "0" 0: No pull-up for pin P64/INT2 1: With pull-up for pin P64/INT2 *Key input interrupt selection bit = "1" 0: Pin P64/INT2 is a port with no pull-up. 1: Pin P64/INT2 is an input pin with pull-up and is used for the key input interrupt. 0 RW 6 Port P5 pull-up selection bit 0: No pull-up for pins P54/TA2OUT/KI0 to P57/TA3IN/KI3 1: With pull-up for pins P54/TA2OUT/KI0 to P57/TA3IN/KI3 0 RW 7 Key input interrupt selection bit 0: INT2 interrupt (TA2 IN and TA3IN inputs are assigned to pins P5 5 and P57.) 1: Key input interrupt (TA2IN and TA3 IN inputs are assigned to pins P7 2 and P73.) 0 RW Bit 0 1 Bit name Standby state selection bit Functions 0: Pins P0 to P3 are used for the external bus output. 1: Pins P0 to P3 are used for the port output. Port-Xc selection bit : Bit 4 of the oscillation circuit control register 0 (address 6C16) Notes 1: When the port-Xc selection bit = "0" and timer B2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: When timer B1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 and 3 to 7 are not used for timer B. Fig. 7.2.6 Structure of port function control register 7733 Group User's Manual 7-9 TIMER B 7.3 Timer mode 7.3 Timer mode (Bits 1 and 0 of timer Bi mode register = "00 2") In this mode, a count source internally generated is counted. (Refer to Table 7.3.1.) Figure 7.3.1 shows the structures of the timer Bi mode register and timer Bi register in the timer mode. Table 7.3.1 Specifications of timer mode Item Specifications Count source Clock f 2 , f16, f 64, or f 512 Count operation Countdown At an underflow, the reload register's contents is reloaded, and counting is continued. Division ratio Count start condition 1 n: Set value in the timer Bi register (n + 1) When the count start flag is set to "1." When the count start flag is cleared to "0." Count stop condition Interrupt request occurrence timing At an underflow Programmable I/O port (Pin TB2IN is a programmable I/O port or SUB output pin.) Pin TBi IN's function Read from timer A counter value can be read out by reading the timer Bi register. Write to timer While counting is stopped When a value is written to the timer Bi register, it is written to both of the reload register and counter. While counting is in progress When a value is written to the timer Bi register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Clocks f 2, f16 , f64 , and f 512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." 7-10 7733 Group User's Manual TIMER B 7.3 Timer mode b7 b6 b5 X b4 b3 b2 b1 b0 X X 0 0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Bit 0 Bit name Functions At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW Undefined -- Undefined RO 0 RW 0 RW At reset RW 15 to 0 Values 000016 to FFFF16 can be set. UnAssuming that the set value = n, counter defined divides the count source frequency by (n + 1). At reading this register, the counter value is read out. RW Operating mode selection bits b1 b0 0 0: Timer mode 1 2 These bits are ignored in the timer mode. 3 4 *Timer B0 mode register Must be fixed to "0." *Timer B1 and B2 mode registers Not implemented. b4 b3 5 This bit is ignored in the timer mode and is undefined at reading. 6 Count source selection bits 7 b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." (b15) b7 (b8) b0 b7 b0 Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) Bit Functions Fig. 7.3.1 Structures of timer Bi mode register and timer Bi register in timer mode 7733 Group User's Manual 7-11 TIMER B 7.3 Timer mode 7.3.1 Setting for timer mode Figure 7.3.2 shows an initial setting example for registers related to the timer mode. Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter "4. INTERRUPTS." 7-12 7733 Group User's Manual TIMER B 7.3 Timer mode Selection of the timer mode and the count source b7 b0 X 0 X X 0 0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Timer mode is selected. Must be fixed to "0" (for i = 0). Count source selection bits b7 b6 0 0 1 1 X: It may be "0" or "1." 0: Clock f 2 1: Clock f 16 0: Clock f 64 1: Clock f 512 Clocks f2, f16, f64, and f512 : Refer to chapter "14. CLOCK GENERATING CIRCUIT." Setting of the division ratio (b8) b0 b7 (b15) b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Values 000016 to FFFF16 (n) can be set. Counter divides count source frequency by (n + 1). Setting of the interrupt priority level b7 b0 Timer Bi interrupt control register (addresses 7A16 to 7C16) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Setting of the count start flag to "1" b7 b0 Count start flag (address 4016) Timer B0 count start flag Timer B1 count start flag AAA AAA AAA Timer B2 count start flag Counting is started. Fig. 7.3.2 Initial setting example for registers related to timer mode 7733 Group User's Manual 7-13 TIMER B 7.3 Timer mode 7.3.2 Count source In the timer mode, by the count source selection bits (bits 7 and 6 at addresses 5B16 to 5D16 ), a count source can be selected. Table 7.3.2 lists the relationship between the count source selection bits and count source. Table 7.3.2 Relationship between count source selection bits and count source b7 b6 Count source Frequency of count source When system clock = 25 MHz When system clock = 16 MHz When system clock = 8 MHz 0 0 f2 12.5 MHz 8 MHz 4 MHz 0 1 f 16 1.5625 MHz 1 0 f 64 390.625 kHz 1 MHz 250 kHz 500 kHz 125 kHz f 512 1 1 48.8281 kHz 31.25 kHz 15.625 kHz Clocks f 2 , f16 , f64 , f512, and system clock: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: This is applied when the system clock selection bit (bit 3 at address 6C16) = "0" and the main clock division selection bit (bit 0 at address 6F16) = "0." (For details, refer to chapter "14. CLOCK GENERATING CIRCUIT.") 7-14 7733 Group User's Manual TIMER B 7.3 Timer mode 7.3.3 Operation in timer mode When the count start flag is set to "1," the counter starts counting of the count source. When an underflow occurs, the reload register's contents is reloaded, and then counting is continued. The timer Bi interrupt request bit is set to "1" when the underflow occurs in . After this, the interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Figure 7.3.3 shows an operation example in the timer mode. n = Reload register's contents Counter contents (Hex.) FFFF16 Counting is started. 1 / fi (n + 1) Counting is stopped. n Counting is restarted. 000016 Time Set to "1" by software Count start flag Cleared to "0" by software Set to "1" by software "1" "0" Timer Bi interrupt "1" request bit "0" fi = Frequency of count source (f2, f16, f64, f512) Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software Fig. 7.3.3 Operation example in timer mode 7733 Group User's Manual 7-15 TIMER B 7.3 Timer mode [Precautions in timer mode] While counting is in progress, by reading out the timer Bi register, the counter value can be read at an arbitrary timing. However, when reading is performed at the reload timing shown in Figure 7.3.4, value "FFFF16" is read out. If reading is performed in the period from when a value is set into the timer Bi register with the counter stopped until the counter starts counting, the set value is correctly read out. Reload Counter value (Hex.) 2 1 0 Read value (Hex.) 2 1 0 n FFFF n - 1 n = Reload register's contents Fig. 7.3.4 Timer Bi register read out 7-16 n-1 7733 Group User's Manual Time TIMER B 7.4 Event counter mode 7.4 Event counter mode (Bits 1 and 0 of timer Bi mode register = "01 2") In this mode, an external signal is counted. (Refer to Table 7.4.1.) Figure 7.4.1 shows the structures of the timer Bi mode register and timer Bi register in the event counter mode. Table 7.4.1 Specifications of event counter mode Specifications Item External signal input to pin TBi IN (Notes 1 and 2). Count source Count operation "Falling edge," "Rising edge," or "Falling and Rising edges" can be selected as the valid edge of the count source by software. Countdown At an underflow, the reload register's contents is reloaded, and counting is continued. Division ratio Count start condition 1 n: Set value in the timer Bi register (n + 1) When the count start flag is set to "1." When the count start flag is cleared to "0." Interrupt request occurrence timing At an underflow Count source input Pin TBi IN's function Count stop condition Read from timer A counter value can be read out by reading the timer Bi register. Write to timer While counting is stopped When a value is written to the timer Bi register, it is written to both of the reload register and counter. While counting is in progress When a value is written to the timer Bi register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Notes 1: When the timer B1 internal connect selection bit (bit 2 at address 6D 16 ) = "1," timer B1 counts the timer B2's underflow signal. (Refer to section "7.4.3 Selectable functions.") 2: When using timer B2 in the event counter mode, set both of the port-Xc selection bit (bit 4 at address 6C16) and the sub-clock output selection bit/Timer B2 clock source selection bit (bit 1 at address 6D16) to "0." When one of or both of these bits = "1," timer B2 functions as a clock timer. (Refer to section "7.6 Clock timer.") 7733 Group User's Manual 7-17 TIMER B 7.4 Event counter mode b7 X b6 b5 X X b4 b3 b2 b1 b0 0 1 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Bit At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW *Timer B1 and B2 mode registers Not implemented. Undefined -- 5 This bit is ignored in the event counter mode and is undefined at reading. Undefined RO 6 These bits are ignored in the event counter mode. 0 RW 0 RW At reset RW Un15 to 0 Values 000016 to FFFF16 can be set. defined Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. RW 0 Bit name Functions Operating mode selection bits b1 b0 0 1: Event counter mode 1 2 Count polarity selection bits 3 4 b3 b2 0 0: Counting is performed at the falling edge of the external signal. 0 1: Counting is performed at the rising edge of the external signal. 1 0: Counting is performed at both falling and rising edges of the external signal. 1 1: Do not select. *Timer B0 mode register Must be fixed to "0." 7 (b15) b7 (b8) b0 b7 b0 Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) Bit Functions Fig. 7.4.1 Structures of timer Bi mode register and timer Bi register in event counter mode 7-18 7733 Group User's Manual TIMER B 7.4 Event counter mode 7.4.1 Setting for event counter mode Figure 7.4.2 shows an initial setting example for registers related to the event counter mode. Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter "4. INTERRUPTS." 7733 Group User's Manual 7-19 TIMER B 7.4 Event counter mode Selection of the event counter mode and the count polarity b7 b0 X X X 0 0 1 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Event counter mode is selected. Count polarity selection bits b3b2 0 0: Counts at falling edge of external signal. 0 1: Counts at rising edge of external signal. 1 0: Counts at both of falling and rising edges of external signal. 1 1: Do not select. Must be fixed to "0" (for i = 0). X: It may be "0" or "1." Setting of the division ratio (b15) b7 (b8) b0 b7 b0 Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) Values 000016 to FFFF16 (n) can be set. Counter divides count source frequency by (n + 1). Setting of the interrupt priority level b7 b0 Timer Bi interrupt control register (addresses 7A16 to 7C16) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Setting of the port P6 direction register b7 b0 Port P6 direction register (address 1016) Pin TB0IN Pin TB1IN Clear the corresponding bit to "0." Pin TB2IN Selection of the timer B1 internal connection b7 b0 0 Port function control register (address 6D16) Timer B1 internal connect selection bit 0: No internal connection 1: Internal connection with timer B2 Setting of the count start flag to "1" b7 b0 Count start flag (address 4016) Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag AAA AAA AAA Counting is started. Fig. 7.4.2 Initial setting example for registers related to event counter mode 7-20 7733 Group User's Manual TIMER B 7.4 Event counter mode 7.4.2 Operation in event counter mode When the count start flag is set to "1," the counter starts counting of the count source. The counter counts the count source's valid edges. When an underflow occurs, the reload register's contents is reloaded, and then counting is continued. The timer Bi interrupt request bit is set to "1" when the underflow occurs in . After this, the interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Figure 7.4.3 shows an operation example in the event counter mode. n = Reload register's contents Counter contents (Hex.) FFFF16 Counting is started. Counting is stopped. n Counting is restarted. 000016 Time Set to "1" by software Count start flag Cleared to "0" by software Set to "1" by software "1" "0" Timer Bi interrupt "1" request bit "0" Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software Fig. 7.4.3 Operation example in event counter mode 7733 Group User's Manual 7-21 TIMER B 7.4 Event counter mode 7.4.3 Selectable functions Timer B1 internal connection is described below. (1) Timer B1 internal connection When the timer B1 internal connect selection bit (bit 2 at address 6D16) is set to "1," timer B1 is internally connected to timer B2 and counts the timer B2's underflow signal. Accordingly, timers B2 and B1 function as a 32-bit (16 bits + 16 bits) timer and counts the timer B2's count source. This function can be used when timer B2 operates in the timer or event counter mode, or as a clock timer. Figure 7.4.4 shows connection between timers B2 and B1 when timer B1 internal connection is selected. Figure 7.4.5 shows structures of the timer B1 mode register and port function control register when timer B1 internal connection is selected. Figure 7.4.6 shows an operation example when timer B1 internal connection is selected. Timer B2 Timer mode Event counter mode Clock timer TB1IN Timer B1 (Event counter mode) Reload register (16) Reload register (16) Counter (16) Counter (16) Timer B2 count source Timer B1 internal connect selection bit Timer B1 interrupt request bit Timer B2 interrupt request bit Fig. 7.4.4 Connection between timers B2 and B1 when timer B1 internal connection is selected b7 b0 AA X X X X 0 1 0 1 b7 0 Timer B1 mode register (address 5C16) b0 1 Port function control register (address 6D16) X: It may be "0" or "1." Fig. 7.4.5 Structures of timer B1 mode register and port function control register when timer B1 internal connection is selected 7-22 7733 Group User's Manual TIMER B 7.4 Event counter mode Timer B1/B2 count start flag Timer B2 counter's content (Hex.) Set to "1" by software 3 0 Time "1" Timer B1 counter's contents (Hex.) Timer B2 interrupt request bit "0" 2 0 Timer B1 interrupt request bit "1" "0" :Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software The above is applied in the following case. Set value of timer B2 register = "000316" Set value of timer B1 register = "000216" Fig. 7.4.6 Operation example when timer B1 internal connection is selected 7733 Group User's Manual 7-23 TIMER B 7.4 Event counter mode [Precautions in event counter mode] 1. While counting is in progress, by reading out the timer Bi register, the counter value can be read at an arbitrary timing. However, when reading is performed at the reload timing shown in Figure 7.4.7, value "FFFF 16" is read out. If reading is performed in the period from when a value is set into the timer Bi register with the counter stopped until the counter starts counting, the set value is correctly read out. Reload Counter value (Hex.) 2 1 0 Read value (Hex.) 2 1 0 n n-1 FFFF n - 1 n = Reload register's contents Time Fig. 7.4.7 Timer Bi register read out 2. The internal connect function between timer B2 and timer B1 can be used when timer B2 operates in the timer or event counter mode, or as a clock timer. Do not use this function in the pulse period/pulse width measurement mode. 7-24 7733 Group User's Manual TIMER B 7.5 Pulse period/Pulse width measurement mode 7.5 Pulse period/Pulse width measurement mode (Bits 1 and 0 of timer Bi mode register = "10 2 ") In this mode, an external signal's pulse period or pulse width is measured. (Refer to Table 7.5.1.) Figure 7.5.1 shows the structures of the timer Bi mode register and timer Bi register in the pulse period/pulse width measurement mode. Pulse period measurement The pulse period of an external signal which is input to pin TBiIN is measured. Pulse width measurement The pulse width ("L" level width and "H" level width) of an external signal which is input to pin TBiIN is measured. Note: When the port-Xc selection bit (bit 4 at address 6C16 ) = "1," timer B2 functions as a clock timer. Accordingly, pulse period/pulse width measurement cannot be performed. Table 7.5.1 Specifications of pulse period/pulse width measurement mode Item Specifications Count source Clock f2 , f 16, f 64, or f 512 Count operation Countup When valid edge of the measurement pulse is input, the counter value is transferred to the reload register. And then, the counter value is cleared to "0000 16 ," and counting is continued. Count start condition When the count start flag is set to "1." Count stop condition Interrupt request occurrence timing When the count start flag is cleared to "0." When the valid edge of the measurement pulse is input (Note 1). Pin TBiIN's function At an overflow (Simultaneously, the overflow flag is set to "1.") Measurement pulse input Read from timer By reading the timer Bi register, the reload register's contents (Measurement result) is read out (Note 2). Write to timer Ignored Clocks f 2 , f16, f 64, and f 512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Overflow flag: A flag used to identify the source of an interrupt request occurrence. Notes 1: An interrupt request is not generated when the first valid edge is input after counting starts. 2: From when counting starts until the second valid edge is input, a value obtained by reading the timer Bi register is undefined. 7733 Group User's Manual 7-25 TIMER B 7.5 Pulse period/Pulse width measurement mode b7 b6 b5 b4 b3 b2 b1 b0 1 0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Bit 0 Bit name Functions Operating mode selection bits b1 b0 1 0: Pulse period/pulse width measurement mode 1 2 b3 b2 Measurement mode selection bits 0 0: Pulse period measurement ( interval between falling edges of the measurement pulse) 0 1: Pulse period measurement Interval between rising edges of the measurement pulse) 1 0: Pulse width measurement (Interval from a falling edge to a rising edge, and from a rising edge to a falling edge of the measurement pulse) 1 1: Do not select. 3 4 *Timer B0 mode register Must be fixed to "0." *Timer B1 and B2 mode registers Not implemented. 5 Timer Bi overflow flag (Note) 6 Count source selection bits 0: No overflow 1: Overflow b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 7 At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW Undefined -- 1 RO 0 RW 0 RW Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: Timer Bi overflow flag is cleared to "0" when writing to the timer Bi mode register is performed with the count start flag = "1." This flag cannot be set to "1" by software. (b15) b7 (b8) b0 b7 b0 Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) Bit Functions At reset RW 15 to 0 The result of the pulse period or pulse width Undefined measurement is read out. RO Fig. 7.5.1 Structures of timer Bi mode register and timer Bi register in pulse period/pulse width measurement mode 7-26 7733 Group User's Manual TIMER B 7.5 Pulse period/Pulse width measurement mode 7.5.1 Setting for pulse period/pulse width measurement mode Figure 7.5.2 shows an initial setting example for registers related to the pulse period/pulse width measurement mode. Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter "4. INTERRUPTS." 7733 Group User's Manual 7-27 TIMER B 7.5 Pulse period/Pulse width measurement mode Selection of the pulse period/pulse width measurement mode and each function b7 b0 0 1 0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Pulse period/Pulse width measurement mode is selected. Measurement mode selection bits b3 b2 0 0: Pulse period measurement (Interval between falling edges) 0 1: Pulse period measurement (Interval between rising edges) 1 0: Pulse width measurement 1 1: Do not select. Must be fixed to "0" (for i = 0). Timer Bi overflow flag (Note) 0: No overflow 1: Overflow Count source selection bits b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Setting of the interrupt priority level b7 b0 Timer Bi interrupt control register (addresses 7A16 to 7C16) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Setting of the port P6 direction register b7 b0 Port P6 direction register (address 1016) Pin TB0IN Pin TB1IN Clear the corresponding bit to "0." Pin TB2IN Setting of the count start flag to "1" b7 b0 Count start flag (address 4016) Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag AAA AAA AAA Counting is started. Note: The timer Bi overflow flag is a read-only flag. This flag is cleared to "0" when writing to timer Bi mode register is performed with the count start flag = "1." Fig. 7.5.2 Initial setting example for registers related to pulse period/pulse width measurement mode 7-28 7733 Group User's Manual TIMER B 7.5 Pulse period/Pulse width measurement mode 7.5.2 Count source In the pulse period/pulse width measurement mode, by the count source selection bits (bits 7 and 6 at addresses 5B 16 to 5D16 ), a count source can be selected. Table 7.5.2 lists the relationship between the count source selection bits and count source. Table 7.5.2 Relationship between count source selection bits and count source b7 b6 Count source 0 0 f2 0 1 1 1 0 1 f16 f64 Frequency of count source When system clock = 25 MHz 12.5 MHz 1.5625 MHz When system clock = 16 MHz When system clock = 8 MHz 8 MHz 4 MHz 1 MHz 500 kHz 390.625 kHz 250 kHz 125 kHz 48.8281 kHz 31.25 kHz 15.625 kHz Clocks f 2, f 16, f 64, f 512, and system clock: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: This is applied when the system clock selection bit (bit 3 at address 6C16) = "0" and the main clock division selection bit (bit 0 at address 6F16) = "0." (For details, refer to chapter "14. CLOCK GENERATING CIRCUIT.") f512 7733 Group User's Manual 7-29 TIMER B 7.5 Pulse period/Pulse width measurement mode 7.5.3 Operation in pulse period/pulse width measurement mode When the count start flag is set to "1," the counter starts counting of the count source. When a valid edge of the measurement pulse is input, the counter value is transferred to the reload register. (Refer to "(1) Pulse period/Pulse width measurement.") After a transfer in , the counter value becomes "000016, " and the counter continues counting. The timer Bi interrupt request bit is set to "1" when the counter value becomes "0000 16 " in ,(Note). After this, the interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Operations to are repeated. Note: Timer Bi interrupt request is not generated when the first valid edge is input after counting starts. (1) Pulse period/Pulse width measurement Whether to measure the pulse period or the pulse width of an external signal can be selected by the measurement mode selection bits (bits 3 and 2 at addresses 5B 16 to 5D 16 ). Table 7.5.3 lists the relationship between the measurement mode selection bits and the pulse period/pulse width measurement. Make sure that the measurement interval from the falling edge to the rising edge and that of from the rising edge to the falling edge are two cycles of the count source or more. When measuring pulse width of a signal whose duty ratio is not 50%, identify whether the measurement result is the "H" level width or the "L" level width by software. Table 7.5.3 Relationship between measurement mode selection bits and pulse period/pulse width measurement b2 Pulse period/Pulse width measurement Measurement interval (Valid edge) b3 0 0 0 1 1 0 7-30 Pulse period measurement From falling edge to falling edge (Falling edge) From rising edge to rising edge (Rising edge) Pulse width measurement From falling edge to rising edge, and from rising edge to falling edge (Falling and Rising edges) 7733 Group User's Manual T IME R B 7.5 Pulse period/Pulse width measurement mode (2) Timer Bi overflow flag When a measurement pulse's valid edge is input or an overflow occurs, a timer Bi interrupt request is generated. The timer Bi overflow flag is used to identify the cause of an interrupt request occurrence, in other words, determine whether it is an overflow or a valid edge input. When an overflow occurs, the timer Bi overflow flag is set to "1." Therefore, the source of the interrupt request occurrence can be identified by checking the timer Bi overflow flag's state in the interrupt routine. The timer Bi overflow flag is cleared to "0" at the next count timing of the count source when a value is written to the timer Bi mode register with the count start flag = "1." The timer Bi overflow flag is a read-only flag. Do not use this flag for detection of overflow timing. Figure 7.5.3 shows the operation during pulse period measurement. Figure 7.5.4 shows the operation during pulse width measurement. Count source Measurement pulse "H" "L" Transferred (Undefined value) Reload register @ @ Counter Transfer timing Transferred (Measured value) Timing when counter is cleared to "000016" Count start flag "1" "0" Timer Bi interrupt "1" request bit "0" Timer Bi overflow flag "1" Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software "0" Initialization of the counter because of measurement completion Overflow The above is applied when measurement is performed from one falling edge of the measurement pulse until the next falling edge of that. Fig. 7.5.3 Operation during pulse period measurement 7733 Group User's Manual 7-31 TIMER B 7.5 Pulse period/Pulse width measurement mode Count source Measurement pulse "H" "L" Transferred (Undefined value) Transferred (Measured value) Transferred (Measured value) Transferred (Measured value) Reload register Counter Transfer timing Timing when counter is cleared to "000016" Count start flag "1" "0" Timer Bi interrupt "1" request bit "0" Timer Bi overflow flag "1" Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software "0" Initialization of the counter because of measurement completion Overflow Fig. 7.5.4 Operation during pulse width measurement 7-32 7733 Group User's Manual TIMER B 7.5 Pulse period/Pulse width measurement mode [Precautions in pulse period/pulse width measurement mode] 1. A timer Bi interrupt request is generated by the following sources: The measurement pulse's valid edge which is input An overflow The interrupt request source shown above can be determined by the timer Bi overflow flag. 2. At reset, the timer Bi overflow flag is set to "1." This flag can be cleared to "0" by performing writing to the timer Bi mode register with the count start flag = "1." 3. When the first valid edge is input after counting starts, an undefined value is transferred to the reload register. At this time, a timer Bi interrupt request is not generated. 4. At start of counting, the counter value is undefined. Therefore, there is a possibility that a timer Bi interrupt request is generated by an overflow which occurs immediately after counting starts. 5. When the measurement mode selection bits are changed after counting starts, the timer Bi interrupt request bit is set to "1." Note that the timer Bi interrupt request bit does not change if the same value as before is written to the measurement mode selection bits. 6. When an input signal to pin TBi IN is affected by noise or others, there is a possibility that the counter cannot perform the exact measurement. We recommend to verify, by software, that the measurement values are within a constant range. 7733 Group User's Manual 7-33 TIMER B 7.6 Clock timer 7.6 Clock timer Timer B2 functions as a clock timer on the following condition (Refer to Table 7.6.1.): When the port-Xc selection bit (bit 4 at address 6C16) = "1" When the port-Xc selection bit = "0" and the timer B2 clock source selection bit (bit 1 at address 6D16 ) = "1" Figure 7.6.1 shows the structures of the timer B2 mode register and timer B2 register when a clock timer is used. Table 7.6.1 Specifications of clock timer Item Count source Count operation Division ratio Specifications fc32 (Sub clock divided by 32: f(XCIN)/32), or Main clock divided by 32: f(XIN )/32) Countdown At an underflow, the reload register's contents is reloaded, and counting is continued. 1 (n + 1) n: Set value in the timer B2 register Count start condition Count stop condition When the count start flag is set to "1." Interrupt request occurrence timing At an underflow Pin TB2 IN's function Read from timer Programmable I/O port or SUB output pin A counter value can be read out by reading the timer B2 register. Write to timer While counting is stopped When the count start flag is cleared to "0." When a value is written to the timer B2 register, it is written to both of the reload register and counter. While counting is in progress Clocks fc 32 When a value is written to the timer B2 register, it is written only to the reload register. (Transferred to the counter at the next reload time.) and f(X CIN): Refer to chapter "14. CLOCK GENERATING CIRCUIT." Either of f(X CIN)/32 or f(X IN)/32 can be selected as the clock timer's count source, fc32 . The way to generate f(X CIN)/32 is different from that for clocks whose source is the system clock (e.g., internal clock , clocks f 2 to f 512, and so on). (Refer to chapter "14. CLOCK GENERATING CIRCUIT.") f(X CIN )/32 is not affected by the system clock selection bit and system clock stop bit at wait state (bits 3 and 5 at address 6C16). Therefore, in the wait mode, (Refer to chapter "11. STOP AND WAIT MODES.") only the clock timer can operate by itself. In other words, it is possible to supply fc32 only. Oppositely, the way to generate f(XIN )/32 is the same as that for the system clock. Therefore, when the system clock stop bit at wait state = "1," fc32 is not supplied in the wait mode. Figure 7.6.2 shows the structure of the clock timer. 7-34 7733 Group User's Manual TIMER B 7.6 Clock timer b7 b6 b5 X X X b4 b3 b2 b1 b0 0 1 0 1 Timer B2 mode register (address 5D16) Bit Functions (b8) b0 b7 RW 0 Must be fixed to "1" for the clock timer. 0 RW 1 Must be fixed to "0" for the clock timer. 0 RW 2 Must be fixed to "1" for the clock timer. 0 RW 3 Must be fixed to "0" for the clock timer. 0 RW 4 Not implemented. Undefined -- 5 This bit is ignored for the clock timer. Undefined RO 6 These bits are ignored for the clock timer. 0 RW 0 RW 7 (b15) b7 At reset b0 Timer B2 register (addresses 5516 and 5416) Bit Functions 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. At reset RW Undefined RW Fig. 7.6.1 Structures of timer B2 mode register and timer B2 register when clock timer is used 7733 Group User's Manual 7-35 TIMER B 7.6 Clock timer Timer B2 reload register Clock prescaler Sub clock : f(XCIN) 1/32 fc32 Timer B2 interrupt request bit Clock timer (Timer B2 counter) Main clock : f(XIN) System clock (Clock source for f2 to f512, and internal clock Fig. 7.6.2 Structure of clock timer 7-36 7733 Group User's Manual ) TIMER B 7.6 Clock timer 7.6.1 Setting for clock timer Figure 7.6.3 shows an initial setting example for registers related to the clock timer. Note that when using interrupts, setting for enabling interrupts is required. For details, refer to chapter "4. INTERRUPTS." When using sub clock (Xc) Selection of the clock timer b0 b7 Selection of the clock timer Oscillation circuit control register 0 (address 6C16) 1 Port-Xc selection bit 1: XCIN-XCOUT selected (Sub clock used) b0 b7 X X X 0 1 0 1 When not using sub clock (Xc) b0 b7 Oscillation circuit control register 0 (address 6C16) 0 Port-Xc selection bit 0: Ports P77 and P76 selected (Sub clock not used) b0 b7 Timer B2 mode register (address 5D16) Port function control register (address 6D16) 1 X: It may be "0" or "1." Sub-clock output selection bit/Timer B2 clock source selection bit Timer B2 (Event counter mode) clock source selection 1: Main clock divided by 32 b7 b0 X X X 0 1 0 1 Timer B2 mode register (address 5D16) X: It may be "0" or "1." Setting of the division ratio (b15) b7 (b8) b0 b7 b0 Timer B2 register (addresses 5516 and 5416) Values 000016 to FFFF16 (n) can be set. Counter divides the count source frequency by (n + 1). Setting of the interrupt priority level b7 b0 Timer B2 interrupt control register (address 7C16) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Initialization of the clock prescaler By using LDM instruction, write value "8016" to address 6F16. Setting of the count start flag to "1" b7 1 b0 Count start flag (address 4016) Timer B2 count start flag AAAAA AAAAA Counting is started. AAAAA AAAAA AAAAA Note: After oscillation of an oscillator connected to the sub-clock oscillation circuit is stabilized, set the count start flag to "1." Fig. 7.6.3 Initial setting example for registers related to clock timer 7733 Group User's Manual 7-37 TIMER B 7.6 Clock timer 7.6.2 Operation of clock timer When the count start flag is set to "1," the counter starts counting of the count source. When an underflow occurs, the reload register's contents is reloaded, and then counting is continued. The timer B2 interrupt request bit is set to "1" when the underflow occurs in . After this, the interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Timer B2 counter's contents (Hex.) For example, if f(XCIN) = 32.768 kHz, a timer B2 interrupt request can be issued every second when value "3FF16" is set into the timer B2 register (addresses 54 16 and 5516) and every minute when value "EFFF16" is set into the register. Figure 7.6.4 shows an operation example of clock timer. FFFF16 n Timer B2 counter's contents (Hex.) 000016 FFFF16 n 000016 Cleared to "0" by software Set to "1" by software "1" Count start flag "0" Timer B1 "1" interrupt request bit "0" Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software Fig. 7.6.4 Operation example of clock timer 7-38 7733 Group User's Manual TIMER B 7.6 Clock timer [Precautions for clock timer] 1. While counting is in progress, by reading out the timer B2 register, the counter value can be read at an arbitrary timing. However, when reading is performed at the reload timing shown in Figure 7.6.5, value "FFFF 16" is read out. If reading is performed in the period from when a value is set into the timer B2 register with the counter stopped until the counter starts counting, the set value is correctly read out. Reload Counter value (Hex.) 2 1 0 Read value (Hex.) 2 1 0 n n-1 FFFF n - 1 n = Reload register's contents Time Fig. 7.6.5 Timer B2 register read out 2. For the clock prescaler reset, refer to section "14.3.4 Clock prescaler reset." 7733 Group User's Manual 7-39 TIMER B 7.6 Clock timer MEMO 7-40 7733 Group User's Manual CHAPTER 8 SERIAL I/O 8.1 Overview 8.2 Block description 8.3 Clock synchronous serial I/O mode 8.4 Clock asynchronous serial I/O (UART) mode SERIAL I/O 8.1 Overview The serial I/O consists of 3 channels: UART0, UART1 and UART2. They each have a dedicated timer for generating a transfer clock and can operate independently. 8.1 Overview UARTi (i = 0 to 2) has the following two operating modes: clock synchronous serial I/O and clock asynchronous serial I/O (UART) modes. Except for a few functions in the clock synchronous serial I/O mode, UART0, UART1 and UART2 have the same functions. Clock synchronous serial I/O mode Transmitter and receiver use the same clock as a transfer clock. Transfer data has a length of 8 bits. Clock asynchronous serial I/O (UART) mode Transfer rate and transfer data format can arbitrarily be set. The transfer data length can be selected from the following three types: 7 bits, 8 bits, and 9 bits. Figure 8.1.1 shows the transfer data formats in each operating mode. Table 8.1.1 shows the differences between UART0, UART1 and UART2. Clock synchronous serial I/O mode UART mode Transfer data length : 7 bits Transfer data length : 8 bits Transfer data length : 9 bits Fig. 8.1.1 Transfer data formats in each operating mode 8-2 7733 Group User's Manual SERIAL I/O 8.1 Overview Table 8.1.1 Differences between UART0, UART1 and UART2 _______ CTS input/ Data output/CLK Multiple Communication RTS output polarity/transfer format clocks output function select function function UART0 Clock synchronous or Both functions are *UART0 transmission Available Available asynchronous (UART) available. *UART0 reception mode is selectable. (2 systems) UART1 Clock synchronous or Both functions are *UART1 transmission Available Not available asynchronous (UART) available. *UART1 reception mode is selectable. (2 systems) _______ UART2 Clock synchronous or Only CTS input *UART2 transmission Not available Not available asynchronous (UART) function is available. /reception (Note 1) (Note 2) mode is selectable. (1 system) _______ Interrupt function Sleep function Available Available Not available Notes 1: The A-D conversion interrupt and UART2 transmission/reception interrupt share the interrupt vector addresses and the interrupt control register. When the UART2 mode is selected by specifying bits 2 to 0 of the UART2 transmit/receive mode register (address 64 16 ), the A-D conversion interrupt function cannot be used. 2: UART2 is fixed as follows. * Data output (TxD2 pin): CMOS output * Polarity of CLK2 : Transmit data is output at the falling edge of the transfer clock. Receive data is input at the rising edge of the transfer clock. When not transferring, CLK 2 pin's level is "H." (Used in the clock synchronous serial I/O mode) * Transfer format: LSB (the least significant bit) first 7733 Group User's Manual 8-3 SERIAL I/O 8.2 Block description 8.2 Block description Figure 8.2.1 shows the block diagram for serial I/O. Registers related to serial I/O are described below. Data bus (odd) Data bus (even) Bit converter (Note) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 Receive buffer register UART0 (Addresses 37 16, 3616) UART1 (Addresses 3F 16, 3E16) UART2 (Addresses 6B 16, 6A16) Receive register RxDi Clock source selection f2 f16 f64 f512 Baud rate register UART0 (Address 31 16) UART1 (Address 39 16) UART2 (Address 65 16 ) UART receive Clock synchronous Divider(1/16 ) Internal Divider [1/(n+1)] External Receive control circuit UART transmission Clock synchronous (Note) CLKi Divider(1/16 ) Transmission control circuit Clock synchronous (Internal clock) Divider (1/2 ) Clock synchronous (When internal clock is selected) Transfer clock Transfer clock Transmission register Clock synchronous (External clock) D8 D7 D6 D5 D4 D3 D2 D1 D0 Transmission buffer register Polarity reversing circuit CTSi / RTSi (Note) (Note) UART0 (Addresses 33 16, 3216) UART1 (Addresses 3B 16 , 3A16 ) UART2 (Addresses 67 16, 6616 ) Bit converter Data bus (odd) Note: The bit converter, the polarity reversing circuit and RTSi output function are not assigned for UART2. n: Value set to the UARTi baud rate register Fig. 8.2.1 Block diagram for serial I/O 8-4 TxDi 7733 Group User's Manual Data bus (even) SERIAL I/O 8.2 Block description 8.2.1 UARTi transmit/receive mode register Figures 8.2.2 and 8.2.3 show the structure of UARTi transmit/receive mode register. The serial I/O mode selection bits are used to select a UARTi's operating mode. For bits 4 to 6, refer to section "8.4.2 Transfer data format." For bit 7, refer to section "8.4.8 Sleep mode." b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive mode register (address 30 16) UART1 transmit/receive mode register (address 38 16) Bit 0 Functions Bit name Serial I/O mode selection bits 1 2 b2 b1 b0 0 0 0: Serial I/O is disabled. (P8 functions as a programmable I/O port.) 0 0 1: Clock synchronous serial I/O mode 0 1 0: Do not select. 0 1 1: Do not select. 1 0 0: UART mode (Transfer data length = 7 bits) 1 0 1: UART mode (Transfer data length = 8 bits) 1 1 0: UART mode (Transfer data length = 9 bits) 1 1 1: Do not select. At reset RW 0 RW 0 RW 0 RW 0 RW 3 Internal/External clock selection bit 4 Stop bit length selection bit 0: One stop bit (Valid in the UART mode.) (Note) 1: Two stop bits 0 RW 5 Odd/Even parity selection bit 0: Odd parity (Valid in the UART mode when 1: Even parity the parity enable bit = "1.") (Note) 0 RW 6 0: Parity is disabled. Parity enable bit (Valid in the UART mode.) (Note) 1: Parity is enabled. 0 RW 7 Sleep selection bit 0: The sleep mode is terminated. (Ignored.) (Valid in the UART mode.) (Note) 1: The sleep mode is selected. 0 RW 0: Internal clock 1: External clock Note: Bits 4 to 6 are ignored in the clock synchronous serial I/O mode. (They may be "0" or "1.") Fix bit 7 to "0." Fig. 8.2.2 Structure of UARTi transmit/receive mode register (1) 7733 Group User's Manual 8-5 SERIAL I/O 8.2 Block description b7 b6 b5 b4 b3 b2 b1 b0 UART2 transmit/receive mode register (address 64 16) Bit 0 Bit name Serial I/O mode selection bits (Note 1) 1 2 Functions b2 b1 b0 0 0 0: Serial I/O is ignored. (P7 functions as a programmable I/O port) 0 0 1: Clock synchronous serial I/O mode 0 1 0: 0 1 1: Do not select. 1 0 0: UART mode (Transfer data length = 7 bits) 1 0 1: UART mode (Transfer data length = 8 bits) 1 1 0: UART mode (Transfer data length = 9 bits) 1 1 1: Do not select. At reset RW 0 RW 0 RW 0 RW Internal/External clock selection bit 0: Internal clock 1: External clock 0 RW 4 Stop bit length selection bit (Valid in the UART mode.) (Note 2) 0: One stop bit 1: Two stop bits 0 RW 5 Odd/Even Parity selection bit (Valid in the UART mode when the parity enable bit = "1".) (Note 2) 0: Odd parity 1: Even parity 0 RW 6 Parity enable bit (Valid in the UART mode.) (Note 2) 0: Parity is disabled. 1: Parity is enabled. 0 RW 7 Not implemented. Undefined -- Notes 1: By specifying these bits, an A-D conversion interrupt or a UART2 transmit/receive interrupt is selected. When bits 2 to 0 = "0002," an A-D conversion interrupt is selected. When bits 2 to 0 = "001 2" or "1002 to 111 2," a UART2 transmit/receive interrupt is selected. 2: In the clock synchronous serial I/O mode, bits 4 to 6 are ignored. (They may be "0" or "1.") Fig. 8.2.3 Structure of UARTi transmit/receive mode register (2) 8-6 7733 Group User's Manual SERIAL I/O 8.2 Block description (1) Internal/External clock selection bit (bit 3) Clock synchronous serial I/O mode When an internal clock is selected by clearing this bit to "0," a clock which is specified with the BRG count source selection bits (bits 1 and 0 at addresses 3416, 3C16 and 6816) becomes the count source of BRGi (described later). At this time, the BRGi's output divided by 2 is the transfer clock. The transfer clock is output from the CLKi pin (Note). When an external clock is selected by setting this bit to "1," a clock input to the CLKi pin becomes the transfer clock. Note : When selecting an internal clock and performing only transmission in UART0, the number of the transfer clock output pins varies according to the contents of the transmit clock output pin selection bits (bits 5 and 4 at address 6E16). (Refer to section "8.3.1 Transfer clock.") UART mode When an internal clock is selected by clearing this bit to "0," a clock which is specified with the BRG count source selection bits (bits 1 and 0 at addresses 3416, 3C16 and 6816) becomes the count source of the BRGi (described later). At this time, the CLKi pin functions as a programmable I/O port. When an external clock is selected by setting this bit to "1," a clock input to the CLKi pin becomes the count source of BRGi . Note that, in the UART mode, the BRGi's output divided by 16 is always the transfer clock. BRGi: UARTi baud rate register (Refer to section "8.2.7 UARTi baud rate register (BRGi).") 7733 Group User's Manual 8-7 SERIAL I/O 8.2 Block description 8.2.2 UARTi transmit/receive control register 0 Figures 8.2.4 and 8.2.5 show the structure of UARTi transmit/receive control register 0. For bits 1 and 0, refer to section "(1) Internal/External clock selection bit" in page 8-7. For bits 7 to 4, refer to the description of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 0 (address 3 416) UART1 transmit/receive control register 0 (address 3C 16) Bit Bit name 0 BRG count source selection bits Functions At reset RW 0 RW 0 RW 0 RW 1 RO b1 b0 0 0: Clock f 2 0 1: Clock f 16 1 0: Clock f 64 1 1: Clock f 512 1 0: The CTS function is selected. 1: The RTS function is selected. 2 CTS /RTS function selection bit (Valid when the CTS /RTS enable bit is "0.") 3 Transmission register empty flag 0: Data is present in the transmission register. (Transmission is in progress.) 1: No data is present in the transmission register. (Transmission is completed.) 4 CTS/RTS enable bit 0: The CTS /RTS function is enabled. 1: The CTS /RTS function is disabled. (P80 and P8 4 function as programmable I/O ports.) 0 RW 5 Data output selection bit 0: Pin TxD i is set for CMOS output. 1: Pin TxDi is set for N-channel opendrain output. 0 RW 6 0: At the falling edge of the transfer CLK polarity selection bit clock, transmit data is output; at (This bit is used in the clock the rising edge of the transfer synchronous serial I/O mode.) clock, receive data is input. (Note) When not in transferring, pin CLK i's level is "H." 1: At the rising edge of the transfer clock, transmit data is output; at the falling edge of the transfer clock, receive data is input. When not in transferring, pin CLK i's level is "L." 0 RW 7 Transfer format selection bit (This bit is used in the clock synchronous serial I/O mode.) (Note) 0 RW 0: LSB (Least Significant Bit) first 1: MSB (Most Significant Bit) first Clocks f 2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: Fix bits 6 and 7 to "0" in the UART mode. Fig. 8.2.4 Structure of UARTi transmit/receive control register 0 (1) 8-8 7733 Group User's Manual SERIAL I/O 8.2 Block description b7 b6 b5 b4 b3 b2 b1 b0 UART2 transmit/receive control register 0 (address 68 16) Bit 0 Bit name BRG count source selection bits 1 Functions b1 b0 0 0: Clock f 2 0 1: Clock f 16 1 0: Clock f 64 1 1: Clock f 512 At reset RW 0 RW 0 RW 2 CTS enable bit 0: The CTS function is enabled. 1: The CTS function is disabled. (P8 0 and P84 function as programmable I/O ports.) 0 RW 3 Transmission register empty flag 0: Data is present in the transmission register. (Transmission is in progress.) 1: No data is present in the transmission register. (Transmission is completed.) 1 RO 7 to 4 Not implemented. Undefined Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Fig. 8.2.5 Structure of UARTi transmit/receive control register 0 (2) ____ ____ (1) CTS / RTS function selection bit (bit 2) (UART0, UART1) ____ ____ This bit becomes valid when the CTS / RTS enable bit____ (bit 6) is cleared to "0." When this bit is cleared to "0" in order to select the CTS function, the P8 0 and P8 4 pins function as ____ ____ CTS input pins. At this time, a "L"-level signal input to the CTS pin is one of the transmit conditions. ____ ____ When this bit is set to "1" in order to select the RTS function, the P80 and P84 pins function as RTS output pins. When the receive enable bit (bit 2 at addresses 35 16 , 3D 16 ) is "0" (in other words, ____ reception is disabled.), the RTS pin outputs "H" level. ____ In the clock synchronous serial I/O mode, the output level of RTS pin becomes "L" when receive conditions are satisfied; it becomes "H" when reception is started. Note that, when an internal clock ____ is selected (bit 3 at addresses 30 16 , 38 16 = "0"), the RTS function____ is ignored. In the clock asynchronous serial I/O mode, the output level of the RTS pin becomes "L" when receive enable bit is set to "1"; it becomes "H" when reception is started; it becomes "L" when the reception is completed. ____ (2) ____ CTS enable bit (bit 2) (UART2) CTS input pin is valid when this bit is set to "0." ____ A "L"-level signal input to the CTS pin is one of the transmit conditions. (3) Transmission register empty flag (bit 3) This flag is cleared to "0" when the contents of the UARTi transmission buffer register is transferred to the UARTi transmission register. When transmission is completed and the UARTi transmission register becomes empty, this flag is set to "1." 7733 Group User's Manual 8-9 SERIAL I/O 8.2 Block description 8.2.3 UARTi transmit/receive control register 1 Figure 8.2.6 shows the structure of UARTi transmit/receive control register 1. For bits 7 to 4, refer to the description of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (address 35 16) UART1 transmit/receive control register 1 (address 3D 16) UART2 transmit/receive control register 1 (address 69 16) Bit Bit name Functions At reset RW 0 Transmit enable bit 0: Transmission is disabled. 1: Transmission is enabled. 0 RW 1 Transmission buffer empty flag 0: Data is present in the transmission buffer register. 1: No data is present in the transmission buffer register. 1 RO 2 Receive enable bit 0: Reception is disabled. 1: Reception is enabled. 0 RW 3 Receive completion flag 0: No data is present in the receive buffer register. 1: Data is present in the receive buffer register. 0 RO 4 Overrun error flag (Note 1) 0: No overrun error is detected. 1: Overrun error is detected. 0 RO 5 Framing error flag (Notes 1 and 2) (Valid in the UART mode.) 0: No framing error is detected. 1: Framing error is detected. 0 RO 6 Parity error flag (Notes 1 and 2) (Valid in the UART mode.) 0: No parity error is detected. 1: Parity error is detected. 0 RO 7 Error sum flag (Notes 1 and 2) (Valid in the UART mode.) 0: No error is detected. 1: Error is detected. 0 RO Notes 1: Bits 4 to 7 are cleared to "0" when the serial I/O mode selection bits (bits 2 to 0 at addresses 3016, 3816) are cleared to "000 2" or when the receive enable bit is cleared to "0." (Bit 7 is cleared to "0" when all of bits 4 to 6 are "0.") Note also that bits 5 and 6 are cleared to "0" when the low-order byte of the UARTi receive buffer register (addresses 36 16, 3E16, 6A16) is read out. 2: Bits 5 to 7 are ignored in the clock synchronous serial I/O mode. Fig. 8.2.6 Structure of UARTi transmit/receive control register 1 8-10 7733 Group User's Manual SERIAL I/O 8.2 Block description (1) Transmit enable bit (bit 0) When this bit is set to "1," UARTi enters the transmit enable state. When this bit is cleared to "0" during transmission, UARTi enters the transmit disable state after the transmission which is in progress at this clearing is completed. (2) Transmission buffer empty flag (bit 1) This flag is set to "1" when data is transferred from the UARTi transmission buffer register to the UARTi transmission register. This flag is cleared to "0" when data is set to the UARTi transmission buffer register. (3) Receive enable bit (bit 2) When this bit is set to "1," UARTi enters the receive enable state. When this bit is cleared to "0" during reception, UARTi quits the reception immediately and enters the receive disable state. (4) Receive completion flag (bit 3) This flag is set to "1" in the following case; * when data is ready in the UARTi receive register and is transferred to the UARTi receive buffer register (in other words, when reception is completed). This flag is cleared to "0" in one of the following cases; * when the low-order byte of the UARTi receive buffer register is read out, * when the receive enable bit (bit 2) is cleared to "0," * when port P8 is used as a programmable I/O port by clearing the serial I/O mode selection bits (bits 2 to 0 at addresses 30 16, 38 16 and 64 16) to "000 2" 7733 Group User's Manual 8-11 SERIAL I/O 8.2 Block description 8.2.4 Serial transmit control register Figure 8.2.7 shows the structure of the serial transmit control register. The transmission clock output pin selection bits are valid only for UART0. For these bits, refer to section "8.3.1 Transfer clock." b7 b6 b5 b4 b3 b2 b1 b0 Serial transmit control register (address 6E 16) Bit Functions Bit name 3 to 0 Not implemented. 4 5 7, 6 Transmission clock output pin selection bits (Valid only in the clock synchronous serial I/O mode.) (Note) b5 b4 0 0: One transfer clock output pin (CLK 0) 0 1: Multiple transfer clock 1 0: output pins 1 1: Not implemented. Value "0" is read out from here. At reset RW Undefined -- 0 RW 0 RW 0 -- When using multiple transfer clock output pins, satisfy the following conditions: Serial I/O mode selection bits (bits 2 to 0 at address 30 16) = "001 2" Internal/external clock selection bit (bit 3 at address 30 16) = "0" CTS /RTS enable bit (bit 4 at address 34 16) = "1" Receive enable bit (bit 2 at address 35 16) = "0" (for cases and in Table 8.3.4) Transmission clock output pin selection bits = "01 2", "102", or "11 2" (Refer to Table 8.3.3.) Note: Bits 4 and 5 are ignored in the UART mode. (They may be "0" or "1.") Fig. 8.2.7 Structure of serial transmit control register 8-12 7733 Group User's Manual SERIAL I/O 8.2 Block description 8.2.5 UARTi transmission register and UARTi transmission buffer register Figure 8.2.8 shows the block diagram for the transmitter. Figure 8.2.9 shows the structure of the UARTi transmission buffer register. Data bus (odd) Data bus (even) Bit converter D8 D7 D6 D5 D4 D3 (Note) D2 D1 SP : Stop bit PAR : Parity bit Parity enabled 2SP SP SP 9-bit UART D0 UARTi transmission buffer register 8-bit UART 9-bit UART Clock sync. UART TxDi PAR 1SP Parity disabled Clock sync. 7-bit UART 8-bit UART Clock sync. 7-bit UART UARTi transmission register "0" Note: The bit converter is not assigned for UART2. Fig. 8.2.8 Block diagram for transmitter (b15) b7 (b8) b0 b7 b0 UART0 transmission buffer register (addresses 33 16, 3216) UART1 transmission buffer register (addresses 3B 16, 3A16) UART2 transmission buffer register (addresses 67 16, 6616) Functions Bit 8 to 0 The transmit data is set. 15 to 9 Not implemented. At reset RW Undefined WO Undefined -- Fig. 8.2.9 Structure of UARTi transmission buffer register 7733 Group User's Manual 8-13 SERIAL I/O 8.2 Block description Transmit data is set into the UARTi transmission buffer register. When the microcomputer operates in the clock synchronous serial I/O mode or when 7-bit or 8-bit length is selected as the transfer data's length in the UART mode, the transmit data is set into the low-order byte of this register. When 9-bit length is selected as the transfer data's length in the UART mode, the transmit data is set into the UARTi transmission buffer register as follows. Bit 8 of the transmit data is set into bit 0 of the high-order byte of the UARTi transmission buffer register. Bits 7 to 0 of the transmit data are set into the low-order byte of the UARTi transmission buffer register. When transmit conditions are satisfied, the transmit data which is set in the UARTi transmission buffer register is transferred to the UARTi transmission register, and then it is output from the TxDi pin synchronously with the transfer clock. The UARTi transmission buffer register becomes empty when data which is set in this register is transferred to the UARTi transmission register, so the next transmit data can be set. When the "MSB first" is selected in the clock synchronous serial I/O mode, bit position of set data is reversed, and then this data is written into the UARTi transmission buffer register as the transmit data. (Refer to section "8.3.2 Transfer data format.") Transmit operation itself is the same whichever format is selected, "LSB first" or "MSB first." When quitting the transmission which is in progress and setting the UARTi transmission buffer register again, follow the procedure described below. Clear the serial I/O mode selection bits (bits 2 to 0 at addresses 30 16, 38 16 and 64 16 ) to "000 2." (Serial I/O is ignored.) Set the serial I/O mode selection bits again. Set the transmit enable bit (bit 0 at addresses 3516, 3D16 and 6916) to "1" (in other words, transmission is enabled.) and set the transmit data into the UARTi transmission buffer register. 8-14 7733 Group User's Manual SERIAL I/O 8.2 Block description 8.2.6 UARTi receive register and UARTi receive buffer register Figure 8.2.10 shows the block diagram for the receiver. Figure 8.2.11 shows the structure of the UARTi receive buffer register. Data bus (odd) Data bus (even) Bit converter 0 0 0 0 0 0 0 D8 D7 9-bit UART 8-bit UART 9-bit UART Clock sync. SP : Stop bit PAR : Parity bit Parity enabled 2SP RxDi SP SP UART D6 D5 D4 D3 (Note) D2 D1 D0 UARTi receive buffer register PAR Parity disabled 1SP Clock sync. 7-bit UART 8-bit UART Clock sync. 7-bit UART UARTi receive register Note: The bit converter is not assigned for UART2. Fig. 8.2.10 Block diagram for receiver (b15) b7 (b8) b0 b7 b0 UART0 receive buffer register (addresses 37 16, 36 16) UART1 receive buffer register (addresses 3F 16, 3E 16) UART2 receive buffer register (addresses 6B 16, 6A16) Functions Bit 8 to 0 The receive data is read out from here. 15 to 9 Not implemented. A value of "0" is read out from here. At reset RW Undefined RO 0 -- Fig. 8.2.11 Structure of UARTi receive buffer register 7733 Group User's Manual 8-15 SERIAL I/O 8.2 Block description The UARTi receive register is used to convert serial data, which is input from the RxDi pin, into parallel data. This register takes a signal which is input from the RxDi pin by the 1 bit synchronously with the transfer clock. The UARTi receive buffer register is used to read receive data. When reception is completed, the receive data which is taken into the UARTi receive register is automatically transferred to the UARTi receive buffer register. Note that the contents of the UARTi receive buffer register is updated when the next data is ready in the UARTi receive register before data which has been transferred to the UARTi receive buffer register is read out (in other words, when an overrun error occurs). When "MSB first" is selected in the clock synchronous serial I/O mode, bit position of data in the UARTi receive buffer register is reversed, and then this data is read out as the receive data. (Refer to section "8.3.2 Transfer data format.") Receive operation itself is the same whichever format is selected, "LSB first" or "MSB first." The UARTi receive buffer register is initialized when the receive enable bit (bit 2 at addresses 3516, 3D 16 and 69 16) is set to "1" after clearing it to "0." Figure 8.2.12 shows the contents of the UARTi receive buffer register when reception is completed. High-order byte (addresses 37 16, 3F16, 6B 16) b7 <UART mode> (Transfer data length : 9 bits) 0 b0 0 0 0 0 0 Low-order byte (addresses 36 16, 3E16, 6A 16) b7 b0 0 Receive data (9 bits) <Clock synchronous serial I/O mode> During UART mode (Transfer data length : 8 bits) During UART mode (Transfer data length : 7 bits) 0 0 0 0 0 0 0 Same value as bit 7 in low-order byte 0 0 0 0 0 0 Same value as bit 6 in low-order byte Receive data (8 bits) 0 Receive data (7 bits) Fig. 8.2.12 Contents of UARTi receive buffer register when reception is completed 8-16 7733 Group User's Manual SERIAL I/O 8.2 Block description 8.2.7 UARTi baud rate register (BRGi) The UARTi baud rate register (BRGi) is an 8-bit timer used only for UARTi. It generates a transfer clock and has a reload register. Assuming that a value set in BRGi is "n" (n = 0016 to FF16 ), the BRGi divides the count source frequency by (n + 1). In the clock synchronous serial I/O mode, BRGi is valid when an internal clock is selected. At this time, the BRGi's output divided by 2 is the transfer clock. In the UART mode, the BRGi is always valid. At this time, the BRGi's output divided by 16 is the transfer clock. When a value is written to addresses 31 16, 39 16, and 6516 , the value is also written to the timer and the reload register whether transmission/reception is in progress or stopped. Therefore, when writing a value to these addresses, be sure to perform it while transmission/reception is stopped. Figure 8.2.13 shows the structure of BRGi and Figure 8.2.14 shows the block diagram of transfer clock generating section. b7 b0 UART0 baud rate register (address 31 16) UART1 baud rate register (address 39 16) UART2 baud rate register (address 65 16) Functions At reset RW 7 to 0 Values 00 16 to FF16 can be set. Undefined Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). WO Bit Fig. 8.2.13 Structure of UARTi baud rate register (BRGi) <Clock synchronous serial I/O mode> fi BRGi 1/2 Transmit control circuit Transfer clock for transmit operation Receive control circuit Transfer clock for receive operation 1/16 Transmit control circuit Transfer clock for transmit operation 1/16 Receive control circuit Transfer clock for receive operation fEXT <UART mode> fi fEXT BRGi fi : Clock selected with the BRG count source selection bits (f2, f16, f64, or f512) fEXT : Clock input to the CLKi pin (external clock) Fig. 8.2.14 Block diagram of transfer clock generating section 7733 Group User's Manual 8-17 SERIAL I/O 8.2 Block description 8.2.8 Interrupt control register related to UARTi When UARTi is used, the following interrupts can be used: UARTi transmission interrupt and UARTi reception interrupt. Each interrupt has its corresponding interrupt control register. However, in UART2, an interrupt for transmission and an interrupt for reception are controlled with the same register. Figure 8.2.15 shows the structure of interrupt control registers related to UARTi. For details about interrupts, refer to chapter "4 Interrupts." The UART2 transmission/reception interrupt and the A-D conversion interrupt share the same interrupt vector addresses and interrupt control register. Switching between the A-D conversion interrupt and the UART2 transmission/reception interrupt is performed with bits 2 to 0 of the UART2 transmission/reception mode register. (Refer to Figure 8.2.3.) b7 b6 b5 b4 b3 b2 b1 b0 A-D/UART2 trans./rece. interrupt control register (address 70 16) UART0 transmission interrupt control register (address 71 16) UART0 receive interrupt control register (address 72 16) UART1 transmission interrupt control register (address 73 16) UART1 receive interrupt control register (addresses 74 16) Bit Bit name 0 Interrupt priority level selection bits 1 2 3 7 to 4 Interrupt request bit Functions b2 b1 b0 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 Priority is low. 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Priority is high. 0: No interrupt has occurred. 1: Interrupt has occurred. Not implemented. At reset RW 0 RW 0 RW 0 RW 0 (Note) RW Undefined -- Note: When the UART2 function is selected, bit 3 of the A-D conversion/UART2 trans./rece. interrupt control register is set to "1." Accordingly, before enabling interrupts, write value "0" to this bit. Fig. 8.2.15 Structure of interrupt control registers related to UARTi 8-18 7733 Group User's Manual SERIAL I/O 8.2 Block description (1) Interrupt priority level selection bits (bits 2 to 0) These bits are used to select the priority level of the UARTi transmission interrupt or UARTi reception interrupt. When using the UARTi transmission/reception interrupt, select one of priority levels 1 to 7. When a UARTi transmission/reception interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL) and the requested interrupt is enabled only when its priority level is higher than the IPL. (Note that this is applied when the interrupt disable flag (I) = "0.") When these bits are set to "0002" (level 0), the UARTi transmission/reception interrupt is disabled. (2) Interrupt request bit (bit 3) The UARTi transmission interrupt request bit is set to "1" when data is transferred from the UARTi transmission buffer register to the UARTi transmission register. The UARTi reception interrupt request bit is set to "1" when data is transferred from the UARTi receive register to the UARTi receive buffer register. Note that these bits do not change when an overrun error occurs. When each interrupt request is accepted, the corresponding interrupt request bit is automatically cleared to "0." Note that each bit can be set to "1" or cleared to "0" by software. 7733 Group User's Manual 8-19 SERIAL I/O 8.2 Block description 8.2.9 Ports P7 and P8 direction registers I/O pins of UARTi are multiplexed with ports P7 and P8. When using the P7 4, P82 and P86 pins as serial data input pins (RxDi), set the corresponding bits of the ports P7_____ and P8 direction registers to "0" to set these ports for the input mode. When using the P7 2 pin as the CTS 2 input pin, set bit 2 of the port P7 direction register to "0" to set this port for the input mode. When using the P73, P75 , P80, P81, P83 -P85, _________ _________ and P87 pins as UARTi's I/O pins ( CTSi/RTSi, CLKi, TxDi), these pins are forcibly set as the UARTi's I/O pins, regardless of the ports P7 and P8 direction register's contents. Also, as for CLKS 0 and CLKS1, refer to section "8.3.1 (4) Number of transfer clock output pins (UART0)." Figure 8.2.16 shows the relationship between the ports P7, P8 direction registers and UARTi's I/O pins. Note that the functions of the UARTi's I/O pins can be switched by software. For details, refer to the description of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 Port P7 direction register (address 11 16) Bit b7 b6 b5 b4 b3 b2 b1 Corresponding pin name 0 Pin P70/AN0 1 Pin P71/AN1 Functions 0: Input mode 1: Output mode When using pin P72 as the CTS2 input pin and using pin P74 as serial data's input pin (RxD2), set the corresponding bit to "0." At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 2 Pin P72/AN2/CTS2 3 Pin P73/AN3/CLK2 4 Pin P74/AN4/RxD2 5 Pin P75/AN5/ADTRG/TxD2 6 Pin P76/AN6/XCOUT 0 RW 7 Pin P77/AN7/XCIN 0 RW At reset RW 0: Input mode 1: Output mode 0 RW 0 RW When using pins P82 and P86 as serial data's input pins (RxD0, RxD1), set the corresponding bits to "0." 0 RW 0 RW 0 RW b0 Port P8 direction register (address 1416) Bit Corresponding pin name 0 Pin P80/CTS0/RTS0/CLKS1 1 Pin P81/CLK0 Functions 2 Pin P82/RxD0/CLKS0 3 Pin P83/TxD0 4 Pin P84/CTS1/RTS1 5 Pin P85/CLK1 0 RW 6 Pin P86/RxD1 0 RW 7 Pin P87/TxD1 0 RW Note: For pins CLKS0 and CLKS1, refer to section "8.3.1 (4) Number of transfer clock output pins (UART0)." : Not used for serial I/O Fig. 8.2.16 Relationship between ports P7, P8 direction register and UARTi's I/O pins 8-20 7733 Group User's Manual SERIAL I/O 8.3 Clock synchronous serial I/O mode 8.3 Clock synchronous serial I/O mode Table 8.3.1 lists the performance overview in the clock synchronous serial I/O mode and Table 8.3.2 lists the functions of I/O pins in this mode. Table 8.3.1 Performance overview in clock synchronous serial I/O mode Item Functions Transfer data has a length of 8 bits. LSB first or MSB first is selected by software. Transfer rate When internal clock is selected BRGi's output divided by 2 When external clock is selected Maximum of 5 Mbps ____ ____ CTS function or RTS function is selected by software (Note). Transmit/Receive control Transfer data format ____ Note: The RTS function is not assigned for UART2. Table 8.3.2 Functions of I/O pins in clock synchronous serial I/O mode Pin name Functions Method of selection Serial data output TxDi (They output dummy data when only reception is performed.) Serial data input Ports P7 and P8 direction registers' corresponding bits ="0" RxDi (They can be used as input ports when only transmission is (P8 2, P86 , P74) performed.) Transfer clock output Internal/External clock selection bit = "0" CLKi Transfer clock input Internal/External clock selection bit = "1" (P8 1, P85 , P73) ____ ____ ____ _________ _________ CTS input CTS /RTS enable bit = "0" CTS 0/ RTS 0 (P80 ), ____ ____ _________ _________ CTS/ RTS function selection bit = "0" CTS 1/ RTS 1 (P8 4) ____ ____ ____ RTS output CTS /RTS enable bit = "0" (Note 1) ____ ____ CTS/ RTS function selection bit = "1" ____ ____ Programmable I/O port CTS /RTS enable bit = "1" ____ ____ _________ CTS input CTS enable bit = "0" CTS2 (P72) ____ Programmable I/O port CTS enable bit = "1" Port P7 direction register: Address 1116 Port P8 direction register: Address 1416 Internal/External clock selection bit: Bit 3 at addresses 3016 , 3816 , and 64 16 ____ ____ CTS / RTS enable bit: Bit 4 at addresses 3416 and 3C 16 ____ ____ CTS/ RTS function selection bit: Bit 2 at addresses 3416 and 3C 16 ____ CTS enable bit: Bit 2 at address 6816 The TxDi pin outputs "H" level from when a UARTi's operating mode is selected until transfer starts. (The TxDi pin is in a floating state when N-channel open-drain output is selected.) In UART0, multiple transfer clock output pins can be used. (Refer to Table 8.3.3.) (P8 3, P87 , P75) ____ Notes 1: The RTS function is not assigned for UART2. 2: As for CLKS 0 and CLKS 1 , refer to section "8.3.1 (4) Number of transfer clock output pins (UART0)." 7733 Group User's Manual 8-21 SERIAL I/O 8.3 Clock synchronous serial I/O mode 8.3.1 Transfer clock (sync clock) Data is transferred synchronously with the transfer clock. For the transfer clock, the following items can be specified: Whether to generate the transfer clock internally or to input it from the external. Polarity of a clock which is output from the CLKi pin (UART0, UART1) Number of transfer clock output pins (UART0). Note that the transfer clock is generated while the transmit control circuit is operating. Therefore, even when performing only reception, set the transmit enable bit to "1" and make the transmit control circuit operate by setting dummy data into the UARTi transmission buffer register. (1) How to generate transfer clock internally A count source is selected with the BRG count source selection bits. The count source is divided in the BRGi, and then the BRGi's output is further divided by 2. (In this way, the transfer clock is generated.) This transfer clock is output from the CLKi pin. [Setting for related registers] An internal clock is selected (bit 3 at addresses 30 16 , 38 16 , and 64 16 = "0"). The BRGi's count source is selected (bits 1 and 0 at addresses 34 16 , 3C16 , and 68 16 ). A value of "divide value - 1" (= n: 00 16 to FF 16) is set into the BRGi (addresses 31 16 , 39 16 , and 6516). Transfer clock's frequency = fi fi: BRGi's count source frequency (f 2 , f16 , f 64, and f 512) 2 (n+1) Transmission is enabled (bit 0 at addresses 3516 , 3D 16 , and 69 16 = "1"). Data is set into the UARTi transmission buffer register (addresses 3216 , 3A 16 , and 6616 ) [Pin status] Transfer clock is output from the CLKi pin. Serial data is output from the TxDi pin. (Dummy data is output when only reception is performed.) (2) How to input transfer clock from the external A clock which is input from the CLKi pin is the transfer clock. [Setting related registers] An external clock is selected (bit 3 at addresses 30 16 , 38 16 , and 64 16 = "1"). Transmission is enabled (bit 0 at addresses 3516 , 3D 16 , and 69 16 = "1"). Data is set into the UARTi transmission buffer register (addresses 32 16, 3A 16 , 66 16). [Pin status] Transfer clock is input from the CLKi pin. Serial data is output from the TxDi pin. (Dummy data is output when only reception is performed.) 8-22 7733 Group User's Manual SERIAL I/O 8.3 Clock synchronous serial I/O mode (3) How to select polarity of transfer clock The polarity of a clock which is output from the CLKi pin can be selected with the CLK polarity selection bit (UART0, UART1) as shown in Figure 8.3.1. The CLK polarity select bit is not implemented for UART2. The CLK 2 pin outputs the transmit data at the fall of the transfer clock; this pin inputs the receive data at the rise of the transfer clock. [Setting for related registers] The CLK polarity is selected (bit 6 at addresses 3416 , 3C 16). When CLK polarity selection bit = "0." CLKi T X Di D0 D1 D2 D3 D4 D5 D6 D7 RX Di D0 D1 D2 D3 D4 D5 D6 D7 The transmit data is output to the TxDi pin at the falling edge of the transfer clock; the receive data is input from the RxDi pin at the rising edge of the transfer clock. When not transferring, the CLKi pin's level is "H." When CLK polarity selection bit = "1." CLKi T X Di D0 D1 D2 D3 D4 D5 D6 D7 RX Di D0 D1 D2 D3 D4 D5 D6 D7 The transmit data is output to the TxDi pin at the rising edge of the transfer clock; the receive data is input from the RxDi pin at the falling edge of the transfer clock. When not transferring, the CLKi pin's level is "L." Fig. 8.3.1 Polarity of transfer clock 7733 Group User's Manual 8-23 SERIAL I/O 8.3 Clock synchronous serial I/O mode (4) Number of transfer clock output pins (UART0) Only in UART0, when an internal clock is selected, one pin can be selected as the transfer clock output pin from the following pins: CLK0, CLKS0 (in common with RxD0), and CLKS1 (in common with ____ ____ CTS 0/ RTS0). By this selection, data can be transmitted to the maximum of three external receiving devices. (Refer ____ ____ to in Table 8.3.4). In this case, since the RxD 0 and CTS 0/ RTS 0 pins function as the transfer clock ____ ____ output pins (CLK 0, CLKS 1), the CTS/ RTS function and reception are disabled. _____ ____ When only the CLK 0 and CLKS 0 pins are used as the transfer clock output pins, the P80 (CTS0/RTS0/ CLKS 1) pin can be used as a programmable I/O port. (Refer to in Table 8.3.4.) Also, when the CLK0 and CLKS 1 pins are used as the transfer clock output pins and bit 2 of the port P8 direction register is set to "0," data can be received from the RxD0 pin. (Refer to in Table 8.3.4.) [Setting for related registers] An internal clock is selected (bit 3 at address 3016 = "0"). ____ ____ The CTS / RTS function is disabled (bit 4 at address 34 16 = "1"). Reception is disabled (bit 2 at address 35 16 = "0"). (Refer to and in Table 8.3.4.) Number of transfer clock output pins is selected. (bits 5 and 4 at address 6E 16 ; Refer to Table 8.3.3.) Conditions for "output when not transferring" (described later) are set. (CLKS 0 : bit 2 at address 14 16 = "1": CLKS1: bit 0 at address 1416 = "1," bit 0 at address 1216 = level at "output when not transferring") [Pin status] Refer to Table 8.3.3. Table 8.3.3 Pin functions when one transfer clock output pin is selected Transfer clock Number of pins output pin from which one selection bits transfer clock ____ ____ CTS0/RTS0/CLKS1 output pin is (P80) b4 b5 selected Programmable I/O port 0 0 1 1 0 Selectable Programmable I/O port Programmable I/O port 0 1 Outputs transfer clock. 1 1 Functions CLK0 (P8 1) Outputs transfer clock. Outputs transfer clock. Output when not transferring* Output when not transferring* RxD 0/CLKS 0 TxD0 (P8 2) (P8 3) Programmable I/O port Outputs serial data. Outputs transfer clock. Output when not transferring*: When the CLK polarity selection bit (bit 6 at address 3416) = "0," the CLK0 pin outputs "H" level; when this bit = "1," the CLK 0 pin outputs "L" level. When bit 2 at address 14 16 (port P8 direction register) = "0," the RxD0/CLKS0 pin is in a floating state; when this bit = "1," the RxD0/CLKS 0 pin do the processing of "output when not transferring." M37733MHBXXXFP TXD0 CLKS 1 CLKS 0 CLK0 IN IN IN CLK CLK CLK Note: This is applied when the following conditions are satisfied: *Only transmission is performed. *Clock synchronous serial I/O mode is selected. *An internal clock is selected. Fig. 8.3.2 Connection example when one transfer clock output pin is selected from three pins 8-24 7733 Group User's Manual SERIAL I/O 8.3 Clock synchronous serial I/O mode [Switching of transfer clock output pin] When the transfer clock output pin is switched while transmission is enabled, follow the procedure described below. Transmission starts when step is executed: Check whether the previous transfer is completed or not. (Refer to Figure 8.3.6.) If the previous transfer has been completed, change the contents of the transmit clock output pin selection bit. Set the transmit data. For usage examples, refer to section "17.2.2 Examples of transmission for several peripheral ICs (Clock synchronous serial I/O mode)." Table 8.3.4 Number of channels for serial I/O transmission/reception for the case where multiple transfer clock output pins are used Setting example ____ ____ Outputs transfer clock. Programmable I/O port CTS 0/ RTS 0/CLKS1 (P8 0) Outputs transfer clock. Outputs transfer clock. CLK 0 (P8 1) Outputs transfer clock. Outputs transfer clock. RxD 0/CLKS0 (P8 2) Transmits data. Transmits data. TxD 0 (P8 3) *Number of channels for 3 channels for transmission 2 channels for transmission CLKS1 CLK0 serial I/O transmission/ (1, 1) (0, 1) TxD 0 TxD0 reception CLK0 CLKS0 *Status of transmit clock (0, 1) (1, 0) TxD0 output pin selection bits TxD0 CLKS0 (b5, b4) (1, 0) TxD0 Pin Outputs transfer clock. Outputs transfer clock. Receives data. Transmits data. 1 channel for transmission CLKS 1 (1, 1) TxD0 1 channel for transmission/reception CLK0 RxD 0 (0, 1) TxD0 Note: Set bit 2 at address 1416 (port P8 direction register) to "0." 7733 Group User's Manual 8-25 SERIAL I/O 8.3 Clock synchronous serial I/O mode 8.3.2 Transfer data format LSB-first or MSB-first can be selected (UART0, UART1). Table 8.3.5 lists the relationship between the transfer data format and the way to write/read to and from the UARTi transmission/receive buffer register. By setting the transfer format selection bit (bit 7 at addresses 3416, 3C 16), transfer data format can be selected. When this bit is cleared to "0," the set data is written to the UARTi transmission buffer register as the transmit data. Similarly, the data in the UARTi receive buffer register is read out as the receive data. (Refer to the upper row in Table 8.3.5.) When this bit is set to "1," each bit's position of the set data is reversed, and then this data is written to the UARTi transmission buffer register as the transmit data. Similarly, each bit's position of data in the UARTi receive buffer register is reversed, and then this data is read out as the receive data. (Refer to the lower row in Table 8.3.5.) Note that only the way to write/read to and from the UARTi transmission/receive buffer register is affected by the transfer data format. The transmit/receive operation is unaffected. The transfer data format for UART2 is fixed to "LSB-first." Table 8.3.5 Relationship between transfer data format and way to write/read to and from UARTi transmission/receive buffer register Transfer format selection bit Transfer data format When data is written to UARTi transmission buffer register Data bus LSB 0 (Least Significant Bit) first 1 (Most Significant Bit) first 8-26 Data bus UARTi receive buffer register DB7 D7 DB7 D7 DB6 D6 DB6 D6 DB5 D5 DB5 D5 DB4 D4 DB4 D4 DB3 D3 DB3 D3 DB2 D2 DB2 D2 DB1 D1 DB1 D1 DB0 D1 DB0 D0 Data bus MSB UARTi transmission buffer register When data is read from UARTi receive buffer register UARTi transmission buffer register Data bus UARTi receive buffer register DB7 D7 DB7 D7 DB6 D6 DB6 D6 DB5 D5 DB5 D5 DB4 D4 DB4 D4 DB3 D3 DB3 D3 DB2 D2 DB2 D2 DB1 D1 DB1 D1 DB0 D0 DB0 D0 7733 Group User's Manual SERIAL I/O 8.3 Clock synchronous serial I/O mode 8.3.3 Method of transmission Figures 8.3.3 and 8.3.4 show initial setting examples for related registers when transmitting. Transmission is started when all of the following conditions ( to ) are satisfied. When an external clock is selected, satisfy conditions to with the following preconditions satisfied. [Preconditions for UART0 and UART1] * The CLKi pin's input is at "H" level. (When an external clock is selected and the CLK polarity selection bit = "0.") * The CLKi pin's input is at "L" level. (When an external clock is selected and the CLK polarity selection bit = "1.") Note: When an internal clock is selected, the above preconditions are ignored. [Preconditions for UART2] * The CLKi pin's input is at "H" level. (When an external clock is selected) Note: When an internal clock is selected, the above precondition is ignored. Transmit enable state (transmit enable bit = "1") Transmit data is present in the UARTi transmission buffer register (transmission buffer empty flag = "0")._____ ____ The CTSi pin's____ input is at "L" level (when the CTS function is selected) Note: When the CTS function is not selected or in UART2, this condition is ignored. ____ ____ By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched (UART0, UART1). For details, refer to section "8.3.6 Receive operation." When using interrupts, settings for enabling interrupts are required. For details, refer to chapter "4. Interrupts." Figure 8.3.5 shows how to write data after transmission is started and Figure 8.3.6 shows how to detect the transmit completion. 7733 Group User's Manual 8-27 SERIAL I/O 8.3 Clock synchronous serial I/O mode UART0 transmit/receive mode register (address 30 16) UART1 transmit/receive mode register (address 38 16) UART2 transmit/receive mode register (address 64 16) b7 0 b0 0 0 1 Clock synchronous serial I/O mode Internal/External clock selection bit 0: Internal clock 1: External clock : It may be "0" or "1." Note 1: Nothing is implemented to bit 7 of UART2 transmit/receive mode register. UART0 transmit/receive control register 0 (address 34 16) UART1 transmit/receive control register 0 (address 3C 16) b7 UART2 transmit/receive control register 0 (address 68 16) b0 b7 b0 BRG count source selection bits BRG count source selection bits b1 b0 b1 b0 0 0: Clock f 2 0 1: Clock f 16 1 0: Clock f 64 1 1: Clock f 512 0 0: Clock f 2 0 1: Clock f 16 1 0: Clock f 64 1 1: Clock f 512 CTS / RTS function selection bit (Note 2) 0: The CTS function is selected. 1: The RTS function is selected. ( CTS function is disabled.) CTS enable bit 0: The CTS function is enabled. 1: The CTS function is disabled (I/O port). CTS / RTS enable bit 0: The CTS / RTS function is enabled. 1: The CTS / RTS function is disabled. Data output selection bit 0: T XDi pin is set for CMOS output. 1: T XDi pin is set for N-channel open-drain output. CLK polarity selection bit 0: At the falling edge of the transfer clock, transmit data is output. 1: At the rising edge of the transfer clock, transmit data is output. Transfer format selection bit 0: LSB first 1: MSB first Clocks f 2, f 16 , f 64, and f 512 : Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note 2: The CTS / RTS function selection bit is valid when the CTS / RTS enable bit = "0." Serial transmit control register (address 6E 16) b7 b0 Transmission clock output pin selection bits b5 b4 0 0: One transfer clock output pin 0 1: 1 0: Multiple transfer clock output pins 1 1: Multiple transfer clock output pins can be selected when performing only transmission with an internal clock selected in UART0. In this case, the CTS function cannot be used. Continued to "Initial setting example for related registers when transmitting (2)" on the next page Fig. 8.3.3 Initial setting example for related registers when transmitting (1) 8-28 7733 Group User's Manual SERIAL I/O 8.3 Clock synchronous serial I/O mode Continued from "Initial setting example for related registers when transmitting (1)" on the preceding page UART0 baud rate register (BRG0) (address 31 16) UART1 baud rate register (BRG1) (address 39 16) UART2 baud rate register (BRG2) (address 65 16) b7 b0 A value from 00 16 to FF16 is set. Necessary only when internal clock is selected. Port P8 register (address 12 16) b7 b0 Set the output level of CLKS1 pin when not transferring 0: "L" (when clock polarity selection bit = "1") 1: "H" (when clock polarity selection bit = "0") 1 Port P8 direction register (address 14 16) b7 b0 1 1 1 CLKS1 pin 2 CLKS0 pin : It may be "0" or "1." 1: Set this bit only when the number of the transfer clock output pins is 3. 2: Set this bit only when the number of the transfer clock output pins is 2 or 3. UART0 transmission interrupt control register (address 71 16) UART1 transmission interrupt control register (address 73 16) A-D/UART2 trans./rece. interrupt control register (address 70 16) b7 b0 0 Interrupt priority level selection bits When using interrupts, one of level 1 to 7 must be set. When disabling interrupts, level 0 must be set. UART0 transmission buffer register (address 32 16) UART1 transmission buffer register (address 3A 16) UART2 transmission buffer register (address 66 16) b7 b0 Transmit data is set here. UART0 transmit/receive control register 1 (address 35 16) UART1 transmit/receive control register 1 (address 3D 16) UART2 transmit/receive control register 1 (address 69 16) b7 b0 1 Transmit enable bit 1: Transmission is enabled. Transmission is started. (If the CTS function is selected, transmission is started when the CTSi pin's input level is "L.") Fig. 8.3.4 Initial setting example for related registers when transmitting (2) 7733 Group User's Manual 8-29 SERIAL I/O 8.3 Clock synchronous serial I/O mode [When using interrupts] [When not using interrupts] A UARTi transmission interrupt request occurs when the UARTi transmission buffer register becomes empty. Checking status of the UARTi transmission buffer register UART0 transmit/receive control register 1 (address 35 16) UART1 transmit/receive control register 1 (address 3D 16) UART2 transmit/receive control register 1 (address 69 16) b7 UARTi transmission interrupt b0 1 Transmission buffer empty flag 0: Data is present in the transmission buffer register. 1: No data is present in the transmission buffer register. (Next transmit data can be written.) Writing of next transmit data UART0 transmission buffer register (address 32 16) UART1 transmission buffer register (address 3A 16) UART2 transmission buffer register (address 66 16) b7 This diagram indicates bits and registers required for processing. Refer to Figure 8.3.8 for details about the change of flag status and the occurrence timing of an interrupt request. b0 Transmit data is set here. Fig. 8.3.5 How to write data after transmission is started 8-30 7733 Group User's Manual SERIAL I/O 8.3 Clock synchronous serial I/O mode [When not using interrupts] [When using interrupts] A UARTi transmission interrupt request occurs when the transmission is started. Checking the start of transmission UART0 transmission interrupt control register (address 71 16) UART1 transmission interrupt control register (address 73 16) A-D/UART2 trans./rece. interrupt control register (address 70 16) b7 UARTi transmission interrupt b0 Interrupt request bit 0: No interrupt request has occurred. 1: Interrupt request has occurred. (Transmission has been started.) Checking the completion of transmission UART0 transmit/receive control register 0 (address 34 16) UART1 transmit/receive control register 0 (address 3C 16) UART2 transmit/receive control register 0 (address 68 16) b7 This diagram indicates bits and registers required for processing. Refer to Figure 8.3.8 for details about the change of flag status and the occurrence timing of an interrupt request. b0 Transmission register empty flag 0: Transmission is in progress. 1: Transmission is completed. Note: Nothing is allocated to bits 7 to 4 of the UART2 transmit/receive control register 0. Processing at completion of transmission Fig. 8.3.6 How to detect of transmit completion 7733 Group User's Manual 8-31 SERIAL I/O 8.3 Clock synchronous serial I/O mode 8.3.4 Transmit operation When the transmit conditions described in section "8.3.3 Method of transmission" are satisfied while an internal clock is selected, the transfer clock is generated. And then, the following operations are automatically performed after one cycle of the transfer clock has passed. When the transmit conditions are satisfied and the external clock is input to the CLKi pin while the external clock is selected, the following operations are automatically performed. The UARTi transmission buffer register's contents is transferred to the UARTi transmission register. The transmission buffer empty flag is set to "1." The transmission register empty flag is cleared to "0." A UARTi transmission interrupt request occurs and the interrupt request bit is set to "1." Eight transfer clocks are generated (when an internal clock is selected). The transmit operation is described below. Data in the UARTi transmission register is transmitted from the TxDi pin synchronously with the valid edge of the CLKi pin's clock. This data is transmitted bit by bit sequentially beginning with the least significant bit (LSB). When one byte of data has been transmitted, the transmission register empty flag is set to "1." This indicates the completion of transmission. Valid edge : In UART0 and UART1, this means the falling edge when the CLK polarity selection bit = "0" and the rising edge when the CLK polarity selection bit = "1"; in UART2, this means the rising edge. Figure 8.3.7 shows the transmit operation. When an internal clock is selected, if the transmit conditions for the next data are satisfied at completion of transmission, the next transfer clock is generated immediately. Accordingly, when performing transmission in succession, set the next transmit data to the UARTi transmission buffer register during transmission (when the transmission register empty flag = "0"). When the transmit conditions for the next data are not satisfied, the transfer clock stops at "H" level when the CLK polarity selection bit = "0," and it stops at "L" level when the CLK polarity selection bit = "1." ____ Figure 8.3.8 shows an example of transmit timing (when an internal clock and the CTS function are selected). 4 8-32 7733 Group User's Manual SERIAL I/O 8.3 Clock synchronous serial I/O mode b7 b0 UARTi transmission buffer register Transmit data MSB UARTi transmission register CLKi pin's clock LSB D7 D6 D5 D4 D3 D2 D7 D6 D1 D0 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D2 D3 D7 This is applied when the CLK polarity selection bit = "0." When the CLK polarity selection bit = "1," data is shifted at the rising edge of the transfer clock of CLKi pin. Fig. 8.3.7 Transmit operation Tc Transfer clock "1" Transmit enable bit "0" Data is set in UARTi transmission buffer register. Transmission buffer "1" empty flag "0" UARTi transmission registerUARTi transmission buffer register "H" CTSi "L" TCLK Stopped because CTSi pin's level = "H" Stopped because transmit enable bit = "0" CLKi TENDi TxDi D0 D1 D 2 D 3 D4 D5 D6 D7 D0 D1 D 2 D 3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Transmission register "1" empty flag "0" UARTi transmit interrupt "1" request bit "0" The above timing diagram is applied when the following conditions are satisfied: Internal clock is selected. ** CTS function is selected. * CLK polarity selection bit = "0." Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. TENDi: Next transmit conditions are checked when this signal level becomes "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = TCLK = 2(n+1)/fi fi: BRGi's count source frequency (f 2, f16, f64, or f512) n: Value set to BRG i ____ Fig. 8.3.8 Example of transmit timing (when internal clock and CTS function are selected) 7733 Group User's Manual 8-33 SERIAL I/O 8.3 Clock synchronous serial I/O mode Tc Transfer clock Transmit enable bit "1" "0" Data is set in UARTi transmission buffer register. Transmission buffer "1" empty flag "0" TCLK UARTi transmission registerUARTi transmission buffer register Stopped because transmit enable bit = "0" CLKi TENDi TxDi D0 D 1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D 6 D 7 Transmission register "1" empty flag "0" UARTi transmit "1" interrupt request bit "0" The above timing diagram is applied when the following conditions are satisfied: Internal clock is selected. Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. TENDi: Next transmit conditions are checked when this signal level becomes "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) CTS function is not selected. CLK polarity selection bit = "0." Tc = TCLK = 2(n+1)/fi fi: BRGi's count source frequency (f 2, f16, f64, or f512) n: Value set to BRG i ____ Fig. 8.3.9 Example of transmit timing (when internal clock is selected and CTS function is not selected) 8-34 7733 Group User's Manual SERIAL I/O 8.3 Clock synchronous serial I/O mode 8.3.5 Method of reception Figures 8.3.10 and 8.3.11 show initial setting examples for related registers when receiving. Reception is started when all of the following conditions ( to ) are satisfied. When an external clock is selected, satisfy conditions to with the following preconditions satisfied. [Preconditions for UART0 and UART1] * The CLKi pin's input is at "H" level. (When an external clock is selected and the CLK polarity selection bit = "0.") * The CLKi pin's input is at "L" level. (When an external clock is selected and the CLK polarity selection bit = "1.") Note: When an internal clock is selected, the above preconditions are ignored. [Preconditions for UART2] * The CLKi pin's input is at "H" level. (When an external clock is selected) Note: When an internal clock is selected, the above precondition is ignored. Receive enable state (receive enable bit = "1") Transmit enable state (transmit enable bit = "1") Dummy data is present in the UARTi transmission buffer register (transmission buffer empty flag = "0"). ____ ____ By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched (UART0, UART1). For details, refer to section "8.3.6 Receive operation." When using interrupts, settings for enabling interrupts are required. For details, refer to chapter "4. Interrupts." Figure 8.3.12 shows the processing after reception is completed. 7733 Group User's Manual 8-35 SERIAL I/O 8.3 Clock synchronous serial I/O mode UART0 transmit/receive mode register (address 30 16) UART1 transmit/receive mode register (address 38 16) UART2 transmit/receive mode register (address 64 16) b7 0 b0 0 0 1 Clock synchronous serial I/O mode Internal/External clock selection bit 0: Internal clock 1: External clock : It may be "0" or "1." Notes 1: Nothing is implemented to bit 7 of the UART2 transmit/receive mode register. UART0 transmit/receive control register 0 (address 34 16) UART1 transmit/receive control register 0 (address 3C 16) b7 UART2 transmit/receive control register 0 (address 68 16) b0 b7 b0 BRG count source selection bits BRG count source selection bits b1b0 b1b0 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 0 0: Clock f 2 0 1: Clock f 16 1 0: Clock f 64 1 1: Clock f 512 CTS / RTS function selection bit (Note 2) 0: The CTS function is selected. (The RTS function is disabled.) 1: The RTS function is selected. CTS enable bit 0: The CTS function is enabled. 1: The CTS function is disabled (I/O port). CTS / RTS enable bit 0: The CTS / RTS function is enabled. 1: The CTS / RTS function is disabled. CLK polarity selection bit 0: The receive data is input at the rising edge of the transfer clock. 1: The receive data is input at the falling edge of the transfer clock. Transfer format selection bit 0: LSB first 1: MSB first Clocks f2 , f16, f 64, and f512 : Refer to chapter "14. CLOCK GENERATING CIRCUIT." Notes 2: The CTS / RTS function selection bit is valid when the CTS / RTS enable bit = "0." The RTS function is ignored when an internal clock is selected. 3: The RTS output function is not assigned for UART2. UART0 baud rate register (BRG0) (address 31 16) UART1 baud rate register (BRG1) (address 39 16) UART2 baud rate register (BRG2) (address 65 16) b7 b0 A value from 00 16 to FF16 is set. Necessary only when an internal clock is selected. Continued to "Initial setting example for related registers when receiving (2)" on the next page Fig. 8.3.10 Initial setting example for related registers when receiving (1) 8-36 7733 Group User's Manual SERIAL I/O 8.3 Clock synchronous serial I/O mode Continued from "Initial setting example for related registers when receiving (1)" on the proceeding page Port P8 direction register (address 14 16) b7 b0 0 0 RXD0 pin RXD1 pin Port P7 direction register (address 11 16) b7 b0 0 RXD2 pin (Note 1) Notes 1: In the 7733 Group or the 7735 Group, set this bit. In the 7736 Group, it is not necessary to set this bit. UART0 receive interrupt control register (address 72 16) UART1 receive interrupt control register (address 74 16) A-D/UART2 trans./rece. interrupt control register (address 70 b7 16) b0 0 Interrupt priority level selection bits When using interrupts, one of level 1 to 7 must be set. When disabling interrupts, level 0 must be set. UART0 transmission buffer register (address 32 16) UART1 transmission buffer register (address 3A 16) UART2 transmission buffer register (address 66 16) b7 b0 Dummy data is set. UART0 transmit/receive control register 1(address 35 16) UART1 transmit/receive control register 1(address 3D 16) UART2 transmit/receive control register 1(address 69 16) b7 b0 1 1 Transmit enable bit ( Note 2) 1: Transmission is enabled. Receive enable bit ( Note 2) 1: Receptipn is enabled. Notes 2: Set the receive enable bit and the transmit enable bit to "1" simultaneously. Reception is started. Fig. 8.3.11 Initial setting example for related registers when receiving (2) 7733 Group User's Manual 8-37 SERIAL I/O 8.3 Clock synchronous serial I/O mode [When using interrupts] [When not using interrupts] A UARTi receive interrupt request occurs when reception is completed. Checking the completion of reception UART0 transmit/receive control register 1 (address 35 16) UART1 transmit/receive control register 1 (address 3D 16) UART2 transmit/receive control register 1 (address 69 16) b7 UARTi receive interrupt b0 1 1 Receive completion flag 0: Reception is not completed. 1: Reception is completed. Reading of the receive data UART0 receive buffer register (address 36 16) UART1 receive buffer register (address 3E 16) UART2 receive buffer register (address 6A 16) b0 b7 Receive data is read out. Checking the error UART0 transmit/receive control register 1 (address 35 16) UART1 transmit/receive control register 1 (address 3D 16) UART2 transmit/receive control register 1 (address 69 16) This diagram indicates bits and registers required for processing. Refer to Figure 8.3.15 for details about the change of flag status and the occurrence timing of an interrupt request. b0 b7 1 1 Overrun error flag 0: No overrun error is detected. 1: Error is detected. Processing after reading out receive data Fig. 8.3.12 Processing after reception is completed 8-38 7733 Group User's Manual SERIAL I/O 8.3 Clock synchronous serial I/O mode 8.3.6 Receive operation When the receive conditions described in section "8.3.5 Method of reception" are satisfied while an internal clock is selected, the transfer clock is generated. And then, the receive is started after one cycle of the transfer clock has passed. When the receive conditions are satisfied while the external clock is selected, UARTi is in the reception enabled state. Then, the external ____ clock is input to the CLKi pin and reception is started. _____ In UART0 and UART1, when the RTS function is selected with an external clock selected, the RTSi pin's output level is "L," and the microcomputer informs the transmitter side that reception____ is enabled. When ____ ____ reception is started, the RTSi pin's output level is "H." Accordingly, by connecting the RTSi pin to the CTSi pin of the transmitter side, the timing of transmission and that of reception can be matched. ____ _____ When an internal clock is selected, do not use the RTS function because the RTSi output is undefined. Figure 8.3.13 shows a connection example. ____ The RTS output function is not assigned for UART2. The receive operation is described below. The signal which is input from the RxDi pin is taken in the most significant bit of the UARTi receive register synchronously with the valid edge of the clock which is output from the CLKi pin or input to the CLKi pin. The contents of the UARTi receive register is shifted by 1 bit to the right. Operations and are repeated at each valid edge of the clock which is output from the CLKi pin or input to the CLKi pin. When one byte of data is prepared in the UARTi receive register, the contents of this register is transferred to the UARTi receive buffer register. Simultaneously with , the receive completion flag is set to "1." At this time, a receive interrupt request occurs, and then an interrupt request bit is set to "1." Valid edge : In UART0 and UART1, this means the rising edge when the CLK polarity selection bit = "0" and the falling edge when the CLK polarity selection bit = "1"; in UART2, this means the rising edge. The receive completion flag is cleared to "0" when the low-order byte of the UARTi receive buffer register ____ is read out. The RTSi pin continues to output "H" level until the receive conditions are next satisfied (when ____ the RTS function is selected). Figure 8.3.14 shows the receive operation and Figure 8.3.15 shows an example of receive timing (when an external clock is selected). When the contents of the UARTi receive buffer register is read out with the transfer format selection bit = "1" (MSB first), each bit's position of this register's contents is reversed and the resultant data is read out (UART0, UART1). 7733 Group User's Manual 8-39 SERIAL I/O 8.3 Clock synchronous serial I/O mode Receiver side Transmitter side TxDi TxDi RxDi RxDi CLKi CLKi CTSi RTSi (Note) Note: The RTSi output function is not assigned for Fig. 8.3.13 Connection example MSB Clock which is output from or input to CLKi pin LSB UARTi receive register D0 D0 D2 D1 D0 D7 D6 D 5 D4 c c D1 D3 D2 b7 UARTi receive buffer register b0 Receive data This is applied when the CLK polarity selection bit = "0." When the CLK polarity selection bit = "1," data is shifted at the falling edge of the clock which is output from or input to the CLKi pin. Fig. 8.3.14 Receive operation 8-40 7733 Group User's Manual D1 D0 SERIAL I/O 8.3 Clock synchronous serial I/O mode "1" Receive enable bit "0" "1" Transmit enable bit "0" Dummy data is set in UARTi transmission buffer register. "1" Transmission buffer empty flag "0" UARTi transmission register UARTi transmission buffer register "H" (Note) RTSi "L" 1 / fEXT CLKi Received data is taken in. D0 D1 D 2 D 3 D4 D5 D6 D7 RxDi Receive completion flag "1" D0 D1 D 2 D3 D4 D5 UARTi receive register UARTi receive buffer register UARTi receive buffer register is read out. "0" UARTi receive "1" interrupt request bit "0" The above timing diagram is applied when the following conditions are satisfied: External clock is selected. RTS function is selected. CLK polarity selection bit = "0." fEXT: Frequency of external clock Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. When the CLKi pin's input level is "H," satisfy the following conditions: Transmit enable bit "1" Receive enable bit "1" Writing of dummy data to UARTi transmission buffer register Note: The RTSi output function is not assigned for UART2. Fig. 8.3.15 Example of receive timing (when external clock is selected) 7733 Group User's Manual 8-41 SERIAL I/O 8.3 Clock synchronous serial I/O mode 8.3.7 Processing when an overrun error is detected In the clock synchronous serial I/O mode, an overrun error can be detected. An overrun error occurs when the next data is prepared in the UARTi receive register with the receive completion flag = "1" (in other words, data is present in the UARTi receive buffer register), and then the next data is transferred to the receive buffer register. In other words, when the next data is prepared before the contents of the UARTi receive buffer register is read out, an overrun error occurs. When an overrun error occurs, the next data is written into the UARTi receive buffer register. At this time, the UARTi receive interrupt request bit does not change. An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register. At this time, the overrun error flag is set to "1." The overrun error flag is cleared to "0" when the serial I/O mode selection bits are cleared to "0002" or when the receive enable bit is cleared to "0." When an overrun error occurs during reception, initialize the overrun error flag and the UARTi receive buffer register, and then perform reception again. When it is necessary to perform transmission owing to an overrun error which occurs in the receiver side, set the UARTi transmission buffer register again, and then starts transmission again. The method of initializing the UARTi receive buffer register and that of setting the UARTi transmission buffer register again are described below. (1) Method of Initializing UARTi receive buffer register Clear the receive enable bit to "0." (Reception is disabled.) Set the receive enable bit to "1" again. (Reception is enabled.) (2) Method of setting UARTi transmission buffer register again Clear the serial I/O mode selection bits to "000 2 ." (Serial I/O is ignored.) Set the serial I/O mode selection bits to "0012" again. Set the transmit enable bit to "1." (Transmission is enabled.) And set the transmit data to the UARTi transmission buffer register. 8-42 7733 Group User's Manual SERIAL I/O 8.3 Clock synchronous serial I/O mode 8.3.8 Precautions for clock synchronous serial I/O 1. The transfer clock is generated by the operation of the transmit control circuit. Accordingly, even when performing only reception, the transmit operation (setting for transmission) must be performed. In this case, dummy data is output from the TxDi pin to the external. 2. When an internal clock is selected during reception, the transfer clock is generated if the following conditions are satisfied: *The transmit enable bit is set to "1." (Transmission is enabled.) *Dummy data is set to the UARTi transmission buffer register. When an external clock is selected during reception, the transfer clock is generated if the following conditions are satisfied: *The transmit enable bit is set to "1." *A clock is input to the CLKi pin after dummy data is set to the UARTi transmission buffer register. 3. When an external clock is selected, make sure that the following conditions are satisfied with the CLKi pin's input level = "H" if the CLK polarity selection bit = "0" or with the CLKi pin's input level = "L" if the CLK polarity selection bit = "1": [At transmitting] Set the transmit enable bit to "1." Write the transmit data to the UARTi transmission buffer register. _____ ____ Input "L" level to the CTSi pin (when CTS function is selected). [At receiving] Set the receive enable bit to "1." Set the transmit enable bit to "1." Write dummy data to the UARTi transmission buffer register. 4. When receiving data in succession, set dummy data to the low-order byte of the UARTi transmission buffer register each time when 1-byte data is received. 5. For performing the transmission and the reception simultaneously, UART2 does not distinguish the transmission interrupt from the reception interrupt. The UART2 transmission/reception interrupt request occurs when either interrupt request occurs. Accordingly, in the system which performs the transmission and reception simultaneously for UART2, not use the UART2 transmission/reception interrupt but use the method of poling the transmission buffer empty flag and the receive completion flag by software. 7733 Group User's Manual 8-43 SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode 8.4 Clock asynchronous serial I/O (UART) mode Table 8.4.1 lists the performance overview in the UART mode and Table 8.4.2 lists the functions of I/O pins in this mode. Table 8.4.1 Performance overview in UART mode Item Functions Transfer Start bit 1 bit data format Character bit (Transfer data) 7 bits, 8 bits, or 9 bits Parity bit 0 bit or 1 bit (Odd or Even can be selected.) Stop bit 1 bit or 2 bits Transfer rate When internal clock is selected BRGi's output divided by 16 (Maximum of 781.25 kbps (Note)) When external clock is selected Maximum of 312.5 kbps Error detection 4 types (Overrun, Framing, Parity, and Summing) Presence of error can be detected only by checking error sum flag. Note: This is applied when the system clock selection bit (bit 3 at address 6C16) = "0" and the system clock frequency = 25 MHz (f(f2 ) = 12.5 MHz). (For details, refer to chapter "14. CLOCK GENERATING CIRCUIT." Table 8.4.2 Functions of I/O pins in UART mode Method of selection Functions Pin name Serial data output TxDi (They cannot be used as programmable I/O ports.) (P8 3 , P87, P75) Ports P7 and P8 direction register's corresponding bit = "0" Serial data input RxDi (They can be used as input ports when only transmission is performed.) (P8 2 , P86, P74) Programmable I/O port Internal/External clock selection bit = "0" CLKi (P8 1 , P85, P73) BRGi count source input Internal/External clock selection bit = "1" ____ ____ ____ ____ ____ CTS /RTS enable bit = "0" CTSi /RTSi (Note) CTS input ____ ____ CTS/ RTS function selection bit = "0" (P8 0, P8 4) ____ ____ ____ CTS /RTS enable bit = "0" RTS output ____ ____ CTS/ RTS function selection bit = "1" ____ ____ Programmable I/O port CTS /RTS enable bit = "1" ____ ____ CTS enable bit = "0" CTS input CTS2 (P72 ) ____ Programmable I/O port CTS enable bit = "1" Port P7 direction register: Address 11 16 Port P8 direction register: Address 14 16 Internal/External clock selection bit: Bit 3 at addresses 3016, 38 16, and 64 16 ____ ____ CTS / RTS enable bit: Bit 4 at addresses 3416 and 3C 16 ____ ____ CTS / RTS function selection bit: Bit 2 at addresses 3416 and 3C 16 ____ CTS enable bit: Bit 2 at addresses 6816 The TxDi pin outputs "H" level while not transmitting after a UARTi's operating mode is selected. (The TxDi pin is in a floating state when N-channel open-drain output is selected.) ____ Note: The RTSi output function is not assigned for UART2. 8-44 7733 Group User's Manual SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode 8.4.1 Transfer rate (Baud rate: transfer clock frequency) The transfer rate is determined by BRGi (addresses 31 16, 39 16, and 65 16 ). When a value of "n" is set in BRGi (n = 0016 to FF 16), the count source is divided by (n + 1) in the BRGi, and then the BRGi's output is further divided by 16. (In this way, the transfer clock is generated.) Accordingly, assuming that the baud rate is B (bps), "n" is expressed by the following formula. n = F 16 B -1 F : BRGi's count source frequency An internal clock or an external clock can be selected as the BRGi's count source by specifying the internal/external clock selection bit (bit 3 at addresses 30 16 , 3816 , and 64 16 ). When an internal clock is selected, the clock selected by the BRG count source selection bits (bits 1 and 0 at addresses 34 16, 3C 16, and 6816) is the BRGi's count source. When an external clock is selected, the clock which is input to the CLKi pin is the BRGi's count source. Tables 8.4.3 to 8.4.5 list examples of baud rate setting. Be sure to set the same baud rate for both transmitter and receiver sides. 7733 Group User's Manual 8-45 SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode Table 8.4.3 Example of baud rate setting (1) Baud rate BRGi's System clock: 14.7456 MHz System clock: 19.6608 MHz (bps) countsource BRGi's set value: n Actual time (bps) BRGi's set value: n Actual time (bps) 300 f16 191 (BF 16 ) 300.00 255 (FF 16 ) 300.00 600 f16 95 (5F 16 ) 600.00 127 (7F16 ) 600.00 1200 f16 47 (2F 16 ) 1200.00 63 (3F 16 ) 1200.00 2400 f2 191 (BF 16 ) 2400.00 255 (FF 16 ) 2400.00 4800 f2 95 (5F 16 ) 4800.00 127 (7F16 ) 4800.00 9600 f2 47 (2F 16 ) 9600.00 63 (3F 16 ) 9600.00 19200 f2 23 (17 16 ) 19200.00 31 (1F 16 ) 19200.00 38400 f2 11 (0B 16 ) 38400.00 15 (F 16 ) 38400.00 57600 f2 7 (07 16 ) 57600.00 115200 f2 3 (03 16 ) 115200.00 System clock, and clocks f 2, f 16 : Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: This is applied when the system clock selection bit (bit 3 at address 6C 16 ) = "0." For details, refer to chapter "14. CLOCK GENERATING CIRCUIT." Table 8.4.4 Example of baud rate setting (2) Baud rate BRGi's System clock: 24.576 MHz System clock: 25 MHz (bps) countsource BRGi's set value: n Actual time (bps) BRGi's set value: n Actual time (bps) 300 f64 79 (4F 16 ) 300.00 80 (50 16 ) 301.41 600 f16 159 (9F16 ) 600.00 162 (A2 16 ) 599.12 1200 f16 79 (4F 16 ) 1200.00 80 (50 16 ) 1205.63 2400 f16 39 (27 16 ) 2400.00 40 (28 16 ) 2381.86 4800 f2 159 (9F16 ) 4800.00 162 (A2 16 ) 4792.94 9600 f2 79 (4F 16 ) 9600.00 80 (50 16 ) 9645.06 14400 f2 52 (34 16 ) 14490.57 53 (35 16 ) 14467.59 19200 f2 39 (27 16 ) 19200.00 40 (28 16 ) 19054.88 31250 f2 24 (18 16 ) 31250.00 System clock, and clocks f 2, f 16 , f64 : Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: This is applied when the system clock selection bit (bit 3 at address 6C 16 ) = "0." For details, refer to chapter "14. CLOCK GENERATING CIRCUIT." Table 8.4.5 Example of baud rate setting (3) Baud rate BRGi's System clock: 11.0592 MHz (bps) countsource BRGi's set value: n Actual time (bps) 300 f16 143 (8F16 ) 300.00 600 f16 71 (47 16 ) 600.00 1200 f16 35 (23 16 ) 1200.00 2400 f2 143 (8F16 ) 2400.00 4800 f2 71 (47 16 ) 4800.00 9600 f2 35 (23 16 ) 9600.00 14400 f2 24 (18 16 ) 14400.00 19200 f2 17 (11 16 ) 19200.00 28800 f2 12 (0C 16 ) 28800.00 31250 f2 System clock: 12 MHz BRGi's set value: n Actual time (bps) 155 (9B 16 ) 300.48 77 (4D 16 ) 600.96 38 (26 16 ) 1201.92 155 (9B 16 ) 2403.85 77 (4D 16 ) 4807.69 38 (26 16 ) 9615.38 26 (1A 16 ) 14423.08 13 (0D 16 ) 11 (0B 16 ) System clock, and clocks f 2, f 16 : Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: This is applied when the system clock selection bit (bit 3 at address 6C 16 ) = "0." For details, refer to chapter "14. CLOCK GENERATING CIRCUIT." 8-46 7733 Group User's Manual 28846.15 31250.00 SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode 8.4.2 Transfer data format The transfer data format can be selected from three formats shown in Figure 8.4.1. By setting bits 6 to 4 at addresses 30 16, 3816 and 64 16, the transfer data format can be selected. (Refer to Figures 8.2.2 and 8.2.3.) Be sure to set the same transfer data format for both transmitter and receiver sides. Figure 8.4.2 shows an example of transfer data format. Table 8.4.6 lists each bit in transmit data. When transfer data has a length of 7 bits 1ST-7DATA 1SP 1ST-7DATA 2SP 1ST-7DATA-1PAR- 1SP 1ST-7DATA-1PAR- 2SP When transfer data has a length of 8 bits 1ST-8DATA 1SP 1ST-8DATA 2SP 1ST-8DATA-1PAR- 1SP 1ST-8DATA-1PAR- 2SP When transfer data has a length of 9 bits 1ST-9DATA 1SP 1ST-9DATA 2SP 1ST-9DATA-1PAR- 1SP 1ST-9DATA-1PAR- 2SP ST DATA PAR SP : : : : Start bit Character bit (transfer data) Parity bit Stop bit Fig. 8.4.1 Transfer data format 7733 Group User's Manual 8-47 SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode For the case where 1ST-8DATA-1PAR-1SP Time Next transmit/receive data (When transferring in succession) Transmit/Receive data DATA (8 bits) "H" ST LSB MSB PAR SP ST Fig. 8.4.2 Example of transfer data format Table 8.4.6 Each bit in transmit data Name ST Start bit DATA Functions "L" signal equivalent to 1 character bit which is added immediately before the character bits. It indicates start of data transmission. Transmit data which is set in the UARTi transmission buffer register. Character bit PAR Parity bit SP Stop bit 8-48 A signal which is added immediately after the character bits in order to improve data reliability. The level of this signal changes depending on odd/even parity selection in such a way that the sum of "1"s in bits (this bit and character bits) is always an odd or even number. "H" level signal equivalent to 1 or 2 character bits which is added immediately after the character bits (or parity bit when parity is enabled). It indicates end of data transmission. 7733 Group User's Manual SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode 8.4.3 Method of transmission Figure 8.4.3 shows an initial setting example for related registers when transmitting. The difference derived by selection of transfer data length (7 bits, 8 bits, or 9 bits) is only that data is transmitted in different lengths. When a 7/8-bit data length is selected, set the transmit data in the loworder byte of the UARTi transmission buffer register; when a 9-bit data length is selected, set the transmit data in the low-order byte and bit 0 of the high-order byte. Transmission is started when the following conditions ( to ) are satisfied: Transmit enable state (transmit enable bit = "1") Transmit data is present in the UARTi transmission buffer register (transmission buffer empty flag = "0") ____ ____ The CTSi pin's input is at "L" level (when the CTS function is selected) ____ Note: When the CTS function is not selected or in UART2, this condition is ignored. ____ ____ By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched (UART0, UART1). For details, refer to section "8.4.6 Receive operation." When using interrupts, settings for enabling interrupts are required. For details, refer to chapter "4. Interrupts." Figure 8.4.4 shows how to write data after transmission is started and Figure 8.4.5 shows how to detect the transmit completion. 7733 Group User's Manual 8-49 SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode UART0 transmit/receive mode register (address 3016) UART1 transmit/receive mode register (address 3816) UART2 transmit/receive mode register (address 6416) b7 UART0 baud rate register (BRG0) (address 3116) UART1 baud rate register (BRG1) (address 3916) UART2 baud rate register (BRG2) (address 6516) b7 b0 b0 1 b2b1b0 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Internal/External clock selection bit 0: Internal clock 1: External clock Stop bit length selection bit 0: 1 stop bit 1: 2 stop bits A value from 0016 to FF16 is set. UART0 transmission interrupt control register (address 7116) UART1 transmission interrupt control register (address 7316) A-D/UART2 transm./rece. interrupt control register (address 7016) b7 b0 0 Interrupt priority level selection bits When using interrupts, one of level 1 to 7 must be set. When disabling interrupts, level 0 must be set. Odd/Even parity selection bit 0: Odd parity 1: Even parity Parity enable bit 0: Parity is disabled. 1: Parity is enabled. Sleep selection bit (Note 1) 0: The sleep mode is terminated (ignored). 1: The sleep mode is selected. UART0 transmission buffer register (addresses 3316, 3216) UART1 transmission buffer register (addresses 3B16, 3A16) UART2 transmission buffer register (addresses 6716, 6616) b8 b7 b0 Note 1: Nothing is allocated to bit 7 of the UART2 transmit/ receive mode register. UART0 transmit/receive control register 0 (address 3416) UART1 transmit/receive control register 0 (address 3C16) b7 b0 0 0 Transmit data is set here. UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) b7 b0 1 BRG count source selection bits b1b0 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 AAA AAA AAA Transmit enable bit 1: Transmission is enabled. CTS / RTS function selection bit (Note 2) 0: The CTS function is selected. 1: The RTS function is selected. (The CTS function is disabled.) CTS / RTS enable bit 0: The CTS / RTS function is enabled. 1: The CTS / RTS function is disabled. Data output selection bit 0: TxDi pin is set for CMOS output. 1: TxDi pin is set for N-channel open-drain output. Transmission is started. (If the CTS function is selected, transmission is started when the CTSi pin's input level is "L.") Clocks f2, f16, f64, and f512 : Refer to chapter "14. CLOCK GENERATING CIRCUIT." UART2 transmit/receive control register 0 (address 6816) b7 b0 BRG count source selection bits b1b0 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 CTS enable bit 0: The CTS function is enabled. 1: The CTS function is disabled (I/O port). Note 2: The CTS/RTS function selection bit is valid when the CTS/RTS enable bit = "0." Fig. 8.4.3 Initial setting example for related registers when transmitting 8-50 7733 Group User's Manual SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode [When not using interrupts] [When using interrupts] A UARTi transmission interrupt request occurs when the UARTi transmission buffer register becomes empty. Checking the status of the UARTi transmission buffer register UART0 transmit/receive control register 1 (address 35 16) UART1 transmit/receive control register 1 (address 3D 16) UART2 transmit/receive control register 1 (address 69 16) b7 UARTi transmission interrupt b0 1 Transmission buffer empty flag 0: Data is present in the transmission buffer register. 1: No data is present in the transmission buffer register. (Next transmit data can be written.) Writing of the next transmit data UART0 transmission buffer register (addresses 33 16 , 3216) UART1 transmission buffer register (addresses 3B 16, 3A16) UART2 transmission buffer register (addresses 67 16 , 6616) b15 b8 b7 This diagram indicates bits and registers required for processing. Refer to Figures 8.4.6, 8.4.7 and 8.4.8 for details about the change of flag status and the occurrence timing of an interrupt request. b0 Transmit data is set here. Fig. 8.4.4 How to write data after transmission is started 7733 Group User's Manual 8-51 SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode [When using interrupts] [When not using interrupts] UARTi transmission interrupt request occurs when transmission is started. Checking the start of transmission UART0 transmission interrupt control register (address 71 16) UART1 transmission interrupt control register (address 73 16) A-D/UART2 trans./rece. interrupt control register (address 70 16) b7 b0 UARTi transmission interrupt Interrupt request bit 0: No interrupt has occurred. 1: Interrupt has occurred. (Transmission has been started.) This diagram indicates bits and registers required for processing. Refer to Figures 8.4.6, 8.4.7 and 8.4.8 for details about the change of flag status and the occurrence timing of an interrupt request. Checking the completion of transmission UART0 transmit/receive control register 0 (address 34 16) UART1 transmit/receive control register 0 (address 3C 16) UART2 transmit/receive control register 0 (address 68 16) b7 b0 0 0 Transmisson register empty flag 0: Transmission is in progress. 1: Transmission is completed. Note: Nothing is implemented to bits 7 to 4 of UART2. Processing at transmit completion Fig. 8.4.5 How to detect transmit completion 8-52 7733 Group User's Manual SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode 8.4.4 Transmit operation When the transmit conditions described in section "8.4.3 Method of transmission" are satisfied, the transfer clock is generated and the following operations are automatically performed after one cycle of the transfer clock has passed. The UARTi transmission buffer register's contents is transferred to the UARTi transmission register. The transmission buffer empty flag is set to "1." The transmission register empty flag is cleared to "0." A UARTi transmission interrupt request occurs and the interrupt request bit is set to "1." The transmit operation is described below. Data in the UARTi transmission register is transmitted from the TX Di pin. This data is transmitted bit by bit sequentially in order of STDATA (LSB) *** DATA (MSB)PAR SP according to the transfer data format. In the middle of the stop bit (the second stop bit when two stop bits are selected), the transmission register empty flag is set to "1." This indicates completion of transmission. Also, whether the transmit conditions for the next data are satisfied or not is checked. When the transmit conditions for the next data are satisfied at completion of transmission in operation , a start bit is generated following the stop bit and the next data is transmitted. When performing transmission in succession, set the next transmit data in the UARTi transmission buffer register during transmission (when transmission register empty flag = "0"). When the transmit conditions for the next data are not satisfied, the TXDi pin outputs "H" level and the transfer clock is stopped. Figure 8.4.6 shows an example of transmit timing when the transfer data length has a 8 bits. Figure 8.4.7 shows an example of transmit timing when the transfer data length has a 9 bits. 7733 Group User's Manual 8-53 SEIRAL I/O 8.4 Clock asynchronous serial I/O (UART) mode Tc Transfer clock "1" Transmit enable bit "0" Data is set in UARTi transmission buffer register. Transmission buffer "1" empty flag "0" UARTi transmission register UARTi transmission buffer register TENDi Parity bit Start bit TxDi ST D0 D1 D2 D3 D4 D5 D6 D7 P Stopped because transmit enable bit = "0" Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 Transmission register "1" empty flag "0" UARTi transmission "1" interrupt request bit "0" Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. The above timing diagram is applied when the following conditions are satisfied: Parity is enabled. 1 stop bit CTS function is not selected. TENDi : Next transmit conditions are checked when this signal level becomes "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) TC = 16(n + 1)/f i or 16(n + 1)/f EXT fi : BRGi's count source frequency (f 2, f16, f64, or f512) fEXT : BRGi's count source frequency (external clock) n : Value set to BRG i Fig. 8.4.6 Example of transmit timing when data is transferred in 8 bits (When parity is enabled, one ____ stop bit, and CTS function is not selected) Tc Transfer clock "1" Transmit enable bit "0" Data is set in UARTi transmission buffer register. "1" Transmission buffer empty flag "0" UARTi transmission register TENDi Stop bit Stop bit Start bit TxDi UARTi transmission buffer register Stopped because transmit enable bit = "0" ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 Transmission register "1" empty flag "0" UARTi transmission interrupt request bit "1" "0" Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. The above timing diagram is applied when the following conditions are satisfied: Parity is disabled. 2 stop bits CTS function is not selected. TENDi : Next transmit conditions are checked when this signal level becomes "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) TC = 16(n + 1)/f i or 16(n + 1)/fEXT fi : BRGi's count source frequency (f 2, f16, f64, or f512) fEXT : BRGi's count source frequency (external clock) n : Value set to BRG i Fig. 8.4.7 Example of transmit timing when data is transferred in 9 bits (When parity is disabled and two stop bits) 8-54 7733 Group User's Manual SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode Tc Transfer clock Transmit enable bit "1" "0" Data is set in UARTi transmission buffer register. Transmission buffer "1" empty flag "0" UARTi transmission register UARTi transmission buffer register CTSi "H" "L" TENDi Parity bit Start bit TxDi ST D0 D1 D2 D3 D4 D5 D6 D7 P Stopped because CTS pin's level is "H." Stopped because transmit enable bit = "0" SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 Stop bit Transmission register "1" empty flag "0" UARTi transmission "1" interrupt request bit "0" Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. The above timing diagram is applied when the following conditions are satisfied: Parity is enabled. 1 stop bit CTS function is selected. TENDi : Next transmit conditions are checked when this signal level becomes "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) TC = 16(n + 1)/f i or 16(n + 1)/fEXT fi : BRGi's count source frequency (f 2, f16, f64, or f512) fEXT : BRGi's count source frequency (external clock) n : Value set to BRG i Fig. 8.4.8 Example of transmit timing when data is transferred in 8 bits (When parity is enabled, one ____ stop bit, and CTS function is selected) 7733 Group User's Manual 8-55 SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode 8.4.5 Method of reception Figure 8.4.9 shows an initial setting example for related registers when receiving. Reception is started when the following conditions ( and ) are satisfied. Receive enable state (receive enable bit = "1"). The start bit is detected. ____ ____ By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched (UART0, UART1). For details, refer to section "8.4.6 Receive operation." When using interrupts, settings for enabling interrupts are required. For details, refer to chapter "4. Interrupts." Figure 8.4.10 shows the processing after reception is completed. 8-56 7733 Group User's Manual SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode UART0 transmit/receive mode register (address 30 16) UART1 transmit/receive mode register (address 38 16) UART2 transmit/receive mode register (address 64 16) b7 UART0 baud rate register (BRG0) (address 31 16) UART1 baud rate register (BRG1) (address 39 16) UART2 baud rate register (BRG2) (address 65 16) b7 b0 b0 1 b2b1b0 A value from 00 16 to FF16 is set. 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Internal/External clock selection bit 0: Internal clock 1: External clock Port P8 direction register (address 14 16) b7 b0 0 0 Stop bit length selection bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity selection bit 0: Odd parity 1: Even parity RxD0 pin RxD1 pin Port P7 direction register (address 11 16) b7 b0 0 Parity enable bit 0: Parity is disabled. 1: Parity is enabled. RxD2 pin (Note 3) Note 3: In the 7733 Group or the 7735 Group, set this bit. In the 7736 Group, it is not neccessary to set this bit. Sleep selection bit (Note 1) 0: The sleep mode is terminated (ignored). 1: The sleep mode is selected. Set the transfer data format in the same way as set on the transmitter side. Note 1: Nothing is allocated to bit 7 of UART2 transmit/receive mode register. UART0 receive interrupt control register (address 72 16) UART1 receive interrupt control register (address 74 16) A-D/UART2 trans./rece. interrupt control register (address 70 16) b7 b0 0 UART0 transmit/receive control register 0 (address 34 16) UART1 transmit/receive control register 0 (address 3C 16) b7 Interrupt priority level selection bits When using interrupts, one of level 1 to 7 must be set. When disabling interrupts, level 0 must be set. b0 0 0 BRG count source selection bits b1b0 0 0: Clock f 2 0 1: Clock f 16 1 0: Clock f 64 1 1: Clock f 512 UART0 transmit/receive control register 1 (address 35 16) UART1 transmit/receive control register 1 (address 3D 16 ) UART2 transmit/receive control register 1 (address 69 16) CTS/RTS function selection bit (Note 2) 0: The CTS function is selected. b7 b0 1 (The RTS function is disabled.) 1: The RTS function is selected. Receive enable bit 1: Reception is enabled. CTS / RTS enable bit 0: The CTS / RTS function is enabled. 1: The CTS / RTS function is disabled. Clocks f 2, f16 , f64, and f512 : Refer to chapter "14. CLOCK GENERATING CIRCUIT." UART2 transmit/receive control register 0 (address 68 16) b7 b0 BRG count source selection bits b1b0 0 0: Clock f 2 0 1: Clock f 16 1 0: Clock f 64 1 1: Clock f 512 Then, reception starts when the start bit is detected. CTS enable bit 0: The CTS function is enabled. 1: The CTS function is disabled (I/O port). Note 2: The CTS/RTS function selection bit is valid when CTS/RTS enable bit = "0." Fig. 8.4.9 Initial setting example for related registers when receiving 7733 Group User's Manual 8-57 SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode [When using interrupts] [When not using interrupts] A UARTi receive interrupt request occurs when reception is completed. Checking the completion of reception UART0 transmit/receive control register 1 (address 35 16) UART1 transmit/receive control register 1 (address 3D 16) UART2 transmit/receive control register 1 (address 69 16) b7 UARTi receive interrupt b0 1 Receive completion flag 0: Reception is not completed. 1: Reception is completed. Checking the error UART0 transmit/receive control register 1 (address 35 16) UART1 transmit/receive control register 1 (address 3D 16) UART2 transmit/receive control register 1 (address 69 16) b0 b7 1 Framing error flag Parity error flag Error sum flag 0: No error is detected. 1: Error is detected. This diagram indicates bits and registers required for processing. Refer to Figure 8.4.12 for details about the change of flag status and the occurrence timing of an interrupt request. Reading out the receive data UART0 receive buffer register (addresses 37 16, 3616) UART1 receive buffer register (addresses 3F 16, 3E16) UART2 receive buffer register (addresses 6B 16, 6A16) b8 b7 b15 b0 0 0 0 0 0 0 0 Read out the receive data Checking the error UART0 transmit/receive control register 1 (address 35 16) UART1 transmit/receive control register 1 (address 3D 16) UART2 transmit/receive control register 1 (address 69 16) b0 b7 1 Overrun error flag 0: No error is detected. 1: Error is detected. Processing after reading out receive data Fig. 8.4.10 Processing after reception is completed 8-58 7733 Group User's Manual SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode 8.4.6 Receive operation When the receive enable bit is set to "1," the UARTi enters the receive enable state. And then, the transfer clock is generated when ST is detected, and reception is____ started. ____ When the RTS function is selected (UART0, UART1), the RTSi pin's output level becomes "L" if the UARTi enters the receive enable state and the____ microcomputer informs the transmitter side that reception is enabled. When reception is started, the RTSi pin's output level becomes "H." Accordingly, by connecting ____ ____ the RTSi pin (receiver side) and the CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. Figure 8.4.11 shows an connection example. The receive operation is described below. The signal which is input from the RxDi pin is taken in the most significant bit of the UARTi receive register synchronously with the transfer clock's rising edge. The contents of UARTi receive register is shifted by 1 bit to the right. Operations and are repeated at each transfer clock's rising edge. When a set of data is prepared, in other words, when shifted several times depending on the specified data format, the UARTi receive register's contents is transferred to the UARTi receive buffer register. Simultaneously with , the receive completion flag is set to "1." Furthermore, a UARTi receive interrupt request occurs and the interrupt request bit is set to "1." The receive completion flag is cleared to "0" when the low-order of the UARTi receive buffer register is read ____ ____ out. The RTSi pin's output level becomes "L" simultaneously with (when RTS function is selected). Figure 8.4.12 shows an example of receive timing when transfer data has a length of 8 bits. Receiver side Transmitter side TxDi TxDi RxDi RxDi CTSi RTSi (Note) Note: The RTSi output function is not assigned for Fig. 8.4.11 Connection example 7733 Group User's Manual 8-59 SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode BRGi count source Receive enable bit "1" "0" Stop bit Start bit RxDi D1 D0 Check whether the level is "L." D7 Received data is taken in. Transfer clock Receive completion "1" flag "0" The transfer clock is generated at the falling edge of start bit, and reception is started. UARTi receive register UARTi receive buffer register "H" (Note) RTSi "L" UARTi receive "1" interrupt request bit "0" Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. The above timing diagram is applied when the following conditions are satisfied: Parity is disabled. 1 stop bit RTS function is selected. Note: The RTSi output function is not assigned for Fig. 8.4.12 Example of receive timing when data is transferred in 8 bits (When parity is disabled and one stop bit) 8-60 7733 Group User's Manual SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode 8.4.7 Processing when error is detected Errors listed below can be detected in the UART mode: Overrun error An overrun error occurs when the next data is prepared in the UARTi receive register with the receive completion flag = "1" (in other words, data is present in the UARTi receive buffer register), and then the next data is transferred to the UARTi receive buffer register. In other words, when the next data is prepared before the contents of the UARTi receive buffer register is read out. When an overrun error occurs, the next receive data is written into the UARTi receive buffer register. At this time, the UARTi receive interrupt request bit is not set to "1." Framing error A framing error occurs when the number of detected stop bits does not match the number which is set. (The UARTi interrupt request bit is set to "1.") Parity error A parity error occurs when the sum of "1"s in the parity bit and character bits does not match the number which is set. (The UARTi interrupt request bit is set to "1.") Each error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register, and the corresponding error flag is set to "1." Furthermore, when any of the above errors occurs, the error sum flag is set to "1." Accordingly, the error sum flag informs whether any error has occurred or not. Error flags are cleared to "0" when the serial I/O mode selection bits are cleared to "000 2" or when the receive enable bit is cleared to "0." (When all of the overrun, framing, and parity error flags are cleared to "0," the error sum flag is cleared to "0.") Note also that the framing and parity error flags are cleared to "0" when the low-order byte of the UARTi receive buffer register is read out. When an error occurs during reception, initialize the error flags and the UARTi receive buffer register, and then perform reception again. When it is necessary to perform transmission again owing to an error which occurs in the receiver side, set the UARTi transmission buffer register again, and then starts transmission again. The method of initializing the UARTi receive buffer register and that of setting the UARTi transmission buffer register again are described below. (1) Method of initializing UARTi receive buffer register Clear the receive enable bit to "0." (Reception is disabled.) Set the receive enable bit to "1" again. (Reception is enabled.) (2) Method of setting UARTi transmission buffer register again Clear the serial I/O mode selection bits to "000 2." (Serial I/O is ignored.) Set the serial I/O mode selection bits again. Set the transmit enable bit to "1." (Transmission is enabled.) And set the transmit data to the UARTi transmission buffer register. 8.4.8 Precautions for UART For performing the transmission and the reception simultaneously, UART2 does not distinguish the transmission interrupt from the reception interrupt. The UART2 transmission/reception interrupt request occurs when either interrupt request occurs. Accordingly, in the system which performs the transmission and reception simultaneously for UART2, not use the UART2 transmission/reception interrupt but use the method of poling the transmission buffer empty flag and the receive completion flag by software. 7733 Group User's Manual 8-61 SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode 8.4.9 Sleep mode (UART0 and UART1) This mode is used when data is transferred between the master microcomputer and one slave microcomputer, which is selected from multiple slave microcomputers connected to the master microcomputer using UARTi. The sleep mode is selected when the sleep selection bit (bit 7 at addresses 3016 and 3816 ) is set to "1" at receiving. In the sleep mode, the receive operation is performed when the MSB (D8 when the transfer data has a length of 9 bits; D7 when the transfer data has a length of 8 bits; D 6 when the transfer data has a length of 7 bits) of the receive data = "1." The receive operation is not performed when the MSB = "0." (The UARTi receive register's contents is not transferred to the UARTi receive buffer register. The receive completion flag and error flags do not change and a UARTi receive interrupt request does not occur, also.) A usage example of the sleep mode when the transfer data has a length of 8 bits is described below. Set the same transfer data format for the master and slave microcomputers. Select the sleep mode for the slave microcomputer. Transmit the data, which has "1" in bit 7 and the address of the slave microcomputer to be communicated in bits 6 to 0, from the master microcomputer to all slave microcomputers. All slave microcomputers receive data in operation . (At this time, a UARTi receive interrupt request occurs.) For all slave microcomputers, check in the interrupt routine whether bits 6 to 0 in the receive data match their own addresses. For the slave microcomputer whose address matches bits 6 to 0 in the receive data, terminate the sleep mode. (Do not terminate the sleep mode for the other slave microcomputers.) By performing operations to , "the slave microcomputer which performs transmission" can be specified. Transmit the data, which has "0" in bit 7, from the master microcomputer. (Only the microcomputer selected by operations to receives this data. The other microcomputers do not receive this data.) By repeating operation , data is transferred between two specific microcomputers in succession. Also, by performing operations to , another slave microcomputer can be specified. Master Slave A Slave B Data is transferred between the master microcomputer and one specific slave microcomputer, which is selected from multiple slave microcomputers. Slave C Fig. 8.4.13 Sleep mode 8-62 7733 Group User's Manual Slave D CHAPTER 9 A-D CONVERTER 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Overview Block description A-D conversion method Absolute accuracy and Differential non-linearity error One-shot mode Repeat mode Single sweep mode Repeat sweep mode Precautions for A-D converter A-D CONVERTER 9.1 Overview The A-D converter is described below. For this A-D converter, 8-bit resolution or 10-bit resolution can be selected. It's conversion method is the successive approximation method and has 8 analog input pins. 9.1 Overview The performance overview is listed in Table 9.1.1. Table 9.1.1 Performance overview Item Performance Resolution Successive approximation method 8/10 bits can be selected by software Absolute accuracy 8-bit resolution: 2 LSB A-D conversion method 10-bit resolution: 3 LSB Analog input pin Conversion rate per analog input pin 8 pins (AN 0 to AN 7 ) 8-bit resolution: 49 AD cycles 10-bit resolution: 59 AD cycles AD : A-D converter's operating clock The A-D convertor has the following four operation modes. One-shot mode A-D conversion is once performed for the input voltage of one analog input pin. Repeat mode A-D conversion is repeatedly performed for the input voltage of one analog input pin. Single sweep mode A-D conversion is performed for the input voltage of multiple analog input pins, one at a time. Repeat sweep mode A-D conversion is repeatedly performed for the input voltage of multiple analog input pins. 9-2 7733 Group User's Manual A-D CONVERTER 9.2 Block description 9.2 Block description Figure 9.2.1 shows the block diagram of the A-D converter. Registers related to the A-D converter are described below. A-D conversion frequency selection AD f VREF connection selection 1/2 2 1/2 VREF Resistor ladder network Vref AVSS Successive approximation register A-D control register 1 A-D control register 0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 Decoder A-D register 4 A-D register 5 A-D register 6 A-D register 7 Data bus (Odd) Comparator Data bus (Even) AN0 AN1 AN2 AN3 VIN AN4 AN5/AD TRG AN6 AN7 Selector Fig. 9.2.1 Block diagram of A-D converter 7733 Group User's Manual 9-3 A-D CONVERTER 9.2 Block description 9.2.1 A-D control register 0 Figure 9.2.2 shows the structure of A-D control register 0. A-D operation mode selection bits select an operation mode of A-D converter. The other bits are described below. b7 b6 b5 b4 b3 b2 b1 b0 @A-D control register 0 (address 1E 16) Bit name Bit Analog input selection bits (Valid in the one-shot and repeat modes) (Note 1) 0 1 @ 2 @ 3 4 A-D operation mode selection bits @ Functions At reset RW Undefined RW Undefined RW Undefined RW 0 RW 0 RW b2 b1 b0 0 0 0: AN 0 is stopped. 0 0 1: AN 1 is stopped. 0 1 0: AN 2 is stopped. 0 1 1: AN 3 is stopped. 1 0 0: AN 4 is stopped. 1 0 1: AN 5 is stopped. (Note 2) 1 1 0: AN 6 is stopped. 1 1 1: AN 7 is stopped. b4b3 00: One-shot mode 01: Repeat mode 10: Single sweep mode 11: Repeat sweep mode 5 Trigger selection bit 0: Internal trigger 1: External trigger 0 RW 6 A-D conversion start flag 0: A-D conversion is stopped. 1: A-D conversion is started. 0 RW 7 A-D conversion frequency ( AD) selection flag 0: f 2/4 1: f 2/2 0 RW f2: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Notes 1: These bits are ignored in the single sweep and repeat sweep modes. (They may be "0" or "1.") 2: When an external trigger is selected, pin AN 5 cannot be used as an analog input pin. 3: Writing to each bit (except bit 6) of the A-D control register 0 must be performed while the A-D converter stops operating. Fig. 9.2.2 Structure of A-D control register 0 (1) Analog input selection bits (bits 2 to 0) These bits are used to select an analog input pin in the one-shot and repeat modes. (Refer to section "9.2.5 Port P7 direction register.") When switching the operating mode to the one-shot or repeat mode after A-D conversion is once performed in the single sweep or repeat sweep mode, set these bits again. 9-4 7733 Group User's Manual A-D CONVERTER 9.2 Block description (2) Trigger selection bit (bit 5) This bit selects a trigger occurrence source. (Refer to "(3) A-D conversion start flag.") (3) A-D conversion start flag (bit 6) When internal trigger is selected When this bit is set to "1," a trigger occurs, and then the A-D converter starts operating. When this bit is cleared to "0," the A-D converter stops operating. In the one-shot or single sweep mode, this bit is cleared to "0" after A-D conversion is completed. In the repeat or repeat sweep mode, the A-D converter continues operating until this bit is cleared to "0" by software. When external trigger is selected ______ If the ADTRG pin level goes from "H" to "L" when this bit = "1," a trigger occurs, and then the A-D converter starts operating. The A-D converter stops operating when this bit is cleared to "0." In the one-shot or single sweep mode, this bit remains set to "1" even after A-D conversion is completed. In the repeat or repeat sweep mode, the A-D converter continues operating until this bit is cleared to "0" by software. (4) A-D conversion frequency ( AD) selection flag (bit 7) Conversion time varies according to the A-D converter's operating clock (AD) selected by this bit as listed in Table 9.2.1. Since the A-D converter's comparator consists of capacity coupling amplifiers, keep that AD 250 kHz during A-D conversion. Table 9.2.1 Conversion time per one analog input pin (Unit: s) A-D conversion frequency ( AD) selection flag 0 AD Conversion time Resolution : 8 bits *System clock = 25 MHz (Note) Resolution : 10 bits 1 f 2 divided by 4 f 2 divided by 2 15.68 7.84 18.88 9.44 Note: This is applied when the following conditions are satisfied; *f(XIN) = 25 MHz *The main clock is selected as the system clock. *Main clock divided by 2 is available. 7733 Group User's Manual 9-5 A-D CONVERTER 9.2 Block description 9.2.2 A-D control register 1 Figure 9.2.3 shows the structure of A-D control register 1. b7 b6 b5 b4 0 b3 b2 b1 b0 A-D control register 1 (address 1F 16) Bit 0 1 Bit name Functions b1 b0 A-D sweep pin selection bits 0 0: Pins AN 0 and AN 1 (2 pins) (Valid in the single sweep and repeat sweep modes.) (Note 1) 0 1: Pins AN 0 to AN 3 (4 pins) 1 0: Pins AN0 to AN5 (6 pins) (Note 2) 1 1: Pins AN 0 to AN 7 (8 pins) 2 Not implemented. 3 8/10-bit mode selection bit 4 Must be fixed to "0." 5 VREF connection selection bit (Note 4) 6 Not implemented. 0: 8-bit resolution 1: 10-bit resolution 0: Pin V REF is connected. 1: Pin V REF is disconnected. (High impedance) At reset RW 1 RW 1 RW Undefined _ 0 RW 0 RW 0 RW Undefined _ 7 Notes 1: These bits are ignored in the one-shot and repeat modes. (They may be "0" or "1.") 2: When an external trigger is selected, pin AN 5 cannot be used as an analog input pin. 3: Writing to each bit of the A-D control register 1 must be performed while the A-D converter stops operating. 4: When the V REF connection selection bit is cleared from "1" to "0," wait for an interval of 1 s or more passed, and then start A-D conversion. Fig. 9.2.3 Structure of A-D control register 1 (1) A-D sweep pin selection bits (bits 1 and 0) These bits are used to select analog input pins in the single sweep and repeat sweep modes. Refer to section "9.2.5 Port P7 direction register." (2) V REF connection selection bit (bit 5) This bit is used to disconnect the A-D converter's resistor ladder network from the reference voltage input pin (V REF) when not using the A-D converter. When pin V REF is disconnected from the resistor ladder network, no current flows from pin V REF to the resistor ladder network. 9-6 7733 Group User's Manual A-D CONVERTER 9.2 Block description 9.2.3 A-D register i (i = 0 to 7) Figure 9.2.4 shows the structure of A-D register i. When A-D conversion is completed, the conversion result (in other words, the contents of the successive approximation register) is stored into this register. Each AD register i corresponds to an analog input pin (ANi ), one for one. Table 9.2.2 lists the correspondence of an analog input pin to A-D register i. When resolution = 8 bits (b15) (b8) b7 b0 b7 b0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 (addresses 21 16 and 20 16) (addresses 23 16 and 22 16) (addresses 25 16 and 24 16) (addresses 27 16 and 26 16) (addresses 29 16 and 28 16) (addresses 2B 16 and 2A 16) (addresses 2D 16 and 2C 16) (addresses 2F 16 and 2E 16) Bit 7 to 0 15 to 8 When resolution = 10 bits (b15) (b8) b7 b0 b7 b0 Functions The A-D conversion result is read out. "0" at reading. At reset RW Undefined RO 0 RO At reset RW Undefined RO 0 RO A-D register 0 (addresses 21 16 and 20 16) A-D register 1 (addresses 23 16 and 22 16) A-D register 2 (addresses 25 16 and 24 16) A-D register 3 (addresses 27 16 and 26 16) A-D register 4 (addresses 29 16 and 28 16) A-D register 5 (addresses 2B 16 and 2A 16) A-D register 6 (addresses 2D 16 and 2C 16) A-D register 7 (addresses 2F 16 and 2E 16) Bit 9 to 0 Functions The A-D conversion result is read out. 15 to 10 "0" at reading. Fig. 9.2.4 Structure of A-D register i Table 9.2.2 Correspondence of analog input pin and A-D register i Analog input pin A-D register i where conversion result is stored Pin AN 0 A-D register 0 Pin AN 1 A-D register 1 Pin AN 2 A-D register 2 Pin AN 3 Pin AN 4 A-D register 3 Pin AN 5 A-D register 4 A-D register 5 Pin AN 6 A-D register 6 Pin AN 7 A-D register 7 7733 Group User's Manual 9-7 A-D CONVERTER 9.2 Block description 9.2.4 A-D/UART2 trans./rece. interrupt control register Figure. 9.2.5 shows the structure of the A-D/UART2 trans./rece. control register. The A-D conversion interrupt and UART2 transmission/reception interrupt share the same interrupt control register and interrupt vector addresses. When UART2 is selected, the A-D/UART2 trans./rece. interrupt control register functions as an register which control the UART2 transmission/reception interrupt. At this time, the A-D conversion interrupt cannot be used. For details on interrupts, refer to chapter "4. INTERRUPTS." For details on UART2, refer to chapter "8. SERIAL I/O." The case where this register is used as the A-D conversion interrupt control register is described below. b7 b6 b5 b4 b3 b2 b1 b0 A-D/UART2 trans./rece. interrupt control register (address 70 Bit Bit name 0 Interrupt priority level selection bits 1 2 3 7 to 4 Interrupt request bit (Note) 16) Functions b2 b1 b0 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 Priority is low. 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Priority is high. 0: No interrupt request has occurred. 1: Interrupt request has occurred. Not implemented. At reset RW 0 RW 0 RW 0 RW 0 RW Undefined - Note: When UART2 is selected, in other words, when a serial I/O mode is selected by specifying the serial I/O mode selection bits (bits 0 to 2 at address 64 16), this bit is set to "1." Fig. 9.2.5 Structure of A-D/UART2 trans./rece. interrupt control register 9-8 7733 Group User's Manual A-D CONVERTER 9.2 Block description (1) Interrupt priority level selection bits (bits 2 to 0) These bits select an A-D conversion interrupt's priority level. When using A-D conversion interrupts, select one priority level from levels 1 to 7. If an A-D conversion interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL), and the requested interrupt is enabled only when its priority level is higher than the IPL. (Note that this is applied to the case where the interrupt disable flag (I) = "0.") When disabling A-D conversion interrupts, set these bits to "000 2" (Level 0). (2) Interrupt request bit (bit 3) This bit is set to "1" when an A-D conversion interrupt request occurs. This bit is automatically cleared to "0" when the A-D conversion interrupt request is accepted. Note that this bit can be set to "1" or cleared to "0" by software. 7733 Group User's Manual 9-9 A-D CONVERTER 9.2 Block description 9.2.5 Port P7 direction register Input pins of the A-D converter are multiplexed with port P7. When using these pins as A-D converter's input pins, set the corresponding bits of the port P7 direction register to "0" to set these ports for the input mode. Figure 9.2.6 shows the relationship between the port P7 direction register and I/O pins of the subclock oscillation circuit and peripheral functions. b7 b6 b5 b4 b3 b2 b1 b0 Port P7 direction register (address 11 16) Bit Corresponding bit's name 0 Pin AN0 1 Pin AN1 Functions At reset RW 0 RW 0 RW 0 RW 0: Input mode 1: Output mode When using these pins as A-D converter's input pins, set the corresponding bits to "0." 2 Pin AN2/CTS 2 3 Pin AN3/CLK 2 0 RW 4 Pin AN4/RxD 2 0 RW 5 Pin AN5/AD TRG/TxD2 0 RW 6 Pin AN6/XCOUT 0 RW 7 Pin AN7/XCIN 0 RW Fig. 9.2.6 Relationship between port P7 direction register and I/O pins of sub-clock oscillation circuit and peripheral functions Analog input pins function as the port P7's I/O pins and also function as I/O pins of the sub-clock oscillation circuit and UART2. For pins which are forcedly set to the output mode when the function for the sub-clock oscillation circuit or UART2 is selected, analog input is disabled. (Refer to "Table 9.2.3.") Table 9.2.3 Port P7's pin which is forcedly set to output mode Pin P7 3/AN3/CLK2 Conditions where pin is forcedly set to output mode Clock synchronous serial I/O mode is selected and an internal clock is used. (bits 3 to 0 at address 64 16 = "0001 2 ") _____ P7 5/AN 5/ AD TRG/TxD 2 Serial I/O mode is selected. (bits 2 to 0 at address 64 16 = "001 2," "100 2 ," "101 2 ," or "110 2") P7 6/AN 6/X COUT Sub-clock oscillation circuit is operating by itself. (bit 4 at address 6C 16 = "1" and bit 2 at address 6F 16 = "0" ) 9-10 7733 Group User's Manual A-D CONVERTER 9.3 A-D conversion method 9.3 A-D conversion method The A-D converter compares the comparison voltage (V ref), which is internally generated according to the contents of the successive approximation register, and the analog input voltage (V IN), which is input from the analog input pin. By reflecting the comparison result on the successive approximation register, VIN is converted into a digital value (successive approximation method). When a trigger occurs, the A-D converter performs the following processing: Determination of successive approximation register's bit 9 The A-D converter compares V ref and V IN . At this time, contents of the successive approximation register is "10000000002 " (Initial value). Bit 9 of the successive approximation register changes according to the comparison result as follows: If V ref < V IN , bit 9 = "1" If V ref > V IN , bit 9 = "0" Determination of successive approximation register's bit 8 After setting bit 8 of the successive approximation register to "1," the A-D converter compares V ref and V IN. Bit 8 changes according to the comparison result as follows: If V ref < V IN , bit 8 = "1" If V ref > V IN , bit 8 = "0" Determination of successive approximation register's bits 7 to LSB When resolution = 8 bits ........... For bits 7 to 2, perform operation . When resolution = 10 bits ......... For bits 7 to 0, perform operation . When the LSB is determined, the contents of the successive approximation register, in other words, the conversion result is transferred to the A-D register i. Vref is generated according to the latest contents of the successive approximation register. Table 9.3.1 lists the relationship between the successive approximation register's contents and Vref. Tables 9.3.2 and 9.3.3 list changes of the successive approximation register and V ref during A-D conversion. Figure 9.3.1 shows theoretical A-D conversion characteristics when resolution = 10 bits. Table 9.3.1 Relationship between successive approximation register's contents and Vref Successive approximation register's contents: n 0 Vref (V) 0 VREF 1 to 1023 1024 x (n - 0.5) VREF: Reference voltage 7733 Group User's Manual 9-11 A-D CONVERTER 9.3 A-D conversion method Table 9.3.2 Change of successive approximation register and Vref during A-D conversion (when resolution = 8 bits) Successive approximation register b9 Vref b0 A-D converter stopped 1 0 0 0 0 0 0 0 0 0 VREF [V] 2 1st comparison 1 0 0 0 0 0 0 0 0 0 VREF VREF - [V] 2 2048 2nd comparison n9 1 0 0 0 0 0 0 0 0 3rd comparison n9 n8 1 0 0 0 0 0 0 0 1st comparison result 2nd comparison result 8th comparison n9 n8 n7 n6 n5 n4 n 3 1 0 0 Conversion complete n9 n8 n7 n6 n5 n4 n 3 n2 0 0 *When n 9 = 1, + VREF VREF 4 VREF - VREF [V] 2 4 2048 *When n 9 = 0, - VREF 4 VREF VREF VREF *When n 8 = 1, + VREF VREF 8 - [V] 8 2 2048 4 *When n 8 = 0, - VREF 8 VREF VREF VREF 2 8 4 VREF [V] VREF - 256 2048 Table 9.3.3 Change of successive approximation register and Vref during A-D conversion (when resolution = 10 bits) Successive approximation register b9 Vref b0 A-D converter stopped 1 0 0 0 0 0 0 0 0 0 VREF [V] 2 1st comparison 1 0 0 0 0 0 0 0 0 0 VREF VREF - [V] 2 2048 2nd comparison n9 1 0 0 0 0 0 0 0 0 *When n 9 = 1, + VREF VREF VREF 4 - [V] *When n 9 = 0, - VREF 2 4 2048 4 3rd comparison n9 n8 1 0 0 0 0 0 0 0 1st comparison result 2nd comparison result 10th comparison n9 n8 n7 n6 n5 n4 n 3 n 2 n1 1 Conversion complete n9 n8 n7 n6 n5 n4 n 3 n2 n1 n0 9-12 VREF *When n 8 = 1, + VREF VREF VREF VREF - VREF 8 [V] 8 2 2048 4 *When n 8 = 0, - VREF 8 VREF VREF VREF 2 8 4 7733 Group User's Manual VREF - VREF [V] 1024 2048 A-D CONVERTER 9.3 A-D conversion method A-D conversion result Theoretical A-D conversion characteristics 3FF16 3FE 16 3FD 16 00316 00216 00116 00016 0 VREF 1 1024 VREF 2 1024 VREF 3 1024 VREF VREF VREF 1022 1023 1021 1024 1024 1024 VREF 0.5 1024 VREF Analog input voltage Fig. 9.3.1 Theoretical A-D conversion characteristics when resolution = 10 bits 7733 Group User's Manual 9-13 A-D CONVERTER 9.4 Absolute accuracy and Differential non-linearity error 9.4 Absolute accuracy and Differential non-linearity error The A-D conversion's accuracy is described below. 9.4.1 Absolute accuracy The absolute accuracy is the difference expressed in the LSB between the actual A-D conversion result and the output code of an A-D converter with ideal characteristics. The analog input voltage when measuring the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code from an A-D converter with ideal characteristics. For example, in the case of the 10-bit resolution, when VREF = 5.12 V, 1-LSB width is 5 mV, and 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, ... are selected as the analog input voltages. The absolute accuracy = 3 LSB when the analog input voltage = 25 mV indicates that the output code expected from an ideal A-D conversion characteristics is "00516" but the actual A-D conversion result is between "00216" to "008 16 ." The absolute accuracy includes the zero error and the full-scale error. The absolute accuracy degrades when VREF is lowered. The output codes for analog input voltages between VREF and AV CC are "3FF 16." Output code (A-D conversion result) 00B16 00A16 00916 +3 LSB 00816 Ideal A-D conversion characteristics 00716 00616 00516 00416 00316 00216 -3 LSB 00116 00016 0 5 10 15 20 25 30 35 40 45 50 Analog input voltage (mV) Fig. 9.4.1 Absolute accuracy of A-D converter (when resolution = 10 bits) 9-14 7733 Group User's Manual 55 A-D CONVERTER 9.4 Absolute accuracy and Differential non-linearity error 9.4.2 Differential non-linearity error The differential non-linearity error indicates the difference between the 1-LSB step width (the ideal analog input voltage width while the same output code is expected to output) of an A-D converter with ideal characteristics and the actual measured step width (the actual analog input voltage width while the same output code is output). For example, in the case of the 10-bit mode, when V REF = 5.12 V, the 1-LSB width of an A-D converter with ideal characteristics is 5 mV, but if the differential non-linearity error is 1 LSB, the actual measured 1-LSB width is 0 to 10 mV. (Refer to section "16.1.4 A-D converter standard characteristics.") Output code (A-D conversion result) 009 16 1-LSB width with A-D conversion characteristics 008 16 007 16 006 16 005 16 004 16 003 16 002 16 001 16 Differential non-linearity error 000 16 0 5 10 15 20 25 30 35 40 45 Analog input voltage (mV) Fig. 9.4.2 Differential non-linearity error (when resolution = 10 bits) 7733 Group User's Manual 9-15 A-D CONVERTER 9.4 Absolute accuracy and Differential non-linearity error 9.4.3 Comparison voltage when resolution = 8 bits When 8-bit resolution is selected in the M37733MHBXXXFP, the high-order 8 bits of the 10-bit successive approximation register is the conversion result. Accordingly, when compared with the 8-bit A-D converter, the comparison reference voltage is different by 3VREF/2048 (refer to the underlined portions in the Table 9.4.1). The difference of the output code change point is generated as shown in Figure 9.4.3. Table 9.4.1 Compare reference voltage M37733MHBXXXFP (When resolution = 8 bits) 8-bit A-D converter V REF1/28 n 2 - V REF/2 10 0.5 V REF/2 8 n - V REF/2 8 0.5 Comparison reference voltage Vref VREF 1: Reference voltage n 2: Contents of successive approximation register 8-bit A-D converter (When VREF = 5.12 V) Output code (A-D conversion result) 02 01 00 10 30 Analog input voltage (mV) M37733MHBXXXFP's A-D converter with ideal characteristics (When VREF = 5.12 V) Output code (A-D conversion result) 8-bit resolution 02 01 00 10-bit resolution 09 08 07 06 05 04 03 02 01 00 10-bit resolution 8-bit resolution () () 17.5 37.5 Analog input voltage (mV) : Difference from output code change point VREF: Reference voltage Fig. 9.4.3 Difference of output code change point 9-16 7733 Group User's Manual A-D CONVERTER 9.5 One-shot mode 9.5 One-shot mode *A-D operation mode selection bits (bits 4 and 3 at address 1E 16 ) = "00 2" In this mode, A-D conversion is once performed for the input voltage of one analog input pin. An A-D conversion interrupt request occurs when the A-D conversion is completed. Note that an A-D conversion interrupt cannot be used when the UART2 transmission/reception interrupt is used. 9.5.1 Setting for one-shot mode Figure 9.5.1 shows an initial setting example for registers related to the one-shot mode. When using interrupts, settings for enabling interrupts are required. For details, refer to chapter "4. INTERRUPTS." 7733 Group User's Manual 9-17 A-D CONVERTER 9.5 One-shot mode Setting of the A-D control registers 0, 1 b7 b7 b0 0 0 0 b0 0 0 A-D control register 0 (address 1E 16) A-D control register 1 (address 1F 16) 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution Analog input selection bits b2b1b0 0 0 0: AN 0 is selected. 0 0 1: AN 1 is selected. 0 1 0: AN 2 is selected. 0 1 1: AN 3 is selected. 1 0 0: AN 4 is selected. 1 0 1: AN 5 is selected. 1 1 0: AN 6 is selected. 1 1 1: AN 7 is selected. VREF connection selection bit 0: Pin VREF is connected. Selection of the one-shot mode Trigger selection bit 0: Internal trigger 1: External trigger A-D conversion start flag 0: A-D conversion is stopped. A-D conversion frequency ( AD) : It may be "0" or "1." f2: Refer to chapter "14. CLOCK GENERATING CIRCUIT." selection flag 0: f 2/4 1: f2/2 Setting of the interrupt priority level b7 b0 A-D/UART2 trans./rece. interrupt control register (address 70 16) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Setting of the port P7 direction register b7 b0 Port P7 direction register (address 11 16) Setting of the A-D conversion start flag to "1" b7 AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 b0 1 Set bits corresponding to selected analog input pins to "0." When an external trigger is selected, set bit 7 to "0." A-D control register 0 (address 1E 16) A-D conversion start flag When external trigger is selected Falling edges input to pin AD TRG Note: Writing to each bit (except bit 6) of the A-D control register 0 and each bit of the A-D control register 1 must be performed while A-D converter stops operating, in other words, before a trigger is generated. When the V REF connection selection bit is cleared from "1" to "0," wait for an interval of 1 s or more passed, and then generate a trigger. When internal trigger is selected Trigger is generated. A-D conversion is started. Fig. 9.5.1 Initial setting example for registers related to one-shot mode 9-18 7733 Group User's Manual A-D CONVERTER 9.5 One-shot mode 9.5.2 Operation in one-shot mode Figure 9.5.2 shows the conversion operation in the one-shot mode. (1) When internal trigger is selected By setting the A-D conversion start flag to "1," the A-D converter starts operating. The A-D conversion is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register i. *49 cycles of AD have passed when resolution = 8 bits *59 cycles of AD have passed when resolution = 10 bits When a UART2 trans./rece. interrupt is not used, the A-D conversion interrupt request bit is set to "1" simultaneously with . The A-D conversion start flag is cleared to "0," and then the A-D converter stops operating. (2) When external trigger is selected ______ If pin ADTRG's level goes from "H" to "L" when the A-D conversion start flag = "1," the A-D converter starts operating. The A-D conversion is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register i. *49 cycles of AD have passed when resolution = 8 bits *59 cycles of AD have passed when resolution = 10 bits When a UART2 trans./rece. interrupt is not used, the A-D conversion interrupt request bit is set to "1" simultaneously with . The A-D converter stops operating. The A-D conversion start flag remains set to "1" after the A-D converter stops operating. Accordingly, when ______ pin AD TRG's level goes from "H" to "L", the A-D converter restarts conversion from . Note that when pin ______ AD TRG's level goes from "H" to "L" during A-D conversion, the converter quits the conversion which is performed at that time and restarts it from . Trigger is generated. Conversion result Input voltage of ANi pin is converted. A-D register i A-D conversion interrupt request occurs. A-D converter is stopped. Fig. 9.5.2 Conversion operation in one-shot mode 7733 Group User's Manual 9-19 A-D CONVERTER 9.6 Repeat mode 9.6 Repeat mode *A-D operation mode selection bits (bits 4 and 3 at address 1E 16 ) = "01 2" In this mode, A-D conversion is repeatedly performed for the input voltage of one analog input pin. No A-D conversion interrupt request occurs in this mode. The A-D conversion start flag (bit 6 at address 1E16) remains set to "1" until it is cleared to "0" by software. While the A-D conversion start flag = "1," the A-D converter repeats A-D conversion without a stop. 9.6.1 Setting for repeat mode Figure 9.6.1 shows an initial setting example for registers related to the repeat mode. 9-20 7733 Group User's Manual A-D CONVERTER 9.6 Repeat mode Setting of the A-D control registers 0, 1 b7 b0 0 0 1 b7 b0 0 0 A-D control register 0 (address 1E16) A-D control register 1 (address 1F16) Analog input selection bits 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution b2b1b0 0 0 0: AN0 is selected. 0 0 1: AN1 is selected. 0 1 0: AN2 is selected. 0 1 1: AN3 is selected. 1 0 0: AN4 is selected. 1 0 1: AN5 is selected. 1 1 0: AN6 is selected. 1 1 1: AN7 is selected. VREF connection selection bit 0: Pin VREF is connected. Selection of the repeat mode Trigger selection bit 0: Internal trigger 1: External trigger A-D conversion start flag 0: A-D conversion is stopped. A-D conversion frequency ( 0: f2/4 1: f2/2 AD) selection flag : It may be "0" or "1." f2: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Setting of the port P7 direction register b7 b0 Port P7 direction register (address 1116) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Set bits corresponding to selected analog input pins to "0." When an external trigger is selected, set bit 7 to "0." Setting of the A-D conversion start flag to "1" b7 b0 1 A-D control register 0 (address 1E16) A-D conversion start flag When external trigger is selected Falling edges input to Pin When internal trigger is selected ADTRG Note: Writing to each bit (except bit 6) of the A-D control register 0 and each bit of the A-D control register 1 must be performed while A-D converter stops operating, in other words, before a trigger is generated. When the VREF connection selection bit is cleared from "1" to "0," wait for an interval of 1 s or more passed, and then Trigger generate a trigger. is generated. A-D conversion is started. Fig. 9.6.1 Initial setting example for registers related to repeat mode 7733 Group User's Manual 9-21 A-D CONVERTER 9.6 Repeat mode 9.6.2 Operation in repeat mode Figure 9.6.2 shows the conversion operation in the repeat mode. (1) When internal trigger is selected When the A-D conversion start flag is set to "1," the A-D converter starts operating. The first A-D conversion is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register i. *49 cycles of AD have passed when resolution = 8 bits *59 cycles of AD have passed when resolution = 10 bits The A-D converter continues operating until the A-D conversion start flag is cleared to "0" by software. Each time A-D conversion is completed, the conversion result is transferred to the A-D register i. (2) When external trigger is selected ______ If pin ADTRG's level goes from "H" to "L" when the A-D conversion start flag = "1," the A-D converter starts operating. The first A-D conversion is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register i. *49 cycles of AD have passed when resolution = 8 bits *59 cycles of AD have passed when resolution = 10 bits The A-D converter continues operating until the A-D conversion start flag is cleared to "0" by software. Each time A-D conversion is completed, the conversion result is transferred to the A-D register i. ______ Note that when pin AD TRG's level goes from "H" to "L" during A-D conversion, the A-D converter quits the conversion which is performed at that time and restarts it from . Trigger is generated. Conversion result Input voltage of AN i pin is converted. Fig. 9.6.2 Conversion operation in repeat mode 9-22 7733 Group User's Manual A-D register i A-D CONVERTER 9.7 Single sweep mode 9.7 Single sweep mode *A-D operation mode selection bits (bits 4 and 3) = "102 " In this mode, A-D conversion is performed for the input voltage of multiple analog input pins, one at a time. A-D conversion is performed in order of AN0, AN1, AN2, .... An A-D conversion interrupt request occurs when A-D conversions are completed for all analog input pins selected. 9.7.1 Setting for single sweep mode Figure 9.7.1 shows an initial setting example for registers related to the single sweep mode. When using interrupts, settings for enabling interrupts are required. For details, refer to chapter "4. INTERRUPTS." 7733 Group User's Manual 9-23 A-D CONVERTER 9.7 Single sweep mode Setting of the A-D control registers 0, 1 b7 b0 0 1 0 5 5 b7 5 b0 0 0 A-D control register 0 (address 1E 16) A-D sweep pin selection bits Selection of the single sweep mode b1b0 0 0: AN0 and AN1 (2 pins) 0 1: AN0 to AN3 (4 pins) 1 0: AN0 to AN5 (6 pins) 1 1: AN0 to AN7 (8 pins) Trigger selection bit 0: Internal trigger 1: External trigger A-D conversion start flag 0: A-D conversion is stopped. A-D conversion frequency ( 0: f2/4 1: f2/2 5 A-D control register 1 (address 1F 16) AD) 8/10-bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution selection flag VREF connection selection bit 0: Pin VREF is connected. : It may be "0" or "1." f2: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Setting of the interrupt priority level b7 b0 A-D/UART2 trans./rece. interrupt control register (address 70 16) Interrupt priority level selection bits When using interrupts, one of levels 1 to 7 must be set. When disabling interrupts, level 0 must be set. Setting of the port P7 direction register b7 b0 Port P7 direction register (address 11 16) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Set bits corresponding to selected analog input pins to "0." When an external trigger is selected, set bit 7 to "0." When external trigger is selected Setting of the A-D conversion start flag to "1" b7 b0 1 A-D control register 0 (address 1E 16) When internal trigger is selected Falling edges input to Pin ADTRG A-D conversion start flag Note: Writing to each bit (except bit 6) of the A-D control register 0 and each bit of the A-D control register 1 must be performed while A-D converter stops operating, in other words, before a trigger is generated. When the V REF connection selection bit is cleared from "1" to "0," wait for an interval of 1 s or more passed, and then generate a trigger. Trigger is generated. A-D conversion is started. Fig. 9.7.1 Initial setting example for registers related to single sweep mode 9-24 7733 Group User's Manual A-D CONVERTER 9.7 Single sweep mode 9.7.2 Operation in single sweep mode Figure 9.7.2 shows the conversion operation in the single sweep mode. (1) When internal trigger is selected When the A-D conversion start flag is set to "1," the A-D converter starts A-D conversion for an input voltage of pin AN 0. The A-D conversion for pin AN0 is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register 0. *49 cycles of AD have passed when resolution = 8 bits *59 cycles of AD have passed when resolution = 10 bits A-D conversion is performed for all analog input pins selected. Each time A-D conversion is completed for a pin, the conversion result is transferred to the A-D register i which corresponds to the pin. When a UART2 trans./rece. interrupt is not used, the A-D conversion interrupt request bit is set to "1" at completion of . The A-D conversion start flag is cleared to "0," and the A-D converter stops operating. (2) When external trigger is selected ______ If pin ADTRG's level goes from "H" to "L" when the A-D conversion start flag = "1," the A-D converter starts A-D conversion for the input voltage of pin AN 0. The A-D conversion for pin AN0 is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register 0. *49 cycles of AD have passed when resolution = 8 bits *59 cycles of AD have passed when resolution = 10 bits A-D conversion is performed for all analog input pins selected. Each time A-D conversion is completed for a pin, the conversion result is transferred to the A-D register i which corresponds to the pin. When a UART2 trans./rece. interrupt is not used, the A-D conversion interrupt request bit is set to "1" at completion of . The A-D converter stops operating. ______ The A-D conversion start flag remains set to "1" after this. Accordingly, when pin ADTRG's level goes from ______ "H" to "L," the A-D converter restarts conversion from . Note that if pin ADTRG's level goes from "H" to "L" during A-D conversion, the A-D converter quits the conversion which is performed at that time and restarts it from . 7733 Group User's Manual 9-25 A-D CONVERTER 9.7 Single sweep mode Trigger is generated. Conversion result A-D register 0 Input voltage of pin AN 0 is converted. Conversion result A-D register 1 Input voltage of pin AN 1 is converted. Conversion result Input voltage of pin AN i is converted. A-D register i A-D conversion interrupt request occurs. A-D converter is stopped. Fig. 9.7.2 Conversion operation in single sweep mode 9-26 7733 Group User's Manual A-D CONVERTER 9.8 Repeat sweep mode 9.8 Repeat sweep mode *A-D operation mode selection bits (bits 4 and 3 at address 1E 16 ) = "11 2" In this mode, A-D conversion is repeatedly performed for the input voltage of multiple analog input pins. A-D conversion is performed in order of AN 0 , AN 1, AN 2 , .... No A-D conversion interrupt request occurs in this mode. The A-D conversion start flag (bit 6 at address 1E16) remains set to "1" until it is cleared to "0" by software. While the A-D conversion start flag is "1," the A-D converter repeats A-D conversion without a stop. 9.8.1 Setting for repeat sweep mode Figure 9.8.1 shows an initial setting example for registers related to the repeat sweep mode. 7733 Group User's Manual 9-27 A-D CONVERTER 9.8 Repeat sweep mode Setting of the A-D control registers 0, 1 b7 b0 0 b7 b0 0 0 1 1 A-D control register 0 (address 1E 16) A-D control register 1 (address 1F 16) A-D sweep pin selection bits Selection of the repeat sweep mode b1b0 0 0: AN0 and AN1 (2 pins) 0 1: AN0 to AN3 (4 pins) 1 0: AN0 to AN5 (6 pins) 1 1: AN0 to AN7 (8 pins) Trigger selection bit 0: Internal trigger 1: External trigger A-D conversion start flag 0: A-D conversion is stopped. AD) A-D conversion frequency ( 0: f2/4 1: f2/2 8-10 bit mode selection bit 0: 8-bit resolution 1: 10-bit resolution selection flag VREF connection selection bit 0: Pin VREF is connected. : It may be "0" or "1." f2: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Setting of the port P7 direction register b7 b0 Port P7 direction register (address 11 16) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Set bits corresponding to selected analog input pins to "0." When an external trigger is selected, set bit 7 to "0." Setting of the A-D conversion start flag to "1" b7 b0 1 A-D control register 0 (address 1E 16) A-D conversion start flag When external trigger is selected Falling edges input to pin When internal trigger is selected AD TRG Note: Writing to each bit (except bit 6) of the A-D control register 0 and each bit of the A-D control register 1 must be performed while A-D converter stops operating, in other words, before a trigger is generated. When the V REF connection selection bit is cleared from "1" to "0," wait for an period of 1 s or more passed, and then generate a trigger. Trigger is generated. A-D conversion is started. Fig. 9.8.1 Initial setting example for registers related to repeat sweep mode 9-28 7733 Group User's Manual A-D CONVERTER 9.8 Repeat sweep mode 9.8.2 Operation in repeat sweep mode Figure 9.8.2 shows the conversion operation in the repeat sweep mode. (1) When internal trigger is selected When the A-D conversion start flag is set to "1," the A-D converter starts A-D conversion for an input voltage of pin AN 0. The A-D conversion for pin AN0 is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register 0. *49 cycles of AD have passed when resolution = 8 bits *59 cycles of AD have passed when resolution = 10 bits A-D conversion is performed for all analog input pins selected. Each time A-D conversion is completed for a pin, the conversion result is transferred to the A-D register i which corresponds to the pin. A-D conversion is repeatedly performed for all analog input pins selected. The A-D converter continues operating until the A-D conversion start flag is cleared to "0" by software. (2) When external trigger is selected ______ If pin ADTRG's level goes from "H" to "L" when the A-D conversion start flag = "1," the A-D converter starts A-D conversion for the input voltage of pin AN 0. The A-D conversion for pin AN0 is completed when one of the following conditions is satisfied, and then the contents of the successive approximation register (in other words, the conversion result) is transferred to the A-D register 0. *49 cycles of AD have passed when resolution = 8 bits *59 cycles of AD have passed when resolution = 10 bits A-D conversion is performed for all analog input pins selected. Each time A-D conversion is completed for a pin, the conversion result is transferred to the A-D register i which corresponds to the pin. A-D conversion is repeatedly performed for all analog input pins selected. The A-D converter continues operating until the A-D conversion start flag is cleared to "0" by software. ______ Note that when pin AD TRG's level goes from "H" to "L" during A-D conversion, the A-D converter quits the conversion which is performed at that time and restarts it from . 7733 Group User's Manual 9-29 A-D CONVERTER 9.8 Repeat sweep mode Trigger is generated. Conversion result Input voltage of pin AN 0 is converted. A-D register 0 Conversion result A-D register 1 Input voltage of pin AN 1 is converted. Conversion result Input voltage of pin AN i is converted. Fig. 9.8.2 Conversion operation in repeat sweep mode 9-30 7733 Group User's Manual A-D register i A-D CONVERTER 9.9 Precautions for A-D converter 9.9 Precautions for A-D converter 1. Writing to each bit (except bit 6) of the A-D control register 0 and each bit of the A-D control register 1 must be performed while the A-D converter stops operating, in other words, before a trigger is generated. When the V REF connection selection bit is cleared from "1" to "0," in other words, when pin V REF is disconnected from the resistor ladder network, wait for an period of 1 s or more, and then generate a trigger. 2. When an external trigger is selected, pin AN5 cannot be used as an analog input pin because this pin is disconnected from the comparator. If pin AN 5 is selected as an analog input pin when an external trigger is selected, the A-D converter operates, but an undefined value is stored into the A-D register 5. 3. When using the A-D converter, refer to section "Appendix 8. Countermeasures against noise," also. 7733 Group User's Manual 9-31 A-D CONVERTER 9.9 Precautions for A-D converter MEMO 9-32 7733 Group User's Manual CHAPTER 10 WATCHDOG TIMER 10.1 Block description 10.2 Operation description 10.3 Precautions for watchdog timer WATCHDOG TIMER 10.1 Block description The watchdog timer is described below and functions as follows: * Detects a program runaway. * Measures a certain time from when oscillation starts at termination of the stop mode. (Refer to chapter "11. STOP AND WAIT MODES.") 10.1 Block description Figure 10.1.1 shows the block diagram of the watchdog timer. f8 (Note 1) f32 f512 Watchdog timer frequency selection flag (Note 3) Watchdog timer Hold request Writing to the watchdog timer register (address 6016) RESET STP instruction Watchdog timer interrupt request Value FFF16 is set. 2Vcc detection circuit S Q R (Note 2) Clocks f8, f32, f512 : Refer to chapter "14. CLOCK GENERATING CIRCUIT." Notes 1: Only when the system clock selection bit (bit 3 at address 6C16) = "1" and the stop mode is terminated by an interrupt request generated, the watchdog timer is connected to clock f 8. 2: Clock f16 is input when one of the following conditions is satisfied; * The port-Xc selection bit = "0" and the main clock external input selection bit = "1" * The system clock selection bit = "0" and the main clock external input selection bit = "1" * The port-Xc selection bit = "1," the system clock selection bit = "1" and the sub clock external input selection bit = "1" 3: When the STP instruction is executed, the watchdog timer is connected as follows; *Connected to clock f32 when the system clock selection bit = "0" *Connected to clock f8 when the system clock selection bit = "1" Fig. 10.1.1 Block diagram of watchdog timer 10-2 7733 Group User's Manual WATCHDOG TIMER 10.1 Block description 10.1.1 Watchdog timer The watchdog timer is a 12-bit counter that down-counts a count source which is selected by the watchdog timer frequency selection flag (bit 0 at address 61 16). Value "FFF16 " is automatically set in the watchdog timer in the following cases. Note that an arbitrary value cannot be set in the watchdog timer. When dummy data is written to the watchdog timer register (Refer to Figure 10.1.2.) When the most significant bit of the watchdog timer becomes "0" When the STP instruction is executed (Refer to chapter "11. STOP AND WAIT MODES.") At reset b7 b0 Watchdog timer register (address 6016) Functions Bit 7 to 0 Watchdog timer is initialized. By writing dummy data to this register, watchdog timer's value is initialized to "FFF 16" (Dummy data: 0016 to FF16). At reset RW Undefined WO Fig. 10.1.2 Structure of watchdog timer register 7733 Group User's Manual 10-3 WATCHDOG TIMER 10.1 Block description 10.1.2 Watchdog timer frequency selection flag This is used to select a watchdog timer's count source. Figure 10.1.3 shows the structure of the watchdog timer frequency selection flag. b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency selection flag (address 6116) Bit 0 7 to 1 Bit name Watchdog timer frequency selection flag Functions 0 : Clock f512 1 :Clock f32 Not implemented. Clocks f32, f512 : Refer to chapter "14. CLOCK GENERATING CIRCUIT." Fig. 10.1.3 Structure of watchdog timer frequency selection flag 10-4 7733 Group User's Manual At reset RW 0 RW Undefined -- WATCHDOG TIMER 10.2 Operation description 10.2 Operation description The watchdog timer's operation is described below. For its operation in the stop and wait modes, refer to chapter "11. STOP AND WAIT MODES." 10.2.1 Basic operation The watchdog timer starts counting down from "FFF 16." When the watchdog timer's most significant bit becomes "0," in other words, when the countdown has been performed 2048 times, a watchdog timer interrupt request occurs. (Refer to Table 10.2.1.) When the interrupt request occurs (), value "FFF 16" is set to the watchdog timer. The watchdog timer interrupt is a non-maskable interrupt. When a watchdog timer interrupt request is accepted, the processor interrupt priority level (IPL) is set to "1112." Table 10.2.1 Occurrence interval of watchdog timer interrupt request Occurrence interval of watchdog timer interrupt request Watchdog timer's When system clock = When system clock = When system clock = count source 25 MHz (Note 1) 32 kHz (Note 2) 12 MHz (Note 1) f512 f32 41.9 ms 2.62 ms 87.4 ms 5.46 ms 32768 ms 2048 ms Clocks f 32, f 512, and system clock: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Notes 1: This is applied when the system clock selection bit (bit 3 at address 6C 16; Refer to Figure 10.2.1.) = "0" and the main clock division selection bit (bit 0 at address 6F 16; Refer to Figure 10.2.2.) = "0." 2: This is applied when the port-Xc selection bit (bit 4 at address 6C 16 ; Refer to Figure 10.2.1.) = "1" and the system clock selection bit = "1." Make sure that dummy data must be written to address 6016 (Watchdog timer register) by software before the most significant bit of the watchdog timer becomes "0." If writing to address 60 16 is not performed because of a program runaway and the most significant bit of the watchdog timer becomes "0," a watchdog timer interrupt request occurs. This means that a program runaway has occurred. When resetting the microcomputer after detecting a program runaway, write "1" to the software reset bit (bit 3 at address 5E16) in the watchdog timer interrupt routine. (Make sure that writing "1" to the software reset bit must be performed on the condition that the main clock is stably supplied.) (For details, refer to chapter "13. RESET" and section "17.3 Watchdog timer.") 7733 Group User's Manual 10-5 WATCHDOG TIMER 10.2 Operation description 10.2.2 Operation in stop mode In the stop mode, the watchdog timer stops operating. Immediately after the stop mode is terminated, the watchdog timer operates as follows. (1) When stop mode is terminated by a hardware reset Supply of internal clock starts immediately after the stop mode is terminated, and the microcomputer performs the "operation after reset." (Refer to chapter "13. RESET.") The watchdog timer frequency selection flag becomes "0," and the watchdog timer starts counting of the main clock 1 divided by 512 from "FFF16 ." Main clock 1: Refer to chapter "14. CLOCK GENERATING CIRCUIT." (2) When stop mode is terminated by an interrupt request generated According to bit state listed in Table 10.2.2, the watchdog timer operates as "a" or "b" described below. a. Supply of internal clock starts immediately after the stop mode is terminated, and the routine of the interrupt which is used to terminate the stop mode is executed. From "FFF 16," the watchdog timer restarts counting of a count source which was counted just before the STP instruction is executed (Note 1). b. Immediately after the stop mode is terminated, the watchdog timer starts counting of a count source (Note 2) from "FFF16." Supply of internal clock starts when the watchdog timer's most significant bit becomes "0." (At this time, a watchdog timer interrupt request is not generated.) When supply of internal clock starts, the microcomputer executes the routine of the interrupt which is used to terminate the stop mode. From "FFF16," the watchdog timer restarts counting of a count source which was counted just before the STP instruction is executed (Note 1). Notes 1: Clock f 32 or f 512 is counted. 2: When the system clock selection bit = "0," clock f 32 is counted. When the system clock selection bit = "1" and the port-Xc selection bit = "0," clock f 8 is counted. 10-6 7733 Group User's Manual WATCHDOG TIMER 10.2 Operation description Table 10.2.2 Watchdog timer's operation and bit state related to oscillation circuit control Bit state related to oscillation circuit control Port-Xc selection bit System clock Main clock external Sub clock external W a t c h d o g selection bit timer's operation input selection bit input selection bit (Bit 4 at address 6C16) (Bit 3 at address 6C16) (Bit 1 at address 6F16) (Bit 2 at address 6F16) 0 b 1 0 a 1 1 0 b 0 1 0 a 1 1 0 b 0 1 0 a 1 1 b 0 0 a 1 b 0 1 a 1 to Figures 10.2.1 and 10.2.2. For the procedure of writing to the main bit and the sub clock external input selection bit, refer to Figure 10.2.3. 0 0 0 1 0 1 1 Note: For each bit's function, refer clock external input selection 10.2.3 Operation in wait mode When the system clock stop bit at wait state (bit 5 at address 6C16 ; Refer to Figure 10.2.1.) = "1," the watchdog timer stops operating in the wait mode. Furthermore, after the wait mode is terminated, the watchdog timer restarts counting from the same state as that before the watchdog timer stops. When the system clock stop bit at wait state = "0," the watchdog timer does not stop. 7733 Group User's Manual 10-7 WATCHDOG TIMER 10.2 Operation description 10.2.4 Operation in hold state The watchdog timer stops operating in the hold state. (Refer to section "12.4 Hold function.") When the hold state is terminated, the watchdog timer restarts counting from the same state as that before the watchdog timer stops. b7 b6 b5 b4 b3 b2 b1 b0 Oscillation circuit control register 0 (address 6C16) Bit Bit name Functions 0: Drivability "LOW" 1: Drivability "HIGH" At reset RW 1 RW (Note 1) Undefined _ 0 XCOUT drivability selection bit 1 Not implemented. 2 Main clock stop bit 0: Main clock oscillation or external clock input is available. 1: Main clock oscillation or external clock input is stopped. 0 RW (Note 1) 3 System clock selection bit When the port-Xc selection bit = "0," 0: Main clock 1: Main clock divided by 8 When the port-Xc selection bit = "1," 0: Main clock 1: Sub clock 0 RW (Note 2) 4 Port-Xc selection bit 0: Operate as I/O ports (P77, P76). 1: Operate as pins XCIN and XCOUT. 0 5 System clock stop bit at wait state 0: Operates in the wait mode. 1: Stopped in the wait mode. 0 RW 6 Signal output disable selection bit 0: Output is enabled. 1: Output is disabled. 0 RW 7 Not implemented. Undefined _ (Refer to Tables 12.1.2 and 12.1.5) RW (Notes 2 and 3) Notes 1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc selection bit = "1." 2: When selecting the sub clock as the system clock, set bit 3 to "1" after setting bit 4 to "1." If the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to "1." 3: Although this bit can be set to "1," it cannot be cleared to "0" after this bit is once set to "1." 4: represents that bits 0 to 2 and bit 7 are not used for the watchdog timer. Fig. 10.2.1 Structure of oscillation circuit control register 0 10-8 7733 Group User's Manual WATCHDOG TIMER 10.2 Operation description b7 b6 b5 AA AA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA b4 0 b3 b2 b1 b0 Oscillation circuit control register 1 (address 6F16) Bit Bit name Functions 0 Main clock division selection bit 0: Main clock is divided by 2. (Note 1) 1: Main clock is not divided by 2. 1 Main clock external input selection bit 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating (Note 1) stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. 2 Sub clock external input selection bit 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT. (Note 1) Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. At reset RW 0 RW 0 RW 0 RW AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA Ignored in the mask ROM and external ROM versions. 0 Must be fixed to "1" in the one time PROM and EPROM versions (Notes 1 and 2). 1 4 Must be fixed to "0" (Note 2). 0 RW 5 Not implemented. Undefined -- 6 Not implemented. Undefined -- 7 Clock prescaler reset bit 0 WO 3 RW (Note 3) By writing "1" to this bit, clock prescaler is initialized. Notes 1: When writing to this register, follow the procedure shown in Figure 10.2.3. 2: The case where data "010101012" is written with the procedure shown in Figure 10.2.3 is not included. 3: In the 7735 Group, fix this bit to "0." 4: represents that bits 3 to 7 are not used for the watchdog timer. Fig. 10.2.2 Structure of oscillation circuit control register 1 * When writing to bits 0 to 3 Write data "010101012." (LDM instruction) Next instruction Write data "00001XXX2." (LDM instruction) (b3 in Figure 10.2.2) (b2 to b0 in Figure 10.2.2) Fig. 10.2.3 Procedure for writing data to oscillation circuit control register 1 7733 Group User's Manual 10-9 WATCHDOG TIMER 10.3 Precautions for watchdog timer 10.3 Precautions for watchdog timer 1. If dummy data is written to address 6016 when the data length flag (m) is "0," writing to address 6116 is simultaneously performed. Accordingly, when a change of the watchdog timer frequency selection flag's value (bit 0 at address 61 16 ) is not required, write the same value that is set. 2. In order to stop the watchdog timer in the hold state, the count source which is actually counted by the _____ watchdog timer is the logical product of two signals. One is the inverted signal input from pin HOLD, and the other is a count source which is selected by the watchdog timer frequency selection flag (clock f 32 or f 512). (Refer to Figure 10.1.1.) Accordingly, there is a possibility that counting is performed when pin _____ HOLD's input signal level changes during a duration which is shorter than 1 cycle of the selected count source (clock f 32 or f 512). Clock f32 or f512 HOLD pin input signal Count source actually counted by watchdog timer Pin HOLD's input signal level changes during a duration which is shorter than 1 cycle of clock f32 or f512. Fig. 10.3.1 Watchdog timer's count source 3. When the main clock is not stably supplied, do not use the software reset (that is, writing "1" to the software reset bit) as a means to reset the microcomputer at a program runaway. 4. When the STP instruction (Refer to chapter "11. STOP AND WAIT MODES") is executed, the watchdog timer stops operating. For the system where the watchdog timer is used to detect a program runaway, select "STP instruction disabled" with "STP instruction option" on "MASK ROM ORDER CONFIRMATION FORM." 10-10 7733 Group User's Manual CHAPTER 11 STOP AND WAIT MODES 11.1 11.2 11.3 11.4 Overview Clock generating circuit Stop mode Wait mode STOP AND WAIT MODES 11.1 Overview The stop and wait modes are described below. When there is no need for operation of the central processing unit (CPU), the stop and wait modes are used to stop oscillation or internal clock . The microcomputer enters the stop mode when the STP instruction is executed; the microcomputer enters the wait mode when the WIT instruction is executed. 11.1 Overview Table 11.1.1 lists the differences between the stop and wait modes. The stop state of oscillation or internal clock can be terminated by an interrupt request occurrence or hardware reset. Table 11.1.1 Differences between stop and wait modes State/Operation Item State in each mode Oscillation Internal clock Clock timer*1 Clocks f2 to f 512, clock 1*2 Operation When terminated by after each interrupt request mode is occurrence terminated Stop mode Wait mode Stopped Operating (Note 1) Stopped Operating Stopped Operating Supply of internal clock starts after measuring a certain time by watchdog timer. Current consumption Internal peripheral devices Interval from termination of each mode until execution of instruction Supply of internal clock starts immediately after termination of the wait mode. Operation after hardware reset When terminated by hardware reset Features Supply of internal clock starts after f 2 x 7 cycles. Less than that when clocks f 2 to f 512 operate Functions using the external clock are enabled. Functions using clocks f2 to f512 are disabled. Less than that in the wait mode Long Condition Less than that when CPU operates Operating enabled Short From the external, a clock must stably be input to a clock input pin (Note 2). Clock timer *1 : Refer to section "7.6 Clock timer." Clocks f 2 to f 512, clock 1*2 : Refer to Figure 11.2.1. Note 1: When the main clock external input selection bit = "1," the main-clock oscillation circuit stops operating; when the sub clock external input selection bit = "1," the sub-clock oscillation circuit stops operating. (Note that, in this case, an external clock can be input.) 2: When the main clock is the system clock, pin X IN is used; when the sub clock is the system clock, pin XCIN is used. 11-2 7733 Group User's Manual STOP AND WAIT MODES 11.2 Clock generating circuit 11.2 Clock generating circuit Figure 11.2.1 shows the block diagram of the clock generating circuit (with the STP and WIT instructions). Figures 11.2.2 and 11.2.3 show the structures of the oscillation circuit control register 0 and oscillation circuit control register 1, respectively. Figure 11.2.4 shows the procedure for writing data to the oscillation circuit control register 1. P76/AN6/XCOUT P77/AN7/XCIN P67/TB2IN/ 1 SUB 1 CM4 PC 1 CM4 (Port latch) 0 CM4 (Oscillation circuit control register 0: address 6C 16) CM2: Main clock stop bit CM3: System clock selection bit CM4: Port-Xc selection bit CM5: System clock stop bit at wait state (Oscillation circuit control register 1: address 6F 16) CC0: Main clock division selection bit CC1: Main clock external input selection bit CC2: Sub clock external input selection bit (Port function control register: address 6D 16) PC1: Sub-clock output selection bit/Timer B2 clock source selection bit 0 PC1 CM4 CC2 1 0 1 CM3 Timer B2 (Clock timer) (Event counter mode) 1/32 1 1 0 Sub clock f2 1 XOUT 1/8 1/2 1/4 1/2 f32 1/2 1/8 f512 0 0 0 Main clock f64 System clock CM4 1 0 f16 1/2 0 0 f8 1 1 XIN 1 fC32 (Clock prescaler) Internal clock CC0 CM3 CM3 CM4 CC1 CM 12-bit watchdog timer WDC CM2 CM3 Watchdog timer frequency selection flag 5 1 Q S S R STP instruction WIT instruction R Q Q S R Reset STP instruction 0 CC 1 CM3 CM4 CMi: Bit i at address 6C 16 (Refer to Figure 11.2.2.) CCi: Bit i at address 6F 16 (Refer to Figure 11.2.3.) Switch represented by is controlled by a signal represented by " Interrupt disable flag Interrupt request CC2 ". Fig. 11.2.1 Block diagram of clock generating circuit (with STP and WIT instructions) 7733 Group User's Manual 11-3 STOP AND WAIT MODES 11.2 Clock generating circuit b7 b6 b5 b4 b3 b2 b1 b0 Oscillation circuit control register 0 (address 6C 16) Bit Bit name 0 XCOUT drivability selection bit 1 Not implemented. 2 Main clock stop bit Functions 0: Drivability "LOW" 1: Drivability "HIGH" 0: Main clock oscillation or external clock input is available. At reset RW 1 RW (Note 1) Undefined _ 0 RW (Note 1) RW (Note 2) 1: Main clock oscillation or external clock input is stopped. 3 System clock selection bit When the port-Xc selection bit = "0," 0: Main clock 1: Main clock divided by 8 When the port-Xc selection bit = "1," 0: Main clock 1: Sub clock 0 4 Port-Xc selection bit 0: Operate as I/O ports (P7 7, P76 ). 1: Operate as pins X CIN and XCOUT . 0 5 System clock stop bit at wait state (Note 4) 0: Operates in the wait mode. 1: Stopped in the wait mode. 0 RW 6 Signal output disable selection bit 0: Output is enabled. 1: Output is disabled. 0 RW 7 Not implemented. Undefined _ (Refer to Tables 12.1.2 and 12.1.5) RW (Notes 2 and 3) Notes 1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc selection bit = "1." 2: When selecting the sub clock as the system clock, set bit 3 to "1" after setting bit 4 to "1." If the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to "1." 3: Although this bit can be set to "1," it cannot be cleared to "0" after this bit is once set to "1." 4: When setting the system clock stop bit at wait state to "1," perform it immediately before the WIT instruction is executed. Furthermore, clear this bit to "0" immediately after the wait mode is terminated. Fig. 11.2.2 Structure of oscillation circuit control register 0 11-4 7733 Group User's Manual STOP AND WAIT MODES 11.2 Clock generating circuit b7 b6 b5 b4 0 b3 b2 b1 b0 Oscillation circuit control register 1 (address 6F 16) Bit Bit name Functions At reset RW 0 Main clock division selection bit 0: Main clock is divided by 2. (Note 1) 1: Main clock is not divided by 2. 0 RW 1 Main clock external input selection bit 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when (Note 1) terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. 0 RW 2 Sub clock external input selection bit 0: Sub-clock oscillation circuit is operating by itself. Pin P7 6 functions as pin X COUT . (Note 1) 0 RW Ignored in the mask ROM and external ROM versions. 0 RW Must be fixed to "1" in the one time PROM and EPROM versions (Notes 1 and 2). 1 4 Must be fixed to "0" (Note 2) 0 RW 5 Not implemented. Undefined -- 6 Not implemented. Undefined -- 7 Clock prescaler reset bit 0 WO Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P7 6 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. 3 (Note 3) By writing "1" to this bit, clock prescaler is initialized. Notes 1: When writing to this register, follow the procedure shown in Figure 11.2.4. 2: The case where data "01010101 2" is written with the procedure shown in Figure 11.2.4 is not included. 3: In the 7735 Group, fix this bit to "0." 4: represents that bits 3 to 7 are not used for the stop and wait modes. Fig. 11.2.3 Structure of oscillation circuit control register 1 * When writing to bits 0 to 3 Write data "01010101 2." (LDM instruction) Next instruction Write data "00001XXX 2." (LDM instruction) (b3 in Figure 11.2.3) (b2 to b0 in Figure 11.2.3) Fig. 11.2.4 Procedure for writing data to oscillation circuit control register 1 7733 Group User's Manual 11-5 STOP AND WAIT MODES 11.3 Stop mode 11.3 Stop mode When the STP instruction is executed, the main-clock and sub-clock oscillation circuits stop operating. This state is called "stop mode." In the stop mode, even when oscillation stops, the contents of the internal RAM can be retained if there is 2 V of Vcc (power source voltage) or more. Furthermore, because the CPU and all internal peripheral devices which use clocks f2 to f512*1 stop operating, power consumption is lowered. Refer to section "17.4 Power saving" for lowering the power consumption. Table 11.3.1 lists the microcomputer's state/operation in the stop mode and after the stop mode is terminated. Table 11.3.2 lists the pin state in the stop mode. Table 11.3.1 Microcomputer's state/operation in stop mode and after stop mode is terminated State/Operation Item Watchdog timer is used Watchdog timer is not used when terminating the stop mode when terminating the stop mode Internal peripheral devices Oscillation State in Internal clock stop mode Clocks f2 to f512*1, clock 1*2 Clock f(X IN)/32 Operation after stop mode is terminated timer *3 Stopped Stopped f(XCIN)/32 Timer A, Timer B Serial I/O A-D converter Watchdog timer Pins When terminated by interrupt request occurrence When terminated by hardware reset Operating enabled only in the event counter mode Operating enabled only when the external clock is selected Stopped Stopped Refer to Table 11.3.2 Supply of internal clock starts after measuring a certain time by watchdog timer. Supply of internal clock starts after f2 x 7 cycles. Operation after hardware reset From the external, a clock must stably be input to a clock input pin*4. Condition Clocks f 2 to f 512*1, clock 1 *2 : Refer to Figure 11.2.1. Clock timer *3 : Refer to section "7.6 Clock timer." Clock input pin*4 : When the system clock is the main clock, pin XIN is used; when the system clock is the sub clock, pin X CIN is used. In order to select whether to use the watchdog timer or not when terminating the stop mode, specify the main clock external input selection bit (bit 1 at address 6F16; when the main clock is used) or the sub clock external input selection bit (bit 2 at address 6F16; when the sub clock is used). (Refer to Figure 11.2.3, sections "11.3.2 Stop mode terminating operation by interrupt request occurrence (when using watchdog timer)" and "11.3.3 Stop mode terminating operation by interrupt request occurrence (when not using watchdog timer)." 11-6 7733 Group User's Manual STOP AND WAIT MODES 11.3 Stop mode Table 11.3.2 Pin state in stop mode Pins __ Single-chip mode When the signal output disable selection bit = "0," "H" level is output E State Memory expansion Microprocessor mode mode When the standby state When the standby state selection bit1 = "0" selection bit1 = "1" Same as in the micro- "H" level is output. When the signal output processor mode disable selection bit = "0," "H" level is output. When the signal output disable selection bit = "1," "L" level is output. When the signal output disable selection bit = "1," "L" level is output. __ R/W, ____ BHE, _____ HLDA ALE A0 -A7, A8 /D8-A 15/D15, A16/D0-A 23/D7 P42/1 When the clock 1 output selection bit *2 = "1" 1: "L" level is output. When the clock 1 output selection bit = "0" P42: Retains the same state in which the STP instruction is executed. Ports P0 to P8 (not including P42) : Retains the same state in which the STP instruction is executed. Output levels can be set. (Refer to section "11.3.1 Output levels "L" level is output. of external bus and Retains the same bus control signals state in which the in stop mode.") STP instruction is executed. When the signal output disable selection bit *3 = "0" 1: "L" level is output. When the signal output disable selection bit = "1" P4 2 : Bit 2's value of the port P4 register is output (Note). P4 3 to P4 7, P5 to P8 :Retains the same state in which the STP instruction is executed. Standby state selection bit*1: Bit 0 at address 6D16 (Refer to Figure 11.3.1.) Clock 1 output selection bit *2: Bit 7 at address 5E 16 (Refer to section "12.1 Signals required for accessing external devices.") Signal output disable selection bit *3: Bit 6 at address 6C 16 (Refer to section "12.1 Signals required for accessing external devices.") Note: Make sure to set bit 2 of the port P4 direction register to "1." 11.3.1 Output levels of external bus and bus control signals in stop mode In the memory expansion or microprocessor mode, the output levels of the external bus and bus control signals in the stop mode can be set by software. By setting the standby state selection bit (bit 0 at address 6D16) to "1," these output levels become levels set by software. Figure 11.3.1 shows an output level setting example in the stop mode. In the single-chip mode, do not set the standby state selection bit to "1." 7733 Group User's Manual 11-7 STOP AND WAIT MODES 11.3 Stop mode Setting of the output levels for the external bus and bus control signals (not including E) b7 b0 1 1 1 1 1 1 1 1 Port P0 direction register (address 4 16) Port P1 direction register (address 5 16) Port P2 direction register (address 8 16) Port P3 direction register (address 9 16) Must be fixed to "FF 16." b7 b0 Port P0 register (address 2 16) Port P1 register (address 3 16) Port P2 register (address 6 16) Port P3 register (address 7 16) Set output level by the bit which corresponds to each pin. 0: "L" level output 1: "H" level output * When setting the signal output disable selection bit to "1" in the microprocessor mode * When setting the clock 1 output selection bit to "0" in the memory expansion mode b7 b0 1 Port P4 direction register (address C 16) * When setting the signal output disable selection bit to "0" in the microprocessor mode 1 output selection bit to * When setting the clock "1" in the memory expansion mode (Note 1) b7 b0 Port P4 register (address A 16) 0: "L" level output 1: "H" level output Note 1: This is applied only in the microprocessor mode. In the memory expansion mode, it may be "0" or "1" because the I/O port function is selected. Setting of the standby state selection bit to "1" b7 b0 0 1 Port function control register (address 6D 16) Standby state selection bit ( Note 2) Note 2: This bit's value also affects the pin state in the wait mode. (Refer to Figure 11.4.1.) Setting of E signal's output level (Setting of pin P4 2/ b7 1's state) b0 Oscillation circuit control register 0 (address 6C 16) Signal output disable selection bit ( Note 3) 0: In the stop mode, pin E outputs "H" level, and pin P4 2/ "L" level. 1: In the stop mode, pin E outputs "L" level, and pin P4 2/ bit 2's value of port P4 register. 1 outputs STP instruction is executed. 1 outputs Note 3: This bit's value also affects the following: * Output state of bus control signals and others after the stop mode is terminated (Refer to chapter "12. CONNECTING EXTERNAL DEVICES" ) * Pin state in the wait mode. (Refer to Figure 11.4.1.) Furthermore, description of pin P4 2/ 1 is applied only in the microprocessor mode. Fig. 11.3.1 Output level setting example in stop mode (Memory expansion or Microprocessor mode) 11-8 7733 Group User's Manual STOP AND WAIT MODES 11.3 Stop mode 11.3.2 Stop mode terminating operation by interrupt request occurrence (when using watchdog timer) When there is little possibility that a clock is stably supplied from an oscillation circuit (Note 1) in returning from the stop mode, instruction execution can be started after a certain time (Note 2) measured by the watchdog timer. Notes 1: A clock is supplied in one of the following ways: An oscillation circuit operates by itself. An external clock is input. 2: "a certain time" means an interval from occurrence of an interrupt request until stabilization of clock supply. When an interrupt request occurs, an oscillator starts oscillating. Simultaneously, supply of clocks f2 to f 512 starts. By start of oscillation, the watchdog timer starts counting. The watchdog timer counts f32 when the system clock selection bit (bit 3 at address 6C 16; Refer to Figure 11.2.2.) = "0" or f 8 when the system clock selection bit = "1." When the watchdog timer's MSB becomes "0," supply of internal clock starts. At the same time, the watchdog timer's count source returns to a count source (clock f 32 or f512) which is selected by the watchdog timer frequency selection flag (bit 0 at address 6116 ). The interrupt request which occurs in is accepted. Table 11.3.3 lists interrupts which can be used for termination of the stop mode. Table 11.3.3 Interrupts which can be used for termination of stop mode Interrupt Key input interrupt INT i interrupt (i = 0 to 2) Timer Ai interrupt (i = 0 to 4) Timer Bi interrupt (i = 0 to 2) UARTi transmission interrupt (i = 0, 1) UARTi reception interrupt (i = 0, 1) UART2 transmission/reception interrupt ____ Conditions for each function which generates interrupt request When the key input interrupt function is selected INT2 interrupt: When the key input interrupt function is invalid. ____ In the event counter mode When the external clock is selected Note 1: Because an oscillator has stopped oscillating, each function is available only in the conditions listed in Table 11.3.3. Note that the A-D converter and clock timer (Refer to section "7.6 Clock timer") do not operate, also. 2: Because an oscillator has stopped oscillating, interrupts not listed in Table 11.3.3 cannot be used. 3: For each interrupt, refer to chapters "4. INTERRUPTS," "5. KEY INPUT INTERRUPT FUNCTION," "6. TIMER A," "7. TIMER B," and "8. SERIAL I/O." 7733 Group User's Manual 11-9 STOP AND WAIT MODES 11.3 Stop mode When using the watchdog timer in termination of the stop mode, make sure to set as follows before executing the STP instruction. Enable an interrupt which is used for termination. Also, make sure that the interrupt priority level of an interrupt which is used for termination is higher than the processor interrupt priority level (IPL) of a routine where the STP instruction is executed. Furthermore, when multiple interrupts in Table 11.3.3 are enabled, the stop mode is terminated by the interrupt request which occurs first. After oscillation starts (), there is a possibility that an interrupt request occurs until the supply of internal clock starts (). Interrupt requests which occur during this period are accepted in order of priority after the watchdog timer's MSB becomes "0." For interrupts which have no need to be accepted, set their interrupt priority levels to "0" (Interrupt disabled) before executing the STP instruction. When the system clock is the main clock or the main clock divided by 8, set the main clock external input selection bit (bit 1 at address 6F16 ; Refer to Figure 11.2.3.) to "0." When the system clock is the sub clock, set the sub clock external input selection bit (bit 2 at address 6F16 ) to "0." 11.3.3 Stop mode terminating operation by interrupt request occurrence (when not using watchdog timer) When a clock is stably input from the external to a clock input pin (Refer to Figures 14.2.2 and 14.2.4.), instruction execution can be started immediately after the termination of the stop mode. When an interrupt request occurs, clock input from pin X IN starts. Simultaneously, supply of clocks f2 to f 512 starts. Supply of internal clock starts after 7 cycles of f 2. The interrupt request which occurs in is accepted. Table 11.3.3 lists interrupts which can be used for termination. When not using the watchdog timer in termination of the stop mode, make sure to set as follows before executing the STP instruction. Enable an interrupt which is used for termination. Also, make sure that the interrupt priority level of an interrupt which is used for termination is higher than the processor interrupt priority level (IPL) of a routine where the STP instruction is executed. Furthermore, when multiple interrupts in Table 11.3.3 are enabled, the stop mode is terminated by the interrupt request which occurs first. When the system clock is the main clock or the main clock divided by 8, set the main clock external input selection bit (bit 1 at address 6F16; Refer to Figure 11.2.3.) to "1." When the system clock is the sub clock, set the sub clock external input selection bit (bit 2 at address 6F16) to "1." 11-10 7733 Group User's Manual STOP AND WAIT MODES 11.3 Stop mode When using watchdog timer Stop mode System clock : f(XIN) or f(XCIN) ....... (Note 1) Internal clock Interrupt request which is used for termination (Interrupt request bit) "1" "0" 32/f(X IN) 2048 counts or 8/f(X CIN) 2048 counts "FFF 16" Value of watchdog timer "7FF 16" CPU Operating Stopped Stopped Operating Internal peripheral devices Operating Stopped Operating Operating STP instruction Interrupt request which is Watchdog timer's MSB = "0" is executed (However, watchdog timer interrupt used for termination occurs. request does not occur.) Oscillation starts. Supply of CPU (internal clock ) (When an external clock is Note 1: Sub clock (f(XCIN)) is stopped at starts. input from pin XIN, clock input "L" level in the stop mode. starts.) Interrupt request which was used for Watchdog timer starts counting. termination is accepted. When not using watchdog timer Stop mode System clock : f(XIN) or f(XCIN) ....... (Note 2) Internal clock Interrupt request which is used for termination "1" (Interrupt request bit) "0" 2/f(X IN) 7 counts "FFF16 " Value of watchdog timer "7FF16 " CPU Operating Stopped Stopped Operating Internal peripheral devices Operating Stopped Operating Operating STP instruction is executed Interrupt request which is used for termination occurs. Clock input from pin XIN or Note 2: In the stop mode, clock input can be stopped. XCIN starts. In order to stop clock input, be sure to generate an interrupt request after a clock is stably supplied when returning from the stop mode. Watchdog timer starts counting. Supply of CPU (internal clock ) starts. Interrupt request which was used for termination is accepted. Fig. 11.3.2 Stop mode terminating sequence by interrupt request occurrence 7733 Group User's Manual 11-11 STOP AND WAIT MODES 11.3 Stop mode 11.3.4 Stop mode terminating operation by hardware reset ______ When terminating the stop mode by hardware reset, input "L" level to pin RESET from the external circuit until oscillation of an oscillator which is connected to the main-clock oscillation circuit is stabilized. The CPU and SFR area are initialized in the same way as at system reset. However, the internal RAM area retains the same contents as that before the STP instruction was executed. The terminating sequence is the same as the internal processing sequence after reset. When determining whether hardware reset was applied for termination of the stop mode or system reset was applied, use software after reset. For reset, refer to chapter "13. RESET." 11.3.5 Precautions for stop mode 1. In the mask ROM version, select "STP instruction enabled" with "STP instruction option" on "MASK ROM ORDER CONFIRMATION FORM." (In the built-in PROM and external ROM versions, STP instruction is always enabled.) 2. "Stop mode terminating operation by an interrupt request occurrence (when not using watchdog timer)" can be selected only when an external clock is stably input to a clock input pin for a clock which is selected as the system clock. In one of the following cases, select "Stop mode terminating operation by an interrupt request occurrence (when using watchdog timer)": When an oscillator is connected between input and output pins for a clock which is selected as the system clock When there is a possibility that the above external clock is temporarily unstable in termination of the stop mode 11-12 7733 Group User's Manual STOP AND WAIT MODES 11.4 Wait mode 11.4 Wait mode When the WIT instruction is executed, internal clock stops. (The oscillator does not stop oscillating.) This state is called "wait mode." In the wait mode, power consumption can be lowered with Vcc (power source voltage) retained. Refer to section "17.4 Power saving" for lowering the power consumption. Table 11.4.1 lists the microcomputer's state/operation in the wait mode and after the wait mode is terminated. Table 11.4.2 lists the pin state in the wait mode. Table 11.4.1 Microcomputer's state/operation in wait mode and after wait mode is terminated Item When clocks f2 to f 512 Internal peripheral devices Oscillation State in Internal clock wait mode Clocks f2 to f 512*1, clock 1 *2 f(X IN)/32 Clock *3 f(XCIN)/32 timer Timer A, Timer B Serial I/O A-D converter Watchdog timer Pins Operation When terminated by interafter wait rupt request occurrence mode is When terminated by terminated hardware reset State/Operation are stopped When clocks f 2 to f512 are not stopped Operating Stopped Stopped Operating Stopped Operating Operating Operating enabled only in the event counter mode. Operating enabled only when the external clock is selected. Stopped Stopped Operating Operating Operating Operating Refer to Table 11.4.2. Supply of internal clock starts immediately after termination. Operation after hardware reset Clocks f2 to f5121, clock 12 : Refer to Figure 11.2.1. Clock timer3 : Refer to section "7.6 Clock timer." In order to select the state of clocks f2 to f512 in the wait mode, specify the system clock stop bit at wait state (bit 5 at address 6C16). (Refer to Figure 11.2.2 and section "11.4.1 State of clocks f2 to f512 in wait mode.") 7733 Group User's Manual 11-13 STOP AND WAIT MODES 11.4 Wait mode Table 11.4.2 Pin state in wait mode Pins __ Single-chip mode State Memory expansion Microprocessor mode mode When the standby state When the standby state selection bit1 = "0" selection bit1 = "1" When the signal output Same as in the micro- "H" level is output. When the signal output disable selection bit = processor mode disable selection bit = "0," "H" level is output. "0," "H" level is output. E When the signal output disable selection bit = "1," "L" level is output. When the signal output disable selection bit = "1," "L" level is output. __ Output levels can be set. (Refer to section "11.4.2 Output levels "L" level is output. of external bus and Retains the same bus control signals state in which the in wait mode") WIT instruction is executed. R/W, ____ BHE, _____ HLDA ALE A0-A 7, A8/D8-A15/D15, A16/D0-A23/D7 P42/1 When the clock 1 output selection bit *2 = "1" Ports P0 to P8 (not including P4 2) : Retains the same state in which the WIT instruction is executed. When the signal output disable selection bit *3 = "0" 1: Operating when the system clock stop bit 1: Operating when the at wait state *4 = "0." system clock stop bit at "L" level is output when the system clock wait state = "0." stop bit at wait state = "1." "L" level is output when When the clock 1 output selection bit = "0" the system clock stop bit at wait state = "1." P42: Retains the same state in which the WIT instruction is When the signal output disable selection bit = "1" executed. P4 2: Bit 2's value of port P4 register is output (Note). P4 3 to P4 7, P5 to P8 : Retains the same state in which the WIT instruction is executed. Standby state selection bit *1: Bit 0 at address 6D16 (Refer to Figure 11.4.1.) Clock 1 output selection bit *2 : Bit 7 at address 5E16 (Refer to section "12.1 Signals required for accessing external devices.") Signal output disable selection bit *3: Bit 6 at address 6C 16 (Refer to section "12.1 Signals required for accessing external devices.") System clock stop bit at wait state *4: Bit 5 at address 6C 16 (Refer to section "11.4.1 State of clocks f2 to f 512 in wait mode.") Note: Make sure to set bit 2 of the port P4 direction register to "1." 11-14 7733 Group User's Manual STOP AND WAIT MODES 11.4 Wait mode 11.4.1 State of clocks f 2 to f 512 in wait mode The state of clocks f2 to f512 in the wait mode can be selected by the system clock stop bit at wait state (bit 5 at address 6C16 : Refer to Figure 11.2.2.). When supply of clocks f 2 to f 512 is stopped in the wait mode, power consumption can further be lowered. When supply of clocks f 2 to f 512 is stopped, internal peripheral devices which use clocks f 2 to f 512 stop operating as in the stop mode. Furthermore, when pin P42/ 1 functions as a clock 1 output pin, this pin outputs "L" level. (Refer to Table 11.4.2.) When supply of clocks f 2 to f512 is not stopped, both of the internal peripheral devices' operation and clock 1 output do not stop. Note that, in the microprocessor mode, clock 1 output stops when the signal output disable selection bit = "1." In both cases, internal clock stops, so that the CPU does not operate. Furthermore, because clock fc 32 does not stop operating, the clock timer continues operating. (Refer to Table 11.4.3.) 11.4.2 Output levels of external bus and bus control signals in wait mode In the memory expansion or microprocessor mode, the output levels of the external bus and bus control signals in the wait mode can be set by software. By setting the standby state selection bit (bit 0 at address 6D16) to "1," these output levels become levels set by software. Figure 11.4.1 shows an output level setting example in the wait mode. In the single-chip mode, do not set the standby state selection bit to "1." (Fix this bit to "0.") 7733 Group User's Manual 11-15 STOP AND WAIT MODES 11.4 Wait mode Setting of the output levels for the external bus and bus control signals (not including E) b7 b0 1 1 1 1 1 1 1 1 Port P0 direction register (address 4 16) Port P1 direction register (address 5 16) Port P2 direction register (address 8 16) Port P3 direction register (address 9 16) Must be fixed to "FF 16." b7 b0 Port P0 register (address 2 16) Port P1 register (address 3 16) Port P2 register (address 6 16) Port P3 register (address 7 16) Set output level by the bit which corresponds to each pin. 0: "L" level output 1: "H" level output * When setting the signal output disable selection bit to "1" in the microprocessor mode * When setting the clock 1 output selection bit to "0" in the memory expansion mode b7 b0 1 Port P4 direction register (address C 16) (Note 1) b7 b0 * When setting the signal output disable selection bit to "0" in the microprocessor mode 1 output selection bit to * When setting the clock "1" in the memory expansion mode Port P4 register (address A 16) 0: "L" level output 1: "H" level output Note 1: This is applied only in the microprocessor mode. In the memory expansion mode, it may be "0" or "1" because the I/O port function is selected. Setting of the standby state selection bit to "1" b7 b0 0 1 Port function control register (address 6D 16) Standby state selection bit (Note 2) Note 2: This bit's value also affects the pin state in the stop mode. (Refer to Figure 11.3.1.) Setting of E signal's output level (Setting of pin P4 2/ b7 1's state) b0 Oscillation circuit control register 0 (address 6C 16) Signal output disable selection bit (Note 3) 0: In the wait mode, pin E outputs "H" level. Pin P4 2/ 1 operates when system clock stop bit at wait state = "0" and outputs "L" level when this bit = "1." 1: In the wait mode, pin E outputs "L" level. Pin P4 2/ 1 outputs bit 2's value of port P4 register. WIT instruction is executed. Note 3: This bit's value also affects the following: * Output state of bus control signals and others after the wait mode is terminated (Refer to chapter "12. CONNECTING EXTERNAL DEVICES." ) * Pin state in the stop mode. (Refer to Figure 11.3.1.) Furthermore, description of pin P4 2/ 1 is applied only in the microprocessor mode. Fig. 11.4.1 Output level setting example in wait mode (Memory expansion or Microprocessor mode) 11-16 7733 Group User's Manual STOP AND WAIT MODES 11.4 Wait mode 11.4.3 Wait mode terminating operation by interrupt request occurrence When an interrupt request occurs with supply of clocks f 2 to f 512 stopped, the clock supply restarts. Supply of internal clock starts. The interrupt request which occurs in is accepted. An interrupt which can be used for termination depends on the state of clocks f 2 to f512 in the wait mode. (Refer to Table 11.4.3.) Table 11.4.3 Interrupts which can be used for termination of wait mode Interrupt Conditions for each function which generates interrupt request When clocks f2 to f512 are stopped When clocks f2 to f512 are not stopped Key input interrupt When the key input interrupt function is selected ____ INT i interrupt (i = 0 to 2) INT 2 interrupt: When the key input interrupt function is invalid. Timer Ai interrupt (i = 0 to 4) In the event counter mode Enabled in all modes Timer Bi interrupt (i = 0 to 2) Always enabled UARTi transmission interrupt (i = 0 to 2) Enabled only when the external clock is selected UARTi reception interrupt (i = 0 to 2) Clock timer * Disabled f(XIN)/32 (timer B2) interrupt When timer B2 functions as the clock timer f(XCIN)/32 A-D conversion interrupt Disabled Enabled in one-shot mode and single sweep mode Clock timer : Refer to section "7.6 Clock timer." For each interrupt, refer to chapters "4. INTERRUPTS," "5. KEY INPUT INTERRUPT FUNCTION," "6. TIMER A," "7. TIMER B," "8. SERIAL I/O," and "9. A-D CONVERTER." ____ Before executing the WIT instruction, be sure to enable an interrupt which is used for termination. Also make sure that the interrupt priority level of an interrupt which is used for termination is higher than the processor interrupt priority level (IPL) of a routine where the WIT instruction is executed. Furthermore, when multiple interrupts in Table 11.4.3 are enabled, the wait mode is terminated by the interrupt request which occurs first. 11.4.4 Wait mode terminating operation by hardware reset The CPU and SFR area are initialized in the same way as at system reset. However, the internal RAM area retains the same contents as that before the WIT instruction was executed. The terminating sequence is the same as the internal processing sequence after reset. When determining whether hardware reset was applied for termination of the wait mode or system reset was applied, use software after reset. For reset, refer to chapter "13. RESET." 7733 Group User's Manual 11-17 STOP AND WAIT MODES 11.4 Wait mode MEMO 11-18 7733 Group User's Manual CHAPTER 12 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices 12.2 Software wait 12.3 Ready function 12.4 Hold function CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices 12.1 Signals required for accessing external devices Functions and operations of signals required for accessing external devices are described below. When connecting external devices which require a long access time, refer to sections "12.2 Software wait," "12.3 Ready function," and "12.4 Hold function," also. When connecting external devices, make sure that the microcomputer operates in the memory expansion or microprocessor mode. (Refer to section "2.5 Processor modes.") When the microcomputer operates in __ these modes, ports P0 to P4 and pin E function as I/O pins of signals required for accessing external devices. Figure 12.1.1 shows the pin configuration in the memory expansion or microprocessor mode. Table 12.1.1 __ lists the functions of ports P0 to P4 and pin E in the memory expansion or microprocessor mode. 12-2 7733 Group User's Manual CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 A0(P00) A1(P01) A2(P02) A3(P03) A4(P04) A5(P05) A6(P06) A7(P07) A8/D8(P10) A9/D9(P11) A10/D10(P12) A11/D11(P13) A12/D12(P14) A13/D13(P15) A14/D14(P16) A15/D15(P17) A16/D0(P20) A17/D1(P21) A18/D2(P22) A19/D3(P23) When external data bus is 16 bits wide (BYTE = "L") 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG/TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 65 40 66 39 67 38 68 37 69 36 70 35 71 34 72 M37733MHBXXXFP 73 74 33 32 31 75 30 76 29 77 28 78 27 79 26 80 25 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 P42/ 1 RDY 1 A20/D4(P24) A21/D5(P25) A22/D6(P26) A23/D7(P27) R/W(P30) BHE(P31) ALE(P32) HLDA(P3 3) Vss E XOUT XIN RESET CNVSS BYTE HOLD 1 in the microprocessor mode : External address bus, external data bus, and bus control signals By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin's level can be fixed in the stop or wait mode. P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 A0(P00) A1(P01) A2(P02) A3(P03) A4(P04) A5(P05) A6(P06) A7(P07) A8(P10) A9(P11) A10(P12) A11(P13) A12(P14) A13(P15) A14(P16) A15(P17) A16/D0(P20) A17/D1(P21) A18/D2(P22) A19/D3(P23) When external data bus is 8 bits wide (BYTE = "H") 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG/TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 65 40 66 39 67 38 68 37 69 36 70 35 71 34 72 M37733MHBXXXFP 73 33 32 74 31 75 30 76 29 77 28 78 27 79 26 80 25 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 P42/ 1 RDY 1 A20/D4(P24) A21/D5(P25) A22/D6(P26) A23/D7(P27) R/W(P30) BHE(P31) ALE(P32) HLDA(P33) Vss E XOUT XIN RESET CNVss BYTE HOLD 1 in the microprocessor mode : External address bus, external data bus, and bus control signals By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin's level can be fixed in the stop or wait mode. Fig. 12.1.1 Pin configuration in memory expansion or microprocessor mode (Top view) 7733 Group User's Manual 12-3 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices __ Table 12.1.1 Functions of ports P0 to P4 and pin E in memory expansion or microprocessor mode External data bus width 16 bits (BYTE = "L") Pin name A7 to A0 A7 to A0 A15/D15 to A8/D8 A15/D 15 to A8/D8 8 bits (BYTE = "H") A7 to A0 A15 to A 8 A15 to A8 D(odd) A 15 to A8 D(odd) : Data at odd address A23/D7 to A16/D0 A23/D 7 to A16/D 0 A23 to A16 A23 /D7 to A16 /D0 D(even) D(even) : Data at even address HLDA HLDA ALE ALE BHE BHE BHE R/W R/W R/W P47 to P43 A23 to A 16 D D : Data HLDA ALE P47 to P43 P P : Functions as programmable I/O port 1 RDY HOLD E 1 RDY HOLD E (Note 1) 1 RDY HOLD (Note 2) Notes 1: In the memory expansion mode, this pin functions as a programmable I/O port. Furthermore, it can be switched to be a clock 1 output pin when selected by software. In the microprocessor mode, this pin is affected by the signal output disable selection bit (bit 6 at address 6C16). (Refer to Table 12.1.5.) 2: This signal is affected by the signal output disable selection bit (bit 6 at address 6C 16). (Refer to Table 12.1.2.) 12-4 7733 Group User's Manual CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices 12.1.1 External bus (A0 to A 7, A 8/D 8 to A15 /D 15 , and A 16 /D 0 to A 23 /D 7) The address is output from pins A0 to A 23 and specify the external area. Figure 12.1.2 shows the external area. Pins A 8 to A 23 of the external address bus and pins D0 to D 15 of the external data bus share the same pins. When pin BYTE's level, which is described later, is "L," in other words, when the external data bus is 16 bits wide, pins A 8 /D8 to A 15/D 15 and A 16/D 0 to A 23/D 7 perform address output and data input/ output with the time-sharing method. When pin BYTE's level is "H," in other words, when the external data bus is 8 bits wide, pins A16/D0 to A23/D7 perform address output and data input/output with the time-sharing method and pins A 8 to A 15 output the address. Microprocessor mode Memory expansion mode 00000016 00000016 SFR area SFR area 00008016 000080 16 Internal RAM area 00100016 Internal RAM area 00100016 Internal ROM area (Note) 02000016 FFFFFF 16 FFFFFF 16 : External area Note: This is applied when the memory allocation selection bits (bits 2 to 0 at address 63 For details, refer to section "2.4 Memory allocation." 16) = "000 2." Fig. 12.1.2 External area 7733 Group User's Manual 12-5 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices 12.1.2 External data bus width selection signal (Pin BYTE's level) This signal is used to select the external data bus width from 8 bits and 16 bits. When this signal level is "L," the external data bus is 16 bits wide; when this signal level is "H," the external data bus is 8 bits wide. (Refer to Table 12.1.1.) This signal level must be fixed to either "H" or "L." This signal is valid only for the external areas. (When the internal area is accessed, the data bus is always 16 bits wide.) __ 12.1.3 Enable signal ( E) When data is read or written, this signal level is "L." This signal is affected by the signal output disable selection bit (bit 6 at address 6C16). (Refer to Table 12.1.2.) __ Table 12.1.2 E state Processor mode Signal output disable selection bit 0 1 Conditions Memory expansion or When the external area is accessed Microprocessor mode When the internal area is accessed When the standby state selection bit = "1" in the stop or wait mode When the standby state selection bit = "0" in the stop or wait mode When not in the stop or wait mode Single-chip mode When in the stop or wait mode Operating Operating Stopped at "H" level Stopped at "H" level Stopped at "L" level Stopped at "H" level Operating Stopped at "L" level Stopped at "H" level Stopped at "L" level For the stop and wait modes and the standby state selection bit, refer to chapter "11. STOP AND WAIT MODES." : Not affected by the signal output disable selection bit. __ 12.1.4 Read/Write signal (R/ W) This signal indicates data bus state. When data is written, this signal level is "L." Table 12.1.3 lists the data __ __ bus state indicated by signals E and R/ W. Table 12.1.3 Data bus state __ __ E R/W Data bus state H H Not used L L H Read L Write 12-6 7733 Group User's Manual CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices ____ 12.1.5 Byte high enable signal ( BHE) This signal indicates access to an odd address. This signal level is "L" when accessing only an odd address or when simultaneously accessing both an odd address and an even address. This signal is used when connecting memory or I/O of which data bus is 8 bits wide with the 16-bit external data bus used. Table 12.1.4 lists the relationship between signal A 0 of the external address bus, signal ____ BHE, and access address. ____ Table 12.1.4 Relationship between signals A 0, BHE and access address Access address Even and Odd addresses (Simultaneous 2-byte access) Even address (1-byte access) Odd address (1-byte access) L L L H H L A0 ____ BHE 12.1.6 Address latch enable signal (ALE) This signal is used to latch an address from a multiplexed signal. This multiplexed signal consists of the address and data and is input or output to or from pins A8/D8 to A15/D15, A16/D0 to A23/D7. When this signal level is "H," take the address into a latch and output it simultaneously. When this signal level is "L," retain the latched address. ____ 12.1.7 Signal related to ready function (RDY) This signal is required to use the ready function. (Refer to section "12.3 Ready function.") _____ _____ 12.1.8 Signals related to hold function (HOLD , HLDA) These signals are required to use the hold function. (Refer to section "12.4 Hold function.") 12.1.9 Clock 1 This signal has the same period as internal clock . Whether to output or stop clock 1 can be selected by software. However, the method of this selection depends on the processor mode. Table 12.1.5 lists the method to select whether to output or stop clock 1 . Figure 12.1.3 shows the clock 1 output start timing. Table 12.1.5 Method to select whether to output or stop clock 1 Processor mode Clock 1 output Single-chip or Memory expansion mode Set the clock 1 output selection bit "1." *1 to Microprocessor mode Clear the signal output disable selection bit*2 to "0." Clock 1 stopped Clear the clock 1 output selection bit to "0." (Pin P4 2 functions as a programmable I/O port.) Set the signal output disable selection bit to "1." (Note) Remark Clock 1 is stopped after reset. The signal output disable selection bit is ignored. Clock 1 is output after reset. The clock 1 output selection bit is ignored. Clock 1 output selection bit *1: Bit 7 at address 5E 16 Signal output disable selection bit *2: Bit 6 at address 6C 16 (Refer to Table 12.1.2.) Note: In this case, make sure that bit 2 at address C 16 (Port P4 direction register) is set to "1." When bit 2 at address A16 (Port P4 register) = "0," "L" level is output: when this bit = "1," "H" level is output. 7733 Group User's Manual 12-7 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices The clock 1 output selection bit is set to "1." E Clock 1 Notes 1: There is a possibility that the first cycle of clock 1 output is not an exact square; the shaded section may be lost. 2: This is applied when "1" is written to the clock 1 output selection bit while pin P4 2 outputs "L" level. Fig. 12.1.3 Clock 1 output start timing (when clock 1 output selection bit is set from "0" to "1") b7 b6 b5 b4 b3 b2 b1 b0 Oscillation circuit control register 0 (address 6C16) Bit Bit name 0 XCOUT drivability selection bit 1 Not implemented. 2 Main clock stop bit Functions 0: Drivability "LOW" 1: Drivability "HIGH" 0: Main clock oscillation or external clock input is available. At reset RW 1 RW (Note 1) Undefined - 0 RW (Note 1) RW (Note 2) 1: Main clock oscillation or external clock input is stopped. 3 System clock selection bit When the port-Xc selection bit = "0," 0: Main clock 1: Main clock divided by 8 When the port-Xc selection bit = "1," 0: Main clock 1: Sub clock 0 4 Port-Xc selection bit. 0: Operate as I/O ports (P77, P76). 1: Operate as pins XCIN and XCOUT. 0 5 System clock stop bit at wait state (Note 4) 0: Operates in the wait mode. 1: Stopped in the wait mode. 0 RW 6 Signal output disable selection bit 0: Output is enabled. 1: Output is disabled. 0 RW 7 Not implemented. Undefined - (Refer to Tables 12.1.2 and 12.1.5) RW (Notes 2 and 3) Notes 1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc selection bit = "1." 2: When selecting the sub clock as the system clock, set bit 3 to "1" after setting bit 4 to "1." If the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to "1." 3: Although this bit can be set to "1," it cannot be cleared to "0" after this bit is once set to "1." 4: When setting the system clock stop bit at wait state to "1," perform it immediately before the WIT instruction is executed. Furthermore, clear this bit to "0" immediately after the wait mode is terminated. 5: represents that bits 0 to 5 and 7 are not used for access control of external area. (Functions of these bits are valid.) Fig. 12.1.4 Structure of oscillation circuit control register 0 12-8 7733 Group User's Manual CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices Value "1" is written to the signal output disable selection bit. E (Note) Clock 1 (in the microprocessor mode) Signal is stopped. Note: For conditions and signal levels, refer to Tables 12.1.2 and 12.1.5. Fig. 12.1.5 Relationship __ between setting of signal output disable selection bit and stop timing of clock 1 and E 7733 Group User's Manual 12-9 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices 12.1.10 Operation of bus interface unit (BIU) Figures 12.1.6 and 12.1.7 show operating waveform examples of signals which are input to or output from the external when accessing external devices. These waveforms are described in relation to the basic operating waveforms. (Refer to section "2.2.3 Operation of bus interface unit (BIU).") (1) When fetching an instruction into an instruction queue buffer When an instruction which is next fetched resides at an even address When the external data bus is 16 bits wide, the BIU fetches two bytes of the instruction at a time with waveform (a). When the external data bus is 8 bits wide, the BIU fetches only one byte of the instruction with the first half of waveform (e). When an instruction which is next fetched resides at an odd address When the external data bus is 16 bits wide, the BIU fetches only one byte of the instruction with waveform (d). When the external data bus is 8 bits wide, the BIU fetches only one byte of the instruction with the first half of waveform (f). When branched to an odd address by executing a branch instruction or others with the 16-bit external data bus, at first, the BIU fetches one byte of an instruction with waveform (d) and then fetches instructions by the two bytes with waveform (a). (2) When reading or writing data from or to memory * I/O When accessing 16-bit data which starts from an even address, waveform (a) or (e) is applied. When accessing 16-bit data which starts from an odd address, waveform (b) or (f) is applied. When accessing 8-bit data which resides at an even address, waveform (c) or the first half of waveform (e) is applied. When accessing 8-bit data which resides at an odd address, waveform (d) or the first half of waveform (f) is applied. For instructions which are affected by data length flag (m) and index register length flag (x), an operation is applied as follows: *When "m" or "x" = "0," operation or is applied. *When "m" or "x" = "1," operation or is applied. Settings of flags "m" and "x" and selection of the external data bus width do not affect each other. 12-10 7733 Group User's Manual CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices When external data bus is 16 bits wide (BYTE = "L" ) <16-bit data access> (a) Access starting from even address E ALE A0 to A 7 Address A8/D8 to A 15/D15 Address Data (odd) A16/D0 to A23/D 7 Address Data (even) A0 BHE (b) Access starting from odd address E ALE A0 to A 7 Address A8/D8 to A 15/D15 Address A16/D0 to A 23/D7 Address Address Data (odd) Address Address Data (even) A0 BHE <8-bit data access> (c) Access to even address (d) Access to odd address E E ALE ALE A0 to A 7 A0 to A 7 Address A8/D8 to A 15/D15 Address A16/D0 to A 23/D7 Address Data (even) Address A8/D8 to A 15/D15 Address A16/D0 to A23/D 7 Address A0 A0 BHE BHE Data (odd) Fig. 12.1.6 Operating waveform examples of signals which are input to or output from the external (1) 7733 Group User's Manual 12-11 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices When external data bus is 8 bits wide (BYTE = "H" ) <8/16-bit data access> (e) Access starting from even address E ALE A0 to A7 Address Address A8 to A15 Address Address A16/D0 to A 23/D7 Address Data Address Data A0 BHE 8-bit data access 16-bit data access (f) Access starting from odd address E ALE A0 to A7 Address Address A8 to A15 Address Address A16/D0 to A23/D7 Address Data Address Data A0 BHE 8-bit data access 16-bit data access Note: When 16-bit data is accessed, the low-order 8 bits of data are accessed first, and then, the high-order 8 bits are accessed. Fig. 12.1.7 Operating waveform examples of signals which are input to or output from the external (2) 12-12 7733 Group User's Manual CONNECTING EXTERNAL DEVICES 12.2 Software wait 12.2 Software wait The software wait facilitates access to external devices which require a long access time. There are two types of software waits: wait 0 and wait 1. The software wait is set by the wait bit (bit 2 at address 5E16) and the wait selection bit (bit 0 at address 5F16). (Refer to Table 12.2.1.) Figure 12.2.1 shows the structures of the processor mode register 0 (address 5E16) and processor mode register 1 (address 5F 16). Figure 12.2.2 shows bus timing examples when the software wait is used. The software wait is valid only for the external area. (Access to the internal areas is always performed with no wait.) Table 12.2.1 Setting method of software wait Wait bit Wait selection bit Software wait Bus cycle 1 0 Invalid (No wait) Cycle of "internal clock divided by 2" (clock 1's cycle 2) 0 0 Wait 0 "Cycle in the no-wait state" 2 (clock 1's cycle 4) 0 1 Wait 1 "Cycle in the no-wait state" 1.5 (clock 1's cycle 3) 7733 Group User's Manual 12-13 CONNECTING EXTERNAL DEVICES 12.2 Software wait b7 b6 b5 b4 b3 b2 b1 b0 0 Processor mode register 0 (address 5E 16) Bit name Bit 0 Functions b1 b0 Processor mode bits 00: Single-chip mode 01: Memory expansion mode 10: Microprocessor mode 11: Do not select. 1 At reset RW 0 RW 0 RW (Note 1) 2 Wait bit 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. 0 RW 3 Software reset bit Microcomputer is reset by setting this bit to "1." This bit is "0" at reading. 0 WO 4 Interrupt priority detection time selection bits 0 RW 0 RW 0 RW 0 RW b5 b4 5 6 Must be fixed to "0." 7 Clock 1 output selection bit (Note 2) 00: 7 cycles of 01: 4 cycles of 10: 2 cycles of 11: Do not select. 0: Clock 1 output is disabled. (P4 2 functions as a programmable /O port.) 1: Clock 1 output is enabled. (Port P4 2 functions as a clock 1 output pin.) Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to "1" after reset. (At reading, this bit is always "1.") 2: This bit is ignored in the microprocessor mode. (It may be "0" or "1.") 3: represents that bits 3 to 6 are not used for access control of the external area. (Functions of these bits are valid.) b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 1 (address 5F 16 ) Bit 0 Bit name Wait selection bit Function 0 : Wait 0 1 : Wait 1 7 to1 Not implemented. At reset RW 0 RW Undefined _ Fig. 12.2.1 Structures of processor mode register 0 and processor mode register 1 12-14 7733 Group User's Manual CONNECTING EXTERNAL DEVICES 12.2 Software wait <<No wait>> 1-bus cycle Clock 1 E ALE A 0 to A7 (Note) A 8/D8 to A15/D15, A16/D 0 to A23/D7 Address Address Address Data Address Data This waveform is always applied when the internal area is accessed. <<Wait 0>> 1-bus cycle Clock 1 E ALE Address A 0 to A7 Address (Note) A 8/D8 to A15/D15, A16/D 0 to A23/D7 Address Data Address Data <<Wait 1>> 1-bus cycle Clock 1 E ALE A 0 to A7 Address Address (Note) A8/D8 to A15/D 15, A16/D 0 to A23/D7 Address Data Address Data Note: When the external data bus is 8 bits wide (BYTE = "H" ), operating waveform of A 8/D8 to A 15/D15 is the same as that of A 0 to A 7. Fig. 12.2.2 Bus timing examples when software wait is used (BYTE = "L" ). 7733 Group User's Manual 12-15 CONNECTING EXTERNAL DEVICES 12.3 Ready function 12.3 Ready function The ready function facilitates access to external devices which require a long access time. ____ By applying "L" level to pin RDY in the memory expansion or microprocessor mode, the microcomputer ____ enters the ready state. While pin RDY's level is "L," this state is retained. Table 12.3.1 lists the microcomputer's state in the ready state. In the ready state, oscillation of the oscillator does not stop. Therefore, the internal peripheral devices can operate even in the ready state. The ready function is valid for the internal and external areas. Table 12.3.1 Microcomputer's state in ready state Item State Operating Oscillation CPU _____ Stopped at "L" level __ __ ____ ____ HLDA, E, R/W, BHE, ALE, A0 Retains the same state in which RDY was accepted. to A7, A8/D8 to A15/D15, A16/ D0 to A 23 /D 7, P4 3 to P4 7 , P 5 to P 8 P4 2/ 1 In the memory expansion mode When the clock 1 output selection bit *1 = "1" Outputs clock 1 . When the clock 1 output selection bit = "0" ____ Retains the same state in which RDY was accepted. In the microprocessor mode When the signal output disable selection bit*2 = "1" ____ Retains the same state in which RDY was accepted. When the signal output disable selection bit = "0" Outputs clock 1 . Timers A and B, Serial I/O, Operating A-D converter, Watchdog timer Clock 1 output selection bit *1: Bit 7 at address 5E 16 Signal output disable selection bit *2: Bit 6 at address 6C 16 ____ Note: When "L" level which was input to pin RDY is sampled at one of the following timings, this signal is not accepted. (Note that CPU is stopped at "L" level.) __ When the level of signal E is "H" while the bus is in use (Refer to in Figure 12.3.1.) Immediately before a wait generated by the software wait (Refer to in Figure 12.3.1.) 12-16 7733 Group User's Manual CONNECTING EXTERNAL DEVICES 12.3 Ready function 12.3.1 Operation in ready ____ state When "L" level is input to pin RDY, this signal is accepted at the falling edge of clock 1 and the microcomputer ____ enters the ready state. ____ The ready state can be terminated by setting pin RDY's level to "H" again. When "H" level is input to pin RDY, this signal is also accepted at the falling edge of clock 1 and the ready state is terminated. Figure 12.3.1 shows timings when the ready state is accepted and terminated. Refer to section "17.1 Memory expansion" for the way to use the ready function. 7733 Group User's Manual 12-17 CONNECTING EXTERNAL DEVICES 12.3 Ready function <<No wait>> Sampling timing Clock 1 CPU "L" level which is input to pin RDY is accepted, so that signal E is stopped at "H" level for 1 cycle of clock 1 (area ), and at "L" level. CPU is stopped E "L" level which is input to pin RDY is not accepted, but CPU is stopped at "L" level. "L" level which is input to pin RDY is accepted, so that signal E is stopped at "L" level for 1 cycle of clock 1 ALE RDY Bus is not in use. <<Wait 0>> (area "L" level. Bus is in use. "L" level which is input to pin RDY is not accepted because it is sampled immediately before a wait generated by software (area ), but CPU is stopped at "L" level. CPU E ALE RDY Bus is in use. Sampling timing Clock 1 CPU E ALE RDY Bus is in use. Fig. 12.3.1 Timings when ready state is accepted and terminated 12-18 7733 Group User's Manual is stopped at Ready state is terminated. 1 <<Wait 1>> CPU Sampling timing Clock ), and CONNECTING EXTERNAL DEVICES 12.4 Hold function 12.4 Hold function When an external circuit which accesses the bus without using the central processing unit (CPU), for example DMA, is used, it is necessary to generate a timing for transferring the right to use of the bus from the CPU to the external circuit. The hold function is used to generate this timing. _____ By applying "L" level to pin HOLD in the memory expansion or microprocessor mode, the microcomputer _____ enters the hold state. While pin HOLD's level is "L," this state is retained. Table 12.4.1 lists the microcomputer's state in the hold state. In the hold state, oscillation of the oscillator does not stop. Therefore, the internal peripheral devices can operate even in the hold state. (Note that the watchdog timer stops.) Table 12.4.1 Microcomputer's state in hold state Item Oscillation Operating CPU Stopped at "L" State A 0 to A 7 , A 8 /D 8 to A 15 /D 15 , Floating __ ____ A16 /D 0 to A 23 /D 7, R/ W, BHE _____ Outputs "L" level. In the memory expansion mode When the clock 1 output selection bit *1 = "1" Outputs clock 1. When the clock 1 output selection bit = "0" _____ Retains the same state in which HOLD was accepted. HLDA , ALE P4 2/ 1 In the microprocessor mode When the signal output disable selection bit*2= "1" _____ Retains the same state in which HOLD was accepted. When the signal output disable selection bit = "0" Outputs clock 1. _____ P4 3 to P4 7 , P5 to P8 Retains the same state in which HOLD was accepted. Timers A and B, Serial I/O, Operating A-D converter Watchdog timer Stopped Clock 1 output selection bit : Bit 7 at address 5E 16 Signal output disable selection bit *2: Bit 6 at address 6C 16 *1 7733 Group User's Manual 12-19 CONNECTING EXTERNAL DEVICES 12.4 Hold function 12.4.1 Operation in Hold state _____ When "L" level is input to pin HOLD while the bus is not in use, this signal is accepted at the falling edge _____ of clock 1 in each bus cycle. When "L" level is input to pin HOLD while the bus is in use, this signal is accepted at the last falling edge of clock 1 . (Refer to Figures 12.4.2 to 12.4.6.) When word data which starts from an odd address is accessed by the two bus cycles, determination is performed only in the second bus cycle. (Refer to Figure 12.4.1.) _____ When "L" level which_____ was input to pin HOLD is accepted, CPU is stopped at the next rising edge of clock 1 . At this time, pin HLDA outputs "L" level, and so the external _____ is informed that the microcomputer is in __ ____ the hold state. After one cycle of clock 1 has passed since pin HLDA's level becomes "L," pins R/ W, BHE and the external bus enter the floating state. _____ The hold state can be terminated by setting pin HOLD 's level to "H" again. When "H" level is input to pin _____ _____ HOLD, the signal _____ is accepted at the falling edge of clock 1. When "H" level which was input to pin HOLD is accepted, pin HLDA's level goes from "L" to "H." And then, the hold state is terminated after one cycle of clock 1 has passed. Figures 12.4.2 to 12.4.6 show the timing when the hold state is accepted and terminated. _____ In the ready state, determination of pin HOLD's input level is not performed. Determination timing of pin HOLD 's input level Not Determined determined Clock 1 E ALE At reading A At writing A A W A W Word data is accessed by the two bus cycles. (in this case, no wait) Fig.12.4.1 Determination when word data which starts from odd address is accessed by the two bus cycles 12-20 7733 Group User's Manual CONNECTING EXTERNAL DEVICES 12.4 Hold function <<When "L" level is input to pin HOLD while bus is not in use>> State when "L" level is input to pin HOLD External data bus Data length External data bus width Software wait 8 8, 16 No wait, 16 8, 16 Wait 1, Wait 0 Not in use Note: The same operation is performed independent of the software wait (no wait, wait 0, or wait 1). This diagram shows the operation when no wait is selected. Sampling timing Clock 1 ALE E Floating R/W External address bus/ External data bus Address A Data Floating Address A Address B External address bus Floating BHE HOLD 1 1 1 1 HLDA Hold state Bus is in use. Bus is not in use. Bus is in use. Because the bus is not in use, the address which was output immediately before is output again, instead of a new address. Fig. 12.4.2 Timing when hold state is accepted and terminated (1) 7733 Group User's Manual 12-21 CONNECTING EXTERNAL DEVICES 12.4 Hold function <<When "L" level is input to pin HOLD while bus is in use (1)>> State when "L" level is input to pin HOLD External data bus Data length External data bus width 8 8,16 In use 16 Software wait No wait 16 (When accessed starting from even address) Sampling timing Clock 1 ALE E Floating R/W Address A External address bus/ External data bus Address A Floating Data External address bus Address B Floating BHE HOLD 1 1 1 1 HLDA Hold state Bus is in use. When "L" level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. Fig. 12.4.3 Timing when hold state is accepted and terminated (2) 12-22 7733 Group User's Manual Bus is in use. CONNECTING EXTERNAL DEVICES 12.4 Hold function <<When "L" level is input to pin HOLD while bus is in use (2)>> State when "L" level is input to pin HOLD External data bus Data length External data bus width 8 8,16 In use Software wait Wait 1 16 16 (When accessed starting from even address) Sampling timing Clock 1 ALE E Floating R/W Address A Address A External address bus/ External data bus Floating Address B Data Floating External address bus BHE HOLD 1 1 1 1 HLDA Hold state Bus is in use. Bus is in use. When "L" level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. Fig. 12.4.4 Timing when hold state is accepted and terminated (3) 7733 Group User's Manual 12-23 CONNECTING EXTERNAL DEVICES 12.4 Hold function <<When "L" level is input to pin HOLD while bus is in use (3)>> State when "L" level is input to pin HOLD External data bus Data length External data bus width 8 8,16 In use Software wait Wait 0 16 16 (When accessed starting from even address) Sampling timing Clock 1 ALE E Floating R/W Address A External address bus/ External data bus Floating Address A Address B Data External address bus Floating BHE HOLD 1 1 1 1 HLDA Hold state Bus is in use. When "L" level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. Fig. 12.4.5 Timing when hold state is accepted and terminated (4) 12-24 7733 Group User's Manual Bus is in use. CONNECTING EXTERNAL DEVICES 12.4 Hold function <<When "L" level is input to pin HOLD while bus is in use (4)>> State when "L" level is input to pin HOLD External data bus Data length In use 16 External data bus width Software wait 8 No wait 16 (When accessed starting from odd address) Sampling timing Clock 1 ALE E Floating R/W Low-order address High-order address External address bus/ External data bus Floating Data Data Address External address bus Floating BHE HOLD Not sampled 1 1 1 1 HLDA Hold state Bus is in use. Bus is in use. When "L" level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. Sampling is not performed until 16-bit data input/output is finished. ( "L" level input to pin HOLD is not accepted.) Fig. 12.4.6 Timing when hold state is accepted and terminated (5) 7733 Group User's Manual 12-25 CONNECTING EXTERNAL DEVICES 12.4 Hold function MEMO 12-26 7733 Group User's Manual CHAPTER 13 RESET 13.1 Hardware reset 13.2 Software reset RESET 13.1 Hardware reset How to reset the microcomputer is described below. There are two methods to reset the microcomputer: hardware reset and software reset. 13.1 Hardware reset When the power source voltage satisfies the recommended operating conditions, the microcomputer is reset ______ by applying "L" level to pin RESET . (This is called "Hardware reset.") Figure 13.1.1 shows an example of hardware reset timing. "H" RESET "L" 2 s or more 4 to 5 cycles of internal clock Internal processing sequence after reset Program executed Fig. 13.1.1 Example of hardware reset timing (when main clock is stably supplied.) The microcomputer's operation during periods to is described below. ______ After "L" level is applied to pin RESET , pins are initialized within a period of several ten ns. (Refer to Table 13.1.1.) ______ ______ While pin RESET is at "L" level or within a period of 4 to 5 cycles of internal clock after pin RESET's level changes from "L" to "H," the central processing unit (CPU) and SFR area are initialized. At this time, the contents of the internal RAM area is undefined (except the cases where the stop or wait mode is terminated.). Refer to Figures 13.1.2 to 13.1.6. After , "Internal processing sequence after reset" is performed. Refer to Figure 13.1.7. A program is executed beginning with the address set in the reset vector addresses (addresses FFFE 16 and FFFF 16). 13-2 7733 Group User's Manual RESET 13.1 Hardware reset 13.1.1 Pin state ______ Table 13.1.1 lists the pin state while pin RESET is at "L" level. ______ Table 13.1.1 Pin state while pin RESET is at "L" level Mask ROM version Pin CNVSS 's level V SS or V CC Pin (Port) name P0 to P8 _ E Built-in PROM version VSS P0 to P8 _ E VCC P0, P1, P3 to P8 P2 _ E External ROM version VCC A0 to A 7 , ____ A8 /D8 to A 23/D 7, BHE __ _____ _ R/W, HLDA , E , ALE P4 to P8 7733 Group User's Manual Pin state Floating "H" level is output. Floating "H" level is output. Floating *Floating when "H" level is applied to both or one of pins P51 and P52 *"H" or "L" level is output when "L" level is applied to both of pins P5 1 and P5 2 . "H" level is output. Undefined value is output. "H" level is output. "L" level is output. Floating 13-3 RESET 13.1 Hardware reset 13.1.2 State of CPU, SFR area, and internal RAM area Figure 13.1.2 shows the state of the CPU registers immediately after reset. Figures 13.1.3 to 13.1.6 show the state of the SFR area and internal RAM area immediately after reset. 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. 0 : Nothing is allocated. Always "0" at reading State immediately after reset Register name b7 b0 Data bank register (DT) 0016 b7 b0 Program bank register (PG) 0016 b15 Program counter (PC) b8 b15 b8 b0 0016 0 0 0 0 0 0 0 IPL Fig. 13.1.2 State of CPU registers immediately after reset 13-4 b7 0016 b15 Processor status register (PS) b0 Contents of address FFFE 16 Contents of address FFFF 16 Direct page register (DPR) b7 7733 Group User's Manual b8 b7 b0 0 ? ? 0 0 0 1 ? ? N V m x D I Z C RESET 13.1 Hardware reset SFR area (addresses 016 to 7F16) Abbreviations and symbols which represent access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Not implemented. It is impossible to read the bit state. The written value becomes invalid. 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. Address Register name 016 116 216 316 416 516 616 716 816 916 A16 B16 C16 D16 E16 F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 1E16 1F16 Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register b7 0 : Always "0" at reading ? : Always undefined at reading 0 : "0" immediately after reset. Must be fixed to "0." Access characteristics Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register (Reserved area) (Reserved area) A-D control register 0 A-D control register 1 b7 b0 RW RW RW RW RW Port P3 register Port P2 direction register State immediately after reset b0 RW 0 0 0 RW 0 0 0 0 ? 0 ? 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW ? ? ? ? 0016 0016 ? 0 0016 0 0 ? ? 0016 0016 ? ? 0016 0016 ? ? 0016 ? ? ? ? ? ? ? ? ? 0 0 0 0 ? 0 0 0 ? ? ? 1 ? 1 Do not write data to addresses 1C16 and 1D16. Fig. 13.1.3 State of SFR area and internal RAM area immediately after reset (1) 7733 Group User's Manual 13-5 RESET 13.1 Hardware reset Address Register name 2016 A-D register 0 2116 2216 A-D register 1 2316 2416 A-D register 2 2516 2616 A-D register 3 2716 2816 A-D register 4 2916 2A16 A-D register 5 2B16 2C16 A-D register 6 2D16 2E16 A-D register 7 2F16 3016 UART0 transmit/receive mode register 3116 UART0 baud rate register 3216 UART0 transmission buffer register 3316 3416 UART0 transmit/receive control register 0 3516 UART0 transmit/receive control register 1 3616 UART0 receive buffer register 3716 3816 UART1 transmit/receive mode register UART1 baud rate register 3916 3A16 UART1 transmission buffer register 3B16 3C16 UART1 transmit/receive control register 0 3D16 UART1 transmit/receive control register 1 3E16 UART1 receive buffer register 3F16 b7 Access characteristics b0 State immediately after reset b7 RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW WO WO RW RO RO ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 1 0 0 0 0 ? 0 0 0 1 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? WO RW RW RO RW 0 0 0 0 0 0 RO 0 0 0 WO RW RW RO RW 0 0 0 0 0 0 RO 0 0 0 RO 0016 ? ? ? 0 1 0 0 ? 0 0 0016 ? ? ? 0 1 0 0 ? 0 0 Fig. 13.1.4 State of SFR area and internal RAM area immediately after reset (2) 13-6 ? ? RW WO WO RO ? ? RO RW RO b0 ? 7733 Group User's Manual RESET 13.1 Hardware reset Address Register name Access characteristics Count start flag 4016 4116 One-shot start flag 4216 4316 Up-down flag 4416 4516 4616 Timer A0 register 4716 4816 Timer A1 register 4916 4A16 Timer A2 register 4B16 4C16 Timer A3 register 4D16 4E16 Timer A4 register 4F16 5016 Timer B0 register 5116 5216 Timer B1 register 5316 5416 Timer B2 register 5516 Timer A0 mode register 5616 Timer A1 mode register 5716 Timer A2 mode register 5816 Timer A3 mode register 5916 Timer A4 mode register 5A16 Timer B0 mode register 5B16 Timer B1 mode register 5C16 Timer B2 mode register 5D16 5E16 Processor mode register 0 5F16 Processor mode register 10 State immediately after reset b0 b7 b0 b7 RW ? WO WO RW 0 0 0 0 0 0 0 0 0 0 0 ? ? ? 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RW RW RW RW RW RW RW RW 2 2 2 RW RW RW RW WO RW 3 RW RW 0016 ? 0 0 ? 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0016 0016 0016 0016 0016 ? 0 ? 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 1 Access characteristics at addresses 4616 to 5516 vary according to the timer's operating mode. (Refer to chapters "6. TIMER A" and "7. TIMER B.") 2 Access characteristics for bit 5 at addresses 5B16 to 5D16 vary according to the timer B's operating mode. (Refer to chapter "7. TIMER B.") 3 Access characteristics for bit 1 at address 5E16 and its state immediately after reset vary according to the voltage level applied to pin CNVSS. (Refer to section "2.5 Processor modes.") Fig. 13.1.5 State of SFR area and internal RAM area immediately after reset (3) 7733 Group User's Manual 13-7 RESET 13.1 Hardware reset Address Register name b7 Watchdog timer register 6016 6116 Watchdog timer frequency selection flag (Reserved area) 4 6216 Memory allocation control register 6316 UART2 transmit/receive mode register 6416 UART2 baud rate register (BRG2) 6516 6616 UART2 transmission buffer register 6716 6816 UART2 transmit/receive control register 0 6916 UART2 transmit/receive control register 1 6A16 UART2 receive buffer register 6B16 Oscillation circuit control register 0 6C16 Port function control register 6D16 Serial transmit control register 6E16 Oscillation circuit control register 1 6F16 WO 7016 A-D / UART2 trans./rece. interrupt control register 7116 UART0 transmission interrupt control register 7216 UART0 receive interrupt control register 7316 UART1 transmission interrupt control register 7416 UART1 receive interrupt control register Timer A0 interrupt control register 7516 Timer A1 interrupt control register 7616 Timer A2 interrupt control register 7716 Timer A3 interrupt control register 7816 Timer A4 interrupt control register 7916 Timer B0 interrupt control register 7A16 Timer B1 interrupt control register 7B16 Timer B2 interrupt control register 7C16 INT0 interrupt control register 7D16 INT1 interrupt control register 7E16 INT2/Key input interrupt control register 7F16 Access characteristics b0 State immediately after reset b7 b0 WO RW ? ? 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 RW RW WO WO RO RO WO RW RW RO RW 0 ? RO RW(2) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RO RW ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? ? ? 0 0 0 ? (1) ? ? 0 0 0 ? ? ? 1 0 0 ? 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 ? 0 ? 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value "FFF 16" is set to the watchdog timer. (Refer to chapter "10. WATCHDOG TIMER.") 2 For access characteristics at address 6C 16, also refer to Figure 14.3.2. 3 State immediately after reset for bit 3 at address 6F 16 vary according to the microcomputer. (Refer to Figure 14.3.3.) 4 Do not write data to address 62 16. Internal RAM area (M37733MHBXXXFP: addresses 80 16 to FFF16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset . When the stop or wait mode is terminated (when hardware reset is applied)...Retains the state immediately before the STP or WIT instruction was executed. Fig. 13.1.6 State of SFR area and internal RAM area immediately after reset (4) 13-8 7733 Group User's Manual RESET 13.1 Hardware reset 13.1.3 Internal processing sequence after a reset Figure 13.1.7 shows the internal processing sequence after reset. (1) Single-chip and Memory expansion modes Internal clock CPU Ap 0016 AHAL 000016 FFFE16 ADH, ADL Next op-code Unused DATA Unused ADH, ADL IPL, vector address E (2) Microprocessor mode Internal clock CPU Ap 0016 AHAL 000016 FFFE16 ADH, ADL Unused DATA Next op-code Unused ADH, ADL IPL, vector address E CPU: CPU's standard clock A p: High-order 8 bits of CPU address bus AHAL: Low-order 16 bits of CPU address bus DATA : CPU data bus ADH, AD L: Contents of reset vector addresses (addresses FFFE 16 and FFFF 16) Fig. 13.1.7 Internal processing sequence after reset 7733 Group User's Manual 13-9 RESET 13.1 Hardware reset ______ 13.1.4 Time required for applying "L" level to pin RESET ______ Time required for applying "L" level to pin RESET varies according to the main clock oscillation circuit's state. The case where an oscillator is stably oscillating or an external clock is stably input from pin X IN Apply "L" level for 2 s or more. The case where an oscillator is not stably oscillating (including the cases where power-on reset is applied and where the microcomputer operates in the stop mode) Apply "L" level until oscillation is stabilized. The time required for stabilizing oscillation varies according to the oscillator. For details, contact with the oscillator manufacturer. Figure 13.1.8 shows power-on reset conditions. Figure 13.1.9 shows an example of a power-on reset circuit. For the stop mode, refer to chapter "11. STOP MODE AND WAIT MODES." For clocks, refer to chapter "14. CLOCK GENERATING CIRCUIT." Powered on here 4.5V VCC 0V RESET 0.9V 0V Note: For the low voltage version, refer to Figure 18.3.1. Fig. 13.1.8 Power-on reset conditions 13-10 7733 Group User's Manual RESET 13.1 Hardware reset 5V M37733MHBXXXFP 1 M51957AL VCC VCC 27 k 2 10 k IN OUT 5 RESET 47 Delay 4 capacity VSS GND Cd 3 SW GND Delay time td is about 11 ms when C d = 0.033 F. td 0.34 Cd [ s], Cd: [ pF ] Note: For the low voltage version, refer to Figure 18.3.2. Fig. 13.1.9 Example of power-on reset circuit 7733 Group User's Manual 13-11 RESET 13.2 Software reset 13.2 Software reset When the power source voltage satisfies the recommended operating conditions and the main clock is stably supplied (Note), the microcomputer is reset by writing "1" to the software reset bit (bit 3 at address 5E 16). (This is called "Software reset.") In this case, the microcomputer initializes pins, CPU, and SFR area as in the case of a hardware reset. However, the microcomputer retains the contents of the internal RAM area. (Refer to Table 13.1.1 and Figures 13.1.2. to 13.1.6.) After completing initialization, the microcomputer performs "internal processing sequence after reset." (Refer to Figure 13.1.7.) Then, a program is executed beginning with the address set in the reset vector addresses (addresses FFFE 16 and FFFF16 ). Note: This means "when a oscillator is stably oscillating or when an external clock is stably input from pin X IN." For clocks, refer to chapter "14. CLOCK GENERATING CIRCUIT." b7 b6 0 b5 b4 b3 b2 b1 b0 Processor mode register 0 (address 5E 16) Bit name Bit 0 Processor mode bits 1 Functions At reset RW 0 RW 0 RW b1 b0 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Microprocessor mode 1 1: Do not select. (Note 1) 2 Wait bit 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. 0 RW 3 Software reset bit Microcomputer is reset by setting this bit to "1." This bit is "0" at reading. 0 WO 4 Interrupt priority detection time selection bits 0 RW 0 RW 5 b5 b4 0 0: 7 cycles of 0 1: 4 cycles of 1 0: 2 cycles of 1 1: Do not select. 6 Must be fixed to "0." 0 RW 7 Clock 1 output selection bit 0: Clock 1 output is disabled. (P4 2 functions as a (Note 2) 0 RW programmable I/O port.) 1: Clock 1 output is enabled. (Port P4 2 functions as a clock 1 output pin.) Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to "1" after reset. (At reading, this bit is always "1.") 2: This bit is ignored in the microprocessor mode. (It may be "0" or "1.") 3: represents that bits 0 to 2 and bits 4 to 7 are not used for software reset. Fig. 13.2.1 Structure of processor mode register 0 13-12 7733 Group User's Manual CHAPTER 14 CLOCK GENERATING CIRCUIT 14.1 Overview 14.2 Oscillation circuit example 14.3 Clock control CLOCK GENERATING CIRCUIT 14.1 Overview The clock generating circuit is described below. 14.1 Overview This clock generating circuit includes two oscillation circuits, which are main-clock and sub-clock oscillation circuits. Each of the main and sub clocks can be used as an operating clock for the CPU, internal peripheral devices, and clock timer. Table 14.1.1 Main-clock and sub-clock oscillation circuits Main-clock oscillation circuit * Operating clock source of CPU Usage of clock * Operating clock source of internal peripheral devices * Operating clock source of clock timer Resonator/Oscillator which can be connected Pins which are connected to resonator/oscillator Oscillation stop/restart (Note 2) Oscillator's state just after reset Remarks Sub-clock oscillation circuit * Ceramic resonator * Quartz-crystal oscillator Pins X IN and X OUT Quartz-crystal oscillator Available Operating Not available Stopped (Note 1) Pins X CIN and X COUT A clock which is externally generated * A clock which is externally can be input. generated can be input. * Sub clock can be input to external devices. (Refer to 14.3.1.) Notes 1: Immediately after reset, pins XCIN and X COUT function as ports P77 and P7 6 , respectively. The oscillator starts operating when pins' function is switched by the port-XC selection bit (bit 4 at address 6C16). 2: Whether oscillation is stopped or restarted is set by the main clock stop bit (bit 2 at address 6C16). In the main-clock/sub-clock oscillation circuit, oscillation can be stopped by the STP instruction; oscillation can be restarted by an interrupt request generated. (Refer to Figure 14.3.9.) 14-2 7733 Group User's Manual CLOCK GENERATING CIRCUIT 14.2 Oscillation circuit example 14.2 Oscillation circuit example Main-clock and sub-clock oscillation circuits' examples are described below. 14.2.1 Main-clock oscillation circuit example To the main-clock oscillation circuit, a resonator/ oscillator can be connected, or a clock which is externally generated can be input. M37733MHBXXXFP XIN (1) Connection example of resonator/oscillator Figure 14.2.1 shows an example where pins X IN and X OUT connect across a ceramic resonator/quartz-crystal oscillator. Circuit constants such as Rf, Rd, CIN, and COUT (shown in Figure 14.2.1) depend on the resonator/oscillator. These values shall be set to the resonator/oscillator manufacturer's recommended values. XOUT Rf Rd CIN COUT Fig. 14.2.1 Connection example of resonator/oscillator (2) Input example of clock which is externally generated Figure 14.2.2 shows an input example of a clock which is externally generated. When inputting a main clock from an external circuit, set "1" to bit 1 of the main-clock oscillation circuit control register 1. (Refer to Figure 14.3.3.) By this setting, the main-clock oscillation circuit stops operating and power consumption can be held down. Note that this bit has a function to select return conditions from the stop mode. (Refer to chapter "11. STOP AND WAIT MODES.") Furthermore, when writing to the oscillation circuit control register 1, follow the procedure shown in Figure 14.3.4. When inputting a main clock from an external circuit, that the external clock must be input from pin XIN, and pin XOUT must be left open. M37733MHBXXXFP XIN XOUT Open Externally generated clock VCC VSS Fig. 14.2.2 Externally generated clock input example 7733 Group User's Manual 14-3 CLOCK GENERATING CIRCUIT 14.2 Oscillation circuit example 14.2.2 Sub-clock oscillation circuit example To the Sub-clock oscillation circuit, an oscillator can be connected, or a clock which is externally generated can be input. (1) Connection example of oscillator When using an oscillator, connect a quartzcrystal oscillator between pins XCIN and XCOUT. (A ceramic resonator cannot be connected.) Figure 14.2.3 shows a quartz-crystal oscillator connection example. Circuit constants such as Rcf, Rcd, CCIN, and CCOUT (shown in Figure 14.2.3) depend on the oscillator. These values shall be set to the oscillator manufacturer's recommended values. When connecting an oscillator to the sub-clock oscillation circuit, set the port-Xc selection bit (bit 4 at address 6C16) to "1" and the sub clock external input selection bit (bit 2 at address 6F 16) to "0." Note that the sub clock external input selection bit has a function to select return conditions from the stop mode. (Refer to chapter "11. STOP AND WAIT MODES.") M37733MHBXXXFP XCIN XCOUT RCf RCd CCIN CCOUT Fig. 14.2.3 Connection example of quartz-crystal oscillator M37733MHBXXXFP XCIN P76/AN6 External circuit (2) Input example of clock which is externally generated Figure 14.2.4 shows an input example of a clock which is generated in an external circuit. When inputting a sub clock from an external circuit, be sure to set the sub clock external input selection bit to "1," and then, select pins X CIN and X COUT by the port-Xc selection bit. In this case, an externally generated clock is input to pin XIN, and pin XOUT functions as pin P76/AN6. Note that the sub clock external input selection bit has a function to select return conditions from the stop mode. (Refer to chapter "11. STOP AND WAIT MODES.") If the sub-clock output selection bit (bit 1 at address 6D 16) is set to "1" when the port-Xc selection bit = "1" (Note), sub clock SUB is output from port P6 7 . Accordingly, a 32-kHz sub clock can be supplied to external gates. Externally generated clock VCC VSS Fig. 14.2.4 Externally generated clock input example Note: At this time, a sub clock is used. 14-4 7733 Group User's Manual CLOCK GENERATING CIRCUIT 14.3 Clock control 14.3 Clock control Figure 14.3.1 shows the clock generating circuit block diagram. P76/AN6/XCOUT P77/AN7/XCIN P67/TB2IN/ 1 SUB 1 CM4 PC 1 CM4 (Port latch) 0 CM4 (Oscillation circuit control register 0: address 6C 16) CM2: Main clock stop bit CM3: System clock selection bit CM4: Port-Xc selection bit CM5: System clock stop bit at wait state (Oscillation circuit control register 1: address 6F 16) CC0: Main clock division selection bit CC1: Main clock external input selection bit CC2: Sub clock external input selection bit (Port function control register: address 6D 16) PC1: Sub-clock output selection bit/Timer B2 clock source selection bit 0 PC1 CM4 CC2 1 0 1 CM3 Timer B2 (Clock timer) (Event counter mode) 1/32 1 1 0 Sub clock f2 1 XOUT 1/8 1/2 1/4 1/2 f32 1/2 1/8 f512 0 0 0 Main clock f64 System clock CM4 1 0 f16 1/2 0 0 f8 1 1 XIN 1 fC32 (Clock prescaler) Internal clock CC0 CM3 CM3 CM4 12-bit watchdog timer WDC CM2 CM3 CC1 Watchdog timer frequency selection flag CM5 1 Q S S R STP instruction WIT instruction R Q Q S R Reset STP instruction 0 CC 1 CM3 CM4 CMi: Bit i at address 6C 16 (Refer to Figure 11.2.2.) CCi: Bit i at address 6F 16 (Refer to Figure 11.2.3.) Switch represented by Interrupt disable flag Interrupt request is controlled by a signal represented by " CC2 ". Fig. 14.3.1 Clock generating circuit block diagram 7733 Group User's Manual 14-5 CLOCK GENERATING CIRCUIT 14.3 Clock control 14.3.1 Clock generated in clock generating circuit (1) System clock It is the clock source of the system clock divided by 2, internal clock , clock 1, and clocks f2 to f512. (Refer to Figure 14.3.1.) Each of the main clock, main clock divided by 8, and the sub clock can be selected as the system clock by the system clock selection bit (bit 3 at address 6C16). Table 14.3.1 lists clock combinations of the system clock, internal clock , 1, and f 2. Table 14.3.1 Clock Port-Xc selection bit (bit 4 at 6C16) 0 (Sub clock is not used.) combinations of system clock, internal clock , 1, and f2 Main clock division System clock selection bit selection bit System clock Internal clock , 1, f2 (bit 0 at 6C16) (bit 3 at 6C16) 0 0 1 1 0 1 0 1 (Sub clock is used.) 0 1 1 0 Main clock Main clock Main clock divided by 8 Main clock divided by 8 Main clock Main clock Sub clock Main clock divided by 2 Main clock Main clock divided by 16 Main clock divided by 8 Main clock divided by 2 Main clock Sub clock divided by 2 1 (2) Main clock It is the clock supplied by the main-clock oscillation circuit. This clock is selected as the system clock immediately after reset. After the sub clock is selected as the system clock, the main-clock supply is stopped/restarted by the main clock stop bit (bits 2 at address 6C 16 ). (Refer to Figures 14.3.6 and 14.3.7.) By stopping the main-clock supply, power consumption can be held down. Figure 14.3.5 shows the clock f 2 state transition when a sub clock is not used because the port-Xc selection bit (bit 4 at address 6C16) = "0." During reset and till after reset state is terminated, the main clock divided by 2 is selected as clock f2. If the system clock selection bit (bit 3 at address 6C16 ) is set to "1," at this time, the main clock divided by 16 is selected as clock f2, and the clock frequency which is supplied to the CPU and peripheral devices becomes 1/8. Though this slow down the processing speed, current consumption is held down. Furthermore, by setting "1" to both of the main clock division selection bit (bit 0 at address 6F 16) and system clock selection bit, the main clock divided by 8 is selected as clock f 2. When the port-Xc selection bit = "0," clock fC32 , which is the main clock divided by 32, is connected as the timer B2's count source if the timer B2 clock source selection bit (bit 1 at address 6D 16) = "1" and timer B2 is used as a clock timer. By this, even when the main clock's ratio is changed, the clock timer can use the same clock source. (Refer to Figure 14.3.1.) 14-6 7733 Group User's Manual CLOCK GENERATING CIRCUIT 14.3 Clock control (3) Sub clock It is the clock supplied by the sub-clock oscillation circuit. The sub-clock supply is stopped immediately after reset (Note). When the port-Xc selection bit (bit 4 at address 6C16) is set to "1," the sub-clock oscillation circuit starts operating, in other words, oscillation starts or an external clock is input. Furthermore, in this case, f C32 (sub clock divided by 32) is connected. (Refer to section "7.6 Clock timer.") Furthermore, a sub clock can be the system clock by specifying the system clock selection bit after the oscillation is stabilized. (Refer to Figure 14.3.6.) The XCOUT pin's drivability can be lowered by the XCOUT drivability selection bit (bit 0 at address 6C16) after oscillation of the sub-clock oscillation circuit is stabilized. By lowering the X COUT pin's drivability, power consumption is held down. When a sub clock is used, in other words, bit 4 at address 6C 16 = "1," sub clock SUB is output from pin P6 7/TB2 IN/ SUB if the sub-clock output selection bit (bit 1 at address 6D 16 ) is set to "1." Note: At this time, the oscillator which is connected to the sub-clock oscillation circuit stops operating, and pins X CIN and XCOUT function as ports P76 and P7 7. (4) Internal clock It is the CPU's operating clock source, and its clock source is the system clock. (5) Clocks f 2 to f 512 Each of them is the internal peripheral devices' operating clock, and its clock source is the system clock. (6) Clock 1 It is output to external circuits and has the same period as internal clock , and its clock source is the system clock. (7) fC32 It is the main clock/sub clock divided by 32 (Refer to Figure 14.3.1.) and the count source of the clock timer. (Refer to "7.6 Clock timer.") (8) Sub clock SUB Sub clock SUB is output from port P67 if the sub clock output selection bit (bit 1 at address 6D16) is set to "1" when the port Xc selection bit = "1," in other words, when the sub clock is used. Therefore, the 32-kHz sub clock can be supplied to the external gate. 7733 Group User's Manual 14-7 CLOCK GENERA TING CIRCUIT 14.3 Clock control b7 b6 b5 b4 b3 b2 b1 b0 Oscillation circuit control register 0 (address 6C 16) Bit Bit name 0 XCOUT drivability selection bit 1 Not implemented. 2 Main clock stop bit Functions 0: Drivability "LOW" 1: Drivability "HIGH" 0: Main clock oscillation or external clock input is available. At reset RW 1 RW (Note 1) Undefined - 0 RW (Note 1) RW (Note 2) 1: Main clock oscillation or external clock input is stopped. 3 System clock selection bit When the port-Xc selection bit = "0," 0: Main clock 1: Main clock divided by 8 When the port-Xc selection bit = "1," 0: Main clock 1: Sub clock 0 4 Port-Xc selection bit 0: Operate as I/O ports (P7 7, P76 ). 1: Operate as pins X CIN and XCOUT . 0 5 System clock stop bit at wait state (Note 4) 0: Operates in the wait mode. 1: Stopped in the wait mode. 0 RW 6 Signal output disable selection bit 0: Output is enabled. 1: Output is disabled. 0 RW 7 Not implemented. Undefined - (Refer to Tables 12.1.2 and 12.1.5) RW (Notes 2 and 3) Notes 1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc selection bit = "1." 2: When selecting the sub clock as the system clock, set bit 3 to "1" after setting bit 4 to "1." If the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to "1." 3: Although this bit can be set to "1," it cannot be cleared to "0" after this bit is once set to "1." 4: When setting the system clock stop bit at wait state to "1," perform it immediately before the WIT instruction is executed. Furthermore, clear this bit to "0" immediately after the wait mode is terminated. Fig. 14.3.2 Structure of oscillation circuit control register 0 14-8 7733 Group User's Manual CLOCK GENERATING CIRCUIT 14.3 Clock control b7 b6 b5 b4 0 b3 b2 b1 b0 Oscillation circuit control register 1 (address 6F 16) Bit Bit name At reset RW 0 Main clock division selection bit 0: Main clock is divided by 2. (Note 1) 1: Main clock is not divided by 2. 0 RW 1 Main clock external input selection bit 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating (Note 1) stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. 0 RW 2 Sub clock external input selection bit 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin X COUT . (Note 1) Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P7 6 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. 0 RW 3 Ignored in the mask ROM and external ROM versions. 0 RW Must be fixed to "1" in the one time PROM and EPROM versions (Notes 1 and 2). 1 4 Must be fixed to "0" (Note 2). 0 RW 5 Not implemented. Undefined -- 6 Not implemented. Undefined -- 7 Clock prescaler reset bit 0 WO Functions (Note 3) By writing "1" to this bit, clock prescaler is initialized. Notes 1: When writing to this register, follow the procedure shown in Figure 14.3.4. 2: The case where data "01010101 2" is written with the procedure shown in Figure 14.3.4 is not included. 3: In the 7735 Group, fix this bit to "0." 4: represents that bits 3 to 7 are not used for the clock generating circuit Fig. 14.3.3 Structure of oscillation circuit control register 1 * When writing to bits 0 to 3 Write data "01010101 2." (LDM instruction) Next instruction Write data "00001XXX 2." (LDM instruction) (b3 in Figure 14.3.3) (b2 to b0 in Figure 14.3.3) Fig. 14.3.4 Procedure for writing data to oscillation circuit control register 1 7733 Group User's Manual 14-9 CLOCK GENERATING CIRCUIT 14.3 Clock control * When the sub clock is not used (CM 4 = "0") Notes 1: f2 = f(X IN)/2 represents that clock f 2 is the main clock divided by 2. 2: f2 = f(X IN) represents that clock f 2 is the main clock not divided. Reset (Note 1) f2 = f(XIN)/2 CM 3 = "0" CC0 = "1" CM 3 = "1" CC0 = "0" (Note 2) f2 = f(XIN)/16 f2 = f(XIN) CM 3 = "0" CC0 = "1" CC0 = "0" CM 3 = "1" f2 = f(XIN)/8 CC0: Main clock division selection bit CM 3: System clock selection bit CM4: Port-Xc selection bit Fig. 14.3.5 Clock f2 state transition (when sub clock is not used) 14-10 7733 Group User's Manual CLOCK GENERATING CIRCUIT 14.3 Clock control 14.3.2 System clock switching procedure Figures 14.3.6 to 14.3.8 show the system clock switching procedure. State of bits 4 to 1 of the oscillation circuit control register 0 when switching the system clock "1" (Sub-clock oscillation circuit: Oscillating) Port-Xc selection bit (bit 4) "0" System clock selection bit (bit 3) "1" "0" (Sub clock) (Main clock) (Main clock) "1" (Main-clock oscillation Main clock stop bit (bit 2) (Stopped) circuit: Oscillating) "0" a Main clock (Oscillating) b Main clock Sub clock System clock Oscillation stabilizing time (Note 2) Stopped Operating Operating Oscillation of the main-clock oscillation circuit Oscillation stabilizing time (Note 1) Oscillation of the sub-clock oscillation circuit Stopped Operating Notes 1: Before selecting the sub clock, make sure that oscillation of the sub clock is fully stabilized after oscillation starts. 2: Before selecting the main clock, make sure that oscillation of the main clock is fully stabilized after oscillation restarts. Fig. 14.3.6 System clock switching procedure (1) 7733 Group User's Manual 14-11 CLOCK GENERATING CIRCUIT 14.3 Clock control System clock switching procedure in order to stop the main clock supply when oscillator connected to the sub-clock oscillation circuit stops operating. (Refer to "a" in Figure 14.3.6. ) Operation start of the sub-clock oscillation circuit b7 b0 1 0 0 1 : Oscillation circuit control register 0 (address 6C 16) Port-X C selection bit 1: Function as pins X CIN and XCOUT (Waiting for oscillation stabilized in the sub-clock oscillation circuit) System clock switching b7 b0 : Oscillation circuit control register 0 (address 6C 16) 1 1 0 System clock selection bit 1: Sub clock Stop of the the main-clock supply b7 b0 1 1 1 : Oscillation circuit control register 0 (address 6C 16) Main clock stop bit 1: Stopped Fig. 14.3.7 System clock switching procedure (2) 14-12 7733 Group User's Manual CLOCK GENERATING CIRCUIT 14.3 Clock control System clock switching procedure in order to select the main clock as the system clock when the main clock supply stops. (Refer to "b" in Figure 14.3.6. ) Operation start of the main-clock oscillation circuit b7 b0 1 1 0 1 : Oscillation circuit control register 0 (address 6C 16) Main clock stop bit 0: Oscillator operates (or clock which is externally generated is input). (Waiting for oscillation stabilized in the main-clock oscillation circuit) System clock switching b7 b0 1 0 0 : Oscillation circuit control register 0 (address 6C 16) System clock selection bit 0: Main clock Fig. 14.3.8 System clock switching procedure (3) 7733 Group User's Manual 14-13 CLOCK GENERATING CIRCUIT 14.3 Clock control 14.3.3 Clock transition Figure 14.3.9 shows the clock transition. Reset Wait mode Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Stopped f2 - f512 (Note 2) Internal clock : Stopped WIT instruction Interrupt request generated Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Stopped System clock: Main clock STP instruction Stop mode Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Stopped System clock: Stopped Interrupt request generated Port-Xc selection bit: "1" Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Oscillating f2 - f512 (Note 2) Internal clock : Stopped WIT instruction Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Oscillating System clock: Main clock System clock selection bit: "0" (Note 1) Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Oscillating f2 - f512 (Note 2) Internal clock : Stopped Main-clock oscillation circuit: Oscillating Sub-clock oscillation circuit: Oscillating System clock: Sub clock STP instruction Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Stopped System clock: Stopped Interrupt request generated Main clock stop bit: "0" Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Oscillating f2 - f512 (Note 2) Internal clock : Stopped System clock selection bit: "1" (Note 1) Interrupt request generated WIT instruction Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Stopped System clock: Stopped Interrupt request generated Interrupt request generated WIT instruction STP instruction Main clock stop bit: "1" Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Oscillating System clock: Sub clock Interrupt request generated STP instruction Main-clock oscillation circuit: Stopped Sub-clock oscillation circuit: Stopped System clock: Stopped Interrupt request generated For the stop and wait modes, refer to chapter "11. STOP AND WAIT MODES." Notes 1: Before selecting the system clock, make sure that operation of the oscillator is fully stabilized. Additionally, generate oscillation stabilizing time by software. 2: In the wait mode, whether clocks f2 to f512 are supplied or stopped can be specified by the system clock stop bit at wait state. Fig. 14.3.9 Clock transition 14-14 7733 Group User's Manual CLOCK GENERATING CIRCUIT 14.3 Clock control 14.3.4 Clock prescaler reset The clock prescaler, which divides a sub clock by 32, is reset by writing "1" to the clock prescaler reset bit (bit 7 at address 6F16). By this function, the count source (fC32) error immediately after the clock timer starts counting can be held down. Figure 14.3.10 shows the operation timing of the clock prescaler and timer B2. Timer B2 count start flag Clock prescaler reset bit write pulse XCIN XCIN divided by 31 (Note) XCIN divided by 32 Clock timer clock source fC32 Timer B2 count value n (Set value) n--1 The above is applied when the main clock is selected as the system clock, in other words, when the system clock selection bit (CM3) = "0." Note: Only in this period, X CIN divided by 31 is selected. After this period, X CIN divided by 32 is selected. Figure 14.3.10 Operation timing of clock prescaler and timer B2 7733 Group User's Manual 14-15 CLOCK GENERATING CIRCUIT 14.3 Clock control Memo 14-16 7733 Group User's Manual CHAPTER 15 ELECTRICAL CHARACTERISTICS 15.1 Absolute maximum ratings 15.2 Recommended operating conditions 15.3 Electrical characteristics 15.4 A-D converter characteristics 15.5 Internal peripheral devices 15.6 Ready and Hold 15.7 Single-chip mode 15.8 Memory expansion mode and Microprocessor mode : with no wait 15.9 Memory expansion mode and Microprocessor mode : with wait 1 15.10 Memory expansion mode and Microprocessor mode : with wait 0 15.11 Measuring circuit for ports P0 to P8 and pins 1 and _ E ELECTRICAL CHARACTERISTICS 15.1 Absolute maximum ratings M37733MHBXXXFP's electrical characteristics are described below. For low voltage version, refer to section "18.4 Electrical characteristics." For the latest data, inquire of addresses described last ("CONTACT ADDRESSES FOR FURTHER INFORMATION") . 15.1 Absolute maximum ratings Absolute maximum ratings Symbol Parameter Vcc Power source voltage AVcc Analog power source voltage VI Input voltage RESET, CNVss, BYTE Input voltage P00-P07, P10-P17, P20-P27, P30-P33, VI P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, VREF, XIN Output voltage P00-P07, P10-P17, P20-P27, P30-P33, VO P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, XOUT, E Pd Power dissipation Topr Operating temperature Tstg Storage temperature 15-2 Conditions Ta = 25 C 7733 Group User's Manual Ratings -0.3 to 7 -0.3 to 7 -0.3 to 12 Unit V V V -0.3 to Vcc+0.3 V -0.3 to Vcc+0.3 V 300 -20 to 85 -40 to 150 mW C C ELECTRICAL CHARACTERISTICS 15.2 Recommended operating conditions 15.2 Recommended operating conditions Recommended operating conditions (Vcc = 5 V 10 %, Ta = -20 to 85 C, unless otherwise noted) Limits Unit Symbol Parameter Typ. Min. Max. 4.5 5.5 5.0 f(XIN) :Operating Power source voltage Vcc V 2.7 5.5 f(XIN) :Stopped, f(XCIN) = 32.768 kHz Analog power source voltage Vcc AVcc V Power source voltage 0 Vss V Analog power source voltage 0 AVss V P00-P07, P30-P33, P40-P47, High-level input voltage P50-P57, P60-P67, P70-P77, 0.8 Vcc Vcc VIH V P80-P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3) High-level input voltage P10-P17, P20-P27 0.8 Vcc Vcc VIH V (in single-chip mode) P10-P17, P20-P27 High-level input voltage (in memory expansion mode and 0.5 Vcc Vcc VIH V microprocessor mode) P00-P07, P30-P33, P40-P47, Low-level input voltage P50-P57, P60-P67, P70-P77, 0 0.2 Vcc VIL V P80-P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3) Low-level input voltage P10-P17, P20-P27 0 0.2 Vcc VIL V (in single-chip mode) P10-P17, P20-P27 Low-level input voltage 0 (in memory expansion mode and 0.16 Vcc VIL V microprocessor mode) P00-P07, P10-P17, P20-P27, High-level peak output current P30-P33, P40-P47, P50-P57, -10 IOH (peak) mA P60-P67, P70-P77, P80-P87 High-level average output current P00-P07, P10-P17, P20-P27, P30-P33, P40-P47, P50-P57, -5 IOH (avg) mA P60-P67, P70-P77, P80-P87 P00-P07, P10-P17, P20-P27, Low-level peak output current P30-P33, P40-P43, P54-P57, 10 IOL (peak) mA P60-P67, P70-P77, P80-P87 Low-level peak output current P44-P47, P50-P53 20 IOL (peak) mA Low-level average output current P00-P07, P10-P17, P20-P27, P30-P33, P40-P43, P54-P57, 5 IOL (avg) mA P60-P67, P70-P77, P80-P87 Low-level average output current P44-P47, P50-P53 15 IOL (avg) mA 25 f(XIN) MHz Main-clock oscillation frequency (Note 4) 32.768 50 f(XCIN) Sub-clock oscillation frequency kHz Notes 1: Average output current is the average value of a 100 ms interval. 2: The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less. 3: Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = "1." 4: The maximum value of f(XIN) = 12.5 MHz when the main clock division selection bit = "1." 7733 Group User's Manual 15-3 ELECTRICAL CHARACTERISTICS 15.3 Electrical characteristics 15.3 Electrical characteristics Electrical characteristics (Vcc = 5 V, Vss = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Limits Symbol Parameter Measuring conditions Unit Min. Typ. Max. High-level output voltage P00-P07, P10-P17, P20-P27, IOH = -10 mA V VOH 3 P33, P40-P47, P50-P57, P60-P67, P70-P77, P80-P87 High-level output voltage P00-P07, P10-P17, P20-P27, IOH = -400 A V VOH 4.7 P33 High-level output voltage IOH = -10 mA 3.1 V VOH I OH = -400 A 4.8 P30-P32 High-level output voltage IOH = -10 mA 3.4 V VOH I OH = -400 A 4.8 E Low-level output voltage P00-P07, P10-P17, P20-P27, IOL = 10 mA VOL 2 V P33, P40-P43, P54-P57, P60-P67, P70-P75, P80-P87 Low-level output voltage P44-P47, P50-P53 IOL = 20 mA VOL 2 V Low-level output voltage P00-P07, P10-P17, P20-P27, IOL = 2 mA VOL 0.45 V P33 Low-level output voltage IOL = 10 mA 1.9 V VOL I OL = 2 mA 0.43 P30-P32 Low-level output voltage IOL = 10 mA 1.6 V VOL E IOL = 2 mA 0.4 Hysteresis HOLD, RDY, TA0IN-TA4IN, TB0IN-TB2IN, VT+-VT- 1 V INT0-INT2, ADTRG, CTS0, CTS1, CTS2, CLK0, 0.4 CLK1, CLK2, KI0-KI3 RESET VT+-VT- Hysteresis 0.5 V 0.2 XIN VT+-VT- Hysteresis 0.4 V 0.1 XCIN (When external clock is input) VT+-VT- Hysteresis 0.4 V 0.1 High-level input current P00-P07, P10-P17, P20-P27, P30-P33, P40-P47, P50-P57, VI = 5 V 5 A IIH P60-P67, P70-P77, P80-P87, XIN, RESET, CNVss, BYTE Low-level input current P00-P07, P10-P17, P20-P27, P30-P33, P40-P47, P50-P53, -5 A IIL P60, P61, P65- P67, P70-P77, VI = 0 V P80-P87, XIN, RESET, CNVss, BYTE Low-level input current VI = 0 V, P54-P57, P62-P64 -5 A without a pull-up transistor IIL VI = 0 V, -0.25 -0.5 -1.0 mA with a pull-up transistor RAM hold voltage When clock is stopped V 2 VRAM 15-4 7733 Group User's Manual ELECTRICAL CHARACTERISTICS 15.3 Electrical characteristics 15.4 A-D converter characteristics ELECTRICAL CHARACTERISTICS (Vcc= 5 V, Vss = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter Measuring conditions Min. Limits Typ. Max. Unit Vcc = 5 V, f(XIN) = 25 MHz (Square waveform), (f(f2) = 12.5 MHz), 9.5 19 mA f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 5V, f(XIN) = 25 MHz (Square waveform), (f(f2) = 1.5625 MHz), 1.3 2.6 mA f(XCIN) : Stopped, in operating (Note 1) In single-chip Vcc = 5V, mode, output f(XIN) = 25 MHz (Square waveform), 20 A pins are open, 10 f(XCIN) = 32.768 kHz, Power source and the other ICC current when the WIT instruction is executed (Note 2) pins are conVcc = 5 V, nected to Vss. f(XIN) : Stopped, 50 100 A f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 5 V, f(XIN) : Stopped, 5 10 A f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 C, 1 A when clock is stopped Ta = 85 C, 20 A when clock is stopped Notes 1: This is applied when the main clock external input selection bit = "1," the main clock division selection bit = "0," and the signal output disable selection bit = "1." 2: This is applied when the main clock external input selection bit = "1" and the system clock stop selection bit at wait state = "1." 3: This is applied when the CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the X COUT drivability selection bit = "0" and the system clock stop bit at wait state = "1." 15.4 A-D converter characteristics A-D CONVERTER CHARACTERISTICS (Vcc = AVcc = 5 V, Vss = AVss = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz (Note), unless otherwise noted) Limits Symbol Parameter Measuring conditions Unit Min. Typ. Max. -- Resolution VREF = Vcc 10 Bits -- Absolute accuracy VREF = Vcc 3 LSB RLADDER Ladder resistance VREF = Vcc 10 25 k tCONV Conversion time 9.44 s VREF Reference voltage 2 Vcc V VIA Analog input voltage 0 VREF V Note: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 7733 Group User's Manual 15-5 ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices 15.5 Internal peripheral devices Timing requirements (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Timer A input (Count input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) Limits Min. Max. 80 40 40 Parameter TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Unit ns ns ns Timer A input (Gating input in timer mode) Symbol Data formula (Min.) Parameter 8 10 2 f(f2) 4 109 2 f(f2) 4 109 2 f(f2) Limits Min. Max. Unit 9 tc(TA) TAiIN input cycle time (Note 3) tw(TAH) TAiIN input high-level pulse width (Note 3) tw(TAL) TAiIN input low-level pulse width (Note 3) (Note 2) 320 ns (Note 2) 160 ns (Note 2) 160 ns Timer A input (External trigger input in one-shot pulse mode) Symbol Data formula (Min.) Parameter 8 10 2 f(f2) Limits Min. Max. Unit 9 tc(TA) TAiIN input cycle time tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width (Note 2) 320 ns 80 80 ns ns Timer A input (External trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) Parameter TAiIN input high-level pulse width TAiIN input low-level pulse width Limits Min. Max. 80 80 Unit ns ns Timer A input (Up-down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-T ) th(T -UP) IN IN Parameter TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Limits Min. Max. 2000 1000 1000 400 400 Unit ns ns ns ns ns Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 3: The TAi IN input cycle time must be 4 cycles of a count source or more. The TAiIN input high-level pulse width and low-level pulse width must be 2 cycles of a count source or more, respectively. 15-6 7733 Group User's Manual ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices Timer A input (Two-phase pulse input in event counter mode) Symbol tc(TA) Parameter TAjIN input cycle time tsu(TAj TAjIN input setup time tsu(TAj TAjOUT input setup time IN-TAjOUT) OUT-TAjIN) Measuring conditions f(XIN) = 8 MHz f(XIN) = 16 MHz f(XIN) = 25 MHz f(XIN) = 8 MHz f(XIN) = 16 MHz f(XIN) = 25 MHz f(XIN) = 8 MHz f(XIN) = 16 MHz f(XIN) = 25 MHz Limits Min. Max. 800 800 800 500 250 200 500 250 200 Unit ns ns ns ns ns ns ns ns ns Note: This is applied when the main clock division selection bit = "0." 7733 Group User's Manual 15-7 ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices Internal peripheral devices Count input in event counter mode Gating input in timer mode External trigger input in one-shot pulse mode External trigger input in pulse width modulation mode tc(TA) tw(TAH) TAiIN input tw(TAL) Up-down input and count input in event counter mode tc(UP) tw(UPH) TAiOUT input (Up-down input) tw(UPL) TAiOUT input (Up-down input) TAiIN input (When fall count is selected) th(TIN-UP) tsu(UP-TIN) TAiIN input (When rise count is selected) Two-phase pulse input in event counter mode tc(TA) TAjIN input tsu(TAjIN-TAjOUT) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAjOUT input tsu(TAjOUT-TAjIN) Measuring conditions *VCC = 5 V 10 % *Input timing voltage : V IL = 1.0 V, VIH = 4.0 V 15-8 7733 Group User's Manual ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices Timer B input (Count input in event counter mode) tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Limits Min. Max. 80 40 40 160 80 80 Parameter Symbol TBiIN input cycle time (One edge count) TBiIN input high-level pulse width (One edge count) TBiIN input low-level pulse width (One edge count) TBiIN input cycle time (Both edges count) TBiIN input high-level pulse width (Both edges count) TBiIN input low-level pulse width (Both edges count) Unit ns ns ns ns ns ns Timer B input (Pulse period measurement mode) Symbol Parameter Data formula (Min.) tc(TB) TBiIN input cycle time (Note 1) tw(TBH) TBiIN input high-level pulse width (Note 1) tw(TBL) TBiIN input low-level pulse width (Note 1) 8 109 2 f(f2) 4 109 2 f(f2) 4 109 2 f(f2) Limits Min. Max. Unit (Note 2) 320 ns (Note 2) 160 ns (Note 2) 160 ns Timer B input (Pulse width measurement mode) Symbol Data formula (Min.) Parameter 8 10 2 f(f2) 4 109 2 f(f2) 4 109 2 f(f2) 9 tc(TB) TBiIN input cycle time tw(TBH) TBiIN input high-level pulse width tw(TBL) TBiIN input low-level pulse width Limits Min. Max. Unit (Note 2) 320 ns (Note 2) 160 ns (Note 2) 160 ns A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (Minimum allowable trigger) ADTRG input low-level pulse width Limits Min. Max. 1000 125 Unit ns ns Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Parameter CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time Limits Min. Max. 200 100 100 80 0 30 90 Unit ns ns ns ns ns ns ns Notes 1: The TBiIN input cycle time must be 4 cycles of a count source or more. The TBiIN input high-level pulse width and low-level pulse width must be 2 cycles of a count source or more, respectively. 2: f(f2) represents the clock f 2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 7733 Group User's Manual 15-9 ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices ____ __ External interrupt INTi input, Key input interrupt KI i input Symbol tw(INH) tw(INL) tw(KIL) Limits Min. Max. 250 250 250 Parameter INTi input high-level pulse width INTi input low-level pulse width KIi input low-level pulse width Internal peripheral devices tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi input tw(CKL) th(C-Q) TxDi output td(C-Q) tsu(D-C) th(C-D) RxDi input tw(INL) INTi input KIi input tw(INH) tw(KIL) Measuring conditions * VCC = 5 V 10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 15-10 7733 Group User's Manual Unit ns ns ns ELECTRICAL CHARACTERISTICS 15.5 Internal peripheral devices 15.6 Ready and Hold Timing requirements (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Symbol tsu(RDY- ) tsu(HOLD- ) th( -RDY) th( -HOLD) 1 1 1 1 Limits Min. Max. 55 55 0 0 Parameter RDY input setup time HOLD input setup time RDY input hold time HOLD input hold time Unit ns ns ns ns Note: This is applied when the main clock division selection bit = "0" and f(f2) = 12.5 MHz. Switching characteristics (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz, unless otherwise noted) Parameter Symbol td( -HLDA) 1 HLDA output delay time Conditions Fig. 15.11.1 7733 Group User's Manual Limits Min. Max. 50 Unit ns 15-11 ELECTRICAL CHARACTERISTICS 15.6 Ready and Hold Ready With no wait 1 E output RDY input tsu(RDY- 1) th( 1-RDY) With wait 1 E output RDY input tsu(RDY- 1) th( 1-RDY) Hold 1 tsu(HOLD- 1) th( 1-HOLD) HOLD input td( 1-HLDA) HLDA output Measuring conditions * VCC = 5 V 10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 15-12 7733 Group User's Manual td( 1-HLDA) ELECTRICAL CHARACTERISTICS 15.7 Single-chip mode 15.7 Single-chip mode Timing requirements (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Symbol Parameter Unit Min. Max. External clock input cycle time (Note 2) ns tc 40 External clock input high-level pulse width (Note 3) ns tw(H) 15 External clock input low-level pulse width (Note 3) ns tw(L) 15 External clock rise time ns tr 8 External clock fall time ns tf 8 Port P0 input setup time ns tsu(P0D-E) 60 Port P1 input setup time ns tsu(P1D-E) 60 Port P2 input setup time ns tsu(P2D-E) 60 Port P3 input setup time ns tsu(P3D-E) 60 Port P4 input setup time ns tsu(P4D-E) 60 Port P5 input setup time ns tsu(P5D-E) 60 Port P6 input setup time ns tsu(P6D-E) 60 tsu(P7D-E) Port P7 input setup time ns 60 tsu(P8D-E) Port P8 input setup time ns 60 th(E-P0D) Port P0 input hold time ns 0 ns th(E-P1D) Port P1 input hold time 0 ns th(E-P2D) Port P2 input hold time 0 ns th(E-P3D) Port P3 input hold time 0 ns th(E-P4D) Port P4 input hold time 0 ns th(E-P5D) Port P5 input hold time 0 ns th(E-P6D) Port P6 input hold time 0 ns th(E-P7D) Port P7 input hold time 0 ns Port P8 input hold time th(E-P8D) 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 80 ns. 3: When the main clock division selection bit = "1," values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) Limits Symbol Parameter Conditions Min. Max. Unit td(E-P0Q) Port P0 data output delay time ns 80 td(E-P1Q) Port P1 data output delay time ns 80 td(E-P2Q) Port P2 data output delay time ns 80 td(E-P3Q) Port P3 data output delay time ns 80 Fig. 15.11.1 td(E-P4Q) Port P4 data output delay time ns 80 td(E-P5Q) Port P5 data output delay time ns 80 td(E-P6Q) Port P6 data output delay time ns 80 td(E-P7Q) Port P7 data output delay time ns 80 td(E-P8Q) Port P8 data output delay time ns 80 Note: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 7733 Group User's Manual 15-13 ELECTRICAL CHARACTERISTICS 15.7 Single-chip mode Single-chip mode tf tr tc tW(H) tW(L) XIN E td(E-P0Q) Port P0 output th(E-P0D) tsu(P0D-E) Port P0 input td(E-P1Q) Port P1 output th(E-P1D) tsu(P1D-E) Port P1 input td(E-P2Q) Port P2 output th(E-P2D) tsu(P2D-E) Port P2 input td(E-P3Q) Port P3 output th(E-P3D) tsu(P3D-E) Port P3 input td(E-P4Q) Port P4 output th(E-P4D) tsu(P4D-E) Port P4 input td(E-P5Q) Port P5 output th(E-P5D) tsu(P5D-E) Port P5 input td(E-P6Q) Port P6 output th(E-P6D) tsu(P6D-E) Port P6 input td(E-P7Q) Port P7 output tsu(P7D-E) th(E-P7D) Port P7 input td(E-P8Q) Port P8 output tsu(P8D-E) Port P8 input Measuring conditions *VCC = 5 V 10 % *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 15-14 7733 Group User's Manual th(E-P8D) ELECTRICAL CHARACTERISTICS 15.8 Memory expansion mode and Microprocessor mode : with no wait 15.8 Memory expansion mode and Microprocessor mode : with no wait Timing requirements (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Min. Max. Unit External clock input cycle time (Note 2) tc ns 40 External clock input high-level pulse width (Note 3) tw(H) ns 15 External clock input low-level pulse width (Note 3) tw(L) ns 15 External clock rise time tr ns 8 External clock fall time tf ns 8 Data input setup time tsu(D-E) ns 32 Data input hold time th(E-D) ns 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 80 ns. 3: When the main clock division selection bit = "1," values of tw (H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) Symbol Parameter td(An-E) Address output delay time td(A-E) Address output delay time th(E-An) Address hold time tw(ALE) ALE pulse width tsu(A-ALE) Address output setup time th(ALE-A) Conditions Data formula (Min.) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) Limits Min. Max. Unit - 28 12 ns - 28 12 ns - 22 18 ns - 18 22 ns - 35 5 ns Address hold time 9 ns td(ALE-E) ALE output delay time 4 ns td(E-DQ) Data output delay time th(E-DQ) Data hold time tw(EL) E pulse width tpxz(E-DZ) Floating start delay time tpzx(E-DZ) Floating release delay time td(BHE-E) BHE output delay time td(R/W-E) R/W output delay time th(E-BHE) BHE hold time th(E-R/W) R/W hold time td(E- 1) 1 output delay time 45 Fig. 15.11.1 1 10 2 f(f2) 2 109 2 f(f2) 9 - 22 18 ns - 30 50 ns 5 1 10 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 9 ns ns - 20 20 ns - 28 12 ns - 28 12 ns - 22 18 ns - 22 18 ns 0 18 ns Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: f(f2) represents the clock f 2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 7733 Group User's Manual 15-15 ELECTRICAL CHARACTERISTICS 15.8 Memory expansion mode and Microprocessor mode : with no wait Memory expansion mode and Microprocessor mode : With no wait (Wait bit = "1") (Write) (Read) tr tw(L) tf tw(H) tr tc tw(L) tf tc tw(H) XIN 1 td(E-1) td(E-1) tw(EL) E td(An-E) Address output A0-A7 A8-A15 (BYTE = "H") th(E-An) th(ALE-A) Address td(A-E) td(E-1) tw(EL) td(An-E) Address Address/Data output A16/D0-A23/D7, A8/D8-A15/D15 (BYTE = "L") Data input D8-D15 (BYTE = "L"), D0-D7 (BYTE = "H") td(E-1) th(E-An) Address th(E-DQ) Data tpxz(E-DZ) tpzx(E-DZ) Address td(E-DQ) tsu(D-E) th(E-D) tsu(A-ALE) tw(ALE) tw(ALE) td(ALE-E) td(ALE-E) ALE output td(BHE-E) th(E-BHE) td(BHE-E) th(E-BHE) BHE output td(R/W-E) th(E-R/W) td(R/W-E) th(E-R/W) R/W output td(E-PiQ) Port Pi output (i = 4-8) tsu(PiD-E) Port Pi input (i = 4-8) Measuring conditions ( 1, E, Ports P0-P3) *VCC = 5 V 10 % *VCC = 5 V 10 % *Output timing voltage *Port P1, P2 input 15-16 Measuring conditions (Ports P4-P8) : VOL = 0.8 V, VOH = 2.0 V *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V : VIL = 0.8 V, VIH = 2.5 V *Output timing voltage : V OL = 0.8 V, VOH = 2.0 V 7733 Group User's Manual th(E-PiD) ELECTRICAL CHARACTERISTICS 15.9 Memory expansion mode and Microprocessor mode : with wait 1 15.9 Memory expansion mode and Microprocessor mode : with wait 1 Timing requirements (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Min. Max. Unit External clock input cycle time (Note 2) tc ns 40 External clock input high-level pulse width (Note 3) tw(H) ns 15 External clock input low-level pulse width (Note 3) tw(L) ns 15 External clock rise time tr ns 8 External clock fall time tf ns 8 Data input setup time tsu(D-E) ns 32 Data input hold time th(E-D) ns 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 80 ns. 3: When the main clock division selection bit = "1," values of tw (H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) Symbol Parameter td(An-E) Address output delay time td(A-E) Address output delay time th(E-An) Address hold time tw(ALE) ALE pulse width tsu(A-ALE) Address output setup time th(ALE-A) Conditions Data formula (Min.) 1 10 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 9 Limits Min. Max. Unit - 28 12 ns - 28 12 ns - 22 18 ns - 18 22 ns - 35 5 ns Address hold time 9 ns td(ALE-E) ALE output delay time 4 ns td(E-DQ) Data output delay time th(E-DQ) Data hold time tw(EL) E pulse width tpxz(E-DZ) Floating start delay time tpzx(E-DZ) Floating release delay time td(BHE-E) BHE output delay time td(R/W-E) R/W output delay time th(E-BHE) BHE hold time th(E-R/W) R/W hold time td(E- 1) 1 output delay time 45 Fig. 15.11.1 1 10 2 f(f2) 4 109 2 f(f2) 9 - 22 18 ns - 30 130 ns 5 1 10 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 9 ns ns - 20 20 ns - 28 12 ns - 28 12 ns - 22 18 ns - 22 18 ns 0 18 ns Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: f(f2) represents the clock f 2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 7733 Group User's Manual 15-17 ELECTRICAL CHARACTERISTICS 15.9 Memory expansion mode and Microprocessor mode : with wait 1 Memory expansion mode and Microprocessor mode : When external memory area is accessed with wait 1 (Wait bit = "0" and Wait selection bit = "1") (Write) (Read) tw(L) tw(H) tf tr tc tw(L) tw(H) tr tf tc XIN 1 td(E-1) E td(An-E) Address output A0-A7, A8-A15 (BYTE = "H") Address/Data output A16/D0-A23/D7, A8/D8-A15/D15 (BYTE = "L") td(E-1) td(E-1) td(E-1) tw(EL) tw(EL) th(E-An) td(An-E) Address th(ALE-A) Address tsu(A-ALE) th(E-An) Address th(E-DQ) tpxz(E-DZ) Data td(E-DQ) tsu(D-E) Data input D8-D15 (BYTE = "L") D0-D7 (BYTE = "H") tpzx(E-DZ) Address td(A-E) th(E-D) td(ALE-E) tw(ALE) td(ALE-E) tw(ALE) ALE output td(BHE-E) th(E- BHE) td(BHE-E) th(E- BHE) BHE output td(R/W-E) th(E- R/W) td(R/W-E) th(E- R/W) R/W output td(E-PiQ) Port Pi output (i = 4-8) tsu(PiD-E) Port Pi input (i = 4-8) Measuring conditions ( 1, Measuring conditions (Ports P4-P8) E, Ports P0-P3) * VCC = 5 V 10 % * VCC = 5 V 10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V : VIL = 0.8 V, VIH = 2.5 V * Ports P1, P2 input * Input timing voltage 15-18 th(E-PiD) : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 7733 Group User's Manual ELECTRICAL CHARACTERISTICS 15.10 Memory expansion mode and Microprocessor mode : with wait 0 15.10 Memory expansion mode and Microprocessor mode : with wait 0 Timing requirements (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Min. Max. Unit External clock input cycle time (Note 2) tc ns 40 External clock input high-level pulse width (Note 3) tw(H) 15 ns External clock input low-level pulse width (Note 3) tw(L) 15 ns External clock rise time tr ns 8 External clock fall time tf ns 8 Data input setup time tsu(D-E) 32 ns Data input hold time th(E-D) ns 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 80 ns. 3: When the main clock division selection bit = "1," values of tw (H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) Symbol Parameter td(An-E) Address output delay time td(A-E) Address output delay time th(E-An) Address hold time tw(ALE) ALE pulse width tsu(A-ALE) Address output setup time th(ALE-A) Address hold time td(ALE-E) ALE output delay time td(E-DQ) Data output delay time th(E-DQ) Data hold time tw(EL) E pulse width tpxz(E-DZ) Floating start delay time tpzx(E-DZ) Floating release delay time td(BHE-E) BHE output delay time td(R/W-E) R/W output delay time th(E-BHE) BHE hold time th(E-R/W) R/W hold time td(E- 1) 1 output delay time Conditions Data formula (Min.) 3 10 2 f(f2) 3 109 2 f(f2) 1 109 2 f(f2) 2 109 2 f(f2) 2 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 9 Limits Min. Max. - 33 87 ns - 45 75 ns - 22 18 ns - 23 57 ns - 35 45 ns - 25 15 ns - 30 10 ns 45 Fig. 15.11.1 1 10 2 f(f2) 4 109 2 f(f2) 9 1 10 2 f(f2) 3 109 2 f(f2) 3 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) ns - 22 18 ns - 30 130 ns 5 9 Unit ns - 20 20 ns - 33 87 ns - 33 87 ns - 22 18 ns - 22 18 ns 0 18 ns Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: f(f2) represents the clock f 2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 7733 Group User's Manual 15-19 ELECTRICAL CHARACTERISTICS 15.10 Memory expansion mode and Microprocessor mode : with wait 0 Memory expansion mode and Microprocessor mode : When external memory area is accessed with wait 0 (Wait bit = "0" and Wait selection bit = "0") <Write> <R ead> tw(L) tw(H) tf tr tw (L) tc tw (H ) tf tr tc XIN 1 td(E-1) td(E-1) td(E- td(E- 1) tw (EL) 1) tw(EL) E td(An-E) Address output A0-A7, A8-A15 (BYTE = "H") Address/Data output A16/D0-A23/D7, A8/D8-A15/D15 (BYTE = "L") th(E-An) td(An-E) Address Address th(ALE-A) Address tsu(A-ALE) th(E-DQ) Data tw(ALE) tpxz( E-D Z) tpzx( E-D Z) tsu( D-E) th(E-D ) Address td(E-DQ) td(A-E) Data input D8-D15 (BYTE = "L") D0-D7 (BYTE = "H") th(E-An) tw (ALE) td(ALE-E) td(ALE-E) ALE output td(BHE-E) th(E-BHE) td(BH E-E) th(E-R/W) td(R /W-E) th(E-BH E) BHE output td(R/W-E) th(E-R /W ) R/W output td(E-PiQ) Port Pi output (i = 4-8) tsu(PiD-E) Port Pi input (i = 4-8) Measuring conditions ( 1, Measuring conditions (Ports P4-P8) E, Ports P0-P3) * VCC = 5 V 10 % * VCC = 5 V 10 % * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V * Input timing voltage * Ports P1, P2 input 15-20 : VIL = 0.8 V, VIH = 2.5 V : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 7733 Group User's Manual th(E-PiD) ELECTRICAL CHARACTERISTICS __ 15.11 Measuring circuit for ports P0 to P8 and pins 1 and E __ 15.11 Measuring circuit for ports P0 to P8 and pins 1 and E P0 P1 P2 P3 P4 P5 P6 P7 P8 50 pF 1 E __ Fig. 15.11.1 Measuring circuit for ports P0 to P8 and pins 1 and E 7733 Group User's Manual 15-21 ELECTRICAL CHARACTERISTICS __ 15.11 Measuring circuit for ports P0 to P8 and pins 1 and E MEMO 15-22 7733 Group User's Manual CHAPTER 16 STANDARD CHARACTERISTICS 16.1 Standard characteristics STANDARD CHARACTERISTICS 16.1 Standard characteristics 16.1 Standard characteristics Standard characteristics described below are characteristic examples of the M37733MHBXXXFP and are not guaranteed. For each parameter's limits, refer to chapter "15. ELECTRICAL CHARACTERISTICS." 16.1.1 Programmable I/O port (CMOS output) standard characteristics: P0 to P3, P4 0 to P4 3, P5 4 to P5 7 , P6, P7, and P8 (1) P-channel I OH-VOH characteristics Power source voltage V CC = 5 V P channel IOH [ mA ] 50.0 40.0 30.0 Ta = 25C 20.0 Ta = 85C 10.0 0 1.0 2.0 3.0 4.0 5.0 VOH [ V ] (2) N-channel IOL-VOL characteristics Power source voltage V CC = 5 V N channel 50.0 IOL [ mA ] 40.0 30.0 Ta = 25C 20.0 Ta = 85C 10.0 0 1.0 2.0 3.0 VOL [ V ] 16-2 7733 Group User's Manual 4.0 5.0 STANDARD CHARACTERISTICS 16.1 Standard characteristics 16.1.2 Programmable I/O port (CMOS output) standard characteristics: P4 4 to P4 7 and P5 0 to P5 3 (1) P-channel I OH-V OH characteristics Power source voltage V CC = 5 V P channel IOH [ mA ] 50.0 40.0 30.0 Ta = 25C 20.0 Ta = 85C 10.0 0 1.0 2.0 3.0 4.0 5.0 VOH [ V ] (2) N-channel I OL-V OL characteristics Power source voltage V CC = 5 V N channel 50.0 Ta = 25C IOL [ mA ] 40.0 30.0 Ta = 85C 20.0 10.0 0 1.0 2.0 3.0 4.0 5.0 VOL [ V ] 7733 Group User's Manual 16-3 STANDARD CHARACTERISTICS 16.1 Standard characteristics 16.1.3 Icc-f(XIN) standard characteristics (1) Icc-f(XIN ) characteristics on operating and at reset * Measurement condition Vcc = 5V,Ta = 25C, f(XIN): square waveform input, single-chip mode * Register setting condition Oscillation circuit control register 1 = "0216" (Main clock is input from the external.) 14 12 On operating (CPU + peripheral devices) Icc [mA] 10 8 6 On operating (CPU) 4 2 0 0 4 8 12 16 20 24 28 f(XIN) [MHz] (2) Icc-f(XIN) characteristics in wait mode * Measurement condition Vcc = 5V,Ta = 25C, f(XIN): square waveform input, single-chip mode * Register setting condition Oscillation circuit control register 0 = "2016" (In the wait mode, clocks f2 to f512 are stopped.) Oscillation circuit control register 1 = "0216" (Main clock is input from the external.) or "0016" (Main-clock oscillation circuit is operating by itself) 3 2.5 CC1 = 0 Icc [mA] 2 1.5 1 0.5 CC1 = 1 0 0 4 8 12 16 20 24 28 f(XIN) [MHz] CC1: Main clock external input selection bit (b1 of the oscillation circuit control register 1) 16-4 7733 Group User's Manual STANDARD CHARACTERISTICS 16.1 Standard characteristics 16.1.4 A-D converter standard characteristics The lower lines of the graph indicate the absolute precision errors. These are expressed as the deviation from the ideal value when the output code changes. For example, the change in output code from "0E16" to "0F16" should occur at 72.5 mV, but the measured value is 0.6 mV. Accordingly, the measured point of change is 72.5 + 0.6 = 73.1 mV. The upper lines of the graph indicate the input voltage width for which the output code is constant. For example, the measured input voltage width for which the output code is "0F16" is 4.7 mV. Accordingly, the differential non-linear error is 4.7 - 5.0 = -0.3 mV (-0.06LSB). [Measurement condition] * V CC = AV CC = 5 V, * V REF = 5.12 V, * f(X IN) = 25 MHz, * Ta = 25 C 7733 Group User's Manual 16-5 STANDARD CHARACTERISTICS 16.1 Standard characteristics 16-6 7733 Group User's Manual CHAPTER 17 APPLICATIONS 17.1 17.2 17.3 17.4 17.5 Memory expansion Serial I/O Watchdog timer Power saving Timer B APPLICATIONS 17.1 Memory expansion Some application examples are described below. Applications shown here are just examples. Modify the desired application to suit the user's need and make sufficient evaluation before actually using it. 17.1 Memory expansion Memory * I/O expansion examples are described below. * For functions and operations of pins used in memory * I/O expansion, refer to chapter "12. CONNECTING EXTERNAL DEVICES." * For timing characteristics, refer to chapter "15. ELECTRICAL CHARACTERISTICS." * For timing characteristics and applications of the low voltage version, refer to chapter "18. LOW VOLTAGE VERSION." 17.1.1 Memory expansion model Memory expansion to the external is enabled in the memory expansion or microprocessor mode. In the 7733 Group, the desired memory expansion model can be selected from four models listed in Table 17.1.1. This selection depends on the level of the external data bus width selection signal (BYTE). (1) Minimum model The external data bus is 8 bits wide and the accessible area can be expanded up to 64 Kbytes. No external address latch is necessary, so this model gives priority to cost and is most suitable when connecting a memory of which data bus is 8 bits wide. (2) Medium model A The external data bus is 8 bits wide and the accessible area can be expanded up to 16 Mbytes. The high-order 8 bits of the external address bus (A23 to A 16) are multiplexed with the external data bus. Therefore, one n-bit (n 8) address latch is necessary in order to latch n bits of address in A23 to A 16. (3) Medium model B The external data bus is 16 bits wide and the accessible area can be expanded up to 64 Kbytes. This model gives priority to speed. The middle-order 8 bits of the external address bus (A 15 to A8) are multiplexed with the external data bus. Therefore, one 8-bit address latch is necessary in order to latch A15 to A 8 . (4) Maximum model The external data bus is 16 bits wide and the accessible area can be expanded up to 16 Mbytes. The high- and middle- order 16 bits of the external address bus (A 23 to A8) are multiplexed with the external data bus. Therefore, both of the following latches are necessary: * One 8-bit address latch used for latching A15 to A 8 * One n-bit (n 8) address latch used for latching n bits of address in A 23 to A 16 17-2 7733 Group User's Manual APPLICATIONS 17.1 Memory expansion Table 17.1.1 Memory expansion models Accessible area External data bus 64 Kbytes (Max.) 16 Mbytes (Max.) 7733 Group BYTE 7733 Group 16 BYTE A0 to A15 P0 8 bits wide P1 P2 P1 BYTE = "H" 8 Minimum model 7733 Group 16 Latch ALE 8 BYTE 8 DQ E 16 D 0 to D15 BHE Memory expansion model Medium model B D0 to D7 Memory expansion model Medium model A P0 A0 to A 15 P0 BYTE = "L" n D Q E 7733 Group BYTE P2 Latch ALE Memory expansion model P1 A0 to A15+n D0 to D7 P2 16 bits wide 16+n P0 16+n Latch P1 DQ E P2 DQ E ALE Latch A0 to A15+n 8 n 16 D0 to D 15 BHE Memory expansion model Maximum model For functions and operations of pins used in memory expansion, refer to chapter "12. CONNECTING EXTERNAL DEVICES." For timing characteristics, refer to chapter "15. ELECTRICAL CHARACTERISTICS." In memory expansion, the address bus can be expanded up to 24 bits wide. Accordingly, be sure to strengthen the 7733 Group's Vss line on the system. (Refer to section "Appendix 8.Countermeasure examples against noise.") 7733 Group User's Manual 17-3 APPLICATIONS 17.1 Memory expansion 17.1.2 Calculation ways for timing When expanding memory, use a memory of which specifications satisfy the following timing requirements: address access time (t a(AD)) and data setup time for writing data (tsu(D)). Calculation ways for t a(AD) and tsu(D) are described below. Address access time of external memory [t a(AD)] t a(AD) = t d(An/A-E) + t w(EL) - t su(D-E) - (address decode time1 + address latch delay time2) t d(An/A-E) : t d(An-E) or t d(A-E) address decode time1: time necessary for validating a chip select signal after an address is decoded address latch delay time2 : delay time necesarry for latching an address (This is not necessary on the minimum model.) Data setup time of external memory for writing data [t su(D)] t su(D) = tw(EL) - t d(E-D) Table 17.1.2 lists the calculation formulas and constants for each parameter in the above formulas. Figure 17.1.1 shows bus timing diagrams. Figure 17.1.2 shows the relationship between ta(AD) and 2*f(f2). Figure 17.1.3 shows the relationship between t su(D) and 2*f(f 2). Table 17.1.2 Calculation formulas and constants for each parameter (Unit: ns) Software wait Wait bit Wait selection bit td(A-E) td(An-E) tw(EL) No wait 1 0 or 1 Wait 0 0 0 Wait 1 0 1 3 10 9 - 45 2 *f(f2) 1 10 9 - 28 2 *f(f2) 2 10 9 - 30 2 *f(f2) 4 10 9 - 30 2 *f(f2) 32 45 tsu(D-E) td(E-DQ) Wait bit: Bit 2 at address 5E 16 Wait selection bit: Bit 0 at address 5F 16 Note: The above is applied when the system clock selection bit (bit 3 at address 6C 16 ) = "0." 17-4 7733 Group User's Manual APPLICATIONS 17.1 Memory expansion When BYTE = "H" (External data bus = 8 bits wide) E tw(EL) tw(EL) ALE A0 to A7 Low-order address Low-order address Middle-order address Middle-order address td(An-E) A8 to A15 td(An-E) A16/D0 to A23/D7 High-order address Data td(A-E) ta(AD) R/W High-order address Data td(E-DQ) tsu(D-E) tsu(D) When data is read When data is written When BYTE = "L" (External data bus = 16 bits wide) E tw(EL) tw(EL) ALE A0 to A7 Low-order address Low-order address td(An-E) A8/D8 to A15/D15 A16/D0 to A23/D7 Middle-order address Data td(A-E) tsu(D-E) High-order address Data td(A-E) tsu(D-E) Middle-order address td(E-DQ) High-order address Low-order data td(E-DQ) tsu(D) ta(AD) R/W High-order data When data is read When data is written : Specifications of the 7733 Group (The others are specifications of external memory.) Fig. 17.1.1 Bus timing diagrams 7733 Group User's Manual 17-5 APPLICATIONS 17.1 Memory expansion [ns] 900 893 768 800 Address access time ta(AD) No wait 670 700 624 600 Wait 1 is valid. Wait 0 is valid. 593 535 529 476 465 500 431 410 400 393 364 338 326 285 300 243 210 200 182 160 359 330 294 140 267 124 243 110 222 97 100 304 204 86 281 187 76 261 243 173 160 67 226 211 197 148 137 60 52 20 21 184 173 127 118 110 46 40 35 30 22 23 24 25 0 7 8 9 10 11 12 13 14 15 16 17 18 19 [MHz] External clock input frequency 2*f(f2) Address decode time and address latch delay time are not considered. Fig. 17.1.2 Relationship between ta(AD) and 2* f(f2) [ns] 500 496 Data setup time tsu(D) 425 400 369 No wait Wait 1 or Wait 0 is valid. 325 288 300 258 232 210 210 175 200 191 175 147 125 106 100 91 78 67 58 50 160 42 147 36 135 30 125 115 106 98 91 85 5 25 20 15 11 8 20 21 22 23 24 0 7 8 9 10 11 12 13 14 15 16 17 18 19 External clock input frequency 2*f(f2) Fig. 17.1.3 Relationship between tsu(D) and 2 * f(f2 ) 17-6 7733 Group User's Manual 25 [MHz] APPLICATIONS 17.1 Memory expansion 17.1.3 Points in memory expansion (1) Timing for reading data Figure 17.1.4 shows the timing at which data is read from an external memory. When data is read, the external data bus enters a floating state and reads data from the external memory. The floating state of the external data bus is retained from when an interval of_ tpxz(E-DZ) has _ passed after signal E's falling edge until an interval of tpzx(E-DZ) has passed after signal E's rising edge. Table 17.1.3 lists the value of t pxz(E-DZ) and the calculation formula for tpzx(E-DZ) . Note that the external data bus is multiplexed with the external address bus. Therefore, when reading data, it is necessary to consider timing to avoid collision between data being read-in and an address which is output preceding or following the data. (Refer to "(3) Precautions on memory expansion.") tw(EL) E External memory output enable signal (Read signal) External memory chip select signals OE CE, S tpxz(E-DZ) Address output and data input tpzx(E-DZ) ta(OE) 1 A8/D8 to A15/D15 A16/D0 to A23/D7 Address Address ta(CE), ta(S) 2 ten(OE) tDF, tdis(OE) 3 ten(CE), ten(S) External memory data output Data tsu(D-E) : Specifications of the 7733 Group (The others are specifications of external memory.) 1 This is applied when the external data bus = 16 bits wide (BYTE = "L"). 2 When the external memory's specifications are smaller than tpxz(E-DZ), there is a possibility that the tail of address collides with the head of data. Refer to "(3) Precautions on memory expansion." 3 When the external memory's specifications are greater than tpzx(E-DZ), there is a possibility that the tail of data collides with the head of address. Refer to "(3) Precautions on memory expansion." Fig. 17.1.4 Timing at which data is read from external memory 7733 Group User's Manual 17-7 APPLICATIONS 17.1 Memory expansion Table 17.1.3 Value of t pxz(E-DZ) and calculation formula for t pzx(E-DZ) (Unit: ns) Software wait Wait bit Wait selection bit t pxz(E-DZ) t pzx(E-DZ) No wait 1 0 or 1 Wait 1 0 1 5 1 10 9 - 20 2 *f(f2) Wait 0 0 0 Wait bit: Bit 2 at address 5E 16 Wait selection bit: Bit 0 at address 5F 16 Note: The above is applied when the system clock selection bit (bit 3 at address 6C 16 ) = "0." 17-8 7733 Group User's Manual APPLICATIONS 17.1 Memory expansion (2) Timing for writing data Figure 17.1.5 shows the timing for writing data to an external memory. _ When data is written, the data is output from when an interval of_ t d(E-DQ) has passed after signal E's falling edge until an interval of th(E-DQ) has passed after signal E's rising edge. Table 17.1.4 lists the value of t d(E-DQ ) and the calculation formula for th( E-DQ). Make sure that the data output timing for writing data satisfies the following specifications of the external memory: data setup time (t su( D)) and data hold time (t h( D)) for writing data. tw(EL) E External memory write signals W, WE External memory chip select signals CE, S td(E-DQ) th(E-DQ) Address and data output A8/D8 to A15/D15 A16/D0 to A23/D7 Address Data Address th(D) tsu(D) : Specifications of the 7733 Group This is applied when the external data bus = 16 bits wide (BYTE = "L" ). (The others are specifications of external memory.) Fig. 17.1.5 Timing at which data is written to external memory Table 17.1.4 Value of t d(E-DQ) and calculation formula for t h(E-DQ) (Unit: ns) No wait Software wait Wait 1 1 Wait bit 0 0 or 1 Wait selection bit 1 t d(E-DQ) t h(E-DQ) Wait 0 0 0 45 1 10 9 - 22 2*f(f2) Wait bit: Bit 2 at address 5E16 Wait selection bit: Bit 0 at address 5F 16 Note: The above is applied when the system clock selection bit (bit 3 at address 6C16 ) = "0." 7733 Group User's Manual 17-9 APPLICATIONS 17.1 Memory expansion (3) Precautions on memory expansion When specifications of the 7733 Group do not match those of an external memory as described in the following to , some considerations about the circuit are necessary: When using an external memory which requires a long address access time (ta(AD)) _ When using an external memory which outputs data within an interval of tpxz(E-DZ) after signal E's falling edge. When _ using an external memory which outputs data for more than an interval of t pzx(E-DZ) after signal E's rising edge When using an external memory which requires a long address access time (ta (AD) ) When an external memory requires a long address access time (ta(AD)) which does not satisfy the 7733 Group's t su(D-E), try to carry out the following: Lower 2 *f(f 2) Select "Software wait is inserted." (Refer to section "12.2 Software wait.") Use the ready function. (Refer to section "12.3 Ready function.") Figure 17.1.6 shows a ready generating circuit example (with no wait). Figure 17.1.7 shows a ready generating circuit example (with wait 1). Note that the ready function is also valid for the internal area. Therefore, in Figures 17.1.6 and 17.1.7, ___ areas where the ready function is valid are specified by using the chip select signal ( CS 2 ) which is externally generated. 17-10 7733 Group User's Manual APPLICATIONS 17.1 Memory expansion M37733MHBXXXFP A8 to A23 (D0 to D15) Data bus Address Address latch circuit CS1 decode CS2 circuit Address bus A0 to A7 RDY AC32 AC74 E AC32 D Q T 1 Wait generated by the ready function is inserted only to an area where accessed by signal CS2. AC04 Circuit conditions: f (XIN) 15.7 MHz, no wait 1= td(E- 1) f(XCIN) f(XIN) f(XIN) f(XIN) or 8 , 16 , 2 , 2 tc 1 1 E CS2 Condition to satisfy the relationship of t su(RDY- 55 ns in the left timing chart is tc 63.5 ns. Q Accordingly, when f(X IN) 15.7 MHz, this example satisfies the relationship of t su(RDY- RDY tsu(RDYPropagation delay time of AC32 (Max.: 8.5 ns) 1) 1) 55 ns. 1) : Wait generated by the ready function Fig. 17.1.6 Ready generating circuit example (with no wait) 7733 Group User's Manual 17-11 APPLICATIONS 17.1 Memory expansion M37733MHBXXXFP A8 to A23 (D0 to D15) Data bus Address Address latch circuit CS1 decode CS2 circuit Address bus A0 to A7 1 to 3 Make sure that the sum of propagation delay time is within RDY E 2 109 - tsu(RDY- 1 ) 2 * f(f2) (when 2 * f(f 2) = 25 MHz, 25 ns). 3 F32 F32 F04 1D 1Q 1T RD 2D 2Q 2T Wait generated by the ready function is inserted only to an area where accessed by signal CS 2. 1 F04 2 1 F74 Circuit conditions: f (XIN) 25 MHz, wait 1 is valid, 1= f(XIN) f(XIN) f(XIN) or 8 , 16 , 2 , f(XCIN) 2 1 1 E 1Q 2Q CS2 RDY tsu(RDY- 1) th( 1-RDY) : Software wait : Wait generated by the ready function Fig. 17.1.7 Ready generating circuit example (with wait 1) 17-12 7733 Group User's Manual APPLICATIONS 17.1 Memory expansion _When using an external memory which outputs data within an interval of tpxz(E-DZ) after signal E's falling edge When there is a possibility that the tail of an address collides with the _head of data because the external memory outputs data within an interval of t pxz(E-DZ) after signal E's falling edge, delay only _ ___ the E's front falling edge.__In this case, the falling edge of the read signal ( OE) for the memory, which is generated from signal E, is delayed. (Refer to Figure 17.1.8.) E External memory output enable signal (Read signal) d OE tpxz(E-DZ) Address output Address External memory data output Address Data ta(OE) ten(OE) : Specifications of 7733 Group (The others are specifications of external memory.) Note: Satisfy the following conditions: * tpxz(E-DZ) ten(OE) +d * When ten(OE) tpxz(E-DZ) (= 5 ns), make sure that signal E's falling edge precedes signal OE's falling edge and an interval of "d" is secured. Fig. 17.1.8 Timing example when data output is delayed 7733 Group User's Manual 17-13 APPLICATIONS 17.1 Memory expansion When using an external memory which outputs data for more than an interval of tpzx(E-DZ) after _ signal E's rising edge When there is a possibility that the tail of data collides with the head of an address because the _ external memory outputs the data for more than an interval of tpzx(E-DZ) after signal E's rising edge, try to carry out the following: By using bus buffers and others, delete the tail of data which is output from the memory. Use a memory which is made by MITSUBISHI ELECTRIC CORPORATION and can be connected without bus buffers. Figures 17.1.9 to 17.1.12 show bus buffer usage examples and the corresponding timing diagrams. Table 17.1.5 lists memories which can be connected without bus buffers (made by MITSUBISHI ELECTRIC CORPORATION). The reason why these memories do not need buffers is that timing parameters _ t DF or tdis(OE) is guaranteed. (Make sure that the read signal rises within 10 ns after signal E's rising edge.) Table 17.1.5 Memories which can be connected without bus buffers (made by MITSUBISHI ELECTRIC CORPORATION) Memory EPROM One time PROM Frash memory SRAM Type M5M27C256AK-85, -10, -12, -15 M5M27C512AK-10, -12, -15 tDF/tdis(OE) (Max.) Usage condition 15 ns (When guaranteed as kit) 2 * f(f2) 20 MHz M5M27C100K-12, -15 M5M27C101K-12, -15 M5M27C102K-12, -15 M5M27C201K, JK-10, -12, -15 M5M27C202K, JK-10, -12, -15 M5M27C256AP, FP, VP, RV-12, -15 M5M27C512AP, FP-15 M5M27C100P-15 M5M27C101P, FP, J, VP, RV-15 M5M27C102P, FP, J, VP, RV-15 M5M27C201P, FP, J, VP, RV-12, -15 M5M27C202P, FP, J, VP, RV-12, -15 M5M28F101P, FP, J, VP, RV-10, -12, -15 M5M28F102FP, J, VP, RV-10, -12, -15 M5M5256CP, FP, KP, VP, RV-55LL, -55XL, -70LL, -70XL, -85LL, -85XL, -10LL, -10XL M5M5278CP, FP, J-20, -20L M5M5278CP, FP, J-25, -25L M5M5278DP, J-12 M5M5278DP, FP, J-15, -15L M5M5278DP, FP, J-20, -20L (Note) 8 ns 10 ns 6 ns 7 ns 8 ns 2 * f(f2) 25 MHz Note: Specifications of the above memories are available if a comment of "tDF/tdis(OE) = 15 ns, microcomputer and kit" is added. 17-14 7733 Group User's Manual APPLICATIONS 17.1 Memory expansion M37733MHBXXXFP CNVSS A1 to A7 Address bus AC573 BYTE D Q LE OE AC573 D Q ALE LE OE F245 2 A8/D8 to A1 5/D 15 A Data bus (odd) B DIR OC F245 2 A16/D0 to A23/D7 A B Data bus (even) DIR OC E BC32 AC04 3 1 RD R/W WO BHE WE A0 XIN XOUT AC32 4 Circuit conditions: Wait 1 is valid, 25 MHz 1= f(XCIN) f(XIN) f(XIN) f(XIN) or , 16 , 2 2 , 8 1 Make sure that the propagation delay time is 12 ns or less. 2, 3 Make sure that the following relationships are satisfied: The sum of output disable time of 2 and propagation delay time of 3 is 20 ns or less. The sum of output enable time of 2 and propagation delay time of 3 is 5 ns or more. 4 Make sure that the propagation delay time is 12 ns or less. Fig. 17.1.9 Bus buffer usage example (1) 7733 Group User's Manual 17-15 APPLICATIONS 17.1 Memory expansion <At reading> 130 (min.) E 20 (min.) 5 (max.) A8/D8 to A 15/D15 A16/D0 to A23/D7 A A BC32 (t PHL) BC32 (t PLH) OC (F245),RD F245 (tPZH/tPZL) Data output A from external memory (F245) F245 (tPHZ/tPLZ) D <At writing> 130 (min.) E 45 (max.) A8/D8 to A 15/D15 A16/D0 to A23/D7 A D A BC32 (t PLH) BC32 (t PHL) OC (F245),WO,WE F245 (tPHL/tPLH) Data output B to external memory (F245) F245 (tPHZ/tPLZ) D (Unit: ns) Fig. 17.1.10 Timing diagram for bus buffer usage example (1) 17-16 7733 Group User's Manual APPLICATIONS 17.1 Memory expansion M37733MHBXXXFP CNVSS A1 to A7 Address bus AC573 BYTE D Q LE OE AC573 D Q LE OE ALE ALS245A2 A8/D8 to A15/D15 A Data bus (odd) B DIR OC ALS245A2 A16/D0 to A23/D7 A Data bus (even) B DIR OC These circuits make the rising edge of the write signal earlier by 1/2 1, so that the write hold time is extended. E AC04 1D1Q 2D 1T 2T 2Q AC74 1 1 AC04 1 RD R/W WO BHE WE A0 XIN XOUT AC32 16 MHz AC32 Circuit conditions: Wait 1 is valid, 1= f(XCIN) f(XIN) f(XIN) f(XIN) or , 16 , 2 2 , 8 1 Make sure that the propagation delay time is 40.5 ns or less. 2 Make sure that the output enable time is 5 ns or more and the output disable time is 42.5 ns or less. Fig. 17.1.11 Bus buffer usage example (2) (when a memory which requires a long data hold time for writing is connected) 7733 Group User's Manual 17-17 APPLICATIONS 17.1 Memory expansion <At reading> 220 (min.) E, OC (ALS245A) 42.5 (min.) 5 (max.) A8/D8 to A15/D15 A16/D0 to A 23/D7 A A AC32 (t PLH) AC32 (t PHL) RD ALS245A (tPZH/tPZL) Data output A from external memory (ALS245A) ALS245A (tPHZ/tPLZ) D <At writing> 1 1 220 (min.) E, OC (ALS245A) 1Q (AC74) AC32 2 (t PHL) AC04 (t PLH)+AC74 (t PLH) 2Q(AC74) AC32 2 (tPLH) AC04 (t PLH)+AC74 (t PHL) WO,WE A8/D8 to A 15/D15 A16/D0 to A23 /D7 Data output B to external memory (ALS245A) 70 (max.) A D ALS245A (tPHL/tPLH) ALS245A (tPHZ/tPLZ) D Write hold time (Unit: ns) Fig. 17.1.12 Timing diagram for bus buffer usage example (2) 17-18 7733 Group User's Manual APPLICATIONS 17.1 Memory expansion 17.1.4 Memory expansion example (1) ROM expansion example on minimum model Figure 17.1.3 shows a ROM expansion example on the minimum model (with a 32-Kbyte ROM, memory expansion mode). Figure 17.1.4 shows the corresponding timing diagram. M37733S4BFP BYTE AC00 A15 M5M27C256AK-10 CE A0 to A14 A0 to A14 D0 to D7 D0 to D7 OE BHE 000016 008016 Open Memory map SFR area Internal RAM area 088016 Not used R/W 800016 E External ROM area (M5M27C256AK) XIN X OUT FFFF 16 25 MHz Circuit conditions: Wait 1 is valid, 1= f(XIN) 2 , f(XIN) f(XIN) 8 , 16 , or f(XCIN) 2 Make sure that the propagation delay time is 10 ns or less. Fig. 17.1.13 ROM expansion example on minimum model 7733 Group User's Manual 17-19 APPLICATIONS 17.1 Memory expansion <At reading> 130 (min.) E, OE 12 (min.) A0 to A14 A 20 (min.) 5 (max.) D0 to D7 (A) (A) CE AC00 (tPHL) AC00 (tPLH) ta(CE) 15 (max.) (Guaranteed as kit.) ta(AD) External ROM data output D ta(OE) tsu(D-E) 32 (Unit: ns) Fig. 17.1.14 Timing diagram for ROM expansion example on minimum model 17-20 7733 Group User's Manual APPLICATIONS 17.1 Memory expansion (2) ROM expansion example on maximum model Figure 17.1.5 shows a ROM expansion example on the maximum model (with a 2-Mbit ROM, microprocessor mode). Figure 17.1.6 shows the corresponding timing diagram. M5M27C202K-10 M37733S4BFP CNVss A1 to A7 BYTE A 8/D 8 to A15/D 15 Address bus ALE D1 to D7 A0 to A 16 D Q A8 to A15 LE AC573 A 16/D0, A17 /D1 A1 to A17 AC573 1 D Q 0000 16 0080 16 A16, A17 LE Data bus D0 to D15 D0 to D 15 OE E 1, 2 Make sure that the propagation delay time is 10 ns or less. Internal RAM area 088016 CE External ROM area AC04 2 (M5M27C202K) R/W XIN Memory map SFR area XOUT 3FFFF 16 25 MHz Circuit conditions: Wait 1 is valid, 1= f(XCIN) f(XIN) f(XIN) f(XIN) or , 16 , 2 2 , 8 Fig. 17.1.15 ROM expansion example on maximum model 7733 Group User's Manual 17-21 APPLICATIONS 17.1 Memory expansion <At reading> 130 (min.) E,OE 12 (min.) A8/D8 to A15/D15 A16/D0 20 (min.) 5 (max.) A A 12 (min.) 18 (max.) R/W ta(AD)+AC573 (tPHL/tPLH) AC04 (tPHL) AC04 (tPLH) CE ta(OE) External ROM data output 15 (max.) (Guaranteed as kit.) D ta(CE) tsu(D-E) 32 (Unit: ns) Fig. 17.1.16 Timing diagram for ROM expansion example on maximum model 17-22 7733 Group User's Manual APPLICATIONS 17.1 Memory expansion (3) ROM and SRAM expansion example on maximum model Figure 17.1.17 shows an expansion example for ROM and SRAM on the maximum model (with two 32-Kbyte ROMs and two 32-Kbyte SRAMs, microprocessor mode). Figure 17.1.18 shows the corresponding timing diagram. M37733S4BFP CNVSS BYTE M5M5256CP-70LL M5M27C256AK-15 Address bus A1 to A7 AC573 2 A8/D8 to A15 /D15 A8 to A15 LE A0 to A14 ALE A1 to A15 D8 to D15 1 AC04 CE CE D Q to A15 S A0 to A14 A0 to A14 A1 S A1 to A15 D8 to D15 A0 to A14 A1 to A15 2 AC573 D Q A16 /D0 A16 D0 LE to D7 D0 to D7 D0 to D7 OE OE Data bus (odd) D0 DQ1 to DQ8 OE W to D7 DQ1 to DQ8 OE W Data bus (even) D1 to D7 AC04 AC32 R/W E 3 RD WE A0 WO BHE XIN XOUT Memory map AC32 0000 16 0080 16 20 MHz Circuit conditions: Wait 1 is valid, 1= f(XIN) 2 , f(XIN) f(XIN) 8 , 16 , or f(XCIN) 2 1, 2 Make sure that the following relationship is satisfied: The sum of propagation delay time of 1 and that of 2 is 90 ns or less. 2 Make sure that the propagation delay time is 10 ns or less. 3 Make sure that the propagation delay time is 15 ns or less. 0880 16 SFR area Internal RAM area External ROM area (M5M27C256AK2) 10000 16 External RAM area (M5M5256CP2) 1FFFF 16 Fig. 17.1.17 Expansion example for ROM and SRAM on maximum model 7733 Group User's Manual 17-23 APPLICATIONS 17.1 Memory expansion <At reading> 170 (min.) E 22 (min.) A1 to A7 A A 5 (max.) A8/D8 to A15/D15 A16/D0 A A 30 (min.) AC573 (tPHL) CE,S AC04 (tPHL) S CE ta(S) AC32 (tPLH) OE AC32 (tPHL) ta(OE) 15 (max.) (Guaranteed as kit.) External memory data output D tsu(D-E) 32 ta(AD),ta(CE) <At writing> 170 (min.) E 22 (min.) A1 to A7 A8/D8 to A15/D15 A16/D0,D1 to D7 A A A D tsu(D) 30 45 (max.) A 23 (min.) AC573 (tPHL)+AC04 (tPHL) S AC32 (tPHL) AC32 (tPLH) WE,WO (Unit: ns) Fig. 17.1.18 Timing diagram for ROM and SRAM expansion example on maximum model 17-24 7733 Group User's Manual APPLICATIONS 17.1 Memory expansion 17.1.5 I/O expansion example (1) Port expansion example where the M66010FP is used Fig. 17.1.19 shows a port expansion example where the M66010FP is used. The frequency of a transmit clock for serial I/O must be 1.923 MHz or less. Serial I/O control in this expansion example is described below. In this expansion example, 8-bit data transmission/reception is performed three times by using UART0, and so ports expand by 24 bits. UART0 is set as follows: Clock synchronous serial I/O mode is selected. Transmission/Reception is enabled. An internal clock is selected. Transfer rate = 1.5625 MHz LSB first is selected. The control procedure is as follows: "L" level is output from port P4 5. (By this signal, the expanded I/O ports of the M66010FP enter a floating state.) "H" level is output from port P4 5. "L" level is output from port P4 4. 24-bit data is transmitted/received using UART0. "H" level is output from port P4 4. Fig. 17.1.20 shows the timing of serial transfer between the M37733MHBXXXFP and M66010FP. 7733 Group User's Manual 17-25 APPLICATIONS 17.1 Memory expansion M37733MHBXXXFP M66010FP TxD0 DI CNVss RxD0 DO BYTE CLK0 CLK P44 CS P45 S RTS0 A0 to A7 Open Vcc A8/D8 to A15/D15 GND A16/D0 to A23/D7 ALE E D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 Expanded I/O ports 1 R/W BHE Circuit conditions: UART0 is used in clock synchronous serial I/O mode. Internal clock is selected. f2 = 1.5625 MHz Transfer clock frequency = 2 (3 + 1) XIN XOUT 25 MHz Fig. 17.1.19 Port expansion example where M66010FP is used 17-26 7733 Group User's Manual CS P44 7733 Group User's Manual D1 D2 Expanded I/O port Expanded I/O port Expanded I/O port DO RX D0 D24 to DI TXD0 CLK0 CLK S P45 DO2 DO3 DO4 DO5 DI2 DI3 DI4 DI5 DI6 DO6 Output structure of expanded I/O ports is N-channel open drain output. DI24 DI2 DI1 DI1 Data of the shift register 1 is output in serial. DO1 Serial data is input to the shift register 2. Data of expanded I/O ports are input to the shift register 1. Expanded I/O ports are released from the floating state. DI7 DO7 DI8 DO8 DI20 DO20 DI22 DO22 DI23 DO23 DI24 DO24 : Pins' names of the 7733 Group. The others are pins' names or operations of the M66010FP. DI21 DO21 Data of the shift register 2 is output to expanded I/O ports. DO24 DO2 DO1 APPLICATIONS 17.1 Memory expansion Fig. 17.1.20 Timing of serial transfer between M37733MHBXXXFP and M66010FP 17-27 APPLICATIONS 17.2 Serial I/O 17.2 Serial I/O Examples for serial I/O are described below: *Examples where the microcomputer is connected with an external device by using serial I/O *Examples where serial data is transmitted and received 17.2.1 Connection examples with external device (Clock synchronous serial I/O mode) (1) Connection with peripheral ICs CLKi CLK CLKi CLK T X Di IN T X Di IN RX Di OUT M37733MHBXXXFP Peripheral IC (OSD controller and so on) M37733MHBXXXFP Fig. 17.2.1 Example where only transmission is performed CLKi CLK TXDi IN RX Di M37733MHBXXXFP Peripheral IC (E 2 PROM and so on) Fig. 17.2.2 Example where transmission/reception is performed Set pin TxD i to N-channel open-drain output. UART0: Data output selection bit ( bit 5 at address 34 16) "1" "1" UART1: Data output selection bit ( bit 5 at address 3C 16) When receiving, be sure to set pin TxD i's output to "H" level. (Pin RxD i is in a floating state.) OUT Peripheral IC (E 2PROM and so on) Fig. 17.2.3 Example where transmission/reception is performed (Connection example with wiredOR) 17-28 7733 Group User's Manual APPLICATIONS 17.2 Serial I/O CLK0 CLK IN Peripheral IC 1 CLKS0 CLK IN Peripheral IC 2 CLKS1 TXD0 M37733MHBXXXFP CLK IN One of three transmit clock output pins, which is selected by software, outputs a transmit clock. Multiple transmit clock output pins can be used only when the following conditions are satisfied: Clock synchronous serial I/O mode is selected. Internal clock is selected. Only transmission is performed with UART0 used. Peripheral IC 3 Fig. 17.2.4 Case where transmission for several peripheral devices is performed with 1-channel serial I/O used (2) Connection with microcomputer CLKi CLK CLKi CLK CTSi Port RTSi Port TXDi IN TXDi IN RXDi OUT RXDi OUT M37733MHBXXXFP Microcomputer M37733MHBXXXFP Microcomputer i = 0 to 2, j = 0 and 1 Note: The RTS output function is not assigned for UART2. i = 0 to 2 Fig. 17.2.5 Case where internal clock is selected Fig. 17.2.6 Case where external clock is selected 7733 Group User's Manual 17-29 APPLICATIONS 17.2 Serial I/O 17.2.2 Examples of transmission for several peripheral ICs (Clock synchronous serial I/O mode) In this example, transmission for three peripheral ICs is performed with UART0 used. (Note that simultaneous transmission for several peripheral ICs is disabled.) (1) Specifications Clock synchronous serial I/O mode is selected. An internal clock is selected. Transfer rate = 2 MHz MSB first is selected. Transmit data is output at the falling edge of the transfer clock. Pin TxD 0's output structure: CMOS output Completion of transmission is determined by checking the transmission register empty flag. CLK0 CLK IN Peripheral IC 1 CLKS 0 CLK IN Peripheral IC 2 CLKS 1 T X D0 M37733MHBXXXFP Fig. 17.2.7 Connection example 17-30 7733 Group User's Manual CLK IN Peripheral IC 3 APPLICATIONS 17.2 Serial I/O (2) Initial settings for related registers b7 b0 0 X X X 0 0 0 1 UART0 transmit/receive mode register (address 30 16) Clock synchronous serial I/O mode Internal clock is selected. Must be fixed to "0." b7 b0 1 0 0 1 X X 0 0 UART0 transmit/receive control register 0 (address 34 16) BRG0 count source: f 2 CTS/RTS function is disabled. Pin TXD0's output structure: CMOS output Transmit data is output at the falling edge of the transfer clock. MSB first b7 b0 0116 UART0 baud rate register (BRG0) (address 31 16) When the system clock (main clock) frequency = 16 MHz, transfer rate = 2 MHz b7 b0 X X X X X 0 X 1 UART0 transmit/receive control register 1 (address 35 16) Transmission is enabled. Reception is disabled. b7 b0 X 0 0 00 UART0 transmission interrupt control register (address 71 16) UART0 transmission interrupt is disabled. b7 b0 X 1 X 1 Port P8 direction register (address 14 16) Pin CLKS1 is in the output mode when not transferring. Pin CLKS0 do the processing of "output when not transferring." ("H" level is output.) b7 b0 X X X 1 Port P8 register (address 12 16) Pin CLKS1 outputs "H" level when not transferring. By this setting, pin CLKS 1 functions as port P8 0 and outputs "H" level when not transferring, in other words, when no clock is output. X: It may be "0" or "1." Fig. 17.2.8 Initial settings for related registers 7733 Group User's Manual 17-31 APPLICATIONS 17.2 Serial I/O (3) Approximate flowchart At first, transmit data 1 is transmitted to peripheral IC1, and then transmit data 2 is transmitted to peripheral IC2. Main routine Serial transmit control register (address 6E 16) UART0 transmission buffer register (address 32 16) 0 "XX01XXXX 2" [Transmit data 1] Transmission buffer empty flag = "1" ? (bit 1 at address 35 16) Transfer clock is output from pin CLK 0. (Data is transmitted to peripheral IC1.) Transmit data is set. Waiting for the start of transmission 1: Transfer is completed. 0 Transmission register empty flag = "1" ? (bit 3 at address 34 16) Waiting for the completion of transmission 1: Transmission is completed. Serial transmit control register (address 6E 16) UART0 transmission buffer register (address 32 16) 0 "XX10XXXX 2" [Transmit data 2] Transmission buffer empty flag = "1" ? (bit 1 at address 35 16) Transfer clock is output from pin CLKS 0. (Data is transmitted to peripheral IC2.) Transmit data is set. Waiting for the start of transmission 1: Transfer is completed. 0 Transmission register empty flag = "1" ? (bit 3 at address 34 16) Waiting for the completion of transmission 1: Transmission is completed. X: It may be "0" or "1." Fig. 17.2.9 Approximate flowchart 17-32 7733 Group User's Manual APPLICATIONS 17.2 Serial I/O 17.2.3 Transmission/Reception example (UART mode, transfer data length = 8 bits) In this example, transmission/reception is performed with UART1 used (transfer data length = 8 bits). (1) Specifications UART mode is selected (transfer data length = 8 bits) An internal clock is selected. Baud rate = 9,600 bps Parity is disabled. 1 stop bit is selected. Pin TxD1 's output structure: CMOS output The sleep mode is invalid. Transmission start is determined by using a UART1 transmission interrupt. Receive data is read out by using a UART1 reception interrupt. RTS1 Port TXD1 IN RXD1 OUT M37733MHBXXXFP Peripheral IC Fig. 17.2.10 Connection example 7733 Group User's Manual 17-33 APPLICATIONS 17.2 Serial I/O (2) Initial settings for related registers b7 b0 0 0 X 0 0 1 0 1 UART1 transmit/receive mode register (address 38 16) UART mode (Transfer data length = 8 bits) Internal clock is selected. 1 stop bit Parity is disabled. Sleep mode is invalid. b7 b0 0 0 0 0 X 1 0 0 UART1 transmit/receive control register 0 (address 3C 16) BRG1 count source: f 2 RTS function is selected. CTS/RTS function is enabled. Pin TXD1's output structure: CMOS output Must be fixed to "0." b7 b0 3316 UART1 baud rate register (BRG1) (address 39 16) When the system clock (main clock) frequency = 16 MHz, baud rate = 9,600 bps b7 b0 X X X X X 1 X 1 UART1 transmit/receive control register 1 (address 3D 16) Transmission is enabled. Reception is enabled. b7 b0 0 UART1 transmission interrupt control register (address 73 16) Interrupt priority level is set. (Note that a value other than "000 2" is set.) Interrupt request bit: 0 (Initialized) b7 b0 0 UART1 receive interrupt control register (address 74 16) Interrupt priority level is set. (Note that a value other than "000 2" is set.) Interrupt request bit: 0 (Initialized) b7 X 0 X X b0 Port P8 direction register (address 14 16) Pin R XD1: Input mode Interrupt disable flag (I) "0": Interrupt is enabled. Fig. 17.2.11 Initial settings for related registers 17-34 7733 Group User's Manual X: It may be "0" or "1." APPLICATIONS 17.2 Serial I/O (3) Approximate flowchart Main routine 0 Whether transmission of the preceding data has started or not is determined. (Whether the next data can be set to the UART1 transmission buffer register or not is determined.) [F_DATAOUT] = "1" ? 1: Transmission interrupt request has occurred. [F_DATAOUT] UART1 transmission buffer register (address 3A 16) The flag used to determine whether a transmission interrupt request has occurred or not is initialized. "0" [TRA_DATA] Transmit data is set. UART1 transmission interrupt routine Register save processing [F_DATAOUT] "1" Flag used to determine whether a transmission interrupt request has occurred or not: "1" Register return processing RTI [F_DATAOUT]: Flag used to determine whether a transmission interrupt request has occurred or not. [TRA_DATA]: RAM where transmit data is stored. Fig. 17.2.12 Approximate flowchart (1) 7733 Group User's Manual 17-35 APPLICATIONS 17.2 Serial I/O Main routine 0 [F_DATAIN] = "1" ? Whether reception has been completed or not is determined. 1: Reception interrupt request has occurred. [F_DATAIN] The flag used to determine whether a reception interrupt request has occurred or not is initialized. 0" [F_ERROR] ? 1: Error is found. Whether data has been correctly received or not is determined. 0: No error is found. Received data processing Error processing (Note) [F_DATAIN]: Flag used to determine whether a reception interrupt request has occurred or not [F_ERROR]: Flag used to determine whether a data reception error has occurred or not Note: When an error occurs, reception is disabled in a reception interrupt routine. Therefore, when restarting reception after error processing is completed in the main routine, make reception enabled again. Fig. 17.2.13 Approximate flowchart (2) 17-36 7733 Group User's Manual APPLICATIONS 17.2 Serial I/O UART1 reception interrupt routine Register save processing Error sum flag? (bit 7 at address 3D16) 1: Error is found. Whether data has been correctly received or not is determined. 0: No error is found. [F_ERROR] [WORK_RAM] Flag used to determine whether a data reception error has occurred or not = "0" "0" Receive data is temporarily stored in [WORK_RAM] Framing error flag = "0" Parity error flag = "0" UART1 receive buffer register (address 3E 16) Overrun error flag? (bit 4 at address 3D16) 1: Error is found. (Note) 0: No error is found. [REC_DATA] [WORK_RAM] Confirmed receive data is stored in [REC_DATA] [F_ERROR] "1" Reception enable bit "0" (bit 2 at address 3D16) [F_DATAIN] "1" Register return processing Flag used to determine whether a data reception error has occurred or not = "1" All of error flags = "0" (Reception is disabled.) Flag used to determine whether a reception interrupt request has occurred or not = "1" [F_ERROR]: Flag used for determination of data reception error [WORK_RAM]: RAM where receive data is temporarily stored RTI [REC_DATA]: RAM where confirmed receive data is stored [F_DATAIN]: Flag used to determine whether a reception interrupt request has occurred or not Note: If the next data is received from when the error sum flag is checked until the contents of the UART1 receive buffer register is transferred to [WORK_RAM], an overrun error occurs. Therefore, at this timing, the content of the overrun error flag is checked again. Fig. 17.2.14 Approximate flowchart (3) 7733 Group User's Manual 17-37 APPLICATIONS 17.2 Serial I/O 17.2.4 8-bit transmission example (Clock synchronous serial I/O mode) In this example, after 8-bit data is transmitted with UART1 used, a strobe signal is output. (1) Specifications Clock synchronous serial I/O mode is selected. An internal clock is selected. Transfer rate = 2 MHz LSB first is selected. Transmit data is output at the falling edge of the transfer clock. Pin T xD 1's output structure: CMOS output A strobe signal is output from port P43 each time 8-bit data is transmitted. (Refer to Figure 17.2.16.) Completion of the transmission is determined by checking the transmission register empty flag. CLK1 CLK TXD1 IN P43 M37733MHBXXXFP STB Peripheral IC Fig. 17.2.15 Connection example CLK1 T X D1 D0 D1 D2 D3 D4 D5 P43 (Strobe signal) Fig. 17.2.16 Strobe signal output timing 17-38 7733 Group User's Manual D6 D7 APPLICATIONS 17.2 Serial I/O (2) Initial settings for related registers b7 b0 0 X X X 0 0 0 1 UART1 transmit/receive mode register (address 38 16) Clock synchronous serial I/O mode Internal clock is selected. Must be fixed to "0." b7 b0 0 0 0 1 0 0 UART1 transmit/receive control register 0 (address 3C 16) BRG1 count source: f 2 CTS/RTS function is disabled. Pin TXD1's output structure: CMOS output Transmit data is output at the falling edge of the transfer clock. LSB first b7 b0 0116 UART1 baud rate register (BRG1) (address 39 16) When the system clock (main clock) frequency = 16 MHz, transfer rate = 2 MHz. b7 b0 X X X X X 0 X 1 UART1 transmit/receive control register 1 (address 3D 16) Transmission is enabled. Reception is disabled. b7 b0 X 0 0 0 UART1 transmission interrupt control register (address 73 16) UART1 transmission interrupt is disabled. b7 b0 1 Port P4 direction register (address C 16) Pin P43:Output mode b7 b0 0 Port P4 register (address A 16) Pin P43's output level: "L" X: It may be "0" or "1." Fig. 17.2.17 Initial settings for related registers 7733 Group User's Manual 17-39 APPLICATIONS 17.2 Serial I/O (3) Approximate flowchart 16-bit data is transmitted by the 8 bits in two operations. Main routine UART1 transmission buffer register (address 3A 16) 0 [Transmit data 1] Transmission buffer empty flag = "1" ? (bit 1 at address 3D 16) Transmit data is set. Waiting for the start of transmission 1: Transfer is completed. 0 Transmission register empty flag = "1" ? (bit 3 at address 3C 16) Waiting for the completion of transmission 1: Transmission is completed. Port P4 register (address A 16) "1 2" NOP instruction or others are used. "H" level output time for a strobe signal is set. Waiting Port P4 register (address A 16) "XXXX0XXX 2" UART1 transmission buffer register (address 3A 16) 0 Strobe signal's level: "H" Strobe signal's level: "L" [Transmit data 2] Transmission buffer empty flag = "1" ? (bit 1 at address 3D 16) Transmit data is set. Waiting for the start of transmission 1: Transfer is completed. 0 Transmission register empty flag = "1" (bit 3 at address 3C 16) Waiting for the completion of transmission 1: Transmission is completed. Port P4 register (address A 16) "XXXX1XXX 2" Waiting Port P4 register (address A 16) "XXXX0XXX 2" Strobe signal's level: "H" NOP instruction or others are used. "H" level output time for a strobe signal is set. Strobe signal's level: "L" X: It may be "0" or "1." Fig. 17.2.18 Approximate flowchart 17-40 7733 Group User's Manual APPLICATIONS 17.3 Watchdog timer 17.3 Watchdog timer A program runaway detection example with using the watchdog timer is described below. 17.3.1 Program runaway detection example In this example, when the watchdog timer detect a program runaway, the microcomputer is reset. (1) Specifications The main clock is the system clock and f(XIN ) = 16 MHz. When an interval of 4.09 ms has passed after value "FFF 16 " is set, the watchdog timer issues an interrupt request. (When writing to address 60 16 is not performed because of a program runaway.) When a watchdog timer interrupt request occurs, the microcomputer is reset. ("Software reset" is applied.) (2) Initial setting for related register b7 b0 1 @ Watchdog timer frequency selection flag (address 61 16) Watchdog timer count source: clock f 32 (In the case where f(X IN) = 16 MHz, a watchdog timer interrupt request occurs when an interval of 4.09 ms has passed after value "FFF 16" is set.) Fig. 17.3.1 Initial setting for related register 7733 Group User's Manual 17-41 APPLICATIONS 17.3 Watchdog timer (3) Approximate flowchart Main routine Watchdog timer register 8-bit dummy data (address 60 16) Watchdog timer is initialized. Watchdog timer's value: FFF 16 (Note 1) Watchdog timer interrupt request occurs. (Detection of a program runaway) Watchdog timer interrupt routine Software reset bit "1 " (bit 3 at address 5E 16) (Note 2) Microcomputer is resset. RTI Notes 1: The watchdog timer is initialized again from when the watchdog timer is initialized until the most significant bit of the watchdog timer becomes "0," in other words, until a watchdog timer interrupt request occurs. 2: When a program runaway occurs, there is a possibility that values of data bank register (DT), direct page register (DPR), and others are incorrect. When accessing the software reset bit by using an addressing mode which uses DT, DPR, and others, be sure to set values of DT, DPR, and others again. Fig. 17.3.2 Approximate flowchart 17-42 7733 Group User's Manual APPLICATIONS 17.3 Watchdog timer (4) Precautions 1. The watchdog timer stops counting when the STP instruction is executed. For systems which use the watchdog timer, select "STP instruction disabled" with "STP instruction option" on "MASK ROM ORDER CONFIRMATION FORM." 2. The watchdog timer stops counting when the WIT instruction is executed after the system clock stop bit at wait state (bit 5 at address 6C16) is set to "1." 3. The contents of the processor interrupt priority level (IPL) is not initialized in the following cases: When a value which is the same as the reset vector address's contents is set to the watchdog timer's vector address When a program branches to the destination address at reset in a watchdog timer interrupt routine. Reset of the microcomputer is realized by applying the software reset. 7733 Group User's Manual 17-43 APPLICATIONS 17.4 Power saving 17.4 Power saving Power saving examples (in other words, examples to save power consumption) with the stop or wait mode used are described below. 17.4.1 Power saving example with stop mode used In this example, power saving is realized by using the stop mode. The stop mode is terminated by using the key input interrupt function. (1) Specifications The microcomputer operates in the single-chip mode. Pins P5 0 to P5 3 are used as output pins for the key matrix scanning. Input pins ( KI 0 to KI3) for the key input interrupt function are used as key input pins. Pins KI0 to KI3 are pulled high by using the pull-up function. The initial output levels of pins P5 0 to P5 3 are "L." When a key input interrupt request occurs owing to a key push, the key data is read-in. (This reading is surely performed independent of power saving.) In the stop mode, interrupts other than a key input interrupt are disabled. An external clock is used as the main clock. 17-44 7733 Group User's Manual APPLICATIONS 17.4 Power saving (2) Initial settings for related registers b7 b0 0 1 Oscillation circuit control register 1 (address 6F 16) (Note) 1 An external clock is selected as the main clock. Watchdog timer is not used when the stop mode is terminated. In the one time PROM version or EPROM version of the 7733 Group, this bit must be fixed to "1." (In the 7735 Group, this bit must be fixed to "0." ) Must be fixed to "0." Note: When writing a value to this register, write a value of "5516" by executing the LDM instruction, and then write a desired value. (Refer to Figure 11.2.4.) b7 b0 1 1 0 0 X Port function control register (address 6D 16) Must be fixed to "0." Pin P64/INT2 is not used for the key input interrupt. Pins KI0 to KI3 are pulled high. Key input interrupt function is selected. b7 b0 0 0 0 0 1 1 1 1 Port P5 direction register (address D 16) Pins P5 0 to P5 3: Output mode Pins P5 4 to P5 7 (KI0 to KI3): Input mode b7 b0 X X X X 0 0 0 0 Port P5 register (address B 16) Pins P5 0 to P53's output (scan output) level: "L" b7 b0 0 0 0 INT2/Key input interrupt control register (address 7F 16) Interrupt priority level is set. (Note that a value other than "000 2" is set.) Interrupt request bit: 0 (Initialized) Must be fixed to "0." Interrupt disable flag (I) "0": Interrupt is enabled. X: It may be "0" or "1." Fig. 17.4.1 Initial settings for related registers 7733 Group User's Manual 17-45 APPLICATIONS 17.4 Power saving (3) Approximate flowchart Main routine Port P5 register's bits which correspond to pins P50 to P53 (bits 0 to 3 at address B16) Bits 2 to 0 at addresses 7016 to 7E16 VREF connection selection bit (bit 5 at address 1F16) Scan output: "L" level Interrupts other than a key input interrupt are disabled. "0002" Pin VREF is disconnected from resistor ladder network. (Note 1) "1" Port level is fixed. Key input interrupt request occurs. (Key is pushed.) "0" (Note 2) STP Stop mode is selected. Key input (INT2) interrupt routine Register save processing Key data is read-in. Port P5 register's bits which correspond to pins P50 to P53 (bits 0 to 3 at address B16) "0" Scan output: "L" level Register return processing RTI Notes 1: When pin VREF and resistor ladder network are connected, current flows into the resistor ladder network. When using the A-D converter after the stop mode is terminated, do as follows: qReconnect pin VREF and resistor ladder network. w And then, start A-D conversion after a period of 1 s or more passed. 2: When a port is connected to an external device and so on, there is a possibility that current consumption increases according to the port's level. In order to avoid this problem, do as follows: *When output mode is selected: Fix the port's level to a level where no current flows into the external. *When input mode is selected : Pull the port high or low via a resistor. (Floating state is disabled.) Fig. 17.4.2 Approximate flowchart 17-46 7733 Group User's Manual APPLICATIONS 17.4 Power saving (4) Settings for performing power saving in memory expansion or microprocessor mode In the memory expansion or microprocessor mode, when saving power consumption, it is necessary to fix the I/O pins' levels of the external bus and bus control signals in the stop mode. For this purpose, set the standby state selection bit to "1." 7733 Group User's Manual 17-47 APPLICATIONS 17.4 Power saving Main routine VREF connection selection bit (bit 5 at address 1F16) Port P0 register (address 216) Port P1 register (address 316) Port P2 register (address 616) Port P3 register (address 716) "1" Pin VREF is disconnected from resistor ladder network. I/O pins' levels of external bus and bus control signals in the stop mode are set. (These levels can be set by the corresponding port register's bits.) In this example, I/O pins for "L"-active signals are set to "H" and the other pins are set to "L." "001111112" "000000002" "000000002" "000010112" Port P0 direction register (address 416) Port P1 direction register (address 516) Port P2 direction register (address 816) Port P3 direction register (address 916) "FF16" Ports which correspond to I/O pins of external bus and bus control signals: Output mode (This setting is done in order to output a value set to a port register in the stop mode) "FF16" "FF16" "FF16" Levels of ports other than the above are fixed. Port P4 register's bit which corresponds to P42 pin "0" (bit 2 at address A16) Port P4 direction register's bit which corresponds to P42 pin (bit 2 at address C16) Standby state selection bit (bit 0 at address 6D16) Signal output disable selection bit (bit 6 at address 6C16) Interrupt request occurs. STP "1" Pin 1's state in the stop mode is set (Note). In this example, "L" level output is set. Standby state selection bit: "1" (In the stop mode, a value which is set to the corresponding port register is output from an I/O pin of the external bus or bus control signals.) "1" "1" Pin E's output level in the stop mode is set. In this example, it is set to "L." Stop mode is selected. Note: Regardless of this setting, in the following cases, pin 1 outputs "L" level in the stop mode: When the signal output disable selection bit is set to "0" in the microprocessor mode When the clock 1 output selection bit is set to "1" in the memory expansion mode Fig. 17.4.3 Fixing I/O pins' levels of external bus and bus control signals (Microprocessor mode) 17-48 7733 Group User's Manual APPLICATIONS 17.4 Power saving 17.4.2 Power saving example with wait mode used In this example, power saving is realized by using the wait mode. While power is saved, the clock function is realized by using the clock timer (Timer B2). (1) Specifications The microcomputer operates in the single-chip mode. The frequency of the sub clock (f(XCIN)) = 32.768 kHz. An external clock is used as the sub clock. Clock counting is performed by using the clock timer. (An interrupt request occurs every second.) When an INT0 interrupt request occurs (Note), the wait mode is terminated. Note: An interrupt request occurs at every falling edge of the signal input from pin INT 0. In the wait mode, interrupts other than the following interrupts are disabled. *Timer B2 interrupt * INT0 interrupt An external input is used as the main clock. 7733 Group User's Manual 17-49 APPLICATIONS 17.4 Power saving (2) Initial settings for related registers b7 b0 X 0 1 1 1 Oscillation circuit control register 1 (address 6F 16) An external clock is selected as the main clock. Watchdog timer is not used when the stop mode is terminated. An external clock is selected as the sub clock and P7 6 functions as a port. Watchdog timer is not used when the stop mode is terminated. In the one time PROM version or EPROM version of the 7733 Group, this bit must be fixed to "1." (In 7735 Group, this bit must be fixed to "0." ) Must be fixed to "0." Note: When writing a value to this register, write a value of "55 16" by executing the LDM instruction, and then write a desired value. (Refer to Figure 11.2.4.) b7 b0 1 1 X Oscillation circuit control register 0 (address 6C 16) XCIN-XCOUT is selected. (Sub clock is used.) In the wait mode, clocks b7 2 to 512 are stopped. b0 0 0 0 INT0 interrupt control register (address 7D 16) Interrupt priority level is set. (Note that a value other than "000 2" is set.) Interrupt request bit: 0 (Initialized) An interrupt request occurs at the falling edge. b7 b0 0 Timer B2 interrupt control register (address 7C 16) Interrupt priority level is set. (Note that a value other than "000 2" is set.) Interrupt request bit: 0 (Initialized) b15 b8 b7 03 16 b0 FF16 Timer B2 register (addresses 55 16 and 54 16) Interval of the clock timer's interrupt request occurrence: 1 second Interrupt disable flag (I) b7 X X X "0": Interrupt is enabled. b0 0 1 0 1 Timer B2 mode register (address 5D 16) Settings for the clock timer X: It may be "0" or "1." Fig. 17.4.4 Initial settings for related registers 17-50 7733 Group User's Manual APPLICATIONS 17.4 Power saving (3) Approximate flowchart Main routine Bits 2 to 0 at addresses 70 16 to 7B 16, 7E 16, and 7F 16 "0002" Timer B2 count start flag (bit 7 at address 40 16) "1" VREF connection selection bit (bit 5 at address 1F 16) "1" System clock selection bit (bit 3 at address 6C 16) [F_WIT] INT0 interrupt request occurs. "1" Pin V REF is disconnected from resistor ladder network. (Note 1) System clock: Main clock <<A>> Sub clock Main clock oscillation circuit: Stopped <<B>> "1" (By this setting, the wait mode is terminated only when an INT0 interrupt request occurs.) "1" Clock timer interrupt request occurs. WIT Clock timer starts counting . (Note 2) Port level is fixed. Main clock stop bit (bit 2 at address 6C 16) Interrupts other than timer B2 and INT0 interrupts are disabled. Wait mode is selected. "1": Clock timer interrupt [F_WIT] = "1" ? 0: INT0 interrupt Main clock stop bit (bit 2 at address 6C 16) System clock selection bit (bit 3 at address 6C 16) Main clock oscillation circuit: Oscillating <<C>> "0" "0" System clock: Sub clock <<D>> Main clock (Note 3) [F_WIT]: Flag used to determine whether an INT0 interrupt request has occurred or not For Notes 1 to 3, refer to the next page. <<A>> <<B>> <<C>> <<D>>: Refer to Figure 17.4.8. Fig. 17.4.5 Approximate flowchart (1) 7733 Group User's Manual 17-51 APPLICATIONS 17.4 Power saving Notes 1: When pin V REF and resistor ladder network are connected, current flows into the resistor ladder network. When using the A-D converter after the wait mode is terminated, do as follows: Reconnect pin VREF and resistor ladder network. And then, start A-D conversion after a period of 1 s or more passed. 2: When a port is connected to an external device and so on, there is a possibility that current consumption increases according to the port's level. In order to avoid this problem, do as follows: *When output mode is selected: Fix the port's level to a level where no current flows into the external. *When input mode is selected: Pull the port high or low via a resistor. (Floating state is disabled.) 3: Do not switch the system clock until oscillation of a clock which is input from the external is stabilized. INT0 interrupt routine Register save processing [F_WIT] Timer B2 interrupt routine Register save processing "0" Clock count Register return processing Register return processing RTI RTI [F_WIT]: Flag used to determine whether an INT0 interrupt request has occurred or not Fig. 17.4.6 Approximate flowchart (2) 17-52 7733 Group User's Manual APPLICATIONS 17.4 Power saving Notes 1: When pin V REF and resistor ladder network are connected, current flows into the resistor ladder network. When using the A-D converter after the wait mode is terminated, do as follows: q Reconnect pin VREF and resistor ladder network. w And then, start A-D conversion after a period of 1 s or more passed. 2: When a port is connected to an external device and so on, there is a possibility that current consumption increases according to the port's level. In order to avoid this problem, do as follows: *When output mode is selected: Fix the port's level to a level where no current flows into the external. *When input mode is selected: Pull the port high or low via a resistor. (Floating state is disabled.) 3: Do not switch the system clock until oscillation of a clock which is input from the external is stabilized. INT0 interrupt routine Register save processing [F_WIT] Timer B2 interrupt routine Register save processing "0" Clock count Register return processing Register return processing RTI RTI [F_WIT]: Flag used to determine whether an INT0 interrupt request has occurred or not Fig. 17.4.6 Approximate flowchart (2) 17-52 7733 Group User's Manual 7733 Group User's Manual Main clock stop bit System clock selection bit System clock Sub clock Main clock "0" "1" "0" "1" Main clock <<A>> <<B>> <<C>> Sub clock <<D>> Main clock APPLICATIONS 17.4 Power saving Fig. 17.4.7 State of main clock, sub clock, and system clock 17-53 APPLICATIONS 17.5 Timer B 17.5 Timer B An application example of the clock timer (Timer B) is described below. 17.5.1 Application example of clock timer In this example, the clock timer is controlled by a clock of 32.768 kHz. When the main power source is off, the clock timer can continue counting for the maximum of approximate 45 days by using the backup power source and the internal connect function between timers B1 and B2. (1) Specifications Main power source = 5 V to 2.75 V. Backup power source = 2.75 V to 2.2 V Timer B2 uses the sub clock (32.768 kHz) divided by 32 as the count source and counts the time up to 1 minute. Timer B2 counts the power-source-off time up to the maximum of approximate 45 days, checking the timer B2's overflow signal. The clock counter is counted up each time timer B2 interrupt occurs, in other words, every 1 minute. When Vcc is less than 2.75 V, in other words, when the main power source is off, the INT0 input's level changes from "H" to "L" and the microcomputer enters the wait mode at this falling edge. (Refer to "a" in Figure 17.5.2.) In the wait mode (Vcc = 2.2 V or more), only timers B2 and B1 do counting. (In this case, note that clock display is disabled and the timer B2 and B1 interrupts are disabled.) When Vcc = 2.75 V or more in the wait mode, in other words, when the main power source is on, the INT0 input's level changes from "L" to "H" and the wait mode is terminated at the INT0 input's rise. (Refer to "b" in Figure 17.5.2.) At this time, the following is done according to the timer B1's state. *When no overflow has occurred in timer B1 (Timer B1 interrupt request bit = "0"), timer B1's value is added to the clock counter's value which was obtained immediately before the wait mode. *When an overflow has occurred in timer B1, in other words, when a period of approximate 45 days or more has passed, a message for resetting time is displayed. When Vcc = 2.2 V or less, the microcomputer enters the reset state owing to the power source detection circuit. (Refer to "c" in Figure 17.5.2.) And then, when Vcc = 2.75 V or more, the microcomputer is released from reset state. (Refer to "d" in Figure 17.5.2.) Main power source (5 V) Backup power source Detection voltage Clock display Vcc Reset signal RESET Control signal INT0 Vss XCIN XCOUT 32.768 kHz Power source detection circuit M37733MHBXXXFP Fig. 17.5.1 Connection example 17-54 7733 Group User's Manual APPLICATIONS 17.5 Timer B 5V Main power source 2.75 V Vcc Backup power source 2.2 V 0V RESET INT 0 Wait mode Approx. 45.5 days (Max.) a b c d Fig. 17.5.2 Timing chart (2) Structure of timer B block where timers B1 and B2 are internally connected Figure 17.5.3 shows the structure of the timer B block. Timer B2 reload register Timer B2 interrupt request bit Timer B1 reload register Timer B1 internal connect selection bit Clock prescaler Sub clock : f(X CIN) Main clock : f(X IN) 1/32 Clock timer fc32 (Timer B2 counter) Timer B1 counter Timer B1 interrupt request bit Event counter mode System clock (Clock source for clocks f 2 to f512 and internal clock ) Fig. 17.5.3 Structure of timer B block 7733 Group User's Manual 17-55 APPLICATIONS 17.5 Timer B (3) Initial settings for related registers b7 b0 X 0 1 X X X Oscillation circuit control register 0 (address 6C 16) Sub clock is used. (Note 1) Clocks f2 to f512 are operating in the wait mode. (Note 2) b7 b0 X X X 0 1 0 1 Timer B1 mode register (address 5C 16) Timer B2 mode register (address 5D 16) 01: Event counter mode 01: Count at the rising edge b7 b0 0 0 0 0 Timer B1 interrupt control register (address 7B 16) Interrupt is disabled. No interrupt is requested. b7 b0 0 0 0 1 Timer B2 interrupt control register (address 7C 16) Interrupt priority level (any value other than "000 2") is set. No interrupt is requested. b7 b0 X X X 0 X 1 X X Port function control register (address 6D 16) Timers B1 and B2 are connected internally. Must be fixed to "0." b7 b0 0 0 0 0 0 1 INT0 interrupt control register (address 7D 16) Interrupt priority level (any value other than "000 2") is set. No interrupt is requested. Interrupt request bit is set at the falling edge ( "H" to "L"). Edge sense b15 b0 Timer B2 register (addresses 55 16 and 54 16) EFFF 16 b15 b0 FFFF 16 Timer B1 register (addresses 53 16 and 52 16) X: It may be "0" or "1." Notes 1: Once this bit is set to "1," it cannot be cleared to "0." 2: When setting this bit to "1," set "1" to this bit immediately before the WIT instruction is executed. Furthermore, clear this bit to "0" immediately after the wait mode is terminated. Fig. 17.5.4 Initial settings for related registers 17-56 7733 Group User's Manual APPLICATIONS 17.5 Timer B (4) Approximate flowchart Main routine Oscillation circuit control register (address 6F 16) "8016" Clock prescaler is initialized. A value of "80 16" is written to address 6F 16 by executing the LDM instruction. Count start flag (address 40 16) "C016" Count start flag Counting for timers B1 and B2 start Timer B2 interrupt routine Count-up processing for clock Counted up every minute RTI INT0 interrupt routine By software initial settings, interrupt priority level is set as follows: Timer B2 < INT 0 INT0 level/edge selection bit = "?" (bit 4 at address 7D 16) 1: Rising edge ("L" 0: Falling edge ("H" INT0 interrupt control register (address 7D 16) Timer B1 count start flag (bit 6 at address 40 16) "11 16" "0" "L") "H") INT0 interrupt control register (address 7D 16) "01 16" INT 0 interrupt polarity is selected. (Falling edge: "H" "L") INT0 interrupt polarity is selected. (Rising edge: "L" "H") Counting for timer B1 stops. Timer B1 register FFFF 16 (addresses 53 16 and 52 16) Timer B1 count start flag (bit 6 at address 40 16) "1 " Counting for timer B1 starts. 0: No request Timer B2 interrupt request bit = ? (bit 3 at address 7C 16) Timer B1 interrupt request bit = ? (bit 3 at address 7B 16) 1: Requested Timer B1 count start flag (bit 6 at address 40 16) "0" Timer B1 register FFFE 16 (addresses 53 16 and 52 16) Timer B1 count start flag (bit 6 at address 40 16) "1" 1: Requested 0: No request Counting for timer B1 stops. Display urging user to set time again Count value of timers B1 and B2 Clock counter Counting for timer B1 starts. By setting interrupt priority level, interrupts other than INT 0 are disabled. System clock stop bit at wait state (bit 5 at address 6C 16) "1" Make INT 0 interrupt priority level higher. WIT instruction Make INT 0 interrupt priority level to the former level. RTI Fig. 17.5.5 Approximate flowchart 7733 Group User's Manual 17-57 APPLICATIONS 17.5 Timer B MEMO 17-58 7733 Group User's Manual CHAPTER 18 LOW VOLTAGE VERSION 18.1 18.2 18.3 18.4 18.5 18.6 Performance overview Pin configuration Functional description Electrical characteristics Standard characteristics Applications LOW VOLTAGE VERSION The low voltage version has the following characteristics: * Low power source voltage (2.7 to 5.5 V) * Wide operating temperature range (-40 to 85 C) The low voltage version is suitable to control equipment which is required to process a large amount of data with a little power dissipation, for example portable equipment which is driven by a battery and OA equipment. Differences between the M37733MHLXXXHP, which is the low voltage version of the 7733 Group, and the M37733MHBXXXFP are mainly described below. For the EPROM mode of the built-in PROM version, refer to chapter "19. BUILT-IN PROM VERSION." 18-2 7733 Group User's Manual LOW VOLTAGE VERSION 18.1 Performance overview 18.1 Performance overview Table 18.1.1 shows the performance overview of the M37733MHLXXXHP. Table 18.1.1 M37733MHLXXXHP performance overview Items Performance Number of basic instructions 103 333 ns (When f(X IN ) = 12 MHz and main clock The minimum instruction execution time is system clock) Main-clock frequency f(XIN) 12 MHz (Max.) (Note) Sub-clock frequency f(X CIN) 32.768 kHz (Typ.) Memory size 124 kbytes ROM 3968 bytes RAM Programmable input/output Ports P0-P2, P4-P8 8 bits 8 ports 4 bits 1 Port P3 Multi-function timers 16 bits 5 Timers A0-A4 16 bits 3 Timers B0-B2 (UART or clock synchronous serial I/O) 3 Serial I/O UART0-UART2 A-D converter (10-bit successive approximation method) 1(8 channels) 12 bits 1 Watchdog timer 3 external, 16 internal (By software, one of interrupt priority Interrupts levels 0 to 7 can be set for each interrupt.) Built-in (externally connected to a ceramic resoClock generating circuits Main-clock oscillation nator or a quartz-crystal oscillator) circuit Built-in (externally connected to a quartz-crystal Sub-clock oscillation oscillator) circuit 2.7 V - 5.5 V Power source voltage Power consumption (in single-chip mode) 9 mW (When f(X IN ) = 12 MHz, Vcc = 3 V, and the main clock is the system clock, Typ.) 22.5 mW (When f(XIN) = 12 MHz, Vcc = 5 V, the main clock is the system clock, Typ.) 90 W (When f(XCIN) = 32 kHz, Vcc = 3 V, the sub clock is the system clock, and the main clock is stopped, Typ.) Port input/output 5 V Input/Output withstand characteristics voltage 5 mA Output current Memory expansion Possible (Maximum of 16 Mbytes) Operating temperature range -40 C to +85 C Device structure High-performance CMOS silicon gate process Package 80-pin plastic molded fine-pitch QFP Note: When the main clock division selection bit = "1," the maximum value of f(X IN ) = 6 MHz. 7733 Group User's Manual 18-3 LOW VOLTAGE VERSION 18.2 Pin configuration 18.2 Pin configuration P67/TB2IN/ SUB P70/AN0 P71/AN1 P72/AN2/ C TS2 P73/AN3/ C LK2 P74/AN4/ R xD 2 P75/AN5/AD TR G/ TxD 2 P76/AN6/XC O U T P77/AN7/XC IN VSS AVSS VR EF AVC C VC C P8 0/C TS0/R TS0/C LKS1 P81/C LK0 P8 2/RXD0/C LKS0 P8 3/TXD0 P8 4/C TS1/R TS1 P8 5/C LK1 Figure 18.2.1 shows the M37733MHLXXXHP pin configuration. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 58 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 M 37733M H L XXXH P P66/TB1IN P65/TB0IN P64/IN T2 P63/IN T1 P62/IN T0 P61/TA4IN P60/TA4O U T P57/TA3IN/KI3 P5 6/TA3O U T/KI2 P55/TA2IN/KI1 P54/TA2O U T/KI0 P53/TA1IN P52/TA1O U T P51/TA0IN P50/TA0O U T P47 P46 P45 P44 P43 56 55 54 53 52 51 50 49 48 47 46 45 44 43 19 42 20 41 P42/ 1 P41/R D Y P40/H O LD BYTE C N VSS R ESET XIN XO U T E VSS P33/H LD A P32/ALE P31/BH E P30/R /W P27/A23 /D7 P26/A22 /D6 P25/A21 /D5 P24/A20 /D4 P23/A19 /D3 P22/A18 /D2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Outline 80P6D-A Fig. 18.2.1 M37733MHLXXXHP pin configuration (Top view) 18-4 57 7733 Group User's Manual P86/RxD1 P87/TxD1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10 /D10 P13/A11 /D11 P14/A12 /D12 P15/A13 /D13 P16/A14 /D14 P17/A15 /D15 P20/A16 /D0 P21/A17 /D1 LOW VOLTAGE VERSION 18.3 Functional description 18.3 Functional description The M37733MHLXXXHP has the same functions as the M37733MHBXXXFP except for the power-on reset conditions. Power-on reset conditions are described below. For the other functions, refer to chapters "2. CENTRAL PROCESSING UNIT" to "14. CLOCK GENERATING CIRCUIT." 7733 Group User's Manual 18-5 LOW VOLTAGE VERSION 18.3 Functional description 18.3.1 Power-on reset conditions Figure 18.3.1 shows the power-on reset conditions and Figure 18.3.2 shows an example of power-on reset circuit. For details of reset, refer to chapter "13. RESET." Powered on here 2.7V Vcc 0V RESET 0.55V 0V Fig. 18.3.1 Power-on reset conditions 5V M37733MHLXXXHP Vcc M62003L Vcc INTi (i = 0 to 2) INT (Interrupt signal) Cd RESET (Reset signal) GND Cd Delay time td is about 10 ms when Cd = 0.07 F. td 0.152 Cd [ s ], Cd: [ F ] Fig. 18.3.2 Example of power-on reset circuit 18-6 7733 Group User's Manual RESET LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4 Electrical characteristics The M37733MHLXXXHP's electrical characteristics are described below. For the latest data, inquire of addresses described last ("CONTACT ADDRESSES FOR FURTHER INFORMATION") . 18.4.1 Absolute maximum ratings Absolute maximum ratings Parameter Symbol Power source voltage Vcc Analog power source voltage AVcc ______ Input voltage RESET, CNVss, BYTE VI Input voltage P00-P07, P10-P17, P20-P27, P30-P33, VI P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, VREF, XIN Output voltage P00-P07, P10-P17, P20-P27, P30-P33, VO P40-P47, P50-P5 7, P60-P67, P70-P77, __ P80-P87, XOUT, E Power dissipation Pd Operating temperature Topr Storage temperature Tstg Conditions Ta = 25 C 7733 Group User's Manual Ratings -0.3 to 7 -0.3 to 7 -0.3 to 12 Unit V V V -0.3 to Vcc+0.3 V -0.3 to Vcc+0.3 V 200 -40 to 85 -65 to 150 mW C C 18-7 LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.2 Recommended operating conditions Recommended operating conditions (Vcc = 2.7 to 5.5 V, Ta = -40 to 85 C, unless otherwise noted) Limits Unit Symbol Parameter Min. Typ. Max. 2.7 5.5 f(XIN) :Operating Vcc Power source voltage V 2.7 5.5 f(XIN) :Stopped, f(XCIN) = 32.768 kHz AVcc Analog power source voltage Vcc V Vss Power source voltage 0 V AVss Analog power source voltage 0 V P00-P07, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, VIH High-level input voltage V 0.8 Vcc Vcc P80-P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3) P10-P17, P20-P27 VIH High-level input voltage V 0.8 Vcc Vcc (in single-chip mode) P10-P17, P20-P27 VIH High-level input voltage (in memory expansion mode and 0.5 Vcc V Vcc microprocessor mode) P00-P07, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, Low-level input voltage 0 VIL V 0.2 Vcc P80-P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3) P10-P17, P20-P27 Low-level input voltage 0 VIL V 0.2 Vcc (in single-chip mode) P10-P17, P20-P27 Low-level input voltage 0 VIL (in memory expansion mode and 0.16 Vcc V microprocessor mode) P00-P07, P10-P17, P20-P27, IOH (peak) High-level peak output current P30-P33, P40-P47, P50-P57, mA -10 P60-P67, P70-P77, P80-P87 P00-P07, P10-P17, P20-P27, High-level average output current P30-P33, P40-P47, P50-P57, IOH (avg) mA -5 P60-P67, P70-P77, P80-P87 P00-P07, P10-P17, P20-P27, IOL (peak) Low-level peak output current P30-P33, P40-P43, P54-P57, mA 10 P60-P67, P70-P77, P80-P87 IOL (peak) Low-level peak output current P44-P47, P50-P53 mA 16 P00-P07, P10-P17, P20-P27, Low-level average output current P30-P33, P40-P43, P54-P57, IOL (avg) mA 5 P60-P67, P70-P77, P80-P87 Low-level average output current P44-P47, P50-P53 IOL (avg) mA 12 f(XIN) Main-clock oscillation frequency (Note 4) MHz 12 f(XCIN) Sub-clock oscillation frequency 32.768 kHz 50 Notes 1: Average output current is the average value of an interval of 100 ms. 2: The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less. 3: Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = "1." 4: The maximum value of f(XIN) = 6 MHz when the main clock division selection bit = "1." 18-8 7733 Group User's Manual LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.3 Electrical characteristics Electrical characteristics (Vcc = 5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. High-level output voltage P00-P07, P10-P17, P20-P27, Vcc = 5 V, IOH = -10 mA 3 V VOH P33, P40-P47, P50-P57, Vcc = 3 V, I OH = -1 mA 2.5 P60-P67, P70-P77, P80-P87 High-level output voltage P00-P07, P10-P17, P20-P27, Vcc = 5 V, IOH = -400 A V VOH 4.7 P33 High-level output voltage P30-P32 Vcc = 5 V, IOH = -10 mA 3.1 VOH Vcc = 5 V, IOH = -400 A 4.8 V Vcc = 3 V, IOH = -1 mA 2.6 _ High-level output voltage E Vcc = 5 V, IOH = -10 mA 3.4 VOH V Vcc = 5 V, IOH = -400 A 4.8 Vcc = 3 V, IOH = -1 mA 2.6 Low-level output voltage P00-P07, P10-P17, P20-P27, Vcc = 5 V, IOL = 10 mA 2 V VOL P33, P40-P43, P54-P57, Vcc = 3 V, I OL = 1 mA 0.5 P60-P67, P70-P75, P80-P87 Low-level output voltage P44-P47, P50-P53 VOL Vcc = 5 V, IOL = 16 mA 1.8 V Vcc = 3 V, IOL = 10 mA 1.5 Low-level output voltage P00-P07, P10-P17, P20-P27, VOL Vcc = 5 V, IOL = 2 mA 0.45 V P33 Low-level output voltage P30-P32 1.9 Vcc = 5 V, IOL = 10 mA VOL 0.43 V Vcc = 5 V, IOL = 2 mA 0.4 Vcc = 3 V, IOL = 1 mA Low-level output voltage E 1.6 Vcc = 5 V, IOL = 10 mA VOL 0.4 V Vcc = 5 V, IOL = 2 mA 0.4 Vcc = 3 V, IOL = 1 mA Hysteresis HOLD, RDY, TA0IN-TA4IN, TB0IN-TB2IN, 0.4 1 Vcc = 5 V V INT0-INT2, ADTRG, CTS0, CTS1, CTS2, CLK0, VT+-VT- 0.7 0.1 Vcc = 3 V CLK1, CLK2, KI0-KI3 0.5 0.2 Vcc = 5 V VT+-VT- Hysteresis RESET 0.4 V 0.1 Vcc = 3 V 0.4 0.1 Vcc = 5 V VT+-VT- Hysteresis XIN 0.26 V Vcc = 3 V 0.06 0.4 Vcc = 5 V 0.1 VT+-VT- Hysteresis XCIN (When external clock is input) 0.26 V Vcc = 3 V 0.06 High-level input current P00-P07, P10-P17, P20-P27, 5 Vcc = 5 V, VI = 5 V IIH P30-P33, P40-P47, P50-P57, A P60-P67, P70-P77, P80-P87, 4 Vcc = 3 V, VI = 3 V XIN, RESET, CNVss, BYTE Low-level input current P00-P07, P10-P17, P20-P27, -5 P30-P33, P40-P47, P50-P53, Vcc = 5 V, VI = 0 V IIL P60, P61, P65- P67, P70-P77, A P80-P87, XIN, RESET, CNVss, Vcc = 3 V, VI = 0 V -4 BYTE Low-level input current P54-P57, P62-P64 -5 Vcc = 5 V VI = 0 V, A IIL -4 without a pull-up transistor Vcc = 3 V Vcc = 5 V -0.25 -0.5 -1.0 VI = 0 V, mA Vcc = 3 V -0.08 -0.18 -0.35 with a pull-up transistor VRAM When clock is stopped V 2 RAM hold voltage 7733 Group User's Manual 18-9 LOW VOLTAGE VERSION 18.4 Electrical characteristics ELECTRICAL CHARACTERISTICS (Vcc= 5 V, Vss = 0 V, Ta = -40 to 85 C, unless otherwise noted) Limits Symbol Parameter Measuring conditions Min. Typ. Max. Unit Vcc = 5 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), 4.5 9 mA f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), 3 6 mA f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 0.75 MHz), 0.4 0.8 mA In single-chip f(XCIN) : Stopped, mode, output in operating (Note 1) Power source pins are open, Vcc = 3V, ICC current and the other f(XIN) = 12 MHz (Square waveform), 6 12 A pins are con- f(XCIN) = 32.768 kHz, nected to Vss. when the WIT instruction is executed (Note 2) Vcc = 3 V, f(XIN) : Stopped, 30 60 A f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 3 V, f(XIN) : Stopped, 3 6 A f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 C, 1 A when clock is stopped Ta = 85 C, 20 A when clock is stopped Notes 1: This is applied when the main clock external input selection bit = "1," the main clock division selection bit = "0," and the signal output disable selection bit = "1." 2: This is applied when the main clock external input selection bit = "1" and the system clock stop bit at wait state = "1." 3: This is applied when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the X COUT drivability selection bit = "0" and the system clock stop bit at wait state = "1." 18.4.4 A-D converter characteristics A-D CONVERTER CHARACTERISTICS (Vcc = AVcc = 5 V, Vss = AVss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note) , unless otherwise noted) Limits Symbol Parameter Measuring conditions Unit Min. Typ. Max. -- Resolution VREF = Vcc 10 Bits -- Absolute accuracy VREF = Vcc 3 LSB RLADDER Ladder resistance VREF = Vcc 10 25 k tCONV Conversion time 19.6 s VREF Reference voltage 2.7 Vcc V VIA Analog input voltage 0 VREF V Note: This is applied when the main clock division selection bit = "0" and f(f 2) = 6 MHz. 18-10 7733 Group User's Manual LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.5 Internal peripheral devices Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(X IN) = 12 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Timer A input (Count input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) Limits Min. Max. 250 125 125 Parameter TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Unit ns ns ns Timer A input (Gating input in timer mode) Symbol Data formula (Min.) Parameter 8 10 2 f(f2) 4 109 2 f(f2) 4 109 2 f(f2) Limits Min. Max. Unit 9 tc(TA) TAiIN input cycle time (Note 3) tw(TAH) TAiIN input high-level pulse width (Note 3) tw(TAL) TAiIN input low-level pulse width (Note 3) (Note 2) 666 ns (Note 2) 333 ns (Note 2) 333 ns Timer A input (External trigger input in one-shot pulse mode) Symbol Data formula (Min.) Parameter 8 10 2f(f2) Limits Min. Max. Unit 9 tc(TA) TAiIN input cycle time tw(TAH) tw(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width (Note 2) 666 ns 166 166 ns ns Timer A input (External trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) Parameter TAiIN input high-level pulse width TAiIN input low-level pulse width Limits Min. Max. 166 166 Unit ns ns Timer A input (Up-down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-T ) th(T -UP) IN IN Parameter TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Limits Min. Max. 3333 1666 1666 666 666 Unit ns ns ns ns ns Notes 1: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 2: f(f2) represents the clock f 2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 3: The TAi IN input cycle time must be 4 cycles of a count source or more. The TAiIN input high-level pulse width and low-level pulse width must be 2 cycles of a count source or more, respectively. 7733 Group User's Manual 18-11 LOW VOLTAGE VERSION 18.4 Electrical characteristics Timer A input (Two-phase pulse input in event counter mode) Limits Min. Max. tc(TA) TAjIN input cycle time 2 tsu(TAj -TAj ) TAjIN input setup time 500 tsu(TAj -TAj ) TAjOUT input setup time 500 Note: This is applied when the main clock division selection bit = "0" and f(f 2) = 6 MHz. Symbol IN OUT 18-12 Parameter Measuring conditions OUT IN 7733 Group User's Manual Unit s ns ns LOW VOLTAGE VERSION 18.4 Electrical characteristics Internal peripheral devices Count input in event counter mode Gating input in timer mode External trigger input in one-shot pulse mode External trigger input in pulse width modulation mode tc(TA) tw(TAH) TAiIN input tw(TAL) Up-down input and count input in event counter mode tc(UP) tw(UPH) TAiOUT input (up-down input) tw(UPL) TAiOUT input (up-down input) TAiIN input (When fall count is selected) th(TIN-UP) tsu(UP-TIN) TAiIN input (When rise count is selected) Two-phase pulse input in event counter mode tc(TA) TAjIN input tsu(TAjIN-TAjOUT) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAjOUT input tsu(TAjOUT-TAjIN) Measuring conditions *VCC = 2.7 to 5.5 V *Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC 7733 Group User's Manual 18-13 LOW VOLTAGE VERSION 18.4 Electrical characteristics Timer B input (Count input in event counter mode) tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Limits Min. Max. 250 125 125 500 250 250 Parameter Symbol TBiIN input cycle time (One edge count) TBiIN input high-level pulse width (One edge count) TBiIN input low-level pulse width (One edge count) TBiIN input cycle time (Both edges count) TBiIN input high-level pulse width (Both edges count) TBiIN input low-level pulse width (Both edges count) Unit ns ns ns ns ns ns Timer B input (Pulse period measurement mode) Symbol Parameter Data formula (Min.) 8 10 2f(f2) 4 109 2f(f2) 4 109 2f(f2) Limits Min. Max. Unit 9 tc(TB) TBiIN input cycle time tw(TBH) TBiIN input high-level pulse width tw(TBL) TBiIN input low-level pulse width (Note 2) 666 ns (Note 2) 333 ns (Note 2) 333 ns Timer B input (Pulse width measurement mode) Symbol Data formula (Min.) Parameter 8 10 2f(f2) 4 109 2f(f2) 4 109 2f(f2) Limits Min. Max. Unit 9 tc(TB) TBiIN input cycle time tw(TBH) TBiIN input high-level pulse width tw(TBL) TBiIN input low-level pulse width 666 ns 333 ns 333 ns A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (Minimum allowable trigger) ADTRG input low-level pulse width Limits Min. Max. 1333 166 Unit ns ns Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Parameter CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time Limits Min. Max. 333 166 166 100 0 65 75 Unit ns ns ns ns ns ns ns Notes 1: The TBi IN input cycle time must be 4 cycles of a count source or more. The TBiIN input high-level pulse width and low-level pulse width must be 2 cycles of a count source or more, respectively. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 18-14 7733 Group User's Manual LOW VOLTAGE VERSION 18.4 Electrical characteristics External interrupt INT i input, Key input interrupt KI i input Symbol tw(INH) tw(INL) tw(KIL) Limits Min. Max. 250 250 250 Parameter INTi input high-level pulse width INTi input low-level pulse width KIi input low-level pulse width Unit ns ns ns Internal peripheral devices tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi input tw(CKL) th(C-Q) TxDi output td(C-Q) tsu(D-C) th(C-D) RxDi input tw(INL) INTi input KIi input tw(INH) tw(KIL) Measuring conditions *VCC = 2.7 to 5.5 V *Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 7733 Group User's Manual 18-15 LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.6 Ready and Hold Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Symbol tsu(RDY- ) tsu(HOLD- ) th( -RDY) th( -HOLD) 1 1 1 1 Limits Min. Max. 80 80 0 0 Parameter ____ RDY input setup time _____ HOLD input setup time ____ RDY input hold time _____ HOLD input hold time Unit ns ns ns ns Note: This is applied to the case where the main clock division selection bit = "0" and f(f2) = 6 MHz. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(X IN ) = 12 MHz, unless otherwise noted) Parameter Symbol td( -HLDA) 1 18-16 _____ Conditions Fig. 18.4.1 HLDA output delay time 7733 Group User's Manual Limits Min. Max. 120 Unit ns LOW VOLTAGE VERSION 18.4 Electrical characteristics Ready With no wait 1 E output RDY input tsu(RDY- 1) th( 1-RDY) With wait 1 E output RDY input tsu(RDY- 1) th( 1-RDY) Hold 1 tsu(HOLD- 1) th( 1-HOLD) HOLD input td( 1-HLDA) td( 1-HLDA) HLDA output Measuring conditions *VCC = 2.7 to 5.5 V *Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 7733 Group User's Manual 18-17 LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.7 Single-chip mode Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(X IN) = 12 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Unit Min. Max. External clock input cycle time (Note 2) ns tc 83 External clock input high-level pulse width (Note 3) ns tw(H) 33 External clock input low-level pulse width (Note 3) ns tw(L) 33 External clock rise time ns tr 15 External clock fall time ns tf 15 Port P0 input setup time ns tsu(P0D-E) 200 Port P1 input setup time ns tsu(P1D-E) 200 Port P2 input setup time ns tsu(P2D-E) 200 Port P3 input setup time ns tsu(P3D-E) 200 Port P4 input setup time ns tsu(P4D-E) 200 Port P5 input setup time ns tsu(P5D-E) 200 Port P6 input setup time ns tsu(P6D-E) 200 Port P7 input setup time ns tsu(P7D-E) 200 Port P8 input setup time ns tsu(P8D-E) 200 Port P0 input hold time ns th(E-P0D) 0 ns Port P1 input hold time th(E-P1D) 0 ns Port P2 input hold time 0 th(E-P2D) ns Port P3 input hold time 0 th(E-P3D) ns Port P4 input hold time 0 th(E-P4D) ns Port P5 input hold time 0 th(E-P5D) ns Port P6 input hold time 0 th(E-P6D) ns Port P7 input hold time 0 th(E-P7D) ns Port P8 input hold time 0 th(E-P8D) Notes 1: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 166 ns. 3: When the main clock division selection bit = "1," values of tw(H)/t c and tw(L)/t c must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note 2), unless otherwise noted) Limits Symbol Parameter Conditions Min. Max. Unit td(E-P0Q) Port P0 data output delay time ns 300 td(E-P1Q) Port P1 data output delay time ns 300 td(E-P2Q) Port P2 data output delay time ns 300 td(E-P3Q) Port P3 data output delay time ns 300 Fig. 18.4.1 td(E-P4Q) Port P4 data output delay time ns 300 td(E-P5Q) Port P5 data output delay time ns 300 td(E-P6Q) Port P6 data output delay time ns 300 td(E-P7Q) Port P7 data output delay time ns 300 td(E-P8Q) Port P8 data output delay time ns 300 Note: This is applied when the main clock division selection bit = "0" and f(f 2) = 6 MHz. 18-18 7733 Group User's Manual LOW VOLTAGE VERSION 18.4 Electrical characteristics Single-chip mode tf tr tc tW(H) tW(L) XIN E td(E-P0Q) Port P0 output th(E-P0D) tsu(P0D-E) Port P0 input td(E-P1Q) Port P1 output th(E-P1D) tsu(P1D-E) Port P1 input td(E-P2Q) Port P2 output th(E-P2D) tsu(P2D-E) Port P2 input td(E-P3Q) Port P3 output th(E-P3D) tsu(P3D-E) Port P3 input td(E-P4Q) Port P4 output th(E-P4D) tsu(P4D-E) Port P4 input td(E-P5Q) Port P5 output th(E-P5D) tsu(P5D-E) Port P5 input td(E-P6Q) Port P6 output th(E-P6D) tsu(P6D-E) Port P6 input td(E-P7Q) Port P7 output tsu(P7D-E) th(E-P7D) Port P7 input td(E-P8Q) Port P8 output tsu(P8D-E) th(E-P8D) Port P8 input Measuring conditions *VCC = 2.7 to 5.5 V *Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 7733 Group User's Manual 18-19 LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.8 Memory expansion mode and Microprocessor mode : with no wait Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Min. Max. Unit External clock input cycle time (Note 2) tc ns 83 External clock input high-level pulse width (Note 3) tw(H) 33 ns External clock input low-level pulse width (Note 3) tw(L) 33 ns External clock rise time tr ns 15 External clock fall time tf ns 15 Data input setup time tsu(D-E) 80 ns Data input hold time th(E-D) ns 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 166 ns. 3: When the main clock division selection bit = "1," values of tw(H)/t c and tw(L)/t c must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) Symbol Parameter td(An-E) Address output delay time td(A-E) Address output delay time th(E-An) Address hold time tw(ALE) ALE pulse width tsu(A-ALE) Address output setup time th(ALE-A) Conditions Data formula (Min.) 1 10 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 9 Limits Min. Typ. Unit - 63 20 ns - 63 20 ns - 43 40 ns - 43 40 ns - 73 10 ns Address hold time 9 ns td(ALE-E) ALE output delay time 4 ns td(E-DQ) Data output delay time th(E-DQ) Data hold time tw(EL) E pulse width tpxz(E-DZ) Floating start delay time tpzx(E-DZ) Floating release delay time td(BHE-E) BHE output delay time td(R/W-E) R/W output delay time th(E-BHE) BHE hold time th(E-R/W) R/W hold time td(E- 1) 1 output delay time 90 Fig. 18.4.1 1 10 2 f(f2) 2 109 2 f(f2) 9 - 43 - 35 ns 131 1 10 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 53 ns - 63 20 ns - 63 20 ns - 50 33 ns - 50 33 ns 0 7733 Group User's Manual ns - 30 Notes 1: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 18-20 ns 40 10 9 ns 30 ns LOW VOLTAGE VERSION 18.4 Electrical characteristics Memory expansion mode and Microprocessor mode : With no wait (Wait bit = "1") (Write) tw(L) (Read) tr tf tr tc tw(H) tw(L) tf tc tw(H) XIN 1 td(E-1) Address/Data output A16/D0-A23/D7, A8/D8-A15/D15 (BYTE = "L") Data input D8-D15 (BYTE = "L"), D0-D7 (BYTE = "H") td(E-1) tw(EL) E Address output A0-A7 A8-A15 (BYTE = "H") td(E-1) tw(EL) td(An-E) th(E-An) td(An-E) Address th(E-An) Address th(ALE-A) Address td(A-E) td(E-1) th(E-DQ) tpxz(E-DZ) tpzx(E-DZ) Address Data td(E-DQ) tsu(D-E) th(E-D) tsu(A-ALE) tw(ALE) tw(ALE) td(ALE-E) td(ALE-E) ALE output td(BHE-E) th(E-BHE) td(BHE-E) th(E-BHE) BHE output td(R/W-E) th(E-R/W) td(R/W-E) th(E-R/W) R/W output td(E-PiQ) Port Pi output (i = 4-8) tsu(PiD-E) th(E-PiD) Port Pi input (i = 4-8) Measuring conditions *VCC = 2.7 to 5.5 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Data input : VIL = 0.16 VCC, VIH = 0.5 VCC 7733 Group User's Manual 18-21 LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.9 Memory expansion mode and Microprocessor mode : with wait 1 Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Min. Max. Unit External clock input cycle time (Note 2) tc ns 83 External clock input high-level pulse width (Note 3) tw(H) ns 33 External clock input low-level pulse width (Note 3) tw(L) ns 33 External clock rise time tr ns 15 External clock fall time tf ns 15 Data input setup time tsu(D-E) ns 80 Data input hold time th(E-D) ns 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 166 ns. 3: When the main clock division selection bit = "1," values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) Symbol Parameter td(An-E) Address output delay time td(A-E) Address output delay time th(E-An) Address hold time tw(ALE) ALE pulse width tsu(A-ALE) Address output setup time th(ALE-A) Conditions Data formula (Min.) 1 10 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 9 Limits Min. Typ. Unit - 63 20 ns - 63 20 ns - 43 40 ns - 43 40 ns - 73 10 ns Address hold time 9 ns td(ALE-E) ALE output delay time 4 ns td(E-DQ) Data output delay time th(E-DQ) Data hold time tw(EL) E pulse width tpxz(E-DZ) Floating start delay time tpzx(E-DZ) Floating release delay time td(BHE-E) BHE output delay time td(R/W-E) R/W output delay time th(E-BHE) BHE hold time th(E-R/W) R/W hold time td(E- 1) 1 output delay time 90 Fig. 18.4.1 1 109 2 f(f2) 4 109 2 f(f2) - 43 40 ns - 35 298 ns 10 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 53 ns - 63 20 ns - 63 20 ns - 50 33 ns - 50 33 ns 0 7733 Group User's Manual ns - 30 Notes 1: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 18-22 ns 30 ns LOW VOLTAGE VERSION 18.4 Electrical characteristics Memory expansion mode and Microprocessor mode : When external memory area is accessed with wait 1 (Wait bit = "0" and Wait selection bit = "1") <Write> tw(L) tw(H) <Read> tf tr tc tw(L) tw(H) tf tr tc XIN 1 td(E-1) E td(An-E) Address output A0-A7, A8-A15 (BYTE = "H") Address/Data output A16/D0-A23/D7, A8/D8-A15/D15 (BYTE = "L") td(E-1) td(E-1) td(E-1) tw(EL) tw(EL) th(E-An) td(An-E) Address th(ALE-A) Address tsu(A-ALE) th(E-An) Address th(E-DQ) tpxz(E-DZ) Data Address td(E-DQ) tsu(D-E) Data input D8-D15 (BYTE = "L") D0-D7 (BYTE = "H") tpzx(E-DZ) td(A-E) th(E-D) td(ALE-E) tw(ALE) td(ALE-E) tw(ALE) ALE output td(BHE-E) th(E- BHE) td(BHE-E) th(E- BHE) BHE output td(R/W-E) td(R/W-E) th(E- R/W) th(E- R/W) R/W output td(E-PiQ) Port Pi output (i = 4-8) tsu(PiD-E) Port Pi input (i = 4-8) th(E-PiD) Measuring conditions * VCC = 2.7 to 5.5 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V : VIL = 0.16 VCC, VIH = 0.5 VCC * Data input 7733 Group User's Manual 18-23 LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.10 Memory expansion mode and microprocessor mode : with wait 0 Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Min. Max. Unit External clock input cycle time (Note 2) tc ns 83 External clock input high-level pulse width (Note 3) tw(H) ns 33 External clock input low-level pulse width (Note 3) tw(L) ns 33 External clock rise time tr ns 15 External clock fall time tf ns 15 Data input setup time tsu(D-E) ns 80 Data input hold time th(E-D) ns 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 166 ns. 3: When the main clock division selection bit = "1," values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) Symbol Parameter td(An-E) Address output delay time td(A-E) Address output delay time th(E-An) Address hold time tw(ALE) ALE pulse width tsu(A-ALE) Address output set up time th(ALE-A) Address hold time td(ALE-E) ALE output delay time td(E-DQ) Data output delay time th(E-DQ) Data hold time tw(EL) E pulse width tpxz(E-DZ) Floating start delay time tpzx(E-DZ) Floating release delay time td(BHE-E) BHE output delay time td(R/W-E) R/W output delay time th(E-BHE) BHE hold time th(E-R/W) R/W hold time td(E- 1) 1 output delay time Conditions Data formula (Min.) 3 10 2 f(f2) 3 109 2 f(f2) 1 109 2 f(f2) 2 109 2 f(f2) 2 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) 9 Limits Min. 182 ns - 88 162 ns - 43 40 ns - 43 123 ns - 73 93 ns - 43 40 ns - 43 40 ns 90 Fig. 18.4.1 1 10 2 f(f2) 4 109 2 f(f2) 9 40 ns - 35 298 ns ns - 30 53 ns - 68 182 ns - 68 182 ns - 50 33 ns - 50 33 ns 0 7733 Group User's Manual ns - 43 10 1 109 2 f(f2) 3 109 2 f(f2) 3 109 2 f(f2) 1 109 2 f(f2) 1 109 2 f(f2) Unit - 68 Notes 1: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 2: f(f2) represents the clock f2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 18-24 Typ. 30 ns LOW VOLTAGE VERSION 18.4 Electrical characteristics Memory expansion mode and Microprocessor mode : When external memory area is accessed with wait 0 (Wait bit = "0" and Wait selection bit = "0") <Write> <R ead> tw(L) tw(H) tf tr tc tw (L) tw (H ) tf tr tc XIN 1 td(E-1) td(E-1) td(E- 1) tw(EL) td(E- 1) tw (EL) E td(An-E) Address output A0-A7, A8-A15 (BYTE = "H") Address/Data output A16/D0-A23/D7, A8/D8-A15/D15 (BYTE = "L") td(An-E) Address Address th(E-DQ) Data tpxz( E-D Z) tpzx( E-D Z) tsu( D-E) th(E-D ) Address td(E-DQ) td(A-E) tw(ALE) th(E-An) Address th(ALE-A) tsu(A-ALE) Data input D8-D15 (BYTE = "L") D0-D7 (BYTE = "H") th(E-An) tw (ALE) td(ALE-E) td(ALE-E) ALE output td(BHE-E) th(E-BHE) td(BH E-E) th(E-R/W) td(R /W-E) th(E-BH E) BHE output td(R/W-E) th(E-R /W ) R/W output td(E-PiQ) Port Pi output (i = 4-8) tsu(PiD-E) Port Pi input (i = 4-8) th(E-PiD) Measuring conditions *VCC = 2.7 to 5.5 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Data input : VIL = 0.16 VCC, VIH = 0.5 VCC 7733 Group User's Manual 18-25 LOW VOLTAGE VERSION 18.4 Electrical characteristics __ 18.4.11 Measuring circuit for ports P0 to P8 and pins 1 and E P0 P1 P2 P3 P4 P5 P6 P7 P8 1 50 pF E _ Fig. 18.4.1 Measuring circuit for ports P0 to P8 and pins 1 and E 18-26 7733 Group User's Manual LOW VOLTAGE VERSION 18.5 Standard characteristics 18.5 Standard characteristics Standard characteristics described below are just examples of the M37733MHLXXXHP's characteristics and are not guaranteed. For rated values, refer to section "18.4 Electrical characteristics." 18.5.1 Programmable I/O port (CMOS output) standard characteristics: Ports P0 to P3, P4 0 -P4 3 , P5 4-P5 7, P6, P7, and P8 (1) P-channel I OH-VOH characteristics Power source voltage Vcc = 3 V P-channel 20.0 IOH [mA] 16.0 12.0 Ta = 25 C 8.0 Ta = 85 C 4.0 0 0.6 1.2 1.8 2.4 3.0 VOH [V] (2) N-channel IOL-VOL characteristics Power source voltage Vcc = 3 V N-channel 20.0 IOL [mA] 16.0 12.0 Ta = 25 C 8.0 Ta = 85 C 4.0 0 0.6 1.2 1.8 2.4 3.0 VOL [V] 7733 Group User's Manual 18-27 LOW VOLTAGE VERSION 18.5 Standard characteristics 18.5.2 Programmable I/O port (CMOS output) standard characteristics: Ports P4 4 to P4 7 and P5 0 to P5 3 (1) P-channel I OH-V OH characteristics Power source voltage Vcc = 3 V P-channel 20.0 IOH [mA] 16.0 12.0 Ta = 25 C 8.0 Ta = 85 C 4.0 0 0.6 1.2 1.8 2.4 3.0 VOH [V] (2) N-channel IOL-V OL characteristics Power source voltage Vcc = 3 V N-channel 20.0 IOL [mA] 16.0 Ta = 25 C 12.0 Ta = 85 C 8.0 4.0 0 0.6 1.2 1.8 VOL [V] 18-28 7733 Group User's Manual 2.4 3.0 LOW VOLTAGE VERSION 18.5 Standard characteristics 18.5.3 Icc-f(XIN) standard characteristics (1) Icc-f(XIN ) characteristics on operating and at reset *Measuring conditions (Vcc = 3 V, Ta = 25 C, f(XIN):square waveform input, single-chip mode) *Register setting conditions Oscillation circuit control register 1 = "0216" (Main clock is input from the external.) 4 Icc [mA] 3 On operating (CPU + peripheral devices) 2 On operating (CPU) 1 0 0 2 4 6 8 10 12 14 f(XIN) [MHz] (2) Icc-f(X IN) characteristics during wait mode *Measuring conditions (Vcc = 3 V, Ta = 25 C, f(XIN):square waveform input, single-chip mode) *Register setting conditions Oscillation circuit control register 0 = "2016" (In wait mode, clocks f2 to f512 are stopped.) Oscillation circuit control register 1 = "0216" (Main clock is input from the external.) or "0016" (Main-clock oscillation circuit is operating by itself.) 1 0.8 Icc [mA] CC1 = 0 0.6 0.4 0.2 CC1 = 1 0 0 2 4 6 8 10 12 14 f(XIN) [MHz] CC1 : Main clock external input selection bit (bit 1 of oscillation circuit control register 1) 7733 Group User's Manual 18-29 LOW VOLTAGE VERSION 18.5 Standard characteristics 18.5.4 A-D converter standard characteristics The lower line of the graph indicate the absolute precision errors. These are expressed as the deviation from the ideal value when the output code changes. For example, the change in output code from "0E16" to "0F16" should occur at 36.25 mV, but the measured value is 0.3 mV. Accordingly, the measured point of change is 36.25 + 0.3 = 36.55 mV. The upper line of the graph indicate the input voltage width for which the output code is constant. For example, the measured input voltage width for which the output code is "0F16" is 2.2 mV. Accordingly, the differential non-linear error is 2.2 - 2.5 = -0.3 mV (-0.12 LSB). [Measuring conditions] *Vcc = AVcc = 3 V, *V REF = 2.56 V, *f(X IN ) = 12 MHz, *Temp. = 25 C 18-30 7733 Group User's Manual LOW VOLTAGE VERSION 18.5 Standard characteristics 7733 Group User's Manual 18-31 LOW VOLTAGE VERSION 18.6 Applications 18.6 Applications Some application examples of connecting external memorys for the low voltage version are described bellow. Applications shown here are just examples. Modify the desired application to suit the user's need and make sufficient evaluation before actually using it. 18.6.1 Memory expansion The following items of the low voltage version are the same as section "17.1 Memory expansion," but a part of the calculation way and constants for parameters is different: *Memory expansion model *Calculation way for address access time of external memory *Bus timing *Memory expansion way Address access time of external memory ta(AD) t a(AD) = t d(A-E) + t w(EL) - t su(D-E) - (address decode time 1 + address latch delay time2) address decode time1 : time necessary for validating a chip select signal after an address is decoded address latch delay time2 : delay time necessary for latching an address (This is not necessary on the minimum model.) Data setup time of external memory for writing data t su(D) t su(D) = t w(EL) - td(E-DQ) Table 18.6.1 lists the calculation formulas and constants for each parameter of the low voltage version. Figure 18.6.1 shows the relationship between ta(AD) and 2 f(f 2 ). Figure 18.6.2 shows the relationship between tsu(D) and 2 f(f 2). Table 18.6.1 Calculation formulas and constants for each parameter (Unit : ns) Software wait Wait bit Wait selection bit td(A-E) tw(EL) Wait 1 0 1 No wait 1 0 or 1 Wait 0 0 0 3 109 - 88 2f(f2) 1 109 - 63 2 f(f2) 2 109 - 35 2f(f2) tsu(D-E) 4 109 - 35 2 f(f2) 80 90 10 1 109 - 30 2 f(f2) tsu(E-DQ) tpxz(E-DZ) tpzx(E-DZ) Wait bit : Bit 2 at address 5E 16 Wait selection bit : Bit 0 at address 5F16 Note: This is applied to the case where the system clock selection bit (bit 3 at address 6C 16 ) = "0." 18-32 7733 Group User's Manual LOW VOLTAGE VERSION 18.6 Applications [ns] 3500 3297 3000 Memory access time ta(AD) No wait Wait 1 is valid. Wait 0 is valid. 2500 2322 2130 2000 1488 1547 1500 1322 1197 1072 1000 822 963 822 797 655 572 536 422 500 322 250 672 447 574 497 377 197 322 155 122 8 9 433 380 276 94 238 72 0 2 3 4 5 6 7 10 11 12 [MHz] External clock input frequency 2 f(f2) Address decode time and address latch delay time are not considered. Fig. 18.6.1 Relationship between ta(AD) and 2 f(f2) [ns] 2000 1875 1800 No wait Data setup time tsu(D) 1600 Wait 1 or Wait 0 is valid. 1400 1208 1200 1000 875 875 800 675 541 600 541 446 375 400 275 208 200 160 375 125 319 275 238 208 97 75 56 41 9 10 11 12 0 2 3 4 5 6 7 8 External clock input frequency 2f(f2) [MHz] Fig. 18.6.2 Relationship between tsu(D) and 2 f(f2) 7733 Group User's Manual 18-33 LOW VOLTAGE VERSION 18.6 Applications 18.6.2 Memory expansion example on minimum model Figure 18.6.3 shows a memory expansion example on the minimum model (with external RAM) and Figure 18.6.4 shows the corresponding timing diagram. In example, an Atmel company's EPROM (AT27LV256R) is used as the external ROM. In Figure 18.6.3, the circuit condition is "No wait." M37733S4LHP AC32 1 A15 BYTE AC04 2 AT27LV256R-15DI CE M5M5256CFP-10VLL S A0 to A14 A0 to A14 D0 to D7 D0 to D 7 A0 to A 14 DQ1 to DQ 8 Memory map OE W 000016 008016 Open BHE AC04 XIN OE Internal RAM area 088016 External RAM area 3 R/W RD E WR X OUT SFR area AC32 (M5M5256CFP) 800016 External ROM area 1 (AT27LV256R) FFFF16 8 MHz Circuit conditions : No wait, Vcc = 3.3 0.3 V 1 2 3 1= f(XIN) 2 f(XIN) 8 , f(XIN) 16 Make sure that the propagation delay time is 35 ns or less. Make sure that the propagation delay time is 47 ns or less. Make sure that the propagation delay time is 62 ns or less. Fig. 18.6.3 Memory expansion example on minimum model 18-34 , 7733 Group User's Manual , or f(XCIN) 2 LOW VOLTAGE VERSION 18.6 Applications At reading 215 (min.) E 62 (min.) A1 to A14 A A 95 (min.) 10 (max.) A A D0 to D7 ta(AD) CE ta(CE) AC04 (tPHL) S, OE AC32 (tPHL) AC32 (tPLH) ta(S), ta(OE) ROM : 25 (max.) RAM : 30 (max.) External memory data output D tsu(P2D-E) 80 At writing 215 (min.) E 62 (min.) A1 to A14 A A 90 (max.) D0 to D7 A 82 (min.) D AC32 (tPHL) tsu(D) 40 A AC32 (tPLH) S, W (Unit : ns) Fig. 18.6.4 Timing diagram on minimum model 7733 Group User's Manual 18-35 LOW VOLTAGE VERSION 18.6 Applications 18.6.3 Memory expansion example on medium model A Figure 18.6.5 shows a memory expansion example on the medium model A. Figure 18.6.6 shows the corresponding timing diagram. M37733MHLXXXHP M5M51008AFP-10VLL BYTE A0 to A15 CNVSS A0 to A16 D 0-D7 AC573 A16/D0 to A 23/D7 D Q DQ1 to DQ 8 A16 S1 S2 A17 LE ALE BHE OE W Memory map 000000 16 SFR area 000080 16 Internal RAM area 000FFF 16 Open E Internal ROM area R/W XIN 01FFFF 16 020000 16 XOUT External ROM area 10 MHz VCC = 3.3 0.3 V 03FFFF 16 (M5M51008AFP) Circuit conditions : No wait 1= f(XIN) 2 , f(XIN) f(XIN) , 16 8 , or Make sure that the propagation delay time is 22 ns or less. Fig. 18.6.5 Memory expansion example on medium model A 18-36 7733 Group User's Manual f(XCIN) 2 LOW VOLTAGE VERSION 18.6 Applications At reading 165 (min.) E, OE, S1 37 (min.) A0 to A15 A A 10 (max.) A16/D0 to A23/D7 A A ta(A) + AC573 70 (min.) AC573 (tPHL) A16, A17, S2 AC573 (tPLH) ta(S2) 35 (max.) External memory data output D tsu(P1D/P2D-E) 80 ta(OE), ta(S1) At writing 165 (min.) E, OE, S1 37 (min.) A0 to A15 A A16/D0 to A23/D7 A 90 (max.) A D tsu(D) 40 A 57 (min.) AC573 (tPHL) A16, A17, S2 R/W, WE (Unit : ns) Fig. 18.6.6 Timing diagram on medium model A 7733 Group User's Manual 18-37 LOW VOLTAGE VERSION 18.6 Applications 18.6.4 Memory expansion example on maximum model Figure 18.6.7 shows a memory expansion example on the maximum model. Figure 18.6.8 shows the corresponding timing diagram. In this example, Atmel company's EPROMs (AT27LV256R) are used as the external ROMs. In Figure 18.6.7, the circuit condition is "No wait." AT27LV256R-15DI M37733S4LHP Address bus A1 to A7 BYTE M5M51008AFP-10VLL AC04 AC32 1 AC573 A8/D8 to A15/D15 D Q A16/D0 S1 A0 to A14 A1 to A15 A0 to A14 to A17/D1 A0 to A15 A0 to A15 A1 to A16 A16 A16 A17 D8 to D15 D0 to D7 D8 to D15 D0 to D7 OE D0 to D7 D0 to D7 DQ1 to DQ8 OE OE W Odd data bus D2 to D7 S2 A1 to A16 A1 to A15 A16 D Q S1 S2 LE ALE LE CE CE A8 to A16 DQ1 to DQ8 OE W Even data bus AC04 3 R/W AC32 2 RD E WE A0 WO Memory map BHE XIN 00000016 00008016 AC32 2 XOUT 8 MHz 00088016 00FFFF16 Vcc = 3.3 0.3 V f(XIN) f(XIN) , 8 2 IN) , f(X , or 16 1 Make sure that the propagation delay time is 47 ns or less. 2 Make sure that the propagation delay time is 50 ns or less. 3 Make sure that the propagation delay time is 62 ns or less. Fig. 18.6.7 Memory expansion example on maximum model 18-38 External ROM area (AT27LV256R 2) Not used Circuit conditions : No wait 1= SFR area Internal RAM area 7733 Group User's Manual f(XCIN) 2 02000016 External RAM area 03FFFF16 (M5M51008AFP 2) LOW VOLTAGE VERSION 18.6 Applications At reading 215 (min.) E 62 (min.) A1 to A7 A A 10 (max.) A8/D8 to A15/D15 A16/D0 A A 95 (min.) AC573 (tPHL) CE, S1 AC04 (tPHL) S1 CE AC32 (tPLH) ta(S1) OE AC32 (tPHL) ROM : 25 (max.) RAM : 35 (max.) ta(OE) External memory data output D tsu(P1D/P2D-E) 80 ta(AD), ta(CE) At writing 215 (min.) E 62 (min.) A1 to A7 A8/D8 to A15/D15 A16/D0, D1 to D7 A A D tsu(D) 40 90 (max.) AC32 (tPHL) W A A 82 (min.) AC32 (tPLH) AC573 (tPHL) + AC04 (tPHL) S1 (U nit : ns) Fig. 18.6.8 Timing diagram on maximum model 7733 Group User's Manual 18-39 LOW VOLTAGE VERSION 18.6 Applications 18.6.5 Ready generating circuit example When validating "wait" only for a certain area (for example, ROM area) in Figures 18.6.3 to 18.6.8, use the ready function. Figure 18.6.9 shows a ready generating circuit example. M37733MHLXXXHP A8 to A 23 (D0 to D15) Data bus Address decode circuit Address latch circuit CS1 CS2 Address bus A0 to A7 RDY AC32 AC74 E AC32 D Q T 1 Wait generated by the ready function is inserted only to an area where accessed by Signal CS 2. AC04 Circuit conditions : f(X IN) 10.8 MHz, no wait, VCC = 3.0 to 5.5 V 1= td(E- 1) f(XIN) f(XIN) f(XIN) f(XCIN) 2 2 , 8 , 16 , or tc 1 1 E CS2 Q RDY tsu(RDY- 1) Condition to satisfy the relationship of tsu(RDY- 1) 80 ns in the left timing chart is tc 91.9 ns. Accordingly, when f(X IN) 10.8 MHz, this example satisfies the relationship of tsu(RDY- 1) 80 ns. : Wait generated by the ready function Propagation delay time of AC32 (Max. : 11.9 ns) Fig. 18.6.9 Ready generating circuit example 18-40 7733 Group User's Manual CHAPTER 19 BUILT-IN PROM VERSION 19.1 EPROM mode 19.2 Usage precaution BUILT-IN PROM VERSION In the PROM version, programming to the built-in PROM is possible by using a general-purpose PROM programmer and a programming adapter which is suitable for the microcomputer. The built-in PROM version has the following two types : One Time PROM version Programming to the PROM is possible once. This version is suitable for a small quantity of and various production. EPROM version Programming to the PROM is possible repeatedly because a program can be erased by exposing the erase window on the top of the package to an ultraviolet light source. This version can be used only for program development (Evaluation only). The built-in PROM version differs from the mask ROM version in the following: * The built-in PROM version has a built-in PROM. * Bit 3 of the oscillation circuit control register 1 (address 6F 16) of the built-in PROM version is "1" at reset. * Bit 3 of the oscillation circuit control register 1 (address 6F 16) of the built-in PROM version must be fixed to "1." 19-2 7733 Group User's Manual BUILT-IN PROM VERSION 19.1 EPROM mode 19.1 EPROM mode The built-in PROM version has the following two modes : Normal operating mode The microcomputer has the same function as the mask ROM version. EPROM mode Programming to the built-in PROM can be performed. The built-in PROM version enters this mode ______ when "L" level is input to pin RESET. 19.1.1 Pin description Table 19.1.1 lists the pin description in the EPROM mode. In the normal operating mode, each pin has the same function as the mask ROM version. Table 19.1.1 Pin description in EPROM mode Pin Name Input/Output -- Functions Vcc, Vss Power source input Apply 5 V 10% to pin Vcc, and 0 V to pin Vss. CNVss V PP input Input Apply V PP level when programming or verifying. RESET Reset input Input Connect to pin Vss. XIN Clock input Input XOUT Clock output Connect pins XIN and XOUT via a ceramic resonator or a quartz-crystal oscillator. When an external clock is used, the clock should be input to pin X IN, and pin X OUT should be left open. Open. BYTE ______ Enable output AVcc, AVss Analog power source input E Output Output -- Connect pin AVcc to pin Vcc and pin AVss to pin Vss. Reference voltage input Input Connect to pin Vss. P0 0-P07 Address input (A 0-A 7) Input Input pins for low-order 8 bits (A0-A 7) of address P1 0-P17 P2 0-P27 Address input (A 8-A 15) Data input/output (D 0-D 7) Input I/O Input pins for middle-order 8 bits (A8-A15) of address P3 0 Address input (A 16) Input I/O pins for 8-bit data (D 0 -D 7) Input pin for the most significant bit (A16) address P3 1-P33 Input port P3 Input Connect to pin Vss. P4 0-P47 Input port P4 Input Connect to pin Vss. P5 0-P57 Control input Input P5 0 , P5 1 and P5 2 respectively function as PGM, ___ ___ OE and CE input pins. Connect P5 3 -P5 6 to pin Vcc, and P57 to pin Vss. P6 0-P67 Input port P6 Input Connect to pin Vss. P7 0-P77 Input port P7 Input P8 0-P87 Input port P8 Input Connect to pin Vss. Connect to pin Vss. VREF _____ 7733 Group User's Manual 19-3 BUILT-IN PROM VERSION 19.1 EPROM mode 19.1.2 Reading/Programming from and to built-in PROM In the EPROM mode, ports P0, P1, P2, P30, P5 0 , P51 , P52 and pins CNVss and BYTE are EPROM pins (M5M27C101K equivalent), and reading/programming from and to the built-in PROM can be performed in the same manner as for M5M27C101K. However, there is no device identification code. Accordingly, programming conditions must be set carefully. Furthermore, specify addresses from 0100016 to 1FFFF 16 as the programmable area. Table 19.1.2 lists the pin correspondence in the EPROM mode and Table 19.1.3 lists the programmable area. Figures 19.1.1 and 19.1.2 show the pin connections in the EPROM mode. Table 19.1.2 Pin correspondence in EPROM mode Vcc V PP Vss Address input M37733EHBFP(M37733EHBXXXFP) M37733EHBFS M37733EHLHP(M37733EHLXXXHP) Vcc CNVss, BYTE Vss P0, P1, P3 0 P2 P52 P51 P50 Data I/O CE OE PGM M5M27C101K Vcc VPP Vss A 0-A 16 D0 -D 7 CE OE PGM Table 19.1.3 Programmable area Memory allocation selection bits Programmable area b2 0 0 0 1 b1 0 b0 0 0100016 -1FFFF 16 0 1 0200016 -1FFFF 16 1 0 0100016 -0FFFF 16 0 0 0800016 -0FFFF 16 1 0 1 0C000 16-0FFFF 16 1 1 0 0800016 -1FFFF 16 Note: When changing the allocation of the internal memory by the memory allocation selection bits (Refer to Figure 2.4.1.), specify addresses listed in Table 19.1.3 as the programmable area. 19-4 7733 Group User's Manual BUILT-IN PROM VERSION 19.1 EPROM mode P71/AN1 P72/AN2 /CTS2 P73/AN3 /CLK2 P74 /AN4/RxD2 P75/AN5 /ADTRG /TxD2 P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80 /CTS0 /RTS0/CLKS1 P81/CLK0 P82/RxD0/CLKS 0 P83/TxD0 VCC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 OE PGM 1 64 2 63 3 62 4 61 5 60 6 59 7 58 M37733EHBFP CE P70/AN0 P67/TB2IN / SUB P66/TB1IN P65/TB0IN P64/INT 2 P63/INT 1 P62/INT 0 P61/TA4IN P60/TA4OUT P57/TA3IN /KI3 P56/TA3OUT /KI2 P55/TA2IN /KI1 P54/TA2OUT /KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 P42/ 1 P41/RDY 8 9 10 11 12 13 14 15 16 17 57 56 55 54 53 52 51 50 49 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 P84/CTS1/RTS1 P85 /CLK1 P86/RxD1 P87/TxD1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10 /A8 /D8 P11 /A9 /D9 P12 /A10 /D10 P13 /A11 /D11 P14 /A12 /D12 P15 /A13 /D13 P16/A14 /D14 P17/A15 /D15 P20/A16 /D0 P21/A17 /D1 P22/A18 /D2 P23/A19 /D3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 * A16 D7 D6 D5 D4 VPP P40/HOLD BYTE CNVSS RESET XIN XOUT E VSS P33/HLDA P32 /ALE P31/BHE P30/R/W P27/A23 /D7 P26/A22 /D6 P25/A21 /D5 P24/A20 /D4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VSS * : Connect these pins to a resonator or an oscillator. : EPROM pin. Outline 80P6N-A Fig. 19.1.1 Pin connections in EPROM mode (M37733EHBFP) 7733 Group User's Manual 19-5 BUILT-IN PROM VERSION 19.1 EPROM mode P67/TB2IN/ SUB P70/AN0 P71/AN1 P72/AN2/CTS2 P73/AN3/CLK2 P74/AN4/RxD2 P75/AN5/ADTRG/TxD2 P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RXD0/CLKS0 P83/TXD0 P84/CTS1/RTS1 P85/CLK1 VCC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 OE PGM 1 60 2 59 3 58 4 57 5 56 M37733EHLHP CE P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 6 7 8 9 10 11 12 13 14 15 55 54 53 52 51 50 49 48 47 46 16 45 17 44 18 43 19 42 20 41 P86/RXD1 P87/TXD1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D7 D6 D5 D4 D3 D2 A16 VPP P42/ 1 P41/RDY P40/HOLD BYTE CNVSS RESET XIN XOUT E VSS P33/HLDA P32/ALE P31/BHE P30/R/W P27/A23/D7 P26/A22/D6 P25/A21/D5 P24/A20/D4 P23/A19/D3 P22/A18/D2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 * VSS * : Connect these pins to a resonator or an oscillator. : EPROM pin. Outline 80P6D-A Fig. 19.1.2 Pin connections in EPROM mode (M37733EHLHP) 19-6 7733 Group User's Manual BUILT-IN PROM VERSION 19.1 EPROM mode (1) Read ___ ___ When pins CE and OE are set to "L" level and an address is input to address input pins, the contents ___ ___ of the built-in PROM can be read from data I/O pins; When pins CE and OE are set to "H" level, data I/O pins enter the floating state. (2) Program ___ ___ When pin CE is set to "L" level, pin OE is set to "H" level, and V PP level is applied to pin V PP , programming to the PROM can be performed. Input an address to address input pins and supply data to be programmed to data I/O pins in 8-bit ____ parallel. On this condition, when pin PGM is set to "L" level, the data is programmed into the built-in PROM. (3) Erase (Available only in EPROM version) The contents of the built-in PROM is erased by exposing the glass window on top of the package to an ultraviolet light which has a wave length of 2537 Angstrom. The light must be 15 W*s/cm2 or more. Table 19.1.4 I/O signals in EPROM mode Pin name CE OE PGM VPP Vcc Data I/O Read-out VIL VIL X 5 V 5 V Output Output disable VIL VIH VIH X X X 5 V 5 V 5 V Floating Floating Program VIL VIH VIL 12.5 V 6 V Input Program verify VIL VIL VIH 12.5 V 6 V Output VIH or V IH. VIH VIH 12.5 V 6 V Floating Mode Program disable X : It may be V IL 7733 Group User's Manual 5 V 19-7 BUILT-IN PROM VERSION 19.1 EPROM mode 19.1.3 Programming algorithm to built-in PROM Set Vcc = 6 V, V PP = 12.5 V, and address to 01000 16. (Refer to Table 19.1.3.) After applying a programming pulse of 0.2 ms, check whether data can be read or not. If the data cannot be read, apply a programming pulse of 0.2 ms again. Repeat the procedure, which consists of applying a programming pulse of 0.2 ms and read check, until the data can be read. Additionally, record the number of pulses applied ( X ) before the data was read. Apply X pulses (0.2 X ms) (described in ) as additional programming pulses. When this procedure ( to ) is complete, increment the address and repeat the above procedure until the last address is reached. After programming to the last address, read data when Vcc = V PP = 5 V (or Vcc = VPP = 5.5 V). Figure 19.1.3 shows the programming algorithm flow chart. START ADDR = FIRST LOCATION VCC = 6.0 V VPP = 12.5 V X=0 PROGRAM ONE PULSE OF 0.2 ms X=X+1 X = 25? YES NO FAIL VERIFY BYTE VERIFY BYTE FAIL DEVICE FAILED PASS PASS PROGRAM PULSE OF 0.2 x ms DURATION INCREMENT ADDR NO LAST ADDR? YES VCC = VPP = *5.0 V VERIFY ALL BYTE FAIL DEVICE FAILED PASS DEVICE PASSED * : 4.5 V VCC = V PP 5.5 V Fig. 19.1.3 Programming algorithm flow chart 19-8 7733 Group User's Manual BUILT-IN PROM VERSION 19.1 EPROM mode 19.1.4 Electrical characteristics of programming algorithm AC electrical characteristics (Ta = 25 5 C, Vcc = 6 V 0.25 V, VPP = 12.5 0.3 V, unless otherwise noted) Symbol Limits Parameter Min. tAS Address setup time 2 tOES OE setup time 2 tDS tAH Data setup time Address hold time 2 tDH Data hold time tDFP Output floating delay time after OE 0 tVCS Vcc setup time 2 tVPS V PP setup time 2 ____ 0.19 PGM pulse width ____ 0.19 2 Additional PGM pulse width ___ tCES CE setup time ___ tOE Max. 0 2 ___ tPW tOPW Typ. 130 0.2 0.21 5.25 150 Data delay time after OE Unit s s s s s ns s s ms ms s ns Programming timing diagram Program Verify VIH Address VIL t AS t AH VIH/VOH Data Data set VIL/VOL t DS Data output valid tDH tDFP VPP V PP VCC VCC + 1 V CC tVPS tVCS VCC VIH CE VIL tCES VIH PGM tOES tOE VIL tPW OE VIH tOPW VIL Switching characteristics measuring conditions Input voltage : V IL = 0.45 V, V IH = 2.4 V Input signal rise/fall time (10%-90%) : 20 ns Reference voltage in timing measurement : Input/output "L" = 0.8 V, "H" = 2 V 7733 Group User's Manual 19-9 BUILT-IN PROM VERSION 19.2 Usage precaution 19.2 Usage precaution [Precautions on all built-in PROM versions] When programming to the built-in PROM, high voltage is required. Accordingly, be careful not to apply excessive voltage to the microcomputer. Furthermore, be especially careful during power-on. [Precautions on One Time PROM version] One Time PROM versions shipped in blank (M37733EHBFP, M37733EHLHP), of which built-in PROMs are programmed by users, are also provided. For these microcomputers, a programming test and screening are not performed in the assembly process and the following processes. To improve their reliability after programming, we recommend to program and test as the flow shown in Figure 19.2.1 before use. Programming with PROM programmer Screening (Note) (Leave at 150 C for 40 hours) Verify test with PROM programmer Function check in target device Note: Never expose to 150 C exceeding 100 hours. Fig. 19.2.1 Programming and test flow for One Time PROM version [Precautions on EPROM version] Cover the transparent glass window with a shield or others during the read mode because exposing to sun light or fluorescent lamp can cause erasing the programmed data. A shield to cover the transparent window is available from Mitsubishi Electric Corporation. Be careful that the shield does not touch the EPROM lead pins. Clean the transparent glass before erasing. There is a possibility that fingers' flat and paste disturb the passage of ultraviolet rays and affect badly the erasure capability. The EPROM version is a tool only for program development (Evaluation only), and do not use it for the mass product run. 19-10 7733 Group User's Manual CHAPTER 20 EXTERNAL ROM VERSION 20.1 Performance overview 20.2 Pin configuration 20.3 Pin description 20.4 Block description 20.5 Memory allocation 20.6 Processor modes 20.7 Timer A 20.8 Reset 20.9 Electrical characteristics 20.10 Low voltage version EXTERNAL ROM VERSION The external ROM version can operate only in the microprocessor mode. Functions of the external ROM version differ from those of the mask ROM version in the following. Therefore, only the differences are described in this chapter: * Memory allocation * Operation is available only in the microprocessor mode * The ROM area change function is not available. * Timer A has the pulse output port mode. * Power source current and Current consumption For the other functions, refer to chapters "2. CENTRAL PROCESSING UNIT (CPU)" to "18. LOW VOLTAGE VERSION." For product expansion information of the 7733 Group, contact the appropriate office, as listed in "CONTACT ADDRESSES FOR FURTHER INFORMATION." 20-2 7733 Group User's Manual EXTERNAL ROM VERSION 20.1 Performance overview 20.1 Performance overview Performance overview of the external ROM version differs from that of the mask ROM version in the following: memory size and current consumption. For the other items, refer to section "1.1 Overview." Table 20.1.1 lists the M37733S4BFP's performance overview. Table 20.1.1 M37733S4BFP's performance overview Memory size Current consumption Items RAM Performance 2048 bytes 57 mW (When f(X IN ) = 25-MHz external square wave input, Vcc = 5 V, and the main clock is the system clock, Typ.) 300 W (When f(X CIN ) = 32 kHz, Vcc = 5 V, the sub clock is the system clock, and the main clock is stopped, Typ.) 7733 Group User's Manual 20-3 EXTERNAL ROM VERSION 20.2 Pin configuration 20.2 Pin configuration P71/AN1 P72/AN2/CTS2 P73/AN3/CLK2 P74/AN4/RXD2 P75/AN5/ADTRG/TXD2 P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RXD0/CLKS0 P83/TXD0 Figure 20.2.1 shows the M37733S4BFP pin configuration. Note: For the low voltage version, refer to section "20.10 Low voltage version." 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 64 2 63 3 62 4 61 5 60 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 M37733S4BFP P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3/RTP13 P56/TA3OUT/KI3/RTP12 P55/TA2IN/KI1/RTP11 P54/TA2OUT/KI0/RTP10 P53/TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P47 P46 P45 P44 P43 (P42)/ 1 RDY 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 21 44 22 43 23 42 24 41 P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 A0 (P00) A1 (P01) A2 (P02) A3 (P03) A4 (P04) A5 (P05) A6 (P06) A7 (P07) A8 /D8(P10) A9 /D9(P11) A10 /D10(P12) A11/D11(P13) A12/D12(P14) A13/D13(P15) A14/D14(P16) A15/D15(P17) A16/D0(P20) A17/D1(P21) A18/D2(P22) A19/D3(P23) HOLD BYTE CNVSS RESET XIN XOUT E Vss (P33)HLDA (P32)ALE (P31)BHE (P30)R/W (P27)A23/D7 (P26)A22/D6 (P25)A21/D5 (P24)A20/D4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Outline 80P6N-A Fig. 20.2.1 M37733S4BFP pin configuration (Top view) 20-4 7733 Group User's Manual By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin's level can be fixed in the stop or wait mode. EXTERNAL ROM VERSION 20.3 Pin description 20.3 Pin description Tables 20.3.1 and 20.3.2 list the pin description. Table 20.3.1 Pin description (1) Pin Vcc, Vss Name Power source input CNVss RESET CNVss Reset input Input Input XIN Clock input Input XOUT Clock output Output E Enable output Output BYTE External data bus width selection input AVcc Analog power source input ______ Input/Output _ Input AVss VREF Reference voltage input A 0 (P0 0)- A 7 (P0 7) A8 /D8 (P1 0)-A 15/ D 15 (P17) Address (low order) output Output Address (middle order) output/Data (high order) I/O I/O Address (high order) output/ A16/D0 (P20)-A23/ Data (low-order) I/O D 7 (P2 7) I/O Input Functions To pin Vcc, apply 5 V10% (When the main clock is the system clock) or 2.7 V to 5.5 V (When the subclock is the system clock). To pin Vss, apply 0 V. Connect to pin Vcc. The microcomputer is reset when "L" level is input to this pin. Pins X IN and X OUT are the I/O pins of the clock generating circuit, respectively. Connect these pins via a ceramic resonator or a quartz-crystal oscillator. When an external clock is used, the clock should be input to pin X IN, and pin X OUT should be left open. _ _ This pin outputs signal E . When E 's level is "L," the microcomputer reads data and instruction codes or writes _ data. Also, output of signal E can be stopped by software. Input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. A 16-bit width is selected when the level is "L," and an 8-bit width is selected when the level is "H." Power source input for the A-D converter. Connect to pin Vcc. Power source input for the A-D converter. Connect to pin Vss. This is the reference voltage input pin for the A-D converter. Address's low-order 8 bits (A0-A7) are output. When the external data bus width = 8 bits (Pin BYTE is at "H" level) Address's middle-order 8 bits (A8-A 15) are output. When the external bus width = 16 bits (Pin BYTE is at "L" level) Input/Output of data (D8-D15) and output of address's middle-order 8 bits (A8-A15) are performed with the time sharing method. Input/Output of data (D0-D7 ) and output of address's high-order 8 bits (A16-A23) are performed with the time sharing method. 7733 Group User's Manual 20-5 EXTERNAL ROM VERSION 20.3 Pin description Table 20.3.2 Pin description (2) Pin Name __ R/ W (P30), Read write output, ____ BHE (P3 1), Byte high enable output, ALE (P3 2), Address latch enable _____ HLDA (P33) output, Input/Output Output Hold acknowledge output _____ HOLD , 1(P42), P4 3-P47 Hold request, Ready, Clock output, I/O port P4 P5 0-P57 I/O port P5 I/O P6 0-P67 I/O port P6 I/O P7 0-P77 I/O port P7 I/O P8 0-P87 I/O port P8 I/O ____ RDY , 20-6 Input Input Output I/O Functions __ ____ These pins respectively output signals R/W, BHE, ALE, _____ and HLDA . __ Signal R/ W This signal indicates the data bus state. When this signal level is "H," a data bus is in the read state. When this signal level is "L," a data bus is in the write state. ____ Signal BHE This signal's level is "L" when the microcomputer accesses an odd address. Signal ALE This signal is used to separate the multiplexed signal which consists of an address and data to the address and the data. _____ Signal HLDA This signal informs the external whether the microcomputer enters the Hold state or not. _____ In Hold state, pin HLDA outputs "L" level. _____ The microcomputer is in Hold state while pin HOLD 's ____ input level is "L" and is in Ready state while pin RDY's input level is "L." Clock 1 is output from pin 1. P4 3-P4 7 function as I/ O ports with the same functions as port P5. P5 is a CMOS 8-bit I/O port and has an I/O direction register. Each pin can be programmed as an input port or an output port. And it can be programmed as I/O pins for timers A0-A3 and input pins ( KI 0- KI 3) for the key input interrupt. P6 is an 8-bit I/O port with the same function as port P5 and can be programmed as I/O pins for timer A4, external interrupt input pins, and input pins for timers B0-B2. P67 also functions as an output pin for the sub clock ( SUB). P7 is an 8-bit I/O port with the same function as port P5 and can be programmed as analog input pins for the A-D converter. P7 6 and P7 7 can be programmed as I/O pins (X COUT , X CIN ) for the sub-clock (32 kHz) oscillation circuit. When using P7 6 and P7 7 as pins X COUT and X CIN , connect a quartz-crystal oscillator between them. P72-P75 also function as UART2's I/O pins. P8 is an 8-bit I/O port with the same function as port P5 and can be programmed as serial I/O's I/O pins. 7733 Group User's Manual EXTERNAL ROM VERSION 20.4 Block description 20.4 Block description Stack Pointer S(16) Timer TA4(16) P4 (5) A-D Converter(10) UART1 (9) UART2 (9) Address bus Address bus/ Data bus Input/Output port P7 Input/Output port P8 P8 (8) Anthmetic Logic Unit(16) P7 (8) RAM 2048 bytes Accumulator A(16) Clock Generating Circuit Clock output XOUT Clock input XIN Accumulator B(16) XCIN XCOUT Internal enable output E XCIN XCOUT Index Register Y(16) Index Register X(16) UART0 (9) Timer TB0(16) Direct Page Register DPR(16) Timer TA0(16) Reset input RESET Processor Status Register PS(11) Timer TB2(16) Input Buffer Register IB(16) Timer TB1(16) VCC Data Bank Register DT(8) Timer TA1(16) Program Bank Register PG(8) Timer TA2(16) (0V) VSS Program Counter PC(16) Central Processing Unit (CPU) Incrementer/Decrementer(24) Watchdog Timer CNVss Data Address Register DA(24) Timer TA3(16) (0V) AVSS Program Address Register PA(24) Bus Interface Unit (BIU) Address Bus Incrementer(24) Input/Output port P4 Instruction Queue Buffer Q2(8) Input/Output port P5 Instruction Queue Buffer Q1(8) 1 RDY HOLD HLDA ALE BHE R/W High-order * Middle-order address/Data (16) Instruction Queue Buffer Q0(8) P5 (8) AVCC Instruction Register(8) Data Buffer DBL(8) Input/Output port P6 Data Bus(Odd) Data Buffer DBH(8) Low-order address (8) Data Bus(Even) P6 (8) Reference External data bus width voltage input selection input VREF BYTE Figure 20.4.1 shows the M37733S4BFP block diagram. Fig.20.4.1 M37733S4BFP block diagram 7733 Group User's Manual 20-7 EXTERNAL ROM VERSION 20.5 Memory allocation 20.5 Memory allocation The internal area's memory allocation is described below. For details, refer to section "2.4 Memory allocation." For the external area, refer to section "20.6 Processor modes." Figure 20.5.1 shows the M37733S4BFP's memory map and Figure 20.5.2 shows the SFR area's memory map. 20-8 7733 Group User's Manual EXTERNAL ROM VERSION 20.5 Memory allocation 000000 16 00007F 16 000080 16 00087F 16 000880 16 SFR area 000000 16 Peripheral device control registers (SFR) Internal RAM area 2048 bytes Refer to Figure 20.5.2. Bank 0 16 00007F 16 Interrupt vector table 00FFD6 16 A-D/UART2 trans./rece. UART1 transmission 00FFFF 16 010000 16 UART1 reception UART0 transmission UART0 reception Timer B2 Bank 1 16 Timer B1 Timer B0 Timer A4 01FFFF 16 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Watchdog timer DBC BRK instruction Zero divide 00FFFE 16 RESET : External memory area FF0000 16 Bank FF 16 FFFFFF 16 For the 7733 Group's microcomputers other than the M37733S4BFP, refer to section "Appendix 1. 7733 Group memory allocation ." Fig. 20.5.1 M37733S4BFP's memory map 7733 Group User's Manual 20-9 EXTERNAL ROM VERSION 20.5 Memory allocation Address (Hexadecimal notation) 000000 000001 000002 Port P0 register (Note 3) 000003 Port P1 register (Note 3) 000004 Port P0 direction register (Note 3) 000005 Port P1 direction register (Note 3) 000006 Port P2 register (Note 3) 000007 Port P3 register (Note 3) 000008 Port P2 direction register (Note 3) 000009 Port P3 direction register (Note 3) 00000A Port P4 register (Note 3) 00000B Port P5 register 00000C Port P4 direction register (Note 3) 00000D Port P5 direction register 00000E Port P6 register 00000F Port P7 register 000010 Port P6 direction register 000011 Port P7 direction register 000012 Port P8 register 000013 000014 Port P8 direction register 000015 000016 000017 000018 000019 00001A 00001B 00001C Pulse output data register 1 (Note 1) 00001D Pulse output data register 0 (Note 1) 00001E A-D control register 0 00001F A-D control register 1 000020 A-D register 0 000021 000022 A-D register 1 000023 000024 A-D register 2 000025 000026 A-D register 3 000027 000028 A-D register 4 000029 00002A A-D register 5 00002B 00002C A-D register 6 00002D 00002E A-D register 7 00002F 000030 UART 0 transmit/receive mode register 000031 UART 0 baud rate register (BRG0) 000032 UART 0 transmission buffer register 000033 000034 UART 0 transmit/receive control register 0 000035 UART 0 transmit/receive control register 1 000036 UART 0 receive buffer register 000037 000038 UART 1 transmit/receive mode register 000039 UART 1 baud rate register (BRG1) 00003A UART 1 transmission buffer register 00003B 00003C UART 1 transmit/receive control register 0 00003D UART 1 transmit/receive control register 1 00003E UART 1 receive buffer register 00003F Address (Hexadecimal notation) 000040 000041 000042 000043 000044 000045 000046 000047 000048 000049 00004A 00004B 00004C 00004D 00004E 00004F 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005A 00005B 00005C 00005D 00005E 00005F 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006A 00006B 00006C 00006D 00006E 00006F 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007A 00007B 00007C 00007D 00007E 00007F Count start flag One-shot start flag Up-down flag Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Watchdog timer frequency selection flag Waveform output mode register (Note 1) Reserved area (Notes 1, 2) UART2 transmit/receive mode register UART2 baud rate register (BRG2) UART2 transmission buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Oscillation circuit control register 0 Port function control register Serial transmit control register Oscillation circuit control register 1 A-D/UART2 trans./rece. interrupt control register UART 0 transmission interrupt control register UART 0 receive interrupt control register UART 1 transmission interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2/Key input interrupt control register Notes 1: Memory map of the M37733S4BFP differs from that of the M37733MHBXXXFP in addresses 1C16, 1D16, 6216, and 6316 . 2: Writing to the reserved area is disabled. 3: These registers are used when outputting an arbitrary data in the stop or wait mode. Fig. 20.5.2 SFR area's memory map 20-10 7733 Group User's Manual EXTERNAL ROM VERSION 20.6 Processor modes 20.6 Processor modes The M37733S4BFP can operate only in the microprocessor mode. For the processor mode, refer to the description of the microprocessor mode in section "2.5 Processor modes." Also, be sure to set as follows: * Connect pin CNVss to Vcc. * Fix the processor mode bits to "102 ." Figure 20.6.1 shows the structure of the processor mode register 0. b7 b6 0 b5 b4 b3 b2 b1 b0 Processor mode register 0 (address 5E 16) Bit Bit name 0 Processor mode bits ( Note) 1 Functions b1 b0 0 0: Do not select. 0 1: Do not select. 1 0: Microprocessor mode 1 1: Do not select. At reset RW 0 RW 0 RW 0 RW 2 Wait bit 3 Software reset bit Microcomputer is reset by setting this bit to "1." This bit is "0" at reading. 0 WO 4 Interrupt priority detection time selection bits b5 b4 0 RW 0 RW 5 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. 0 0: 7 cycles of 0 1: 4 cycles of 1 0: 2 cycles of 1 1: Do not select. 6 Must be fixed to "0." 0 RW 7 This bit is ignored. 0 RW represents that bits 2 to 7 are not used for setting the processor mode. : It may be "0" or "1." Note: Fix the processor mode bits to "10 2." Fig. 20.6.1 Structure of processor mode register 0 7733 Group User's Manual 20-11 EXTERNAL ROM VERSION 20.7 Timer A 20.7 Timer A Timer A is used mainly for output to the external. It consists of five counters (Timers A0 to A4) each equipped with a 16-bit reload function. Timers A0 to A4 operate independently of each other. 20.7.1 Overview In the external ROM version, timer A has five operating modes listed below. In operating modes to , the external ROM version operates the same as the mask ROM and PROM versions. Operating mode is described in this chapter. Timer mode Event counter mode One shot pulse mode Pulse width modulation (PWM) mode Pulse output mode 20-12 Refer to chapter "6. TIMER A." 7733 Group User's Manual EXTERNAL ROM VERSION 20.7 Timer A 20.7.2 Pulse output port mode (1) Overview In the pulse output mode, there are two types of pulse output port: RTP0 controlled by timer A0 and RTP1 controlled by timer A2. When an underflow occurs in timer A0 or A2, the contents of the pulse output data register 0 or 1 is output from the corresponding pulse output pins. Also, the pulse width can be modulated by timer A as follows: use timer A1 for RTP0 and use timer A3 for RTP1. In addition, RTP0 can reverse the polarity of the contents of the pulse output data register 0 by software and outputs it. Table 20.7.1 lists the specifications of the pulse output mode. Table 20.7.1 Specifications of pulse output port mode Pulse output port RTP1 RTP0 Control timer Timer A0 Timer A2 Pulse output pins RTP0 0-RTP03 (Ports P5 0-P5 3) RTP1 0-RTP13 (Ports P5 4-P5 7) Register where pulse data is set Pulse output data register 0 Pulse output data register 1 Pulse width modulation Possible (Timer A1 is used) Possible (Timer A3 is used) Output level reverse function Available Not available 7733 Group User's Manual 20-13 EXTERNAL ROM VERSION 20.7 Timer A (2) Block description Figure 20.7.1 shows the block diagram for the pulse output mode. Figures 20.7.3 to 20.7.6 show the structures of registers related to the pulse output port mode. Also, Figure 20.7.2 shows the structure of the port P5 output control circuit. Pulse width modulation selection bits (Bits 4, 5 at address 62 16) 4 5 Pulse width modulation output by timer A3 Pulse width modulation output by timer A1 Timer A2 Data bus (odd) Data bus (even) Pulse output data register 1 (Address 1C 16) b3 D TQ RTP1 3(P57/TA3IN) b2 D Q RTP1 2(P56/TA3OUT) b1 D Q RTP1 1(P55/TA2IN) b0 D Q RTP1 0(P54/TA2OUT) b3 D Q RTP0 3(P53/TA1IN) b2 D Q RTP02(P5 2/TA1OUT) b1 D Q RTP0 1(P51/TA0IN) b0 DT Q RTP00(P5 0/TA0OUT) Pulse output data register 0 (Address 1D 16) Polarity selection bit (Bit 3 at address 62 16) Timer A0 Fig. 20.7.1 Block diagram for pulse output port mode 20-14 7733 Group User's Manual EXTERNAL ROM VERSION 20.7 Timer A P5 0/TA0 OUT/RTP0 0, P5 2/TA1 OUT/RTP0 2, P54/TA2 OUT/RTP1 0, P56/TA3 OUT /RTP1 2 Bit 2 of the timer Ai mode register (addresses 56 16 to 59 16 ) (Note 2) (Whether to output a pulse or not is selected.) "1" "1" "0" "0" Direction register Pulse output Timer A output "1" "0" Port latch "1" "0" Input Bits 0 and 1 of the waveform output mode register (address 62 16) (Note 1) (RTP1, RTP0 selected) P51/TA0 IN/RTP0 1, P53/TA1 IN/RTP0 3, P55/TA2 IN/RTP1 1, P57/TA3 IN/RTP1 3 Bits 0 and 1 of the waveform output mode register (Note 1) (RTP1, RTP0 selected) "1" Direction register "0" Pulse output "1" Port latch "0" Input Notes 1: Ports P5 0 to P5 3 correspond to bit 1. Ports P5 4 to P57 correspond to bit 0. 2: Bit 2 of the timer Ai mode register which corresponds to each port Fig. 20.7.2 Port P5 output control circuit 7733 Group User's Manual 20-15 EXTERNAL ROM VERSION 20.7 Timer A b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 0 0 Timer A0 mode register (address 56 16) Timer A2 mode register (address 58 16) Bit Bit name Functions 0 Operating mode selection bits b1 b0 0 0: Timer mode 1 1: Pulse is output. Must be fixed to "1." 2 Pulse output function selection bit 3 Gate function selection bits 4 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW At reset RW Undefined RW b4 b3 0 0: 0 1: No gate function Bit 4 must be fixed to "0." 5 Must be fixed to "0" in the timer mode. 6 Count source selection bits 7 At reset b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 X: It may be either "0" or "1." (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 47 16, 46 16) Timer A2 register (addresses 4B 16, 4A16) Bit Functions 15 to 0 Values 0000 16 to FFFF 16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Fig. 20.7.3 Structures of timer A0, A2 mode registers and timer A0, A2 registers in pulse output port mode 20-16 7733 Group User's Manual EXTERNAL ROM VERSION 20.7 Timer A b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 1 Timer A1 mode register (address 57 16) Timer A3 mode register (address 59 16) Bit 0 1 2 Bit name Functions Operating mode selection bits b1 b0 1 1: PWM mode Must be fixed to "1" in the PWM mode. ( Note) b4 b3 3 Trigger selection bits (Note) 0 0: Writing "1" to the count start flag 0 1: (Pin TAiIN functions as a programmable I/O port.) 4 0: The counter operates as a 16-bit pulse width modulator. 1: The counter operates as an 8-bit pulse width modulator. 5 16/8-bit PWM mode selection bit 6 Count source selection bits 0 0: Clock f 2 0 1: Clock f 16 1 0: Clock f 64 1 1: Clock f 512 7 b7 b6 At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW Note: Fix bit 2 to "1" and bit 4 to "0" even when not using the pulse width modulation function. X: It may be "0" or "1." When operating as a 16-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A1 register (addresses 49 16, 48 16) Timer A3 register (addresses 4D 16, 4C16) Functions Bit 15 to 0 Values 0000 16 to FFFE 16 can be set. Assuming that the set value = n, "H" level width of the PWM pulse which is output from pin TA1 OUT or TA3OUT is n/fi. At reset RW Undefined WO At reset RW Undefined WO Undefined WO fi: Frequency of the count source (f 2, f16, f64, or f512 ) When operating as an 8-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A1 register (addresses 49 16, 4816) Timer A3 register (addresses 4D 16, 4C16) Bit 7 to 0 Functions Values 00 16 to FF16 can be set. Assuming that the set value = m, period of the PWM pulse which is output from pin TA1OUT or TA3OUT is (m + 1)(2 8 - 1)/fi. 15 to 8 Values 00 16 to FE16 can be set. Assuming that the set value = n, "H" level width of the PWM pulse which is output from pin TA1 OUT or TA3OUT is n(m +1)/fi. fi: Frequency of the count source (f 2, f16 , f64 , or f512 ) Fig. 20.7.4 Structures of timer A1, A3 mode registers and timer A1, A3 registers in pulse output port mode (when pulse width modulation function is used) 7733 Group User's Manual 20-17 EXTERNAL ROM VERSION 20.7 Timer A b7 0 b6 b5 b4 b3 b2 b1 b0 Waveform output mode register (address 62 16) Bit Bit name Functions b1 b0 0 Waveform output selection bits 1 0 0: Port P5 is a programmable I/O port. 0 1: RTP1 is selected. 1 0: RTP0 is selected. 1 1: RTP1 and RTP0 are selected. RW 0 RW 0 RW Undefined - 2 Not implemented. This bit is "0" at reading. 3 Polarity selection bit (Valid only for RTP0) 0: Positive polarity 1: Negative polarity 0 RW 4 Pulse width modulation selection bit by timer A1 0: Not modulated 1: Modulated 0 RW 5 Pulse width modulation selection bit by timer A3 0: Not modulated 1: Modulated 0 RW 6 Not implemented. This bit is "0" at reading. Undefined - 7 Must be fixed to "0." 0 RW Fig. 20.7.5 Structures of waveform output mode register 20-18 At reset 7733 Group User's Manual EXTERNAL ROM VERSION 20.7 Timer A b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 1 (address 1C 16) Bit Bit name Functions 0: "L" level is output. 1: "H" level is output. At reset RW Undefined WO 0 RTP10 output data bit 1 RTP11 output data bit Undefined WO 2 RTP12 output data bit Undefined WO 3 RTP13 output data bit Undefined WO Not implemented. Undefined - At reset RW Undefined WO Undefined WO Undefined WO Undefined WO Undefined - 4 to 7 Note: Use the LDM and STA instructions to set bits 0 to 3. b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 1 (address 1D 16) Bit Bit name 0 RTP00 output data bit 1 RTP01 output data bit 2 RTP02 output data bit 3 RTP03 output data bit 4 to 7 Functions When the positive polarity is selected, 0: "L" level is output. 1: "H" level is output. When the negative polarity is selected, 0: "H" level is output. 1: "L" level is output. Not implemented. Note: Use the LDM and STA instructions to set bits 0 to 3. Fig. 20.7.6 Structures of pulse output data registers 0, 1 7733 Group User's Manual 20-19 EXTERNAL ROM VERSION 20.7 Timer A (3) Initial setting example for registers related to pulse output port mode Figures 20.7.7 to 20.7.9 show an initial setting example for registers related to the pulse output port mode. Setting of the pulse output data register 0 and pulse output data register 1 b7 b0 Pulse output data register 0 (address 1D 16) RTP00 RTP01 Output data is set to the corresponding bit. RTP02 RTP03 b7 b0 Pulse output data register 1 (address 1C 16) RTP10 RTP11 Output data is set to the corresponding bit. RTP12 RTP13 Setting of the division ratio for timer A0 or timer A2 (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 47 16, 4616) Timer A2 register (addresses 4B 16, 4A16) Values 0000 16 to FFFF 16 (n) can be set. Counter divides the count source by (n + 1). Setting of the timer A0 mode register or timer A2 mode register b7 b0 0 0 1 0 0 Timer A0 mode register (address 56 16) Timer A2 mode register (address 5A 16) Count source selection bits b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 X: It may be "0" or "1." Continued to "Initial setting example for registers related to pulse output port mode (2)" on the next page Fig. 20.7.7 Initial setting example for registers related to pulse output port mode (1) 20-20 7733 Group User's Manual EXTERNAL ROM VERSION 20.7 Timer A Continued from "Initial setting example for registers related to pulse output port mode (1)" on the preceding page When not modulating the pulse width When modulating the pulse width Setting of the timer A1 mode register or timer A3 mode register b7 b0 1 Timer A1 mode register (address 57 16) Timer A3 mode register (address 59 16) Setting of the PWM pulse's period and "H" level width When operating as a 16-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A1 register (addresses 49 16, 48 16) Timer A3 register (addresses 4D 16, 4C16) Values 0000 16 to FFFE16 (n) can be set. When operating as an 8-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A1 register (addresses 49 16, 48 16) Timer A3 register (addresses 4D 16, 4C16) Values 00 16 to FF16 (m) can be set. Values 00 16 to FE16 (n) can be set. When operating as an 8-bit pulse width modulator Period = (m+1) (2 8 - 1)/fi "H" level width = n(m + 1)/fi fi: Frequency of the count source However, if n = 00 16 , the counter does not operate and pin TAi OUT outputs "L" level. At this time, no timer Ai request is generated. When operating as a 16-bit pulse width modulator Period = (2 16 - 1)/fi "H" level width = n/fi fi: Frequency of the count source However, if n = 000016, the counter does not operate and pin TAiOUT outputs "L" level. At this time, no timer Ai request is generated. Setting of timers A1 and A3 b7 b0 0 1 1 1 Timer A1 mode register (address 57 16) Timer A3 mode register (address 59 16) Trigger selection bits b4 b3 0 X: Count start flag 16/8-bit PWM mode selection bit 0: The counter operates as a 16-bit pulse width modulator. 1: The counter operates as an 8-bit pulse width modulator. Count source selection bits b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 X: It may be "0" or "1." Continued to "Initial setting example for registers related to pulse output port mode (3)" on the next page Fig. 20.7.8 Initial setting example for registers related to pulse output port mode (2) 7733 Group User's Manual 20-21 EXTERNAL ROM VERSION 20.7 Timer A Continued from "Initial setting example for registers related to pulse output port mode (2)" on the preceding page Setting of the waveform output mode register b7 b0 Waveform output mode register (address 62 16) 0 Waveform output selection bits b1 b0 0 0: Port P5 is a programmable I/O port. 0 1: RTP1 is selected. 1 0: RTP0 is selected. 1 1: RTP0 and RTP1 are selected. Polarity selection bit (Affective only for RTP0) 0: Positive polarity 1: Negative polarity Pulse width modulation selection bit by timer A1 0: Not modulated 1: Modulated Pulse width modulation selection bit by timer A3 0: Not modulated 1: Modulated Setting of the interrupt priority level b7 b0 Timer A0 interrupt control register (address 75 16) Timer A1 interrupt control register (address 76 16) (Note) 0 Timer A2 interrupt control register (address 77 16) Timer A3 interrupt control register (address 78 16) (Note) Interrupt priority level selection bits When using interrupts, one of levels 1-7 must be set. When disabling interrupts, level 0 must be set. Note: This is used when the pulse width is modulated. Setting of the count start flag to "1" b7 b0 Count start flag (address 40 16) Timer A0 count start flag Timer A1 count start flag ( Note) Timer A2 count start flag Timer A3 count start flag ( Note) Note: This is used when the pulse width is modulated. Counting is started. Fig. 20.7.9 Initial setting example for registers related to pulse output port mode (3) 20-22 7733 Group User's Manual EXTERNAL ROM VERSION 20.7 Timer A (4) Operation in pulse output port mode The RTP0 operation when the pulse width is not modulated and the output level reverse function is not used is described below. Note: Description in ( ) is applied to the RTP1 operation. When the count start flag of timer A0 (A2) is set to "1," the counter starts counting of the count source. When an underflow occurs, data is output from each bit of RTP0 (RTP1) according to the setting of each bit of the pulse output data register 0 (1). This data is retained until the next underflow occurs. Timer A0 (A2) reloads the contents of the reload register and continues counting. When the underflow occurs in , the timer A0 (A2) interrupt request bit is set to "1." Then, the interrupt request bit remains set to "1" until the interrupt request is accepted or the interrupt request bit is cleared to "0" by software. Figure 20.7.10 shows an operation example of the pulse output port mode. Counting is started. Pulse output is started. Counter contents (Hex.) FFFF16 n, m : Reloaded value m n 000016 Count start flag Contents of pulse output data register 0 3 (00112) 6 (01102) C (11002) 9 (10012) RTP0 3 output RTP0 2 output RTP0 1 output RTP0 0 output Contents of RTP0 output Undefined 3 6 C Timer A0 interrupt request bit Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. Note: The output level of the pulse output port is undefined from when the pulse output port mode is set until the first timer underflow occurs. Also, this output level is at a floating state after reset because the pulse output port becomes the input port at that time. In the above example, in order to shorten this undefined period, the following procedure is performed: * A small value (n) is set to the timer counter as the initial value. * After the first underflow occurs, the normal value (m) is set to the timer counter. e p t Fig. 20.7.10 Operation example of pulse output port mode 7733 Group User's Manual 20-23 EXTERNAL ROM VERSION 20.7 Timer A (5) Selectable functions The pulse width modulation function and the RTP0 output level reverse function are described below. Pulse width modulation function The RTP0 operation when the positive polarity is selected is described below. Note: Description in ( ) is applied to the RTP1 operation. When "the pulse width modulation selection bit by timer A1(A3)" [bit 4(5)) at address 6216] is set to "1," "modulated" (Refer to Figure 20.7.5.) is selected. The pulse width modulation is performed while pins RTP00 to RTP03 (RTP10 to RTP13) output "H" level. (Refer to section "6.6 Pulse width modulation (PWM) mode" and Figure 20.7.4.) Figure 20.7.11 shows an operation example when "modulated" is selected. Counting is started. Pulse output is started. Counter contents (Hex.) FFFF16 n, m : Reloaded value m n 000016 Count start flag Contents of pulse output data register 0 3 (00112) 6 (01102) C (11002) 9 (10012) RTP0 3 output RTP0 2 output RTP0 1 output RTP0 0 output Timer A0 interrupt request bit Timer A1 interrupt request bit Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. Note: The output level of the pulse output port is undefined from when the pulse output port mode is set until the first timer underflow occurs. Also, this output level is at a floating state after reset because the pulse output port becomes the input port at that time. In the above example, in order to shorten this undefined period, the following procedure is performed: * A small value (n) is set to the timer counter as the initial value. * After the first underflow occurs, the normal value (m) is set to the timer counter. Fig. 20.7.11 Operation example when "modulated" is selected 20-24 7733 Group User's Manual EXTERNAL ROM VERSION 20.7 Timer A Output level reverse function (only for RTP0) When the polarity selection bit (bit 3 at address 6216) is set to "1," the output level can be reversed. In this case, when the RTP0 0 to RTP0 3 output data bits (bits 0 to 3 at address 1D 16 ) are set to "0," pins RTP0 0 to RTP0 3 output "H" level; when these bits are set to "1," these pins output "L" level. When the output level reverse function and "modulated" are selected, the pulse width modulation is performed while pins RTP0 0 to RTP0 3 output "L" level. Figure 20.7.12 shows an operation example when the output level is reversed with "modulated" selected. Counting is started. Pulse output is started. FFFF16 n, m : Reloaded value Counter contents (Hex.) m n 000016 Count start flag Contents of pulse output data register 0 3 (00112) 6(0110 2 ) C (11002) 9 (10012) RTP0 3 output RTP0 2 output RTP0 1 output RTP0 0 output Timer A0 interrupt request bit Timer A1 interrupt request bit Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. Cleared to "0" when an interrupt request is accepted; otherwise, cleared by software. Note: The output level of the pulse output port is undefined from when the pulse output port mode is set until the first timer underflow occurs. Also, this output level is at a floating state after reset because the pulse output port becomes the input port at that time. In the above example, in order to shorten this undefined period, the following procedure is performed: * A small value (n) is set to the timer counter as the initial value. * After the first underflow occurs, the normal value (m) is set to the timer counter. t g n Fig. 20.7.12 Operation example when RTP0 output level reverse function and "modulated" are selected [Precautions for pulse output port mode (pulse output function)] 1. In order to make ports P50 (RTP00), P52 (RTP02), P54 (RTP10), and P56 (RTP12) function as the pulse output pins, fix bit 2 of the timer A0 to A3 mode registers to "1." When using RTP0: Fix bit 2 of the timer A0 and A1 mode registers to "1." When using RTP1: Fix bit 2 of the timer A2 and A3 mode registers to "1." 2. When the pulse width modulation function is not used, timers A1 and A3 can be used as timers which do not have I/O pins. In this case, fix bit 2 of the timer A1 and A3 mode registers to "1." In addition, fix bits 0, 1, 4, and 5 of these registers to "0." 7733 Group User's Manual 20-25 EXTERNAL ROM VERSION 20.8 Reset 20.8 Reset The reset description of the external ROM version differs from that of the mask ROM version in the state immediately after reset. The state immediately after reset of the external ROM version differs from that of the mask ROM version in the following addresses: addresses 1C16, 1D16, 6216 and 6316. Only the differences are described below. Figures 20.8.1 and 20.8.2 show the state of SFR area and internal RAM area immediately after reset (1) and (4). Figure 20.8.1 corresponds to Figure 13.1.3. Figure 20.8.2 corresponds to Figure 13.1.6. For the other descriptions, refer to chapter "13. RESET." 20-26 7733 Group User's Manual EXTERNAL ROM VERSION 20.8 Reset SFR area (addresses 016 to 7F16) Abbreviations which represent access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Not implemented. It is impossible to read the bit state. The written value becomes invalid. 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. Address Register name 016 116 Port P0 register 216 Port P1 register 316 416 Port P0 direction register 516 Port P1 direction register Port P2 register 616 Port P3 register 716 816 Port P2 direction register 916 Port P3 direction register Port P4 register A16 Port P5 register B16 Port P4 direction register C16 D16 Port P5 direction register Port P6 register E16 Port P7 register F16 Port P6 direction register 1016 1116 Port P7 direction register Port P8 register 1216 1316 1416 Port P8 direction register 1516 1616 1716 1816 1916 1A16 1B16 1C16 Pulse output data register 1 1D16 Pulse output data register 0 1E16 A-D control register 0 1F16 A-D control register 1 b7 0 : Always "0" at reading ? : Always undefined at reading 0 : "0" immediately after reset. Must be fixed to "0." State immediately after reset Access characteristics b0 b7 b0 RW RW RW RW RW RW 0 0 0 RW 0 0 0 0 ? 0 ? 0 0 RW RW RW RW RW RW RW RW RW RW RW WO WO RW RW RW ? ? ? ? 0016 0016 ? 0 0016 0 0 ? ? 0016 0016 ? ? 0016 0016 ? ? 0016 ? ? ? ? ? ? ? ? ? 0 0 0 0 ? 0 0 0 ? ? ? 1 ? 1 The contents of addresses 1C16 and 1D16 of the M37733S4BFP differ from those of the M37733MHBXXXFP. Fig. 20.8.1 State of SFR area and internal RAM area immediately after reset (1) 7733 Group User's Manual 20-27 EXTERNAL ROM VERSION 20.8 Reset Address Register name b7 Watchdog timer register 6016 6116 Watchdog timer frequency selection flag Waveform output mode register 3 RW 6216 6316 4 (Reserved area) UART 2 transmit/receive mode register 6416 UART 2 baud rate register (BRG2) 6516 6616 UART 2 transmission buffer register 6716 6816 UART 2 transmit/receive control register 0 6916 UART 2 transmit/receive control register 1 6A16 UART 2 receive buffer register 6B16 Oscillation circuit control register 0 6C16 Port function control register 6D16 Serial transmit control register 6E16 Oscillation circuit control register 1 6F16 WO 7016 A-D / UART 2 trans./rece. interrupt control register 7116 UART0 transmission interrupt control register 7216 UART0 receive interrupt control register 7316 UART1 transmission interrupt control register 7416 UART1 receive interrupt control register Timer A0 interrupt control register 7516 Timer A1 interrupt control register 7616 Timer A2 interrupt control register 7716 Timer A3 interrupt control register 7816 Timer A4 interrupt control register 7916 Timer B0 interrupt control register 7A16 Timer B1 interrupt control register 7B16 Timer B2 interrupt control register 7C16 INT0 interrupt control register 7D16 INT1 interrupt control register 7E16 INT2/Key input interrupt control register 7F16 Access characteristics b0 State immediately after reset b7 b0 WO RW RW RW RW WO WO RO RO WO RW RW RO RW 0 ? 0 ? 0 0 RW(2) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 ? 0 ? 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? 0 0 0 0 ? 0 0 0 0 0 0 0 0 RO RO RW ? (1) ? 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? ? ? 0 0 0 0 ? 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A value of "FFF 16" is set to the watchdog timer. (Refer to Chapter "10. WATCHDOG TIMER.") 2 For access characteristics at address 6C 16, also refer to Figure 14.3.2. 3 The contents of addresses 62 16 and 6316 of the M37733S4BFP differ from those of the M37733MHBXXXFP. 4 Do not wirte to address 63 16. Internal RAM area (M37733S4BFP: addresses 80 16 to FFF16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset . When the stop or wait mode is terminated (when hardware reset is used)...Retains the state immediately before the STP or WIT instruction is executed. Fig. 20.8.2 State of SFR area and internal RAM area immediately after reset (4) 20-28 7733 Group User's Manual EXTERNAL ROM VERSION 20.9 Electrical characteristics 20.9 Electrical characteristics Except for "Icc," the electrical characteristics of the M37733S4BFP are the same as those of the M37733MHBXXXFP in the microprocessor mode. For the others, refer to chapter "15. ELECTRICAL CHARACTERISTICS.") ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter Measuring conditions Min. Limits Typ. Max. Unit Vcc = 5 V, f(XIN) = 25 MHz (Square waveform), (f(f2) = 12.5 MHz), 11.4 22.8 mA f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 5V, f(XIN) = 25 MHz (Square waveform), (f(f2) = 1.5625 MHz), 1.6 3.2 mA f(XCIN) : Stopped, in operating (Note 1) External bus is Vcc = 5V, operating, output f(XIN) = 25 MHz (Square waveform), pins are open, 10 20 A Power source f(XCIN) = 32.768 kHz, ICC and the other current when the WIT instruction is executed (Note 2) pins are Vcc = 5 V, connected to f(XIN) : Stopped, Vss. 60 120 A f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 5 V, f(XIN) : Stopped, 5 10 A f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 C, 1 A when clock is stopped Ta = 85 C, 20 A when clock is stopped Notes 1: This is applied when the main clock external input selection bit = "1," the main clock division selection bit = "0," and the signal output disable selection bit = "1." 2: This is applied when the main clock external input selection bit = "1" and the system clock stop selection bit at wait state = "1." 3: This is applied when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the XCOUT drivability selection bit = "0" and the system clock stop bit at wait state = "1." 7733 Group User's Manual 20-29 EXTERNAL ROM VERSION 20.10 Low voltage version 20.10 Low voltage version Differences from the M37733S4BFP are mainly described below. 20.10.1 Performance overview The performance overview of the low voltage version differs from that of the mask ROM version in the following: memory size and current consumption. For the other items, refer to section "18.1 Performance overview." Table 20.10.1 shows the performance overview of the M37733S4LHP. Table 20.10.1 M37733S4LHP's performance overview Items Memory size Current consumption 20-30 Performance RAM 2048 bytes 10.8 mW (When f(XIN) = 12-MHz external square wave input, Vcc = 3 V, and the main clock is the system clock, Typ.) 120 W (When f(XCIN) = 32 kHz, Vcc = 3 V, the sub clock is the system clock, and the main clock is stopped, Typ.) 7733 Group User's Manual EXTERNAL ROM VERSION 20.10 Low voltage version P67/TB2IN/ SUB P70/AN0 P71/AN1 P72/AN2/CTS2 P73/AN3/CLK2 P74/AN4/RxD2 P75/AN5/ADTRG/TxD2 P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RXD0/CLKS0 P83/TXD0 P84/CTS1/RTS1 P85/CLK1 20.10.2 Pin configuration Figure 20.10.1 shows the M37733S4LHP pin configuration. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 7 8 9 10 11 12 13 14 15 M37733S4LHP P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3/RTP13 P56/TA3OUT/KI2/RTP12 P55/TA2IN/KI1/RTP11 P54/TA2OUT/KI0/RTP10 P53/TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P47 P46 P45 P44 P43 55 54 53 52 51 50 49 48 47 46 16 45 17 44 18 43 19 42 20 41 P86/RxD1 P87/TxD1 A0(P00) A1(P01) A2(P02) A3(P03) A4(P04) A5(P05) A6(P06) A7(P07) A8/D8(P10) A9/D9(P11) A10/D10(P12) A11/D11(P13) A12/D12(P14) A13/D13(P15) A14/D14(P16) A15/D15(P17) A16/D0(P20) A17/D1(P21) (P42)/ 1 RDY HOLD BYTE CNVSS RESET XIN XOUT E VSS (P33)HLDA (P32)ALE (P31)BHE (P30)R/W (P27)A23/D7 (P26)/A22/D6 (P25)A21/D5 (P24)A20/D4 (P23)A19/D3 (P22)A18/D2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin's level can be fixed in the stop or wait mode. Outline 80P6D-A Fig. 20.10.1 M37733S4LHP pin configuration (Top view) 7733 Group User's Manual 20-31 EXTERNAL ROM VERSION 20.10 Low voltage version 20.10.3 Functional description Except for the power-on reset conditions, the M37733S4LHP has the same functions as the M37733S4BFP. For the other functions, refer to chapters "2. CENTRAL PROCESSING UNIT (CPU)" to "14. CLOCK GENERATING CIRCUIT." The power-on reset conditions of the M37733S4LHP are the same as those of the M37733MHLXXXHP. For details, refer to section "18.3 Functional description". 20.10.4 Electrical characteristics Except for "Icc," the electrical characteristics of the M37733S4LHP are the same as those of the M37733MHLXXXHP in the microprocessor mode. For the others, refer to section "18.4 Electrical characteristics." ELECTRICAL CHARACTERISTICS (Vcc= 5 V, Vss = 0 V, Ta = -40 to 85 C, unless otherwise noted) Limits Symbol Parameter Measuring conditions Min. Typ. Max. Unit Vcc = 5 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), 5.4 10.8 mA f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), 3.6 7.2 mA f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 0.75 MHz), 0.5 1.0 mA External bus is f(XCIN) : Stopped, operating, in operating (Note 1) Power source output pins are Vcc = 3 V, Icc current open, and the f(XIN) = 12 MHz (Square waveform), 6 12 A other pins are f(XCIN) = 32.768 kHz, connected when the WIT instruction is executed (Note 2) to Vss. Vcc = 3 V, f(XIN) : Stopped, 40 80 A f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 3 V, f(XIN) : Stopped, 3 6 A f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 C, 1 A when clock is stopped Ta = 85 C, 20 A when clock is stopped Notes 1: This is applied when the main clock external input selection bit = "1," the main clock division selection bit = "0," and the signal output disable selection bit = "1." 2: This is applied when the main clock external input selection bit = "1" and the system clock stop bit at wait state = "1." 3: This is applied when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the XCOUT drivability selection bit = "0" and the system clock stop bit at wait state = "1." 20-32 7733 Group User's Manual APPENDIX Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix 1. 2. 3. 4. 5. 6. 7. 8. Memory allocation of 7733 Group Memory allocation in SFR area Control registers Package outlines Hexadecimal instruction code table Machine instructions Examples of handling unused pins Countermeasure examples against noise Appendix 9. Q & A APPENDIX Appendix 1. Memory allocation of 7733 Group Appendix 1. Memory allocation of 7733 Group 1. M37733MHBXXXFP, M37733EHBXXXFP, M37733EHBFS, M37733MHLXXXHP, M37733EHLXXXHP * Memory allocation selection bits (b2, b1, b0)=(0, 0, 0) * ROM size: 124 Kbytes * RAM size: 3.9 Kbytes 00000016 00007F16 00008016 SFR area Internal RAM area 3968 bytes 000FFF16 00100016 00000016 00007F16 00008016 000FFF16 * Memory allocation selection bits (b2, b1, b0)=(0, 0, 1) * ROM size: 120 Kbytes * RAM size: 3.9 Kbytes SFR area 00000016 Internal RAM area 3968 bytes Peripheral device control registers (SFR) (4 Kbytes) 00200016 Refer to Appendix 2. Bank 016 Internal ROM area 60 Kbytes 00FFFF16 01000016 Internal ROM area 56 Kbytes 00007F16 Interrupt vector table 00FFFF16 01000016 00FFD616 A-D/UART2 trans./rece. UART1 transmission UART1 reception Bank 116 Internal ROM area 64 Kbytes Internal ROM area 64K bytes UART0 transmission UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 01FFFF16 02000016 Timer A3 01FFFF16 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Bank 216 Watchdog timer DBC BRK instruction Zero divide 00FFFE16 RESET 02FFFF16 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode FF000016 Bank FF16 FFFFFF16 FFFFFF16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes.") 2: Memory allocation of the 7735 Group differs from that of the 7733 Group. (For the memory allocation of the 7735 Group, refer to section "Appendix 1 in part 2.") Fig. 1 Memory allocation of M37733MHBXXXFP, M37733EHBXXXFP, M37733EHBFS, M37733MHLXXXHP, M37733EHLXXXHP (1) 21-2 7733 Group User's Manual APPENDIX Appendix 1. Memory allocation of 7733 Group * Memory allocation selection bits (b2, b1, b0)=(0, 1, 0) * ROM size: 60 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 2048 bytes 00087F16 (1.9 Kbytes) 00100016 * Memory allocation selection bits (b2, b1, b0)=(1, 0, 0) * ROM size: 32 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 2048 bytes 00087F16 00000016 Peripheral device control registers (SFR) Refer to Appendix 2. (29.9 Kbytes) Bank 016 Internal ROM area 60 Kbytes 00FFFF16 01000016 00800016 Internal ROM area 32 Kbytes 00FFFF16 01000016 00007F16 Interrupt vector table 00FFD616 A-D/UART2 trans./rece. UART1 transmission UART1 reception UART0 transmission UART0 reception Bank 116 Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 01FFFF16 02000016 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Bank 216 Watchdog timer DBC BRK instruction Zero divide 00FFFE16 RESET 02FFFF16 FF000016 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Bank FF16 FFFFFF16 FFFFFF16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes.") 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Fig. 2 Memory allocation of M37733MHBXXXFP, M37733EHBXXXFP, M37733EHBFS, M37733MHLXXXHP, M37733EHLXXXHP (2) 7733 Group User's Manual 21-3 APPENDIX Appendix 1. Memory allocation of 7733 Group * Memory allocation selection bits (b2, b1, b0)=(1, 0, 1) * ROM size: 16 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 2048 bytes 00087F16 00000016 00007F16 00008016 000FFF16 00100016 Bank 016 * Memory allocation selection bits (b2, b1, b0)=(1, 1, 0) * ROM size: 96 Kbytes * RAM size: 3968 bytes SFR area 00000016 Internal RAM area 3968 bytes Peripheral device control registers (SFR) Refer to Appendix 2. (28 Kbytes) (45.9 Kbytes) 00800016 00C00016 00FFFF16 01000016 Internal ROM area 16 Kbytes Internal ROM area 32 Kbytes 00FFFF16 01000016 00007F16 Interrupt vector table 00FFD616 A-D/UART2 trans./rece. UART1 transmission UART1 reception UART0 transmission UART0 reception Internal ROM area 64 Kbytes Bank 116 Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 01FFFF16 02000016 01FFFF16 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Bank 216 Watchdog timer DBC BRK instruction Zero divide 00FFFE16 RESET 02FFFF16 FF000016 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Bank FF16 FFFFFF16 FFFFFF16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes.") 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Fig. 3 Memory allocation of M37733MHBXXXFP, M37733EHBXXXFP, M37733EHBFS, M37733MHLXXXHP, M37733EHLXXXHP (3) 21-4 7733 Group User's Manual APPENDIX Appendix 1. Memory allocation of 7733 Group 2. M37733S4BFP, M37733S4LHP 00000016 00007F16 00008016 00087F16 00088016 SFR area 00000016 Peripheral device control registers (SFR) Internal RAM area 2048 bytes Refer to Appendix. 2 Bank 016 00007F16 Interrupt vector table 00FFD616 A-D/UART2 trans./rece. UART1 transmission 00FFFF16 01000016 UART1 reception UART0 transmission UART0 reception Timer B2 Bank 116 Timer B1 Timer B0 Timer A4 01FFFF16 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Watchdog timer DBC BRK instruction Zero divide 00FFFE16 RESET : External memory area FF000016 Bank FF16 FFFFFF16 The area at addresses 00FFD616 to 00FFFF16 is the interrupt vector table area. Be sure to set ROM to this area. Memory allocation of the 7735 Group differs from that of the 7733 Group. (For the memory allocation of the 7735 Group, refer to section "Appendix 1 in part 2.") Fig. 4 Memory allocation of M37733S4BFP, M37733S4LHP 7733 Group User's Manual 21-5 APPENDIX Appendix 2. Memory allocation in SFR area Appendix 2. Memory allocation in SFR area Figures 5 to 8 show the memory allocation in SFR area. The signals used in Figures 5 to 8 are shown below. Abbreviations which represent access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Not implemented. It is impossible to read the bit state. The written value becomes invalid. 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. 0 : Always "0" at reading ? : Always undefined at reading 0 : "0" immediately after reset. Must be fixed to "0." SFR area (addresses 016 to 7F16) Address Register name b7 Access characteristics 016 116 Port P0 register 216 Port P1 register 316 416 Port P0 direction register 516 Port P1 direction register Port P2 register 616 Port P3 register 716 Port P2 direction register 816 Port P3 direction register 916 Port P4 register A16 Port P5 register B16 Port P4 direction register C16 Port P5 direction register D16 Port P6 register E16 Port P7 register F16 Port P6 direction register 1016 Port P7 direction register 1116 Port P8 register 1216 1316 1416 Port P8 direction register 1516 1616 1716 1816 1916 1A16 1B16 1C16 (Reserved area) (Reserved area) 1D16 1E16 A-D control register 0 1F16 A-D control register 1 State immediately after reset b0 b0 b7 RW RW RW RW RW RW 0 0 0 RW 0 0 0 0 ? 0 ? 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW ? ? ? ? 0016 0016 ? 0 0016 0 0 ? ? 0016 0016 ? ? 0016 0016 ? ? 0016 ? ? ? ? ? ? ? ? ? 0 0 0 0 ? 0 0 0 ? ? ? 1 ? 1 Do not write to the reserved area. (For the M37733S4BFP, M37733S4LHP, M37735S4BFP, M37735S4LHP, refer to Figure 20.8.1.) Fig. 5 Memory allocation in SFR area (1) 21-6 7733 Group User's Manual APPENDIX Appendix 2. Memory allocation in SFR area Address Register name b7 Access characteristics State immediately after reset b0 b0 b7 RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW WO WO 2016 A-D register 0 2116 2216 A-D register 1 2316 2416 A-D register 2 2516 2616 A-D register 3 2716 2816 A-D register 4 2916 2A16 A-D register 5 2B16 2C16 A-D register 6 2D16 2E16 A-D register 7 2F16 3016 UART0 transmit/receive mode register 3116 UART0 baud rate register 3216 UART0 transmission buffer register 3316 3416 UART0 transmit/receive control register 0 3516 UART0 transmit/receive control register 1 3616 UART0 receive buffer register 3716 3816 UART1 transmit/receive mode register UART1 baud rate register 3916 3A16 UART1 transmission buffer register 3B16 3C16 UART1 transmit/receive control register 0 3D16 UART1 transmit/receive control register 1 3E16 UART1 receive buffer register 3F16 ? ? RO ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 1 0 0 0 0 ? 0 0 0 1 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? RW RW RO RW 0 0 0 0 0 0 RO 0 0 0 WO RW RW RO RW 0 0 0 0 0 0 RO 0 0 0 RW WO WO RO ? ? RO RW RO ? ? WO RW RO ? ? RO 0016 ? ? ? 0 1 0 0 ? 0 0 0016 ? ? ? 0 1 0 0 ? 0 0 Fig. 6 Memory allocation in SFR area (2) 7733 Group User's Manual 21-7 APPENDIX Appendix 2. Memory allocation in SFR area Address 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C16 4D16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C16 5D16 5E16 5F16 Register name b7 Access characteristics Count start flag WO Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B2 mode register Processor mode register 0 RW 0 0 0 0 0 0 0 0 0 0 0 ? ? ? 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RW RW RW RW RW Timer A1 register Timer B1 mode register ? WO Timer A0 register Timer B0 mode register State immediately after reset b7 RW One-shot start flag Up-down flag b0 RW RW RW 2 2 2 RW Processor mode register 1 RW RW RW WO RW 3 RW RW 0016 ? 0 0 ? 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0016 0016 0016 0016 0016 ? 0 ? 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 Access characteristics at addresses 4616 to 5516 vary according to the timer's operating mode. (Refer to chapter "6. TIMER A," and chapter "7. TIMER B.") 2 Access characteristics for bit 5 at addresses 5B16 to 5D16 vary according to the timer B's operating mode. (Refer to chapter "7. TIMER B.") 3 Access characteristics for bit 1 at address 5E16 and its state immediately after reset vary according to the voltage level applied to pin CNVSS. (Refer to section "2.5 Processor modes.") Fig. 7 Memory allocation in SFR area (3) 21-8 7733 Group User's Manual b0 0 0 0 0 0 APPENDIX Appendix 2. Memory allocation in SFR area Address Register name b7 6016 6116 Watchdog timer frequency selection flag (Reserved area) 4 6216 Memory allocation control register 6316 UART 2 transmit/receive mode register 6416 UART 2 baud rate register (BRG2) 6516 6616 UART 2 transmission buffer register 6716 6816 UART 2 transmit/receive control register 0 6916 UART 2 transmit/receive control register 1 6A16 UART 2 receive buffer register 6B16 Oscillation circuit control register 0 6C16 Port function control register 6D16 Serial transmit control register 6E16 Oscillation circuit control register 1 WO 6F16 7016 A-D / UART 2 trans./rece. interrupt control register 7116 UART0 transmission interrupt control register 7216 UART0 receive interrupt control register 7316 UART1 transmission interrupt control register 7416 UART1 receive interrupt control register Timer A0 interrupt control register 7516 Timer A1 interrupt control register 7616 Timer A2 interrupt control register 7716 Timer A3 interrupt control register 7816 Timer A4 interrupt control register 7916 Timer B0 interrupt control register 7A16 Timer B1 interrupt control register 7B16 Timer B2 interrupt control register 7C16 INT0 interrupt control register 7D16 INT1 interrupt control register 7E16 INT2/Key input interrupt control register 7F16 Access characteristics b0 State immediately after reset b0 b7 WO Watchdog timer register RW ? ? 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 RW RW WO WO RO RO WO RW R WR OR W RO O RO RW(2) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? ? ? 0 0 0 ? (1) ? ? 0 0 0 0 ? ? ? 1 0 0 ? 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 ? 0 ? 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A value of "FFF16" is set to the watchdog timer. (Refer to chapter "10. WATCHDOG TIMER.") 2 For access characteristics at address 6C16, also refer to Figure 14.3.2. 3 Fix this bit to "1" in the One Time PROM version and EPROM version. (However, fix this bit to "0" in the 7735 Group.) 4 Do not write to the reserved area. (Refer to Figure 20.8.1 for the M37733S4BFP, M37733S4LHP, M37735S4BFP, 37735S4LHP.) Internal RAM area (M37733MHBXXXFP: addresses 8016 to FFF16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset. When the stop or wait mode is terminated (when the hardware reset is used)...Retains the state immediately before the STP or WIT instruction is executed. Fig. 8 Memory allocation in SFR area (4) 7733 Group User's Manual 21-9 APPENDIX Appendix 3. Control registers Appendix 3. Control registers The control registers allocated in the SFR area are shown on the following pages. Below is the structure diagram for all registers. 1 b7 b6 b5 b4 b3 0 b2 b1 b0 XXX register (address XX16) Bit 2 Bit name 3 Functions At reset RW 0 RW Undefined WO 0 RO 0 ... select bit 0 : ... 1 : ... 1 ... select bit 0 : ... 1 : ... The value is "0" at reading. 2 ... flag 0 : ... 1 : ... 3 Fix this bit to "0." 0 RW 4 This bit is ignored in ... mode. 0 RW Undefined 7 to 5 Not implemented. | 4 1 Blank 0 1 : Set to "0" or "1" according to the usage. : Set to "0" at writing. : Set to "1" at writing. : Ignored depending on the mode or state. It may be "0" or "1." : Not implemented. 2 0 : "0" immediately after reset. 1 : "1" immediately after reset. Undefined : Undefined immediately after reset. 3 RW RO WO -- 21-10 : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written value may be "0" or "1." : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading. However, when ["0" at reading] is indicated in the "Function" or "Note" column, the bit is always "0" at reading.(See to 4 above.) : It is impossible to read the bit state. The value is undefined at reading. However, when ["0" at reading] is indicated in the "Function" or "Note" column, the bit is always "0" at reading.(See to 4 above.) The written value becomes invalid. Accordingly, the written value may be "0" or "1." 7733 Group User's Manual APPENDIX Appendix 3. Control registers Port Pi register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi register (i = 0 to 8) (addresses 216,316,616,716,A16,B16,E16,F16,1216) Bit Bit name Functions At reset RW Undefined RW Undefined RW Undefined RW Undefined RW 0 Port Pi0's pin 1 Port Pi1's pin 2 Port Pi2's pin 3 Port Pi3's pin 4 Port Pi4's pin Undefined RW 5 Port Pi5's pin Undefined RW 6 Port Pi6's pin Undefined RW 7 Port Pi7's pin Undefined RW Data is input from or output to a pin by reading from or writing to the corresponding bit. 0: "L" level 1: "H" level Note: Writing to bits 4 to 7 of the port P3 register is invalid and these bits are fixed to "0" when they are read. Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 0 to 8) (addresses 416,516,816,916,C16,D16,1016,1116,1416) Bit Bit name Functions At reset RW 0 RW 0 RW 0 RW 0 Port Pi0 direction selection bit 1 Port Pi1 direction selection bit 2 Port Pi2 direction selection bit 3 Port Pi3 direction selection bit 0 RW 4 Port Pi4 direction selection bit 0 RW 5 Port Pi5 direction selection bit 0 RW 6 Port Pi6 direction selection bit 0 RW 7 Port Pi7 direction selection bit 0 RW 0: Input mode (The port functions as an input port.) 1: Output mode (The port functions as an output port.) Note: Writing to bits 4 to 7 of the port P3 direction register is invalid and these bits are fixed to "0" when they are read. Bit b7 b6 b5 b4 b3 b2 b1 b0 Corresponding pin Pi7 Pi6 Pi5 Pi4 Pi3 Pi2 Pi1 Pi0 7733 Group User's Manual 21-11 APPENDIX Appendix 3. Control registers A-D control register 0 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 0 (address 1E16) Bit Bit name Functions 2 Analog input selection bits (Valid in the one-shot and repeat 0 0 0: AN0 is selected. 0 0 1: AN1 is selected. modes.) (Note 1) 0 1 0: AN2 is selected. 0 1 1: AN3 is selected. 1 0 0: AN4 is selected. 1 0 1: AN5 is selected. (Note 2) 1 1 0: AN6 is selected. 1 1 1: AN7 is selected. 3 A-D operation mode selection bits 0 1 At reset RW Undefined RW Undefined RW Undefined RW 0 RW 0 RW b2 b1 b0 4 b4b3 00: One-shot mode 01: Repeat mode 10: Single sweep mode 11: Repeat sweep mode 5 Trigger selection bit 0: Internal trigger 1: External trigger 0 RW 6 A-D conversion start flag 0: A-D conversion is stopped. 1: A-D conversion is started. 0 RW 7 A-D conversion frequency ( f AD ) selection flag 0: f2/4 1: f2/2 0 RW f2: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Notes 1: These bits are ignored in the single sweep and repeat sweep modes. (They may be "0" or "1.") 2: When an external trigger is selected, pin AN5 cannot be used as an analog input pin. 3: Writing to each bit (except bit 6) of the A-D control register 0 must be performed while the A-D converter stops operating. A-D control register 1 b7 b6 b5 b4 0 b3 b2 b1 b0 A-D control register 1 (address 1F16) Bit 0 1 Bit name Functions b1 b0 A-D sweep pin selection bits 0 0: Pins AN0 and AN1 (2 pins) (Valid in the single sweep and 0 1: Pins AN0 to AN3 (4 pins) repeat sweep modes.) (Note 1) 1 0: Pins AN0 to AN5 (6 pins) (Note 2) 1 1: Pins AN0 to AN7 (8 pins) 2 Not implemented. 3 8/10-bit mode selection bit 4 Must be fixed to "0." 5 VREF connection selection bit (Note 4) 6 Not implemented. 0: 8-bit resolution 1: 10-bit resolution 0: Pin VREF is connected. 1: Pin VREF is disconnected. (High impedance) At reset RW 1 RW 1 RW Undefined - 0 RW 0 RW 0 RW Undefined - 7 Notes 1: These bits are ignored in the one-shot and repeat modes. (They may be "0" or "1.") 2: When an external trigger is selected, pin AN5 cannot be used as an analog input pin. 3: Writing to each bit of the A-D control register 1 must be performed while the A-D converter stops operating. 4: When the VREF connection selection bit is cleared from "1" to "0," wait for an interval of 1 s or more passed, and then start A-D conversion. 21-12 7733 Group User's Manual APPENDIX Appendix 3. Control registers A-D register i When resolution = 8 bits (b15) (b8) b7 b0 b7 b0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 (addresses 2116 and 2016) (addresses 2316 and 2216) (addresses 2516 and 2416) (addresses 2716 and 2616) (addresses 2916 and 2816) (addresses 2B16 and 2A16) (addresses 2D16 and 2C16) (addresses 2F16 and 2E16) Bit Functions 7 to 0 The A-D conversion result is read out. 15 to 8 "0" at reading. When resolution = 10 bits (b15) (b8) b7 b0 b7 b0 At reset RW Undefined RO 0 RO At reset RW Undefined RO 0 RO A-D register 0 (addresses 2116 and 2016) A-D register 1 (addresses 2316 and 2216) A-D register 2 (addresses 2516 and 2416) A-D register 3 (addresses 2716 and 2616) A-D register 4 (addresses 2916 and 2816) A-D register 5 (addresses 2B16 and 2A16) A-D register 6 (addresses 2D16 and 2C16) A-D register 7 (addresses 2F16 and 2E16) Bit 9 to 0 Functions The A-D conversion result is read out. 15 to 10 "0" at reading. 7733 Group User's Manual 21-13 APPENDIX Appendix 3. Control registers UART0, UART1 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive mode register (address 3016) UART1 transmit/receive mode register (address 3816) Bit 0 Bit name Serial I/O mode selection bits 1 2 Functions b2 b1 b0 0 0 0: Serial I/O is disabled. (P8 functions as a programmable I/O port.) 0 0 1: Clock synchronous serial I/O mode 0 1 0: Do not select. 0 1 1: Do not select. 1 0 0: UART mode (Transfer data length = 7 bits) 1 0 1: UART mode (Transfer data length = 8 bits) 1 1 0: UART mode (Transfer data length = 9 bits) 1 1 1: Do not select. 0: Internal clock 1: External clock At reset RW 0 RW 0 RW 0 RW 0 RW 3 Internal/External clock selection bit 4 Stop bit length selection bit 0: One stop bit (Valid in the UART mode.) (Note) 1: Two stop bits 0 RW 5 Odd/Even parity selection bit (Valid in the UART mode when the parity enable bit = "1.") (Note) Parity enable bit (Valid in the UART mode.) (Note) 0: Odd parity 1: Even parity 0 RW 0: Parity is disabled. 1: Parity is enabled. 0 RW 0 RW 6 7 Sleep selection bit 0: The sleep mode is terminated. (Ignored.) (Valid in the UART mode.) (Note) 1: The sleep mode is selected. Note: Bits 4 to 6 are ignored in the clock synchronous serial I/O mode. (They may be "0" or "1.") Fix bit 7 to "0." UARTi baud rate register (BRGi) b7 b0 UART0 baud rate register (address 3116) UART1 baud rate register (address 3916) UART2 baud rate register (address 6516) Bit 21-14 Functions At reset RW 7 to 0 Values 0016 to FF16 can be set. Undefined Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). WO 7733 Group User's Manual APPENDIX Appendix 3. Control registers UARTi transmission buffer register (b8) b0 b7 (b15) b7 b0 UART0 transmission buffer register (addresses 3316, 3216) UART1 transmission buffer register (addresses 3B16, 3A16) UART2 transmission buffer register (addresses 6716, 6616) Functions Bit 8 to 0 The transmit data is set. 15 to 9 Not implemented. At reset RW Undefined WO Undefined -- At reset RW UART0, UART1 transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 0 (address 3416) UART1 transmit/receive control register 0 (address 3C16) Bit Bit name 0 BRG count source selection bits 1 Functions 0 RW 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 0 RW 0: The CTS function is selected. 1: The RTS function is selected. 0 RW 1 RO b1 b0 2 CTS/RTS function selection bit (Valid when the CTS/RTS enable bit is "0.") 3 Transmission register empty flag 0: Data is present in the transmission register. (Transmission is in progress.) 1: No data is present in the transmission register. (Transmission is completed.) 4 CTS/RTS enable bit 0: The CTS/RTS function is enabled. 1: The CTS/RTS function is disabled. (P80 and P84 function as programmable I/O ports.) 0 RW 5 Data output selection bit 0: Pin TxDi is set for CMOS output. 1: Pin TxDi is set for N-channel opendrain output. 0 RW 6 0: At the falling edge of the transfer CLK polarity selection bit clock, transmit data is output; at (This bit is used in the clock the rising edge of the transfer synchronous serial I/O mode.) clock, receive data is input. (Note) When not in transferring, pin CLK i's level is "H." 1: At the rising edge of the transfer clock, transmit data is output; at the falling edge of the transfer clock, receive data is input. When not in transferring, pin CLK i's level is "L." 0 RW 7 Transfer format selection bit (This bit is used in the clock synchronous serial I/O mode.) (Note) 0 RW 0: LSB (Least Significant Bit) first 1: MSB (Most Significant Bit) first Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: Fix bits 6 and 7 to "0" in the UART mode. 7733 Group User's Manual 21-15 APPENDIX Appendix 3. Control registers UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) Bit name Bit Functions At reset RW 0 Transmit enable bit 0: Transmission is disabled. 1: Transmission is enabled. 0 RW 1 Transmission buffer empty flag 0: Data is present in the transmission buffer register. 1: No data is present in the transmission buffer register. 1 RO 2 Receive enable bit 0: Reception is disabled. 1: Reception is enabled. 0 RW 3 Receive completion flag 0: No data is present in the receive buffer register. 1: Data is present in the receive buffer register. 0 RO 4 Overrun error flag (Note 1) 0: No overrun error is detected. 1: Overrun error is detected. 0 RO 5 Framing error flag (Notes 1 and 2) (Valid in the UART mode.) 0: No framing error is detected. 1: Framing error is detected. 0 RO 6 Parity error flag (Notes 1 and 2) (Valid in the UART mode.) 0: No parity error is detected. 1: Parity error is detected. 0 RO 7 Error sum flag (Notes 1 and 2) (Valid in the UART mode.) 0: No error is detected. 1: Error is detected. 0 RO Notes 1: Bits 4 to 7 are cleared to "0" when the serial I/O mode selection bits (bits 2 to 0 at addresses 3016, 3816) are cleared to "0002" or when the receive enable bit is cleared to "0." (Bit 7 is cleared to "0" when all of bits 4 to 6 are "0.") Note also that bits 5 and 6 are cleared to "0" when the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16, 6A16) is read out. 2: Bits 5 to 7 are ignored in the clock synchronous serial I/O mode. UARTi receive buffer register (b15) b7 (b8) b0 b7 b0 UART0 receive buffer register (addresses 3716, 3616) UART1 receive buffer register (addresses 3F16, 3E16) UART2 receive buffer register (addresses 6B16, 6A16) Bit Functions 8 to 0 The receive data is read out from here. 15 to 9 Not implemented. A value of "0" is read out from here. 21-16 7733 Group User's Manual At reset RW Undefined RO 0 -- APPENDIX Appendix 3. Control registers Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Count start flag (address 4016) Bit Bit name Functions At reset RW 0 RW 0 RW 0 Timer A0 count start flag 1 Timer A1 count start flag 2 Timer A2 count start flag 0 RW 3 Timer A3 count start flag 0 RW 4 Timer A4 count start flag 0 RW 5 Timer B0 count start flag 0 RW 6 Timer B1 count start flag 0 RW 7 Timer B2 count start flag 0 RW 0: Counting is stopped. 1: Counting is started. One-shot start flag b7 b6 b5 b4 b3 b2 b1 b0 One-shot start flag (address 4216) Bit Bit name Functions At reset RW 0 WO 0 WO 0 WO 0 Timer A0 one-shot start flag 1 Timer A1 one-shot start flag 1: One-shot pulse output is started. (Valid when the internal trigger is selected.) 2 Timer A2 one-shot start flag "0" at reading. 3 Timer A3 one-shot start flag 0 WO 4 Timer A4 one-shot start flag 0 WO Undefined - At reset RW 0 RW 0 RW 0 RW 0 RW 7 to 5 Not implemented. Up-down flag b7 b6 b5 b4 b3 b2 b1 b0 Up-down flag (address 4416) Bit Bit name 0 Timer A0 up-down flag 1 Timer A1 up-down flag Functions 0: Countdown 1: Countup This bits is valid when the contents of the up-down flag is selected as the up-down switching factor. 2 Timer A2 up-down flag 3 Timer A3 up-down flag 4 Timer A4 up-down flag 0 RW 5 Timer A2 two-phase pulse signal 0: Two-phase pulse signal processing selection bit processing function is disabled. 1: Two-phase pulse signal Timer A3 two-phase pulse signal processing function is enabled. processing selection bit 0 WO 0 WO When not using the two-phase pulse Timer A4 two-phase pulse signal signal processing function, be sure processing selection bit to set this bit to "0." This bit is "0" at reading. 0 WO 6 7 Note: When writing to bits 5 to 7, use the LDM or STA instruction. 7733 Group User's Manual 21-17 APPENDIX Appendix 3. Control registers Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) Bit Functions At reset RW 0 0: Timer mode 0 1: Event counter mode 1 0: One-shot pulse mode 1 1: Pulse width modulation (PWM) mode 0 RW 0 RW 0 RW 3 0 RW 4 0 RW 5 0 RW 6 0 RW 7 0 RW At reset RW Undefined RW 0 Bit name Operating mode selection bits 1 2 b1 b0 These bits have different functions according to the operating mode. Timer Ai register (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Bit Functions 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. 21-18 7733 Group User's Manual APPENDIX Appendix 3. Control registers Timer mode b7 b6 b5 b4 b3 0 b2 b1 b0 0 0 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) Bit Bit name Functions 0 Operating mode selection bits b1 b0 0 0: Timer mode 1 0: No pulse is output. (Pin TAiOUT functions as a programmable I/O port.) 1: Pulse is output. (Pin TAiOUT functions as a pulse output pin.) 2 Pulse output function selection bit 3 Gate function selection bits 0 X: No gate function (Pin TAiIN functions as a programmable I/O port.) 1 0: Counter counts only while pin TAiIN's input signal level is "L." 1 1: Counter counts only while pin TAiIN's input signal level is "H." At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW At reset RW Undefined RW b4 b3 4 5 6 Must be fixed to "0" in the timer mode. Count source selection bits 7 b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Bit Functions 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. 7733 Group User's Manual 21-19 APPENDIX Appendix 3. Control registers Event counter mode b7 b6 b5 0 b4 b3 b2 b1 b0 0 1 Timer A0 mode register (address 5616) Timer A1 mode register (address 5716) Bit Bit name Functions 0 RW b1 b0 0 RW 2 Pulse output function selection bit 0: No pulse is output. (Pin TA0OUT or TA1OUT functions as a programmable I/O port.) 1: Pulse is output. (Pin TA0OUT or TA1OUT functions as a pulse output pin.) 0 RW 3 Count polarity selection bit 0: Counts at falling edge of external signal 1: Counts at rising edge of external signal 0 RW 4 Up-down switching factor selection bit 0: Contents of the up-down flag 1: A signal which is input to pin TA0OUT or TA1OUT 0 RW 5 Must be fixed to "0" in the event counter mode. 0 RW 6 These bits are ignored in the event counter mode. 0 RW 0 RW 0 1: Event counter mode 1 7 (b8) b0 b7 RW Operating mode selection bits 0 (b15) b7 At reset b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Bit Functions 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1) in down-counting, or by (FFFF16 - n + 1) in upcounting. At reading this register, the counter value is read out. 21-20 7733 Group User's Manual At reset RW Undefined RW APPENDIX Appendix 3. Control registers b7 b6 b5 0 b4 b3 b2 b1 b0 0 1 Timer A2 mode register (address 5816) Timer A3 mode register (address 5916) Timer A4 mode register (address 5A16) Bit 0 1 Bit name Functions Operating mode selection bits b1 b0 0 1: Event counter mode At reset RW 0 RW 0 RW RW 2 Pulse output function selection bit 0: No pulse is output. (Pin TA2OUT, TA3OUT, or TA4OUT functions as a programmable I/O port.) 1: Pulse is output. (Pin TA2OUT, TA3OUT, or TA4OUT functions as a pulse output pin.) 0 3 Count polarity selection bit 0: Counting is performed at the falling edge of the external signal. 1: Counting is performed at the rising edge of the external signal. 0 RW 4 Up-down switching factor selection bit 0: Contents of the up-down flag 1: A signal which is input to pin TA2OUT, TA3OUT, or TA4OUT 0 RW 0 RW 5 Must be fixed to "0" in the event counter mode. 6 Count type selection bit 0: Reload count type 1: Free-run count type 0 RW 7 Two-phase pulse signal processing type selection bit (Note) 0: Normal processing 1: Quadruple processing 0 RW Note: This bit is valid only for the timer A3 mode register. For the timer A2 and A4 mode registers, this bit is ignored. (It may be "0" or "1.") (b15) b7 (b8) b0 b7 b0 Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Bit Functions 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1) in down-counting, or by (FFFF16 - n + 1) in up-counting. At reading this register, the counter value is read out. 7733 Group User's Manual At reset RW Undefined RW 21-21 APPENDIX Appendix 3. Control registers One-shot pulse mode b7 b6 b5 0 b4 b3 b2 b1 b0 1 1 0 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) Bit 0 1 2 Bit name Functions Operating mode selection bits b1 b0 1 0: One-shot pulse mode Must be fixed to "1" in the one-shot pulse mode. At reset RW 0 RW 0 RW 0 RW 0 @@ RW 0 RW 0 RW 0 RW 0 RW At reset RW Undefined WO b4 b3 3 0 X: Writing "1" to the one-shot start flag (Pin TAiIN functions as a programmable I/O port.) 1 0: Falling edge of the pin TAiIN's input signal 1 1: Rising edge of the pin TAiIN's input signal Trigger selection bits 4 5 6 7 Must be fixed to "0" in the one-shot pulse mode. b7 b6 Count source selection bits 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Bit Functions 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, "H" level width of the one-shot pulse output from pin TAiOUT is n/fi. fi: Frequency of the count source (f2, f16, f64, or f512) 7733 Group User's Manual 21-22 APPENDIX Appendix 3. Control registers Pulse width modulation (PMW) mode b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 Timer Ai mode register (i = 0 to 4) (addresses 5616 to 5A16) Bit 0 1 2 Bit name Functions At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW At reset RW 15 to 0 Values 000016 to FFFE16 can be set. UnAssuming that the set value = n, "H" level defined width of the PWM pulse which is output from pin TAiOUT is n/fi. WO Operating mode selection bits b1 b0 1 1: PWM mode Must be fixed to "1" in the PWM mode. b4 b3 3 0 X: Writing "1" to the count start flag (Pin TAiIN functions as a programmable I/O port.) 1 0: Falling edge of the pin TAiIN's input signal 1 1: Rising edge of the pin TAiIN's input signal Trigger selection bits 4 0: The counter operates as a 16-bit pulse width modulator. 1: The counter operates as an 8-bit pulse width modulator. 5 16/8-bit PWM mode selection bit 6 Count source selection bits 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 7 b7 b6 Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." When operating as a 16-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Bit Functions fi: Frequency of the count source (f2, f16, f64, or f512) When operating as an 8-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A0 register (addresses 4716, 4616) Timer A1 register (addresses 4916, 4816) Timer A2 register (addresses 4B16, 4A16) Timer A3 register (addresses 4D16, 4C16) Timer A4 register (addresses 4F16, 4E16) Bit Functions At reset RW Undefined WO 15 to 8 Values 0016 to FE16 can be set. UnAssuming that the set value = n, "H" level defined width of the PWM pulse which is output from pin TAiOUT is n(m +1)/fi. WO 7 to 0 Values 0016 to FF16 can be set. Assuming that the set value = m, period of the PWM pulse which is output from pin TAiOUT is (m + 1)(28 - 1)/fi. fi: Frequency of the count source (f2, f16, f64, or f512) 7733 Group User's Manual 21-23 APPENDIX Appendix 3. Control registers Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Bit 0 Bit name Functions At reset RW 0 RW 0 RW 0 RW 0 RW Must be fixed to "0" (i = 0). 0 RW Not implemented (i = 1, 2). Undefined -- These bits have different functions according to the operating mode. UnRO defined (Note) Operating mode selection bits 1 2 b1 b0 0 0: Timer mode 0 1: Event counter mode 1 0: Pulse period/Pulse width measurement mode 1 1: Do not select. These bits have different functions according to the operating mode. 3 4 5 6 0 RW 7 0 RW Note: In the timer and event counter modes, bit 5 is ignored and undefined at reading. Timer Bi register (b15) b7 (b8) b0 b7 b0 Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) At reset RW 15 to 0 Values 000016 to FFFF16 can be set. UnAssuming that the set value = n, counter defined divides the count source frequency by (n + 1). At reading this register, the counter value is read out. RW Bit 21-24 7733 Group User's Manual Functions APPENDIX Appendix 3. Control registers Timer mode b7 b6 b5 X b4 b3 b2 b1 b0 X X 0 0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Bit 0 Bit name Functions At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW Undefined -- Undefined RO 0 RW 0 RW At reset RW 15 to 0 Values 000016 to FFFF16 can be set. UnAssuming that the set value = n, counter defined divides the count source frequency by (n + 1). At reading this register, the counter value is read out. RW Operating mode selection bits b1 b0 0 0: Timer mode 1 2 These bits are ignored in the timer mode. 3 4 *Timer B0 mode register Must be fixed to "0." *Timer B1 and B2 mode registers Not implemented. b4 b3 5 This bit is ignored in the timer mode and is undefined at reading. 6 Count source selection bits 7 b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." (b15) b7 (b8) b0 b7 b0 Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) Bit 7733 Group User's Manual Functions 21-25 APPENDIX Appendix 3. Control registers Event counter mode b7 X b6 b5 X X b4 b3 b2 b1 b0 0 1 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Bit At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW *Timer B1 and B2 mode registers Not implemented. Undefined -- 5 This bit is ignored in the event counter mode and is undefined at reading. Undefined RO 6 These bits are ignored in the event counter mode. 0 RW 0 RW At reset RW Un15 to 0 Values 000016 to FFFF16 can be set. defined Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. RW 0 Bit name Functions Operating mode selection bits b1 b0 0 1: Event counter mode 1 2 Count polarity selection bits 3 4 b3 b2 0 0: Counting is performed at the falling edge of the external signal. 0 1: Counting is performed at the rising edge of the external signal. 1 0: Counting is performed at both falling and rising edges of the external signal. 1 1: Do not select. *Timer B0 mode register Must be fixed to "0." 7 (b15) b7 (b8) b0 b7 b0 Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) Bit 21-26 7733 Group User's Manual Functions APPENDIX Appendix 3. Control registers Pulse period/Pulse width measurement mode b7 b6 b5 b4 b3 b2 b1 b0 1 0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) Bit 0 Bit name Functions Operating mode selection bits b1 b0 1 0: Pulse period/pulse w idth m easurem ent m ode 1 2 b3 b2 Measurement mode selection bits 0 0: Pulse period m easurem ent Interval betw een falling edges of the m easurem ent pulse) 0 1: Pulse period m easurem ent Interval betw een risi ng edges of the m easurement pulse) 1 0: Pulse w idth m easurem ent Interval from a falling edge to a risi ng edge, and from a risi ng edge to a falling edge of the measurement pulse) 1 1: D o not sel ect . 3 4 *Timer B0 mode register Must be fixed to "0." *Timer B1 and B2 mode registers Not implemented. 5 Timer Bi overflow flag (Note) 6 Count source selection bits 7 0: No overflow 1: Overflow b7 b6 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW Undefined -- 1 RO 0 RW 0 RW Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." Note: Timer Bi overflow flag is cleared to "0" when writing to the timer Bi mode register is performed with the count start flag = "1." This flag cannot be set to "1" by software. (b15) b7 (b8) b0 b7 b0 Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) Bit At reset RW 15 to 0 The result of the pulse period or pulse width Undefined measurement is read out. RO 7733 Group User's Manual Functions 21-27 APPENDIX Appendix 3. Control registers Clock timer b7 b6 b5 X X X b4 b3 b2 b1 b0 0 1 0 1 Timer B2 mode register (address 5D16) Bit Functions At reset RW 0 Must be fixed to "1" for the clock timer. 0 RW 1 Must be fixed to "0" for the clock timer. 0 RW 2 Must be fixed to "1" for the clock timer. 0 RW 3 Must be fixed to "0" for the clock timer. 0 RW 4 Not implemented. Undefined -- 5 This bit is ignored for the clock timer. Undefined RO 6 These bits are ignored for the clock timer. 0 RW 0 RW 7 (b15) b7 (b8) b0 b7 b0 Timer B2 register (addresses 5516 and 5416) Bit Functions 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. 21-28 7733 Group User's Manual At reset RW Undefined RW APPENDIX Appendix 3. Control registers Processor mode register 0 b7 b6 b5 b4 b3 b2 b1 b0 0 Processor mode register 0 (address 5E16) Bit name Bit 0 Processor mode bits 1 Functions b1 b0 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Microprocessor mode 1 1: Do not select. At reset RW 0 RW 0 RW (Note 1) 2 Wait bit 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. 0 RW 3 Software reset bit Microcomputer is reset by setting this bit to "1." This bit is "0" at reading. 0 WO 4 Interrupt priority detection time selection bits 0 RW 0 RW 0 RW 0 RW 5 6 Must be fixed to "0." 7 Clock f 1 output selection bit (Note 2) b5 b4 0 0: 7 cycles of f 0 1: 4 cycles of f 1 0: 2 cycles of f 1 1: Do not select. 0: Clock f 1 output is disabled. (P42 functions as a programmable I/O port.) 1: Clock f 1 output is enabled. (Port P4 2functions as a clock f 1 output pin.) Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to "1" after reset. (At reading, this bit is always "1.") 2: This bit is ignored in the microprocessor mode. (It may be "0" or "1.") Processor mode register 1 b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 1 (address 5F16) Bit 0 Bit name Wait selection bit Function 0 : Wait 0 1 : Wait 1 7 to1 Not implemented. 7733 Group User's Manual At reset RW 0 RW Undefined _ 21-29 APPENDIX Appendix 3. Control registers Watchdog timer register b7 b0 Watchdog timer register (address 6016) Functions Bit 7 to 0 Watchdog timer is initialized. By writing dummy data to this register, watchdog timer's value is initialized to "FFF16" (Dummy data: 0016 to FF16). At reset RW Undefined WO At reset RW 0 RW Undefined -- Watchdog timer frequency selection flag b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency selection flag (address 6116) Bit 0 7 to 1 Bit name Watchdog timer frequency selection flag Functions 0 : Clock f512 1 :Clock f32 Not implemented. Clocks f32, f512 : Refer to chapter "14. CLOCK GENERATING CIRCUIT." 21-30 7733 Group User's Manual APPENDIX Appendix 3. Control registers Memory allocation control register b7 b6 b5 b4 b3 b2 b1 b0 0 0 Memory allocation control register (address 63 16) (Note 3) Bit 0 Bit name Memory allocation selection bits (Notes 1 and 2) 1 At reset RW ROM size 3968 bytes 3968 bytes 2048 bytes 0 RW 2048 bytes 2048 bytes 3968 bytes 0 RW 0 RW 0 RW 0 RW Functions ROM size 0 0 0: 124 Kbytes, 0 0 1: 120 Kbytes, 0 1 0: 60 Kbytes, 0 1 1: Do not select. 1 0 0: 32 Kbytes, 1 0 1: 16 Kbytes, 1 1 0: 96 Kbytes, 1 1 1: Do not select. b2b1b0 2 3 Must be fixed to "0." (Note 1) 4 7 to 5 Undefined Not implemented. | Notes 1: The case where value "55 16" is written in of the procedure listed below is not included. 2: When changing these bits, this change must be performed in an area which is internal ROM area before and after this change, for example addresses 00C000 16 to 00FFFF 16. Also, when changing these bits, be sure to follow the procedure listed below. 3: This figure is applied only to the M37733MHBXXXFP. For the other microcoputers, please refer to the latest datasheets on the English document CD-ROM or our Web site. Procedure By using the LDM instruction, write value "55 16" to address 63 16. (By this, writing to the memory allocation selection bits is enabled.) By using the LDM instruction, write value "00000XXX 2" to address 63 16. (Values of b2, b1, and b0 shown in the above Figure) Writing is performed by the next instruction. Note: When changing bits 2 to 0, be sure to follow this procedure. 7733 Group User's Manual 21-31 APPENDIX Appendix 3. Control registers UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 UART2 transmit/receive mode register (address 6416) Bit name Bit 0 Serial I/O mode selection bits (Note 1) 1 @ 2 @ Functions At reset RW 0 RW 0 RW 0 RW b2 b1 b0 0 0 0: Serial I/O is ignored. (P7 functions as a programmable I/O port) 0 0 1: Clock synchronous serial I/O mode 0 1 0: 0 1 1: Do not select. 1 0 0: UART mode (Transfer data length = 7 bits) 1 0 1: UART mode (Transfer data length = 8 bits) 1 1 0: UART mode (Transfer data length = 9 bits) 1 1 1: Do not select. 3 Internal/External clock selection 0: Internal clock bit 1: External clock 0 RW 4 Stop bit length selection bit (Valid in the UART mode.) (Note 2) 0: One stop bit 1: Two stop bits 0 RW 5 Odd/Even Parity selection bit (Valid in the UART mode when the parity enable bit = "1".) (Note 2) 0: Odd parity 1: Even parity 0 RW 6 Parity enable bit (Valid in the UART mode.) (Note 2) 0: Parity is disabled. 1: Parity is enabled. 0 RW 7 Not implemented. Undefined -- Notes 1: By specifying these bits, an A-D conversion interrupt or a UART2 transmit/receive interrupt is selected. When bits 2 to 0 = "0002," an A-D conversion interrupt is selected. When bits 2 to 0 = "0012" or "1002 to 1112," a UART2 transmit/receive interrupt is selected. 2: In the clock synchronous serial I/O mode, bits 4 to 6 are ignored. (They may be "0" or "1.") UART2 transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 UART2 transmit/receive control register 0 (address 6816) Bit name Bit 0 1 BRG count source selection bits @ Functions b1 b0 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 RW 0 RW 0 RW 2 CTS enable bit 0: The CTS function is enabled. 1: The CTS function is disabled. (P80 and P84 function as programmable I/O ports.) 0 RW 3 Transmission register empty flag 0: Data is present in the transmission register. (Transmission is in progress.) 1: No data is present in the transmission @ @ register. (Transmission is completed.) 1 RO 7 to 4 Not implemented. Clocks f2, f16, f64, and f512: Refer to chapter "14. CLOCK GENERATING CIRCUIT." 21-32 Atreset 7733 Group User's Manual Undefined [ APPENDIX Appendix 3. Control registers Oscillation circuit control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Oscillation circuit control register 0 (address 6C16) Bit Bit name Functions 0: Drivability "LOW" 1: Drivability "HIGH" At reset RW 1 RW (Note 1) Undefined - 0 XCOUT drivability selection bit 1 Not implemented. 2 Main clock stop bit 0: Main clock oscillation or external clock input is available. 1: Main clock oscillation or external clock input is stopped. 0 RW (Note 1) 3 System clock selection bit When the port-Xc selection bit = "0," 0: Main clock 1: Main clock divided by 8 When the port-Xc selection bit = "1," 0: Main clock 1: Sub clock 0 RW (Note 2) 4 P ort-X c selection bit 0: Operate as I/O ports (P77, P76). 1: Operate as pins XCIN and XCOUT. 0 5 System clock stop bit at wait state (Note 4) 0: Operates in the wait mode. 1: Stopped in the wait mode. 0 RW 6 Signal output disable selection bit 0: Output is enabled. 1: Output is disabled. 0 RW 7 Not implemented. Undefined - (Refer to Tables 12.1.2 and 12.1.5) RW (Notes 2 and 3) Notes 1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc selection bit = "1." 2: When selecting the sub clock as the system clock, set bit 3 to "1" after setting bit 4 to "1." If the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to "1." 3: Although this bit can be set to "1," it cannot be cleared to "0" after this bit is once set to "1." 4: When setting the system clock stop bit at wait state to "1," perform it immediately before the WIT instruction is executed. Furthermore, clear this bit to "0" immediately after the wait mode is terminated. 7733 Group User's Manual 21-33 APPENDIX Appendix 3. Control registers Port function control register b7 b6 b5 b4 0 b3 b2 b1 b0 Port function control register (address 6D16) At reset RW 0 RW Sub-clock output selection bit/ *Port-XC selection bit = "0" (when the sub clock is not used) Timer B2 clock source selection Timer B2 (event counter mode) bit clock source selection (Note 1) 0: TB2IN input (event counter mode) 1: Main clock divided by 32 (clock timer) *Port-XC selection bit = "1" (when the sub clock is used) Sub-clock output selection 0: Pin P67/TB2IN/ SUB functions as a programmable I/O port. 1: Sub clock SUB is output from pin P67/TB2IN/ SUB. 0 RW 2 Timer B1 internal connect selection bit (Note 2) 0: No internal connection 1: Internal connection with timer B2 0 RW 3 Port P6 pull-up selection bit 0 0: No pull-up for pins P62/INT0 and P63/INT1 1: With pull-up for pins P62/INT0 and P63/INT1 0 RW 4 Must be fixed to "0." 0 RW 5 Port P6 pull-up selection bit 1 *Key input interrupt selection bit = "0" 0: No pull-up for pin P64/INT2 1: With pull-up for pin P64/INT2 *Key input interrupt selection bit = "1" 0: Pin P64/INT2 is a port with no pull-up. 1: Pin P64/INT2 is an input pin with pull-up and is used for the key input interrupt. 0 RW 6 Port P5 pull-up selection bit 0: No pull-up for pins P54/TA2OUT/KI0 to P57/TA3IN/KI3 1: With pull-up for pins P54/TA2OUT/KI0 to P57/TA3IN/KI3 0 RW 7 Key input interrupt selection bit 0: INT2 interrupt 1: Key input interrupt 0 RW Bit 0 1 Bit name Standby state selection bit Functions 0: Pins P0 to P3 are used for the external bus output. 1: Pins P0 to P3 are used for the port output. Port-Xc selection bit : Bit 4 of the oscillation circuit control register 0 (address 6C16) Notes 1: When the port-Xc selection bit = "0" and timer B2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: When timer B1 operates in the event counter mode, bit 2 is valid. 21-34 7733 Group User's Manual APPENDIX Appendix 3. Control registers Serial transmit control register b7 b6 b5 b4 b3 b2 b1 b0 Serial transmit control register (address 6E16) Bit Functions Bit name 3 to 0 Not implemented. 4 5 7, 6 Transmission clock output pin selection bits (Valid only in the clock synchronous serial I/O mode.) (Note) b5 b4 0 0: One transfer clock output pin (CLK0) 0 1: Multiple transfer clock 1 0: output pins 1 1: Not implemented. Value "0" is read out from here. At reset RW Undefined -- 0 RW 0 RW 0 -- When using multiple transfer clock output pins, satisfy the following conditions: Serial I/O mode selection bits (bits 2 to 0 at address 3016) = "0012" Internal/external clock selection bit (bit 3 at address 3016) = "0" CTS/RTS enable bit (bit 4 at address 3416) = "1" Receive enable bit (bit 2 at address 3516) = "0" (for cases and in Table 8.3.4) Transmission clock output pin selection bits = "012", "102", or "112" (Refer to Table 8.3.3.) Note: Bits 4 and 5 are ignored in the UART mode. (They may be "0" or "1.") 7733 Group User's Manual 21-35 APPENDIX Appendix 3. Control registers A A AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA Oscillation circuit control register 1 b7 b6 b5 b4 0 b3 b2 b1 b0 Oscillation circuit control register 1 (address 6F16) Bit Bit name Functions 0 Main clock division selection bit 0: Main clock is divided by 2. (Note 1) 1: Main clock is not divided by 2. 1 Main clock external input selection bit 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating (Note 1) stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. 2 Sub clock external input selection bit 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT. (Note 1) Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. At reset RW 0 RW 0 RW 0 RW AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA 3 Ignored in the mask ROM and external ROM versions. 0 RW (Note 3) Must be fixed to "1" in the one time PROM and EPROM versions (Notes 1 and 2). 1 4 Must be fixed to "0" (Note 2). 0 RW 5 Not implemented. Undefined -- 6 Not implemented. Undefined -- 7 Clock prescaler reset bit 0 WO By writing "1" to this bit, clock prescaler is initialized. Notes 1: When writing to this register, follow the procedure shown in Figure 10.2.3. 2: The case where data "010101012" is written with the procedure shown in Figure 10.2.3 is not included. 3: In the 7735 Group, fix this bit to "0." * When performing clock prescaler reset Write data "8016." (LDM instruction) * When writing to bits 0 to 3 Write data "010101012." (LDM instruction) Next instruction Write data "00001XXX2." (LDM instruction) (b3 in Figure 10.2.2) 21-36 7733 Group User's Manual (b2 to b0 in Figure 10.2.2) APPENDIX Appendix 3. Control registers Interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 A-D/UART2 trans./rece., UART0 and 1 transmission, UART0 and 1 receive, Timers A0 to A4, Timers B0 to B2 interrupt control registers (addresses 7016 to 7C16) Bit Bit name Interrupt priority level 0 selection bits 1 2 Interrupt request bit 3 Functions b2b1b0 0 0 0 : Level 0 (Interrupt is disabled.) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: No interrupt request has occurred. 1: Interrupt request has occurred. At reset RW 0 RW 0 RW 0 RW 0 RW Undefined -- 4 Not implemented. 5 6 7 b7 b6 b5 b4 b3 b2 b1 b0 INT0, INT1, and INT2/Key input interrupt control registers (addresses 7D16 to 7F16) Bit Bit name Interrupt priority level 0 selection bits 1 2 Functions b2b1b0 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 Interrupt request bit (Note) 0: No interrupt request has occurred. 1: Interrupt request has occurred. Polarity selection bit 4 0: Interrupt request bit is set to "1" at "H" level when level sense is selected; this bit is set to "1" at falling edge when edge sense is selected. 1: Interrupt request bit is set to "1" at "L" level when level sense is selected; this bit is set to "1" at rising edge when level sense is selected. Level sense/Edge sense 5 selection bit 0: Edge sense 1: Level sense 3 6 Not implemented. 7 At reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW Undefined -- Note: The interrupt request bits of INT0 to INT2/Key input interrupts are ignored when the level sense is selected. 7733 Group User's Manual 21-37 APPENDIX Appendix 4. Package outlines Appendix 4. Package outlines 21-38 7733 Group User's Manual APPENDIX Appendix 4. Package outlines 7733 Group User's Manual 21-39 APPENDIX Appendix 4. Package outlines 21-40 7733 Group User's Manual APPENDIX Appendix 5. Hexadecimal instruction code table Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE-1 D3-D0 D7-D4 0000 Hexadecimal notation 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F SEB ORA ORA ORA SEB ORA ASL ORA A,(DIR,X) A,SR DIR,b A,DIR DIR A,L(DIR) ORA CLB ORA ASL ORA A,(DIR),Y A,(DIR) A,(SR),Y DIR,b A,DIR,X ORA 0001 0010 0011 1 ORA JSR AND JSR AND BBS AND ROL AND A,(DIR,X) ABL A,SR DIR,b,R A,DIR DIR A,L(DIR) 4 AND AND AND BBC AND ROL AND RTI A,(DIR,X) EOR Note 1 EOR EOR 1101 A,DIR,X ADC DIR,X A,L(DIR),Y ROR ADC ADC E 1111 F LSR BRA ADC DIR A,DIR DIR A,L(DIR) A,IMM ADC ROR ADC ADC DIR,X A,L(DIR),Y STX STA A,(DIR,X) REL A,SR DIR A,DIR DIR A,L(DIR) STA STA STA STY STA STX STA LDA LDX LDA LDY LDA IMM A,(DIR,X) IMM A,SR DIR A,DIR DIR A,L(DIR) LDA LDA LDA LDY LDA LDX Note 2 LDA CMP CLP CMP CPY CMP IMM A,(DIR,X) IMM A,SR DIR A,DIR CMP CMP CMP CMP A,L(DIR) DEC CMP PEI BNE CPX SBC SEP SBC CPX SBC INC SBC IMM A,(DIR,X) IMM A,SR DIR A,DIR DIR A,L(DIR) SBC SBC SBC INC SBC BEQ A,(DIR),Y A,(DIR) A,(SR),Y SBC PEA A,DIR,X DIR,X A,L(DIR),Y ABS A,ABS ABS A,ABL JMP EOR LSR EOR A,ABS,X ABS,X A,ABL,X ADC ROR ADC ADC ABS A,ABL ROR ADC (ABS,X) A,ABS,X ABS,X A,ABL,X TXA STY STA STX STA ABS LDM A,ABS ABS A,ABL STA LDM STA PHT TXY ABS LDY LDA LDX LDA ABS A,ABS ABS A,ABL LDY LDA LDX LDA TAX TSX TYX ABS,X A,ABS,X ABS,Y A,ABL,X CMP DEX CMP PHX CMP DEC CMP ABS A,ABS ABS A,ABL JMP CMP DEC CMP STP L(ABS) A,ABS,X ABS,X A,ABL,X SBC NOP PSH PLX PUL SBC A,ABS,Y CPY WIT A,ABS,Y A,IMM A,ABS,X ABS,X A,ABL,X PLT A,IMM SEM EOR TDA LDA INX AND LSR JMP A,ABS,Y DIR,X A,L(DIR),Y ROL LDA CLM A,DIR,X A,ABL A,ABS,Y INY DIR AND (ABS) A,ABS A TXS CLV CPY AND ABS EOR ABL A,IMM DIR,Y A,L(DIR),Y DEC CMP ROL JMP JMP STA TAY BCS AND TAD A,ABS,Y DIR,Y A,L(DIR),Y LDX LDA LDY BBC ROR PLY TYA BCC ORA RTL LDM STA ASL ABS,b,R A,ABS,X ABS,X A,ABL,X A,ABS,Y ADC STY BBS ABS,b,R A,ABS A PHY A,SR STA ORA PHG PLA A,(DIR),Y A,(DIR) A,(SR),Y 1110 EOR SEI STA CLB ABS,b A,ABS,X ABS,X A,ABL,X TSA CLI C D A EOR A,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X 1100 INC A,IMM A B AND A,ABS,Y EOR LDM ORA A,ABL PLD A,L(DIR) A,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X 1011 A DIR DEY REL 1010 ROL LSR 8 9 AND A,IMM EOR ADC ABS,b A,ABS TAS A,DIR A,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X 1001 A EOR BVS BRA 1000 DEC PHA PER RTS ADC 7 EOR MVN A,(DIR,X) 0111 ORA A,ABS,Y A,SR BVC ADC 6 LSR MVP A,(DIR),Y A,(DIR) A,(SR),Y 0110 DIR,X A,L(DIR),Y ASL ABS PHD SEC BMI EOR 5 A PLP EOR 0101 DIR,X A,L(DIR),Y ABS A,(DIR),Y A,(DIR) A,(SR),Y DIR,b,R A,DIR,X 0100 ASL CLC BPL 2 3 ORA A,IMM PHP BRK CPX SBC INC SBC ABS A,ABS ABS A,ABL JSR SBC INC SBC (ABS,X) A,ABS,X ABS,X A,ABL,X Notes 1: 4216 specifies the contents of the INSTRUCTION CODE TABLE-2. About the second word's codes, refer to the INSTRUCTION CODE TABLE-2. 2: 8916 specifies the contents of the INSTRUCTION CODE TABLE-3. About the second word's codes, refer to the INSTRUCTION CODE TABLE-2. 7733 Group User's Manual 21-41 APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE-2 (The first word's code of each instruction is 4216 ) D3-D0 D7-D4 0000 Hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ORA ORA ORA ORA ORA ASL ORA ORA B,(DIR,X) B,SR B,DIR B,L(DIR) B,IMM B B,ABS B,ABL 0 ORA 0001 ORA ORA AND AND AND ROL AND AND B,DIR B,L(DIR) B,IMM B B,ABS B,ABL AND AND AND AND B,ABS,X B,ABL,X EOR B,ABS B,ABL PHB EOR EOR EOR EOR EOR B,DIR,X B,L(DIR),Y B,ABS,Y EOR EOR B,ABS,X B,ABL,X TBD 5 ADC ADC ADC ADC B,(DIR,X) B,SR B,DIR B,L(DIR) ADC ROR ADC ADC B,IMM B B,ABS B,ABL PLB 6 ADC ADC ADC ADC ADC B,DIR,X B,L(DIR),Y B,ABS,Y ADC ADC B,ABS,X B,ABL,X TDB 7 STA STA STA STA B,(DIR,X) B,SR B,DIR B,L(DIR) STA STA B,ABS B,ABL TXB 8 STA STA STA STA B,DIR,X B,L(DIR),Y LDA LDA 9 LDA TYB A LDA STA STA STA B,ABS,Y B,ABS,X B,ABL,X LDA LDA LDA TBY B,IMM TBX B,SR B,DIR B,L(DIR) B,ABS B,ABL LDA LDA LDA LDA LDA LDA B B,DIR,X B,L(DIR),Y B,ABS,Y B,ABS,X B,ABL,X CMP CMP CMP CMP CMP CMP B,SR B,DIR B,L(DIR) B,IMM B,ABS B,ABL CMP CMP CMP CMP CMP CMP C B,(DIR,X) CMP CMP D B,(DIR),Y B,(DIR) B,(SR),Y SBC E B,(DIR,X) SBC 21-42 EOR B EOR B,L(DIR) CMP 1111 LSR EOR B,DIR B,(DIR),Y B,(DIR) B,(SR),Y 1110 EOR B,IMM EOR B,SR LDA 1101 B EOR B,(DIR,X) 1100 INC B,(DIR,X) LDA 1011 AND B,ABS,Y 4 B,(DIR),Y B,(DIR) B,(SR),Y 1010 AND B,L(DIR),Y TSB STA 1001 AND B,DIR,X 3 B,(DIR),Y B,(DIR) B,(SR),Y 1000 ORA B,ABL,X AND ADC 0111 ORA B,ABS,X B,SR B,(DIR),Y B,(DIR) B,(SR),Y 0110 B AND EOR 0101 DEC B,(DIR,X) B,(DIR),Y B,(DIR) B,(SR),Y 0100 ORA B,ABS,Y 2 AND 0011 ORA B,L(DIR),Y TBS B,(DIR),Y B,(DIR) B,(SR),Y 0010 ORA B,DIR,X 1 F SBC B,DIR,X B,L(DIR),Y B,ABS,Y B,ABS,X B,ABL,X SBC SBC SBC SBC SBC SBC B,SR B,DIR B,L(DIR) B,IMM B,ABS B,ABL SBC SBC SBC SBC SBC SBC B,DIR,X B,L(DIR),Y B,ABS,Y B,ABS,X B,ABL,X B,(DIR),Y B,(DIR) B,(SR),Y 7733 Group User's Manual APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE-3 (The first word's code of each instruction is 89 16) D3-D0 D7-D4 0000 Hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F MPY MPY MPY MPY MPY SR DIR L(DIR) IMM ABS ABL MPY MPY MPY MPY MPY MPY ABL,X MPY 0001 MPY 1 (SR),Y DIR,X L(DIR),Y ABS,Y ABS,X DIV DIV DIV DIV DIV DIV DIV (DIR,X) SR DIR L(DIR) IMM ABS ABL (DIR),Y (DIR) 0010 XAB 2 DIV 0011 MPY MPY (DIR,X) 0 DIV DIV DIV DIV DIV DIV DIV (SR),Y DIR,X L(DIR),Y ABS,Y ABS,X ABL,X 3 (DIR),Y (DIR) RLA 0100 4 IMM 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C LDT IMM 1101 D 1110 E 1111 F 7733 Group User's Manual 21-43 APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing modes Symbol Functions Details IMP op A CC,CA CC+M+C ADC (Notes 1,2) A CCA CCM AND (Notes 1,2) ASL (Note 1) m=0 C b 15 *** b0 0 m=1 C b 7 *** b0 0 Adds the carry, the accumulator and the memory contents.The result is entered into the accumulator. When the D flag is "0," binary additions is done, and when the D flag is "1," decimal addition is done. Obtains the logical product of the contents of the accumulator and the contents of the memory . The result is entered into the accumulator. DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y 65 4 2 75 5 2 72 6 2 61 7 2 71 8 2 42 4 3 69 42 6 3 65 42 7 3 75 42 8 3 42 9 3 42 10 3 72 61 71 29 2 2 25 4 2 35 5 2 32 6 2 21 7 2 31 8 2 42 4 3 29 42 6 3 25 42 7 3 35 42 8 3 42 9 3 42 10 3 32 21 31 0A 2 1 06 7 2 16 7 2 42 4 2 0A Tests the specified bit of the memory. Branches when all the contents of the specified bit is "0." BBS Mb=1? (Notes 3,5) Tests the specified bit of the memory. Branches when all the contents of the specified bit is "1." BCC (Note 3) C=0? Branches when the contents of the C flag is "0." BCS (Note 3) C=1? Branches when the contents of the C flag is "1." BEQ (Note 3) Z=1? Branches when the contents of the Z flag is "1." BMI (Note 3) N=1? Branches when the contents of the N flag is "1." BNE (Note 3) Z=0? Branches when the contents of the Z flag is "0." BPL (Note 3) N=0? Branches when the contents of the N flag is "0." BRA (Note 4) PCPCoffset PGPG+1 (when carry occurs) PGPG-1 (when borrow occurs) Jumps to the address indicated by the program counter plus the offset value. BRK PCPC+2 M(S)PG SS-1 M(S)PCH SS-1 M(S)PCL SS-1 M(S)PSH SS-1 M(S)PSL SS-1 I1 PCLAD L PCHADH PG00 16 Executes software interruption. BVC (Note 3) V=0? Branches when the contents of the V flag is "0." BVS (Note 3) V=1? Branches when the contents of the V flag is "1." CLB (Note 5) Mb0 Makes the contents of the specified bit in the memory "0." CLC C0 Makes the contents of the C flag "0." 18 2 1 CLI I0 Makes the contents of the I flag "0." 58 2 1 CLM m0 Makes the contents of the m flag "0." D8 2 1 CLP PSb0 Specifies the bit position in the processor status register by the bit pattern of the second byte in the instruction, and sets "0" in that bit. CLV V0 Makes the contents of the V flag "0." 21-44 A 69 2 2 Shifts the accumulator or the memory contents one bit to the left. "0" is entered into bit 0 of the accumulator or the memory. The contents of bit 15 ( bit 7 when the m flag is "1") of the accumulator or memory before shift is entered into the C flag. BBC Mb=0? (Notes 3,5) CMP A CC-M (Notes 1,2) IMM n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 00 15 2 Compares the contents of the accumulator with the contents of the memory. 14 8 3 C2 4 2 B8 2 1 C9 2 2 C5 4 2 D5 5 2 D2 6 2 C1 7 2 D1 8 2 42 4 3 C9 42 6 3 C5 42 7 3 D5 42 8 3 42 9 3 42 10 3 D2 C1 D1 7733 Group User's Manual APPENDIX Appendix 6. Machine instructions Addressing modes L(DIR) L(DIR),Y op ABS ABS,b ABS,X ABS,Y ABL ABL,X (ABS) L(ABS) (ABS,X) Processor status register STK REL DIR,b,R ABS,b,R SR (SR),Y BLK 10 9 8 7 6 5 4 3 2 1 0 n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 67 10 2 77 11 2 6D 4 3 7D 6 3 79 6 3 6F 6 4 7F 7 4 63 5 2 73 8 2 42 12 3 42 13 3 42 6 4 67 77 6D 42 8 4 42 8 4 42 8 5 42 9 5 7D 79 6F 7F 42 7 3 42 10 3 63 73 27 10 2 37 11 2 2D 4 3 3D 6 3 39 6 3 2F 6 4 3F 7 4 23 5 2 33 8 2 42 12 3 42 13 3 42 6 4 27 37 2D 42 8 4 42 8 4 42 8 5 42 9 5 3D 39 2F 3F 42 7 3 42 10 3 23 33 0E 7 3 1E 8 3 N V m x D I Z C IPL * * * N V * * * * Z C * * * N * * * * * Z * * * * N * * * * * Z C 34 7 4 3C 8 5 * * * * * * * * * * * 24 7 4 2C 8 5 * * * * * * * * * * * 90 4 2 * * * * * * * B0 4 2 * * * * F0 4 2 * 30 4 2 * * * * * * * * * * * D0 4 2 * * * * * * * * 10 4 2 * * * * * * * * * * * 80 4 2 * * * * * * * * * * * * * * * * * * * * * * 50 4 2 * * * * * * * * * * * 70 4 2 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 82 4 3 IC 9 4 * * * * * * * * * * * * * * * * * * * * * 0 * * * * * * * * 0 * * * * * * * 0 * * * * * * * * Specified flag becomes "0." * * * C7 10 2 D7 11 2 CD 4 3 DD 6 3 D9 6 3 CF 6 4 DF 7 4 C3 5 2 D3 8 2 42 12 3 42 13 3 42 6 4 C7 D7 CD 42 8 4 42 8 4 42 8 5 42 9 5 DD D9 CF DF 42 7 3 42 10 3 C3 D3 7733 Group User's Manual * * 0 * * * N * * * * * * * * * * Z C 21-45 APPENDIX Appendix 6. Machine instructions Addressing modes Symbol Functions Details IMP op IMM A DIR DIR,b DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y n # op n # op n # op n # op n # op n # op n # op n # op n # op n # CPX (Note 2) X-M Compares the contents of the index register X with the contents of the memory. E0 2 2 E4 4 2 CPY (Note 2) Y-M Compares the contents of the index register Y with the contents of the memory. C0 2 2 C4 4 2 DEC (Note 1) A CCA CC-1 or MM-1 Decrements the contents of the accumlator or memory by 1. 1A 2 1 C6 7 2 D6 7 2 42 4 2 1A DEX XX-1 Decrements the contents of the index register X by 1. CA 2 1 DEY YY-1 Decrements the contents of the index register Y by 1. 88 2 1 DIV (Notes 2,10) A(quotient)B,A/M B(remainder) The numeral that places the contents of accumlator B to the higher order and the contents of accumulator A to the lower order is divided by the contents of the memory. The quotient is entered into accumulator A and the remainder into accumulator B. 89 27 3 29 89 29 3 25 89 30 3 35 89 31 3 89 32 3 89 33 3 32 21 31 EOR (Notes 1,2) A CCA CCM Logical exclusive sum is obtained of the contents of the accumulator and the contents of the memory. The result is placed into the accumulator. 49 2 2 45 4 2 55 5 2 52 6 2 41 7 2 51 8 2 42 4 3 49 42 6 3 45 42 7 3 55 42 8 3 42 9 3 42 10 3 52 41 51 3A 2 1 E6 7 2 F6 7 2 INC (Note 1) A CCA CC+1 or MM+1 Increments the contents of the accumulator or memory by 1. 42 4 2 3A INX XX+1 Increments the contents of the index register X by 1. E8 2 1 INY YY+1 Increments the contents of the index register Y by 1. C8 2 1 JMP ABS PC LADL PCHADH Places a new address into the program counter and jumps to that new address. ABL PC LADL PCHADH PGADG (ABS) PC L(ADH, AD L) PCH(ADH,AD L+1) L(ABS) PC L(ADH, AD L) PC H(AD H, ADL+1) PG(AD H, ADL+2) (ABS, X) PC L(ADH, AD L+X) PC H(AD H, AD L+X +1) JSR ABS M(S)PCH SS-1 M(S)PCL SS-1 PC LADL PCHADH Saves the contents of the program counter (also the contents of the program bank register for ABL) into the stack, and jumps to the new address. ABL M(S)PG SS-1 M(S)PCH SS-1 M(S)PCL SS-1 PC LADL PCHADH PGADG (ABS, X) M(S)PCH SS-1 M(S)PCL SS-1 PC L(ADH, AD L+X) PC H(AD H, AD L+X +1) 21-46 7733 Group User's Manual APPENDIX Appendix 6. Machine instructions Addressing modes L(DIR) L(DIR),Y op ABS ABS,b ABS,X ABS,Y ABL ABL,X (ABS) L(ABS) (ABS,X) Processor status register STK REL DIR,b,R ABS,b,R SR (SR),Y BLK n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 10 9 8 7 6 5 4 3 2 1 0 IPL N V m x D I Z C EC 4 3 * * * N * * * * * Z C CC 4 3 * * * N * * * * * Z C * * * N * * * * * Z * CE 7 3 DE 8 3 * * * N * * * * * * N * * * * Z * * * * Z * 89 35 3 89 36 3 89 29 4 27 2D 37 89 31 4 89 31 4 89 31 5 89 32 5 39 3D 2F 3F 89 30 3 89 33 3 23 33 * * * N V * * * * Z C 47 10 2 57 11 2 4D 4 3 5D 6 3 59 6 3 4F 6 4 5F 7 4 43 5 2 53 8 2 * * * N * 42 12 3 42 13 3 42 6 4 47 57 4D 42 8 4 42 8 4 42 8 5 42 9 5 59 5D 4F 5F 42 7 3 42 10 3 43 53 EE 7 3 FE 8 3 * * * * Z * * * * N * * * * * Z * * * * N * * * * * Z * * * * N * * * * * * * * * * * * * * * * 4C 2 3 5C 4 4 6C 4 3 DC 8 3 7C 6 3 * * * * * 20 6 3 22 8 4 FC 8 3 * * * * 7733 Group User's Manual * * Z * 21-47 APPENDIX Appendix 6. Machine instructions Addressing modes Symbol Functions Details IMP op LDA (Notes 1,2) A CCM IMM A DIR DIR,b DIR,X Enters the contents of the memory into the accummulator. B5 5 2 B2 6 2 A1 7 2 B1 8 2 42 4 3 A9 42 6 3 A5 42 7 3 B5 42 8 3 42 9 3 42 10 3 B2 A1 B1 64 4 3 74 5 3 Enters the immediate vaiue into the memory. LDT DTIMM Enters the immediate value into the data bank regiater. 89 5 3 C2 LDX (Note 2) XM Enters the contents of the memory into index register X. A2 2 2 A6 4 2 LDY (Note 2) YM Enters the contents of the memory into index register Y. A0 2 2 A4 4 2 B4 5 2 LSR (Note 1) m=0 0 b 15 *** b0 C m=1 0 b 7 *** b 0 C Shifts the contents of the accumulator or the contents of the memory one bit to the right. The bit 0 of the accumulator or the memory is entered into the C flag. "0" is entered into bit 15 (bit 7 when the m flag is "1.") 4A 2 1 46 7 2 56 7 2 MPY (Notes 2,11) B, AAM Multiplies the contents of accumulator A and the contents of the memory. The higher order of the result of operation are entered into accumulator B, and the lower order into accumulator A. MVN (Note 8) Mn+iMm+i Transmits the data block. The transmission is done from the lower order address of the block. MVP (Note 9) Mn-iMm-i Transmits the data block. Transmission is done form the higher order address of the data block. NOP PCPC+1 Advances the program counter, but pertorms nothing else. EA 2 1 ORA (Notes 1,2) A CCA CCVM Logical sum per bit of the contents of the accumulator and the contents of the memory is obtained. The result is entered into the accumulator. The 3rd and the 2nd bytes of the instruction are saved into the stack, in this order. PEI M(S)M((DPR)+IMM +1) SS-1 M(S)M((DPR)+IMM) SS-1 Specifies 2 sequential bytes in the direct page in the 2nd byte of the instruction, and saves the contents into the stack. PER EARPC+IMM 2,IMM1 M(S)EARH SS-1 M(S)EARL SS-1 Regards the 2nd and 3rd bytes of the instruction as 16-bit numerals, adds them to the program counter, and saves the result into the stack. PHA m=0 M(S)AH SS-1 M(S)A L SS-1 Saves the contents of accumulator A into the stack. m=0 M(S)BH SS-1 M(S)B L SS-1 89 16 3 09 89 18 3 05 89 19 3 15 89 20 3 89 21 3 89 22 3 01 11 12 09 2 2 05 4 2 15 5 2 12 6 2 01 7 2 11 8 2 42 4 3 09 42 6 3 05 42 7 3 15 42 8 3 42 9 3 42 10 3 12 01 11 Saves the contents of accumuator B into the stack. m=1 M(S)B L SS-1 21-48 B6 5 2 42 4 2 4A m=1 M(S)A L SS-1 PHB (DIR,X) (DIR),Y A5 4 2 MIMM M(S)IMM2 SS-1 M(S)IMM1 SS-1 (DIR) A9 2 2 LDM (Note 5) PEA DIR,Y n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 7733 Group User's Manual APPENDIX Appendix 6. Machine instructions Addressing modes L(DIR) L(DIR),Y op ABS ABS,b ABS,X ABS,Y ABL ABL,X (ABS) L(ABS) (ABS,X) Processor status register STK REL DIR,b,R ABS,b,R SR (SR),Y BLK 10 9 8 7 6 5 4 3 2 1 0 n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # A7 10 2 B7 11 2 AD 4 3 BD 6 3 B9 6 3 AF 6 4 BF 7 4 A3 5 2 B3 8 2 42 12 3 42 13 3 42 6 4 A7 B7 AD 42 8 4 42 8 4 42 8 5 42 9 5 BD B9 AF BF 42 7 3 42 10 3 A3 B3 9C 5 4 N V m x D I Z C * * * N * * 9E 6 4 AE 4 3 IPL BE 6 3 * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * * N * * * * * Z * AC 4 3 BC 6 3 * * * N * * * * * Z * 4E 7 3 5E 8 3 * * * 0 * * * * * Z C * * * * * * Z 0 * * * * * * * * * * * 89 24 3 89 25 3 89 18 4 17 07 0D 89 20 4 89 20 4 89 20 5 89 21 5 1D 1F 19 0F 89 19 3 89 22 3 03 13 54 7 3 + * N * i 7 2 44 9 3 * * * * * + * * * * * * i 7 2 * * * * * * * * * * * * * N * * * * * Z * F4 5 3 * * * * * * * * * * * D4 6 2 * * * * * * * * * * * 62 5 3 * 48 4 1 * * 42 6 2 48 * * * * * 07 10 2 17 11 2 0D 4 3 1D 6 3 19 6 3 0F 6 4 1F 7 4 03 5 2 13 8 2 42 12 3 42 13 3 42 6 4 07 17 0D 42 8 4 42 8 4 42 8 5 42 9 5 1D 19 0F 1F 42 7 3 42 10 3 03 13 7733 Group User's Manual * * * * * * * * * * * * * * * * * * * * * * * * * * 21-49 APPENDIX Appendix 6. Machine instructions Addressing modes Symbol Functions Details IMP op PHD M(S)DPRH SS-1 M(S)DPR L SS-1 Saves the contents of the direct page register into the stack. PHG M(S)PG SS-1 Saves the contents of the program bank register into the stack. PHP M(S)PSH SS-1 M(S)PSL SS-1 Saves the contents of the program status register into the stack. PHT M(S)DT SS-1 Saves the contents of the data bank register into the stack. PHX x=0 M(S)XH SS-1 M(S)X L SS-1 Saves the contents of the index register X into the stack. x=0 M(S)YH SS-1 M(S)Y L SS-1 Saves the contents of the index register Y into the stack. x=1 M(S)Y L SS-1 PLA m=0 SS+1 A LM(S) SS+1 A HM(S) Restores the contents of the stack on the accumulator A. m=1 SS+1 A LM(S) PLB m=0 SS+1 B LM(S) SS+1 B HM(S) Restores the contents of the stack on the accumulator B. m=1 SS+1 B LM(S) PLD SS+1 DPR LM(S) SS+1 DPR HM(S) Restores the contents of the stack on the direct page register. PLP SS+1 PS LM(S) SS+1 PS HM(S) Restores the contents of the stack on the processor status register. PLT SS+1 DTM(S) Restores the contents of the stack on the data bank register. PLX x=0 SS+1 X LM(S) SS+1 X HM(S) Restores the contents of the stack on the index register X. x=1 SS+1 X LM(S) 21-50 A DIR n # op n # op n # op n # x=1 M(S)X L SS-1 PHY IMM 7733 Group User's Manual DIR,b op DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y n # op n # op n # op n # op n # op n # APPENDIX Appendix 6. Machine instructions Addressing modes L(DIR) L(DIR),Y op ABS ABS,b ABS,X ABS,Y ABL ABL,X (ABS) L(ABS) (ABS,X) Processor status register STK REL DIR,b,R ABS,b,R SR (SR),Y BLK n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 10 9 8 7 6 5 4 3 2 1 0 IPL N V m x D I Z C 0B 4 1 * * * * * * * * * * * 4B 3 1 * * * * * * * * * * * 08 4 1 * * * * * * * * * * * 8B 3 1 * * * * * * * * * * * DA 4 1 * * * * * * * * * * * 5A 4 1 * * * * * * * * * * * 68 5 1 * * * N * * * * * Z * 42 7 2 68 * * * N * * * * * Z * 2B 5 1 * * * * * * 28 6 1 Value saved in stack. AB 6 1 * * * N * * * * * Z * FA 5 1 * * * N * * * * * Z * 7733 Group User's Manual * * * * * 21-51 APPENDIX Appendix 6. Machine instructions Addressing modes Symbol Functions Details IMP op PLY x=0 SS+1 Y LM(S) SS+1 Y HM(S) IMM A DIR n # op n # op n # op n # DIR,b op DIR,X DIR,Y (DIR) (DIR,X) (DIR),Y n # op n # op n # op n # op n # op n # Restores the contents of the stack on the index register Y. x=1 SS+1 Y LM(S) PSH (Note 6) M(S)A, B, X*** Saves the registers among accumulator, index register, direct page register, data bank register, program bank register, or processor status register, specified by the bit pattern of the second byte of the instruction into the stack. PUL (Note 7) A, B, X***M(S) Restores the contents of the stack to the registers among accumulator, index register, direct page register, data bank register, or processor status register, specified by the bit pattern of the second byte of the instruction. RLA (Note 13) m=0 n bit rotate left Rotates the contents of the accumulator A, n bits to the left. 89 6 3 49 + i b15 *** b0 m=1 n bit rotate left b 7 *** b 0 ROL (Note 1) m=0 b 15 *** b0 C Links the accumulator or the memory to C flag, and rotates result to the left by 1 bit. 2A 2 1 26 7 2 36 7 2 42 4 2 2A m=1 b 7 *** b 0 C ROR (Note 1) m=0 C b15 *** b0 Links the accumulator or the memory to C flag, and rotates result to the right by 1 bit. 6A 2 1 66 7 2 76 7 2 42 4 2 6A m=1 C b 7 *** b 0 40 11 1 RTI SS+1 PS LM(S) SS+1 PS HM(S) SS+1 PC LM(S) SS+1 PC HM(S) SS+1 PGM(S) Returns from the interruption routine. RTL SS+1 PC LM(S) SS+1 PC HM(S) SS+1 PGM(S) Returns from the subroutine. The contents of the program 6B 8 1 bank register are also restored. RTS SS+1 PC LM(S) SS+1 PC HM(S) Returns from the subroutine. The contents of the program 60 5 1 bank register are not restored. SBC (Notes 1,2) A CC, CA CC-M-C Subtracts the contents of the memory and the borrow from the contents of the accumulator. 21-52 E9 2 2 E5 4 2 F5 5 2 F2 6 2 E1 7 2 F1 8 2 42 4 3 E9 42 6 3 E5 42 7 3 F5 42 8 3 42 9 3 42 10 3 F2 E1 F1 7733 Group User's Manual APPENDIX Appendix 6. Machine instructions Addressing modes L(DIR) L(DIR),Y op ABS ABS,b ABS,X ABS,Y ABL ABL,X (ABS) L(ABS) (ABS,X) Processor status register STK REL DIR,b,R ABS,b,R SR (SR),Y BLK n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 10 9 8 7 6 5 4 3 2 1 0 IPL N V m x D I Z C 7A 5 1 * * * N * * * * * Z * EB 12 2 * * * * * * + * * * * * 2i1+i2 FB 14 2 If restored the contents of PS, it becomes its value. And the other cases are no change. + 3i1+4i 2 * * * * * * * * * * * 2E 7 3 3E 8 3 * * * N * * * * * Z C 6E 7 3 7E 8 3 * * * N * * * * * Z C Value saved in stack. E7 10 2 F7 11 2 ED 4 3 FD 6 3 F9 6 3 EF 6 4 FF 7 4 E3 5 2 F3 8 2 42 12 3 42 13 3 42 6 4 E7 F7 ED 42 8 4 42 8 4 42 8 5 42 9 5 FD F9 EF FF 42 7 3 42 10 3 F3 E3 7733 Group User's Manual * * * * * * * * * * * * * * * * * * * * * * * * * N V * * * * Z C 21-53 APPENDIX Appendix 6. Machine instructions Addressing modes Symbol Functions Details IMP op SEB (Note 5) Mb1 Makes the contents of the specified bit in the memory "1." SEC C1 Makes the contents of the C flag "1." 38 2 1 SEI I1 Makes the contents of the I flag "1." 78 2 1 SEM m1 Makes the contents of the m flag "1." F8 2 1 SEP PSb1 Set the specified bit of the processor status register's lower byte (PSL) to "1." STA (Note 1) MACC Stores the contents of the accumulator into the memory. STP Stops the oscillation of the oscillator. IMM A DIR n # op n # op n # op n # 92 7 2 81 7 2 91 7 2 42 6 3 85 42 7 3 95 42 9 3 42 9 3 42 9 3 92 81 91 DB 3 1 STY MY Stores the contents of the index register Y into the memory. 84 4 2 TAD DPRA Transmits the contents of the accumulator A to the direct 5B 2 1 page register. TAS SA Transmits the contents of the accumulator A to the stack pointer. TAX XA Transmits the contents of the accumulator A to the index AA 2 1 register X. TAY YA Transmits the contents of the accumulator A to the index A8 2 1 register Y. TBD DPRB Transmits the contents of the accumulator B to the direct 42 4 2 page register. 5B TBS SB Transmits the contents of the accumulator B to the stack 42 4 2 pointer. 1B TBX XB Transmits the contents of the accumulator B to the index 42 4 2 register X. AA TBY YB Transmits the contents of the accumulator B to the index 42 4 2 register Y. A8 TDA ADPR Transmits the contents of the direct page register to the 7B 2 1 accumulator A. TDB BDPR Transmits the contents of the direct page register to the 42 4 2 accumulator B. 7B TSA AS Transmits the contents of the stack pointer to the accumulator A. 3B 2 1 TSB BS Transmits the contents of the stack pointer to the accumulator B. 42 4 2 3B TSX XS Transmits the contents of the stack pointer to the index BA 2 1 register X. TXA AX Transmits the contents of the index register X to the accumulator A. 8A 2 1 TXB BX Transmits the contents of the index register X to the accumulator B. 42 4 2 8A TXS SX Transmits the contents of the index register X to the stack pointer. 9A 2 1 TXY YX Transmits the contents of the index register X to the index 9B 2 1 register Y. TYA AY Transmits the contents of the index register Y to the ac- 98 2 1 cumulator A. TYB BY Transmits the contents of the index register Y to the accumulator B. TYX XY Transmits the contents of the index register Y to the index BB 2 1 register X. 21-54 (DIR,X) (DIR),Y 95 5 2 86 4 2 XAB (DIR) 85 4 2 Stores the contents of the index register X into the memory. Stops the internal clock. DIR,Y E2 3 2 MX A B DIR,X n # op n # op n # op n # op n # op n # 04 8 3 STX WIT DIR,b op 1B 2 1 42 4 2 98 CB 3 1 Exchanges the contents of the accumulator A and the con- 89 6 2 tents of the accumulator B. 28 7733 Group User's Manual 96 5 2 94 5 2 APPENDIX Appendix 6. Machine instructions Addressing modes L(DIR) L(DIR),Y op ABS ABS,b ABS,X ABS,Y ABL ABL,X (ABS) L(ABS) (ABS,X) Processor status register STK REL DIR,b,R ABS,b,R SR (SR),Y BLK n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 0C 9 4 10 9 8 7 6 5 4 3 2 1 0 IPL N V m x D I Z C * * * * * * * * * * * * * * * * * * * * * 1 * * * * * * * * 1 * * * * * * * 1 * * * * * * * * Specified * * * flag * *becomes * * * "1." 87 10 2 97 11 2 8D 5 3 9D 5 3 99 5 3 8F 6 4 9F 7 4 83 5 2 93 8 2 42 12 3 42 13 3 42 7 4 87 97 8D 42 7 4 42 7 4 42 8 5 42 9 5 9D 99 8F 9F 42 7 3 42 10 3 93 83 * * * * * * * * * * * * * * * * * * * * * * 8E 5 3 * * * * * * * * * * * 8C 5 3 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * N * * * * * Z * * * * N * * * * * Z * * * * * * * * * * * * * * * * * * * * * * * * * * N * * * * * Z * * * * N * * * * * Z * * * * N * * * * * Z * * * * N * * * * * Z * * * * N * * * * * Z * * * * N * * * * * Z * * * * N * * * * * Z * * * * N * * * * * Z * * * * N * * * * * Z * * * * * * * * * * * * * * * N * * * * * Z * * * * N * * * * * Z * * * * N * * * * * Z * * * * N * * * * * Z * * * * * * * * * * * * * * * N * * * * * Z * 7733 Group User's Manual 21-55 APPENDIX Appendix 6. Machine instructions The number of cycles shown in the table is described in the case of the fastest mode for each instruction. The number of cycles shown in the table is calculated for DPR L =0. The number of cycles in the addressing mode concerning the DPR when DPR L 0 must be incremented by 1. The number of cycles shown in the table differs according to the bytes fetched into the instruction queue buffer, or according to whether the memory read/write address is odd or even. It also differs when the external region memory is accessed by BYTE="H." Notes 1. The operation code at the upper row is used for accumulator A, and the operation at the lower row is used for accumulator B. 2. When setting flag m=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments by 1. 3. The number of cycles increments by 2 when branching. 4. The operation code on the upper row is used for branching in the range of -128 to +127, and the operation code on the lower row is used for branching in the range of -32768 to +32767. 5. When handling 16-bit data with flag m=0, the byte in the table is incremented by 1. 6. Type of register Number of cycles A 2 B 2 X 2 Y 2 DPR 2 DT 1 PG 1 PS 2 The number of cycles corresponding to the register to be pushed are added. The number of cycles when no pushing is done is 12. i 1 indicates the number of registers among A, B, X, Y, DPR, and PS to be saved, while i2 indicates the number of registers among DT and PG to be saved. 7. Type of register Number of cycles A 3 B 3 X 3 Y 3 DPR 4 DT 3 PS 3 The number of cycles corresponding to the register to be pulled are added. The number of cycles when no pulling is done is 14. i 1 indicates the number of registers among A, B, X, Y, DT, and PS to be restored, while i 2 =1 when DPR is to be restored. 8. The number of cycles is the case when the number of bytes to be transferred is even. When the number of bytes to be transferred is odd, the number is calculated as; 7 + (i/2) 7 + 4 Note that, (i/2) shows the integer part when i is divided by 2. 9. The number of cycles is the case when the number of bytes to be transferred is even. When the number of bytes to be transferred is odd, the number is calculated as; 9 + (i/2) 7 + 5 Note that, (i/2) shows the integer part when i is divided by 2. 10. The number of cycles is the case in the 16-bit / 8-bit operation. The number of cycles is incremented by 16 for 32-bit / 16bit operation. 11. The number of cycles is the case in the 8-bit 8-bit operation. The number of cycles is incremented by 8 for 16-bit 16bit operation. 12. When setting flag x=0 to handle the data as 16-bit data in the immediate addressing mode, the number of bytes increments by 1. 13. When flag m is 0, the byte in the table is incremented by 1. 21-56 7733 Group User's Manual APPENDIX Appendix 6. Machine instructions Symbols in machine instructions table Symbol IMP IMM A DIR DIR, b DIR, X DIR, Y (DIR) (DIR,X) (DIR), Y L (DIR) L (DIR),Y ABS ABS, b ABS, X ABS, Y ABL ABL, X (ABS) L (ABS) (ABS, X) STK REL DIR, b, REL ABS, b, REL SR (SR), Y BLK C Z I D x m V N IPL + - / Description Implied addressing mode Immediate addressing mode Accumulator addressing mode Direct addressing mode Direct bit addressing mode Direct indexed X addressing mode Direct indexed Y addressing mode Direct indirect addressing mode Direct indexed X indirect addressing mode Direct indirect indexed Y addressing mode Direct indirect long addressing mode Direct indirect long indexed Y addressing mode Absolute addressing mode Absolute bit addressing mode Absolute indexed X addressing mode Absolute indexed Y addressing mode Absolute long addressing mode Absolute long indexed X addressing mode Absolute indirect addressing mode Absolute indirect long addressing mode Absolute indexed X indirect addressing mode Stack addressing mode Relative addressing mode Direct bit relative addressing mode Absolute bit relative addressing mode Stack pointer relative addressing mode Stack pointer relative indirect indexed Y addressing mode Block transfer addressing mode Carry flag Zero flag Interrupt disable flag Decimal operation mode flag Index register length selection flag Data length selection flag Overflow flag Negative flag Processor interrupt priority level Addition Subtraction Multiplication Division Logical AND Logical OR Symbol - ACC ACCH ACCL A AH AL B BH BL X XH XL Y YH YL S PC PCH PCL PG DT DPR DPRH DPRL PS PSH PSL PSb M(S) Mb ADG ADH ADL op n # i i1, i2 7733 Group User's Manual Description Exclusive OR Negation Movement to the arrow direction Accumulator Accumulator's upper 8 bits Accumulator's lower 8 bits Accumulator A Accumulator A's upper 8 bits Accumulator A's lower 8 bits Accumulator B Accumulator B's upper 8 bits Accumulator B's lower 8 bits Index register X Index register X's upper 8 bits Index register X's lower 8 bits Index register Y Index register Y's upper 8 bits Index register Y's lower 8 bits Stack pointer Program counter Program counter's upper 8 bits Program counter's lower 8 bits Program bank register Data bank register Direct page register Direct page register's upper 8 bits Direct page register's lower 8 bits Processor status register Processor status register's upper 8 bits Processor status register's lower 8 bits Processor status register's b-th bit Contents of memory at address indicated by stack pointer b-th memory location Value of 24-bit address's upper 8-bit (A23-A16) Value of 24-bit address's middle 8-bit (A15-A8) Value of 24-bit address's lower 8-bit (A7-A0) Operation code Number of cycle Number of byte Number of transfer byte or rotation Number of registers pushed or pulled 21-57 APPENDIX Appendix 7. Examples of handling unused pins Appendix 7. Examples of handling unused pins The following are examples of handling unused pins. These are, however, just examples. In actual use, make the necessary adaptations and properly evaluate performance according to the user's application. 1. In single-chip mode Table 1 Examples of handling unused pins in single-chip mode Pins Handling example P0-P8 Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Note 1). __ E Leave this pin open. XOUT (Note 2) AVcc Connect this pin to pin Vcc. AVss, V REF, BYTE Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 2: This is applied when an external clock is input to pin XIN. N When setting ports to input mode N When setting ports to output mode P0-P8 M37733MHBXXXFP M37733MHBXXXFP E XOUT P0-P8 Left open VCC AVcc AVss VREF BYTE Vss Fig. 9 Examples of handling unused pins in single-chip mode 21-58 7733 Group User's Manual E XOUT Left open Left open Vcc AVcc AVss VREF BYTE Vss APPENDIX Appendix 7. Examples of handling unused pins 2. In memory expansion mode Table 2 Examples of handling unused pins in memory expansion Pins Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Notes 1, 2, and 7). Leave this pin open. (Note 5) P4 2-P4 7, P5-P8 ____ BHE (Note 3) ALE (Note 4) _____ HLDA XOUT (Note 6) _____ ____ HOLD, RDY Leave this pin open. Connect these pins to pin Vcc via resistors after these pins set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. AVcc AVss, VREF Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched t voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: This is applied when "H" level is input to pin BYTE. 4: This is applied when "H" level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: this pin functions as an input port from reset until the processor mode is switched to the memory exp a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: This is applied when an external clock is input to pin XIN. 7: Set pin P4 2 / 1 as pin P4 2 . (Clock 1 output is disabled.) And then, for this pin, do the same handling as that for pins P4 3 to P4 7 and P5 to P8. N When setting ports to input mode P42-P47, P5-P8 P42-P47, P5-P8 M37733MHBXXXFP M37733MHBXXXFP BHE ALE Left open HLDA XOUT N When setting ports to output mode Left open Vcc HOLD RDY AVcc AVss VREF Left open BHE ALE Left open HLDA XOUT Left open Vcc HOLD RDY AVcc AVss VREF Vss Vss Fig. 10 Examples of handling unused pins in memory expansion oare ansion mode mode the output modemode by software. by software. Therefore, Therefore, 7733 Group User's Manual 21-59 APPENDIX Appendix 7. Examples of handling unused pins 3. In microprocessor mode Table 3 Examples of handling unused pins in microprocessor mode Pins Handling example P4 3-P4 7, P5-P8 Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Notes 1 and 2). ____ BHE (Note 3) Leave this pin open. (Note 5) ALE (Note 4) _____ HLDA , 1 XOUT (Note 6) Leave this pin open. _____ ____ HOLD, RDY Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) AVcc Connect this pin to pin Vcc. AVss, VREF Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: This is applied when "H" level is input to pin BYTE. 4: This is applied when "H" level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: this pin functions as an input port from reset until the processor mode is switched to the microprocessor mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: This is applied when an external clock is input to pin XIN. N When setting ports to input mode P43-P47, P5-P8 P43-P47, P5-P8 M37733MHBXXXFP M37733MHBXXXFP BHE ALE Left open HLDA 1 XOUT N When setting ports to output mode Left open Vcc HOLD RDY AVcc AVss VREF BHE ALE Left open HLDA 1 XOUT Left open Vcc HOLD RDY AVcc AVss VREF Vss Fig. 11 Examples of handling unused pins in microprocessor mode 21-60 Left open 7733 Group User's Manual Vss APPENDIX Appendix 8. Countermeasure examples against noise Appendix 8. Countermeasure examples against noise General countermeasure examples against noise are described below. Although the effect of these countermeasures depends on each system, refer to the following when a noise-related problem occurs. 1. Shortest wiring length The wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less possibility of noise insertion into the microcomputer. ______ (1) Wiring for pin RESET ______ Make the length of wiring connected to pin RESET as short as possible. In particular, connect a ______ capacitor between pin RESET and pin Vss with the shortest possible wiring (within 20 mm). Reason ______ If noise is input to pin RESET, the microcomputer restarts operation before the internal state of the microcomputer is completely initialized. This may cause a program runaway. M37733MHBXXXFP Noise Reset circuit RESET Vss Vss Not acceptable M37733MHBXXXFP Reset circuit Vss RESET VSS Acceptable ______ Fig. 12 Wiring for pin RESET 7733 Group User's Manual 21-61 APPENDIX Appendix 8. Countermeasure examples against noise (2) Wiring for clock I/O pins Make the length of wiring connected to clock I/O pins as short as possible. Make the length of wiring between the grounding lead of the capacitor, which is connected to the oscillator and pin Vss of the microcomputer, as short as possible (within 20 mm). Separate the Vss pattern only for oscillation from all other Vss patterns. (Refer to Figure 21.) Reason The microcomputer's operation synchronizes with a clock generated by the oscillation circuit. If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or a program runaway. Also, if the noise causes a potential difference between the Vss level of the microcomputer and the Vss level of an oscillator, the correct clock will not be input in the microcomputer. (3) Wiring for pin CNVss Connect pin CNVss to pin Vss with the shortest possible wiring. Reason The processor mode of the microcomputer is influenced by a potential at pin CNVss when pin CNV SS and pin V SS are connected. If the noise causes a potential difference between the two pins, the processor mode may become unstable. This may cause a malfunction or a program runaway. 21-62 Noise M37733MHBXXXFP M37733MHBXXXFP XIN XOUT Vss Not acceptable XIN XOUT Vss Acceptable Fig. 13 Wiring for clock I/O pins M37733MHBXXXFP M37733MHBXXXFP Noise CNVss CNVss Vss Vss Not acceptable Fig. 14 Wiring for pin CNVss 7733 Group User's Manual Acceptable APPENDIX Appendix 8. Countermeasure examples against noise (4) Wiring to pin CNVss [In single-chip and memory expansion modes] Connect pin CNVss to pin Vss of the microcomputer with the shortest possible wiring. If the above countermeasure cannot be taken, insert an approximate 5 k resistor between pins CNVss and Vss and, again, make the distance between the resistor and pin CNVss as short as possible. [In microprocessor mode] Connect pin CNVss to pin Vcc with the shortest possible wiring. Reason Pin CNVss is connected to the internal ROM in the low-impedance state. (Noise is easily to be fed to the pin in this condition.) If noise enters pin CNVss, incorrect instruction codes or data are fetched from the built-in PROM. This may cause a program runaway. Single-chip and Memory expansion modes Microprocessor mode M37733EHBXXXFP M37733EHBXXXFP VCC Shortest possible wiring Approx. 5 K CNVSS CNVSS VSS Shortest possible wiring Pin CNVss is connected to pin Vcc with the shortest possible wiring. Pin CNVss is connected to pin Vss with the shortest possible wiring. The above countermeasure is not necessary for pin BYTE. Fig. 15 Built-in PROM version: Wiring for pin CNVss 7733 Group User's Manual 21-63 APPENDIX Appendix 8. Countermeasure examples against noise 2. Connection of bypass capacitor between Vss line and Vcc line Connect an approximate 0.1 F bypass capacitor as follows: Connect a bypass capacitor between pin Vss and pin Vcc, at equal lengths. The wiring connecting the bypass capacitor between pin Vss and pin Vcc should be as short as possible. Use thicker wiring for the Vss and Vcc lines than for the other signal lines. Bypass capacitor Wiring pattern Vss Wiring pattern Vcc M37733MHBXXXFP Fig. 16 Bypass capacitor connection 21-64 7733 Group User's Manual APPENDIX Appendix 8. Countermeasure examples against noise 3. Wiring for analog input pins, analog power source pins, etc. (1) Processing analog input pins Connect a resistor to the analog signal line, which is connected to an analog input pin, in series. Additionally, connect the resistor to the microcomputer as close as possible. Connect a capacitor between pin AVss and the analog input pin, as close to pin AVss as possible. Reason A signal which is input to the analog input pin is usually an output signal from a sensor. The sensor, which detects changes in status, is installed far from the printed circuit board. Therefore, this long wiring between them becomes an antenna which picks up noise and feeds it into the microcomputer. If a capacitor between an analog input pin and pin AVss is grounded far away from pin AVss, noise on the GND line may enter the microcomputer through the capacitor. Noise (Note 2 j M37733MHBXXXFP Acceptable RI ANi Thermistor Acceptable Not acceptable CI AVss Reference values @ RI: Approximate 100 to 1000 CI: Approximate 100 pF to 1000 pF Notes 1: Design an external circuit for pin ANi so that charge/discharge is available within 1 cycle of AD. 2: This resistor and the thermistor are used to divide resistance. Fig. 17 Countermeasure example against noise for analog input pin using thermistor 7733 Group User's Manual 21-65 line. APPENDIX Appendix 8. Countermeasure examples against noise (2) Processing for analog power source pins, etc. Use independent power sources for pins Vcc, AVcc and VREF. Insert capacitors between pins AVcc and AVss, and between pins V REF and AVss, respectively. Reasons: Prevents noise from affecting the A-D converter on the Vcc M37733MHBXXXFP Reference values 0.47 F C1 C2 0.47 F AVcc VREF C1 C2 Note : Connect capacitors using the thickest, shortest wiring possible. AVss ANi (sensor, etc.) Fig. 18 Processing for analog power source pins, etc. 21-66 7733 Group User's Manual APPENDIX Appendix 8. Countermeasure examples against noise 4. Oscillator protection The oscillator, which generates the basic clock for the microcomputer operations, must be protected from the affect of other signals. (1) Distance oscillator from signal lines with large current flows Install the microcomputer, especially the oscillator, as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance. M37733MHBXXXFP Mutual inductance M XIN XOUT Vss Large current GND Fig. 19 Wiring for signal lines with large current flows Reason The microcomputer is used in systems which contain signal lines for controlling motors, LEDs, thermal heads, etc. Noise occurs due to mutual inductance when a large current flows through the signal lines. (2) Distance oscillator from signal lines with frequent potential level changes Install an oscillator and a connecting pattern away from signal lines in which potential levels change frequently. Do not cross these signal lines over clockrelated or noise-sensitive signal lines. Reason Signal lines with frequently changing potential levels may affect other signal lines at the rising or falling edge. In particular, if the lines cross over a clock-related signal line, clock waveforms may be deformed, which causes a microcomputer malfunction or a program runaway. M37733MHBXXXFP Do not cross. XIN XOUT Vss I/O pin for signal with frequently changing potential levels. Fig. 20 Wiring for signal lines with frequent potential level changes 7733 Group User's Manual 21-67 APPENDIX Appendix 8. Countermeasure examples against noise (3) Oscillator protection using Vss pattern Print a Vss pattern on the bottom (soldering side) of a double-sided printed circuit board, under the oscillator mount position. Connect the Vss pattern to pin Vss of the microcomputer with the shortest possible wiring, separating it from other Vss patterns. An example of Vss pattern on the underside of an oscillator M37733MHBXXXFP Mounted pattern example of an oscillator unit XIN XOUT Vss Separate Vss lines for oscillation and supply. Fig. 21 Vss pattern underneath mounted oscillator 21-68 7733 Group User's Manual APPENDIX Appendix 8. Countermeasure examples against noise 5. Setup for I/O ports Setup for I/O ports is follows: Data bus <Hardware> Connect a resistor of 100 or more to an I/O port in series. <Software> Read the data of an input port several times to confirm that input levels are equal. Periodically rewrite data to the output port's Pi register, as the data may reverse due to noise. Rewrite data to port Pi direction registers periodically. Noise Direction register Port latch Port Fig. 22 Setup for I/O ports 7733 Group User's Manual 21-69 APPENDIX Appendix 8. Countermeasure examples against noise 6. Reinforcement of the power source line For the Vss and Vcc lines, use thicker wiring than that of other signal lines. When using a multilayer printed circuit board, the Vss pattern and the Vcc pattern must each be one of the middle layers. The following is necessary for double-sided printed circuit boards: * On one side, the microcomputer is installed at the center, and the Vss line is looped or meshed around it. The vacant area is filled with the Vss line. * On the opposite side, the Vcc line is wired the same as the Vss line. * The power source lines of external devices which are connected by bus to the microcomputer must be connected to the microcomputer's power source lines with the shortest possible wiring. Reasons With external devices connected to the microcomputer, the levels of many of the signal lines (total external address buses: 24 bits) may change simultaneously, causing noise on the power source line. 21-70 7733 Group User's Manual APPENDIX Appendix 9. Q & A Appendix 9. Q & A Information which may be helpful in fully utilizing the 7733 Group is provided in Q & A format. In Q & A, as a rule, one question and its answer are summarized within one page. The upper box on each page is a question, and a box below the question is its answer. (If a question or an answer extends to two or more pages, there is a page number at the lower right corner.) At the upper right corner of each page, the main function related to the contents of description in that page is listed. 7733 Group User's Manual 21-71 APPENDIX Appendix 9. Q & A Interrupt Q If an interrupt request (b) occurs while an interrupt routin routine is not executed at all from when the execution of th execution of the INTACK sequence for the next interrupt (b) Sequence of execut ion RTI instruction ? Main routine Interrupt routine (a) INTACK sequence (b) Conditions: I = 0 by executing the RTI instruction Interrupt priority level of interrupt (b) is higher than IPL of main routine. Interrupt priority level detection time = 2 cycles of A An interrupt request is sampled by detecting a sampling puls the CPU's op-code fetch cycle. (1) If the next interrupt request (b) occurs before sampling pul of the RTI instruction is generated, sampling for this interrupt request is completed while the RTI instruction is executed. Therefore, the INTACK sequence for (b) is executed without executing the main routine. (Even one instruction is not executed.) Interrupt request (b) Sampling pulse RTI instruction Interrupt routine (a) INTACK sequence for (b) (1/2) 21-72 starts? e se interrupt which (a) is executed, is routine generated (a) is synchronously it is true completed that the until with main the 7733 Group User's Manual APPENDIX Appendix 9. Q & A Interrupt A (2) If the next interrupt request (b) occurs immediately after sampling pulse is generated, this interrupt request is sampled when sampling pulse for the next instruction is generated. Therefore, one instruction in the main routine is executed, and then the INTACK sequence for (b) is executed. Interrupt request (b) Sampling pulse RTI instruction Interrupt routine (a) One instruction is executed. Main routine INTACK sequence for (b) (2/2) 7733 Group User's Manual 21-73 APPENDIX Appendix 9. Q & A Interrupt Q Suppose that there is a routine where a certain interrupt request should not be accepted. (The other interrupt requests are acceptable.) Although when the interrupt priority level selection bits for the above interrupt are set to "0002," in other words, when this interrupt is set to be disabled, this interrupt request is actually accepted immediately after the change of the priority level. Why did this occur and what should I do about it? Interrupt request is accepted in this interval : CLB #07H, XXXIC ; The interrupt priority level selection bits are set to "0002" ; or the interrupt request bit is set to "0." LDA A,DATA ; The first instruction of a routine where a certain interrupt request should not be accepted : ; A As for the change of the interrupt priority level, when the following are met, the microcomputer may pretend to accept an interrupt request immediately after this interrupt is set to be disabled: * The next instruction (in the above example, it is the LDA instruction) is already stored into a instruction queue buffer for the BIU. * Conditions for accepting the instruction which should not be accepted are satisfied immediately before the next instruction in the instruction queue buffer is executed. When writing to the memory * I/O, the CPU transfers an address and data to the BIU. And then, the CPU executes the next instruction in the instruction queue buffer while the BIU is writing the data into the actual address. Interrupt priority level is determined at the start of each instruction. In the above case, the CPU executes the next instruction before the BIU completes the change of the interrupt priority level. Therefore, when the interrupt priority level is detected synchronously with the execution of the next instruction, the interrupt priority level before the change is detected and its interrupt request is accepted. Interrupt request is generated. Interrupt request is accepted. Sequence of execution Interrupt priority detection time CPU operation Previous instruction is executed. CLB instruction is executed. LDA instruction is executed. BIU operation (Instruction is prefetched.) Interrupt priority level selection bits are set. Change of interrupt priority levels is completed 21-74 7733 Group User's Manual (1/2) APPENDIX Appendix 9. Q & A Interrupt A To solve this problem, make sure that, by software, the execution of a routine where a certain interrupt request should not be accepted starts after the change of the interrupt level is completed. The following lists a sample program. [Sample program] After an instruction which writes value "000 2 " to the interrupt priority level selection bits, fill the instruction queue buffer with several NOP instructions and make the next instruction not to be executed until the writing is completed. : CLB #07H, XXXIC NOP NOP NOP LDA A,DATA ; The interrupt priority level selection bits are set to "000 2 ." ; ; ; ; The first instruction of a routine where a certain interrupt request should not be accepted (2/2) 7733 Group User's Manual 21-75 APPENDIX Appendix 9. Q & A Interrupt Q ____ (1) At what timing of clock 1 is an external interrupt (an input signal on the INT i pin) detected? ____ (2) Suppose that more than three external interrupt input pins ( INTi) are necessary, what should I do? A (1) If the edge sense or level____ sense is selected, an external interrupt request occurs when the level of an input signal on the INT i pin changes. This is independent of clock 1. At this time, if the edge sense is selected, the interrupt request bit is set to "1," also. (2) There are two methods: one is the method to use the external interrupt's level sense; the other one is the method to use the timer's event counter mode. Method to use the external interrupt's level sense As for hardware, input a logical sum of several interrupt signals (for example, `a', `b', and `c') ____ to the INTi pin and input each signal to the corresponding port. ____ As for software, check the ports' input levels in an INTi interrupt routine in order to detect a signal (one of signals `a,' `b,' and `c') which is input. M37733MHBXXXFP Port Port Port a b c INTi Note : The same process can be realized by using the key input interrupt function, also. 21-76 Method to use the timer's event counter mode As for hardware, input an interrupt signal to the TAiIN or TBiIN pin. As for software, set the timer's operating mode to the event counter mode and set value "0000 16 " to the timer. Furthermore, select a valid edge. The timer's interrupt request occurs when an interrupt signal (selected valid edge) is input. 7733 Group User's Manual APPENDIX Appendix 9. Q & A Serial I/O (UART mode) Q ____ If the CTS function is selected in UART (clock asynchronous serial I/O) mode, at what timing should ____ the CTS input's level be checked by the transmitter? A Checked near the middle of the stop bit (if two stop bits are selected, the second stop bit). Input level on CTSi pin is checked near this timing. Transmit data .............. D6 D7 n n SP n/2 .............. n/2 Input level on CTSi pin is checked near this timing. Transmit data .............. D6 D7 SP n n n SP n/2 .............. n/2 n: 1-bit length 7733 Group User's Manual 21-77 APPENDIX Appendix 9. Q & A Hold function Q ______ If "L" level is input to the HOLD pin, when is a bus actually opened? A _____ When interval 50 ns (max.) has passed since clock 1 is risen immediately after the HLDA pin's output becomes "L," a bus is opened. Clock 1 ....... HOLD HLDA Interval while bus is open tpxz(HOLD-PZ):Maximum of 50 ns 21-78 7733 Group User's Manual APPENDIX Appendix 9. Q & A Processor mode Q When the processor mode is switched, as described below, by setting the processor mode bits (bits 1 and 0 at address 5E 16) while a program is executed, is there any precaution on software? Single-chip mode A Microprocessor mode Memory expansion mode Microprocessor mode A Although when the processor mode bits are set in order to switch the processor mode, as described above, the mode is not switched until the write cycle for the processor mode bits is completed. (The processor mode is actually switched simultaneously with the write cycle's completion.) At this time, the program counter indicates the address which is next to the address (address XXXX 16) where the write instruction for the processor mode bits is stored. Also, access to the internal ROM area is disabled. Note that there is a possibility that less than four bytes of instructions are prefetched into instruction queue buffers. Therefore, the address which resides in the external ROM area and is accessed first after the mode is switched is one of addresses "XXXX16 + 1" to "XXXX16 + 4." Note also that instructions at addresses "XXXX 16 + 1" to "XXXX 16 + 3" in the internal ROM area may be executed. To solve this problem, do the following processes by software. [Process ] Program a write instruction for the processor mode bits and the following instructions (at least three bytes) to the same addresses of the internal ROM and external ROM areas. (See below.) Internal ROM area XXXX16 LD M ,B #00000010B, PM R NOP NOP NOP External R O M area XXXX16 At least three bytes LD M ,B #00000010B, PM R NOP NOP NOP [Process ] Transfer a write instruction for the processor mode bits to an internal RAM area and make the program branch to the address in order to execute the write instruction. And then, make the program branch to the program address in the external ROM area. (Contents of instruction queue buffers are initialized by a branch instruction.) 7733 Group User's Manual 21-79 APPENDIX Appendix 9. Q & A SFR Q Is there any SFR where a certain write instruction can not be used? A Use the STA and LDM instructions for setting the registers or the bits listed below. Do not use read-modify-write instructions (for example, CLB, SEB, INC, DEC, ASL, LSR, ROL, and ROR). UART0 baud rate register (address 31 16) UART1 baud rate register (address 39 16) UART2 baud rate register (address 65 16) UART0 transmission buffer register (addresses 3316 , 32 16 ) UART1 transmission buffer register (addresses 3B16 , 3A16 ) UART2 transmission buffer register (addresses 6716 , 66 16 ) Timer A4 two-phase pulse signal processing selection bit (bit 7 at address 44 16 ) Timer A3 two-phase pulse signal processing selection bit (bit 6 at address 44 16 ) Timer A2 two-phase pulse signal processing selection bit (bit 5 at address 44 16 ) When writing data to the oscillation circuit control register 1 (address 6F 16), be sure to follow the procedure shown below. * When initializing the clock prescaler Write data "80 16." (LDM instruction) Clock prescaler is reset. * When writing to bits 0 to 2 Write data "01010101 2." (LDM instruction) Write data "000012 ." (LDM instruction) (Note) Bits 0 to 2 are set. Note: In the case of the 7735 Group, write data "00000 2." When writing data to the memory allocation control register (address 6316 ), be sure to follow the procedure shown below. Write data "01010101 2." (LDM instruction) Write data "00000 2." (LDM instruction) Bits 0 to 2 are set. 21-80 Next instruction 7733 Group User's Manual Next instruction APPENDIX Appendix 9. Q & A Debug Q Is there any precaution when debugging? A Some functions of the 7733 Group cannot be evaluated by a debugger. For the operations listed below, use the built-in PROM version to make full evaluation. When debugging, be sure to read the user's manual supplied with the debugger. <<Operation examples that cannot be evaluated by a debugger>> Operation when the signal output disable selection bit (bit 6 at address 6C16 ) = "1" Operation when the stand-by state selection bit (bit 0 at address 6D16 ) = "1" Operations for reading from and writing to addresses 0216 to 0916 in the memory expansion or microprocessor mode 7733 Group User's Manual 21-81 APPENDIX Appendix 9. Q & A Memory Q Questions about the memory allocation selection function are described below: For what purpose is this function used? Is there any precaution on use of this function? A This function is used in order to secure an external memory area to bank 0 16 in the memory expansion mode. If there is an external device which is frequently accessed, this device's memory allocation in bank 0 16 is effective for accessing this device, as well as internal RAM and SFR, with using DPR and DT efficiently. In the M37733MHBXXXFP, all of bank 0 16 is specified as an area for internal resources. Therefore, this function is used to secure an external memory area in bank 0 16 . Note that the memory allocation selection bits are valid in the single-chip mode, also. In the singlechip mode, the memory allocation selection function is valid only for reduction of usable ROM area. Therefore, in the single-chip mode, we recommend to set these bits to "000 2" (the state immediately after reset) and not to change them. Note the following: * When changing the memory allocation selection bits, follow the procedure in Figure 2.4.1. * When changing the memory allocation selection bits, make sure that the change is done within an area which is in the internal ROM area both of after and before the change, for example addresses 00C000 16 to 00FFFF16 . * We recommend to set the memory allocation selection bits only when a processor mode is set after reset and not to change them after this setting. * When programming to the EPROM and one time PROM versions, program to addresses listed in Table 19.1.3. * As for debugging for an area in bank 0 16 or 1 16 which is specified as an external area, some considerations may be necessary. For details concerning the development support tools, refer to the respective operation manuals. 21-82 7733 Group User's Manual PART 2 7735 Group CHAPTER 1 OVERVIEW CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) CHAPTER 3 PROGRAMMABLE I/O PORTS CHAPTER 4 INTERRUPTS CHAPTER 5 KEY INPUT INTERRUPT FUNCTION CHAPTER 6 TIMER A CHAPTER 7 TIMER B CHAPTER 8 SERIAL I/O CHAPTER 9 A-D CONVERTER CHAPTER 10 WATCHDOG TIMER CHAPTER 11 STOP AND WAIT MODES CHAPTER 12 CONNECTING EXTERNAL DEVICES CHAPTER 13 RESET CHAPTER 14 CLOCK GENERATING CIRCUIT CHAPTER 15 ELECTRICAL CHARACTERISTICS CHAPTER 16 STANDARD CHARACTERISTICS CHAPTER 17 APPLICATIONS CHAPTER 18 LOW VOLTAGE VERSION CHAPTER 19 BUILT-IN PROM VERSION CHAPTER 20 EXTERNAL ROM VERSION APPENDIX PART 2 7735 Group The differences between the 7735 Group and the 7733 Group are mainly described below. For the 7733 Group, refer to part "1. 7733 Group." The 7735 Group differs from the 7733 Group in the following: * External bus mode in the memory expansion mode and the microprocessor mode * External memory area (The 7735 Group has the maximum of 1-Mbyte external memory area.) * Setting conditions for bit 3 of the oscillation circuit control register 1 (In the 7735 Group, this bit must be "0." Note that, in the one time PROM version and the EPROM version, this bit is automatically set to "1" after reset. Therefore, be sure to clear this bit to "0.") __ ____ * Functions of pin E/ RDE 2 7735 Group User's Manual CHAPTER 1 OVERVIEW 1.1 1.2 1.3 1.4 Performance overview Pin configuration Pin description Block diagram OVERVIEW 1.1 Performance overview Concerning chapter "1. OVERVIEW," the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter: * "1.1 Performance overview" * "1.2 Pin configuration" * "1.3 Pin description" The following section of the 7735 Group is the same as that of the 7733 Group. Therefore, for this section, refer to part 1: * "1.4 Block diagram" (page 1-11 in part 1) 1.1 Performance overview Concerning section "1.1 Performance overview," the 7735 Group differs from the 7733 Group in the following: * Description of the memory expansion in Table 1.1.1 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "1.1 Performance overview" (page 1-3 in part 1) Table 1.1.1 M37735MHBXXXFP's performance overview Items Memory expansion 1-2 Performance Possible (Maximum of 1 Mbytes) 7735 Group User's Manual OVERVIEW 1.2 Pin configuration 1.2 Pin configuration P71/AN1 P72/AN2/CTS2 P73/AN3/CLK2 P74/AN4/RXD2 P75/AN5/ADTRG/TXD2 P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RXD0/CLKS0 P83/TXD0 Figure 1.2.1 shows the M37735MHBXXXFP pin configuration. Note: For the low voltage version, refer to chapter "18. LOW VOLTAGE VERSION." 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 64 2 63 3 62 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 M37735MHBXXXFP P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 P42/ 1 P41/RDY 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 23 42 24 41 P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 P00/CS0 P01/CS1 P02/CS2 P03/CS3 P04/CS4 P05/RSMP P06/A16 P07/A17 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A0/D0 P21/A1/D1 P22/A2/D2 P23/A3/D3 P40/HOLD BYTE CNVSS RESET XIN XOUT E/RDE VSS P33/HLDA P32/ALE P31/WEH P30/WEL P27/A7/D7 P26/A6/D6 P25/A5/D5 P24/A4/D4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Outline 80P6N-A Fig. 1.2.1 M37735MHBXXXFP pin configuration (Top view) 7735 Group User's Manual 1-3 OVERVIEW 1.3 Pin description 1.3 Pin description Concerning section "1.3___ Pin description," the 7735 Group differs from the 7733 Group in the following: * "Description of pin E in Table 1.3.1" * "Description of pins P0 0-P0 7, P2 0 -P27 and P3 0-P3 3 in Table 1.3.2" * "1.3.1 Examples of handling unused pins" The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "1.3 Pin description" (page 1-5 in part 1) Table 1.3.1 Pin description (1) Pin _ E 1-4 Name Internal enable output Input/Output Functions Output [Single-chip Mode] _ _ This pin outputs internal enable signal E . When E 's level is "L," the microcomputer reads data and instruction codes or writes data. Also, output of internal enable _ signal E can be stopped by software. [Memory Expansion Mode] [Microprocessor Mode] ________ This pin outputs read enable signal RDE. This signal's level is "L" in the data read period of the read cycle. 7735 Group User's Manual OVERVIEW 1.3 Pin description Table 1.3.2 Pin description (2) Pin Name P00-P0 7 I/O port P0 _______ Input/Output Functions I/O [Single-chip Mode] Same as the 7733 Group. [Memory Expansion Mode] [Microprocessor Mode] _______ _______ ____________ These pins respectively output signals CS0-CS4, RSMP, and address's high-order 2 bits (A16 and A 17). _______ _______ Signal CS0- CS4 These signals are the chip select signals. When the microcomputer accesses a certain area, the corresponding pin outputs "L" level. (Refer to Table 2.5.3.) ____________ Signal RSMP This signal is the ready sampling signal and is used ________ to generate signal RDY for accessing external memory area. [Single-chip Mode] Same as the 7733 Group. [Memory Expansion Mode] [Microprocessor Mode] Input/Output of data (D0-D 7) and output of address's low-order 8 bits (A 0 -A 7 ) are performed with the time sharing method. [Single-chip Mode] Same as the 7733 Group. [Memory Expansion Mode] [Microprocessor Mode] ________ _________ These pins respectively output signals WEL, WEH , ALE, _____ and HLDA . ________ _________ Signal WEL, WEH ____ Signal WEL is the write enable low signal. ____ Signal WEH is the write enable high signal. These signals' levels are "L" in the data write period of the write cycle. The operations of these signals depend on the level of pin BYTE. (Refer to Table 12.1.1.) Signal ALE This signal is used to separate the multiplexed signal which consists of an address and data to the address and the data. _____ Signal HLDA This signal informs the external whether the microcomputer enters the Hold state or not. __________ In Hold state, pin HLDA outputs "L" level. _______ CS 0-CS 4, Output _____ RSMP, A16, A17 P20-P2 7 I/O port P2 I/O I/O port P3 I/O A0/D0- A7/D7 P30-P3 3 ________ WEL, ________ WEH, ALE, _____ HLDA Output 7735 Group User's Manual 1-5 OVERVIEW 1.3 Pin description 1.3.1 Examples of handling unused pins The following are examples of handling unused pins. These are, however, just examples. In actual use, make the necessary adaptations and properly evaluate performance according to the user's system. (1) In single-chip mode Table 1.3.4 Examples of handling unused pins in single-chip mode Pins E Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Note 1). Leave this pin open. XOUT (Note 2) AVcc AVss, V REF, BYTE Connect this pin to pin Vcc. Connect these pins to pin Vss. P0-P8 _ Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until the they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these ports function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 2: This is applied when an external clock is input to pin XIN. When setting ports to output mode When setting ports to input mode P0-P8 M37735MHBXXXFP M37735MHBXXXFP E XOUT P0-P8 Left open Vcc AVcc AVss VREF BYTE Vss Fig. 1.3.1 Examples of handling unused pins in single-chip mode 1-6 7735 Group User's Manual E XOUT Left open Left open Vcc AVcc AVss VREF BYTE Vss OVERVIEW 1.3 Pin description (2) In memory expansion mode Table 1.3.5 Examples of handling unused pins in memory expansion mode Pins Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). Leave these pins open. (Note 3) P4 2-P4 7, P5-P8 (Note 5) _________ ________ ________ WEH , WEL, RDE , _____ _______ _______ __________ HLDA, CS0- CS4, RSMP X OUT (Note 4) _____ ____ HOLD , RDY Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. AVcc AVss, V REF Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory expansion mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 4: This is applied when an external clock is input to pin XIN . 5: Set pin P4 2 / 1 as pin P4 2 . (Clock 1 output is disabled.) And then, for this pin, do the same handling as that for pins P4 3 to P4 7 and P5 to P8. When setting ports to input mode When setting ports to output mode P42-P47, P5-P8 XOUT CS0-CS4 M37735MHBXXXFP M37735MHBXXXFP WEH WEL RDE HLDA RSMP P42-P47, P5-P8 Left open Left open Vcc HOLD RDY AVcc AVss VREF WEH WEL RDE HLDA RSMP Left open Left open XOUT CS0-CS4 Left open Vcc HOLD RDY AVcc AVss VREF Vss Vss Fig. 1.3.2 Examples of handling unused pins in memory expansion mode 7735 Group User's Manual 1-7 OVERVIEW 1.3 Pin description (3) In microprocessor mode Table 1.3.6 Examples of handling unused pins in microprocessor mode Pins Handling example P4 3-P4 7, P5-P8 Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). _________ ________ ________ WEH , WEL, RDE Leave these pins open. (Note 3) _____ _______ _______ ___________ HLDA , 1, CS 0-CS 4, RSMP XOUT (Note 4) Leave this pin open. _____ ____ HOLD, RDY Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) AV CC Connect this pin to pin Vcc. AVSS , VREF Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the microprocessor mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. 4: This is applied when an external clock is input to pin XIN. When setting ports to output mode When setting ports to input mode P43-P47, P5-P8 M37735MHBXXXFP M37735MHBXXXFP WEH WEL RDE HLDA P43-P47, P5-P8 Left open 1 RSMP XOUT CS0-CS4 Left open Vcc HOLD RDY AVcc WEH WEL RDE HLDA Left open 1 RSMP Left open XOUT CS0-CS4 AVss VREF Vcc HOLD RDY AVcc AVss VREF Vss Fig. 1.3.3 Examples of handling unused pins in microprocessor mode 1-8 Left open 7735 Group User's Manual Vss CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) 2.1 2.2 2.3 2.4 2.5 Central processing unit Bus interface unit Accessible area Memory allocation Processor modes CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit Concerning chapter "2. CENTRAL PROCESSING UNIT (CPU)," the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter: * "2.2 Bus interface unit" * "2.3 Accessible area" * "2.5 Processor modes" The following sections of the 7735 Group are the same as those of the 7733 Group. Therefore, for these section, refer to part 1: * "2.1 Central processing unit" (page 2-2 in part 1) * "2.4 Memory allocation" (page 2-18 in part 1) 2.2 Bus interface unit Concerning section "2.2 Bus interface unit," the 7735 Group differs from the 7733 Group in the following. * External buses in Figure 2.2.1 * Signal names in Figure 2.2.3 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "2.2 Bus interface unit" (page 2-10 in part 1) 2-2 7735 Group User's Manual (BIU) (CPU) 7735 Group User's Manual Internal control signals Internal bus A17 to A0 Internal bus D7 to D0 Internal bus D15 to D8 Internal bus Bus conversion circuit Internal peripheral devices (SFR) Internal memory Control signals A7/D7 to A0/D0 A15/D15 to A8/D8 A17 and A16 External bus Notes 1: CPU bus, internal bus, and external bus are independent of each other. 2: For details about signals on the external buses, refer to chapter "12. CONNECTING EXTERNAL DEVICES." SFR : Special Function Register Bus interface unit Central processing unit CPU bus M37735MHBXXXFP External devices CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit Fig. 2.2.1 Buses and bus interface unit (BIU) 2-3 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (a) RDE Internal address bus (A0 to A17) Address Internal data bus (D0 to D7) Data (Even address) Internal data bus (D8 to D15) Data (Odd address) (b) RDE Internal address bus (A0 to A17) Address (Odd address) Internal data bus (D0 to D7) Invalid data Data (Even address) Internal data bus (D8 to D15) Data (Odd address) Invalid data Fig. 2.2.3 Basic operating waveforms of bus interface unit (BIU) 2-4 Address (Even address) 7735 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.3 Accessible area 2.3 Accessible area Concerning section "2.3 Accessible area," the 7735 Group differs from the 7733 Group in the following: * Accessible area which is allocated to addresses 016 to 0FFFFF 16 (Maximum of 1 Mbytes) * Figure 2.3.1 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "2.3 Accessible area" (page 2-16 in part 1) *SFR : Special Function Register 00000016 SFR area 00007F16 00008016 Internal RAM area 000FFF16 Bank 016 00100016 00FFFF16 Internal ROM area 01000016 Bank 116 01FFFF16 02000016 FE000016 Bank FE16 FF000016 Bank FF16 represents the memory allocation of internal areas. indicates that nothing is allocated. FFFFFF16 Notes 1: Banks 1016 to FF16 cannot be accessed. 2: Memory allocation of internal area in bank 016 depends on the microcomputer's type and settings of the memory allocation selection bits. The above diagram shows the M37735MHBXXXFP's accessible area immediately after reset. For the other microcomputers of the 7735 Group, refer to "Appendix 1. Memory allocation of 7735 Group." For settings of the memory allocation selection bits, refer to section "2.4 Memory allocation." Fig. 2.3.1 M37735MHBXXXFP's accessible area 7735 Group User's Manual 2-5 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes 2.5 Processor modes Concerning section "2.5 Processor modes," the 7735 Group differs from that of the 7733 Group in the following: * "Fig. 2.5.1 Memory map in each processor mode" * "Fig. 2.5.2 Pin configuration in each processor mode (Top view)" * "Table 2.5.1 Relationship between processor modes and functions of P0_______ to P4" _______ * "2.5.4 Relationship between access addresses and chip select signals (CS0- CS4) (This section is added in part 2.) The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "2.5 Processor modes" (page 2-24 in part 1) Single-chip mode Memory expansion mode SFR area SFR area SFR area Internal RAM area Internal RAM area Internal RAM area Internal ROM area Internal ROM area Microprocessor mode 00000016 00008016 000FFF16 00100016 01FFFF16 02000016 0FFFFF16 10000016 (Note 4) (Note 4) FFFFFF16 Notes 1: represents external area. By accessing this area, an external device connected to the M37735MHBXXXFP can be accessed . 2: This applies when the contents of memory allocation selection bits (bits 2 to 0 at address 6316) = "0002." 3: For the other microcomputers of the 7735 Group, refer to section "Appendix 1. Memory allocation of 7735 Group." 4: Banks 1016 to FF16 cannot be accessed. Fig. 2.5.1 Memory map in each processor mode (M37735MHBXXXFP) 2-6 7735 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 <Single-chip mode> 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG/TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 65 40 66 39 67 38 68 37 69 36 70 35 71 34 M37735MHBXXXFP 72 73 33 32 74 31 75 30 76 29 77 28 78 27 79 26 80 25 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 P42/ 1 P41 1 P24 P25 P26 P27 P30 P31 P32 P33 VSS E XOUT XIN RESET CNVSS 1 BYTE 1 P40 1 Connect this pin to Vss in the single-chip mode. : These pins' functions in the single-chip mode differ from those in the memory expansion or microprocessor mode. P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 CS0 CS1 CS2 CS3 CS4 RSMP A16 A17 A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 A0/D0 A1/D1 A2/D2 A3/D3 <Memory expansion and Microprocessor modes> 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 39 67 38 68 37 69 36 70 35 71 34 33 M37735MHBXXXFP 72 73 32 74 31 75 30 76 29 77 28 78 27 79 26 80 25 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 2 P42/ 1 1 A4/D4 A5/D5 A6/D6 A7/D7 WEL WEH ALE HLDA VSS RDE XOUT XIN RESET CNVSS BYTE HOLD RDY P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG/TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 2 1 in the microprocessor mode : These pins' functions in the single-chip mode differ from those in the memory expansion or microprocessor mode. Fig. 2.5.2 Pin configuration in each processor mode (Top view) 7735 Group User's Manual 2-7 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes Table 2.5.1 Relationship between processor modes and functions of P0 to P4 Processor mode Pin name Memory expansion and Microprocessor modes Single-chip mode P00 to P04 P P0 P: Functions as a programmable I/O port. CS0 to CS4 P05 RSMP P06 and P07 A16, A17 (Note 1) When external data bus is 16 bits wide (BYTE = "L") P P1 A8 to A15 P: Functions as a programmable I/O port. D(odd) D(odd): Data at odd address When external data bus is 8 bits wide (BYTE = "H") A8 to A15 When external data bus is 16 bits wide (BYTE = "L") A0 to A7 P P2 P: Functions as a programmable I/O port. D(even) D(even): Data at even address When external data bus is 8 bits wide (BYTE = "H") A0 to A7 D D: Data When external data bus is 16 bits wide (BYTE = "L") P P: Functions as a programmable I/O port. P30 WEL (Note 2) P31 WEH (Note 2) ALE P32 P33 P3 HLDA When external data bus is 8 bits wide (BYTE = "H") P30 P31 WEL ("H" level output) P32 ALE P33 P P: Functions as a programmable I/O port (Note 3). P4 HLDA P40 HOLD P41 RDY P42 (Note 2) (Note 4) 1 P43 to P47 P P: Functions as a programmable I/O port. E/R D E E (Note 2) RDE (Note 2) Notes 1: When an internal area is accessed, signals CS0 to CS4 are not output. (The output level is fixed to "H.") 2: These signals are affected by the signal output disable selection bit (bit 6 at address 6C16). (Refer to chapter "12. CONNECTING EXTERNAL DEVICES." ) 3: Pin P42 can also function as a clock 1 output pin. (Refer to chapter "12.3:CONNECTING EXTERNAL DEVICES.") 4: In the memory expansion mode, this pin functions as a programmable I/O port. Furthermore, it can be switched to be a clock 1 output pin when selected by software. In the microprocessor mode, this pin is affected by the signal output disable selection bit (bit 6 at address 6C16). (Refer to chapter"12. CONNECTING EXTERNAL DEVICES.") 2-8 7735 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes _______ _______ 2.5.4 Relationship between access addresses and chip select signals CS 0 to CS_______ 4 _______ Table 2.5.3 lists the relationship between access addresses and chip select signals CS0 to CS4. Table 2.5.4 lists the relationship between the memory allocation selection bits and addresses for chip _______ _______ select signals CS0, CS 1 in the memory expansion mode. _______ _______ Table 2.5.3 Relationship between access addresses and chip select signals CS0 to CS4 Chip select signal Access addresses Memory expansion mode Microprocessor mode Area The former half of bank 0016 except for internal memory area _______ CS 0 (Note) 00 100016 to 00 7FFF16 *The latter half of bank 00 16 except for internal memory area *Banks 01 16 to 03 16 _______ CS 1 _______ 02 000016 (Note) to 03 FFFF16 to 03 FFFF16 04 000016 04 000016 Banks 04 16 to 0716 CS 2 _______ to to 07 FFFF16 08 000016 07 FFFF16 to 0B FFFF16 to 0B FFFF16 0C 0000 16 0C 0000 16 Banks 08 16 to 0B 16 CS 3 _______ Banks 0C 16 to 0F 16 CS 4 00 800016 08 000016 to to 0F FFFF16 0F FFFF16 Note: This applies when each of bits 1 and 0 of the memory allocation control register (address 6316) = "0." For details, refer to Table 2.5.4. Table 2.5.4 Relationship between memory allocation selection bits and addresses for chip select _______ _______ signals CS0, CS1 in memory expansion mode Memory allocation selection bits b2 b1 b0 0 0 0 0 0 1 1 1 0 Access addresses Internal ROM area 001000 16 to 01FFFF16 (120 Kbytes) _______ CS0 CS 1 020000 16 to 03FFFF16 (124 Kbytes) 002000 16 to 01FFFF16 ______ 001000 16 to 001FFF 16 020000 16 to 03FFFF16 008000 16 to 01FFFF16 001000 16 to 007FFF 16 020000 16 to 03FFFF16 (96 Kbytes) 008000 16 to 00FFFF16 001000 16 to 007FFF 16 010000 16 to 03FFFF16 (32 Kbytes) Memory allocation selection bits : Bits 0 to 2 of the memory allocation control register (address 6316 ) 1 1 1 7735 Group User's Manual 2-9 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes MEMO 2-10 7735 Group User's Manual CHAPTER 3 PROGRAMMABLE I/O PORTS 3.1 3.2 3.3 3.4 Programmable I/O ports Port peripheral circuits Pull-up function Internal peripheral devices' I/O functions (Ports P42 and P5 to P8) PROGRAMMABLE I/O PORTS 3.2 Port peripheral circuits Concerning chapter "3. PROGRAMMABLE I/O PORTS," the 7735 Group differs from the 7733 Group in the following section. Therefore, only the difference is described in this chapter: * 3.2 Port peripheral circuits The following sections are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1: * "3.1 Programmable I/O ports" (page 3-2 in part 1) * "3.3 Pull-up function" (page 3-8 in part 1) * "3.4 Internal peripheral devices' I/O functions (Ports P42 and P5 to P8)" (page 3-10 in part 1) 3.2 Port peripheral circuits Concerning section "3.2 Port peripheral circuits," the 7735 Group differs from the 7733 Group in the following: _ ____ * Pin E / RDE in Figure 3.2.2 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "3.2 Port peripheral circuits" (page 3-6 in part 1) * E / RDE Hold acknowledge Fig. 3.2.2 Port peripheral circuits (2) 3-2 7735 Group User's Manual CHAPTER 4 INTERRUPTS 4.1 4.2 4.3 4.4 4.5 Overview Interrupt sources Interrupt control Interrupt priority level Interrupt priority level detection circuit 4.6 Interrupt priority level detection time 4.7 How interrupts are processed (from acceptance of interrupt request till execution of interrupt routine) 4.8 Return from interrupt routine 4.9 Multiple interrupts ____ 4.10 External interrupts ( INTi interrupt) 4.11 Precautions for interrupts INTERRUPTS Interrupts of the 7735 Group are the same as those of the 7733 Group. Therefore, for interrupts, refer to the corresponding sections in part 1: * "4.1 Overview (page 4-2 in part 1) * "4.2 Interrupt sources (page 4-4 in part 1) * "4.3 Interrupt control (page 4-6 in part 1) * "4.4 Interrupt priority level (page 4-10 in part 1) * "4.5 Interrupt priority level detection circuit (page 4-11 in part 1) * "4.6 Interrupt priority level detection time (page 4-13 in part 1) * "4.7 How interrupts are processed (from acceptance of interrupt request till execution of interrupt routine) (page 4-14 in part 1) * "4.8 Return from interrupt routine (page 4-17 in part 1) * "4.9 Multiple interrupts (page 4-17 in part 1) ____ * "4.10 External interrupts (INTi interrupt) (page 4-19 in part 1) * "4.11 Precautions for interrupts (page 4-23 in part 1) 4-2 7735 Group User's Manual CHAPTER 5 KEY INPUT INTERRUPT FUNCTION 5.1 Overview 5.2 Block description 5.3 Initial setting example for related registers KEY INPUT INTERRUPT FUNCTION The key input interrupt function of the 7735 Group is the same as that of the 7733 Group. Therefore, the key input interrupt function, refer to the corresponding sections in part 1: * "5.1 Overview (page 5-2 in part 1) * "5.2 Block description (page 5-3 in part 1) * "5.3 Initial setting example for related registers (page 5-7 in part 1) 5-2 7735 Group User's Manual CHAPTER 6 TIMER A 6.1 6.2 6.3 6.4 6.5 6.6 Overview Block description Timer mode Event counter mode One-shot pulse mode Pulse width modulation (PWM) mode TIMER A Timer A of the 7735 Group is the same as that of the 7733 Group. Therefore, for timer A, refer to the corresponding sections in part 1: * "6.1 Overview" (page 6-2 in part 1) * "6.2 Block description" (page 6-3 in part 1) * "6.3 Timer mode" (page 6-9 in part 1) * "6.4 Event counter mode" (page 6-19 in part 1) * "6.5 One-shot pulse mode" (page 6-32 in part 1) * "6.6 Pulse width modulation (PWM) mode" (page 6-41 in part 1) 6-2 7735 GROUP USER'S MANUAL CHAPTER 7 TIMER B 7.1 7.2 7.3 7.4 7.5 Overview Block description Timer mode Event counter mode Pulse period/Pulse width measurement mode 7.6 Clock timer TIMER B Timer B of the 7735 Group is the same as that of the 7733 Group. Therefore, for timer B, refer to the corresponding sections in part 1: * "7.1 Overview" (page 7-2 in part 1) * "7.2 Block description" (page 7-3 in part 1) * "7.3 Timer mode" (page 7-10 in part 1) * "7.4 Event counter mode" (page 7-17 in part 1) * "7.5 Pulse period/Pulse width measurement mode" (page 7-25 in part 1) * "7.6 Clock timer" (page 7-34 in part 1) 7-2 7735 GROUP USER'S MANUAL CHAPTER 8 SERIAL I/O 8.1 Overview 8.2 Block description 8.3 Clock synchronous serial I/O mode 8.4 Clock asynchronous serial I/O (UART) mode SERIAL I/O The serial I/O of the 7735 Group is the same as that of the 7733 Group. Therefore, for serial I/O, refer to the corresponding sections in part 1: * "8.1 Overview" (page 8-2 in part 1) * "8.2 Block description" (page 8-4 in part 1) * "8.3 Clock synchronous serial I/O mode" (page 8-21 in part 1) * "8.4 Clock asynchronous serial I/O (UART) mode" (page 8-44 in part 1) 8-2 7735 Group User's Manual CHAPTER 9 A-D CONVERTER 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Overview Block description A-D conversion method Absolute accuracy and Differential non-linearity error One-shot mode Repeat mode Single sweep mode Repeat sweep mode Precautions for A-D converter A-D CONVERTER The A-D converter of the 7735 Group is the same as that of the 7733 Group. Therefore, for the A-D converter, refer to the corresponding sections in part 1: * "9.1 Overview" (page 9-2 in part 1) * "9.2 Block description" (page 9-3 in part 1) * "9.3 A-D conversion method" (page 9-11 in part 1) * "9.4 Absolute accuracy and Differential non-linearity error" (page 9-14 in part 1) * "9.5 One-shot mode" (page 9-17 in part 1) * "9.6 Repeat mode" (page 9-20 in part 1) * "9.7 Single sweep mode" (page 9-23 in part 1) * "9.8 Repeat sweep mode" (page 9-27 in part 1) * "9.9 Precautions for A-D converter" (page 9-31 in part 1) 9-2 7735 Group User's Manual CHAPTER 10 WATCHDOG TIMER 10.1 Block description 10.2 Operation description 10.3 Precautions for watchdog timer WATCHDOG TIMER 10.2 Operation description Concerning chapter "10. WATCHDOG TIMER," the 7735 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter: * "10.2 Operation description" The following sections are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1: * "10.1 Block description" (page 10-2 in part 1) * "10.3 Precautions for watchdog timer" (page 10-10 in part 1) 10.2 Operation description Concerning section "10.2 Operation description," the 7735 Group differs from the 7733 Group in the following: * Figures 10.2.2 and 10.2.3 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "10.2 Operation description" (page 10-5 in part 1) 10-2 7735 Group User's Manual WATCHDOG TIMER 10.2 Operation description In the M37735MHBXXXFP, set bit 3 of the oscillation circuit control register 1 to "0." b7 b6 b5 A b4 b3 0 0 b2 b1 b0 AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA Oscillation circuit control register 1 (address 6F16) Bit Bit name Functions At reset RW 0 RW 0 RW 0 RW RW 0 Main clock division selection bit 0: Main clock is divided by 2. (Note 1) 1: Main clock is not divided by 2. 1 Main clock external input selection bit 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when (Note 1) terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. 2 Sub clock external input selection bit 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT. (Note 1) Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. 3 Must be fixed to "0" in the mask ROM and external ROM versions (Note 1). 0 Must be fixed to "0" in the one time PROM and EPROM versions (Notes 1 and 2). 1 4 Must be fixed to "0" (Note 3). 0 RW 5 Not implemented. Undefined -- 6 Not implemented. Undefined -- 7 Clock prescaler reset bit 0 WO (Note 4) By writing "1" to this bit, clock prescaler is initialized. Notes 1: When writing to this register, follow the procedure shown below. 2: Because this bit is "1" at reset, clear this bit to "0" with the initial setting program after reset. 3: The case where data "010101012" is written with the procedure shown below is not included. 4: For the 7733 Group, refer to Figure 14.3.3 in part 1. 5: represents that bits 3 to 7 are not used for the watchdog timer. Fig. 10.2.2 Structure of oscillation circuit control register 1 * When writing to bits 0 to 3 Write data "010101012." (LDM instruction) Next instruction Write data "00000XXX2." (LDM instruction) (b3 in Figure 10.2.2) (b2 to b0 in Figure 10.2.2) Fig. 10.2.3 Procedure for writing data to oscillation circuit control register 1 7735 Group User's Manual 10-3 WATCHDOG TIMER 10.2 Operation description MEMO 10-4 7735 Group User's Manual CHAPTER 11 STOP AND WAIT MODES 11.1 11.2 11.3 11.4 Overview Clock generating circuit Stop mode Wait mode STOP AND WAIT MODES 11.2 Clock generating circuit Concerning chapter "11. STOP AND WAIT MODES," the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter: * "11.2 Clock generating circuit" * "11.3 Stop mode" * "11.4 Wait mode" The following section of the 7735 Group is the same as that of the 7733 Group. Therefore, for this section, refer to part 1: * "11.1 Overview" (page 11-2 in part 1) 11.2 Clock generating circuit Concerning section "11.2 Clock generating circuit," the 7735 Group differs from the 7733 Group in the following: * Figures 11.2.3 and 11.2.4 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "11.2 Clock generating circuit" (page 11-3 in part 1) In the M37735MHBXXXFP, be sure to set bit 3 of the oscillation circuit control register 1 to "0." b7 b6 b5 b4 b3 0 0 b2 b1 b0 Oscillation circuit control register 1 (address 6F 16) Bit Bit name Functions At reset RW 0 Main clock division selection bit 0: Main clock is divided by 2. (Note 1) 1: Main clock is not divided by 2. 0 RW 1 Main clock external input selection bit 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when (Note 1) terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. 0 RW 2 Sub clock external input selection bit 0: Sub-clock oscillation circuit is operating by itself. Pin P7 6 functions as pin X COUT . (Note 1) Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. 0 RW 3 Must be fixed to "0" in the mask ROM and external ROM versions (Note 1). 0 RW Must be fixed to "0" in the one time PROM and EPROM versions (Notes 1 and 2). 1 4 Must be fixed to "0" (Note 3). 0 RW 5 Not implemented. Undefined -- 6 Not implemented. Undefined -- 7 Clock prescaler reset bit 0 WO (Note 4) By writing "1" to this bit, clock prescaler is initialized. Notes 1: When writing to this register, follow the procedure shown in Figure 11.2.4. 2: Because this bit is "1" at reset, clear this bit to "0" with the initial setting program after reset. 3: The case where data "01010101 2" is written with the procedure shown in Figure 11.2.4. is not included. 4: For the 7733 Group, refer to Figure 11.2.3 in part 1. 5: represents that bits 3 to 7 are not used for the stop and wait modes. Fig. 11.2.3 Structure of oscillation circuit control register 1 11-2 7735 Group User's Manual STOP AND WAIT MODES 11.3 Stop mode * When writing to bits 0 to 3 Write data "01010101 2." (LDM instruction) Next instruction Write data "00001XXX 2." (LDM instruction) (b3 in Figure 11.2.3) (b2 to b0 in Figure 11.2.3) Fig. 11.2.4 Procedure for writing data to oscillation circuit control register 1 11.3 Stop mode Concerning section "11.3 Stop mode," the 7735 Group differs from the 7733 Group in the following: * Table 11.3.2 and Figure 11.3.1 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "11.3 Stop mode" (page 11-6 in part 1) 7735 Group User's Manual 11-3 STOP AND WAIT MODES 11.3 Stop mode Table 11.3.2 Pin state in stop mode Pins __ E State Single-chip mode Memory expansion Microprocessor mode mode When the standby state When the standby state selection bit1 = "0" selection bit1 = "1" When the signal output Same as in the micro- "H" level is output. When the signal output disable selection bit = disable selection bit = processor mode "0," "H" level is output. "0," "H" level is output When the signal output When the signal output disable selection bit = disable selection bit = "1," "L" level is output. "1," "L" level is output. ____ Output levels can be set. (Refer to section "11.3.1 Output levels of external bus and bus control signals in stop mode.") RDE, ____ WEL, ____ WEH, ____ ____ CS0- CS4, _____ RSMP, _____ HLDA ALE A0/D0-A15/D15, A16 , A 17 P42/1 When the clock 1 output selection bit *2 = "1" 1: "L" level is output. "L" level is output. Retains the same state in which the STP instruction is executed. When the signal output disable selection bit *3 = "0" 1: "L" level is output. When the signal output disable selection bit = "1" P42: Bit 2's value of the port P4 register is output (Note). When the clock 1 output selection bit = "0" P42: Retains the same state in which the STP instruction is executed. P4 3 to P4 7 , P5 to P8 Ports P0 to P8 :Retains the same state (not including P42) : Retains the same in which the STP instruction is executed. state in which the STP instruction is executed. Standby state selection bit *1: Bit 0 at address 6D16 (Refer to Figure 11.3.1.) Clock 1 output selection bit *2: Bit 7 at address 5E 16 (Refer to section "12.1 Signals required for accessing external devices.") Signal output disable selection bit *3: Bit 6 at address 6C 16 (Refer to section "12.1 Signals required for accessing external devices.") Note: Make sure to set bit 2 of the port P4 direction register to "1." 11-4 7735 Group User's Manual STOP AND WAIT MODES 11.3 Stop mode Setting of the output levels for the external bus, chip select signals, and bus control signals (not including RDE) b7 b0 Port P0 direction register (address 4 16) Port P1 direction register (address 5 16) Port P2 direction register (address 8 16) Port P3 direction register (address 9 16) 1 1 1 1 1 1 1 1 Must be fixed to "FF 16." b7 b0 Port P0 register (address 2 16) Port P1 register (address 3 16) Port P2 register (address 6 16) Port P3 register (address 7 16) Set output level by the bit which corresponds to each pin. 0: "L" level output 1: "H" level output * When setting the signal output disable selection bit to "1" in the microprocessor mode 1 output selection * When setting the clock bit to "0" in the memory expansion mode b7 b0 1 Port P4 direction register (address C 16) * When setting the signal output disable selection bit to "0" in the microprocessor mode * When setting the clock 1 output selection bit to "1" in the memory expansion mode (Note 1) b7 b0 Port P4 register (address A 16) 0: "L" level output 1: "H" level output Note 1: This is applied only in the microprocessor mode. In the memory expansion mode, it may be "0" or "1" because the I/O port function is selected. Setting of the standby state selection bit to "1" b7 b0 0 1 Port function control register (address 6D 16) Standby state selection bit ( Note 2) Note 2: This bit's value also affects the pin state in the wait mode. (Refer to Figure 11.4.1.) Setting of RDE signal's output level (Setting of pin P4 2/ b7 1's state) b0 Oscillation circuit control register 0 (address 6C 16) Signal output disable selection bit ( Note 3) 0: In the stop mode, pin E/RDE outputs "H" level, and pin P4 2/ outputs "L" level. 1: In the stop mode, pin E/RDE outputs "L" level, and pin P4 2/ outputs bit 2's value of port P4 register. 1 STP instruction is executed. 1 Note 3: This bit's value also affects the following: * Output state of bus control signals and others after the stop mode is terminated (Refer to chapter "12. CONNECTING EXTERNAL DEVICES" ) * Pin state in the wait mode. (Refer to Figure 11.4.1.) Furthermore, description of pin P4 2/ 1 is applied only in the microprocessor mode. Fig. 11.3.1 Output level setting example in stop mode (Memory expansion or Microprocessor mode) 7735 Group User's Manual 11-5 STOP AND WAIT MODES 11.4 Wait mode 11.4 Wait mode Concerning section "11.4 Wait mode," the 7735 Group differs from the 7733 Group in the following: * Table 11.4.2 and Figure 11.4.1 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "11.4 Wait mode" (page 11-13 in part 1) 11-6 7735 Group User's Manual STOP AND WAIT MODES 11.4 Wait mode Table 11.4.2 Pin state in wait mode Pins __ E Single-chip mode State Memory expansion Microprocessor mode mode When the standby state When the standby state selection bit1 = "0" selection bit1 = "1" When the signal output Same as in the micro- "H" level is output. When the signal output disable selection bit = processor mode disable selection bit = "0," "H" level is output. "0," "H" level is output. When the signal output disable selection bit = "1," "L" level is output. When the signal output disable selection bit = "1," "L" level is output. ____ Output level can be set. (Refer to section "11.4.2 Output levels of external bus and bus control signals in wait mode") RDE, ____ WEL, ____ WEH, ____ ____ CS0- CS4, _____ RSMP, _____ HLDA ALE A0 /D0-A 15/D15, A16 , A17 P42/1 Ports "L" level is output. Retains the same state in which the WIT instruction is executed. When the clock 1 output selection bit *2 = "1" When the signal output disable selection bit *3 = "0" 1: Operating when the system clock stop bit 1: Stopped when the at wait state*4 = "0." system clock stop bit at "L" level is output when the system clock wait state = "0." stop bit at wait state = "1." "L" level is output when When the clock 1 output selection bit = "0" the system clock stop bit at wait state = "1." P4 2: Retains the same state in which the WIT instruction is When the signal output disable selection bit = "1" executed. P42: Bit 2's value of port P4 register is output (Note). P0 to P8 (not including P4 2) : Retains the same state in which the WIT instruction is executed. P4 3 to P4 7, P5 to P8 : Retains the same state in which the WIT instruction is executed. Standby state selection bit*1: Bit 0 at address 6D16 (Refer to Figure 11.4.1.) Clock 1 output selection bit *2: Bit 7 at address 5E 16 (Refer to section "12.1 Signals required for accessing external devices.") Signal output disable selection bit *3: Bit 6 at address 6C 16 (Refer to section "12.1 Signals required for accessing external devices.") System clock stop bit at wait state *4: Bit 5 at address 6C 16 (Refer to section "11.4.1 State of clocks f2 to f512 in wait mode.") Note: Make sure to set bit 2 of the port P4 direction register to "1." 7735 Group User's Manual 11-7 STOP AND WAIT MODES 11.4 Wait mode Setting of the output levels for the external bus, chip select signals, and bus control signals (not including RDE) b7 b0 1 1 1 1 1 1 1 1 Port P0 direction register (address 4 16) Port P1 direction register (address 5 16) Port P2 direction register (address 8 16) Port P3 direction register (address 9 16) Must be fixed to "FF 16." b7 b0 Port P0 register (address 2 16) Port P1 register (address 3 16) Port P2 register (address 6 16) Port P3 register (address 7 16) Set output level by bit which corresponds to each pin. 0: "L" level output 1: "H" level output * When setting the signal output disable selection bit to "1" in the microprocessor mode * When setting the clock 1 output selection bit to "0" in the memory expansion mode b7 b0 1 Port P4 direction register (address C 16) (Note 1) b7 b0 * When setting the signal output disable selection bit to "0" in the microprocessor mode * When setting the clock 1 output selection bit to "1" in the memory expansion mode Port P4 register (address A 16) 0: "L" level output 1: "H" level output Note 1: This is applied only in the microprocessor mode. In the memory expansion mode, it may be "0" or "1" because the I/O port function is selected. Setting of standby state selection bit to "1" b7 b0 0 1 Port function control register (address 6D 16) Standby state selection bit (Note 2) Note 2: This bit's value also affects the pin state in the stop mode. (Refer to Figure 11.3.1.) Setting of E/RDE signal's output level (Setting of pin P4 2/ b7 1's state) b0 Oscillation circuit control register 0 (address 6C 16) Signal output disable selection bit (Note 3) 0: In the wait mode, pin E/RDE outputs "H" level. Pin P4 2/ 1 operates when system clock stop bit at wait state = "0" and outputs "L" level when this bit = "1." 1: In the wait mode, pin E/RDE outputs "L" level. Pin P4 2/ 1 outputs bit 2's value of port P4 register. WIT instruction is executed. Note 3: This bit's value also affects the following: * Output state of bus control signals and others after the wait mode is terminated (Refer to chapter "12. CONNECTING EXTERNAL DEVICES." ) * Pin state in the stop mode. (Refer to Figure 11.3.1.) Furthermore, description of pin P4 2/ 1 is applied only in the microprocessor mode. Fig. 11.4.1 Output level setting example in wait mode (Memory expansion or Microprocessor mode) 11-8 7735 Group User's Manual CHAPTER 12 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices 12.2 Software wait 12.3 Ready function 12.4 Hold function CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices Functions for connecting external devices are described in this chapter. Reading or writing data from or to external devices are performed by the bus interface unit (BIU). (Refer to _ section "2.2 Bus interface unit.") The BIU operates on the basis of _internal enable signal E (usually, internal ____ clock ____ divided by 2) but does not output internal enable signal E to the external. The BIU outputs ____ signals RDE , WEL , and WEH . ____ ____ ____ _ Signals RDE, WEL, and WEH are generated from internal enable signal E and are output at the same timing _ as that of internal enable signal E . When external devices are accessed, the BIU outputs some of these signals, in other words, outputs only signals which are required for the access at that time. 12-2 7735 Group User's Manual CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices 12.1 Signals required for accessing external devices Functions and operations of signals required for accessing external devices are described below. When connecting external devices which require a long access time, refer to sections "12.2 Software wait," "12.3 Ready function," and "12.4 Hold function," also. When connecting external devices, make sure that the microcomputer operates in the memory expansion or microprocessor mode. (Refer to section "2.5 Processor modes.") When the microcomputer operates in __ ____ these modes, ports P0 to P4 and pin E/RDE function as I/O pins of signals required for accessing external devices. Figure 12.1.1 shows the pin configuration in the memory expansion or microprocessor mode. Table 12.1.1 __ ____ lists the functions of ports P0 to P4 and pin E/RDE in the memory expansion or microprocessor mode. 7735 Group User's Manual 12-3 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 CS0(P00) CS1(P01) CS2(P02) CS3(P03) CS4(P04) RSMP(P05) A16(P06) A17(P07) A8/D8(P10) A9/D9(P11) A10/D10(P12) A11/D11(P13) A12/D12(P14) A13/D13(P15) A14/D14(P16) A15/D15(P17) A0/D0(P20) A1/D1(P21) A2/D2(P22) A3/D3(P23) When external data bus is 16 bits wide (BYTE = "L") 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 39 67 38 68 37 69 36 70 35 71 34 M37735MHBXXXFP 72 73 A4/D4(P24) A5/D5(P25) A6/D6(P26) A7/D7(P27) WEL(P30) WEH(P31) ALE(P32) HLDA(P33) Vss RDE XOUT XIN RESET CNVSS BYTE HOLD 33 32 74 31 75 30 76 29 77 28 78 27 79 26 80 25 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 *1 P42/ 1 1 RDY P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG/TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 1 1 in the microprocessor mode : External address bus, external data bus, chip select signals, and bus control signals By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin's level can be fixed in the stop or wait mode. P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 CS0(P00) CS1(P01) CS2(P02) CS3(P03) CS4(P04) RSMP(P05) A16(P06) A17(P07) A8(P10) A9(P11) A10(P12) A11(P13) A12(P14) A13(P15) A14(P16) A15(P17) A0/D0(P20) A1/D1(P21) A2/D2(P22) A3/D3(P23) When external data bus is 8 bits wide (BYTE = "H") 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG/TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 65 40 66 39 67 38 68 37 69 36 70 35 71 34 M37735MHBXXXFP 72 73 33 32 74 31 75 30 76 29 77 28 78 27 79 26 80 25 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 *1 P42/ 1 RDY 1 A4/D4(P24) A5/D5(P25) A6/D6(P26) A7/D7(P27) WEL(P30) WEH(P31) *2 ALE(P32) HLDA(P33) Vss RDE XOUT XIN RESET CNVSS BYTE HOLD 1 1 in the microprocessor mode 2 "H"level is output : External address bus, external data bus, chip select signals, and bus control signals By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin's level can be fixed in the stop or wait mode. Fig. 12.1.1 Pin configuration in memory expansion or microprocessor mode (Top view) 12-4 7735 Group User's Manual CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices __ ____ Table 12.1.1 Functions of ports P0 to P4 and pin E/RDE in memory expansion or microprocessor mode External data 16 bits 8 bits bus width (BYTE = "L") (BYTE = "H") Pin name CS0 to CS4 CS 0 to CS 4 CS0 to CS4 RSMP RSMP RSMP A16, A17 A 16, A17 A 16, A17 A8/D8 to A15/D15 A8/D8 to A15/D 15 A8 to A15 (Note 1) D(odd) A8 to A 15 A8 to A15 D(odd) : Data at odd address A0/D0 to A7/D7 A0/D0 to A7/D7 A 0 to A 7 A0/D0 to A7/D7 D(even) A0 to A 7 D D : Data D(even) : Data at even address WEL WEL WEL WEL (Note 2) WEH WEH WEH (Note 2) ALE ALE ALE ALE HLDA HLDA HLDA HOLD HOLD HOLD RDY 1 P43 to P47 RDY 1 P43 to P47 WEH HLDA WEL (Note 2) ("H" level output) ALE HLDA RDY 1 (Note 3) P P : Functions as programmable I/O port E/RDE RDE (Note 2) Notes 1: When the internal area is accessed, signals CS0 to CS 4 are not output. (Output levels are fixed to "H.") 2: These signals are affected by the signal output disable selection bit (bit 6 at address 6C 16). (Refer to Table 12.1.4.) 3: In the memory expansion mode, this pin functions as a programmable I/O port. Furthermore, it can be switched to be a clock 1 output pin when selected by software. In the microprocessor mode, this signal is affected by the signal output disable selection bit (bit 6 at address 6C 16). (Refer to Table 12.1.3.) 7735 Group User's Manual 12-5 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices ____ ____ 12.1.1 External bus (A0 /D 0 to A15 /D 15 , A 16 and A17 ) and chip select signals ( CS0 to CS4 ) The address (A 0 to A17 ) and chip select signals are output and specify the external area. Figures 12.1.2 and 12.1.3 show the external areas specified by these signals. An area specified by a chip select signal does not the internal area. (When the internal area is accessed, the chip select signal is not output.) Pins A 8 to A 15 of the external address bus and pins D 0 to D 15 of the external data bus share the same pins. When pin BYTE's level, which is described later, is "L" (in other words, when the external data bus is 16 bits wide), pins A0/D 0 to A15/D15 perform address output and data input/output with the time-sharing method. When pin BYTE's level is "H" (in other words, when the external data bus is 8 bits wide), pins A0/ D0 to A7/D7 perform address output and data input/output with the time-sharing method and pins A8 to A15 output the address. Memory expansion mode (for M37735MHBXXXFP) Memory allocation selection bits (b2,b1,b0) = (0,0,0) (0,0,1) (1,1,0) 00000016 00000016 000000 16 SFR area SFR area 000080 16 SFR area 00008016 Internal RAM area 00100016 001000 16 00000016 SFR area 00008016 Internal RAM area (1,1,1) 00008016 Internal RAM area Internal RAM area 00100016 CS0 00100016 CS 0 00200016 00800016 Internal ROM area Internal ROM area 0C000016 0C0000 16 CS3 0C000016 CS4 0FFFFF 16 : External area specified by address and chip select signal The memory allocation selection bits must be set as above. Fig. 12.1.2 External area (Memory expansion mode) 12-6 08000016 0C0000 16 0FFFFF16 CS2 CS3 CS 4 CS4 0FFFFF16 080000 16 CS 3 CS3 04000016 CS2 08000016 08000016 CS1 040000 16 CS 2 CS2 01000016 CS 1 04000016 04000016 Internal ROM area 020000 16 CS1 CS1 00800016 Internal ROM area 02000016 02000016 CS0 7735 Group User's Manual CS4 0FFFFF16 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices Microprocessor mode (for M37735MHBXXXFP) 00000016 SFR area 00008016 Internal RAM area 00100016 CS0 00800016 CS1 04000016 CS2 08000016 CS3 0C0000 16 CS4 0FFFFF16 : External area specified by address and chip select signal Fig. 12.1.3 External area (Microprocessor mode) 7735 Group User's Manual 12-7 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices 12.1.2 External data bus width selection signal (Pin BYTE's level) This signal is used to select the external data bus width from 8 bits and 16 bits. When this signal level is "L," the external data bus is 16 bits wide; when this signal level is "H," the external data bus is 8 bits wide. (Refer to Table 12.1.1.) This signal level must be fixed to either "H" or "L." This signal is valid only for the external areas. (When the internal area is accessed, the data bus is always 16 bits wide.) ____ ____ ____ 12.1.3 Read enable signal ( RDE ) and Write enable signals ( WEL, WEH) These signals are output when data is read or written from or to the external area. When the internal area is accessed, these signals are stopped at "H" level by setting the signal output disable selection bit (bit 6 at address 6C16 ) to "1." (Refer to Table 12.1.4.) Table 12.1.2 Functions of read enable signal and write enable signals External data bus width 16 bits (BYTE = "L") 8 bits (BYTE = "H") ____ ____ ____ RDE WEL WEH H L H H H H L H H H L H L H H L H H H L L H H H External data bus state Data is read out. 1-byte data is written to even address. 1-byte data is written to odd address. 1-word data is written. Data is read out. Data is written. 12.1.4 Address latch enable signal (ALE) This signal is used to latch an address from a multiplexed signal. This multiplexed signal consists of the address and data and is input or output to or from pins A0/D0 to A15/D15, A16/D0 to A23/D7. When this signal level is "H," take the address into a latch and output it simultaneously. When this signal level is "L," retain the latched address. ____ _____ _____ _____ 12.1.5 Signals related to ready function (RDY , RSMP) These signals are required to use the ready function. (Refer to section "12.3 Ready function.") 12.1.6 Signals related to hold function (HOLD, HLDA) These signals are required to use the hold function. (Refer to section "12.4 Hold function.") 12.1.7 Clock 1 This signal has the same period as internal clock . Whether clock 1 is output or stopped can be selected by software. However, the method of this selection depends on the processor mode. Table 12.1.3 lists the method to select whether to output or stop clock 1. Figure 12.1.4 shows the clock 1 output start timing. 12-8 7735 Group User's Manual CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices Table 12.1.3 Method to select whether to output or stop clock 1 Processor mode Single-chip or Memory expansion mode Microprocessor mode *1 Clock 1 output Set the clock 1 output selection bit to Clear the signal output disable selection bit*2 to "0." "1." Clock 1 stopped Clear the clock 1 output selection bit to "0." (Pin P4 2 functions as a programmable I/O port.) Set the signal output disable selection bit to "1." (Note) Remark Clock 1 is stopped after reset. The signal output disable selection bit is ignored. Clock 1 is output after reset. The clock 1 output selection bit is ignored. Clock 1 output selection bit *1: Bit 7 at address 5E 16 Signal output disable selection bit *2: Bit 6 at address 6C 16 (Refer to Table 12.1.4.) Note: When bit 2 at address C16 (Port P4 direction register) is set to "1," bit 2 of the port P4 register is output. Table 12.1.4 Functions of signal output disable bit Processor mode Each signal's state Conditions Signals Memory When the external area is accessed expansion or Microprocessor When the internal area is accessed mode When the standby state selection bit = "1" in the stop or wait mode Signal output disable selection bit 1 0 ____ RDE, ____ WEL, ____ WEH ____ RDE, ____ WEL, ____ WEH Operating Operating Stopped at "H" level Stopped at "H" level Stopped at "L" level Stopped (Output levels can be set.) (Refer to Figures 11.3.1 and 11.4.1.) ____ When the standby state selection bit = "0" in the stop or wait mode RDE, WEL, ____ Stopped at "H" level ____ WEH Clock 1 Microprocessor mode Single-chip mode When not in the stop or wait mode Enable signal Operating (independent Stopped (Note) of the 1 output selection bit) Operating Stopped at "L" level Stopped at "H" level Stopped at "L" level __ E When in the stop or wait mode All functions listed in Table 12.1.4 are not emulated by a debugger. For the stop and wait modes and the standby state selection bit, refer to chapter "11. STOP AND WAIT MODES." Note: When bit 2 at address C16 (Port direction register) is set to "1," bit 2 of the port P4 register is output. :Not affected by the signal output disable selection bit. 7735 Group User's Manual 12-9 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices The clock 1 output selection bit is set to "1." E Clock 1 : There is a possibility that the first cycle of clock 1 output is not an exact square; the shaded section may be lost. : This is applied when "1" is written to the clock 1 output selection bit while pin P4 2 outputs "L" level. Fig. 12.1.4 Clock 1 output start timing (when clock 1 output selection bit is set from "0" to "1") b7 b6 b5 b4 b3 b2 b1 b0 Oscillation circuit control register 0 (address 6C 16) Bit Bit name 0 XCOUT drivability selection bit 1 Not implemented. 2 Main clock stop bit Functions 0: Drivability "LOW" 1: Drivability "HIGH" 0: Main clock oscillation or external clock input is available. At reset RW 1 RW (Note 1) Undefined - 0 RW (Note 1) RW (Note 2) 1: Main clock oscillation or external clock input is stopped. 3 System clock selection bit When the port-Xc selection bit = "0," 0: Main clock 1: Main clock divided by 8 When the port-Xc selection bit = "1," 0: Main clock 1: Sub clock 0 4 Port-Xc selection bit 0: Operate as I/O ports (P7 7, P76 ). 1: Operate as pins X CIN and X COUT . 0 5 System clock stop bit at wait state (Note 4) 0: Operates in the wait mode. 1: Stopped in the wait mode. 0 RW 6 Signal output disable selection bit 0: Output is enabled. 1: Output is disabled. 0 RW 7 Not implemented. Undefined - (Refer to Tables 12.1.3 and 12.1.4) RW (Notes 2 and 3) Notes 1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc selection bit = "1." 2: When selecting the sub clock as the system clock, set bit 3 to "1" after setting bit 4 to "1." If the above settings are performed simultaneously, in other words, performed by executing only one instruction, only bit 3 is set to "1." 3: Although this bit can be set to "1," it cannot be cleared to "0" after this bit is once set to "1." 4: When setting the system clock stop bit at wait state to "1," perform it immediately before the WIT instruction is executed. Furthermore, clear this bit to "0" immediately after the wait mode is terminated. 5: represents that bits 0 to 5 and 7 are not used for access control of external area. (Functions of these bits are valid.) Fig. 12.1.5 Structure of oscillation circuit control register 0 12-10 7735 Group User's Manual CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices Value "1" is written to the signal output disable selection bit. Internal enable signal E (in single-chip mode) RDE (Note) "H" WEL (Note) WEH (Note) Clock 1 (in the microprocessor mode) Signal is stopped. Note: These signals can be stopped only when accessing internal area (in the memory expansion and microprocessor modes). Fig. 12.1.6 Relationship between setting of signal output disable selection bit and stop timing of each signal 7735 Group User's Manual 12-11 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices 12.1.8 Operation of bus interface unit (BIU) Figures 12.1.7 to 12.1.9 show operating waveform examples of signals which are input to or output from the external when accessing external devices. These waveforms are described in relation to the basic operating waveforms. (Refer to section "2.2.3 Operation of bus interface unit (BIU).") (1) When fetching an instruction into an instruction queue buffer When an instruction which is next fetched resides at an even address When the external data bus is 16 bits wide, the BIU fetches two bytes of the instruction at a time with waveform (a). When the external data bus is 8 bits wide, the BIU fetches only one byte of the instruction with the first half of waveform (i). When an instruction which is next fetched resides at an odd address When the external data bus is 16 bits wide, the BIU fetches only one byte of the instruction with waveform (g). When the external data bus is 8 bits wide, the BIU fetches only one byte of the instruction with the first half of waveform (i). When branched to an odd address by executing a branch instruction or others with the 16-bit external data bus, at first, the BIU fetches one byte of an instruction with waveform (g) and then fetches instructions by the two bytes with waveform (a). (2) When reading or writing data from or to memory * I/O When accessing 16-bit data which starts from an even address, waveform (a), (b), (i) or (j) applied. When accessing 16-bit data which starts from an odd address, waveform (c), (d), (i) or (k) applied. When accessing 8-bit data which resides at an even address, waveform (e), (f) or the first half waveform (i) or (j) is applied. When accessing 8-bit data which resides at an odd address, waveform (g), (h) or the first half waveform (k) is applied. is is of of For instructions which are affected by data length flag (m) and index register length flag (x), an operation is applied as follows.: *When "m" or "x" = "0," operation or is applied. *When "m" or "x" = "1," operation or is applied. Settings of flags "m" and "x" and selection of the external data bus width do not affect each other. 12-12 7735 Group User's Manual CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices When external data bus is 16 bits wide (BYTE = "L" ) <16-bit data access> (a) Read starting from even address (b) Write starting from even address "H" RDE RDE "H" "H" WEH WEH "H" WEL WEL ALE ALE CS 0 to CS 4 CS 0 to CS4 A16, A17 A16, A17 Address A8/D8 to A15/D15 Address A0/D0 to A7/D7 Address Address (Note 1) A8/D8 to A15/D15 Address Data (odd) (Note 1) A0/D0 to A7/D7 Address Data (even) (c) Read starting from odd address (d) Write starting from odd address "H" RDE RDE "H" "H" WEH WEH "H" WEL WEL ALE ALE CS0 to CS4 CS0 to CS 4 A16, A17 Address A8/D 8 to A 15/D 15 Address A0/D 0 to A7/D 7 Address (Note 1) (Note 2) Address Address Address A16, A17 Address (Note 2) A8/D 8 to A15/D15 Address (Note 1) A0/D 0 to A7/D 7 Address Address Data (odd) (Note 3) Address (Note 3) Address Data (even) Notes 1: These pins which function as the external bus enter the floating state. While these pins are in the floating state, data on the data bus is fetched into the data buffer of the BIU. 2: These pins which function as the external bus enter the floating state. While these pins are in the floating state, data on the data bus is not fetched fetched into the data buffer of the BIU. 3: Invalid data (Undefined value) Fig. 12.1.7 Operating waveform example of signals which are input to or output from the external (1) 7735 Group User's Manual 12-13 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices When external data bus is 16 bits wide (BYTE = "L" ) <8-bit data access> (e) Read starting from even address (f) Write starting from even address "H" RDE RDE "H" "H" WEH WEH "H" WEL WEL ALE ALE CS 0 to CS 4 CS0 to CS 4 A16, A17 Address A8/D8 to A15/D15 Address A0/D0 to A7/D7 Address Address A16, A17 A8/D8 to A15/D 15 Address (Note 3) (Note 2) A0/D0 to A7/D7 Address Data (even) (Note 1) (g) Read starting from odd address (h) Write starting from odd address "H" RDE RDE "H" WEH WEH "H" "H" WEL WEL ALE ALE CS 0 to CS 4 CS0 to CS 4 A16, A17 Address A8/D8 to A15/D15 Address A0/D0 to A7/D7 Address A16, A17 Address A8/D8 to A15/D 15 Address (Note 1) A0/D0 to A7/D7 Address (Note 2) Data (odd) (Note 3) Notes 1: These pins which function as the external bus enter the floating state. While these pins are in the floating state, data on the data bus is fetched into the data buffer of the BIU. 2: These pins which function as the external bus enter the floating state. While these pins are in the floating state, data on the data bus is not fetched into the data buffer of the BIU. 3: Invalid data (Undefined value) Fig. 12.1.8 Operating waveform example of signals which are input to or output from the external (2) 12-14 7735 Group User's Manual CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices When external data bus is 8 bits wide (BYTE = "H" ) <8/16-bit data access> (i) Read starting from even or odd address (j) Write starting from even address "H" RDE RDE "H" WEH WEH "H" WEL WEL ALE ALE CS 0 to CS4 CS0 to CS4 A16, A17 Address Address A16, A17 Address Address A8 to A15 Address Address A8 to A15 Address Address A0/D0 to A7/D7 Address (Note) Address A 0/D0 to A7/D7 (Note) Address Data (even) Address Data (odd) 8-bit data access 8-bit data access 16-bit data access 16-bit data access (k) Write starting from odd address "H" RDE WEH WEL ALE CS0 to CS4 Note: These pins which function as the external bus enter the floating state. While these pins are in the floating state, data on the data bus is fetched into the data buffer of the BIU. A16, A17 Address Address A8 to A15 Address Address When 16-bit data is accessed, the low-order 8 bits of data are accessed first, and then, the high-order 8 bits are accessed. A0/D0 to A7/D7 Address Data (odd) Address Data (even) 8-bit data access 16-bit data access Fig. 12.1.9 Operating waveform example of signals which are input to or output from the external (3) 7735 Group User's Manual 12-15 CONNECTING EXTERNAL DEVICES 12.2 Software wait 12.2 Software wait The software wait facilitates access to external devices which require a long access time. There are two types of software waits: wait 0 and wait 1. The software wait is set by the wait bit (bit 2 at address 5E16) and the wait selection bit (bit 0 at address 5F16). (Refer to Table 12.2.1.) Figure 12.2.1 shows the structures of the processor mode register 0 (address 5E16) and processor mode register 1 (address 5F 16). Figure 12.2.2 shows bus timing examples when the software wait is used. The software wait is valid only for the external area. (Access to the internal areas is always performed with no wait.) For external devices which can not be accessed even when using the software wait, by using the ready _____ function (signal RSMP ), a wait which is equivalent to 1 cycle of clock 1 can furthermore be generated. (Refer to section "12.3 Ready function." Table 12.2.1 Setting method of software wait Wait bit Wait selection bit 1 0 Invalid (No wait) Cycle of "internal clock divided by 2" (clock 1's cycle 2) 0 0 Wait 0 "Cycle in the no-wait state" 2 (clock 1's cycle 4 ) 0 1 Wait 1 "Cycle in the no-wait state" 1.5 (clock 1's cycle 3 ) 12-16 Software wait Bus cycle 7735 Group User's Manual CONNECTING EXTERNAL DEVICES 12.2 Software wait b7 b6 b5 b4 b3 b2 b1 b0 0 Processor mode register 0 (address 5E 16) Bit name Bit 0 Functions b1 b0 Processor mode bits 00: Single-chip mode 01: Memory expansion mode 10: Microprocessor mode 11: Do not select. 1 At reset RW 0 RW 0 RW (Note 1) 2 Wait bit 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. 0 RW 3 Software reset bit Microcomputer is reset by setting this bit to "1." This bit is "0" at reading. 0 WO 4 Interrupt priority detection time selection bits 0 RW 0 RW 0 RW 0 RW b5 b4 5 6 Must be fixed to "0." 7 Clock f1 output selection bit (Note 2) 00: 7 cycles of f 01: 4 cycles of f 10: 2 cycles of f 11: Do not select. 0: Clock f1 output is disabled. (P4 2 functions as a programmable /O port.) 1: Clock f1 output is enabled. (Port P4 2 functions as a clock f1 output pin.) Notes 1: When the Vcc-level voltage is applied to pin CNVss, this bit is set to "1" after reset. (At reading, this bit is always "1.") 2: This bit is ignored in the microprocessor mode. (It may be "0" or "1.") 3: represents that bits 3 to 6 are not used for access control of the external area. (Functions of these bits are valid.) b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 1 (address 5F 16 ) Bit 0 Bit name Wait selection bit Function 0 : Wait 0 1 : Wait 1 7 to1 Not implemented. At reset RW 0 RW Undefined _ Fig. 12.2.1 Structures of processor mode register 0 and processor mode register 1 7735 Group User's Manual 12-17 CONNECTING EXTERNAL DEVICES 12.2 Software wait <<No wait>> 1-bus cycle Clock 1 ALE RSMP CS0 to CS4 Address A16, A17 (Note) Address A0/D 0 to A15/D15 Address Data Address Data This waveform is always applied when the internal area is accessed. <<Wait 0>> 1-bus cycle Clock 1 ALE RSMP CS0 to CS4 A16, A17 Address Address (Note) A0/D 0 to A15/D15 Data Address Data Address <<Wait 1>> 1-bus cycle Clock 1 ALE RSMP CS0 to CS4 A16, A17 Address Address (Note) A 0/D0 to A15/D15 Address Data Address Data One of the following is applied.: *One of signals RDE, WEL, and WEH *Signals WEL and WEH Note: When the external data bus is 8 bits wide (BYTE = "H" ), operating waveform of A 8/D8 to A 15/D15 is the same as that of A 16 and A17. Fig. 12.2.2 Bus timing examples when software wait is used (BYTE = "L" ). 12-18 7735 Group User's Manual CONNECTING EXTERNAL DEVICES 12.3 Ready function 12.3 Ready function The ready function facilitates____ access to external devices which require a long access time. By applying "L" level to pin RDY in the memory expansion or microprocessor mode, the microcomputer ____ enters the ready state. While pin RDY's level is "L," this state is retained. Table 12.3.1 lists the microcomputer's state in the ready state. In the ready state, oscillation of the oscillator does not stop. Therefore, the internal peripheral devices can operate even in the ready state. The ready function is valid for the internal and external areas. Table 12.3.1 Microcomputer's state in ready state Item Oscillation State Operating Stopped at "L" level CPU ____ ____ ____ RDE, WEL , WEH , CS 0 to CS4 , Retains the same state in which RDY was accepted. _____ HLDA , ALE, A 0/D 0 to A 15 /D 15, A 16, A 17 ____ P43 to P47, P5 to P8 (Note 2) P42/ 1 In the memory expansion mode When the clock 1 output selection bit *1 = "1" Outputs clock 1 . When the clock 1 output selection bit = "0" ____ Retains the same state in which RDY was accepted. In the microprocessor mode When the signal output disable selection bit*2 = "1" ____ Retains the same state in which RDY was accepted. When the signal output disable selection bit = "0" Outputs clock 1 . Timers A and B, Serial I/O, Operating A-D converter, Watchdog timer Clock 1 output selection bit *1: Bit 7 at address 5E16 Signal output disable selection bit *2: Bit 6 at address 6C 16 ____ Notes 1: When "L" level which was input to pin RDY is sampled at one of the following timings, this signal is not accepted. (Note that CPU is stopped at "L" level.) ____ ____ ____ When the levels of signals RDE, WEL, and WEH are "H" while the bus is in use (Refer to in Figure 12.3.2.) Immediately before a wait generated by the software wait (Refer to in Figure 12.3.2.) 2: This is applied when these pins function as programmable I/O ports. 7735 Group User's Manual 12-19 CONNECTING EXTERNAL DEVICES 12.3 Ready function 12.3.1 Operation in ready ____ state When "L" level is input to pin RDY, this signal is accepted at the falling edge of____ clock 1 and the microcomputer enters the ready state. ____ The ready state can be terminated by setting pin RDY 's level to "H" again. When "H" level is input to pin RDY, this signal is also accepted at the falling edge of clock 1 and the ready state is terminated. Figure 12.3.2 shows timings when the ready state is accepted and terminated. When generating a wait which is equivalent to 1 cycle of clock 1 by using the ready function, use signals _____ ____ RSMP and CSn (n = 0 to 4). These signals facilitate to generate a signal input to pin RDY . Figure 12.3.1 _____ _____ shows a connection example when signal RSMP is used. Note that signal RSMP is affected by the software _____ wait. Figure 12.3.3 shows the relationship between the software wait and signal RSMP. Refer to section "17.1 Memory expansion" for the way to use the ready function. M37735MHBXXXFP CS n Chip select signal RSMP RDY n : 0 to 4 _____ Fig. 12.3.1 Connection example when signal RSMP is used 12-20 7735 Group User's Manual CONNECTING EXTERNAL DEVICES 12.3 Ready function <<No wait>> Sampling timing One of the following is applied.: * One of signals RDE, WEL, and WEH * Signals WEL and WEH Clock 1 : Ready state : Software wait CPU "L" level which is input to pin RDY is accepted, so that signal is stopped at "H" level for 1cycle of clock 1 (area ), and at "L" level. ALE CPU is stopped "L" level which is input to pin RDY is not accepted, but CPU is stopped at "L" level. "L" level which is input to pin RDY is accepted, so that signal is stopped at "L" level for 1cycle of clock 1 RDY Bus is not in use. Bus is in use. (area "L" level. <<Wait 0>> CPU is stopped at Sampling timing Clock ), and 1 CPU Ready state is terminated. "L" level which is input to pin RDY is not accepted because it is sampled immediately before a wait generated by software wait (area ), but CPU is stopped at "L" level. ALE RDY Bus is in use. <<Wait 1>> Sampling timing Clock 1 CPU ALE RDY Bus is in use. _____ Fig. 12.3.2 Timings when ready state is accepted and terminated (when not using signal RSMP) 7735 Group User's Manual 12-21 CONNECTING EXTERNAL DEVICES 12.3 Ready function <<No wait>> Clock One of the following is applied.: * One of signals RDE, WEL, and WEH 1 * Signals WEL and WEH CPU : Ready state : Software wait ALE RSMP CS0 to CS4 RDY <<Wait 0>> Clock 1 CPU ALE RSMP CS0 to CS 4 RDY <<Wait 1>> Clock 1 CPU ALE RSMP CS0 to CS 4 RDY _____ Fig. 12.3.3 Relationship between software wait and signal RSMP 12-22 7735 Group User's Manual CONNECTING EXTERNAL DEVICES 12.4 Hold function 12.4 Hold function When an external circuit which accesses the bus without using the central processing unit (CPU), for example DMA, is used, it is necessary to generate a timing for transferring the right to use of the bus from the CPU to the external circuit. The hold function is used to generate this timing. _____ By applying "L" level to pin HOLD in the memory expansion or microprocessor mode, the microcomputer _____ enters the hold state. While pin HOLD's level is "L," this state is retained. Table 12.4.1 lists the microcomputer's state in the hold state. In the hold state, oscillation of the oscillator does not stop. Therefore, the internal peripheral devices can operate even in the hold state. (Note that the watchdog timer stops.) Table 12.4.1 Microcomputer's state in hold state Item State Operating Oscillation Stopped at "L" CPU ____ ____ RDE , WEL, WEH, CS 0 to CS 4, Floating _____ RSMP, A0/D0 to A15/D15, A16, A17 _____ Outputs "L" level. HLDA , ALE In the memory expansion mode P4 2/ 1 When the clock 1 output selection bit *1 = "1" Outputs clock 1. When the clock 1 output selection _____ bit = "0" Retains the same state in which HOLD was accepted. In the microprocessor mode When the signal output disable selection bit *2= "1" _____ Retains the same state in which HOLD was accepted. When the signal output disable selection bit = "0" Outputs clock 1. ____ _____ P43 to P47, P5 to P8 (Note) Retains the same state in which HOLD was accepted. Timers A and B, Serial I/O, Operating A-D converter Watchdog timer Stopped Clock 1 output selection bit : Bit 7 at address 5E 16 Signal output disable selection bit *2: Bit 6 at address 6C 16 Note: This is applied when these pins function as programmable I/O ports. *1 7735 Group User's Manual 12-23 CONNECTING EXTERNAL DEVICES 12.4 Hold function 12.4.1 Operation in hold state _____ When "L" level is input to pin HOLD while _____ the bus is not in use, this signal is accepted at the falling edge of clock 1. When "L" level is input to pin HOLD while the ____ bus is____ in use, ____ this signal is accepted at the clock 1's falling edge which precedes the rising edge of signal RDE, WEL, or WEH by the clock 1's cycle divided by 2. (Refer to Figures 12.4.2 to 12.4.6.) Note that when word data which starts from an odd address is accessed by the two bus cycles, determination is performed only in the second bus cycle. (Refer to Figure 12.4.1.) _____ When "L" level which_____ was input to pin HOLD is accepted, CPU is stopped at the next rising edge of clock 1 . At this time, pin HLDA outputs "L" level, and so the external_____ is informed that the microcomputer is in ____ ____ the hold state. After one cycle of clock 1 has passed since pin HLDA's level becomes "L," pins RDE , WEL, ____ _____ WEH, CS0 to CS4 , RSMP and the external bus enter the floating state. _____ The hold state can be terminated by setting pin HOLD 's level to "H" again. When "H" level is input to pin _____ _____ HOLD, this signal is accepted at the falling edge of clock 1. When "H" level which was input to pin HOLD _____ is accepted, pin HLDA's level goes from "L" to "H." And then, the hold state is terminated after one cycle of clock 1 has passed. Figures 12.4.2 to 12.4.6 show the timing when the hold state is accepted and terminated. _____ In the ready state, determination of pin HOLD's input level is not performed. Determination timing of pin HOLD 's input level Not Determined determined Clock 1 RDE ALE At reading A At writing A A W A W Word data is accessed by the two bus cycles. (in this case, no wait) Fig.12.4.1 Determination when word data which starts from odd address is accessed by the two bus cycles 12-24 7735 Group User's Manual CONNECTING EXTERNAL DEVICES 12.4 Hold function <<When "L" level is input to pin HOLD while bus is not in use>> State when "L" level is input to pin HOLD External data bus Data length External data bus width Software wait 8 8, 16 No wait, 16 8, 16 Wait 1, Wait 0 Not in use Note: The same operation is performed independent of the software wait (no wait, wait 0, or wait 1). This diagram shows the operation when no wait is selected. Sampling timing Clock 1 ALE CS0 to CS 4 External address bus/ External data bus Address A Data Floating Address A Address B External address bus Floating BHE HOLD 1 1 1 1 HLDA Hold state Bus is in use. Bus is not in use. Bus is in use. Because the bus is not in use, the address which was output immediately before is output again, instead of a new address. RDE, WEL, WEH Fig. 12.4.2 Timing when hold state is accepted and terminated (1) 7735 Group User's Manual 12-25 CONNECTING EXTERNAL DEVICES 12.4 Hold function <<When "L" level is input to pin HOLD while bus is in use (1 )>> State when "L" level is input to pin HOLD External data bus Data length External data bus width 8 8, 16 In use 16 Software wait No wait 16 (When accessed starting from even address) Sampling timing Clock 1 ALE Floating CS0 to CS 4 Address A External address bus/ External data bus Address A Floating Data External address bus Address B Floating BHE HOLD 1 1 1 1 HLDA Hold state Bus is not in use. Bus is in use. When "L" level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. RDE, WEL, WEH Fig. 12.4.3 Timing when hold state is accepted and terminated (2) 12-26 7735 Group User's Manual Bus is in use. CONNECTING EXTERNAL DEVICES 12.4 Hold function <<When "L" level is input to pin HOLD while bus is in use (2)>> State when "L" level is input to pin HOLD External data bus Data length External data bus width 8 8, 16 In use Software wait Wait 1 16 16 (When accessed starting from even address) Sampling timing Clock 1 ALE Floating CS0 to CS 4 Address A Address A Floating External address bus/ External data bus Address B Data Floating External address bus BHE HOLD 1 1 1 1 HLDA Hold state Bus is not in use. Bus is in use. Bus is in use. When "L" level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. RDE, WEL, WEH Fig. 12.4.4 Timing when hold state is accepted and terminated (3) 7735 Group User's Manual 12-27 CONNECTING EXTERNAL DEVICES 12.4 Hold function <<When "L" level is input to pin HOLD while bus is in use (3)>> State when "L" level is input to pin HOLD External data bus Data length External data bus width 8 8, 16 In use Software wait Wait 0 16 16 (When accessed starting from even address) Sampling timing Clock 1 ALE Floating CS0 to CS 4 Address A Floating External address bus/ External data bus Address A Address B Data External address bus Floating BHE HOLD 1 1 1 1 HLDA Hold state Bus is not in use. Bus is in use. When "L" level which is input to pin HOLD is accepted, the address which was output immediately before is output again, instead of a new address. RDE, WEL, WEH Fig. 12.4.5 Timing when hold state is accepted and terminated (4) 12-28 7735 Group User's Manual Bus is in use. CONNECTING EXTERNAL DEVICES 12.4 Hold function <<When "L" level is input to pin HOLD while bus is in use (4)>> State when "L" level is input to pin HOLD External data bus Data length In use 16 External data bus width Software wait 8 No wait 16 (When accessed starting from even address) Sampling timing Clock 1 ALE Floating CS0 to CS 4 Low-order address High-order address Floating External address bus/ External data bus Data Data Address External address bus Floating BHE HOLD Not sampled 1 1 1 1 HLDA Hold state Bus is not in use. Bus is in use. Bus is in use. When "L" level which is input to pin HOLD is the accepted, the address which was output immediately before is output again, instead of a new address. Sampling is not performed until 16-bit data input/output is finished. ( "L" level which is input to pin HOLD is not accepted.) RDE, WEL, WEH Fig. 12.4.6 Timing when hold state is accepted and terminated (5) 7735 Group User's Manual 12-29 CONNECTING EXTERNAL DEVICES 12.4 Hold function MEMO 12-30 7735 Group User's Manual CHAPTER 13 RESET 13.1 Hardware reset 13.2 Software reset RESET 13.1 Hardware reset Concerning chapter "RESET," the 7735 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter: * "13.1 Hardware reset" The following section of the 7735 Group is the same as that of the 7733 Group. Therefore, for this section, refer to part 1: * "13.2 Software reset" (page 13-12 in part 1) 13.1 Hardware reset Concerning section "13.1 Hardware reset," the 7735 Group differs from the 7733 Group in the following: ______ * "Table 13.1.1 Pin state while pin RESET is at "L" level" * "Figure 13.1.6 State of SFR area and internal RAM area immediately after reset (4)" The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "13.1 Hardware reset" (page 13-2 in part 1) ______ Table 13.1.1 Pin state while pin RESET is at "L" level Mask ROM version Pin CNV SS's level V SS or V CC Pin (Port) name P0 to P8 _ ____ E/RDE Built-in PROM version VSS P0 to P8 _ ____ E/RDE VCC P0, P1, P3 to P8 P2 _ ____ E/RDE External ROM version VCC A0/D0 to A7/D7, A8/D8 to A15/D15, A16, A17 ___ ___ ____ CS0 to CS 4, WEL, ____ _____ Pin state Floating "H" level is output. Floating "H" level is output. Floating *Floating when "H" level is applied to both or one of pins P51 and P52 *"H" or "L" level is output when "L" level is applied to both of pins P5 1 and P5 2 . "H" level is output. "H" or "L" level is output. "H" level is output. _ ____ WEH, HLDA, E/RDE "L" level is output. ALE 1 ______ P4 3 to P4 7 , P5 to P8 13-2 (operating) is output. Floating 1 ____ HOLD, RDY, 7735 Group User's Manual RESET 13.1 Hardware reset Figure 13.1.6 for the 7735 Group differs from that for the 7733 Group only in 3. Address Register name b7 Watchdog timer register 6016 Watchdog timer frequency selection flag 6116 (Reserved area) 4 6216 Memory allocation control register 6316 6416 UART2 transmit/receive mode register UART2 baud rate register (BRG2) 6516 6616 UART2 transmission buffer register 6716 6816 UART2 transmit/receive control register 0 6916 UART2 transmit/receive control register 1 6A16 UART2 receive buffer register 6B16 Oscillation circuit control register 0 6C16 Port function control register 6D16 Serial transmit control register 6E16 Oscillation circuit control register 1 6F16 WO 7016 A-D / UART2 trans./rece. interrupt control register 7116 UART0 transmission interrupt control register 7216 UART0 receive interrupt control register 7316 UART1 transmission interrupt control register 7416 UART1 receive interrupt control register Timer A0 interrupt control register 7516 Timer A1 interrupt control register 7616 Timer A2 interrupt control register 7716 Timer A3 interrupt control register 7816 Timer A4 interrupt control register 7916 Timer B0 interrupt control register 7A16 Timer B1 interrupt control register 7B16 Timer B2 interrupt control register 7C16 INT0 interrupt control register 7D16 INT1 interrupt control register 7E16 INT2/Key input interrupt control register 7F16 Access characteristics b0 State immediately after reset b0 b7 WO RW RW RW WO WO RO RO WO RW RW RO RW ? ? 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 ? RO RW(2) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RO RW ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? ? ? 0 0 0 ? (1) ? ? 0 0 0 0 ? ? ? 1 0 0 ? 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 ? 0 ? 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value "FFF16" is set to the watchdog timer. (Refer to section Chapter "10. WATCHDOG TIMER.") 2 For access characteristics at address 6C16, also refer to Figure 14.3.2 in part 1. 3 State immediately after reset for bit 3 at address 6F16 vary according to the microcomputer. (Refer to Figure 14.3.3 in part 2 ; This bit's function of the 7735 Group differs from that of the 7733 Group.) This bit must be fixed to "0" in the 7735 Group. 4 Do not write data to address 6216. Internal RAM area (M37735MHBXXXFP: addresses 8016 to FFF16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset. When the stop or wait mode is terminated (when hardware reset is applied)...Retains the state immediately before the STP or WIT instruction is executed. Fig. 13.1.6 State of SFR area and internal RAM area immediately after reset (4) 7735 Group User's Manual 13-3 RESET 13.1 Hardware reset MEMO 13-4 7735 Group User's Manual CHAPTER 14 CLOCK GENERATING CIRCUIT 14.1 Overview 14.2 Oscillation circuit example 14.3 Clock control CLOCK GENERATING CIRCUIT 14.3 Clock control Concerning chapter "14. CLOCK GENERATING CIRCUIT," the 7735 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter: * "14.3 Clock control" The following sections are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1: * "14.1 Overview" (page 14-2 in part 1) * "14.2 Oscillation circuit example" (page 14-3 in part 1) 14.3 Clock control Concerning section "14.3 Clock control," the 7735 Group differs from the 7733 Group in the following: * Figures 14.3.3 and 14.3.4 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "14.3 Clock control" (page 14-5 in part 1) 14-2 7735 Group User's Manual CLOCK GENERATING CIRCUIT 14.3 Clock control In the M37735MHBXXXFP, set bit 3 of the oscillation circuit control register 1 to "0." b7 b6 b5 b4 b3 0 0 b2 b1 b0 Oscillation circuit control register 1 (address 6F16) Bit Bit name Functions At reset RW 0 Main clock division selection bit 0: Main clock is divided by 2. (Note 1) 1: Main clock is not divided by 2. 0 RW 1 Main clock external input selection bit 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when (Note 1) terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. 0 RW 2 Sub clock external input selection bit (Note 1) 0 RW 3 Must be fixed to "0" in the mask ROM and external ROM versions (Note 1). 0 RW Must be fixed to "0" in the one time PROM and EPROM versions (Notes 1 and 2). 1 4 Must be fixed to "0" (Note 3). 0 RW 5 Not implemented. Undefined -- 6 Not implemented. Undefined -- 7 Clock prescaler reset bit 0 WO 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT. Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. (Note 4) By writing "1" to this bit, clock prescaler is initialized. Notes 1: When writing to this register, follow the procedure shown in Figure 14.3.4. 2: Because this bit is "1" at reset, clear this bit to "0" with the initial setting program after reset. 3: The case where data "010101012" is written with the procedure shown in Figure 14.3.4 is not included. 4: For the 7733 Group, refer to Figure 14.3.3 in part 1. 5: represents that bits 3 to 7 are not used for the clock generating circuit. Fig. 14.3.3 Structure of oscillation circuit control register 1 * When writing to bits 0 to 3 Write data "010101012." (LDM instruction) Next instruction Write data "00000XXX2." (LDM instruction) (b3 in Figure 14.3.3) (b2 to b0 in Figure 14.3.3) Fig. 14.3.4 Procedure for writing data to oscillation circuit control register 1 7735 Group User's Manual 14-3 CLOCK GENERATING CIRCUIT 14.3 Clock control MEMO 14-4 7735 Group User's Manual CHAPTER 15 ELECTRICAL CHARACTERISTICS 15.1 Absolute maximum ratings 15.2 Recommended operating conditions 15.3 Electrical characteristics 15.4 A-D converter characteristics 15.5 Internal peripheral devices 15.6 Ready and Hold 15.7 Single-chip mode 15.8 Memory expansion mode and Microprocessor mode : with no wait 15.9 Memory expansion mode and Microprocessor mode : with wait 1 15.10 Memory expansion mode and Microprocessor mode : with wait 0 15.11 Measuring circuit for ports P0 to P8 and pins 1 and _ E ELECTRICAL CHARACTERISTICS Electrical characteristics of the M37735MHBXXXFP are described in this chapter. For the low voltage version, refer to section "18.4 Electrical characteristics." Concerning chapter "15. ELECTRICAL CHARACTERISTICS," the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter: * "15.6 Ready and Hold" * "15.8 Memory expansion mode and Microprocessor mode : with no wait" * "15.9 Memory expansion mode and Microprocessor mode : with wait 1" * "15.10 Memory expansion mode and Microprocessor mode : with wait 0" The following sections are the same as those of the 7733 Group. Therefore, refer to part 1: * "15.1 Absolute maximum ratings" (page 15-2 in part 1) * "15.2 Recommended operating conditions" (page 15-3 in part 1) * "15.3 Electrical characteristics" (page 15-4 in part 1) * "15.4 A-D converter characteristics" (page 15-5 in part 1) * "15.5 Internal peripheral devices" (page 15-6 in part 1) * "15.7 Single-chip mode" (page 15-13 in part 1) _ * "15.11 Measuring circuit for ports P0 to P8 and pins 1 and E " (page 15-21 in part 1) 15-2 7735 Group User's Manual ELECTRICAL CHARACTERISTICS 15.6 Ready and Hold 15.6 Ready and Hold Timing requirements (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Symbol Parameter Unit Min. Max. tsu(RDY- ) RDY input setup time ns 55 tsu(HOLD- ) HOLD input setup time ns 55 th( -RDY) ns 0 RDY input hold time th( -HOLD) HOLD input hold time ns 0 1 1 1 1 Note: This is applied when the main clock division selection bit = "0" and f(f2) = 12.5 MHz. Switching characteristics (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz, unless otherwise noted) Parameter Symbol td( -HLDA) 1 HLDA output delay time Conditions Fig. 15.11.1 in part 1 7735 Group User's Manual Limits Min. Max. 50 Unit ns 15-3 ELECTRICAL CHARACTERISTICS 15.6 Ready and Hold Ready With no wait 1 WEL, WEH, RDE output RDY input tsu(RDY- 1) th( 1-RDY) With wait 1 WEL, WEH, RDE output RDY input tsu(RDY- 1) th( 1-RDY) Hold 1 tsu(HOLD- 1) th( 1-HOLD) HOLD input td( 1-HLDA) HLDA output Measuring conditions * VCC = 5 V 10 % * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 15-4 7735 Group User's Manual td( 1-HLDA) ELECTRICAL CHARACTERISTICS 15.8 Memory expansion mode and Microprocessor mode : with no wait 15.8 Memory expansion mode and Microprocessor mode : with no wait Timing requirements (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Min. Max. Unit External clock input cycle time (Note 2) tc ns 40 External clock input high-level pulse width (Note 3) tw(H) ns 15 External clock input low-level pulse width (Note 3) tw(L) ns 15 External clock rise time tr ns 8 External clock fall time tf ns 8 Data input setup time tsu(D-RDE) ns 32 Data input hold time th(RDE-D) ns 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 80 ns. 3: When the main clock division selection bit = "1," values of tw (H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) Parameter Symbol td(CS-WE) td(CS-RDE) th(WE-CS) th(RDE-CS) td(An-WE) td(An-RDE) td(A-WE) td(A-RDE) th(WE-An) th(RDE-An) tw(ALE) Chip-select output delay time tsu(A-ALE) Address output setup time th(ALE-A) td(ALE-WE) td(ALE-RDE) td(WE-DQ) Address hold time th(WE-DQ) Data hold time Conditions Data formula (Min.) 1 10 2 * f(f2) 9 - 28 1 10 2 * f(f2) 1 109 2 * f(f2) 1 109 2* f(f2) 1 109 2* f(f2) 1 109 2* f(f2) Address output delay time Address output delay time Address hold time ALE pulse width ALE output delay time Data output delay time ____ 4 ns - 28 12 ns - 28 12 ns - 22 18 ns - 18 22 ns - 35 5 ns 9 ns 4 ns 45 1 109 2 * f(f2) 2 109 2 * f(f2) WEL, WEH pulse width tpxz(RDE-DZ) Floating start delay time tpzx(RDE-DZ) Floating release delay time - 22 18 - 30 50 ____ - 20 ns 20 RDE pulse width tw(RDE) - 32 48 td(RSMP-WE) _____ - 30 10 td(RSMP-RDE) RSMP output delay time _____ th( 1-RSMP) RSMP hold time 0 td(WE- 1) 18 1 output delay time 0 td(RDE- 1) Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: f(f2) represents the clock f 2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 7735 Group User's Manual ns ns 5 1 109 2 * f(f2) 2 109 2 * f(f2) 1 109 2 * f(f2) Unit ns Fig. 15.11.1 in part 1 ____ tw(WE) Max. 12 Chip-select hold time 9 Limits Min. ns ns ns ns ns ns 15-5 ELECTRICAL CHARACTERISTICS 15.8 Memory expansion mode and Microprocessor mode : with no wait Memory expansion mode and Microprocessor mode : With no wait (Wait bit = "1") <<Write>> tw(L) tw(H) tf tr <<Read>> tw(L) tc tw(H) tf tr tc XIN 1 td(WE- td(WE- 1) td(RDE- 1) td(RDE- 1) 1) CS0-CS4 output th(WE-CS) td(CS-WE) Address output A8-A15 (BYTE = "H") A16, A17 td(CS-RDE) th(RDE-CS) Address td(An-WE) tw(ALE) Address th(WE-An) Address td(An-RDE) tw(ALE) td(ALE-WE) th(RDE-An) td(ALE-RDE) ALE output Address/Data output A0/D0-A15/D15 (BYTE = "L") A0/D0-A7/D7 (BYTE = "H") tsu(A-ALE) Address td(A-WE) th(ALE-A) tsu(A-ALE) th(WE-DQ) Data Address Data th(ALE-A) Address td(WE-DQ) tw(WE) td(A-RDE) Address tpzx(RDE-DZ) tpxz(RDE-DZ) WEL output WEH output th(RDE-D) tsu(D-RDE) Data input D0-D15 (BYTE = "L") D0-D7 (BYTE = "H") Data tw(RDE) RDE output td(RSMP-WE) th( td(RSMP-RDE) 1-RSMP) th( 1 -RSMP) RSMP output td(WE-PiQ) Port Pi output (i = 4-8) tsu(PiD-RDE) th(RDE-PiD) Port Pi input (i = 4-8) Measuring conditions (CS0-CS4, A0/D0-A15/D15, A16, A17, ALE, WEL, WEH, RDE, RSMP) Measuring conditions (Ports P4-P8) *VCC = 5 V 10 % : VIL = 1.0 V, VIH = 4.0 V *V CC = 5 V 10 % *Input timing voltage *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Data input 15-6 : V IL = 0.8 V, VIH = 2.5 V 7735 Group User's Manual ELECTRICAL CHARACTERISTICS 15.9 Memory expansion mode and Microprocessor mode : with wait 1 15.9 Memory expansion mode and Microprocessor mode : with wait 1 Timing requirements (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Min. Max. Unit External clock input cycle time (Note 2) tc ns 40 External clock input high-level pulse width (Note 3) tw(H) ns 15 External clock input low-level pulse width (Note 3) tw(L) ns 15 External clock rise time tr ns 8 External clock fall time tf ns 8 Data input setup time tsu(D-RDE) ns 32 Data input hold time th(RDE-D) ns 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 80 ns. 3: When the main clock division selection bit = "1," values of tw (H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) Limits Conditions Parameter Unit Symbol Data formula (Min.) Max. Min. td(CS-WE) 1 109 Chip-select output delay time ns - 28 12 td(CS-RDE) 2 * f(f2) th(WE-CS) Chip-select hold time ns 4 th(RDE-CS) td(An-WE) 1 109 Address output delay time - 28 ns 12 td(An-RDE) 2* f(f2) 9 td(A-WE) 1 10 - 28 ns Address output delay time 12 td(A-RDE) 2* f(f2) th(WE-An) 1 109 - 22 ns Address hold time 18 th(RDE-An) 2 f(f2) * tw(ALE) ALE pulse width tsu(A-ALE) Address output setup time th(ALE-A) td(ALE-WE) td(ALE-RDE) td(WE-DQ) Address hold time th(WE-DQ) ALE output delay time Data output delay time Fig. 15.11.1 in part 1 WEL, WEH pulse width tpxz(RDE-DZ) Floating start delay time ns 5 ns 9 ns 4 ns 45 1 10 - 22 2* f(f2) 4 109 - 30 2* f(f2) ____ tw(WE) 22 9 Data hold time ____ tpzx(RDE-DZ) 1 109 - 18 2* f(f2) 1 109 - 35 2* f(f2) ns 18 ns 130 5 1 109 - 20 2* f(f2) 9 4 10 - 32 2* f(f2) 9 1 10 2* f(f2) - 30 Floating release delay time ____ 20 RDE pulse width tw(RDE) 128 _____ td(RSMP-WE) RSMP output delay time 10 td(RSMP-RDE) _____ RSMP hold time th( 1-RSMP) 0 td(WE- 1) 18 1 output delay time 0 td(RDE- 1) Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: f(f2) represents the clock f 2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 7735 Group User's Manual ns ns ns ns ns ns ns 15-7 ELECTRICAL CHARACTERISTICS 15.9 Memory expansion mode and Microprocessor mode : with wait 1 Memory expansion mode and Microprocessor mode : When external memory area is accessed With wait 1 (Wait bit = "0" and Wait selection bit = "1") <<Write>> tw(L) <<Read>> tw(H) tf tr tw(L) tc tw(H) tf tr tc XIN 1 td(WE- td(WE- 1) 1) td(RDE- td(RDE- 1) 1) CS0-CS4 output td(CS-WE) Address output A8-A15 (BYTE = "H") A16, A17 Address td(An-WE) tw(ALE) th(WE-CS) td(CS-RDE) Address th(WE-An) Address th(RDE-CS) Address th(RDE-An) td(An-RDE) tw(ALE) td(ALE-RDE) td(ALE-WE) ALE output Address/Data output A0/D0-A15/D15 (BYTE = "L") A0/D0-A7/D7 (BYTE = "H") tsu(A-ALE) Address td(A-WE) th(ALE-A) th(WE-DQ) Data td(WE-DQ) tw(WE) th(ALE-A) tsu(A-ALE) Address Address td(A-RDE) Address tpzx(RDE-DZ) tpxz(RDE-DZ) WEL output WEH output th(RDE-D) tsu(D-RDE) Data input D0-D15 (BYTE = "L") D0-D7 (BYTE = "H") Data tw(RDE) RDE output td(RSMP-WE) th( td(RSMP-RDE) 1-RSMP) th( 1-RSMP) RSMP output td(WE-PiQ) Port Pi output (i = 4-8) tsu(PiD-RDE) th(RDE-PiD) Port Pi input (i = 4-8) Measuring conditions (CS0-CS4, A0/D0-A15/D15, A16, A17, ALE, WEL, WEH, RDE, RSMP) Measuring conditions (Port P4-P8) *VCC = 5 V 10 % : VIL = 1.0 V, VIH = 4.0 V *VCC = 5 V 10 % *Input timing voltage *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Data input 15-8 : V IL = 0.8 V, VIH = 2.5 V 7735 Group User's Manual ELECTRICAL CHARACTERISTICS 15.10 Memory expansion mode and Microprocessor mode : with wait 0 15.10 Memory expansion mode and Microprocessor mode : with wait 0 Timing requirements (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Min. Max. Unit External clock input cycle time (Note 2) tc ns 40 External clock input high-level pulse width (Note 3) tw(H) ns 15 External clock input low-level pulse width (Note 3) tw(L) ns 15 External clock rise time tr ns 8 External clock fall time tf ns 8 Data input setup time tsu(D-RDE) ns 32 Data input hold time th(RDE-D) ns 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 80 ns. 3: When the main clock division selection bit = "1," values of tw (H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) Parameter Symbol td(CS-WE) td(CS-RDE) th(WE-CS) th(RDE-CS) td(An-WE) td(An-RDE) td(A-WE) td(A-RDE) th(WE-An) th(RDE-An) tw(ALE) Chip-select output delay time tsu(A-ALE) Address output setup time th(ALE-A) td(ALE-WE) td(ALE-RDE) td(WE-DQ) Address hold time th(WE-DQ) Data formula (Min.) 3 109 2* f(f2) Address output delay time Address output delay time Address hold time ALE pulse width ALE output delay time Data output delay time Fig. 15.11.1 in part 1 1 10 2* f(f2) 4 109 2* f(f2) ____ WEL, WEH pulse width tpxz(RDE-DZ) Floating start delay time Max. 4 ns - 33 87 ns - 45 75 ns - 22 18 ns - 23 57 ns - 35 45 ns - 25 15 ns - 30 10 ns Floating release delay time ____ 18 ns - 30 130 ns - 20 20 RDE pulse width - 32 tw(RDE) 128 _____ td(RSMP-WE) RSMP output delay time - 30 10 td(RSMP-RDE) _____ RSMP hold time td( 1-RSMP) 0 td(WE- 1) 18 1 output delay time 0 td(RDE- 1) Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: f(f2) represents the clock f 2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1. 7735 Group User's Manual ns - 22 5 1 109 2* f(f2) 4 109 2* f(f2) 1 109 2* f(f2) Unit ns 45 9 Data hold time tw(WE) 3 109 2* f(f2) 3 109 2* f(f2) 1 109 2* f(f2) 2 109 2* f(f2) 2 109 2* f(f2) 1 109 2* f(f2) 1 109 2* f(f2) Limits Min. 87 - 33 Chip-select hold time ____ tpzx(RDE-DZ) Conditions ns ns ns ns ns ns 15-9 ELECTRICAL CHARACTERISTICS 15.10 Memory expansion mode and Microprocessor mode : with wait 0 Memory expansion mode and Microprocessor mode : When external memory area is accessed with wait 0 (Wait bit = "0" and Wait selection bit = "0") <<Write>> tw(L) <<Read>> tw(H) tf tr tw(L) tc tw(H) tf tr tc XIN 1 td(WE- td(WE- 1) td(RDE- 1) td(RDE- 1) 1) CS0-CS4 output Address output A8-A15 (BYTE = "H") A16, A17 td(CS-WE) th(WE-CS) td(CS-RDE) Address td(An-WE) Address th(WE-An) tw(ALE) th(RDE-CS) th(RDE-An) td(An-RDE) tw(ALE) td(ALE-WE) td(ALE-RDE) ALE output Address/Data output A0/D0-A15/D15 (BYTE = "L") A0/D0-A7/D7 (BYTE = "H") tsu(A-ALE) th(ALE-A) tsu(A-ALE) th(WE-DQ) Address Data Data td(WE-DQ) tw(WE) td(A-WE) th(ALE-A) Address td(A-RDE) Address tpxz(RDE-DZ) tpzx(RDE-DZ) WEL output WEH output tsu(D-RDE) Data input D0-D15 (BYTE = "L") D0-D7 (BYTE = "H") th(RDE-D) Data tw(RDE) RDE output td(RSMP-WE) th( td(RSMP-RDE) 1-RSMP) th( 1-RSMP) RSMP output td(WE-PiQ) Port Pi output (i = 4-8) tsu(PiD-RDE) Port Pi input (i = 4-8) Measuring conditions (CS0-CS4, A0/D0-A15/D15, A16, A17, ALE, WEL, WEH, RDE, RSMP) Measuring conditions (Ports P4-P8) *VCC = 5 V 10 % *VCC = 5 V 10 % *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Data input 15-10 : V IL = 0.8 V, VIH = 2.5 V 7735 Group User's Manual th(RDE-PiD) CHAPTER 16 STANDARD CHARACTERISTICS 16.1 Standard characteristics STANDARD CHARACTERISTICS Concerning chapter "16. STANDARD CHARACTERISTICS," the 7735 Group is the same as the 7733 Group. Therefore, for this chapter, refer to part 1: * "16 STANDARD CHARACTERISTICS" (part 1) 16-2 7735 Group User's Manual CHAPTER 17 APPLICATIONS 17.1 17.2 17.3 17.4 17.5 Memory expansion Serial I/O Watchdog timer Power saving Timer B APPLICATIONS 17.1 Memory expansion Concerning chapter "17. APPLICATIONS," the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter: * "17.1 Memory expansion" * "17.4 Power saving" The following sections of the 7735 Group are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1: * "17.2 Serial I/O" (page 17-28 in part 1) * "17.3 Watchdog timer" (page 17-41 in part 1) * "17.5 Timer B" (page 17-54 in part 1) 17.1 Memory expansion Memory * I/O expansion examples of the M37735MHBXXXFP are described below. * For functions and operations of pins used in memory * I/O expansion, refer to chapter "12. CONNECTING EXTERNAL DEVICES." * For timing characteristics, refer to chapter "15. ELECTRICAL CHARACTERISTICS." 17.1.1 Memory expansion model Memory expansion to the external is available in the memory expansion or microprocessor mode. In the M37735MHBXXXFP, the desired memory expansion model can be selected from two models listed in Table 17.1.1. This selection depends on the level of the external data bus width selection signal (BYTE). (1) 8-bit external data bus model The external data bus is 8 bits wide and the accessible area can be expanded up to 1 Mbytes. The low-order 8 bits of the external address bus (A7 to A 0) are multiplexed with the external data bus. Therefore, one 8-bit address latch is necessary in order to latch A7 to A0 . (2) 16-bit external data bus model The external data bus is 16 bits wide and the accessible area can be expanded up to 1 Mbytes. The low-order 16 bits of the external address bus (A15 to A 0) are multiplexed with the external data bus. Therefore, two 8-bit address latches are necessary in order to latch A 7 to A 0 and A 15 to A 8. 17-2 7735 Group User's Manual APPLICATIONS 17.1 Memory expansion Table 17.1.1 Memory expansion models M37735MHBXXXFP 16 + n n P0 8 bits wide BYTE P2 BYTE = "H" External data bus P1 A0 to A15+n 8 Latch D Q E 8 ALE 8 D0 to D7 (n 2) M37735MHBXXXFP BYTE 16 bits wide BYTE = "L" P0 n Latch P1 D Q E P2 D Q E ALE Latch 16 + n A0 to A15+n 8 8 16 D0 to D15 (n 2) For functions and operations of pins used in memory expansion, refer to chapter "12. CONNECTING EXTERNAL DEVICES." For timing characteristics, refer to chapter "15. ELECTRICAL CHARACTERISTICS." In memory expansion, the address bus can be expanded up to 18 bits wide. Accordingly, be sure to strengthen the 7735 Group's Vss line on the system. (Refer to section "Appendix 8. Countermeasure examples against noise.") 7735 Group User's Manual 17-3 APPLICATIONS 17.1 Memory expansion 17.1.2 Calculation ways for timing When expanding memory, use a memory of which specifications satisfy the following timing requirements: address access time (t a(AD)) and data setup time for writing data (t su(D)). Calculation ways for t a(AD) and tsu(D) are described below. Address access time of external memory [t a(AD)] t a(AD) = t d(A-RDE) + tw(RDE) - t su(D-RDE) - (address decode time1 + address latch delay time2) address decode time1: time necessary for validating a chip select signal after an address is decoded address latch delay time2 : delay time necessary for latching an address Data setup time of external memory for writing data [t su(D)] t su(D) = t w(WE) - t d(WE-DQ) Table 17.1.2 lists the calculation formulas and constants for each parameter in the above formulas. Figure 17.1.1 shows bus timing diagrams. Table 17.1.2 Calculation formulas and constants for each parameter (Unit: ns) Software wait Wait bit Wait selection bit td(A-RDE) tw(RDE) tw(WE) Wait 1 0 1 No wait 1 0 or 1 3 10 9 - 45 2 *f(f2) 1 10 9 - 28 2 *f(f2) 2 10 9 - 32 2 *f(f2) 2 10 9 - 30 2 *f(f2) tsu(D-RDE) td(WE-DQ) Wait 0 0 0 4 10 9 - 30 2 *f(f2) 4 10 9 - 30 2 *f(f2) 32 45 Wait bit: Bit 2 at address 5E 16 Wait selection bit: Bit 0 at address 5F16 Note: The above is applied when the system clock selection bit (bit 3 at address 6C16 ) = "0." 17-4 7735 Group User's Manual APPLICATIONS 17.1 Memory expansion When BYTE = "H" (External data bus = 8 bits wide) td(CS-RDE) td(CS-WE) CS4 to CS0 tw(ALE) ALE td(ALE-RDE) Port P0 (A16, A17) High-order address High-order address td(An-RDE) Port P1 (A8 to A15) Middle-order address AAAAAA AAAAAA AAAAAA td(An-RDE) Port P2 (A0/D0 to A7/D7) External memory's output data Low-order address tsu(A-ALE) ta(AD) Middle-order address Low-order address Data td(WE-DQ) tsu(D-RDE) tsu(D) tw(RDE) RDE tw(WE) WEL, WEH When data is read When data is written When BYTE = "L" (External data bus = 16 bits wide) td(CS-RDE) td(CS-WE) CS4 to CS0 tw(ALE) ALE td(ALE-RDE) Port P0 (A16, A17) High-order address AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA td(An-RDE) Port P1 (A8/D8 to A15/D15) Middle-order address External memory's output data tsu(A-ALE) Port P2 (A0/D0 to A7/D7) High-order address Middle-order address td(WE-DQ) tsu(D-RDE) Low-order address External memory's output data tsu(A-ALE) Data (odd address) Low-order address tsu(D-RDE) Data (even address) td(WE-DQ) tsu(D) ta(AD) tw(RDE) RDE tw(WE) WEL, WEH When data is read : Specifications of the 7735 Group When data is written (The others are specifications of external memory.) Fig. 17.1.1 Bus timing diagrams 7735 Group User's Manual 17-5 APPLICATIONS 17.1 Memory expansion Figure 17.1.2 shows the relationship between ta(AD), t su(D) and the system clock frequency. For t a(AD) in Figure 17.1.2, an address decode time and an address latch delay time are not considered. The actual ta(AD) is a value obtained by subtracting the above times from the value shown in Fig.17.1.2. [ns] 1000 891 Address access time ta(AD) 900 668 700 622 591 533 600 527 463 500 400 No wait Wait 1 is valid. Wait 0 is valid. 766 800 47 4 408 429 391 362 336 324 283 241 300 208 180 200 100 357 292 265 328 302 279 259 241 224 220 202 209 195 182 171 185 171 158 158 146 138 135 125 122 108 116 108 95 84 74 65 58 50 44 38 33 28 241 0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 [ MHz] System clock (Main clock) frequency f(XIN) Address decode time and address latch delay time are not considered. [ns] 496 Data setup time tsu(D) 500 425 369 400 No wait Wait 1 or Wait 0 is valid. 325 288 300 258 232 210 200 175 147 100 125 106 91 78 210 191 175 160 147 135 125 115 106 98 67 58 50 42 36 30 25 20 15 11 91 85 8 5 14 24 25 0 7 8 9 10 11 12 13 15 16 17 18 19 System clock (Main clock) frequency f(XIN) Fig. 17.1.2 Relationship between ta(AD), tsu (D) and f(XIN) 17-6 7735 Group User's Manual 20 21 22 23 [MHz] APPLICATIONS 17.1 Memory expansion 17.1.3 Points in memory expansion (1) Timing for reading data Figure 17.1.3 shows the timing at which data is read from an external memory. When data is read, the external data bus enters a floating state and reads data from an external memory. The floating state of the external data bus is retained from when an interval of t pxz(RDE-DZ) ____ has passed after signal RDE's falling edge until an interval of tpzx(RDE-DZ) has passed after signal ____ RDE's rising edge. tpxz(RDE-DZ) is a constant which is independent of f(XIN); tpzx(RDE-DZ) is a constant which is dependent on f(X IN). Table 17.1.3 lists the value of tpxz(RDE-DZ) and the calculation formula for t pzx(RDE-DZ). Note that the external data bus is multiplexed with the external address bus. Therefore, when reading data, it is necessary to consider timing to avoid collision between data being read-in and an address which is output preceding or following the data. (Refer to "(3) Precautions on memory expansion.") tw(RDE) RDE External memory output enable signal (Read signal) External memory chip select signals Address output A0/D0 to A7/D7 A8/D8 to A15/D15 OE CE, S tpxz(RDE-DZ) ta(OE) 1 tpzx(RDE-DZ) Address Address ta(CE), ta(S) 2 ten(OE) tDF, tdis(OE) ten(CE), ten(S) External memory data output 3 Data tsu(D-RDE) 1 This is applied when the external data bus = 16 bits wide (BYTE = "L"). : Specifications of the 7735 Group (The others are specifications of external memory.) 2 When the external memory's specifications are smaller than tpxz(RDE-DZ), there is a possibility that the tail of an address collides with the head of data. Refer to "(3) Precautions on memory expansion." 3 When the external memory's specifications are greater than tpzx(RDE-DZ), there is a possibility that the tail of data collides with the head of an address. Refer to "(3) Precautions on memory expansion." Fig. 17.1.3 Timing at which data is read from external memory 7735 Group User's Manual 17-7 APPLICATIONS 17.1 Memory expansion Table 17.1.3 Value of tpxz(RDE-DZ) and calculation formula for tpzx(RDE-DZ) (Unit: ns) Software wait Wait bit Wait selection bit t pxz(RDE-DZ) t pzx(RDE-DZ) No wait 1 0 or 1 Wait 1 0 1 5 1 10 9 - 20 2 *f(f2) Wait 0 0 0 Wait bit: Bit 2 at address 5E 16 Wait selection bit: Bit 0 at address 5F16 Note: The above is applied when the system clock selection bit (bit 3 at address 6C16 ) = "0." 17-8 7735 Group User's Manual APPLICATIONS 17.1 Memory expansion (2) Timing for writing data Figure 17.1.4 shows the timing for writing data to an external memory. passed after signal When data is written, the data is output from when an interval of td( WE-DQ) has ____ ____ ____ ____ WEL/WEH's falling edge until an interval of th (WE-DQ) has passed after signal WEL/WEH's rising edge. td(WE-DQ) is a constant which is independent of f(XIN); th(WE-DQ) is a constant which is dependent on f(XIN ). Table 17.1.4 lists the value of td (WE-DQ ) and the calculation formula for t h (WE-DQ ). Make sure that the data output timing for writing data satisfies the following specifications of the external memory: data setup time (t su(D)) and data hold time (t h (D)) for writing data. tw(WE) WEL, WEH External memory write signals W, WE External memory chip select signals CE, S td(WE-DQ) th(WE-DQ) Address and data output A0/D0 to A7/D7 A8/D8 to A15/D15 Address Data tsu(D) Address th(D) : Specifications of the 7735 Group This is applied when the external data bus = 16 bits wide (BYTE = "L" ). (The others are specifications of external memory.) Fig. 17.1.4 Timing at which data is written to external memory Table 17.1.4 Value of td(WE-DQ) and calculation formula for th(WE-DQ) (Unit: ns) No wait Wait 1 Software wait 1 0 Wait bit 0 or 1 1 Wait selection bit Wait 0 0 0 45 td(WE-DQ) th(WE-DQ) 1 10 9 - 22 2*f(f2) Wait bit: Bit 2 at address 5E16 Wait selection bit: Bit 0 at address 5F 16 Note: The above is applied when the system clock selection bit (bit 3 at address 6C16) = "0." 7735 Group User's Manual 17-9 APPLICATIONS 17.1 Memory expansion (3) Precautions on memory expansion When specifications of the 7735 Group do not match those of an external memory as described in the following to , some considerations about the circuit are necessary: When using an external memory which requires a long address access time (ta(AD)) ____ When using an external memory which outputs data within an interval of tpxz(RDE-DZ) after signal RDE's falling edge When using____ an external memory which outputs data for more than an interval of tpzx(RDE-DZ) after signal RDE's rising edge When using an external memory which requires a long address access time (ta(AD)) When an external memory requires a long address access time (ta(AD)) which does not satisfy the 7735 Group's t su(D-RDE), try to lower f(X IN) or extend a bus cycle by inserting a wait. There are two methods for insertion of a wait: the software wait and the ready function. For the software wait, refer to section "12.2 Software wait"; for the ready function, refer to section "12.3 Ready function." Wait 1 (Software wait) ____ ____ ____ Insert a wait equivalent to one cycle of clock 1 while signal RDE/ WEL/ WEH is at "L"-level. Wait 0 (Software wait) ____ ____ ____ Insert a wait equivalent to one cycle of clock 1 while signal RDE/ WEL/ WEH is at "H"- and "L"levels. Ready function Insert a wait in an arbitrary duration. Figure 17.1.5 shows a ready generating____ circuit example (with no wait). In Figure 17.1.5, when f(X IN) > 20.7 MHz, the setup time for the RDY input (t su(RDY-1)) is insufficient. In this case, refer to the ready generating circuit example (with wait 1) shown in Figure 17.1.6. In Figure 17.1.6, t su(RDY-1) is satisfied when f(X IN) 25 MHz. Note that a wait generated by the ready function is also valid for the access to the internal area. Therefore, in Figures 17.1.5 and 17.1.6, areas where the wait _____ is inserted are specified by using signals RSMP and CS0. For circuits where the software wait is used, refer to Figures 17.1.2 to 17.1.5. 17-10 7735 Group User's Manual APPLICATIONS 17.1 Memory expansion M37735MHBXXXFP CS0 CS0 AC32 RSMP Wait generated by the ready function is inserted only to an area where accessed by signal CS2. RDY Circuit conditions: f(XIN) 21.3 MHz, no wait, 1= f(XCIN) f(XIN) f(XIN) f(XIN) or 8 , 16 , 2 2 , Condition to satisfy the relationship of t su(RDY- 1) 55 ns is t c+td(RSMP-RDE) 63.5 ns. Accordingly, when f(XIN) 21.3 MHz, this example satisfies the relationship of tsu(RDY- 1) 55 ns. td(RDE- 1) tc 1 RDE CS0 td(RSMP-RDE) RSMP RDY tsu(RDYPropagation delay time of AC32 (Max.: 8.5 ns) 1) : Wait generated by the ready function Fig. 17.1.5 Ready generating circuit example (with no wait) 7735 Group User's Manual 17-11 APPLICATIONS 17.1 Memory expansion M37735MHBXXXFP CS0 CS0 HC32 RSMP Wait generated by the ready function is inserted only to an area where accessed by signal CS2. RDY Circuit conditions: f(XIN) 25 MHz, wait 1 is valid, 1= f(XIN) f(XIN) f(XIN) f(XCIN) or 8 , 16 , 2 , 2 Make sure that the propagation delay time is within 9 3 10 + td(RSMP-RDE) - tsu(RDY- 1 ) f(XIN) (when f(XIN) = 25 MHz, 75 ns). td(RDE- 1) 1 RDE td(RSMP-RDE) CS0 RSMP RDY Propagation delay time of HC32 tsu(RDY- 1) th( 1-RDY) : Software wait : Wait generated by the ready function Fig. 17.1.6 Ready generating circuit example (with wait 1) 17-12 7735 Group User's Manual APPLICA TIONS 17.1 Memory expansion When using an external memory which outputs data within an interval of t pxz(RDE-DZ) after signal ____ RDE's falling edge When there is a possibility that the tail of an address collides with the head of data because the ____ external memory outputs data within an interval of t pxz(RDE-DZ) after signal RDE's falling edge, delay ____ only the signal RDE's front falling edge and realize the relationship of t pxz(RDE-DZ)-d < ten(OE) . In____ this ___ case, the falling edge of the read signal ( OE) for the memory, which is generated from signal RDE , is delayed. (Refer to Figure 17.1.7.) RDE External memory output enable signal (Read signal) d OE tpxz(RDE-DZ) Address output Address External memory data output Address Data ta(OE) ten(OE) Note: When ten(OE) tpxz(RDE-DZ)(= 5 ns), make sure that signal RDE's falling edge precedes signal OE's falling edge (Refer to "d") and the relationship of tpxz(RED-DZ)-d ten(OE) is realized. Fig. 17.1.7 Timing example when data output is delayed 7735 Group User's Manual 17-13 APPLICATIONS 17.1 Memory expansion When using ____ an external memory which outputs data for more than an interval of t pzx(RDE-DZ) after signal RDE's rising edge When there is a possibility that the tail of data collides with the head of an address because the ____ external memory outputs the data for more than an interval of t pzx(RDE-DZ) after signal RDE's rising edge, try to carry out the following: By using bus buffers and others, delete the tail of data which is output from the memory. Use a memory which is made by MITSUBISHI ELECTRIC CORPORATION and can be connected without bus buffers. Figures 17.1.8 to 17.1.11 show bus buffer usage examples and the corresponding timing diagrams. Table 17.1.5 lists memories which can be connected without bus buffers (made by MITSUBISHI ELECTRIC CORPORATION). The reason why these memories do not need buffers is that timing parameters tDF or tdis(OE) is guaranteed. (Make sure that the read signal rises within 5 ns after signal ____ RDE's rising edge.) Table 17.1.5 Memories which can be connected without bus buffers (made by MITSUBISHI ELECTRIC CORPORATION) Memory EPROM One time PROM Frash memory SRAM Type M5M27C256AK-85, -10, -12, -15 M5M27C512AK-10, -12, -15 M5M27C100K-12, -15 tDF/tdis(OE) (Max.) Usage condition 15 ns (When guaranteed as kit) (Note) 2 * f(f2) 20 MHz 8 ns 10 ns 6 ns 2 * f(f2) 25 MHz M5M27C101K-12, -15 M5M27C102K-12, -15 M5M27C201K, JK-10, -12, -15 M5M27C202K, JK-10, -12, -15 M5M27C256AP, FP, VP, RV-12, -15 M5M27C512AP, FP-15 M5M27C100P-15 M5M27C101P, FP, J, VP, RV-15 M5M27C102P, FP, J, VP, RV-15 M5M27C201P, FP, J, VP, RV-12, -15 M5M27C202P, FP, J, VP, RV-12, -15 M5M28F101P, FP, J, VP, RV-10, -12, -15 M5M28F102FP, J, VP, RV-10, -12, -15 M5M5256CP, FP, KP, VP, RV-55LL, -55XL, -70LL, -70XL, -85LL, -85XL, -10LL, -10XL M5M5278CP, FP, J-20, -20L M5M5278CP, FP, J-25, -25L M5M5278DP, J-12 M5M5278DP, FP, J-15, -15L M5M5278DP, FP, J-20, -20L 7 ns 8 ns Note: Specifications of the above memories are available if a comment "tDF/tdis = 15 ns, microcomputer and kit" is added. 17-14 7735 Group User's Manual APPLICATIONS 17.1 Memory expansion M37735MHBXXXFP Address bus A16, A17 CNVSS ALS573 BYTE D Q E OC ALS573 D Q ALE E OC F245 A8/D8 to A15/D15 B 1 A Data bus (odd) DIR OC F245 A0/D0 to A0/D7 B 1 Data bus (even) A DIR OC F11 2 XIN RDE RD WEH WO WEL WE XOUT 25 MHz Circuit conditions: Wait 1 is valid, 1= 1, 2 f(XIN) f(XIN) f(XIN) 8 , 16 2 , , or f(XCIN) 2 , Make sure that the following relationships are satisfied: The sum of output disable time of 1 and propagation delay time of 2 is 20 ns or less. The sum of output enable time of 1 and propagation delay time of 2 is 5 ns or more. Fig. 17.1.8 Bus buffer usage example (1) 7735 Group User's Manual 17-15 APPLICATIONS 17.1 Memory expansion <At reading> 128 (min.) RDE A0/D0 to A7/D7 A8/D8 to A15/D15 20 (min.) 5 (max.) A A F11 (tPHL) F11 (tPLH) OC F245 (tPZH/tPZL) Data output (B) from external memory F245 (tPHZ/tPLZ) D <At writing> 130 (min.) WEH, WEL A0/D0 to A7/D7 A8/D8 to A15/D15 45 (max.) D A A F11 (tPLH) OC F245 (tPHL/tPLH) Data output (A) to external memory F245 (tPHZ/tPLZ) D (Unit: ns) Fig. 17.1.9 Timing diagram for bus buffer usage example (1) 17-16 7735 Group User's Manual APPLICATIONS 17.1 Memory expansion M37735MHBXXXFP A16, A17 Address bus CNVSS ALS573 BYTE D Q E OC ALS573 D Q E OC ALE ALS245A 2 A8/D8 to A15/D15 B A Data bus (odd) DIR OC ALS245A 2 A0/D0 to A7/D7 B Data bus (even) A DIR OC These circuits make the rising edge of the write signal earlier by 1/2 1, so that the write hold time is extended. F04 1 1D 1Q 2D 1T 2T 2Q F74 F11 1 RDE RD WEH WO WEL WE F32 XIN XOUT 16 MHz Circuit conditions: Wait 1 is valid, 1= f(XIN) f(XIN) f(XIN) or 2 , 8 , 16 , f(XCIN) 2 1 Make sure that the propagation delay time is 20 ns or less. 1, 2 Make sure that the following relationships are satisfied: The sum of propagation delay time of 1 and output disable time of 2 is 42.5 ns or less. The sum of propagation delay time of 1 and output enable time of 2 is 5 ns or more. Fig. 17.1.10 Bus buffer usage example (2) (when a memory which requires a long data hold time for writing is connected) 7735 Group User's Manual 17-17 APPLICATIONS 17.1 Memory expansion <At reading> 218(min.) RDE F11 (tPLH) F11 (tPHL) OC A0/D0 to A7/D7 A8/D8 to A15/D15 42.5 (min.) 5 (max.) A A ALS245A (tPZH/tPZL) ALS245A (tPHZ/tPLZ) Data output B from external memory D <At writing> 1 220(min.) WEL, WEH F11(tPLH) OC 1Q F04 (tPHL)+F74 (tPLH) 2Q F32(tPLH) WO, WE 45 (max.) A0/D0 to A7/D7 A8/D8 to A15/D15 D A ALS245A (tPHL/tPLH) Data output A to external memory ALS245A (tPHZ/tPLZ) D Write hold time (Unit: ns) Fig. 17.1.11 Timing diagram for bus buffer usage example (2) 17-18 7735 Group User's Manual APPLICATIONS 17.1 Memory expansion 17.1.4 Memory expansion example Figure 17.1.12 shows a memory expansion example (with one 128-Kbyte ROM and two 32-Kbyte SRAMs, microprocessor mode). Figure 17.1.13 shows the corresponding timing diagram. M37735MHBXXXFP CNVSS BYTE M5M5256P-15 M5M27C102K-15 Address bus A16 CS1 CS2 AC573 A0/D0 to A7/D7 S CE S D Q A0 to A15 E ALE A0 to A14 A1 to A16 A1 to A15 A0 to A14 A1 to A15 E A8/D8 to A15/D15 D8 to D15 D0 to D15 D Q D0 to D15 D0 to D7 DQ1 to DQ8 DQ1 to DQ8 AC573 Data bus OE OE W OE W Data bus (odd) Data bus (even) RDE WEL WEH XIN RD WE WO XOUT Memory map 000016 008016 25 MHz Circuit conditions: Wait 0 is valid, f(XIN) f(XIN) f(XIN) 1= 8 , 16 , 2 , or f(XCIN) 2 Make sure that the propagation delay time is 33 ns or less. 087F16 SFR area Internal RAM area Not used 800016 External ROM area 1FFFF1 (M5M27C102K-15) 4000016 Not used 4FFFF16 External RAM area (M5M5256P-15 2) Fig. 17.1.12 ROM and SRAM expansion example 7735 Group User's Manual 17-19 APPLICATIONS 17.1 Memory expansion <At reading> 128 (min.) RDE, OE A16 A A 75(min.) 5 (max.) A A A0/D0 to A15/D15 20 (min.) AC573 (tPHL) CE, S, CS1, CS2 Address output (A0 to A15) to external memory A ta (S) ta (OE) External Memory data output D ta (A), ta(AD) tsu (D-RDE) 15 (max.) (Guaranteed as kit.) <At wriring> 130 (min.) WEL, WEH, W tsu (D) 75(min.) A0/D0 to A15/D15 A D A 45 (max.) S, CS2 (Unit: ns) Fig. 17.1.13 Timing diagram for ROM and SRAM expansion example 17-20 7735 Group User's Manual APPLICATIONS 17.1 Memory expansion 17.1.5 I/O expansion example I/O expansion is realized with the memory-mapped method. The method and points in I/O expansion are the same as those in memory expansion. Figure 17.1.15 shows a port expansion example using the M5M81C55P-2. In this example, the M5M81C55P2 is connected to the external data bus and programmable I/O ports expand by 22 bits. A reset signal for __ an external device is supplied from port P43 and IO/M is supplied from port P44 . Note that, when f(X IN) > 10 MHz, bus buffer ALS245A or others is necessary. M37735MHBXXXFP M5M81C55P-2 CNVss CS1 I/O CE Port C BYTE Port B ALE ALE Port A A0/D0 to A7/D7 XIN AD0 to AD7 WEL WR RDE RD P43 RESET P44 IO/M XOUT 10 MHz Circuit condition: Wait 0 is valid. Fig. 17.1.14 Port expansion example where M5M81C55P-2 is used 7735 Group User's Manual 17-21 APPLICATIONS 17.4 Power saving Concerning section "17.4 Power saving," the 7735 Group differs from the 7733 Group in the following: * Bit 3 of the oscillation circuit control register 1 (address 6F16) must be fixed to "0." * External bus pins' functions for ports P0 to P3 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "17.4 Power saving" (page 17-44 in part 1) 17-22 7735 Group User's Manual CHAPTER 18 LOW VOLTAGE VERSION 18.1 18.2 18.3 18.4 18.5 18.6 Performance overview Pin configuration Functional description Electrical characteristics Standard characteristics Applications LOW VOLTAGE VERSION 18.1 Performance overview Concerning chapter "18. LOW VOLTAGE VERSION," the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter: * "18.1 Performance overview" * "18.2 Pin configuration" * "18.3 Functional description" * "18.4 Electrical characteristics" * "18.6 Applications" The following section is the same as that of the 7733 Group. Therefore, refer to part 1: * "18.5 Standard characteristics" (page 18-27 in part 1) 18.1 Performance overview Concerning section "18.1 Performance overview," the 7735 Group differs from the 7733 Group in the following: * Description of the memory expansion in Table 18.1.1 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "18.1 Performance overview" (page 18-3 in part 1.) Table 18.1.1 M37735MHLXXXHP performance overview Items Memory expansion 18-2 Performance Possible (Maximum of 1 Mbytes) 7735 Group User's Manual LOW VOLTAGE VERSION 18.2 Pin configuration 18.2 Pin configuration P67/TB2IN/ SUB P70/AN 0 P71/AN 1 P72/AN 2/C TS2 P73/AN 3/C LK2 P74/AN 4/R xD2 P75/AN 5/ADTR G/TxD2 P76/AN 6/XC O U T P77/AN 7/XC IN VSS AVSS VR EF AVC C VC C P8 0/C TS0/R TS0/C LKS1 P8 1/C LK0 P8 2/RXD0/C LKS0 P8 3/TXD0 P84/C TS1/R TS1 P8 5/C LK1 Figure 18.2.1 shows the M37735MHLXXXHP pin configuration. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 6 7 8 9 10 11 12 13 14 15 16 17 M 37735M H LXXXH P P6 6/TB1IN P6 5/TB0IN P6 4/IN T2 P6 3/IN T1 P6 2/IN T0 P6 1/TA4IN P6 0/TA4 OUT P5 7/TA3IN/KI3 P5 6/TA3O U T/KI2 P5 5/TA2IN/KI1 P5 4/TA2O U T/KI0 P5 3/TA1IN P52 /TA1OUT P51/TA0 IN P50/ TA0OUT P4 7 P4 6 P4 5 P4 4 P4 3 56 55 54 53 52 51 50 49 48 47 46 45 44 18 43 19 42 20 41 P8 6/RxD1 P8 7/Tx D1 P0 0/C S0 P0 1/C S1 P0 2/C S2 P0 3/C S3 P0 4/C S4 P0 5/R SM P P0 6/A16 P0 7/A17 P1 0/A8/D8 P11/A9/D9 P12/A10 /D10 P13/A11 /D11 P14/A12 /D12 P15/A13 /D13 P16/A14 /D14 P17/A15 /D15 P20/A0/D0 P21/A1/D1 P42/ 1 P41/R D Y P40/H O LD BYTE C N VSS R ESET XIN XO U T E/R D E VSS P33/H LD A P32/ALE P31/W EH P30/W EL P27/A7/D7 P26/A6/D6 P25/A5/D5 P24/A4/D4 P23/A3/D3 P22/A2/D2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Outline 80P6D-A Fig. 18.2.1 M37735MHLXXXHP pin configuration (Top view) 7735 Group User's Manual 18-3 LOW VOLTAGE VERSION 18.3 Functional description 18.3 Functional description The M37735MHLXXXHP has the same functions as the M37735MHBXXXFP except for the power-on reset conditions. For power-on reset conditions, refer to section "18.3.1 Power-on reset conditions" in part 1. For the other functions, refer to the following: PART 1. 7733 GROUP * "4. INTERRUPTS" * "5. KEY INPUT INTERRUPT FUNCTION" * "6. TIMER A" * "7. TIMER B" * "8. SERIAL I/O" * "9. A-D CONVERTER" PART 2. 7735 GROUP * "2. CENTRAL PROCESSING UNIT (CPU)" * "3. PROGRAMMABLE I/O PORTS" * "10. WATCHDOG TIMER" * "11. STOP AND WAIT MODES" * "12. CONNECTING EXTERNAL DEVICES" * "13. RESET" * "14. CLOCK GENERATING CIRCUIT" 18-4 7735 Group User's Manual LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4 Electrical characteristics Concerning section "18.4 Electrical characteristic," the 7735 Group differs from the 7733 Group in the following sections: * "18.4.6 Ready and Hold" * "18.4.8 Memory expansion mode and Microprocessor mode : with no wait" * "18.4.9 Memory expansion mode and Microprocessor mode : with wait 1" * "18.4.10 Memory expansion mode and Microprocessor mode : with wait 0" The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "18.4 Electrical characteristics" (page 18-7 in part 1) 18.4.6 Ready and Hold Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Symbol Parameter Unit Min. Max. ____ tsu(RDY- ) RDY input setup time ns 80 _____ tsu(HOLD- ) ____ ns HOLD input setup time 80 th( -RDY) RDY input hold time ns 0 _____ th( -HOLD) HOLD input hold time ns 0 Note: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 1 1 1 1 Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz, unless otherwise noted) Parameter Symbol td( -HLDA) 1 _____ Conditions Fig. 18.4.1 HLDA output delay time 7735 Group User's Manual Limits Min. Max. 120 Unit ns 18-5 LOW VOLTAGE VERSION 18.4 Electrical characteristics Ready With no wait 1 RDE, WEL, WEH output RDY input tsu(RDY- 1) th( 1-RDY) With wait 1 RDE, WEL, WEH output RDY input tsu(RDY- 1) th( 1-RDY) Hold 1 tsu(HOLD- 1) th( 1-HOLD) HOLD input td( 1-HLDA) HLDA output Measuring conditions * VCC = 2.7 to 5.5 V * Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 18-6 7735 Group User's Manual td( 1-HLDA) LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.8 Memory expansion mode and Microprocessor mode : with no wait Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Min. Max. Unit External clock input cycle time (Note 2) tc ns 83 External clock input high-level pulse width (Note 3) tw(H) 33 ns External clock input low-level pulse width (Note 3) tw(L) 33 ns External clock rise time tr ns 15 External clock fall time tf ns 15 Data input setup time tsu(D-RDE) 80 ns Data input hold time th(RDE-D) ns 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 166 ns. 3: When the main clock division selection bit = "1," values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(X IN) = 12 MHz, unless otherwise noted) Parameter Symbol td(CS-WE) td(CS-RDE) th(WE-CS) th(RDE-CS) td(An-WE) td(An-RDE) td(A-WE) td(A-RDE) th(WE-An) th(RDE-An) tw(ALE) Chip-select output delay time tsu(A-ALE) Address output setup time th(ALE-A) td(ALE-WE) td(ALE-RDE) td(WE-DQ) Address hold time th(WE-DQ) Data formula (Min.) 1 109 2* f(f2) 1 10 2* f(f2) 1 109 2* f(f2) 1 109 2* f(f2) 1 109 2* f(f2) 1 109 2* f(f2) 9 Address output delay time Address output delay time Address hold time ALE pulse width ALE output delay time Limits Min. 4 ns - 63 20 ns - 63 20 ns - 43 40 ns - 43 40 ns - 73 10 ns 9 ns 4 ns Fig. 18.4.1 90 1 10 2* f(f2) 2 109 2* f(f2) 9 Data hold time ____ WEL, WEH pulse width tpxz(RDE-DZ) Floating start delay time 1 10 2* f(f2) 2 109 2* f(f2) 1 109 2* f(f2) Floating release delay time ____ 40 ns - 35 131 ns - 30 53 RDE pulse width - 38 tw(RDE) 128 _____ td(RSMP-WE) RSMP output delay time - 58 25 td(RSMP-RDE) _____ th( 1-RSMP) RSMP hold time 0 td(WE- 1) 1 output delay time 30 0 td(RDE- 1) _____ td( 1-HLDA) HLDA output delay time 120 Note: f(f 2) represents the clock f 2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1 in part 1. 7735 Group User's Manual ns - 43 10 9 Unit ns Data output delay time tw(WE) Max. 20 - 63 Chip-select hold time ____ tpzx(RDE-DZ) Conditions ns ns ns ns ns ns ns 18-7 LOW VOLTAGE VERSION 18.4 Electrical characteristics Memory expansion mode and Microprocessor mode : With no wait (Wait bit = "1") <<Read>> <<Write>> tw(H) tw(L) tf tr tw(L) tc tw(H) tf tr tc XIN 1 td(WE- td(WE- 1) 1) td(RDE- td(RDE- 1) 1) CS0-CS4 output Address output A8-A15 (BYTE = "H") A16, A17 th(WE-CS) td(CS-WE) td(CS-RDE) th(RDE-CS) Address Address th(WE-An) td(An-WE) tw(ALE) td(An-RDE) tw(ALE) td(ALE-WE) Address th(RDE-An) td(ALE-RDE) ALE output tsu(A-ALE) Address/Data output A0/D0-A15/D15 (BYTE = "L") A0/D0-A7/D7 (BYTE = "H") Address td(A-WE) th(ALE-A) tsu(A-ALE) th(ALE-A) th(WE-DQ) Address Data Data td(WE-DQ) tw(WE) Address Address tpzx(RDE-DZ) td(A-RDE) tpxz(RDE-DZ) WEL output WEH output th(RDE-D) tsu(D-RDE) Data input D0-D15 (BYTE = "L") D0-D7 (BYTE = "H") Data tw(RDE) RDE output td(RSMP-WE) th( td(RSMP-RDE) 1-RSMP) th( 1-RSMP) RSMP output td(WE-PiQ) Port Pi output (i = 4-8) tsu(PiD-RDE) th(RDE-PiD) Port Pi input (i = 4-8) Measuring conditions (CS0-CS4, A0/D0-A15/D15, A16, A17, ALE, WEL, WEH, RDE, RSMP) Measuring conditions (Ports P4-P8) *VCC = 2.7-5.5 V : VIL = 0.2 VCC, VIH = 0.8 VCC *VCC = 2.7-5.5 V *Input timing voltage *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Data input 18-8 :V IL = 0.16 VCC, VIH = 0.5 VCC 7735 Group User's Manual LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.9 Memory expansion mode and Microprocessor mode : with wait 1 Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Min. Max. Unit External clock input cycle time (Note 2) tc ns 83 External clock input high-level pulse width (Note 3) tw(H) ns 33 External clock input low-level pulse width (Note 3) tw(L) ns 33 External clock rise time tr ns 15 External clock fall time tf ns 15 Data input setup time tsu(D-RDE) ns 80 Data input hold time th(RDE-D) ns 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 166 ns. 3: When the main clock division selection bit = "1," values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(X IN) = 12 MHz, unless otherwise noted) Parameter Symbol td(CS-WE) td(CS-RDE) th(WE-CS) th(RDE-CS) td(An-WE) td(An-RDE) td(A-WE) td(A-RDE) th(WE-An) th(RDE-An) tw(ALE) 1 10 2* f(f2) 9 1 10 2* f(f2) 1 109 2* f(f2) 1 109 2* f(f2) 1 109 2* f(f2) 1 109 2* f(f2) 9 Address output delay time Address output delay time Address hold time ALE pulse width th(ALE-A) td(ALE-WE) td(ALE-RDE) td(WE-DQ) Address hold time ALE output delay time Max. 4 ns - 63 20 ns - 63 20 ns - 43 40 ns - 43 40 ns - 73 10 ns 9 ns 4 ns Fig. 18.4.1 90 1 109 - 43 2* f(f2) 4 109 2* f(f2) - 35 Data hold time ____ tw(WE) WEL, WEH pulse width tpxz(RDE-DZ) Floating start delay time ns 40 ns 298 ns 10 1 109 - 30 2* f(f2) 9 4 10 - 38 2* f(f2) 1 109 2* f(f2) - 58 Floating release delay time Unit ns Data output delay time ____ ns 53 ns 295 ns 25 ns RSMP hold time 0 ns 1 output delay time 0 ____ tw(RDE) td(RSMP-WE) td(RSMP-RDE) th( 1-RSMP) td(WE- 1) td(RDE- 1) td( 1-HLDA) Limits Min. 20 - 63 Chip-select hold time Address output setup time tpzx(RDE-DZ) Data formula (Min.) Chip-select output delay time tsu(A-ALE) th(WE-DQ) Conditions RDE pulse width _____ RSMP output delay time _____ _____ HLDA output delay time 30 ns 120 ns Note: f(f 2) represents the clock f 2 frequency. For the relationship with the main clock and sub clock, refer to Table 14.3.1 in part 1. 7735 Group User's Manual 18-9 LOW VOLTAGE VERSION 18.4 Electrical characteristics Memory expansion mode and Microprocessor mode : When external memory area is accessed with wait 1 (Wait bit = "0" and Wait selection bit = "1") <<Write>> <<Read>> tw(H) tw(L) tw(L) tc tf tr tw(H) tf tr tc XIN 1 td(WE- td(WE- 1) 1) td(RDE- td(RDE- 1) 1) CS0-CS4 output td(CS-WE) td(CS-RDE) th(WE-CS) Address output A8-A15 (BYTE = "H") A16, A17 Address Address Address th(WE-An) td(An-WE) tw(ALE) th(RDE-CS) th(RDE-An) td(An-RDE) tw(ALE) td(ALE-WE) Address td(ALE-RDE) ALE output Address/Data output A0/D0-A15/D15 (BYTE = "L") A0/D0-A7/D7 (BYTE = "H") tsu(A-ALE) th(ALE-A) th(WE-DQ) Address td(A-WE) Data tsu(A-ALE) Address th(ALE-A) Address td(WE-DQ) tw(WE) td(A-RDE) Address tpzx(RDE-DZ) tpxz(RDE-DZ) WEL output WEH output tsu(D-RDE) Data input D0-D15 (BYTE = "L") D0-D7 (BYTE = "H") th(RDE-D) Data tw(RDE) RDE output td(RSMP-WE) th( td(RSMP-RDE) 1-RSMP) th( 1-RSMP) RSMP output td(WE-PiQ) Port Pi output (i = 4-8) tsu(PiD-RDE) th(RDE-PiD) Port Pi input (i = 4-8) Measuring conditions (CS0-CS4, A0/D0-A15/D15, A16, A17, ALE, WEL, WEH, RDE, RSMP) Measuring conditions (Ports P4-P8) *VCC = 2.7-5.5 V : VIL = 0.2 VCC, VIH = 0.8 VCC *VCC = 2.7-5.5 V *Input timing voltage *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Data input 18-10 : V IL = 0.16 VCC, VIH = 0.5 VCC 7735 Group User's Manual LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.10 Memory expansion mode and Microprocessor mode : with wait 0 Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Parameter Symbol Min. Max. Unit External clock input cycle time (Note 2) tc ns 83 External clock input high-level pulse width (Note 3) tw(H) ns 33 External clock input low-level pulse width (Note 3) tw(L) ns 33 External clock rise time tr ns 15 External clock fall time tf ns 15 Data input setup time tsu(D-RDE) ns 80 Data input hold time th(RDE-D) ns 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 166 ns. 3: When the main clock division selection bit = "1," values of tw(H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN ) = 12 MHz, unless otherwise noted) Parameter Symbol td(CS-WE) td(CS-RDE) th(WE-CS) th(RDE-CS) td(An-WE) td(An-RDE) td(A-WE) td(A-RDE) th(WE-An) th(RDE-An) tw(ALE) Chip-select output delay time tsu(A-ALE) Address output setup time th(ALE-A) td(ALE-WE) td(ALE-RDE) td(WE-DQ) Address hold time th(WE-DQ) Data formula (Min.) 3 10 2* f(f2) 9 Address output delay time Address output delay time Address hold time ALE pulse width ALE output delay time Fig. 18.4.1 ns - 68 182 ns - 88 162 ns - 43 40 ns - 43 123 ns - 73 93 ns - 43 40 ns - 43 40 ns 90 1 10 - 43 2* f(f2) 4 109 - 35 2* f(f2) ____ tpxz(RDE-DZ) Floating start delay time ns 40 ns 298 ns 10 1 109 - 30 2* f(f2) 4 109 - 38 2* f(f2) 1 109 - 58 2* f(f2) Floating release delay time Unit 4 9 Data hold time WEL, WEH pulse width Max. ns Data output delay time tw(WE) ns 53 ns 295 ns 25 ns RSMP hold time 0 ns 1 output delay time 0 ____ tw(RDE) td(RSMP-WE) td(RSMP-RDE) th( 1-RSMP) td(WE- 1) td(RDE- 1) th( 1-HLDA) 3 10 2* f(f2) 3 109 2* f(f2) 1 109 2* f(f2) 2 109 2* f(f2) 2 109 2* f(f2) 1 109 2* f(f2) 1 109 2* f(f2) 9 Limits Min. 182 - 68 Chip-select hold time ____ tpzx(RDE-DZ) Conditions RDE pulse width _____ RSMP output delay time _____ _____ HLDA output delay time 7735 Group User's Manual 30 ns 120 ns 18-11 LOW VOLTAGE VERSION 18.4 Electrical characteristics Memory expansion mode and Microprocessor mode : When external memory area is accessed with wait 0 (Wait bit = "0" and Wait selection bit = "0") <<Write>> tw(L) <<Read>> tw(H) tf tr tw(L) tc tw(H) tf tr tc XIN 1 td(WE- td(WE- 1) td(RDE- 1) td(RDE- 1) 1) CS0-CS4 output Address output A8-A15 (BYTE = "H") A16, A17 td(CS-RDE) th(WE-CS) td(CS-WE) Address Address td(An-WE) th(WE-An) tw(ALE) th(RDE-CS) td(An-RDE) tw(ALE) td(ALE-WE) th(RDE-An) td(ALE-RDE) ALE output Address/Data output A0/D0-A15/D15 (BYTE = "L") A0/D0-A7/D7 (BYTE = "H") tsu(A-ALE) th(ALE-A) Data Address td(A-WE) tsu(A-ALE) th(WE-DQ) Data td(WE-DQ) tw(WE) th(ALE-A) Address td(A-RDE) Address tpxz(RDE-DZ) WEL output WEH output tsu(D-RDE) Data input D0-D15 (BYTE = "L") D0-D7 (BYTE = "H") tpzx(RDE-DZ) th(RDE-D) Data tw(RDE) RDE output td(RSMP-WE) th( td(RSMP-RDE) 1-RSMP) th( 1-RSMP) RSMP output td(WE-PiQ) Port Pi output (i = 4-8) tsu(PiD-RDE) th(RDE-PiD) Port Pi input (i = 4-8) Measuring conditions (CS0-CS4, A0/D0-A15/D15, A16, A17, ALE, WEL, WEH, RDE, RSMP) Measuring conditions (Ports P4-P8) *VCC = 2.7-5.5 V : VIL = 0.2 VCC, VIH = 0.8 VCC *VCC = 2.7-5.5 V *Input timing voltage *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V *Data input 18-12 : V IL = 0.16 VCC, VIH = 0.5 VCC 7735 Group User's Manual LOW VOLTAGE VERSION 18.6 Applications 18.6 Applications Some application examples of connecting external memorys for the low voltage version are described below. For the basic description of the memory expansion, refer to chapter "17. APPLICATIONS." Applications shown here are just examples. Modify the desired application to suit the user's need and make sufficient evaluations before actually using it. 18.6.1 Memory expansion The following items of the 7735 Group's low voltage version are the same as section "17.1 Memory expansion" in part 1, but a part of the caluculation way and constants for each parameter is different: *Memory expansion model *Caluculation way for address access time of external memory *Bus timing *Memory expansion way Address access time of external memory ta(AD) t a(AD) = td(A-RDE) + t w(RDE) - t su(D-RDE) - (address decode time 1 + address latch delay time 2) address decode time 1 : time necessary for validating a chip select signal after an address is decoded address latch delay time 2 : time necessary for latching an address Data setup time of external memory for writing data tsu(D) t su(D) = tw(WE) - t d(WE-DQ) Table 18.6.1 lists the caluculation formulas and constants for each parameter of the low voltage version. Figure 18.6.1 shows the relationship between ta(AD) and 2* f(f 2 ). Figure 18.6.2 shows the relationship between tsu(D) and 2* f(f2 ). Table 18.6.1 Caluculation formulas and constants for each parameter (Unit : ns) Software wait Wait bit Wait selection bit td(A-RDE) tw(RDE) tw(WE) No wait 1 0 or 1 Wait 0 0 0 3 109 - 88 2* f(f2) Wait 1 0 1 1 109 - 63 2* f(f2) 2 109 - 38 2* f(f2) 2 109 - 35 2* f(f2) tsu(D-RDE) 4 109 -38 2* f(f2) 4 109 - 35 2* f(f2) 80 td(WE-DQ) 90 Wait bit : Bit 2 at address 5E 16 Wait selection bit : Bit 0 at address 5F16 Note: This is applied to the case where the system clock selection bit (bit 3 at address 6C 16) = "0." 7735 Group User's Manual 18-13 LOW VOLTAGE VERSION 18.6 Applications [ns] 3500 3294 Address access time ta(AD) 3000 No wait Wait 1 is valid. Wait 0 is valid. 2500 2319 2127 2000 1544 1485 1500 1319 1194 1069 1000 960 819 819 569 500 794 652 419 319 669 571 533 444 194 247 374 152 494 319 119 430 273 91 0 2 3 4 5 6 7 8 9 10 11 377 235 69 12 [M H z] External clock input frequency 2* f(f2) Address decode time and address latch delay time are not id d Fig. 18.6.1 Relationship between t a(AD) and 2 * f(f2) [ns] 2000 1875 Data setup time tsu(D) No wait 1500 Wait 1 or Wait 0 is valid. 1208 875 1000 875 675 541 500 541 375 275 208 446 160 375 319 275 238 125 97 208 75 56 41 8 9 10 11 12 0 2 3 4 5 6 7 External clock input frequency 2* f(f2) Fig. 18.6.2 Relationship between t su(D) and 2 * f(f2 ) 18-14 7735 Group User's Manual [MHz] LOW VOLTAGE VERSION 18.6 Applications 18.6.2 Memory expansion example Figure 18.6.3 shows a memory expansion example and Figure 18.6.4 shows the corresponding timing diagram. In this example, an Atmel company's EPROM (AT27LV256R) is used as the external ROM. M37735MHLXXXHP CNVSS BYTE M5M51008AFP-15VLL AT27LV256R-15DI Address bus A8 to A16 CS1 CS2 S1 CE HC573 A0 /D0 to A7/D7 D Q A0 to A14 A0 to A14 D0 to D7 A0 to A16 A0 to A16 E ALE Data bus RDE WEL XIN D0 to D7 D0 to D7 DQ1 to DQ8 OE OE W RD WR XOUT 10 MHz Supply voltage : Vcc = 3.0 to 5.5 V Circuit conditions : Wait 1 f(XIN) f(XIN) f(XIN) f(XCIN) 1= 8 , 16 , or 2 2 , (Can operate with no wait when f(X IN) 8.0 MHz.) Make sure that the propagation delay time is 85 ns (max.) or less. Memory map 000016 008016 SFR area Internal RAM area 087F16 Not used 800016 External ROM area FFFF 16 (AT27LV256R-15DI) Not used 40000 16 External RAM area 5FFFF 16 (M5M51008AFP-15VLL) Fig. 18.6.3 Memory expansion example 7735 Group User's Manual 18-15 LOW VOLTAGE VERSION 18.6 Applications At reading 295 (min.) RDE, OE A A A8 to A16 10 (max.) A A A0/D0 to A7/D7 53 (min.) ta(S1),tCE ta(OE),tOE Extermal memory data output tdis(S1) D HC573 ta(A), tACC ( tPHL/PLH) tsu(D-RDE) 20 (min.) tdis(OE),tDF 4 (min.) CE, S1, CS1, CS2 At writing 298 (min.) WEL, W A8 to A16 A A A tsu(D) A0/D0 to A7/D7 A D A 90 (min.) 20 (min.) CS2, S1 (Unit : ns) Fig. 18.6.4 Timing diagram 18-16 7735 Group User's Manual LOW VOLTAGE VERSION 18.6 Applications 18.6.3 Ready generating circuit example When validating "wait" only for a certain area (for example, ROM area) in Figure 18.6.3, use the ready function. Figure 18.6.5 shows a ready generating circuit example. M37735MHLXXXHP CS0 CS 0 AC32 RSMP Wait generated by the ready function is inserted only to an area where accessed by signal CS 0. RDY Circuit conditions : f(X IN) 12 MHz, no wait, 1= td (RDE- 1) f(XIN) f(XIN) f(XIN) f(XCIN) , 8 , 16 , or 2 2 tc 1 RDE CS0 td(RSMP-RDE) RSMP RDY tsu(RDYPropagation delay time of AC32 (max. : 28 ns) 1) : Wait generated by the ready function Condition to satisfy the relationship tsu(RDY- 1) 80 ns is tc+td(RSMP-RDE) 108 ns Accordingly, when f (XIN) 12 MHz, this example satisfies the relationship tsu(RDY- 1) 80 ns. Fig. 18.6.5 Ready generating circuit example 7735 Group User's Manual 18-17 LOW VOLTAGE VERSION 18.6 Applications MEMO 18-18 7735 Group User's Manual CHAPTER 19 BUILT-IN PROM VERSION 19.1 EPROM mode 19.2 Usage precaution BUILT-IN PROM VERSION 19.1 EPROM mode Concerning chapter "19. BUILT-IN PROM VERSION," the 7735 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter: * "19.1 EPROM mode" The following section of the 7735 Group is the same as that of the 7733 Group. Therefore, for this section, refer to part 1: * "19.2 Usage precaution" (page 19-10 in part 1) 19.1 EPROM mode Concerning section "19.1 EPROM mode," the 7735 Group differs from the 7733 Group in the following: * Figures 19.1.1 and 19.1.2 * Bit 3 of the oscillation circuit control register 1 (address 6F 16) is "1" at reset. After reset, this bit must be cleared to "0" in the single-chip mode. This writing must be performed with the procedure shown in Figure 14.3.4. The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "19.1 EPROM mode" (page 19-3 in part 1) 19-2 7735 Group User's Manual BUILT-IN PROM VERSION 19.1 EPROM mode P71/AN1 P72/AN2/CTS2 P73/AN3/CLK2 P74/AN4/RxD2 P75/AN5/ADTRG/TxD2 P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RxD0/CLKS0 P83/TxD0 VCC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 OE PGM 64 1 2 63 62 3 4 5 61 60 6 59 7 58 M37735EHBFP CE P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 P42/ 1 P41/RDY 8 9 10 11 12 13 14 15 16 17 57 56 55 54 53 52 51 50 49 48 18 47 19 20 46 45 21 44 22 43 23 42 24 41 P84/CTS1/RTS1 P85/CLK1 P86/RxD1 P87/TxD1 P00/CS0 P01/CS1 P02/CS2 P03/CS3 P04/CS4 P05/RSMP P06/A16 P07/A17 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A0/D0 P21/A1/D1 P22/A2/D2 P23/A3/D3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 A16 D7 D6 D5 D4 E/RDE VSS P33/HLDA P32/ALE P31/WEH P30/WEL P27/A7/D7 P26/A6/D6 P25/A5/D5 P24/A4/D4 * VPP P40/HOLD BYTE CNVSS RESET XIN XOUT 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VSS * : Connect these pins to a resonator or an oscillator. : EPROM pin. Outline 80P6N-A Fig. 19.1.1 Pin connections in EPROM mode (M37735EHBFP) 7735 Group User's Manual 19-3 BUILT-IN PROM VERSION 19.1 EPROM mode P67/TB2IN/ SUB P70/AN0 P71/AN1 P72/AN2/CTS2 P73/AN3/CLK2 P74/AN4/RxD2 P75/AN5/ADTRG/TxD2 P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RXD0/CLKS0 P83/TXD0 P84/CTS1/RTS1 P85/CLK1 VCC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 OE PGM 1 60 2 59 3 58 4 57 5 56 M 37735EH LH P CE P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT/KI2 P55/TA2IN/KI1 P54/TA2OUT/KI0 P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47 P46 P45 P44 P43 6 7 8 9 10 11 12 13 14 15 16 55 54 53 52 51 50 49 48 47 46 45 17 44 18 43 19 42 20 41 P86/RXD1 P87/TXD1 P00/CS0 P01/CS1 P02/CS2 P03/CS3 P04/CS4 P05/RSMP P06/A16 P07/A17 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A0D0 P21/A1/D1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 * D7 D6 D5 D4 D3 D2 A16 VPP P42/ 1 P41/RDY P40/HOLD BYTE CNVSS RESET XIN XOUT E/RDE VSS P33/HLDA P32/ALE P31/WEH P30/WEL P27/A7/D7 P26/A6/D6 P25/A5/D5 P24/A4/D4 P23/A3/D3 P22/A2/D2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VSS * : Connect these pins to a resonator or an oscillator. : EPROM pin. Outline 80P6D-A Fig. 19.1.2 Pin connections in EPROM mode (M37735EHLHP) 19-4 7735 Group User's Manual CHAPTER 20 EXTERNAL ROM VERSION 20.1 Performance overview 20.2 Pin configuration 20.3 Pin description 20.4 Block description 20.5 Memory allocation 20.6 Processor modes 20.7 Timer A 20.8 Reset 20.9 Electrical characteristics 20.10 Low voltage version EXTERNAL ROM VERSION The external ROM version can operate only in the microprocessor mode. Functions of the external ROM version differ from those of the mask ROM version in the following. Therefore, only the differences are described in this chapter: *Memory allocation *Operation is available only in the microprocessor mode *ROM area change function is not available. *Timer A has the pulse output port mode. *Power source current and Current consumption For the other functions, refer to the following: * Chapters "4. INTERRUPTS" to "9. A-D CONVERTER" in part 1 * Chapter "2. CENTRAL PROCESSING UNIT (CPU)" in part 2 * Chapter "3. PROGRAMMABLE I/O PORT" in part 2 * Chapters "10. WATCHDOG TIMER" to "17. APPLICATIONS" in part 2 For product expansion information of the 7735 Group, contact the appropriate office, as listed in "CONTACT ADDRESSES FOR FURTHER INFORMATION." 20-2 7735 Group User's Manual EXTERNAL ROM VERSION 20.1 Performance overview 20.1 Performance overview Performance overview of the external ROM version differs from that of the mask ROM version in the following: memory size and current consumption. For the other items, refer to section "1.1 Performance overview" in part 2. Table 20.1.1 lists the M37735S4BFP's performance overview. Table 20.1.1 M37735S4BFP's performance overview Memory size Current consumption Items RAM Performance 2048 bytes 57 mW (When f(X IN ) = 25-MHz external square wave input, Vcc = 5 V, and the main clock is the system clock, Typ.) 300 W (When f(X CIN ) = 32 kHz, Vcc = 5 V, the sub clock is the system clock, and the main clock is stopped, Typ.) 7735 Group User's Manual 20-3 EXTERNAL ROM VERSION 20.2 Pin configuration 20.2 Pin configuration P71/AN1 P72/AN2/CTS2 P73/AN3/CLK2 P74/AN4/RXD2 P75/AN5/ADTRG/TXD2 P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RXD0/CLKS0 P83/TXD0 Figure 20.2.1 shows the M37735S4BFP pin configuration. Note: For the low voltage version, refer to section "20.10 Low voltage version." 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 64 2 63 3 62 4 61 5 60 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 M37735S4BFP P70/AN0 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3/RTP13 P56/TA3OUT/KI2/RTP12 P55/TA2IN/KI1/RTP11 P54/TA2OUT/KI0/RTP10 P53/TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P47 P46 P45 P44 P43 (P42)/ 1 RDY 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 21 44 22 43 23 42 24 41 P84/CTS1/RTS1 P85/CLK1 P86/RXD1 P87/TXD1 CS0(P00) CS1(P01) CS2(P02) CS3(P03) CS4(P04) RSMP(P05) A16(P06) A17(P07) A8/D8(P10) A9/D9(P11) A10/D10(P12) A11/D11(P13) A12/D12(P14) A13/D13(P15) A14/D14(P16) A15/D15(P17) A0/D0(P20) A1/D1(P21) A2/D2(P22) A3/D3(P23) HOLD BYTE CNVSS RESET XIN XOUT RDE Vss (P33)HLDA (P32)ALE (P31)WEH (P30)WEL (P27)A7/D7 (P26)A6/D6 (P25)A5/D5 (P24)A4/D4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Outline 80P6N-A Fig. 20.2.1 M37735S4BFP pin configuration (Top view) 20-4 7735 Group User's Manual By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin's level can be fixed in the stop or wait mode. EXTERNAL ROM VERSION 20.3 Pin description 20.3 Pin description Tables 20.3.1 and 20.3.2 list the pin description. Table 20.3.1 Pin description (1) Pin Vcc, Vss Name Power source input CNVss RESET CNVss Reset input Input Input XIN Clock input Input XOUT Clock output Output RDE Read enable output Output BYTE External data bus width selection input AVcc Analog power source input ______ ____ Input/Output Input AVss VREF Reference voltage input Input ____ CS 0 (P00)- Chip select output, Output ____ CS 4 (P0 4), ______ RSMP (P0 5), Ready sampling output, A 16 (P0 6), Address (high-order) A 17 (P07 ) output A8/D8 (P1 0) - A15/D15 (P1 7) Address (middle-order) output/Data I/O I/O Functions To pin Vcc, apply 5 V10% (When the main clock is the system clock) or 2.7 V to 5.5 V (When the subclock is the system clock). To pin Vss, apply 0 V. Connect to pin Vcc. The microcomputer is reset when "L" level is input to this pin. Pins X IN and X OUT are the I/O pins of the clock generating circuit, respectively. Connect these pins via a ceramic resonator or a quartz-crystal oscillator. When an external clock is used, the clock should be input to pin X IN, and pin X OUT should be left open. ____ ____ This pin outputs read enable signal RDE . RDE 's level is "L" in the data read period of the read cycle. Input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. A 16-bit width is selected when the level is "L," and an 8-bit width is selected when the level is "H." Power source input for the A-D converter. Connect to pin Vcc. Power source input for the A-D converter. Connect to pin Vss. This is the reference voltage input pin for the A-D converter. ___ ___ _____ These pins respectively output signals CS0-CS4, RSMP, and high-order 2 bits (A16 , A 17) of address. ___ ___ Signals CS0-CS4 These signals are the chip-select signals. When the microcomputer accesses a certain area, the corresponding pin outputs "L" level. (Refer to Figure 12.1.3.) _____ Signal RSMP This signal is the ready sampling signal and is used ____ to generate signal RDY for accessing the external memory area. When the external data bus width = 8 bits (Pin BYTE is at "H" level) Address's middle-order 8 bits (A8-A15 ) are output. When the external bus width = 16 bits (Pin BYTE pin is at "L" level) Input/Output of data (D8-D15) and output of address's middle-order 8 bits (A8-A15) are performed with the time sharing system. 7735 Group User's Manual 20-5 EXTERNAL ROM VERSION 20.3 Pin description Table 20.3.2 Pin description (2) Pin Name Input/Output Functions A0 /D0 (P20 ) Address (low-order) Input/Output of data (D0 -D 7) and output of address's I/O -A 7/D7 output/Data (low-order) low-order 8 bits (A 0-A 7 ) are performed with the time (P2 7) I/O sharing system. ____ ____ ____ Output WEL (P3 0), Write enable low output, These pins respectively output signals WEL, WEH, ALE, ____ _____ WEH (P3 1), Write enable high output, and HLDA . ____ ____ ALE (P3 2), Address latch enable output, Signals WEL, WEH _____ ____ HLDA (P33) Hold acknowledge output Signal WEL is the write enable low signal. ____ Signal WEH is the write enable high signal. These signals' levels are "L" in the data write period of the write cycle. The operations of these signals depend on the level of pin BYTE. (Refer to Table 12.1.1.) Signal ALE This signal is used to separate the multiplexed signal which consists of an address and data to the address and data. _____ Signal HLDA This signal informs the external whether this microcomputer enters the Hold state or not. _____ In Hold state, pin HLDA outputs "L" level. _____ _____ HOLD , Hold request input, The microcomputer is in Hold state while pin HOLD 's Input ____ ____ RDY , Ready input, input level is "L" and is in Ready state while pin RDY's Input 1(P42), Clock output, input level is "L." The clock 1 output can be stopped Output by software. (Refer to chapter "14. CLOCK GENERATING CIRCUIT.") P4 3-P47 I/O port P4 P43-P47 function as I/O ports with the same functions I/O as port P5. P5 0-P57 I/O port P5 P5 is a CMOS 8-bit I/O port and has an I/O direction I/O register. Each pin can be programmed for input or output. It can be programmed as I/O pins for timers A0-A3, ___ ___ input pins (KI0-KI3) for the key input interrupt and output pins (RTP0 0-RTP13 ) for the pulse output. P6 0-P67 I/O port P6 P6 is an 8-bit I/O port with the same function as port I/O P5 and can be programmed as I/O pins for timer A4, external interrupt input pins, and input pins for timers B0-B2. P67 also functions as an output pin for the sub clock ( SUB). I/O port P7 P7 0-P77 I/O P7 is an 8-bit I/O port with the same function as port P5 and can be programmed as analog input pins for the A-D converter. P7 6 and P7 7 can be programmed as I/O pins (X COUT , X CIN ) for the sub-clock (32 kHz) oscillation circuit. When using P76 and P77 as pins XCOUT and X CIN, connect a quartz-crystal oscillator between them. P7 2 -P75 also function as UART2's I/O pins. I/O port P8 P8 0-P87 I/O P8 is an 8-bit I/O port with the same function as port P5 and can be programmed as serial I/O's I/O pins. 20-6 7735 Group User's Manual EXTERNAL ROM VERSION 20.4 Block description 20.4 Block description External data bus width selection input BYTE Figure 20.4.1 shows the M37735S4BFP block diagram. Instruction Queue Buffer Q1 (8) 1 RDY HOLD HLDA ALE WEH WELRDE RSMP Input/Output port P4 Input/Output port P5 Input/Output port P6 P5(8) P4(5) A-D Converter(10) Input/Output port P7 Input/Output port P8 P8(8) Anthmetic Logic Unit(16) P7(8) Accumulator A(16) RAM 2048 bytes Clock Generating Circuit Clock output XOUT Accumulator B(16) P6(8) Index Register X(16) UART0 (9) XCIN XCOUT Index Register Y(16) UART1 (9) Stack Pointer S(16) Timer TB0(16) Direct Page Register DPR(16) Timer TA0(16) Reset input RESET Processor Status Register PS(11) UART2 (9) Input Buffer Register IB(16) Timer TB2(16) VCC Data Bank Register DT(8) Timer TB1(16) Program Bank Register PG(8) Timer TA1(16) (0V) VSS Program Counter PC(16) Address Bus Timer TA2(16) Incrementer/Decrementer(24) Timer TA4(16) CNVss Data Address Register DA(24) Timer TA3(16) (0V) AVSS Program Address Register PA(24) Chip select Instruction Queue Buffer Q2 (8) Bus Interface Central Processing Unit (CPU) Unit (BIU) Watchdog Timer AVCC Reference voltage input VREF Instruction Queue Buffer Q0 (8) XCIN XCOUT Instruction Register(8) Data Buffer DB L(8) Address bus/ Data bus Data Bus(Odd) Data Buffer DBH(8) Incrementer(24) Clock input XIN Address (18) / data (16) Data Bus(Even) Fig.20.4.1 M37735S4BFP block diagram 7735 Group User's Manual 20-7 EXTERNAL ROM VERSION 20.5 Memory allocation 20.5 Memory allocation The internal area's memory allocation is described below. For details, refer to section "2.4 Memory allocation" in part 1. For the external area, refer to section "20.6 Processor modes." Figure 20.5.1 shows the M37735S4BFP's memory map and Figure 20.5.2 shows the SFR area's memory map. 20-8 7735 Group User's Manual EXTERNAL ROM VERSION 20.5 Memory allocation * RAM size: 2 Kbytes 000000 16 00007F 16 000080 16 00087F 16 000800 16 SFR area 000000 16 Peripheral device control registers (SFR) Internal RAM area 2048 bytes Refer to Figure 20.5.2. Bank 0 16 00007F 16 Interrupt vector table 00FFD6 16 A-D/UART2 trans./rece. UART1 transmission 00FFFF 16 010000 16 UART1 reception UART0 transmission UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Bank 1 16 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Watchdog timer DBC 01FFFF 16 BRK instruction Zero divide 00FFFE 16 RESET : External memory area 0FFFFF 16 100000 16 (Note) FFFFFF 16 Note: Banks 10 16 to FF 16 cannot be accessed. For the 7735 Group's microcomputers other than the M37735S4BFP, refer to section "Appendix 1. 773 5 Group memory allocation ." Fig. 20.5.1 M37735S4BFP's memory map 7735 Group User's Manual 20-9 EXTERNAL ROM VERSION 20.5 Memory allocation Address (Hexadecimal notation) 000000 000001 000002 Port P0 register (Note 3) 000003 Port P1 register (Note 3) 000004 Port P0 direction register (Note 3) 000005 Port P1 direction register (Note 3) 000006 Port P2 register (Note 3) 000007 Port P3 register (Note 3) 000008 Port P2 direction register (Note 3) 000009 Port P3 direction register (Note 3) 00000A Port P4 register (Note 3) 00000B Port P5 register 00000C Port P4 direction register (Note 3) 00000D Port P5 direction register 00000E Port P6 register 00000F Port P7 register 000010 Port P6 direction register 000011 Port P7 direction register 000012 Port P8 register 000013 000014 Port P8 direction register 000015 000016 000017 000018 000019 00001A 00001B 00001C Pulse output data register 1 (Note 1) 00001D Pulse output data register 0 (Note 1) 00001E A-D control register 0 00001F A-D control register 1 000020 A-D register 0 000021 000022 A-D register 1 000023 000024 A-D register 2 000025 000026 A-D register 3 000027 000028 A-D register 4 000029 00002A A-D register 5 00002B 00002C A-D register 6 00002D 00002E A-D register 7 00002F 000030 UART 0 transmit/receive mode register 000031 UART 0 baud rate register (BRG0) 000032 UART 0 transmission buffer register 000033 000034 UART 0 transmit/receive control register 0 000035 UART 0 transmit/receive control register 1 000036 UART 0 receive buffer register 000037 000038 UART 1 transmit/receive mode register 000039 UART 1 baud rate register (BRG1) 00003A UART 1 transmission buffer register 00003B 00003C UART 1 transmit/receive control register 0 00003D UART 1 transmit/receive control register 1 00003E UART 1 receive buffer register 00003F Address (Hexadecimal notation) 000040 000041 000042 000043 000044 000045 000046 000047 000048 000049 00004A 00004B 00004C 00004D 00004E 00004F 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005A 00005B 00005C 00005D 00005E 00005F 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006A 00006B 00006C 00006D 00006E 00006F 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007A 00007B 00007C 00007D 00007E 00007F Count start flag One-shot start flag Up-down flag Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Watchdog timer frequency selection flag Waveform output mode register (Note 1) Reserved area (Notes 1, 2) UART2 transmit/receive mode register UART2 baud rate register (BRG2) UART2 transmission buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Oscillation circuit control register 0 Port function control register Serial transmit control register Oscillation circuit control register 1 A-D/UART2 trans./rece. interrupt control register UART 0 transmission interrupt control register UART 0 receive interrupt control register UART 1 transmission interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2/Key input interrupt control register Notes 1: Memory map of the M37735S4BFP differs from that of the M37735MHBXXXFP in addresses 1C16, 1D16, 6216, and 6316. 2: Writing to the reserved area is disabled. 3: These registers are used when outputting an arbitrary data in the stop or wait mode. Fig. 20.5.2 SFR area's memory map 20-10 7735 Group User's Manual EXTERNAL ROM VERSION 20.6 Processor modes 20.6 Processor modes The M37735S4BFP can operate only in the microprocessor mode. For the processor mode, refer to the description of the microprocessor mode in section "2.5 Processor modes" in part 1. Also, be sure to set as follows: * Connect pin CNVss to Vcc. * Fix the processor mode bit to "10 2." Figure 20.6.1 shows the structure of the processor mode register 0. b7 b6 0 b5 b4 b3 b2 b1 b0 Processor mode register 0 (address 5E 16) Bit name Bit 0 Processor mode bits 1 Functions b1 b0 0 0: Do not select. 0 1: Do not select. 1 0: Microprocessor mode 1 1: Do not select. At reset RW 0 RW 0 RW 0 RW 2 Wait bit 3 Software reset bit Microcomputer is reset by setting this bit to "1." This bit is "0" at reading. 0 WO 4 Interrupt priority detection time selection bits b5 b4 0 RW 0 RW 5 0: Software wait is inserted when accessing external area. 1: No software wait is inserted when accessing external area. 0 0: 7 cycles of 0 1: 4 cycles of 1 0: 2 cycles of 1 1: Do not select. 6 Must be fixed to "0." 0 RW 7 This bit is ignored. (it may be "0" or "1.") 0 RW represents that bits 2 to 7 are not used for setting the processor mode. Fig. 20.6.1 Structure of processor mode register 0 7735 Group User's Manual 20-11 EXTERNAL ROM VERSION 20.7 Timer A, 20.8 Reset 20.7 Timer A The timer A description of the M37735S4BFP is the same as that of the 7733 Group. For timer A description of the M37735S4BFP, refer to the following: * "6. TIMER A" (page 6-2 in part 1) * "20.7 Timer A" (page 20-12 in part 1) 20.8 Reset The reset description of the M37735S4BFP differs from that of the mask ROM version in the state immediately after reset. The state immediately after reset of the M37735S4BFP differs from that of the mask ROM version in the following addresses: addresses 1C 16, 1D 16, 6216 and 6316 . Figures 20.8.1 and 20.8.2 show the state of SFR area and internal RAM area immediately after reset (1) and (4). Figure 20.8.1 corresponds to Figure 13.1.3 in part 1. Figure 20.8.2 corresponds to Figure 13.1.6 in part 1. For the other descriptions, refer to chapter "13. RESET." ______ For the pin state while pin RESET is at "L" level, refer to Table 13.1.1. 20-12 7735 Group User's Manual EXTERNAL ROM VERSION 20.8 Reset SFR area (addresses 016 to 7F16) Abbreviations which represent access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Not implemented. It is impossible to read the bit state. The written value becomes invalid. 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. Address Register name 016 116 Port P0 register 216 Port P1 register 316 Port P0 direction register 416 Port P1 direction register 516 Port P2 register 616 Port P3 register 716 816 Port P2 direction register 916 Port P3 direction register Port P4 register A16 Port P5 register B16 C16 Port P4 direction register D16 Port P5 direction register Port P6 register E16 Port P7 register F16 Port P6 direction register 1016 1116 Port P7 direction register Port P8 register 1216 1316 1416 Port P8 direction register 1516 1616 1716 1816 1916 1A16 1B16 1C16 Pulse output data register 1 1D16 Pulse output data register 0 1E16 A-D control register 0 1F16 A-D control register 1 b7 0 : Always "0" at reading ? : Always undefined at reading 0 : "0" immediately after reset. Must be fixed to "0." State immediately after reset Access characteristics b0 b0 b7 RW RW RW RW RW RW 0 0 0 RW 0 0 0 0 ? 0 ? 0 0 RW RW RW RW RW RW RW RW RW RW RW WO WO RW RW RW ? ? ? ? 0016 0016 ? 0 0016 0 0 ? ? 0016 0016 ? ? 0016 0016 ? ? 0016 ? ? ? ? ? ? ? ? ? 0 0 0 0 ? 0 0 0 ? ? ? 1 ? 1 The contents of addresses 1C16 and 1D16 of the M37735S4BFP differ from those of the M37735MHBXXXFP. Fig. 20.8.1 State of SFR area and internal RAM area immediately after reset (1) 7735 Group User's Manual 20-13 EXTERNAL ROM VERSION 20.8 Reset Address 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C16 6D16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 Register name b7 Access characteristics Watchdog timer frequency selection flag Waveform output mode register 3 RW RW WO WO UART 2 baud rate register (BRG2) UART 2 transmission buffer register RO UART 2 transmit/receive control register 0 RO UART 2 transmit/receive control register 1 WO A-D / UART 2 trans./rece. interrupt control register UART0 transmission interrupt control register UART0 receive interrupt control register UART1 transmission interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2/Key input interrupt control register ? 0 ? 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ? 0 ? 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? 0 0 0 0 RO RW 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 ? RW Oscillation circuit control register 1 Timer A4 interrupt control register Timer B0 interrupt control register 0 ? RW Port function control register Serial transmit control register Timer A3 interrupt control register WO RW RW RO RW RW(2) Oscillation circuit control register 0 Timer A1 interrupt control register b0 ? (1) ? 0 0 ? ? RO UART 2 receive buffer register Timer A2 interrupt control register RW RW RW (Reserved area) 4 UART 2 transmit/receive mode register Timer A0 interrupt control register State immediately after reset b7 WO Watchdog timer register UART1 receive interrupt control register b0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? ? ? 0 0 0 0 0 0 ? 1 A value of "FFF 16" is set to the watchdog timer. (Refer to Chapter "10. WATCHDOG TIMER" in part 1.) 2 For access characteristics at address 6C 16, also refer to Figure 14.3.2 in part 1. 3 The contents of addresses 62 16 and 6316 of the M37735S4BFP differ from those of the M37735MHBXXXFP. 4 Do not wirte to address 63 16. Internal RAM area (M37735S4BFP: addresses 80 16 to 87F16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset . When the stop or wait mode is terminated (when hardware reset is used)...Retains the state immediately before the STP or WIT instruction is executed. Fig. 20.8.2 State of SFR area and internal RAM area immediately after reset (4) 20-14 7735 Group User's Manual EXTERNAL ROM VERSION 20.9 Electrical characteristics 20.9 Electrical characteristics Except for "Icc," the electrical characteristics of the M37735S4BFP are the same as those of the M37735MHBXXXFP in the microprocessor mode. For the others, refer to chapter "15. ELECTRICAL CHARACTERISTICS." ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter Measuring conditions Min. Limits Typ. Max. Unit Vcc = 5 V, f(XIN) = 25 MHz (Square waveform), (f(f2) = 12.5 MHz), 11.4 22.8 mA f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 5V, f(XIN) = 25 MHz (Square waveform), (f(f2) = 1.5625 MHz), 1.6 3.2 mA f(XCIN) : Stopped, in operating (Note 1) External bus is Vcc = 5V, operating, output f(XIN) = 25 MHz (Square waveform), pins are open, 10 20 A Power source f(XCIN) = 32.768 kHz, Icc and the other current when the WIT instruction is executed (Note 2) pins are conVcc = 5 V, nected to Vss. f(XIN) : Stopped, 60 120 A f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 5 V, f(XIN) : Stopped, 5 10 A f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 C, 1 A when clock is stopped Ta = 85 C, 20 A when clock is stopped Notes 1: This is applied when the main clock external input selection bit = "1," the main clock division selection bit = "0," and the signal output disable selection bit = "1." 2: This is applied when the main clock external input selection bit = "1" and the system clock stop selection bit at wait state = "1." 3: This is applied when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the XCOUT drivability selection bit = "0" and the system clock stop bit at wait state = "1." 7735 Group User's Manual 20-15 EXTERNAL ROM VERSION 20.10 Low voltage version 20.10 Low voltage version Differences from the M37735S4BFP are mainly described below. 20.10.1 Performance overview The performance overview of the low voltage version differs from that of the M37735S4BFP in the following: memory size and current consumption. For the other items, refer to section "18.1 Performance overview." Table 20.10.1 shows the M37735S4LHP's performance overview. Table 20.10.1 M37735S4LHP's performance overview Items Memory size Current consumption 20-16 Performance RAM 2048 bytes 10.8 mW (When f(XIN) = 12-MHz square wave input, Vcc = 3 V, and the main clock is the system clock, Typ.) 120 W (When f(X CIN) = 32 kHz, Vcc = 3 V, the sub clock is the system clock, and the main clock is stopped, Typ.) 7735 Group User's Manual EXTERNAL ROM VERSION 20.10 Low voltage version P67/TB2IN/ SUB P70/AN0 P71/AN1 P72/AN2/CTS2 P73/AN3/CLK2 P74/AN4/RxD2 P75/AN5/ADTRG/TxD2 P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RXD 0/CLKS0 P83/TXD0 P84/CTS1/RTS1 P85/CLK1 20.10.2 Pin configuration Figure 20.10.1 shows the M37735S4LHP pin configuration. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 7 8 9 10 11 12 13 14 15 M37735S4LHP P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3/RTP13 P56/TA3OUT/KI2/RTP12 P55/TA2IN/KI1/RTP11 P54/TA2OUT/KI0/RTP10 P53/TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P47 P46 P45 P44 P43 55 54 53 52 51 50 49 48 47 46 16 45 17 44 18 43 19 42 20 41 P86/Rx D1 P87/TxD1 CS0(P00) CS1(P01) CS2(P02) CS3(P03) CS4(P04) RSMP(P05) A16(P06) A17(P07) A8/D8(P10) A9/D9(P11) A10/D10(P12) A11/D11(P13) A12/D12(P14) A13/D13(P15) A14/D14(P16) A15/D15(P17) A0/D0(P20) A1/D1(P21) (P42)/ 1 RDY HOLD BYTE CNVSS RESET XIN XOUT RDE VSS (P33)HLDA (P32)ALE (P31)WEH (P30)WEL (P27)A7/D7 (P26)A6/D6 (P25)A5/D5 (P24)A4/D4 (P23)A3/D3 (P22)A2/D2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 By setting the port register and port direction register which correspond to the port shown in ( ), the corresponding pin's level can be fixed in the stop or wait mode. Outline 80P6D-A Fig. 20.10.1 M37735S4LHP pin configuration (Top view) 7735 Group User's Manual 20-17 EXTERNAL ROM VERSION 20.10 Low voltage version 20.10.3 Functional description Except for the power-on reset conditions, the M37735S4LHP has the same functions as the M37735S4BFP For the other functions, refer to the following: "4. INTERRUPTS" to "9. A-D CONVERTER" in part 1, "2. CENTRAL PROCESSING UNIT (CPU)" in part 2, "3. PROGRAMMABLE I/O PORTS" in part 2, and "10. WATCHDOG TIMER" to "17. APPLICATIONS" in part 2. The power-on reset condition of the M37735S4LHP is the same as that of the M37735MHLXXXHP. For the power-on reset condition, refer to section "18.3 Functional description" in part 1. 20.10.4 Electrical characteristics Except for "Icc," the electrical characteristics of the M37735S4LHP are the same as those of the M37735MHLXXXHP in the microprocessor mode. For the others, refer to section "18.4 Electrical characteristics" in part 2. ELECTRICAL CHARACTERISTICS (Vcc= 5 V, Vss = 0 V, Ta = -40 to 85 C, unless otherwise noted) Limits Symbol Parameter Measuring conditions Min. Typ. Max. Unit Vcc = 5 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), 5.4 10.8 mA f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), 7.2 mA 3.6 f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 0.75 MHz), 1.0 mA 0.5 External bus is f(XCIN) : Stopped, operating, in operating (Note 1) Power source output pins are Vcc = 3V, ICC current open, and the f(XIN) = 12 MHz (Square waveform), 12 A 6 other pins are f(XCIN) = 32.768 kHz, connected when the WIT instruction is executed (Note 2) to Vss. Vcc = 3 V, f(XIN) : Stopped, 80 A 40 f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 3 V, f(XIN) : Stopped, 6 A 3 f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 C, 1 A when clock is stopped Ta = 85 C, 20 A when clock is stopped Notes 1: This is applied when the main clock external input selection bit = "1," the main clock division selection bit = "0," and the signal output disable selection bit = "1." 2: This is applied when the main clock external input selection bit = "1" and the system clock stop bit at wait state = "1." 3: This is applied when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the XCOUT drivability selection bit = "0" and the system clock stop bit at wait state = "1." 20-18 7735 Group User's Manual APPENDIX Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix 1. 2. 3. 4. 5. 6. 7. 8. Memory allocation of 7735 Group Memory allocation in SFR area Control registers Package outlines Hexadecimal instruction code table Machine instructions Examples of handling unused pins Countermeasure examples against noise Appendix 9. Q & A APPENDIX Concerning chapter "APPENDIX," the 7735 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter: * "Appendix 1. Memory allocation of 7735 Group" * "Appendix 2. Memory allocation in SFR area" * "Appendix 3. Control registers" * "Appendix 7. Examples of handling unused pins" Note: The following sections of the 7735 Group are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1: * "Appendix 4. Package outlines" (page 21-38 in part 1) * "Appendix 5. Hexadecimal instruction code table" (page 21-41 in part 1) * "Appendix 6. Machine instructions" (page 21-44 in part 1) * "Appendix 8. Countermeasure examples against noise" (page 21-61 in part 1) * "Appendix 9. Q & A" (page 21-71 in part 1) 21-2 7735 Group User's Manual APPENDIX Appendix 1. Memory allocation of 7735 Group Appendix 1. Memory allocation of 7735 Group 1. M37735MHBXXXFP, M37735EHBXXXFP, M37735EHBFS, M37735MHLXXXHP, M37735EHLXXXHP * Memory allocation selection bits (b2, b1, b0)=(0, 0, 1) * Memory allocation selection bits (b2, b1, b0)=(0, 0, 0) * ROM size: 120 Kbytes * ROM size: 124 Kbytes * RAM size: 3.9 Kbytes * RAM size: 3.9 Kbytes 000000 16 000000 16 000000 16 SFR area SFR area 00007F 16 00007F 16 000080 16 000080 16 Internal RAM area Internal RAM area Peripheral device 3968 bytes 3968 bytes control registers 000FFF 16 000FFF 16 (SFR) 001000 16 (4 Kbytes) Bank 016 Internal ROM area 002000 16 Refer to Internal ROM area 60 Kbytes Appendix 2. 00FFFF 16 56 Kbytes 00FFFF 16 010000 16 010000 16 00007F 16 Bank 116 Interrupt vector table Internal ROM area 64K bytes Internal ROM area 64 Kbytes 00FFD 616 A-D/UART2 trans./rece. UART1 transmission 01FFFF 16 UART1 reception 01FFFF 16 UART0 transmission UART0 reception Timer B2 Timer B1 Bank 216 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input IN T1 IN T0 Watchdog timer 0FFFFF16 100000 16 D BC BRK instruction Zero divide 00FFFE 16 R ESET Bank 1016 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Bank FF16 FFFFFF16 FFFFFF16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes" in part 1.) 2: In the 7735 Group, banks 1016 to FF16 cannot be accessed. Fig. 1 Memory allocation of M37735MHBXXXFP, M37735EHBXXXFP, M37735EHBFS, M37735MHLXXXHP, M37735EHLXXXHP (1) 7735 Group User's Manual 21-3 APPENDIX Appendix 1. Memory allocation of 7735 Group * Memory allocation selection bits (b2, b1, b0)=(0, 1, 0) * ROM size: 60 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 2048 bytes 00087F16 (1.9 Kbytes) 00100016 * Memory allocation selection bits (b2, b1, b0)=(1, 0, 0) * ROM size: 32 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 2048 bytes 00087F16 00000016 Peripheral device control registers (SFR) Refer to Appendix 2. (29.9 Kbytes) Bank 016 Internal ROM area 60 Kbytes 00FFFF16 01000016 00800016 Internal ROM area 32 Kbytes 00FFFF16 01000016 00007F16 Interrupt vector table 00FFD616 A-D/UART2 trans./rece. UART1 transmission UART1 reception UART0 transmission UART0 reception Bank 116 Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 01FFFF16 02000016 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Bank 216 Watchdog timer DBC BRK instruction Zero divide 00FFFE16 RESET 02FFFF16 FF000016 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Bank FF16 FFFFFF16 FFFFFF16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes.") 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Fig. 2 Memory allocation of M37735MHBXXXFP, M37735EHBXXXFP, M37735EHBFS, M37735MHLXXXHP, M37735EHLXXXHP (2) 21-4 7735 Group User's Manual APPENDIX Appendix 1. Memory allocation of 7735 Group * Memory allocation selection bits (b2, b1, b0)=(1, 0, 1) * ROM size: 16 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 2048 bytes 00087F16 00000016 00007F16 00008016 000FFF16 00100016 Bank 016 * Memory allocation selection bits (b2, b1, b0)=(1, 1, 0) * ROM size: 96 Kbytes * RAM size: 3968 bytes SFR area 00000016 Internal RAM area 3968 bytes Peripheral device control registers (SFR) Refer to Appendix 2. (28 Kbytes) (45.9 Kbytes) 00800016 00C00016 00FFFF16 01000016 Internal ROM area 16 Kbytes Internal ROM area 32 Kbytes 00FFFF16 01000016 00007F16 Interrupt vector table 00FFD616 A-D/UART2 trans./rece. UART1 transmission UART1 reception UART0 transmission UART0 reception Internal ROM area 64 Kbytes Bank 116 Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 01FFFF16 02000016 01FFFF16 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Bank 216 Watchdog timer DBC BRK instruction Zero divide 00FFFE16 RESET 02FFFF16 FF000016 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Bank FF16 FFFFFF16 FFFFFF16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes.") 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Fig. 3 Memory allocation of M37735MHBXXXFP, M37735EHBXXXFP, M37735EHBFS, M37735MHLXXXHP, M37735EHLXXXHP (3) 7735 Group User's Manual 21-5 APPENDIX Appendix 1. Memory allocation of 7735 Group 2. M37735S4BFP, M37735S4LHP 000000 16 00007F 16 000080 16 Bank 016 00087F 16 SFR area 000000 16 Peripheral device control registers (SFR) Internal RAM area 2048 bytes Refer to Appendix. 2 00FFFF 16 010000 16 00007F 16 Interrupt vector table Bank 116 00FFD 616 A-D/UART2 trans./rece. UART1 transmission UART1 reception UART0 transmission 01FFFF 16 UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input IN T1 IN T0 Watchdog timer 0FFFFF16 100000 16 D BC BRK instruction Zero divide 00FFFE 16 R ESET Bank 1016 : External memory area Bank FF16 FFFFFF16 Notes 1: Addresses 00FFD616 to 00FFFF16 are the interrupt vector table. Be sure to set ROM to this area. 2: In the 7735 Group, banks 1016 to FF16 cannot be accessed. Fig. 4 Memory allocation of M37735S4BFP, M37735S4LHP 21-6 7735 Group User's Manual APPENDIX Appendix 2. Memory allocation in SFR area Appendix 2. Memory allocation in SFR area Concerning section "Appendix 2. Memory allocation in SFR area," the 7735 Group differs from the 7733 Group in the following: * Address 6F 16 (Refer to Figure 8.) The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "Appendix 2. Memory allocation in SFR area" (page 21-6 in part 1) 7735 Group User's Manual 21-7 APPENDIX Appendix 2. Memory allocation in SFR area Figure 8 differs from that of the 7733 Group only in 3. Address Register name b7 Watchdog timer register 6016 6116 Watchdog timer frequency selection flag (Reserved area) 4 6216 Memory allocation control register 6316 UART 2 transmit/receive mode register 6416 UART 2 baud rate register (BRG2) 6516 6616 UART 2 transmission buffer register 6716 6816 UART 2 transmit/receive control register 0 6916 UART 2 transmit/receive control register 1 6A16 UART 2 receive buffer register 6B16 Oscillation circuit control register 0 6C16 Port function control register 6D16 Serial transmit control register 6E16 Oscillation circuit control register 1 WO 6F16 7016 A-D / UART 2 trans./rece. interrupt control register 7116 UART0 transmission interrupt control register 7216 UART0 receive interrupt control register 7316 UART1 transmission interrupt control register 7416 UART1 receive interrupt control register Timer A0 interrupt control register 7516 Timer A1 interrupt control register 7616 Timer A2 interrupt control register 7716 Timer A3 interrupt control register 7816 Timer A4 interrupt control register 7916 Timer B0 interrupt control register 7A16 Timer B1 interrupt control register 7B16 Timer B2 interrupt control register 7C16 INT0 interrupt control register 7D16 INT1 interrupt control register 7E16 INT2/Key input interrupt control register 7F16 Access characteristics b0 State immediately after reset b0 b7 WO RW ? ? 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 RW RW WO WO RO RO WO RW R WR OR W 0 ? RO RW(2) RW RW RO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 ? ( 1) ? ? 0 0 0 0 ? ? ? 1 0 0 ? 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 ? 0 ? 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A value of "FFF16" is set to the watchdog timer. (Refer to chapter "10. WATCHDOG TIMER.") 2 For access characteristics at address 6C16, also refer to Figure 14.3.2 in part 1. 3 The state of bit 3 at address 6F16 immediately after reset depends on the product. (Refer to Figure 14.3.3 in part 2 : refer to this part because bit 3 at address 6F16 of the 7735 Group differs from that of the 7733 Group. Fix this bit to "0" in the 7735 Group. 4 Do not wirte to the reserved area. (Refer to Figure 20.8.1 for the M37733S4BFP, M37733S4LHP, M37735S4BFP, 37735S4LHP.) Internal RAM area (M37735MHBXXXFP: addresses 8016 to FFF16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset. When the stop or wait mode is terminated (when the hardware reset is used)...Retains the state immediately before the STP or WIT instruction is executed. Fig. 8 Memory allocation in SFR area (4) 21-8 7735 Group User's Manual APPENDIX Appendix 3. Control registers Appendix 3. Control registers Concerning section "Appendix 3. Control registers," the 7735 Group differs from the 7733 Group in the following: * Oscillation circuit control register 1 The other control registers are the same as those of the 7733 Group. Therefore, for the other control registers, refer to part 1: * "Appendix 3. Control registers" (page 21-10 in part 1) 7735 Group User's Manual 21-9 APPENDIX Appendix 3. Control registers Oscillation circuit control register 1 b7 b6 b5 b4 b3 0 0 b2 b1 b0 Oscillation circuit control register 1 (address 6F16) Bit Bit name Functions At reset RW 0 RW 0 RW 0 RW RW 0 Main clock division selection bit 0: Main clock is divided by 2. (Note 1) 1: Main clock is not divided by 2. 1 Main clock external input selection bit 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when (Note 1) terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. 2 Sub clock external input selection bit (Note 1) 3 Must be fixed to "0" in the mask ROM and external ROM versions (Note 1). 0 Must be fixed to "0" in the one time PROM and EPROM versions (Notes 1 and 2). 1 4 Must be fixed to "0" (Note 3). 0 RW 5 Not implemented. Undefined -- 6 Not implemented. Undefined -- 7 Clock prescaler reset bit 0 WO 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT. Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. (Note 4) By writing "1" to this bit, clock prescaler is initialized. Notes 1: When writing to this register, follow the procedure shown below. 2: Because this bit is "1" at reset, clear this bit to "0" with the initial setting program after reset. 3: The case where data "010101012" is written with the procedure shown below is not included. 4: For the 7733 Group, refer to Figure 14.3.3 in part 1. * When performing clock prescaler reset Write data "8016." (LDM instruction) * When writing to bits 0 to 3 Write data "010101012."(LDM instruction) Next instruction Write data "00000XXX2." (LDM instruction) (b2 to b0 in the above Figure) 21-10 7735 Group User's Manual APPENDIX Appendix 7. Examples of handling unused pins Appendix 7. Examples of handling unused pins The following are examples of handling unused pins. These are, however, just examples. In actual use, make the necessary adaptations and properly evaluate performance according to the user's application. 1. In single-chip mode Table 1 Examples of handling unused pins in single-chip mode Handling example Pins Connect these pins to pin Vcc or Vss via resistors after these P0-P8 pins are set to the input mode, or leave these pins open after they are set to the output mode (Note 1). _ Leave this pin open. E XOUT (Note 2) AVcc Connect this pin to pin Vcc. AVss, V REF, BYTE Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these ports function as input ports. Software reliability can be enhanced when the contents of the above ports ' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 2: This is applied when an external clock is input to pin XIN. When setting ports to output mode When setting ports to input mode P0-P8 M37735MHBXXXFP M37735MHBXXXFP E XOUT P0-P8 Left open Vcc AVcc AVss VREF BYTE Vss E XOUT Left open Left open Vcc AVcc AVss VREF BYTE Vss Fig. 9 Examples of handling unused pins in single-chip mode 7735 Group User's Manual 21-11 APPENDIX Appendix 7. Examples of handling unused pins 2. In memory expansion mode Table 2 Examples of handling unused pins in memory expansion mode Pins Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). Leave these pins open. (Note 3) P4 2-P4 7, P5-P8 (Note 5) _________ ________ ________ WEH , WEL, RDE , _____ __________ HLDA, CS0- CS4, RSMP X OUT (Note 4) _____ ____ HOLD , RDY Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. AVcc AVss, V REF Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory expansion mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 4: This is applied when an external clock is input to pin XIN . 5: Set pin P4 2 / 1 as pin P4 2 . (Clock 1 output is disabled.) And then, for this pin, do the same handling as that for pins P4 3 to P4 7 and P5 to P8. When setting ports to input mode When setting ports to output mode P42-P47, P5-P8 XOUT CS0-CS4 M37735MHBXXXFP M37735MHBXXXFP WEH WEL RDE HLDA RSMP P42-P47, P5-P8 Left open Left open Vcc HOLD RDY AVcc AVss VREF WEH WEL RDE HLDA RSMP Left open XOUT CS0-CS4 Left open Vcc HOLD RDY AVcc AVss VREF Vss Fig. 10 Examples of handling unused pins in memory expansionmode 21-12 Left open 7735 Group User's Manual Vss APPENDIX Appendix 7. Examples of handling unused pins 3. In microprocessor mode Table 3 Examples of handling unused pins in microprocessor mode Pins Handling example P4 3-P4 7, P5-P8 Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). _________ ________ ________ WEH, WEL , RDE Leave these pins open. (Note 3) _____ ___________ HLDA , 1, CS 0-CS4, RSMP XOUT (Note 4) Leave this pin open. _____ ____ HOLD, RDY Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) AVCC Connect this pin to pin Vcc. AVSS, VREF Connect these pins to pin Vss. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the microprocessor mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. 4: This is applied when an external clock is input to pin XIN. When setting ports to output mode When setting ports to input mode P43-P47, P5-P8 M37735MHBXXXFP M37735MHBXXXFP WEH WEL RDE HLDA P43-P47, P5-P8 Left open 1 RSMP XOUT CS0-CS4 Left open Vcc HOLD RDY AVcc AVss VREF WEH WEL RDE HLDA Left open Left open 1 RSMP Left open XOUT CS0-CS4 Vcc HOLD RDY AVcc AVss VREF Vss Vss Fig. 11 Examples of handling unused pins in microprocessor mode 7735 Group User's Manual 21-13 APPENDIX Appendix 7. Examples of handling unused pins MEMO 21-14 7735 Group User's Manual PART 3 7736 Group CHAPTER 1 OVERVIEW CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) CHAPTER 3 PROGRAMMABLE I/O PORTS CHAPTER 4 INTERRUPTS CHAPTER 5 KEY INPUT INTERRUPT FUNCTION CHAPTER 6 TIMER A CHAPTER 7 TIMER B CHAPTER 8 SERIAL I/O CHAPTER 9 A-D CONVERTER CHAPTER 10 WATCHDOG TIMER CHAPTER 11 STOP AND WAIT MODES CHAPTER 12 CONNECTING EXTERNAL DEVICES CHAPTER 13 RESET CHAPTER 14 CLOCK GENERATING CIRCUIT CHAPTER 15 ELECTRICAL CHARACTERISTICS CHAPTER 16 STANDARD CHARACTERISTICS CHAPTER 17 APPLICATIONS CHAPTER 18 LOW VOLTAGE VERSION CHAPTER 19 BUILT-IN PROM VERSION APPENDIX PART 3 7736 Group The differences between the 7736 Group and the 7733 Group are mainly described below. For the 7733 Group, refer to part "1. 7733 Group." For the 7735 Group, refer to part "2. 7735 Group." The 7736 Group differs from the 7733/7735 Group in the following: * External bus mode in the memory expansion mode and the microprocessor mode (In the 7736 Group, pin BSEL's level determines the external bus mode, which is A or B.) * Output port P9 and I/O port P10 (Ports P9 and P10 are assigned only for the 7736 Group.) * Pin assignment for the key input interrupt (In the 7736 Group, the pins are assigned to pins P104 to P10 7 .) * Pin assignment for UART2 (In the 7736 Group, the pins are assigned to pins P9 0 to P9 3.) * External ROM version (In the 7736 Group, there is no external ROM version.) * Package (In the 7736 Group, the 100-pin QFP is used.) 2 7736 Group User's Manual CHAPTER 1 OVERVIEW 1.1 1.2 1.3 1.4 Performance overview Pin configuration Pin description Block diagram OVERVIEW 1.1 Performance overview Concerning chapter "1. OVERVIEW," the 7736 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter: * "1.1 Performance overview" * "1.2 Pin configuration" * "1.3 Pin description" * "1.4 Block diagram" 1.1 Performance overview Concerning section "1.1 Performance overview," the 7736 Group differs from the 7733 Group in the following: * Description of the programmable I/O ports, memory expansion, and package in Table 1.1.1 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "1.1 Performance overview" (page 1-3 in part 1) Table 1.1.1 M37736MHBXXXGP's performance overview Items Performance Programmable I/O ports Ports P0-P2, P4-P8, P10 8 bits 9 4 bits 1 Port P3 Output port 8 bits 1 Port P9 Memory expansion Possible * External bus mode A: Maximum of 16 Mbytes * External bus mode B: Maximum of 1 Mbytes Package 100-pin plastic molded QFP 1-2 7736 Group User's Manual OVERVIEW 1.2 Pin configuration 1.2 Pin configuration P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5/ADTRG P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RXD0/CLKS0 P83/TXD0 P84/CTS1/RTS1 P85/CLK1 P86/RXD1 Figure 1.2.1 shows the M37736MHBXXXGP pin configuration. Note: For the low voltage version, refer to chapter "18. LOW VOLTAGE VERSION." 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 M37736MHBXXXGP P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P107/KI3 P106/KI2 P105/KI1 P104/KI0 P103 P102 P101 P100 P47 P46 P45 P44 P43 P42/ 1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 26 55 27 54 28 53 29 52 30 51 P87/TXD1 P90/CTS2 P91/CLK2 P92/RxD2 P93/TxD2 P94 P95 P96 P97 P00/A0/CS0 P01/A1/CS1 P02/A2/CS2 P03/A3/CS3 P04/A4/CS4 P05/A5/RSMP P06/A6/A16 P07/A7/A17 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/A0/D0 P21/A17/A1/D1 P22/A18/A2/D2 P23/A19/A3/D3 P24/A20/A4/D4 P41/RDY P40/HOLD BYTE CNVSS BSEL RESET XIN XOUT E/RDE VSS VCC EVL1 EVL0 P33/HLDA P32/ALE P31/BHE/WEH P30/R/W/WEL P27/A23/A7/D7 P26/A22/A6/D6 P25/A21/A5/D5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Outline 100P6S-A Fig. 1.2.1 M37736MHBXXXGP pin configuration (Top view) 7736 Group User's Manual 1-3 OVERVIEW 1.3 Pin description 1.3 Pin description Concerning section "1.3 Pin description," the 7736 Group differs from the 7733 Group in the following: ___ * "Description of pins E and BSEL in Table 1.3.1" * "Description of pins P00 -P0 7, P2 0-P2 7 and P30 -P33 in Tables 1.3.2 and 1.3.3" * "Description of pins P50-P5 7, P7 0-P7 7, P9 0-P9 7, P10 0-P10 7, EVL0 and EVL1 in Table 1.3.4" * "1.3.1 Examples of handling unused pins" The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "1.3 Pin description" (page 1-5 in part 1) Table 1.3.1 Pin description (1) Pin _ E BSEL Processor modes External bus modes Single-chip mode Memory expansion or Microprocessor mode -- A Single-chip mode -- Memory expansion or Microprocessor mode 1-4 Name Enable output B A, B Bus select input I/O Functions Output Same as the 7733 Group. _ Output This pin outputs internal enable signal E. ________ Output This pin outputs read enable signal RDE . ________ RDE's level is "L" in the data read period of the read cycle. Input The level of a signal which is input to this pin may be "H" or "L." Input The signal which is input to this pin determines the external bus mode. When this signal's level is "H," external bus mode A is selected; when this signal's level is "L," external bus mode B is selected. 7736 Group User's Manual OVERVIEW 1.3 Pin description Table 1.3.2 Pin description (2) Processor mode External bus mode P0 0-P07 Single-chip mode -- A0-A 7 Memory expansion or Microprocessor mode A Output B Output Single-chip mode -- Pin CS 0-CS 4, _____ RSMP, Name I/O port P0 I/O Functions I/O Same as the 7733 Group. Address's low-order 8 bits (A0-A7) are output. ____ These pins respectively output signals CS 0- CS4 , RSMP , and address's high-order 2 bits (A 16 and A17 ). Signals CS0- CS4 These signals are the chip select signals. When the microcomputer accesses a certain area, the corresponding pin outputs "L" level. (Refer to Table 2.5.4.) _____ Signal RSMP This signal is the ready sampling signal and ________ is used to generate signal RDY for accessing external memory area. Same as the 7733 Group. Input/Output of data (D 0 -D 7 ) and output of address's high-order 8 bits (A 16 -A 23 ) are performed with the time sharing method. Input/Output of data (D 0 -D 7 ) and output of address's low-order 8 bits (A0-A7) are performed with the time sharing method. A 16, A 17 P2 0-P27 A16/D0- Memory expansion A 23 /D 7 or Microprocessor mode A0/D0- A 7 /D 7 I/O port P2 I/O A Output B Output 7736 Group User's Manual 1-5 OVERVIEW 1.3 Pin description Table 1.3.3 Pin description (3) mode External bus mode Name I/O P3__ 0-P3 3 Single-chip mode -- I/O port P3 I/O R/W, BHE, Memory expansion or Microprocessor mode A Pin ____ ALE, _____ Processor HLDA Functions Same as the 7733 Group. __ ____ Output These pins respectively output signals R/W, BHE, _____ ALE, and HLDA. __ Signal R/ W This signal indicates the data bus state. When this signal level is "H," a data bus is in the read state. When this signal level is "L," a data bus is in the write state. ____ Signal BHE This signal's level is "L" when the microcomputer accesses an odd address. Signal ALE This signal is used to separate the multiplexed signal which consists of an address and data to the address and the data. _____ ____ WEL, ____ WEH, ALE, _____ HLDA 1-6 B Signal HLDA This signal informs the external whether this microcomputer enters the Hold state or not. _____ In Hold state, pin HLDA outputs "L" level. ________ ____ Output These pins respectively output signals WEL, WEH, _____ ALE, and HLDA. ________ _________ Signal WEL, WEH ____ Signal WEL is the write enable low signal. ____ Signal WEH is the write enable high signal. These signals' levels are "L" in the data write period of the write cycle. The operations of these signals depend on the level of pin BYTE. (Refer to Table 12.1.1 in part 2.) Signal ALE This signal is the same as that in external bus mode A. _____ Signal HLDA This signal is the same as that in external bus mode A. 7736 Group User's Manual OVERVIEW 1.3 Pin description Table 1.3.4 Pin description (4) Pin P5 0-P5 7 P7 0-P7 7 P9 0-P9 7 P100-P107 Processor mode External bus mode Name I/O Functions Single-chip mode -- I/O port P5 I/O Memory expansion or Microprocessor mode A, B P5 is an 8-bit I/O port with the same function as port P0 and can be programmed as I/O Single-chip mode Memory expansion or Microprocessor mode -- pins for timers A0-A3. -- Memory expansion or Microprocessor mode A, B Single-chip mode -- A, B EVL0, EVL1 Single-chip mode Memory expansion or Microprocessor mode I/O A, B Single-chip mode Memory expansion or Microprocessor mode I/O port P7 P7 is an 8-bit I/O port with the same function as port P0 and can be programmed as analog input pins for the A-D converter. P76 and P77 can be programmed as I/O pins (XCOUT, XCIN) for the sub-clock (32 kHz) oscillation circuit. When using P7 6 and P7 7 as pins X COUT and XCIN, connect a quartz-crystal oscillator between them. When inputting an external clock, input the clock from pin X CIN . Output port P9 Output P9 is an 8-bit output-only port. After reset, P9 enters a floating state. When data is written to the port P9 register, P9 starts outputting (Note). P90-P9 3 also function as UART2's I/O pins. I/O port P10 I/O P10 is an 8-bit I/O port with the same function as port P0. Pins 104-107 can be programmed as input pins (KI0-KI3) for the key input interrupt. -- ------ Output Leave these pins open. A, B Note: After reset, be sure to write data to the port P9 latch. 7736 Group User's Manual 1-7 OVERVIEW 1.3 Pin description 1.3.1 Examples of handling unused pins The following are examples of handling unused pins. These are, however, just examples. In actual use, make the necessary adaptations and properly evaluate performance according to the user's application. (1) In single-chip mode Table 1.3.5 Examples of handling unused pins in single-chip mode Pins E , RDE Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins open after they are set to the output mode (Note 1). Leave these pins open after writing data to the port P9 register (Note 3). Leave this pin open. EVL0, EVL1 XOUT (Note 2) AVcc Connect this pin to pin Vcc. AVss, V REF, BYTE BSEL Connect these pins to pin Vss. Connect this pin to pin Vcc or Vss. P0-P8, P10 P9 _ ____ Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until the they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these ports function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 2: This is applied when an external clock is input to pin XIN. 3: When leaving port P9 pins open after writing data to the port P9 register, note the following: these pins are in a floating state from reset until the data is written to the port P9 register by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. N When setting ports to input mode N When setting ports to output mode P0-P8,P10 M37736MHBXXXGP M37736MHBXXXGP P9 E/RDE XOUT EVL0 EVL1 Left open VCC AVCC AVSS VREF BYTE BSEL VSS Fig. 1.3.1 Examples of handling unused pins in single-chip mode 1-8 7736 Group User's Manual P0-P10 Left open E/RDE XOUT EVL0 EVL1 Left open VCC AVCC AVSS VREF BYTE BSEL VSS OVERVIEW 1.3 Pin description (2) In memory expansion mode (External bus mode A) Table 1.3.6 Examples of handling unused pins in memory expansion mode (External bus mode A) Pins P42 -P47, P5-P8, P10 (Note 7) P9 _____ BHE (Note 3), ALE (Note 4), HLDA X OUT (Note 6) _____ ____ HOLD , RDY AVcc AVss, V REF EVL0, EVL1 Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). Leave these pins open after writing data to the port P9 register (Note 8). Leave these pins open. (Note 5) Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Leave these pins open. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: This is applied when "H" level is input to pin BYTE. 4: This is applied when "H" level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory expansion mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: This is applied when an external clock is input to pin XIN. 7: Set pin P4 2 / 1 as pin P4 2 . (Clock 1 output is disabled.) And then, for this pin, do the same handling as that for pins P4 3 to P4 7, P5 to P8 and P10. 8: When leaving port P9 pins open after writing data to the port P9 register, note the following: these pins are in a floating state from reset until the data is written to the port P9 register by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. N When setting ports to input mode N When setting ports to output mode P42-P47, P5-P8, P10 P42-P47, P5-P10 M37736MHBXXXGP M37736MHBXXXGP P9 BHE ALE HLDA XOUT EVL0 EVL1 Left open Left open VCC HOLD RDY AVCC AVSS VREF BHE ALE HLDA XOUT EVL0 EVL1 Left open Left open Left open VCC HOLD RDY AVCC AVSS VREF VSS VSS Fig. 1.3.2 Examples of handling unused pins in memory expansion mode (External bus mode A) 7736 Group User's Manual 1-9 OVERVIEW 1.3 Pin description (3) In memory expansion mode (External bus mode B) Table 1.3.7 Examples of handling unused pins in memory expansion mode (External bus mode B) Pins Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). Leave these pins open after writing data to the port P9 register (Note 6). Leave these pins open. (Note 3) P42-P47, P5-P8, P10 (Note 5) P9 ____ ____ ____ WHE, WHL , RDE , _____ ___ ___ _____ HLDA, CS 0- CS 4, RSMP XOUT (Note 4) _____ ____ HOLD, RDY Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Leave these pins open. AVcc AVss, VREF EVL0, EVL1 Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory expansion mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 4: This is applied when an external clock is input to pin XIN. 5: Set pin P4 2 / 1 as pin P4 2 . (Clock 1 output is disabled.) And then, for this pin, do the same handling as that for pins P4 3 to P4 7, P5 to P8 and P10. 6: When leaving port P9 pins open after writing data to the port P9 register, note the following: these pins are in a floating state from reset until the data is written to the port P9 register by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. N When setting ports to input mode N When setting ports to output mode P42-P47, P5-P8, P10 M37736MHBXXXGP M37736MHBXXXGP P9 WEH WEL RDE HLDA RSMP XOUT CS0-CS4 EVL0 EVL1 P42-P47, P5-P10 Left open Left open VCC HOLD RDY AVCC AVSS VREF WEH WEL RDE HLDA RSMP XOUT CS0-CS4 EVL0 EVL1 HOLD RDY Left open Left open Left open VCC AVCC AVSS VREF VSS VSS Fig. 1.3.3 Examples of handling unused pins in memory expansion mode (External bus mode B) 1-10 7736 Group User's Manual OVERVIEW 1.3 Pin description (4) In microprocessor mode (External bus mode A) Table 1.3.8 Examples of handling unused pins in microprocessor mode (External bus mode A) Pins Handling example P43-P47, P5-P8, P10 Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). P9 Leave these pins open after writing data to the port P9 register (Note 7). _____ BHE (Note 3), ALE (Note 4), HLDA , 1 Leave these pins open. (Note 3) XOUT (Note 6) Leave this pin open. _____ ____ HOLD, RDY Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Leave these pins open. AV CC AVSS, V REF EVL0, EVL1 Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: This is applied when "H" level is input to pin BYTE. 4: This is applied when "H" level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the microprocessor mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. 6: This is applied when an external clock is input to pin XIN. 7: When leaving port P9 pins open after writing data to the port P9 register, note the following: these pins are in a floating state from reset until the data is written to the port P9 register by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. N When setting ports to input mode N When setting ports to output mode P43-P47, P5-P8, P10 P43-P47, P5-P10 M37736MHBXXXGP M37736MHBXXXGP P9 BHE ALE HLDA Left open 1 XOUT EVL0 EVL1 Left open VCC HOLD RDY AVCC AVSS VREF VSS BHE ALE HLDA Left open Left open 1 XOUT EVL0 EVL1 Left open VCC HOLD RDY AVCC AVSS VREF VSS Fig. 1.3.4 Examples of handling unused pins in microprocessor mode (External bus mode A) 7736 Group User's Manual 1-11 OVERVIEW 1.3 Pin description (5) In microprocessor mode (External bus mode B) Table 1.3.9 Examples of handling unused pins in microprocessor mode (External bus mode B) Pins Handling example P43-P47, P5-P8, P10 Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). P9 Leave these pins open after writing data to the port P9 register (Note 5). ____ ____ ____ WHE, WHL , RDE , Leave these pins open. (Note 3) _____ _____ HLDA , 1, CS 0 - CS 4, RSMP XOUT (Note 4) Leave this pin open. _____ ____ HOLD, RDY Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) AVCC Connect this pin to pin Vcc. AVSS, VREF Connect these pins to pin Vss. EVL0, EVL1 Leave these pins open. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the microprocessor mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. 4: This is applied when an external clock is input to pin XIN. 5: When leaving port P9 pins open after writing data to the port P9 register, note the following: these pins are in a floating state from reset until the data is written to the port P9 register by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. N When setting ports to input mode N When setting ports to output mode P43-P47, P5-P8, P10 P43-P47, P5-P10 Left open P9 M37736MHBXXXGP M37736MHBXXXGP WEH WEL RDE HLDA Left open 1 RSMP XOUT CS0-CS4 EVL0 EVL1 HOLD RDY AVCC Left open VCC AVSS VREF WEH WEL RDE HLDA Left open 1 RSMP XOUT CS0-CS4 EVL0 EVL1 HOLD RDY Left open VCC AVCC AVSS VREF VSS VSS Fig. 1.3.5 Examples of handling unused pins in microprocessor mode (External bus mode B) 1-12 7736 Group User's Manual Clock output XCOUT XCIN Enable output E Clock Generating Circuit Clock input XIN Index Register Y(16) Index Register X(16) Accumulator B(16) Accumulator A(16) Anthmetic Logic Unit(16) 7736 Group User's Manual Input/Output port P8 Output port P9 Input/Output port P10 P6(8) Input/Output port P6 Input/Output port P7 Stack Pointer S(16) P7(8) Program Bank Register PG(8) Input/Output port P3 P3(4) Input/Output port P2 P2(8) Instruction register(8) VREF Reference voltage input P1(8) Input/Output port P1 Instruction Queue Buffer Q1(8) Input/Output port P4 P4(8) A-D converter(10) AVCC External data bus width selection input BYTE Input/Output port P0 P0(8) Data Bus(Even) Input/Output port P5 P5(8) UART1(9) UART0(9) Bus Interface Unit (BIU) Address Bus P8(8) Timer TB0(16) Timer TA0(16) UART2(9) (0V) AVSS Instruction Queue Buffer Q0(8) P9(8) Timer TB1(16) Timer TB2(16) EVL1 CNVss Data Bus(Odd) P10(8) Direct Page Register DPR(16) Timer TA1(16) Program Counter PC(16) RAM 3968 byte Processor Status Register PS(11) Watchdog Timer Input Buffer Register IB(16) Timer TA2(16) Data Bank Register DT(8) Timer TA3(16) EVL0 Data Address Register DA(24) ROM 124 Kbyte BSEL Program Address Register PA(24) Timer TA4(16) (0V) VSS Incrementer (24) Central Processing Unit (CPU) VCC Data Buffer DBH(8) XCIN XCOUT Reset input RESET OVERVIEW 1.4 Block diagram 1.4 Block diagram Figure 1.4.1 shows the M37736MHBXXXGP block diagram. Data Buffer DBL(8) Instruction Queue Buffer Q2(8) Incrementer/Decrementer (24) Fig. 1.4.1 M37736MHBXXXGP block diagram 1-13 OVERVIEW 1.4 Block diagram MEMO 1-14 7736 Group User's Manual CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) 2.1 2.2 2.3 2.4 2.5 Central processing unit Bus interface unit Accessible area Memory allocation Processor modes CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes Concerning chapter "2. CENTRAL PROCESSING UNIT (CPU)," the 7736 Group differs from the 7733 Group in the following section. Therefore, only the differences are described below: * "2.5 Processor modes" The following sections of the 7736 Group differ depending on the external bus mode, which is A or B: * "2.2 Bus interface unit" External bus mode A (page 2-10 in part 1) External bus mode B (page 2-2 in part 2) * "2.3 Accessible area" External bus mode A (page 2-16 in part 1) External bus mode B (page 2-5 in part 2) The following sections of the 7736 Group are the same as those of the 7733 Group. Therefore, for these sections, refer to the part 1: * "2.1 Central processing unit" (page 2-2 in part 1) * "2.4 Memory allocation" (page 2-18 in part 1) 2.5 Processor modes Concerning section "2.5 Processor modes," the 7736 Group differs from the 7733 Group in the following: * "Figure 2.5.2" The following differ depending on the external bus mode. Therefore, refer to the corresponding part: * Figure 2.5.1 and Table 2.5.1 External bus mode A (Figure 2.5.1 and Table 2.5.1 in part 1) External bus mode B (Figure 2.5.1 and Table 2.5.1 in part 2) The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "2.5 Processor modes" (page 2-23 in part 1) 2-2 7736 Group User's Manual P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P107/KI3 P106/KI2 P105/KI1 P104/KI0 P103 P102 P101 P100 P47 P46 P45 P44 P43 2 P42/ 1 7736 Group User's Manual M37736MHBXXXGP 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 P87/TXD1 P90/CTS2 P91/CLK2 P92/RxD2 P93/TxD2 P94 P95 P96 P97 A0/CS0 A1/CS1 A2/CS2 A3/CS3 A4/CS4 A5/RSMP A6/A16 A7/A17 A8/D8 A9/D9 A10/D10 A11/D11 A12/D12 A13/D13 A14/D14 A15/D15 A16/A0/D0 A17/A1/D1 A18/A2/D2 A19/A3/D3 A20/A4/D4 P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P107/KI3 P106/KI2 P105/KI1 P104/KI0 P103 P102 P101 P100 P47 P46 P45 P44 P43 P42/ 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 M37736MHBXXXGP 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P86/RXD1 P85/CLK1 P84/CTS1/RTS1 P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P86/RXD1 P85/CLK1 P84/CTS1/RTS1 P83/TXD0 P82/RXD0/CLKS0 P81/CLK0 P80/CTS0/RTS0/CLKS1 VCC AVCC VREF AVSS VSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/ADTRG P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 79 80 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 P87/TXD1 P90/CTS2 P91/CLK2 P92/RxD2 P93/TxD2 P94 P95 P96 P97 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P12 P22 P23 P24 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes <Single-Chip mode> P25 P26 P27 P30 P31 P32 P33 EVL0 EVL1 VCC VSS E/RDE XOUT XIN RESET BSEL CNVSS 1 BYTE P40 P41 2 1 1 Connect this pin to Vss in the single-chip mode. : These pins' functions in the single-chip mode differ from those in the memory expansion or microprocessor mode. <Memory expansion and Microprocessor modes> A21/A5/D5 A22/A6/D6 A23/A7/D7 R/W/WEL BHE/WEH ALE HLDA EVL0 EVL1 VCC VSS E/RDE XOUT XIN RESET BSEL CNVSS BYTE HOLD RDY 1 in the microprocessor mode :These pins' functions in the single-chip mode differ from those in the memory expansion or microprocessor mode. Fig. 2.5.2 Pin configuration in each processor mode (Top view) 2-3 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes MEMO 2-4 7736 Group User's Manual CHAPTER 3 PROGRAMMABLE I/O PORTS 3.1 Programmable I/O ports and Output-only ports 3.2 Port peripheral circuits 3.3 Pull-up function 3.4 Internal peripheral devices' I/O functions (Ports P42, P5 to P8, P90 to P9 3 , and P10 4 to P10 7) PROGRAMMABLE I/O PORTS 3.1 Programmable I/O ports and Output-only ports Functions of all ports in the single-chip mode and those of ports P4 3 to P4 7 and P5 to P10 in the memory expansion or the microprocessor mode are described below. For more information about ports P0 to P4, whose functions depend on the processor mode, refer to section "2.5 Processor modes" and chapter "12. CONNECTING EXTERNAL DEVICES." 3.1 Programmable I/O ports and Output-only ports The 7736 Group has 76 programmable I/O ports (P0 to P8 and P10) and 8 output-only ports (P9). Each of programmable I/O ports has a port direction register and a port register in the SFR area. Each output-only port has a port register in the SFR area. Figure 3.1.1 shows the memory map of port direction registers and port registers. Note that ports P42, P5 to P8, P90 to P93 and P104 to P10 7 also function as I/O pins for internal peripheral devices. For details, refer to section "3.4 Internal peripheral devices' I/O functions" and the corresponding functional description. addresses 216 Port P0 register 316 Port P1 register 416 Port P0 direction register 516 Port P1 direction register 616 Port P2 register 716 Port P3 register 816 Port P2 direction register 916 Port P3 direction register A16 Port P4 register B16 Port P5 register C16 Port P4 direction register D16 Port P5 direction register E16 Port P6 register F16 Port P7 register 1016 Port P6 direction register 1116 Port P7 direction register 1216 Port P8 register 1316 Port P9 register 1416 Port P8 direction register 1516 1616 Port P10 register 1716 1816 Port P10 direction register Fig. 3.1.1 Memory map of port direction registers and port registers 3-2 7736 Group User's Manual PROGRAMMABLE I/O PORTS 3.1 Programmable I/O ports and Output-only ports 3.1.1 Port Pi direction register This register determines the direction of programmable I/O ports. Each bit of this register corresponds to one specified pin. Figure 3.1.2 shows the structure of the port Pi (i = 0 to 8 and 10) direction register. b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 0 to 8 and 10) (addresses 416,516,816,916,C16,D16,1016,1116,1416,1816) Bit Bit name Functions At reset RW 0 RW 0 RW 0 RW 0 Port Pi0 direction selection bit 1 Port Pi1 direction selection bit 2 Port Pi2 direction selection bit 3 Port Pi3 direction selection bit 0 RW 4 Port Pi4 direction selection bit 0 RW 5 Port Pi5 direction selection bit 0 RW 6 Port Pi6 direction selection bit 0 RW 7 Port Pi7 direction selection bit 0 RW 0: Input mode (The port functions as an input port.) 1: Output mode (The port functions as an output port.) Note: Writing to bits 4 to 7 of the port P3 direction register is invalid and these bits are fixed to "0" when they are read. Bit b7 b6 b5 b4 b3 b2 b1 b0 Corresponding pin Pi7 Pi6 Pi5 Pi4 Pi3 Pi2 Pi1 Pi0 Fig. 3.1.2 Structure of port Pi (i = 0 to 8 and 10) direction register 7736 Group User's Manual 3-3 PROGRAMMABLE I/O PORTS 3.1 Programmable I/O ports and Output-only ports 3.1.2 Port Pi register Data is input from or output to the external by writing or reading data to or from a port register. A port register consists of a port latch, which holds the output data, and a circuit, which reads the pin state. Each bit of the port register corresponds to one specified pin. Figure 3.1.3 shows the structure of the port Pi (i = 0 to 10) register. (1) How to output data from programmable I/O port Set the corresponding bit of the port direction register to the output mode. Write data to the corresponding bit of the port register, and then the data is written into the port latch. Data which is set in the port latch is output. When a bit of a port register which corresponds to a port set for the output mode is read out, the contents of the port latch, instead of pin state, is read out. Accordingly, output data can correctly be read out without influence of external load, etc. (Refer to Figures 3.2.1 and 3.2.2) (2) How to input data from programmable I/O port Set the corresponding bit of the port direction register to the input mode. The pin enters a floating state. When reading the corresponding bit of the port register in state , data which is input from the pin can be read in. When data is written to a port register which corresponds to a port set for the input mode, the data is written only into the port latch and not output to the external. Pins retain a floating state. (3) How to output data from output-only port Write data to the corresponding bit of the port register, and then the data is written into the port latch. Data which is set in the port latch is output. When a bit of a port register which corresponds to a port is read out, the contents of the port latch, instead of pin state, is read out. Accordingly, output data can correctly be read out without influence of external load, etc. (Refer to Figures 3.2.1 and 3.2.2) 3-4 7736 Group User's Manual PROGRAMMABLE I/O PORTS 3.1 Programmable I/O ports and Output-only ports b7 b6 b5 b4 b3 b2 b1 b0 Port Pi register (i = 0 to 10) (addresses 216,316,616,716,A16,B16,E16,F16,1216,1316,1616) Bit Bit name Functions At reset RW Undefined RW Undefined RW Undefined RW Undefined RW 0 Port Pi0's pin 1 Port Pi1's pin 2 Port Pi2's pin 3 Port Pi3's pin 4 Port Pi4's pin Undefined RW 5 Port Pi5's pin Undefined RW 6 Port Pi6's pin Undefined RW 7 Port Pi7's pin Undefined RW Data is input from or output to a pin by reading/writing from/to the corresponding bit. 0: "L" level 1: "H" level Notes 1: Writing to bits 4 to 7 of the port P3 register is invalid and these bits are fixed to "0" when they are read. 2: After reset, be sure to write data to the port P9 register. Fig. 3.1.3 Structure of port Pi (i = 0 to 10) register 7736 Group User's Manual 3-5 PROGRAMMABLE I/O PORTS 3.2 Port peripheral circuits 3.2 Port peripheral circuits Figures 3.2.1 and 3.2.2 show the port peripheral circuits. * Ports P00 to P07, P10 to P17, P20 to P27, P30 to P33, P43 to P46, P100 to P103 (Inside dotted-line not included) Ports P40/HOLD, P41/RDY, P47, P51/TA0IN, P53/TA1IN, P55/TA2IN, P57/TA3IN, P61/TA4IN, P65/TB0IN to P67/TB2IN/ (Inside dotted-line included) SUB, P86/RxD1 Port direction register Data bus Port latch *Ports P83/TxD0, P87/TxD1 (Inside dotted-line not included, and shaded area included) Ports P50/TA0OUT, P52/TA1OUT, P54/TA2OUT, P56/TA3OUT, P60/TA4OUT, P82/RxD0/CLKS0 (Inside dotted-line included, and shaded area not included) Ports P42/ 1 (Inside dotted-line not included, and shaded area not included) N-channel open-drain selection (Note 1) Port direction register Note 1: Valid only when used as pin TxDj for serial I/O. "1" Output Data bus Port latch *Ports P62/INT0 to P64/INT2 (Inside dotted-line included) Ports P104/KI0 to P107/KI3 (Inside dotted-line not included) Pull-up selection Port direction register Data bus Port latch Fig. 3.2.1 Port peripheral circuits (1) 3-6 7736 Group User's Manual Pull-up transistor PROGRAMMABLE I/O PORTS 3.2 Port peripheral circuits *Ports P70/AN0 to P77/AN7/XCIN Port direction register Data bus Port latch (Note 2) Sub-clock oscillation circuit Analog input Note 2: The sub-clock oscillation circuit is present only in ports P76 and P77 *Ports P80/CTS0/RTS0/CLKS1, P81/CLK0, P84/CTS1/RTS1, P85/CLK1 Port direction register "1" "0" Output Data bus Port latch *Ports P90/CTS2, P92/RXD2 (Inside dotted-line included) Ports P94 to P97 (Inside dotted-line not included) Output control Data bus Port latch *Port P91/CLK2 (Inside dotted-line included) Port P93/TXD2 (Inside dotted-line not included) Output control Output Data bus * E (External bus mode A) Port latch * E / RDE (External bus mode B) Hold acknowledge Fig. 3.2.2 Port peripheral circuits (2) 7736 Group User's Manual 3-7 PROGRAMMABLE I/O PORTS 3.3 Pull-up function 3.3 Pull-up function ___ ___ 3.3.1 Pull-up function for ___ ports P104 to P107 ( KI0 to KI3) ___ Ports P10 4 to P10 7 ( KI 0 to KI3 ) can be pulled high by setting the port P10 pull-up selection bit (bit 6 at address 6D16). Figure 3.3.1 shows the structure of the port function control register. When pulling ports P104 to P107 high, clear bits 4 to 7 at address 1816 (Port P10 direction register) to "0." ____ ____ 3.3.2 Pull-up function for ports P62 to P6 4 (INT 0 to INT2 ) ____ ____ Ports P6 2 and P63 ( INT0 and____ INT1 ) can be pulled high by setting the port P6 pull-up selection bit 0 (bit 3 at address 6D 16 ). Port P64 ( INT2 ) can be pulled high by setting the port P6 pull-up selection bit 1 (bit 5 at address 6D 16). Figure 3.3.1 shows the structure of the port function control register. When pulling ports P6 2 to P6 4 high, clear bits 2 to 4 at address 10 16 (port P6 direction register) to "0." 3-8 7736 Group User's Manual PROGRAMMABLE I/O PORTS 3.3 Pull-up function b7 b6 b5 b4 0 b3 b2 b1 b0 Port function control register (address 6D16) At reset RW 0 RW Sub-clock output selection bit/ *Port-XC selection bit = "0" (when the sub clock is not used) Timer B2 clock source selection Timer B2 (event counter mode) bit clock source selection (Note 1) 0: TB2IN input (event counter mode) 1: Main clock divided by 32 (clock timer) *Port-XC selection bit = "1" (when the sub clock is used) Sub-clock output selection 0: Pin P67/TB2IN/ SUB functions as a programmable I/O port. 1: Sub clock SUB is output from pin P67/TB2IN/ SUB. 0 RW 2 Timer B1 internal connect selection bit (Note 2) 0: No internal connection 1: Internal connection with timer B2 0 RW 3 Port P6 pull-up selection bit 0 0: No pull-up for pins P62/INT0 and P63/INT1 1: With pull-up for pins P62/INT0 and P63/INT1 0 RW 4 Must be fixed to "0." 0 RW 5 Port P6 pull-up selection bit 1 *Key input interrupt selection bit = "0" 0: No pull-up for pin P64/INT2 1: With pull-up for pin P64/INT2 *Key input interrupt selection bit = "1" 0: Pin P64/INT2 is a port with no pull-up. 1: Pin P64/INT2 is an input pin with pull-up and is used for the key input interrupt. 0 RW 6 Port P10 pull-up selection bit 0: No pull-up for pins P104/KI0 to P107/KI3 1: With pull-up for pins P104/KI0 to P107/KI3 0 RW 7 Key input interrupt selection bit 0: INT2 interrupt 1: Key input interrupt 0 RW Bit 0 1 Bit name Standby state selection bit Functions 0: Pins P0 to P3 are used for the external bus output. 1: Pins P0 to P3 are used for the port output. Port-Xc selection bit : Bit 4 of the oscillation circuit control register 0 (address 6C16) Notes 1: When the port-Xc selection bit = "0" and timer B2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: When timer B1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 to 2, 4 and 7 are not used for the pull-up function. Fig. 3.3.1 Structure of port function control register 7736 Group User's Manual 3-9 PROGRAMMABLE I/O PORTS 3.4 Internal peripheral devices' I/O functions (Ports P42, P5 to P8, P90 to P93 and P104 to P10 7) 3.4 Internal peripheral devices' I/O functions (Ports P42, P5 to P8, P90 to P93 and P104 to P107) Ports P4 2 , P5 to P8, P9 0 to P9 3 and P10 4 to P10 7 also function as I/O pins for the internal peripheral devices. Table 3.4.1 lists correspondence between each port and internal peripheral devices' I/O pin. For internal peripheral devices' I/O functions, refer to the corresponding functional description. For the clock 1 output pin, refer to chapter "12. CONNECTING EXTERNAL DEVICES." For the sub-clock oscillation circuit's I/O pins, refer to chapter "14. CLOCK GENERATING CIRCUIT." Table 3.4.1 Correspondence between each port and internal peripheral devices' I/O pin Port Internal peripheral devices' I/O pin P42 Clock 1 output pin P5 0, P60 , P61 Timer A's I/O pins P6 2 to P6 4 P65, P6 6 Input pins for external interrupts P67 Timer B's input pin/Clock SUB output pin P70, P7 5 P76, P7 7 A-D converter's input pins A-D converter's input pins/Sub-clock oscillation circuit's I/O pins P8, P9 0 to P9 3 I/O pins for serial I/O P10 4 to P10 7 Input pins for the key input interrupt function 3-10 Timer B's input pins 7736 Group User's Manual CHAPTER 4 INTERRUPTS 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Overview Interrupt sources Interrupt control Interrupt priority level Interrupt priority level detection circuit Interrupt priority level detection time How interrupts are processed (from acceptance of interrupt request till execution of interrupt routine) 4.8 Return from interrupt routine 4.9 Multiple interrupts ____ 4.10 External interrupts (INTi interrupt) 4.11 Precautions for interrupts INTERRUPTS Interrupts of the 7736 Group are the same as those of the 7733 Group. Therefore, for interrupts, refer to the corresponding sections in part 1: * "4.1 Overview (page 4-2 in part 1) * "4.2 Interrupt sources (page 4-4 in part 1) * "4.3 Interrupt control (page 4-6 in part 1) * "4.4 Interrupt priority level (page 4-10 in part 1) * "4.5 Interrupt priority level detection circuit (page 4-11 in part 1) * "4.6 Interrupt priority level detection time (page 4-13 in part 1) * "4.7 How interrupts are processed (from acceptance of interrupt request till execution of interrupt routine) (page 4-14 in part 1) * "4.8 Return from interrupt routine (page 4-17 in part 1) * "4.9 Multiple interrupts (page 4-17 in part 1) ____ * "4.10 External interrupts (INTi interrupt) (page 4-19 in part 1) * "4.11 Precautions for interrupts (page 4-23 in part 1) 4-2 7736 Group User's Manual CHAPTER 5 KEY INPUT INTERRUPT FUNCTION 5.1 Overview 5.2 Block description 5.3 Initial setting example for related registers KEY INPUT INTERRUPT FUNCTION 5.1 Overview The key input interrupt function is used to generate an interrupt request when one of the input levels of four or five pins falls. By using this function when terminating the stop or wait mode, the key-on wakeup can be realized. For the way to terminate the stop or wait mode, refer to section "17.4 Power saving." For the stop and wait modes, refer to chapter "11. STOP AND WAIT MODES." 5.1 Overview ___ ___ A key input interrupt request occurs when one of the input levels of pins KI 0 to KI 3 falls. Therefore, by configuring an external key___ matrix shown in Figure 5.1.1, an interrupt request can be generated only by ___ pushing a key. Pins KI0 to KI3 can be pulled high by software and the same function can also be___ selected ___ for port P64. Therefore, when using the key input interrupt function, whether to use four pins (pins KI0 to KI3) ___ ___ or five pins (pins KI0 to KI3 and____ P64 ) can be selected. The key input interrupt and the INT2 interrupt share the same interrupt vector addresses and interrupt control register. M37736MHBXXXFP Key matrix KI3 KI2 KI1 KI0 P64/INT2 P63 P62 P61 P60 Fig. 5.1.1 Key matrix example when key input interrupt function is used 5-2 7736 Group User's Manual KEY INPUT INTERRUPT FUNCTION 5.2 Block description 5.2 Block description Figure 5.2.1 shows the block diagram for the key input interrupt function. Port P6 pull-up selection bit 1 Port P64 direction register P64/INT2 INT2/Key input interrupt control register Port P6 pull-up selection bit 1 When key input interrupt is selected, it is necessary to select edge sense which uses falling edge. Port P10 pull-up selection bit Pull-up transistor Port P107 direction register (address 7F16) 0 P107/KI3 0 Pull-up transistor 1 Interrupt control register P106/KI2 request 1 Pull-up transistor INT2/Key input interrupt Key input interrupt selection bit P105/KI1 Pull-up transistor P104/KI0 Fig. 5.2.1 Block diagram for key input interrupt function ___ ___ ____ 5.2.1 Pins KI 0 to KI3 and P6 4 /INT 2 When the ___ key input interrupt function is selected, pins P10 4 to P10 7 become input pins for the key input ___ interrupt (KI 0 to KI 3). When selecting the key input interrupt function, clear all of bits 4 to 7 at address 18 16 (Port P10 direction register) to "0." ___ ___ When bits 4 to 7 at address 1616 (Port P10 register) are read out, the status of pins KI0 to KI3 can be read ____ in. When using pin P64/ INT2 as an input pin for the key input interrupt, set both of bits 5 and 7 at address 6D16 to "1" and bit 4 at address 1016 (Port P6 ____ direction register) to "0." When bit 4 at address E6 16 (Port P6 register) is read out, the status of pin P64/ INT 2 can be read in. b7 b6 0 0 b5 b4 b3 b2 b1 b0 0 0 Port P10 direction register (address 1816) 0: Must be set to "0." b7 b6 b5 b4 b3 b2 0 b1 b0 Port P6 direction register (address 1016) 0: Must be set to "0." Fig. 5.2.2 Port P10 and P6 direction registers when key input interrupt function is selected 7736 Group User's Manual 5-3 KEY INPUT INTERRUPT FUNCTION 5.2 Block description 5.2.2 Port function control register Figure 5.2.3 shows the structure of the port function control register. b7 b6 b5 b4 0 b3 b2 b1 b0 Port function control register (address 6D16) Bit Bit name Functions At reset RW 0 Standby state selection bit 0: Pins P0 to P3 are used for the external bus output. 1: Pins P0 to P3 are used for the port output. 0 RW 1 *Port-XC selection bit = "0" Sub-clock output selection bit/ (when the sub clock is not used) Timer B2 clock source selection Timer B2 (event counter mode) bit clock source selection(Note 1) 0: TB2IN input (event counter mode) 1: Main clock divided by 32 (clock timer) *Port-XC selection bit = "1" (when the sub clock is used) Sub-clock output selection 0: Pin P67/TB2IN/ SUB functions as a programmable I/O port. 1: Sub clock SUB is output from pin P67/TB2IN/ SUB. 0 RW 2 Timer B1 internal connect selection bit (Note 2) 0: No internal connection 1: Internal connection with timer B2 0 RW 3 Port P6 pull-up selection bit 0 0: No pull-up for pins P62/INT0 and P63/INT1 1: With pull-up for pins P62/INT0 and P63/INT1 0 RW 4 Must be fixed to "0." 0 RW 5 Port P6 pull-up selection bit 1 *Key input interrupt selection bit = "0" 0: No pull-up for pin P64/INT2 1: With pull-up for pin P64/INT2 *Key input interrupt selection bit = "1" 0: Pin P64/INT2 is a port with no pull-up. 1: Pin P64/INT2 is an input pin with pull-up and is used for the key input interrupt. 0 RW 6 Port P10 pull-up selection bit 0: No pull-up for pins P104/KI0 to P107/KI3 1: With pull-up for pins P104/KI0 to P107/KI3 0 RW 7 Key input interrupt selection bit 0: INT2 interrupt 1: Key input interrupt 0 RW Port-Xc selection bit : Bit 4 of the oscillation circuit control register 0 (address 6C16) Notes 1: When the port-Xc selection bit = "0" and timer B2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: When timer B1 operates in the event counter mode, bit 2 is valid. 3: represents that bits 0 to 4 are not used for the key input interrupt function. Fig. 5.2.3 Structure of port function control register 5-4 7736 Group User's Manual KEY INPUT INTERRUPT FUNCTION 5.2 Block description (1) Port P6 pull-up selection bit (bit 5) ____ When using pin P64/ INT 2 as an input pin for the key input interrupt, set this bit to "1." When this bit ____ is set to "1," pin P64 / INT 2 is pulled high. (2) Port P10 pull-up selection bit___ (bit 6) ___ This is a bit to pull pins KI0 to KI 3 high. When configuring a key matrix,___ there ___ is no need to connect pull-up transistors externally if this bit is set to "1," in other words, if pins KI0 to KI3 are set to be pulled high. (3) Key input interrupt selection bit (bit 7) This is a bit to select the key input interrupt function. ____ The key input interrupt and the INT2 interrupt share the same interrupt vector addresses and interrupt control register. When this bit is set to "1," the key input interrupt function is selected. When this bit ____ = "0," pin P6 4 / 2 = "1" and bit 5 (Port P6 pull-up selection bit ) INT is a programmable I/O port. (At this time, the INT 2 interrupt cannot be used.) When both of this bit and bit 5 (Port P6 pull-up selection bit 1) are "1," ____ pin P64 / INT2 can be used for the key input interrupt. 7736 Group User's Manual 5-5 _ KEY INPUT INTERRUPT FUNCTION 5.2 Block description 5.2.3 Interrupt function ____ The key input interrupt and the INT2 interrupt share the same interrupt vector addresses and interrupt control register. Specify addresses FFF016 and FFF116 (in order wor ds, the vector addresses for the INT 2 /key input interrupt) as the interrupt vector addresses; specify the INT2/key input interrupt control register (address 7F16) as the interrupt control register. Figure 5.2.4 shows the structure of the INT2/key input interrupt control register when the key input interrupt function is selected. The operation at accepting a key input interrupt request is the same as that at accepting an INT2 interrupt request. b7 b6 b5 b4 0 0 b3 b2 b1 b0 INT2/key input interrupt control register (address 7F16) Bit 0 At reset RW 0 0 0: Level 0 (Interrupt is disabled.) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 0 RW 0 RW 0 RW 0: No interrupt request has occurred. 1: Interrupt request has occurred. 0 RW 0 RW 0 RW Undefined - Undefined - Bit name Interrupt priority level selection bits 1 2 3 Interrupt request bit 4 Must be fixed to "0." Functions b2 b1 b0 5 6 Not implemented. 7 ____ Fig. 5.2.4 Structure of INT2/key input interrupt control register when key input interrupt function is selected 5-6 7736 Group User's Manual KEY INPUT INTERRUPT FUNCTION 5.3 Initial setting example for related registers 5.3 Initial setting example for related registers Figure 5.3.1 shows an initial setting example for registers related to the key input interrupt function. Selection of the key input interrupt function Pull-up selection for pins KI0 to KI3 b7 b0 1 Port function control register (address 6D16) 0 Port P6 pull-up selection bit 1 0: Port P64 is a programmable I/O port with no pull-up. 1: Port P64 is an input pin with pull-up and is used for the key input interrupt. Port P10 pull-up selection bit 0: No pull-up 1: Pull-up Selection of the key input interrupt function Setting of the interrupt priority level b7 b0 0 0 0 INT2/Key input interrupt control register (address 7F16) Interrupt priority level selection bits One of levels 1 to 7 must be set. Interrupt request bit Setting of port P10 and P6 direction registers b7 0 b0 0 0 Port P10 direction register (address 1816) 0 P104 to P107 are set to the input mode. (Must be set to "0000.") b7 b0 0 Port P6 direction register (address 1016) When setting P64 as an input pin for the key input interrupt, set this bit to "0." In order to enable the key input interrupt, the interrupt disable flag (I) must be set to "0" and the processor interrupt priority level (IPL) must be a value smaller than the INT2/key input interrupt's priority level. (Refer to chapter "4. INTERRUPTS" in part 1.) Fig. 5.3.1 Initial setting example for registers related to key input interrupt function 7736 Group User's Manual 5-7 KEY INPUT INTERRUPT FUNCTION 5.3 Initial setting example for related registers MEMO 5-8 7736 Group User's Manual CHAPTER 6 TIMER A 6.1 6.2 6.3 6.4 6.5 6.6 Overview Block description Timer mode Event counter mode One-shot pulse mode Pulse width modulation (PWM) mode TIMER A Timer A of the 7736 Group is the same as that of the 7733 Group. Therefore, for timer A, refer to the corresponding sections in part 1: * "6.1 Overview" (page 6-2 in part 1) * "6.2 Block description" (page 6-3 in part 1) * "6.3 Timer mode" (page 6-9 in part 1) * "6.4 Event counter mode" (page 6-19 in part 1) * "6.5 One-shot pulse mode" (page 6-32 in part 1) * "6.6 Pulse width modulation (PWM) mode" (page 6-41 in part 1) 6-2 7736 GROUP USER'S MANUAL CHAPTER 7 TIMER B 7.1 7.2 7.3 7.4 7.5 Overview Block description Timer mode Event counter mode Pulse period/Pulse width measurement mode 7.6 Clock timer TIMER B Timer B of the 7736 Group is the same as that of the 7733 Group. Therefore, for timer B, refer to the corresponding sections in part 1: * "7.1 Overview" (page 7-2 in part 1) * "7.2 Block description" (page 7-3 in part 1) * "7.3 Timer mode" (page 7-10 in part 1) * "7.4 Event counter mode" (page 7-17 in part 1) * "7.5 Pulse period/Pulse width measurement mode" (page 7-25 in part 1) * "7.6 Clock timer" (page 7-34 in part 1) 7-2 7736 GROUP USER'S MANUAL CHAPTER 8 SERIAL I/O 8.1 Overview 8.2 Block description 8.3 Clock synchronous serial I/O mode 8.4 Clock asynchronous serial I/O (UART) mode SERIAL I/O 8.2 Block description In the 7736 Group, the UART2's input pins are independent of pins P72 to P7 5 and are multiplexed with pins P9 0 to P9 3. Therefore, concerning chapter "8. SERIAL I/O," the 7736 Group differs from the 7733 Group in the following sections. Only the differences are described in this chapter: * "8.2 Block description" * "8.3 Clock synchronous serial I/O mode" * "8.4 Clock asynchronous serial I/O (UART) mode" The following section of the 7736 Group is the same as that of the 7733 Group. Therefore, refer to part 1: * "8.1 Overview"(page 8-2 in part 1) 8.2 Block description Concerning section "8.2 Block description," the 7736 Group differs from the 7733 Group in the following: * 8.2.9 Port P8 direction register The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "8.2 Block description" (page 8-4 in part 1) 8-2 7736 Group User's Manual SERIAL I/O 8.2 Block description 8.2.9 Port P8 direction register I/O pins of UARTi are multiplexed with ports P8 and P9. When using pins P82 and P86 as serial data input pins (RxDi), set the corresponding bits of the port P8 direction register to "0" to set this port for the input _________ _________ mode. When using pins P80, P81, P83-P85 and P87 as UARTi's I/O pins (CTSi/RTSi, CLKi, TxDi), these pins are forcibly set as the UARTi's I/O pins, regardless of the port P8 direction register's contents. Also, as for CLKS0 and CLKS 1, refer to section "8.3.1 (4) Number of transfer clock output pins (UART0)" in part 1. Figure 8.2.16 shows the relationship between the port P8 direction register and UARTi's I/O pins. When using UART2, pins P90 -P93 are forcibly set as the UART2's input or output pins. Note that the functions of the UARTi's I/O pins can be switched by software. For details, refer to the description of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 Port P8 direction register (address 1416) At reset RW 0: Input mode 1: Output mode 0 RW 0 RW When using pins P82 and P86 as serial data's input pins (RxD0, RxD1), set the corresponding bits to "0." 0 RW 0 RW 0 RW Pin P85/CLK1 0 RW 6 Pin P86/RxD1 0 RW 7 Pin P87/TxD1 0 RW Bit Corresponding pin name 0 Pin P80/CTS0/RTS0/CLKS1 1 Pin P81/CLK0 2 Pin P82/RxD0/CLKS0 3 Pin P83/TxD0 4 Pin P84/CTS1/RTS1 5 Functions Note: For pins CLKS0 and CLKS1, refer to section "8.3.1 (4) Number of transfer clock output pins (UART0)" in part 1. Fig. 8.2.16 Relationship between port P8 direction register and UARTi's I/O pins 7736 Group User's Manual 8-3 SERIAL I/O 8.3 Clock synchronous serial I/O mode 8.3 Clock synchronous serial I/O mode Concerning section "8.3 Clock synchronous serial I/O mode," the 7736 Group differs from the 7733 Group in the following: * Table 8.3.2 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "8.3 Clock synchronous serial I/O mode" (page 8-21 in part 1) Table 8.3.2 Functions of I/O pins in clock synchronous serial I/O mode Pin name TxDi Functions Serial data output Method of selection (They output dummy data when only reception is performed.) Port P8 direction register's corresponding bits ="0" (It can be used as an input port when only transmission is performed.) (P8 3 , P87, P93) Serial data input RxD 0 (P8 2), RxD 1 (P8 6) RxD 2 (P9 2) (It can be used as an output port when only transmission is performed.) Internal/External clock selection bit = "0" CLKi Internal/External clock selection bit = "1" (P8 1 , P85, P91) ____ ____ CTS / RTS enable bit = "0" CTS 0/RTS 0 (P8 0), ____ ____ CTS/ RTS function selection bit = "0" CTS 1/RTS 1 (P8 4) ____ ____ ____ RTS output CTS / RTS enable bit = "0" (Note 1) ____ ____ CTS/ RTS function selection bit = "1" ____ ____ Programmable I/O port CTS / RTS enable bit = "1" ____ ____ CTS input CTS enable bit = "0" CTS2 (P90 ) ____ Programmable I/O port CTS enable bit = "1" Port P8 direction register: Address 14 16 Internal/External clock selection bit: Bit 3 at addresses 30 16, 38 16, and 64 16 ____ ____ CTS / RTS enable bit: Bit 4 at addresses 34 16 and 3C 16 ____ ____ CTS / RTS function selection bit: Bit 2 at addresses 3416 and 3C 16 ____ CTS enable bit: Bit 2 at address 6816 Pin TxDi outputs "H" level from when a UARTi's operating mode is selected until transfer starts. (Pin TxDi is in a floating state when N-channel open-drain output is selected.) In UART0, multiple transfer clock output pins can be used. (Refer to Table 8.3.3 in part 1.) Transfer clock output Transfer clock input ____ CTS input ____ Notes 1: The RTS output function is not assigned for UART2. 2: As for CLKS 0 and CLKS 1, refer to section "8.3.1 (4) Number of transfer clock output pins (UART0)" in part 1. 8-4 7736 Group User's Manual SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode 8.4 Clock asynchronous serial I/O (UART) mode Concerning section "8.4 Clock asynchronous serial I/O (UART) mode," the 7736 Group differs from the 7733 Group in the following: * Table 8.4.2 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "8.4 Clock asynchronous serial I/O (UART) mode" (page 8-44 in part 1) Table 8.4.2 Functions of I/O pins in UART mode Pin name TxDi (P8 3, P87 , P93) RxD 0 (P82), RxD 1 (P8 6) RxD 2 (P9 2) Method of selection Functions Serial data output Serial data input (They cannot be used as programmable I/O ports.) Port P8 direction register's corresponding bit = "0" (It can be used as an input port when only transmission is performed.) (It can be used as an output port when only transmission is performed.) Programmable I/O port Internal/External clock selection bit = "0" CLKi (P8 1, P85 , P91) BRGi count source input Internal/External clock selection bit = "1" ____ ____ ____ CTS / RTS enable bit = "0" CTS 0/ RTS 0 (P8 0) CTS input ____ ____ CTS / RTS function selection bit = "0" CTS 1/ RTS 1 (P8 4) ____ ____ ____ CTS / RTS enable bit = "0" RTS output (Note) ____ ____ CTS / RTS function selection bit = "1" ____ ____ CTS2 (P90) Programmable I/O port CTS / RTS enable bit = "1" ____ ____ CTS enable bit = "0" CTS input ____ Programmable I/O port CTS enable bit = "1" Port P8 direction register: Address 14 16 Internal/External clock selection bit: Bit 3 at addresses 30 16 , 3816 , and 64 16 ____ ____ CTS / RTS enable bit: Bit 4 at addresses 34 16 and 3C 16 ____ ____ CTS/ RTS function selection bit: Bit 2 at addresses 3416 and 3C 16 ____ CTS enable bit: Bit 2 at addresses 68 16 Pin TxDi outputs "H" level while not transmitting after a UARTi's operating mode is selected. (Pin TxDi____ is in a floating state when N-channel open-drain output is selected.) Note: The RTSi output function is not assigned for UART2. 7736 Group User's Manual 8-5 SERIAL I/O 8.4 Clock asynchronous serial I/O (UART) mode MEMO 8-6 7736 Group User's Manual CHAPTER 9 A-D CONVERTER 9.1 9.2 9.3 9.4 Overview Block description A-D conversion method Absolute accuracy and Differential non-linearity error 9.5 One-shot mode 9.6 Repeat mode 9.7 Single sweep mode 9.8 Repeat sweep mode 9 . 9 Precautions for A - D converter A-D CONVERTER 9.1 Overview In the 7736 Group, the A-D converter's input pins are independent of UART2's I/O pins. Therefore, concerning chapter "9. A-D CONVERTER," the 7736 Group differs from the 7733 Group in the following section. Only the differences are described in this chapter: * "9.2 Block description" The following sections of the 7736 group are the same as those of the 7733 Group. Therefore, refer to part 1: * "9.1 Overview" (page 9-2 in part 1) * "9.3 A-D conversion method" (page 9-11 in part 1) * "9.4 Absolute accuracy and Differential non-linearity error" (page 9-14 in part 1) * "9.5 One-shot mode" (page 9-17 in part 1) * "9.6 Repeat mode" (page 9-20 in part 1) * "9.7 Single sweep mode" (page 9-23 in part 1) * "9.8 Repeat sweep mode" (page 9-27 in part 1) * "9.9 Precautions for A-D converter" (page 9-31 in part 1) 9.2 Block description Concerning section "9.2 Block description," the 7736 Group differs from the 7733 Group in the following: * 9.2.5 Port P7 direction register The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "9.2 Block description" (page 9-3 in part 1) 9-2 7736 Group User's Manual A-D CONVERTER 9.2 Block description 9.2.5 Port P7 direction register Input pins of the A-D converter are multiplexed with port P7. When using these pins as A-D converter's input pins, set the corresponding bits of the port P7 direction register to "0" to set these ports for the input mode. Figure 9.2.6 shows the relationship between the port P7 direction register and I/O pins of the subclock oscillation circuit and peripheral functions. b7 b6 b5 b4 b3 b2 b1 b0 Port P7 direction register (address 1116) Bit Corresponding bit's name 0 Pin AN0 1 Pin AN1 Functions 0: Input mode 1: Output mode When using these pins as A-D converter's input pins, set the corresponding bits to "0." At reset RW 0 RW 0 RW 0 RW 2 Pin AN2 3 Pin AN3 0 RW 4 Pin AN4 0 RW 5 Pin AN5/ADTRG 0 RW 6 Pin AN6/XCOUT 0 RW Pin AN7/XCIN 0 RW 7 Fig. 9.2.6 Relationship between port P7 direction register and I/O pins of sub-clock oscillation circuit and peripheral functions Analog input pins AN6 and AN7 function as the port P7's I/O pins and also function as I/O pins of the subclock oscillation circuit. For the pin which is forcedly set to the output mode when the function for the subclock oscillation circuit is selected, analog input is disabled. (Refer to "Table 9.2.3.") Table 9.2.3 Port P7's pin which is forcedly set to output mode Pin P76/AN6/XCOUT Conditions where pin is forcedly set to output mode Sub-clock oscillation circuit is operating by itself. (bit 4 at address 6C 16 = "1" and bit 2 at address 6F 16 = "0" ) 7736 Group User's Manual 9-3 A-D CONVERTER 9.2 Block description MEMO 9-4 7736 Group User's Manual CHAPTER 10 WATCHDOG TIMER 10.1 Block description 10.2 Operation description 10.3 Precautions for watchdog timer WATCHDOG TIMER 10.2 Operation description Concerning chapter "10. WATCHDOG TIMER," the 7736 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter: * "10.2 Operation description" The following sections of the 7736 Group are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1: * "10.1 Block description" (page 10-2 in part 1) * "10.3 Precautions for watchdog timer" (page 10-10 in part 1) 10.2 Operation description Concerning section "10.2 Operation description," the 7736 Group differs from the 7733 Group in the following: * Figure 10.2.2 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "10.2 Operation description" (page 10-5 in part 1) b7 b6 b5 b4 b3 0 b2 b1 b0 Oscillation circuit control register 1 (address 6F16) Bit Bit name Functions At reset RW 0 Main clock division selection bit 0: Main clock is divided by 2. (Note 1) 1: Main clock is not divided by 2. 0 RW 1 Main clock external input selection bit 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating (Note 1) stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. 0 RW 2 Sub clock external input selection bit 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT. (Note 1) Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. 0 RW 3 This bit is ignored. 1 RW 4 Must be fixed to "0" (Note 2). 0 RW 5 Not implemented. Undefined -- 6 Not implemented. Undefined -- 7 Clock prescaler reset bit 0 WO By writing "1" to this bit, clock prescaler is initialized. Notes 1: When writing to this register, follow the procedure shown in Figure 10.2.3 in part 1. 2: The case where data "010101012" is written with the procedure shown in Figure 10.2.3 in part 1 is not included. 3: represents that bits 3 to 7 are not used for the watchdog timer. Fig. 10.2.2 Structure of oscillation circuit control register 1 10-2 7736 Group User's Manual CHAPTER 11 STOP AND WAIT MODES 11.1 11.2 11.3 11.4 Overview Clock generating circuit Stop mode Wait mode STOP AND WAIT MODES 11.2 Clock generating circuit Concerning chapter "11. STOP AND WAIT MODES" of the 7736 Group, description differs depending on the external bus mode. In external bus mode A, refer to the corresponding sections in part 1; in external bus mode B, refer to the corresponding sections in part 2. Note that, for the structure of the oscillation circuit control register 1, refer to Figure 11.2.3 in part 3. * "11.1 Overview" External bus modes A and B (page 11-2 in part 1) * "11.2 Clock generating circuit" External bus mode A (page 11-3 in part 1) External bus mode B (page 11-2 in part 2) * "11.3 Stop mode" External bus mode A (page 11-6 in part 1) External bus mode B (page 11-3 in part 2) * "11.4 Wait mode" External bus mode A (page 11-13 in part 1) External bus mode B (page 11-6 in part 2) b7 b6 b5 b4 b3 0 b2 b1 b0 Oscillation circuit control register 1 (address 6F16) Bit Bit name Functions At reset RW 0 Main clock division selection bit 0: Main clock is divided by 2. (Note 1) 1: Main clock is not divided by 2. 0 RW 1 Main clock external input selection bit 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating (Note 1) stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. 0 RW 2 Sub clock external input selection bit 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT. (Note 1) Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. 0 RW 3 This bit is ignored. 1 RW 4 Must be fixed to "0" (Note 2). 0 RW 5 Not implemented. Undefined -- 6 Not implemented. Undefined -- 7 Clock prescaler reset bit 0 WO By writing "1" to this bit, clock prescaler is initialized. Notes 1: When writing to this register, follow the procedure shown in Figure 11.2.4 in part 1. 2: The case where data "010101012" is written with the procedure shown in Figure 11.2.4 in part 1 is not included. 3: represents that bits 3 to 7 are not used for the stop and wait modes. Fig. 11.2.3 Structure of oscillation circuit control register 1 11-2 7736 Group User's Manual CHAPTER 12 CONNECTING EXTERNAL DEVICES 12.1 Signals required for accessing external devices 12.2 Software wait 12.3 Ready function 12.4 Hold function CONNECTING EXTERNAL DEVICES Concerning chapter "12. CONNECTING EXTERNAL DEVICES," the 7736 Group differs depending on the external bus mode. In external bus mode A, refer to the corresponding sections in part 1; in external bus mode B, refer to the corresponding sections in part 2. * "12.1 Signals required for accessing external devices" External bus mode A (12-2 in part 1) External bus mode B (page 12-3 in part 2) * "12.2 Software wait" External bus mode A (page 12-13 in part 1) External bus mode B (page 12-16 in part 2) * "12.3 Ready function" External bus mode A (page 12-16 in part 1) External bus mode B (page 12-19 in part 2) * "12.4 Hold function" External bus mode A (page 12-19 in part 1) External bus mode B (page 12-23 in part 2) 12-2 7736 Group User's Manual CHAPTER 13 RESET 13.1 Hardware reset 13.2 Software reset RESET 13.1 Hardware reset Concerning chapter "RESET," the 7736 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter: * "13.1 Hardware reset" The following section of the 7736 Group is the same as that of the 7733 Group. Therefore, for this section, refer to part 1: * "13.2 Software reset" (page 13-12 in part 1) 13.1 Hardware reset Concerning section "13.1 Hardware reset," the 7736 Group differs from the 7733 Group in the following: * Table 13.1.1 * Figure 13.1.6 for external bus mode B (Note) The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "13.1 Hardware reset" (page 13-2 in part 1) Note: In external bus mode A, Figure 13.1.6 of the 7736 Group is the same as that of the 7733 Group. ______ Table 13.1.1 Pin state while pin RESET is at "L" level Mask ROM version Pin CNVss's level Vss or Vcc Pin (Port) name P0 to P10 _ ____ E/RDE Built-in PROM version Vss P0 to P10 _ ____ E/RDE Vss P0, P1, P3 to P10 P2 _ ____ E/RDE 13-2 7736 Group User's Manual Pin state Floating "H" level is output. Floating "H" level is output. Floating *Floating when "H" level is applied to both or one of pins P51 and P52 *"H" or "L" level is output when "L" level is applied to both of pins P5 1 and P5 2. "H" level is output. RESET 13.1 Hardware reset Figure 13.1.6 for the 7736 Group differs from that for the 7733 Group only in bit 3 at address 6F 16 . Address Register name b7 6016 6116 Watchdog timer frequency selection flag (Reserved area) 3 6216 Memory allocation control register 6316 6416 UART2 transmit/receive mode register UART2 baud rate register (BRG2) 6516 6616 UART2 transmission buffer register 6716 6816 UART2 transmit/receive control register 0 6916 UART2 transmit/receive control register 1 6A16 UART2 receive buffer register 6B16 Oscillation circuit control register 0 6C16 Port function control register 6D16 Serial transmit control register 6E16 Oscillation circuit control register 1 6F16 WO 7016 A-D / UART2 trans./rece. interrupt control register 7116 UART0 transmission interrupt control register 7216 UART0 receive interrupt control register 7316 UART1 transmission interrupt control register 7416 UART1 receive interrupt control register Timer A0 interrupt control register 7516 Timer A1 interrupt control register 7616 Timer A2 interrupt control register 7716 Timer A3 interrupt control register 7816 Timer A4 interrupt control register 7916 Timer B0 interrupt control register 7A16 Timer B1 interrupt control register 7B16 Timer B2 interrupt control register 7C16 INT0 interrupt control register 7D16 INT1 interrupt control register 7E16 2 /Key input interrupt control register INT 7F16 Access characteristics b0 State immediately after reset b0 b7 WO Watchdog timer register RW RW RW WO WO RO RO WO RW RW RO RW ? ? 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 ? RO RW(2) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RO RW ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? ? ? 0 0 0 ? (1) ? ? 0 0 0 0 ? ? ? 1 0 0 ? 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 ? 0 ? 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value "FFF16" is set to the watchdog timer. (Refer to chapter "10. WATCHDOG TIMER" in part 1.) 2 For access characteristics at address 6C16, also refer to Figure 14.3.2 in part 1. 3 Do not write data to address 6216. Internal RAM area (M37736MHBXXXFP: addresses 8016 to FFF16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset. When the stop or wait mode is terminated (when hardware reset is applied)...Retains the state immediately before the STP or WIT instruction is executed. Fig. 13.1.6 State of SFR area and internal RAM area immediately after reset (4) 7736 Group User's Manual 13-3 RESET 13.1 Hardware reset MEMO 13-4 7736 Group User's Manual CHAPTER 14 CLOCK GENERATING CIRCUIT 14.1 Overview 14.2 Oscillation circuit example 14.3 Clock control CLOCK GENERATING CIRCUIT 14.3 Clock control Concerning chapter "14. CLOCK GENERATING CIRCUIT," the 7736 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter: * "14.3 Clock control" The following sections of the 7736 Group are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1: * "14.1 Overview" (page 14-2 in part 1) * "14.2 Oscillation circuit example" (page 14-3 in part 1) 14.3 Clock control Concerning section "14.3 Clock control," the 7736 Group differs from that of the 7733 Group in the following: * Figure 14.3.3 The other description is the same as that of the 7733 Group. Therefore, refer to part 1. * "14.3 Clock control" (page 14-5 in part 1) b7 b6 b5 b4 b3 0 b2 b1 b0 Oscillation circuit control register 1 (address 6F16) Bit Bit name Functions At reset RW 0 Main clock division selection bit 0: Main clock is divided by 2. (Note 1) 1: Main clock is not divided by 2. 0 RW 1 Main clock external input selection bit 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when terminating (Note 1) stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. 0 RW 2 Sub clock external input selection bit (Note 1) 0 RW 3 This bit is ignored. 1 RW 4 Must be fixed to "0" (Note 2). 0 RW 5 Not implemented. Undefined -- 6 Not implemented. Undefined -- 7 Clock prescaler reset bit 0 WO 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT. Watchdog timer is used when terminating stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. By writing "1" to this bit, clock prescaler is initialized. Notes 1: When writing to this register, follow the procedure shown in Figure 14.3.4 in part 1. 2: The case where data "010101012" is written with the procedure shown in Figure 14.3.4 in part 1 is not included. 3: represents that bits 3 to 7 are not used for the clock generating circuit. Fig. 14.3.3 Structure of oscillation circuit control register 1 14-2 7736 Group User's Manual CHAPTER 15 ELECTRICAL CHARACTERISTICS 15.1 Absolute maximum ratings 15.2 Recommended operating conditions 15.3 Electrical characteristics 15.4 A-D converter characteristics 15.5 Internal peripheral devices 15.6 Ready and Hold 15.7 Single-chip mode 15.8 Memory expansion mode and Microprocessor mode : with no wait 15.9 Memory expansion mode and Microprocessor mode : with wait 1 15.10 Memory expansion mode and Microprocessor mode : with wait 0 15.11 Measuring circuit for ports P0 to P10 and pins 1 _ and E ELECTRICAL CHARACTERISTICS 15.1 Absolute maximum ratings Electrical characteristics of the M37736MHBXXXGP are described in this chapter. Concerning chapter "15. ELECTRICAL CHARACTERISTICS," the 7736 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter: * "15.1 Absolute maximum ratings" * "15.2 Recommended operating conditions" * "15.3 Electrical characteristics" * "15.7 Single-chip mode" _ * "15.11 Measuring circuit for ports P0 to P10 and pins 1 and E " The following sections of the 7736 Group differ depending on the external bus mode. In external bus mode A, refer to the corresponding sections in part 1; in external bus mode B, refer to the corresponding sections in part 2. * "15.6 Ready and Hold" External bus mode A (page 15-11 in part 1) External bus mode B (page 15-3 in part 2) * "15.8 Memory expansion mode and Microprocessor mode : with no wait" External bus mode A (page 15-15 in part 1) External bus mode B (page 15-5 in part 2) * "15.9 Memory expansion mode and Microprocessor mode : with wait 1" External bus mode A (page 15-17 in part 1) External bus mode B (page 15-7 in part 2) * "15.10 Memory expansion mode and Microprocessor mode : with wait 0" External bus mode A (page 15-19 in part 1) External bus mode B (page 15-9 in part 2) The following sections of the 7736 Group are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1: * "15.4 A-D converter characteristics" (page 15-5 in part 1) * "15.5 Internal peripheral devices" (page 15-6 in part 1) 15.1 Absolute maximum ratings Absolute maximum ratings Symbol Parameter Vcc Power source voltage AVcc Analog power source voltage VI Input voltage RESET, CNVss, BYTE Input voltage P00-P07, P10-P17, P20-P27, P30-P33, VI P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P100-P107, VREF, XIN, BSEL Output voltage P00-P07, P10-P17, P20-P27, P30-P33, VO P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P90-P97, P100-P107, XOUT, E Power dissipation Pd Operating temperature Topr Storage temperature Tstg 15-2 Conditions Ta = 25 C 7736 Group User's Manual Ratings -0.3 to 7 -0.3 to 7 -0.3 to 12 Unit V V V -0.3 to Vcc+0.3 V -0.3 to Vcc+0.3 V 300 -20 to 85 -40 to 150 mW C C ELECTRICAL CHARACTERISTICS 15.2 Recommended operating conditions 15.2 Recommended operating conditions Recommended operating conditions (Vcc = 5 V 10 %, Ta = -20 to 85 C, unless otherwise noted) Limits Unit Symbol Parameter Typ. Min. Max. 4.5 5.5 5.0 f(XIN) :Operating Power source voltage Vcc V 2.7 5.5 f(XIN) :Stopped, f(XCIN) = 32.768 kHz Vcc Analog power source voltage AVcc V 0 Power source voltage Vss V 0 Analog power source voltage AVss V P00-P07, P30-P33, P40-P47, High-level input voltage P50-P57, P60-P67, P70-P77, 0.8 Vcc Vcc VIH V P80-P87, P100-P107, XIN, RESET, CNVss, BYTE, BSEL, XCIN (Note 3) High-level input voltage P10-P17, P20-P27 0.8 Vcc Vcc VIH V (in single-chip mode) P10-P17, P20-P27 High-level input voltage 0.5 Vcc (in memory expansion mode and Vcc VIH V microprocessor mode) P00-P07, P30-P33, P40-P47, Low-level input voltage P50-P57, P60-P67, P70-P77, 0 0.2 Vcc VIL V P80-P8 7, P100-P107, X IN, RESET, CNVss, BYTE, BSEL, XCIN (Note 3) P10-P17, P20-P27 Low-level input voltage 0 0.2 Vcc VIL V (in single-chip mode) P10-P17, P20-P27 Low-level input voltage 0 (in memory expansion mode and 0.16 Vcc VIL V microprocessor mode) P00-P07, P10-P17, P20-P27, High-level peak output current P30-P33, P40-P47, P50-P57, -10 IOH (peak) mA P60-P67, P70-P77, P80-P87, P90-P97, P100-P107 High-level average output current P00-P07, P10-P17, P20-P27, P30-P33, P40-P47, P50-P57, -5 IOH (avg) mA P60-P67, P70-P77, P80-P87, P90-P97, P100-P107 P00-P07, P10-P17, P20-P27, Low-level peak output current P30-P33, P40-P43, P50-P57, 10 IOL (peak) mA P60-P67, P70-P77, P80-P87, P90-P97, P104-P107 Low-level peak output current P44-P47, P100-P103 20 IOL (peak) mA P0 0 -P0 7 , P1 0 -P1 7 , P2 0 -P2 7 , Low-level average output current P30-P33, P40-P43, P50-P57, 5 IOL (avg) mA P60-P67, P70-P77, P80-P87, P90-P97, P104-P107 Low-level average output current P44-P47, P100-P103 15 IOL (avg) mA Main-clock oscillation frequency (Note 4) 25 f(XIN) MHz Sub-clock oscillation frequency 32.768 50 f(XCIN) kHz Notes 1: Average output current is the average value in an interval of 100 ms. 2: The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less. 3: Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = "1." 4: The maximum value of f(XIN) = 12.5 MHz when the main clock division selection bit = "1." 7736 Group User's Manual 15-3 ELECTRICAL CHARACTERISTICS 15.3 Electrical characteristics 15.3 Electrical characteristics Electrical characteristics (Vcc = 5 V, Vss = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz, unless otherwise noted) Limits Symbol Parameter Measuring conditions Unit Min. Typ. Max. High-level output voltage P00-P07, P10-P17, P20-P27, VOH P33, P40-P47, P50-P57, V 3 P60-P67, P70-P77, P80-P87, IOH = -10 mA P90-P97, P100-P107 High-level output voltage P00-P07, P10-P17, P20-P27, IOH = -400 A V VOH 4.7 P33 IOH = -10 mA 3.1 High-level output voltage V VOH IOH = -400 A 4.8 P30-P32 IOH = -10 mA 3.4 High-level output voltage V VOH IOH = -400 A 4.8 E Low-level output voltage P00-P07, P10-P17, P20-P27, VOL P33, P40-P43, P50-P57, P60-P67, P70-P75, P80-P87, IOL = 10 mA 2 V P90-P97, P104-P107 IOL = 20 mA VOL Low-level output voltage P44-P47, P100-P103 2 V Low-level output voltage P00-P07, P10-P17, P20-P27, IOL = 2 mA VOL 0.45 V P33 IOL = 10 mA Low-level output voltage 1.9 V VOL IOL = 2 mA P30-P32 0.43 IOL = 10 mA Low-level output voltage 1.6 V VOL E IOL = 2 mA 0.4 HOLD, RDY, TA0IN-TA4IN, TB0IN-TB2IN, Hysteresis INT0-INT2, ADTRG, CTS0, CTS1, CTS2, CLK0, VT+-VT- 0.4 1 V CLK1, CLK2, KI0-KI3 VT+-VT- Hysteresis 0.2 RESET 0.5 V VT+-VT- Hysteresis 0.1 XIN 0.4 V VT+-VT- Hysteresis 0.1 XCIN (When external clock is input) 0.4 V High-level input current P00-P07, P10-P17, P20-P27, P30-P33, P40-P47, P50-P57, 5 A IIH P60-P67, P70-P77, P80-P87, VI = 5 V P10 0 -P10 7 , X IN , RESET , CNVss, BYTE, BSEL Low-level input current P00-P07, P10-P17, P20-P27, P30-P33, P40-P47, P50-P53, IIL P60, P61, P65- P67, P70-P77, VI = 0 V -5 A P8 0 -P8 7 , P10 0 -P10 3 , X IN , RESET, CNVss, BYTE, BSEL VI = 0 V, Low-level input current P62-P64, P104-P107, -5 A without a pull-up transistor IIL VI = 0 V, -0.25 -0.5 -1.0 mA with a pull-up transistor When clock is stopped V 2 VRAM RAM hold voltage 15-4 7736 Group User's Manual ELECTRICAL CHARACTERISTICS 15.3 Electrical characteristics 15.4 A-D converter characteristics ELECTRICAL CHARACTERISTICS (Vcc= 5 V, Vss = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter Measuring conditions Min. Limits Typ. Max. Unit Vcc = 5 V, f(XIN) = 25 MHz (Square waveform), (f(f2) = 12.5 MHz), 9.5 19 mA f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 5V, f(XIN) = 25 MHz (Square waveform), (f(f2) = 1.5625 MHz), 1.3 2.6 mA f(XCIN) : Stopped, in operating (Note 1) In single-chip Vcc = 5V, mode, output pins f(XIN) = 25 MHz (Square waveform), are open, and the 10 20 A Power source f(XCIN) = 32.768 kHz, ICC other pins are concurrent when the WIT instruction is executed (Note 2) nected to Vss. Vcc = 5 V, f(XIN) : Stopped, 50 100 A f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 5 V, f(XIN) : Stopped, 5 10 A f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 C, 1 A when clock is stopped Ta = 85 C, 20 A when clock is stopped Notes 1: This is applied when the main clock external input selection bit = "1," the main clock division selection bit = "0," and the signal output disable selection bit = "1." 2: This is applied when the main clock external input selection bit = "1" and the system clock stop selection bit at wait state = "1." 3: This is applied when the CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the XCOUT drivability selection bit = "0" and the system clock stop bit at wait state = "1." 7736 Group User's Manual 15-5 ELECTRICAL CHARACTERISTICS 15.7 Single-chip mode 15.7 Single-chip mode Timing requirements (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(X IN) = 25 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Symbol Parameter Unit Min. Max. External clock input cycle time (Note 2) ns tc 40 External clock input high-level pulse width (Note 3) ns tw(H) 15 External clock input low-level pulse width (Note 3) ns tw(L) 15 External clock rise time ns tr 8 External clock fall time ns tf 8 Port P0 input setup time ns tsu(P0D-E) 60 Port P1 input setup time ns tsu(P1D-E) 60 Port P2 input setup time ns tsu(P2D-E) 60 Port P3 input setup time ns tsu(P3D-E) 60 Port P4 input setup time ns tsu(P4D-E) 60 Port P5 input setup time ns tsu(P5D-E) 60 Port P6 input setup time ns tsu(P6D-E) 60 tsu(P7D-E) Port P7 input setup time ns 60 tsu(P8D-E) Port P8 input setup time ns 60 tsu(P10D-E) Port P10 input setup time ns 60 ns th(E-P0D) Port P0 input hold time 0 ns th(E-P1D) Port P1 input hold time 0 Port P2 input hold time ns th(E-P2D) 0 Port P3 input hold time ns th(E-P3D) 0 Port P4 input hold time ns th(E-P4D) 0 ns Port P5 input hold time th(E-P5D) 0 ns Port P6 input hold time th(E-P6D) 0 ns Port P7 input hold time th(E-P7D) 0 Port P8 input hold time ns th(E-P8D) 0 Port P10 input hold time ns th(E-P10D) 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 80 ns. 3: When the main clock division selection bit = "1," values of tw (H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Switching characteristics (Vcc = 5 V 10 %, Vss = 0 V, Ta = -20 to 85 C, f(XIN) = 25 MHz (Note), unless otherwise noted) Limits Symbol Parameter Measuring conditions Min. Max. Unit td(E-P0Q) Port P0 data output delay time ns 80 td(E-P1Q) Port P1 data output delay time ns 80 td(E-P2Q) Port P2 data output delay time ns 80 td(E-P3Q) Port P3 data output delay time ns 80 Fig. 15.11.1 td(E-P4Q) Port P4 data output delay time ns 80 td(E-P5Q) Port P5 data output delay time ns 80 td(E-P6Q) Port P6 data output delay time ns 80 td(E-P7Q) Port P7 data output delay time ns 80 td(E-P8Q) Port P8 data output delay time ns 80 Port P9 data output delay time td(E-P9Q) 80 td(E-P10Q) Port P10 data output delay time 80 Note: This is applied when the main clock division selection bit = "0" and f(f 2) = 12.5 MHz. 15-6 7736 Group User's Manual ELECTRICAL CHARACTERISTICS 15.7 Single-chip mode Single-chip mode tf tr tc tW(H) tW(L) XIN E td(E-PiQ) Port Pi output tsu(PiD-E) th(E-PiD) Port Pi input (i = 0 to 10) Measuring conditions *VCC = 5 V 10 % *Input timing voltage : VIL = 1.0 V, VIH = 4.0 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 7736 Group User's Manual 15-7 ELECTRICAL CHARACTERISTICS __ 15.11 Measuring circuit for ports P0 to P10 and pins 1 and E __ 15.11 Measuring circuit for ports P0 to P10 and pins 1 and E P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 50 pF 1 E __ Fig. 15.11.1 Measuring circuit for ports P0 to P10 and pins 1 and E 15-8 7736 Group User's Manual CHAPTER 16 STANDARD CHARACTERISTICS 16.1 Standard characteristics STANDARD CHARACTERISTICS 16.1 Standard characteristics Concerning chapter "16. STANDARD CHARACTERISTICS," the 7736 Group differs from the 7733 Group in the following sections. Therefore, only the deferences are described in this chapter: * "16.1.1 Programmable I/O port (CMOS output) standard characteristics: P0 to P3, P4 0 to P4 3 , P5 to P9, and P10 4 to P10 7 * "16.1.2 Programmable I/O port (CMOS output) standard characteristics: P44 to P47 and P100 to P103 The following sections of the 7736 Group are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1: *"16.1.3 Icc-f(XIN ) standard characteristics" (page 16-4 in part 1) *"16.1.4 A-D converter standard characteristics" (page 16-5 in part 1) 16-2 7736 Group User's Manual STANDARD CHARACTERISTICS 16.1 Standard characteristics 16.1 Standard characteristics Standard characteristics described below are characteristic examples of the M37736MHBXXXGP and are not guaranteed. For each parameter's limits, refer to chapter "15. ELECTRICAL CHARACTERISTICS." 16.1.1 Programmable I/O port (CMOS output) standard characteristics: P0 to P3, P4 0 to P4 3, P5 to P9, and P10 4 to P10 7 (1) P-channel I OH-V OH characteristics Power source voltage VCC = 5 V P channel IOH [ mA ] 50.0 40.0 30.0 Ta = 25C 20.0 Ta = 85C 10.0 0 1.0 2.0 3.0 4.0 5.0 VOH [ V ] (2) N-channel I OL-V OL characteristics Power source voltage VCC = 5 V N channel 50.0 IOL [ mA ] 40.0 30.0 20.0 Ta = 25C 10.0 Ta = 85C 0 1.0 2.0 3.0 4.0 5.0 VOL [ V ] 7736 Group User's Manual 16-3 STANDARD CHARACTERISTICS 16.1 Standard characteristics 16.1.2 Programmable I/O port (CMOS output) standard characteristics: P4 4 to P4 7 and P10 0 to P10 3 (1) P-channel I OH-VOH characteristics Power source voltage VCC = 5 V P channel IOH [ mA ] 50.0 40.0 30.0 Ta = 25C 20.0 Ta = 85C 10.0 0 1.0 2.0 3.0 4.0 5.0 VOH [ V ] (2) N-channel IOL-VOL characteristics Power source voltage VCC = 5 V N channel 50.0 Ta = 25C IOL [ mA ] 40.0 30.0 Ta = 85C 20.0 10.0 0 1.0 2.0 3.0 4.0 VOL [ V ] 16-4 7736 Group User's Manual 5.0 CHAPTER 17 APPLICATIONS 17.1 17.2 17.3 17.4 17.5 Memory expansion Serial I/O Watchdog timer Power saving Timer B APPLICATIONS Concerning chapter "17. APPLICATIONS," the 7736 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter: * "17.4 Power saving" The following section of the 7736 Group differs depending on the external bus mode, which is A or B: * "17.1 Memory expansion" External bus mode A (page 17-2 in part 1) External bus mode B (page 17-2 in part 2 ) The following sections of the 7736 Group are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1: * "17.2 Serial I/O" (page 17-28 in part 1) * "17.3 Watchdog timer" (page 17-41 in part 1) * "17.5 Timer B" (page 17-54 in part 1) 17-2 7736 Group User's Manual APPLICATIONS 17.4 Power saving 17.4 Power saving Power saving examples (in other words, examples to save power consumption) with the stop or wait mode used in external bus mode A are described below. The following examples differ from examples in external bus mode B only in external bus pins allocated to ports P0 to P3. Therefore, for power saving in external bus mode B, refer to this section. 17.4.1 Power saving example with stop mode used In this example, power saving is realized by using the stop mode. The stop mode is terminated by using the key input interrupt function. (1) Specifications The microcomputer operates in the single-chip mode. Pins P10 0 to P10 3 are used as output pins for the key matrix scanning. Input pins ( KI 0 to KI 3) for the key input interrupt function are used as key input pins. Pins KI 0 to KI 3 are pulled high by using the pull-up function. The initial output levels of pins P100 to P10 3 are "L." When a key input interrupt request occurs owing to a key push, the key data is read-in. (This reading is surely performed independent of power saving.) In the stop mode, interrupts other than a key input interrupt are disabled. An external clock is used as the main clock. 7736 Group User's Manual 17-3 APPLICATIONS 17.4 Power saving (2) Initial settings for related registers b7 b0 0 X Oscillation circuit control register 1 (address 6F16) (Note) 1 An external clock is selected as the main clock. Watchdog timer is not used when the stop mode is terminated. Must be fixed to "0." Note: When writing a value to this register, write a value of "5516" by using the LDM instruction, and then write a value of "0A16." (Refer to Figure 11.2.4.) b7 b0 1 1 0 0 X Port function control register (address 6D16) Must be fixed to "0." Pin P64/INT2 is not used for the key input interrupt. Pins KI0 to KI3 are pulled high. Key input interrupt function is selected. b7 b0 0 0 0 0 1 1 1 1 Port P10 direction register (address 1816) Pins P100 to P103: Output mode Pins P104 to P107 (KI0 to KI3): Input mode b7 b0 X X X X 0 0 0 0 Port P10 register (address 1616) Pins P100 to P103's output (scan output) level: "L" b7 b0 0 0 0 INT2/Key input interrupt control register (address 7F16) Interrupt priority level is set. (Note that a value other than "0002" is set.) Interrupt request bit: 0 (Initialized) Must be fixed to "0." Interrupt disable flag (I) "0": Interrupt is enabled. X: It may be "0" or "1." Fig. 17.4.1 Initial settings for related registers 17-4 7736 Group User's Manual APPLICATIONS 17.4 Power saving (3) Approximate flowchart Main routine Port P10 register's bits which correspond to pins P100 to P103 (bits 0 to 3 at address 1616) Bits 2 to 0 at addresses 7016 to 7E16 VREF connection selection bit (bit 5 at address 1F16) "0002" "1" Port level is fixed. Key input interrupt request occurs. (Key is pushed.) STP "0" Scan output: "L" level Interrupts other than a key input interrupt are disabled. Pin VREF is disconnected from resistor ladder network. (Note 1) (Note 2) Stop mode is selected. Key input (INT2) interrupt routine Register save processing Key data is read-in. Port P10 register's bits which correspond to pins P100 to P103 (bits 0 to 3 at address 1616) "0" Scan output: "L" level Register return processing RTI Notes 1: When pin VREF and resistor ladder network are connected, current flows into the resistor ladder network. When using the A-D converter after the stop mode is terminated, do as follows: qReconnect pin V REF and resistor ladder network. wAnd then, start A-D conversion after a period of 1 s or more passed. 2: When a port is connected to an external device and so on, there is a possibility that current consumption increases according to the port's level. In order to avoid this problem, do as follows: *When output mode is selected: Fix the port's level to a level where no current flows into the external. *When input mode is selected : Pull the port high or low via a resistor. (Floating state is disabled.) Fig. 17.4.2 Approximate flowchart 7736 Group User's Manual 17-5 APPLICATIONS 17.4 Power saving (4) Settings for performing power saving in memory expansion or microprocessor mode In the memory expansion or microprocessor mode, when saving power consumption, it is necessary to fix the I/O pins' levels of the external bus and bus control signals in the stop mode. For this purpose, set the standby state selection bit to "1." 17-6 7736 Group User's Manual APPLICATIONS 17.4 Power saving Main routine VREF connection selection bit (bit 5 at address 1F16) Port P0 register (address 216) Port P1 register (address 316) Port P2 register (address 616) Port P3 register (address 716) "1" Pin VREF is disconnected from resistor ladder network. I/O pins' levels of external bus, chip-select signals and bus control signals in the stop mode are set. (These levels can be set by the corresponding port register's bits.) In this example, I/O pins for "L"-active signals are set to "H" and the other pins are set to "L." "001111112" "000000002" "000000002" "000010112" Port P0 direction register (address 416) Port P1 direction register (address 516) Port P2 direction register (address 816) Port P3 direction register (address 916) "FF16" Ports which correspond to I/O pins of external bus, chipselect signals and bus control signals: Output mode (This setting is done in order to output a value set to a port register in the stop mode) "FF16" "FF16" "FF16" Levels of ports other than the above are fixed. Port P4 register's bit which corresponds to P42 pin "0" (bit 2 at address A16) Port P4 direction register's bit which corresponds to P42 pin (bit 2 at address C16) Standby state selection bit (bit 0 at address 6D16) Signal output disable selection bit (bit 6 at address 6C16) Interrupt request occurs. STP "1" Pin 1's state in the stop mode is set (Note). In this example, "L" level output is set. Standby state selection bit: "1" (In the stop mode, a value which is set to the corresponding port register is output from an I/O pin of the external bus, chip-select signals or bus control signals.) "1" "1" Pin E's output level in the stop mode is set. In this example, it is set to "L." Stop mode is selected. Note: Regardless of this setting, in the following cases, pin 1 outputs "L" level in the stop mode: When the signal output disable selection bit is set to "0" in the microprocessor mode When the clock 1 output selection bit is set to "1" in the memory expansion mode Fig. 17.4.3 Fixing I/O pins' levels of external bus and bus control signals (Microprocessor mode) 7736 Group User's Manual 17-7 APPLICATIONS 17.4 Power saving 17.4.2 Power saving example with wait mode used In this example, power saving is realized by using the wait mode. While power is saved, the clock function is realized by using the clock timer (Timer B2). (1) Specifications The microcomputer operates in the single-chip mode. The frequency of the sub clock (f(XCIN)) = 32.768 kHz. An external clock is used as the sub clock. Clock counting is performed by using the clock timer. (An interrupt request occurs every second.) When an INT 0 interrupt request occurs (Note), the wait mode is terminated. Note: An interrupt request occurs at every falling edge of the signal input from pin INT 0. In the wait mode, interrupts other than the following interrupts are disabled. *Timer B2 interrupt * INT0 interrupt An external input is used as the main clock. 17-8 7736 Group User's Manual APPLICATIONS 17.4 Power saving (2) Initial settings for related registers b7 b0 X 0 X 1 1 Oscillation circuit control register 1 (address 6F16) An external clock is selected as the main clock. Watchdog timer is not used when the stop mode is terminated. An external clock is selected as the sub clock and P76 functions as a port. Watchdog timer is not used when the stop mode is terminated. Must be fixed to "0." Note: When writing a value to this register, write a value of "5516" by using the LDM instruction, and then write a value of "0A16." (Refer to Figure 11.2.4.) b7 b0 1 1 X Oscillation circuit control register 0 (address 6C16) The sub-clock oscillation circuit: oscillating (Timer B2 functions as the clock timer.) In the wait mode, clocks 2 to 512 are stopped. b7 b0 0 0 0 INT0 interrupt control register (address 7D16) Interrupt priority level is set. (Note that a value other than "0002" is set.) Interrupt request bit: 0 (Initialized) An interrupt request occurs at the falling edge. b7 b0 0 Timer B2 interrupt control register (address 7C16) Interrupt priority level is set. (Note that a value other than "0002" is set.) Interrupt request bit: 0 (Initialized) b15 b8 b7 0316 b0 FF16 Timer B2 register (addresses 5516 and 5416) Interval of the clock timer's interrupt request occurrence: 1 second Interrupt disable flag (I) b7 X X X "0": Interrupt is enabled. b0 0 1 0 1 Timer B2 mode register (address 5D16) Settings for the clock timer. X: It may be "0" or "1." Fig. 17.4.4 Initial settings for related registers 7736 Group User's Manual 17-9 APPLICATIONS 17.4 Power saving (3) Approximate flowchart Main routine Bits 2 to 0 at addresses 7016 to 7B16, 7E16, and 7F16 "0002" Timer B2 count start flag (bit 7 at address 4016) "1" VREF connection selection bit (bit 5 at address 1F16) "1" System clock selection bit (bit 3 at address 6C16) [F_WIT] INT0 interrupt request occurs. "1": Clock timer interrupt Clock timer starts counting. Pin VREF is disconnected from resistor ladder network. (Note 1) (Note 2) Port level is fixed. "1" Main clock stop bit (bit 2 at address 6C16) Interrupts other than timer B2 and INT0 interrupts are disabled. System clock: Main clock <<A>> Sub clock Main clock oscillation circuit: Stopped <<B>> "1" (By this setting, the wait mode is terminated only when an INT0 interrupt request occurs.) "1" Clock timer interrupt request Wait mode is selected. occurs. WIT [F_WIT] = "1" ? 0: INT0 interrupt Main clock stop bit (bit 2 at address 6C16) System clock selection bit (bit 3 at address 6C16) Main clock oscillation circuit: Oscillating <<C>> "0" "0" System clock: Sub clock <<D>> Main clock (Note 3) [F_WIT]: Flag used to determine whether an INT0 interrupt request has occurred or not For Notes 1 to 3, refer to the next page. <<A>> <<B>> <<C>> <<D>>: Refer to Figure 17.4.8. Fig. 17.4.5 Approximate flowchart (1) 17-10 7736 Group User's Manual APPLICATIONS 17.4 Power saving Notes 1: When pin V REF and resistor ladder network are connected, current flows into the resistor ladder network. When using the A-D converter after the wait mode is terminated, do as follows: qReconnect pin VREF and resistor ladder network. wAnd then, start A-D conversion after a period of 1 s or more passed. 2: When a port is connected to an external device and so on, there is a possibility that current consumption increases according to the port's level. In order to avoid this problem, do as follows: *When output mode is selected: Fix the port's level to a level where no current flows into the external. *When input mode is selected: Pull the port high or low via a resistor. (Floating state is disabled.) 3: Do not switch the system clock until oscillation of a clock which is input from the external is stabilized. INT0 interrupt routine Register save processing [F_WIT] Timer B2 interrupt routine Register save processing "0" Register return processing Clock count Register return processing RTI RTI [F_WIT]: Flag used to determine whether an INT0 interrupt request has occurred or not Fig. 17.4.6 Approximate flowchart (2) 7736 Group User's Manual 17-11 17-12 Fig. 17.4.7 State of main clock, sub clock, and system clock 7736 Group User's Manual Main clock stop bit System clock selection bit System clock Sub clock Main clock "0" "1" "0" "1" Main clock <<A>> <<B>> <<C>> Sub clock <<D>> Main clock APPLICATIONS 17.4 Power saving CHAPTER 18 LOW VOLTAGE VERSION 18.1 18.2 18.3 18.4 18.5 18.6 Performance overview Pin configuration Functional description Electrical characteristics Standard characteristics Applications LOW VOLTAGE VERSION Concerning chapter "18. LOW VOLTAGE VERSION," the 7736 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this chapter: * "18.1 Performance overview" * "18.2 Pin configuration" * "18.3 Functional description" * "18.4 Electrical characteristics" * "18.5 Standard characteristics" * "18.6 Applications" 18-2 7736 Group User's Manual LOW VOLTAGE VERSION 18.1 Performance overview 18.1 Performance overview Concerning section "18.1 Performance overview," the 7736 Group differs from the 7733 Group in the following: * TABLE 18.1.1: programmable I/O ports, output port, memory expansion, and package The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "18.1 Performance overview" (page 18-3 in part 1) Table 18.1.1 M37736MHLXXXHP performance overview Items Programmable I/O ports Ports P0-P2, P4-P8, P10 Port P3 Output port Port P9 Memory expansion Package Performance 8 bits 8 4 bits 1 8 bits 1 Possible * External bus mode A: Maximum of 16 Mbytes * External bus mode B: Maximum of 1 Mbytes 100-pin plastic molded fine-pitch QFP 7736 Group User's Manual 18-3 LOW VOLTAGE VERSION 18.2 Pin configuration 18.2 Pin configuration P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RXD0/CLKS0 P83/TXD0 P84/CTS1/RTS1 P85/CLK1 P86/RxD1 P87/TxD1 P90/CTS2 P91/CLK2 P75/AN5/ADTRG P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P66/TB1IN P67/TB2IN/ P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 SUB Figure 18.2.1 shows the M37736MHLXXXHP pin configuration. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 8 9 10 11 12 13 14 15 16 17 18 19 M37736MHLXXXHP P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P107/KI3 P106/KI2 P105/KI1 P104/KI0 P103 P102 P101 P100 P47 P46 P45 68 67 66 65 64 63 62 61 60 59 58 57 20 56 21 55 22 54 23 53 24 52 25 51 P44 P43 P42/ 1 P41/RDY P40/HOLD BYTE CNVSS BSEL RESET XIN XOUT E/RDE VSS VCC EVL1 EVL0 P33/HLDA P32/ALE P31/BHE/WEH P30/R/W/WEL P27/A23/A7/D7 P26/A22/A6/D6 P25/A21/A5/D5 P24/A20/A4/D4 P23/A19/A3/D3 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Outline 100P6D-A Fig. 18.2.1 M37736MHLXXXHP pin configuration (Top view) 18-4 69 7736 Group User's Manual P92/RxD2 P93/TxD2 P94 P95 P96 P97 P00/A0/CS0 P01/A1/CS1 P02/A2/CS2 P03/A3/CS3 P04/A4/CS4 P05/A5/RSMP P06/A6/A16 P07/A7/A17 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/A0/D0 P21/A17/A1/D1 P22/A18/A2/D2 LOW VOLTAGE VERSION 18.3 Functional description 18.3 Functional description The M37736MHLXXXHP has the same functions as the M37736MHBXXXGP except for the power-on reset conditions. For the power-on reset conditions, refer to section 18.3.1 in part 1. For the other functions, refer to the corresponding chapters in parts 2 and 3: * Part 2 : Chapters "4. INTERRUPTS" to "9. A-D CONVERTER" * Part 3 : Chapters "2. CENTRAL PROCESSING UNIT," "3. PROGRAMMABLE I/O PORTS," "8. SERIAL I/ O" to "14. CLOCK GENERATING CIRCUIT" 7736 Group User's Manual 18-5 LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4 Electrical characteristics Concerning section "18.4 Electrical characteristics," the 7736 Group differs from the 7733 Group in the following sections: * "18.4.1 Absolute maximum ratings" * "18.4.2 Recommended operating conditions" * "18.4.3 Electrical characteristics" * "18.4.7 Single-chip mode" __ * "18.4.11 Measuring circuit for ports P0 to P10 and pins 1 and E" The following sections of the 7736 Group differ depending on the external bus mode. In external bus mode A, refer to the corresponding sections in part 1; in external bus mode B, refer to the corresponding sections in part 2. * "18.4.6 Ready and Hold" External bus mode A (page 18-16 in part 1) External bus mode B (page 18-5 in part 2) * "18.4.8 Memory expansion mode and Microprocessor mode : with no wait" External bus mode A (page 18-20 in part 1) External bus mode B (page 18-7 in part 2) * "18.4.9 Memory expansion mode and Microprocessor mode : with wait 1" External bus mode A (page 18-22 in part 1) External bus mode B (page 18-9 in part 2) * "18.4.10 Memory expansion mode and Microprocessor mode : with wait 0" External bus mode A (page 18-24 in part 1) External bus mode B (page 18-11 in part 2) The following sections of the 7736 Group are the same as those of the 7733 Group. Therefore, for these sections, refer to part 1: * "18.4.4 A-D converter characteristics" (page 18-10 in part 1) * "18.4.5 Internal peripheral devices" (page 18-11 in part 1) 18-6 7736 Group User's Manual LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.1 Absolute maximum ratings Absolute maximum ratings Parameter Symbol Conditions Power source voltage Vcc Analog power source voltage AVcc ______ Input voltage VI RESET, CNVss, BYTE Input voltage P00-P07, P10-P17, P20-P27, P30-P33, VI P40-P47, P50-P57, P60-P67, P70-P77, P80-P87, P100-P107, VREF, XIN, BSEL Output voltage P00-P07, P10-P17, P20-P27, P30-P33, VO P40-P47, P50-P57, P60-P67, P70-P7__ 7, P80-P87, P90-P97, P100-P107, XOUT, E Power dissipation Pd Ta = 25 C Operating temperature Topr Storage temperature Tstg 7736 Group User's Manual Ratings -0.3 to 7 -0.3 to 7 -0.3 to 12 Unit V V V -0.3 to Vcc+0.3 V -0.3 to Vcc+0.3 V 200 -40 to 85 -65 to 150 mW C C 18-7 LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.2 Recommended operating conditions Recommended operating conditions (Vcc = 2.7 to 5.5 V, Ta = -40 to 85 C, unless otherwise noted) Limits Unit Symbol Parameter Min. Typ. Max. f(XIN) :Operating 2.7 5.5 Vcc Power source voltage V f(XIN) :Stopped, f(XCIN) = 32.768 kHz 2.7 5.5 AVcc Analog power source voltage Vcc V Vss Power source voltage 0 V AVss Analog power source voltage 0 V P00-P07, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, VIH High-level input voltage V 0.8 Vcc Vcc P80-P87, P100-P107, XIN, RESET, CNVss, BYTE, BSEL, XCIN (Note 3) P10-P17, P20-P27 VIH High-level input voltage V 0.8 Vcc Vcc (in single-chip mode) P10-P17, P20-P27 (in memory expansion mode and 0.5 Vcc VIH High-level input voltage V Vcc microprocessor mode) P00-P07, P30-P33, P40-P47, P50-P57, P60-P67, P70-P77, Low-level input voltage 0 VIL V 0.2 Vcc P80-P87, P100-P107, XIN, RESET, CNVss,BYTE, BSEL, XCIN (Note 3) P10-P17, P20-P27 Low-level input voltage 0 VIL V 0.2 Vcc (in single-chip mode) P10-P17, P20-P27 (in memory expansion mode and Low-level input voltage 0 VIL 0.16 Vcc V microprocessor mode) P00-P07, P10-P17, P20-P27, P30-P33, P40-P47, P50-P57, IOH (peak) High-level peak output current mA -10 P60-P67, P70-P77, P80-P87, P90-P97, P100-P107 P00-P07, P10-P17, P20-P27, High-level average output current P30-P33, P40-P47, P50-P57, IOH (avg) mA -5 P60-P67, P70-P77, P80-P87, P90-P97, P100-P107 P00-P07, P10-P17, P20-P27, P30-P33, P40-P43, P54-P57, Low-level peak output current IOL (peak) mA 10 P60-P67, P70-P77, P80-P87, P90-P97, P104-P107 P44-P47, P100-P103 Low-level peak output current IOL (peak) mA 16 P00-P07, P10-P17, P20-P27, Low-level average output current P30-P33, P40-P43, P54-P57, IOL (avg) P60-P67, P70-P77, P80-P87, mA 5 P90-P97, P104-P107 Low-level average output current P44-P47, P100-P103 IOL (avg) mA 12 Main-clock oscillation frequency (Note 4) f(XIN) MHz 12 Sub-clock oscillation frequency f(XCIN) 32.768 kHz 50 Notes 1: Average output current is the average value of an interval of 100 ms. 2: The sum of IOL(peak) for ports P0, P1, P2, P3, P8 and P9 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, P8 and P9 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, P7 and P10 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, P7 and P10 must be 80 mA or less. 3: Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = "1." 4: The maximum value of f(XIN) = 6 MHz when the main clock division selection bit = "1." 18-8 7736 Group User's Manual LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.3 Electrical characteristics Electrical characteristics (Vcc = 5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. High-level output voltage P00-P07, P10-P17, P20-P27, Vcc = 5 V, IOH = -10 mA 3 V VOH P33, P40-P47, P50-P57, 2.5 P6 0-P67, P70-P77, P80-P87, Vcc = 3 V, IOH = -1 mA P90-P97, P100-P107 High-level output voltage P00-P07, P10-P17, P20-P27, Vcc = 5 V, IOH = -400 A 4.7 V VOH P33 High-level output voltage P30-P32 Vcc = 5 V, IOH = -10 mA 3.1 VOH Vcc = 5 V, IOH = -400 A V 4.8 Vcc = 3 V, I OH = -1 mA 2.6 _ High-level output voltage E Vcc = 5 V, I OH = -10 mA 3.4 VOH V Vcc = 5 V, IOH = -400 A 4.8 Vcc = 3 V, IOH = -1 mA 2.6 Low-level output voltage P00-P07, P10-P17, P20-P27, 2 Vcc = 5 V, IOL = 10 mA VOL P33, P40-P43, P50-P57, V P6 0-P67, P70-P75, P80-P87, Vcc = 3 V, IOL = 1 mA 0.5 P90-P97, P104-P107 Vcc = 5 V, IOL = 16 mA 1.8 Low-level output voltage P44-P47, P50-P53 VOL V Vcc = 3 V, IOL = 10 mA 1.5 Low-level output voltage P00-P07, P10-P17, P20-P27, Vcc = 5 V, IOL = 2 mA 0.45 V VOL P33 Vcc = 5 V, IOL = 10 mA 1.9 Low-level output voltage P30-P32 VOL Vcc = 5 V, IOL = 2 mA 0.43 V Vcc = 3 V, IOL = 1 mA 0.4 Vcc = 5 V, IOL = 10 mA 1.6 Low-level output voltage E VOL Vcc = 5 V, IOL = 2 mA 0.4 V Vcc = 3 V, IOL = 1 mA 0.4 HOLD, RDY, TA0IN-TA4IN, TB0IN-TB2IN, VT+-VT- Hysteresis 1 0.4 Vcc = 5 V INT0-INT2, ADTRG, CTS0, CTS1, CTS2, CLK0, V Vcc = 3 V 0.7 0.1 CLK1, CLK2, KI0-KI3 0.5 0.2 Vcc = 5 V VT+-VT- Hysteresis RESET 0.4 V 0.1 Vcc = 3 V 0.4 0.1 Vcc = 5 V VT+-VT- Hysteresis XIN V 0.26 Vcc = 3 V 0.06 0.4 Vcc = 5 V VT+-VT- Hysteresis XCIN (When external clock is input) 0.1 0.26 V Vcc = 3 V 0.06 High-level input current P00-P07, P10-P17, P20-P27, 5 Vcc = 5 V, VI = 5 V IIH P30-P33, P40-P47, P50-P57, A P60-P67, P70-P77, P80-P87, Vcc = 3 V, VI = 3 V 4 P10 0 -P10 7 , X IN , RESET , CNVss, BYTE, BSEL Low-level input current P00-P07, P10-P17, P20-P27, IIL -5 Vcc = 5 V, VI = 0 V P30-P33, P40-P47, P50-P57, A P60, P61, P65- P67, P70-P77, -4 Vcc = 3 V, VI = 0 V P80-P87, P100-P107, XIN, RESET, CNVss, BYTE, BSEL VI = 0 V, Vcc = 5 V -5 Low-level input current P62-P64, P104-P107 IIL without a pull-up transistor Vcc = 3 V -4 A VI = 0 V, Vcc = 5 V -0.25 -0.5 -1.0 with a pull-up transistor Vcc = 3 V -0.08 -0.18 -0.35 mA 2 VRAM RAM hold voltage When clock is stopped V 7736 Group User's Manual 18-9 LOW VOLTAGE VERSION 18.4 Electrical characteristics ELECTRICAL CHARACTERISTICS (Vcc= 5 V, Vss = 0 V, Ta = -40 to 85 C, unless otherwise noted) Limits Symbol Parameter Measuring conditions Min. Typ. Max. Unit Vcc = 5 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), 4.5 9 mA f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 6 MHz), 3 6 mA f(XCIN) = 32.768 kHz, in operating (Note 1) Vcc = 3 V, f(XIN) = 12 MHz (Square waveform), (f(f2) = 0.75 MHz), 0.4 0.8 mA In single-chip f(XCIN) : Stopped, mode, output in operating (Note 1) Power source pins are open, Vcc = 3V, ICC current and the other f(XIN) = 12 MHz (Square waveform), 6 12 A pins are f(XCIN) = 32.768 kHz, connected when the WIT instruction is executed (Note 2) to Vss. Vcc = 3 V, f(XIN) : Stopped, 30 60 A f(XCIN) : 32.768 kHz, in operating (Note 3) Vcc = 3 V, f(XIN) : Stopped, 3 6 A f(XCIN) : 32.768 kHz, when the WIT instruction is executed (Note 4) Ta = 25 C, 1 A when clock is stopped Ta = 85 C, 20 A when clock is stopped Notes 1: This is applied when the main clock external input selection bit = "1," the main clock division selection bit = "0," and the signal output disable selection bit = "1." 2: This is applied when the main clock external input selection bit = "1" and the system clock stop bit at wait state = "1." 3: This is applied when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4: This is applied when the XCOUT drivability selection bit = "0" and the system clock stop bit at wait state = "1." 18-10 7736 Group User's Manual LOW VOLTAGE VERSION 18.4 Electrical characteristics 18.4.7 Single-chip mode Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(X IN) = 12 MHz (Note 1), unless otherwise noted) The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. Limits Unit Min. Max. External clock input cycle time (Note 2) ns tc 83 External clock input high-level pulse width (Note 3) ns tw(H) 33 External clock input low-level pulse width (Note 3) ns tw(L) 33 External clock rise time ns tr 15 External clock fall time ns tf 15 Port P0 input setup time ns tsu(P0D-E) 200 Port P1 input setup time ns tsu(P1D-E) 200 Port P2 input setup time ns tsu(P2D-E) 200 Port P3 input setup time ns tsu(P3D-E) 200 Port P4 input setup time ns tsu(P4D-E) 200 Port P5 input setup time ns tsu(P5D-E) 200 Port P6 input setup time ns tsu(P6D-E) 200 tsu(P7D-E) Port P7 input setup time ns 200 tsu(P8D-E) Port P8 input setup time ns 200 tsu(P10D-E) Port P10 input setup time ns 200 ns th(E-P0D) Port P0 input hold time 0 ns th(E-P1D) Port P1 input hold time 0 Port P2 input hold time ns th(E-P2D) 0 Port P3 input hold time ns th(E-P3D) 0 Port P4 input hold time ns th(E-P4D) 0 ns Port P5 input hold time th(E-P5D) 0 ns Port P6 input hold time th(E-P6D) 0 ns Port P7 input hold time th(E-P7D) 0 Port P8 input hold time ns th(E-P8D) 0 Port P10 input hold time ns th(E-P10D) 0 Notes 1: This is applied when the main clock division selection bit = "0" and f(f2) = 6 MHz. 2: When the main clock division selection bit = "1," the minimum value of tc = 166 ns. 3: When the main clock division selection bit = "1," values of tw (H)/tc and tw(L)/tc must be set to values from 0.45 through 0.55. Symbol Parameter Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -40 to 85 C, f(XIN) = 12 MHz (Note), unless otherwise noted) Limits Symbol Parameter Measuring conditions Min. Max. Unit td(E-P0Q) Port P0 data output delay time ns 300 td(E-P1Q) Port P1 data output delay time ns 300 td(E-P2Q) Port P2 data output delay time ns 300 td(E-P3Q) Port P3 data output delay time ns 300 Fig. 18.4.1 td(E-P4Q) Port P4 data output delay time ns 300 td(E-P5Q) Port P5 data output delay time ns 300 td(E-P6Q) Port P6 data output delay time ns 300 td(E-P7Q) Port P7 data output delay time ns 300 td(E-P8Q) Port P8 data output delay time ns 300 Port P9 data output delay time td(E-P9Q) ns 300 td(E-P10Q) Port P10 data output delay time ns 300 Note: This is applied when the main clock division selection bit = "0" and f(f 2) = 6 MHz. 7736 Group User's Manual 18-11 LOW VOLTAGE VERSION 18.4 Electrical characteristics Single-chip mode tf tc tr tW(H) tW(L) XIN E td(E-P0Q) Port Pi output tsu(P0D-E) Port Pi input (i = 0 to 10) Measuring conditions *VCC = 2.7 to 5.5 V *Input timing voltage : VIL = 0.2 VCC, VIH = 0.8 VCC *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V 18-12 7736 Group User's Manual th(E-P0D) LOW VOLTAGE VERSION 18.4 Electrical characteristics __ 18.4.11 Measuring circuit for ports P0 to P10 and pins 1 and E P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 50 pF 1 E _ Fig. 18.4.1 Measuring circuit for ports P0 to P10 and pins 1 and E 7736 Group User's Manual 18-13 LOW VOLTAGE VERSION 18.5 Standard characteristics 18.5 Standard characteristics Concerning section "18.5 Standard characteristics," the 7736 Group differs from the 7733 Group in the following sections. Therefore, only the differences are described in this section: * "18.5.1 Programmable I/O port (CMOS output) standard characteristics: P0 to P3, P40 to P43, P5 to P9, and P10 4 to P10 7 * "18.5.2 Programmable I/O port (CMOS output) standard characteristics: P44 to P47 and P100 to P103 The other description is the same as that of the 7736 Group. Therefore, refer to part 1: *"18.5 Standard characteristics" (page 18-27 in part 1) Standard characteristics described below are characteristics examples of the M37736MHLXXXHP and are not guaranteed. For each parameter's limits, refer to section "18.4 Electrical characteristics." 18.5.1 Programmable I/O port (CMOS output) standard characteristics: Ports P0 to P3, P4 0 -P4 3 , P5-P9 and P10 4-P10 7 (1) P-channel I OH-V OH characteristics Power source voltage Vcc = 3 V P-channel 20.0 IOH [mA] 16.0 12.0 Ta = 25 C 8.0 Ta = 85 C 4.0 0 0.6 1.2 1.8 2.4 3.0 VOH [V] (2) N-channel I OL-VOL characteristics Power source voltage Vcc = 3 V N-channel 20.0 IOL [mA] 16.0 12.0 Ta = 25 C 8.0 Ta = 85 C 4.0 0 0.6 1.2 1.8 VOL [V] 18-14 7736 Group User's Manual 2.4 3.0 LOW VOLTAGE VERSION 18.5 Standard characteristics 18.5.2 Programmable I/O port (CMOS output) standard characteristics: Ports P4 4 to P4 7 and P5 0 to P5 3 (1) P-channel I OH-VOH characteristics Power source voltage Vcc = 3 V P-channel 20.0 IOH [mA] 16.0 12.0 Ta = 25 C 8.0 Ta = 85 C 4.0 0 0.6 1.2 1.8 2.4 3.0 VOH [V] (2) N-channel IOL-VOL characteristics Power source voltage Vcc = 3 V N-channel 20.0 IOL [mA] 16.0 Ta = 25 C 12.0 Ta = 85 C 8.0 4.0 0 0.6 1.2 1.8 2.4 3.0 VOL [V] 7736 Group User's Manual 18-15 LOW VOLTAGE VERSION 18.6 Applications 18.6 Applications In external bus mode A, section "18.6 Applications" is the same as that of the 7733 Group. Therefore, refer to part 1: * "18.6 Applications" (page 18-32 in part 1) In external bus mode B, section "18.6 Applications" is the same as that of the 7735 Group. Therefore, refer to part 2: * "18.6 Applications" (page 18-13 in part 2) 18-16 7736 Group User's Manual CHAPTER 19 BUILT-IN PROM VERSION 19.1 EPROM mode 19.2 Usage precaution BUILT-IN PROM VERSION 19.1 EPROM mode 19.1 EPROM mode Concerning chapter "19. BUILT-IN PROM VERSION," the 7736 Group differs from the 7733 Group in the following section. Therefore, only the differences are described in this chapter: * "19.1 EPROM mode" The following section is the same as that of the 7733 Group. Therefore, for this section, refer to part 1: * "19.2 Usage precaution" (page 19-10 in part 1) 19.1 EPROM mode Concerning section "19.1 EPROM mode," the 7736 Group differs from the 7733 Group in the following: * Table 19.1.1 * Figures 19.1.1 and 19.1.2 The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "19.1 EPROM mode" (page 19-3 in part 1) Table 19.1.1 Pin description in EPROM mode Pin Name Input/Output Functions P9 0-P97 Input port P9 Input P10 0-P107 Input port P10 Input Connect to Vss. Connect to Vss. BSEL Bus select input Input Connect to pin Vcc. EVL0, EVL1 19-2 -- Output Left open. 7736 Group User's Manual BUILT-IN PROM VERSION 19.1 EPROM mode P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5/ADTRG P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RxD0/CLKS0 P83/TxD0 P84/CTS1/RTS1 P85/CLK1 P86/RxD1 VCC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 OE PGM 1 80 2 79 3 78 4 77 76 5 6 75 7 74 8 73 9 72 10 11 12 13 14 15 16 17 18 19 20 21 22 M37736EHBGP CE P67/TB2IN/ SUB P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P107/KI3 P106/KI2 P105/KI1 P104/KI0 P103 P102 P101 P100 P47 P46 P45 P44 P43 P42/ 1 71 70 69 68 67 66 65 64 63 62 61 60 59 23 58 24 25 57 56 26 55 27 54 28 29 53 52 30 51 P87/TxD1 P90/CTS2 P91/CLK2 P92/RxD2 P93/TxD2 P94 P95 P96 P97 P00/A0/CS0 P01/A1/CS1 P02/A2/CS2 P03/A3/CS3 P04/A4/CS4 P05/A5/RSMP P06/A6/A16 P07/A7/A17 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/A0/D0 P21/A17/A1/D1 P22/A18/A2/D2 P23/A19/A3/D3 P24/A20/A4/D4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 P41/RDY P40/HOLD BYTE VPP CNVSS BSEL RESET XIN * XOUT E/RDE VSS VCC EVL1 EVL0 P33/HLDA P32/ALE P31/BEH/WEH A16 P30/R/W/WEL D7 P27/A23/A7/D7 D6 P26/A22/A6/D6 D5 P25/A21/A5/D5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS * : Connect these pins to a resonator or an oscillator. : EPROM pin. Outline 100P6S-A Fig. 19.1.1 Pin connections in EPROM mode (M37736EHBGP) 7736 Group User's Manual 19-3 BUILT-IN PROM VERSION 19.1 EPROM mode P66/TB1IN P67/TB2IN/ SUB P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5/ADTRG P76/AN6/XCOUT P77/AN7/XCIN VSS AVSS VREF AVCC VCC P80/CTS0/RTS0/CLKS1 P81/CLK0 P82/RxD0/CLKS0 P83/TxD0 P84/CTS1/RTS1 P85/CLK1 P86/RxD1 P87/TxD1 P90/CTS2 P91/CLK2 VCC PGM 1 2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 0 5 4 3 2 1 0 75 74 3 73 4 72 71 70 5 6 M37736EHLHP CE OE P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P107/KI3 P106/KI2 P105/KI1 P104/KI0 P103 P102 P101 P100 P47 P46 P45 7 8 9 10 11 12 13 14 15 16 17 18 19 69 68 67 66 65 64 63 62 61 60 59 58 20 57 56 21 55 22 54 24 53 52 25 51 23 P92/RxD2 P93/TxD2 P94 P95 P96 P97 P00/A0/CS0 P01/A1/CS1 P02/A2/CS2 P03/A3/CS3 P04/A4/CS4 P05/A5/RSMP P06/A6/A16 P07/A7/A17 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/A0/D0 P21/A17/A1/D1 P22/A18/A2/D2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 P41/RDY P40/HOLD BYTE VPP CNVSS BSEL RESET XIN * XOUT E/RDE VSS VCC EVL1 EVL0 P33/HLDA P32/ALE P31/BEH/WEH A16 P30/R/W/WEL D7 P27/A23/A7/D7 D6 P26/A22/A6/D6 D5 P25/A21/A5/D5 D4 P24/A20/A4/D4 P23/A19/A3/D3 D3 P44 P43 P42/ 1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS * : Connect these pins to a resonator or an oscillator. : EPROM pin. Outline 100P6D-A Fig. 19.1.2 Pin connections in EPROM mode (M37736EHLHP) 19-4 7736 Group User's Manual APPENDIX Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix 1. 2. 3. 4. 5. 6. 7. 8. Memory allocation of 7736 Group Memory allocation in SFR area Control registers Package outlines Hexadecimal instruction code table Machine instructions Examples of handling unused pins Countermeasure examples against noise Appendix 9. Q & A APPENDIX Concerning chapter "APPENDIX," the 7736 Group differs from the 7733 Group in the following secti Therefore, only the differences are described in this chapte r: * "Appendix 1. Memory allocation of 7736 Group" * "Appendix 2. Memory allocation in SFR area" * "Appendix 3. Control registers" * "Appendix 4. Package outlines" * "Appendix 7. Examples of handling unused pins" Note: The following sections of the 7736 Group are the same as th ose of the 7733 Group. Therefore, these sections, refer to part 1: * "Appendix 5. Hexadecimal instruction code table" (page 21-41 in part 1 ) * "Appendix 6. Machine instructions" (page 21-44 in part 1 ) * "Appendix 8. Countermeasure examples against noise" (page 21-61 in part 1 ) * "Appendix 9. Q & A" (page 21-71 in part 1 ) 20-2 7736 Group User's Manual APPENDIX Appendix 1. Memory allocation of 7736 Group Appendix 1. Memory allocation of 7736 Group 1. M37736MHBXXXGP, M37736EHBXXXGP, M37736EHBGS, M37736MHLXXXHP, M37736EHLXXXHP * Memory allocation selection bits (b2, b1, b0)=(0, 0, 0) * Memory allocation selection bits (b2, b1, b0)=(0, 0, 1) * ROM size: 120 Kbytes * ROM size: 124 Kbytes * RAM size: 3.9 Kbytes * RAM size: 3.9 Kbytes 00000016 00000016 00000016 SFR area SFR area 00007F16 00007F16 00008016 00008016 Internal RAM area Internal RAM area Peripheral device 3968 bytes 3968 bytes control registers 000FFF16 000FFF16 (SFR) 001000 16 (4 Kbytes) Internal ROM area Bank 016 Refer to 00200016 Internal ROM area 60 Kbytes Appendix 2 56 Kbytes 00FFFF16 00FFFF16 in part 1. 01000016 01000016 00007F16 Bank 116 Internal ROM area 64 Kbytes Interrupt vector table Internal ROM area 64K bytes 00FFD 616 A-D/UART2 trans./rece. UART1 transmission 01FFFF16 02000016 UART1 reception 01FFFF16 UART0 transmission UART0 reception Timer B2 Timer B1 Bank 216 Timer B0 Timer A4 Timer A3 Timer A2 02FFFF16 Timer A1 Timer A0 INT2/Key input IN T1 IN T0 Watchdog timer D BC BRK instruction Zero divide 00FFFE16 R ESET : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode FF000016 Bank FF16 FFFFFF16 FFFFFF16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes" in part 1.) 2: In external bus mode B, banks 1016 to FF16 cannot be accessed. Fig. 1 Memory allocation of M37736MHBXXXGP, M37736EHBXXXGP, M37736EHBGS, M37736MHLXXXHP, M37736EHLXXXHP (1) 7736 Group User's Manual 20-3 APPENDIX Appendix 1. Memory allocation of 7736 Group * Memory allocation selection bits (b2, b1, b0)=(0, 1, 0) * ROM size: 60 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 2048 bytes 00087F16 (1.9 Kbytes) 00100016 * Memory allocation selection bits (b2, b1, b0)=(1, 0, 0) * ROM size: 32 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 2048 bytes 00087F16 00000016 Peripheral device control registers (SFR) Refer to Appendix 2. (29.9 Kbytes) Bank 016 Internal ROM area 60 Kbytes 00FFFF16 01000016 00800016 Internal ROM area 32 Kbytes 00FFFF16 01000016 00007F16 Interrupt vector table 00FFD616 A-D/UART2 trans./rece. UART1 transmission UART1 reception UART0 transmission UART0 reception Bank 116 Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 01FFFF16 02000016 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Bank 216 Watchdog timer DBC BRK instruction Zero divide 00FFFE16 RESET 02FFFF16 FF000016 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Bank FF16 FFFFFF16 FFFFFF16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes.") 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Fig. 2 Memory allocation of M37736MHBXXXGP, M37736EHBXXXGP, M37736EHBGS, M37736MHLXXXHP, M37736EHLXXXHP (2) 20-4 7736 Group User's Manual APPENDIX Appendix 1. Memory allocation of 7736 Group * Memory allocation selection bits (b2, b1, b0)=(1, 0, 1) * ROM size: 16 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 2048 bytes 00087F16 00000016 00007F16 00008016 000FFF16 00100016 Bank 016 * Memory allocation selection bits (b2, b1, b0)=(1, 1, 0) * ROM size: 96 Kbytes * RAM size: 3968 bytes SFR area 00000016 Internal RAM area 3968 bytes Peripheral device control registers (SFR) Refer to Appendix 2. (28 Kbytes) (45.9 Kbytes) 00800016 00C00016 00FFFF16 01000016 Internal ROM area 16 Kbytes Internal ROM area 32 Kbytes 00FFFF16 01000016 00007F16 Interrupt vector table 00FFD616 A-D/UART2 trans./rece. UART1 transmission UART1 reception UART0 transmission UART0 reception Internal ROM area 64 Kbytes Bank 116 Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 01FFFF16 02000016 01FFFF16 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 Bank 216 Watchdog timer DBC BRK instruction Zero divide 00FFFE16 RESET 02FFFF16 FF000016 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Bank FF16 FFFFFF16 FFFFFF16 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes.") 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. Fig. 3 Memory allocation of M37736MHBXXXGP, M37736EHBXXXGP, M37736EHBGS, M37736MHLXXXHP, M37736EHLXXXHP (3) 7736 Group User's Manual 20-5 APPENDIX Appendix 2. Memory allocation in SFR area Appendix 2. Memory allocation in SFR area Concerning section "Appendix 2. Memory allocation in SFR area," the 7736 Group differs from the 7733 Group in the following: * Address 6F16 (Refer to Figure 8.) The other description is the same as that of the 7733 Group. Therefore, refer to part 1: * "Appendix 2. Memory allocation in SFR area" (page 21-6 in part 1) 20-6 7736 Group User's Manual APPENDIX Appendix 2. Memory allocation in SFR area Address Register name b7 Watchdog timer register 6016 6116 Watchdog timer frequency selection flag 6216 (Reserved area) (3) Memory allocation control register 6316 UART 2 transmit/receive mode register 6416 UART 2 baud rate register (BRG2) 6516 6616 UART 2 transmission buffer register 6716 6816 UART 2 transmit/receive control register 0 6916 UART 2 transmit/receive control register 1 6A16 UART 2 receive buffer register 6B16 Oscillation circuit control register 0 6C16 Port function control register 6D16 Serial transmit control register 6E16 Oscillation circuit control register 1 WO 6F16 7016 A-D / UART 2 trans./rece. interrupt control register 7116 UART0 transmission interrupt control register 7216 UART0 receive interrupt control register 7316 UART1 transmission interrupt control register 7416 UART1 receive interrupt control register Timer A0 interrupt control register 7516 Timer A1 interrupt control register 7616 Timer A2 interrupt control register 7716 Timer A3 interrupt control register 7816 Timer A4 interrupt control register 7916 Timer B0 interrupt control register 7A16 Timer B1 interrupt control register 7B16 Timer B2 interrupt control register 7C16 INT0 interrupt control register 7D16 INT1 interrupt control register 7E16 INT2/Key input interrupt control register 7F16 Access characteristics b0 State immediately after reset b0 b7 RW RW RW WO WO WO RO RW RO R W R OR W RO RO RW RW(2) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ? ? 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 ? ( 1) ? ? 0 0 0 0 0 0 0 0 ? ? ? 1 0 0 0 0 0 1 ? 0 0 0 0 0 0 0 ? 0 0 0 0 ? 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A value of "FFF16" is set to the watchdog timer. (Refer to chapter "10. WATCHDOG TIMER" in part 1.) 2 For access characteristics at address 6C16, also refer to Figure 14.3.2 in part 1. 3 Do not wirte to the reserved area. Internal RAM area (M37736MHBXXXGP: addresses 8016 to FFF16) At hardware reset (not including the case where the stop or wait mode is terminated)...Undefined. At software reset...Retains the state immediately before reset. When the stop or wait mode is terminated (when the hardware reset is used)...Retains the state immediately before the STP or WIT instruction is executed. Fig. 8 Memory allocation in SFR area (4) 7736 Group User's Manual 20-7 APPENDIX Appendix 3. Control registers Appendix 3. Control registers Concerning section "Appendix 3. Control registers," the 7736 Group differs from the 7733 Group in the following: * Port Pi register * Port Pi direction register * Port function control register * Oscillation circuit control register 1 The other control registers are the same as those of the 7733 Group. Therefore, for the other control registers, refer to part 1: * "Appendix 3. Control registers" (page 21-10 in part 1) 20-8 7736 Group User's Manual APPENDIX Appendix 3. Control registers Port Pi register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi register (i = 0 to 10) (addresses 216,316,616,716,A16,B16,E16,F16,1216,1316,1616) Bit Bit name Functions At reset RW Undefined RW Undefined RW Undefined RW Undefined RW 0 Port Pi0's pin 1 Port Pi1's pin 2 Port Pi2's pin 3 Port Pi3's pin 4 Port Pi4's pin Undefined RW 5 Port Pi5's pin Undefined RW 6 Port Pi6's pin Undefined RW 7 Port Pi7's pin Undefined RW Data is input from or output to a pin by reading/writing from/to the corresponding bit. 0: "L" level 1: "H" level Notes 1: Writing to bits 4 to 7 of the port P3 register is invalid and these bits are fixed to "0" when they are read. 2: After reset, be sure to write data to the port P9 register. Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 0 to 8 and 10) (addresses 416,516,816,916,C16,D16,1016,1116,1416,1816) Bit Bit name Functions At reset RW 0 RW 0 RW 0 RW 0 Port Pi0 direction selection bit 1 Port Pi1 direction selection bit 2 Port Pi2 direction selection bit 3 Port Pi3 direction selection bit 0 RW 4 Port Pi4 direction selection bit 0 RW 5 Port Pi5 direction selection bit 0 RW 6 Port Pi6 direction selection bit 0 RW 7 Port Pi7 direction selection bit 0 RW 0: Input mode (The port functions as an input port.) 1: Output mode (The port functions as an output port.) Note: Writing to bits 4 to 7 of the port P3 direction register is invalid and these bits are fixed to "0" when they are read. Bit b7 b6 b5 b4 b3 b2 b1 b0 Corresponding pin Pi7 Pi6 Pi5 Pi4 Pi3 Pi2 Pi1 Pi0 7736 Group User's Manual 20-9 APPENDIX Appendix 3. Control registers Port function control register b7 b6 b5 b4 0 b3 b2 b1 b0 Port function control register (address 6D16) At reset RW 0 RW Sub-clock output selection bit/ *Port-XC selection bit = "0" (when the sub clock is not used) Timer B2 clock source selection Timer B2 (event counter mode) bit clock source selection (Note 1) 0: TB2IN input (event counter mode) 1: Main clock divided by 32 (clock timer) *Port-XC selection bit = "1" (when the sub clock is used) Sub-clock output selection 0: Pin P67/TB2IN/f SUB functions as a programmable I/O port. 1: Sub clock f SUB is output from pin P67/TB2IN/f SUB. 0 RW 2 Timer B1 internal connect selection bit (Note 2) 0: No internal connection 1: Internal connection with timer B2 0 RW 3 Port P6 pull-up selection bit 0 0: No pull-up for pins P62/INT0 and P63/INT1 1: With pull-up for pins P62/INT0 and P63/INT1 0 RW 4 Must be fixed to "0." 0 RW 5 Port P6 pull-up selection bit 1 *Key input interrupt selection bit = "0" 0: No pull-up for pin P64/INT2 1: With pull-up for pin P64/INT2 *Key input interrupt selection bit = "1" 0: Pin P64/INT2 is a port with no pull-up. 1: Pin P64/INT2 is an input pin with pull-up and is used for the key input interrupt. 0 RW 6 Port P10 pull-up selection bit 0: No pull-up for pins P104/KI0 to P107/KI3 1: With pull-up for pins P104/KI0 to P107/KI3 0 RW 7 Key input interrupt selection bit 0: INT2 interrupt 1: Key input interrupt 0 RW Bit 0 1 Bit name Standby state selection bit Functions 0: Pins P0 to P3 are used for the external bus output. 1: Pins P0 to P3 are used for the port output. Port-Xc selection bit : Bit 4 of the oscillation circuit control register 0 (address 6C16) Notes 1: When the port-Xc selection bit = "0" and timer B2 operates in the timer mode or the pulse period /pulse width measurement mode, bit 1 is invalid. 2: When timer B1 operates in the event counter mode, bit 2 is valid. 20-10 7736 Group User's Manual APPENDIX Appendix 3. Control registers Oscillation circuit control register 1 b7 b6 b5 b4 b3 0 X b2 b1 b0 Oscillation circuit control register 1 (address 6F16) Bit name Bit Functions At reset RW 0 Main clock division selection bit 0: Main clock is divided by 2. (Note 1) 1: Main clock is not divided by 2. 0 RW 1 Main clock external input selection bit 0: Main-clock oscillation circuit is operating by itself. Watchdog timer is used when (Note 1) terminating stop mode. 1: Main clock is input from the external. Watchdog timer is not used when terminating stop mode. 0 RW 2 Sub clock external input selection bit 0: Sub-clock oscillation circuit is operating by itself. Pin P76 functions as pin XCOUT. (Note 1) Watchdog timer is used when terminating 0 RW stop mode. 1: Sub clock is input from the external. Pin P76 functions as a programmable I/O port. Watchdog timer is not used when terminating stop mode. 3 This bit is ignored. 1 RW 4 Must be fixed to "0" (Note 2). 0 RW 5 Not implemented. Undefined -- 6 Not implemented. Undefined -- 7 Clock prescaler reset bit 0 WO By writing "1" to this bit, clock prescaler is initialized. Notes 1: When writing to this register, follow the procedure shown in Figure 10.2.3. 2: The case where data "010101012" is written with the procedure shown in Figure 10.2.3 is not included. * When performing clock prescaler reset Write data "8016." (LDM instruction) * When writing to bits 0 to 3 Write data "010111012." (LDM instruction) Next instruction Write data "00000XXX2." (LDM instruction) (b2 to b0 in Figure 10.2.2) 7736 Group User's Manual 20-11 APPENDIX Appendix 4. Package outlines Appendix 4. Package outlines 20-12 7736 Group User's Manual APPENDIX Appendix 4. Package outlines 7736 Group User's Manual 20-13 APPENDIX Appendix 7. Examples of handling unused pins Appendix 7. Examples of handling unused pins The following are examples of handling unused pins. These are, however, just examples. In actual use, make the necessary adaptations and properly evaluate performance according to the user's application. 1. In single-chip mode Table 1 Examples of handling unused pins in single-chip mode Pins Handling example Connect these pins to pin Vcc or Vss via resistors after the pins are set to the input mode, or leave these pins open after they are set to the output mode (Note 1). Leave these pins open after writing data to the port P9 register (Note 3). Leave this pin open. P0-P8, P10 P9 _ ____ E , RDE EVL0, EVL1 XOUT (Note 2) AVcc Connect this pin to pin Vcc. AVss, V REF, BYTE Connect these pins to pin Vss. BSEL Connect this pin to pin Vcc or Vss. Notes 1: When leaving these pins open after they are set to the outpu these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power sou ports function as input ports. Software reliability can be enhanced when the contents of th ' direction registers are set periodically. This is because these contents may be chan which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 2: This is applied when an external clock is input to pin XIN . 3: When leaving port P9 pins open after writing data to the port P9 register, note the following: these pins are in a floating state from reset until the data is written to the port P9 register by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. N When setting ports to input mode N When setting ports to output mode P0-P8,P10 M37736MHBXXXGP M37736MHBXXXGP P9 E/RDE XOUT EVL0 EVL1 Left open VCC AVCC AVSS VREF BYTE BSEL VSS Fig. 9 Examples of handling unused pins in single-chip mode 20-14 tsemode, rce e ged above current by noise, note ports may the a increase program following:while runaway these 7736 Group User's Manual P0-P10 Left open E/RDE XOUT EVL0 EVL1 Left open VCC AVCC AVSS VREF BYTE BSEL VSS APPENDIX Appendix 7. Examples of handling unused pins 2. In memory expansion mode (External bus mode A) Table 2 Examples of handling unused pins in memory expansion mode (External bus mode A) Pins P42-P47, P5-P8, P10 (Note 7) P9 _____ BHE (Note 3), ALE (Note 4), HLDA XOUT (Note 6) _____ ____ HOLD, RDY AVcc AVss, VREF EVL0, EVL1 Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). Leave these pins open after writing data to the port P9 register (Note 8). Leave these pins open. (Note 5) Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Leave these pins open. Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: This is applied when "H" level is input to pin BYTE. 4: This is applied when "H" level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory expansion mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 6: This is applied when an external clock is input to pin XIN. 7: Set pin P4 2 / 1 as pin P4 2 . (Clock 1 output is disabled.) And then, for this pin, do the same handling as that for pins P4 3 to P4 7 , P5 to P8 and P10. 8: When leaving port P9 pins open after writing data to the port P9 register, note the following: these pins are in a floating state from reset until the data is written to the port P9 register by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. N When setting ports to input mode P42-P47, P5-P8, P10 N When setting ports to output mode P42-P47, P5-P10 M37736MHBXXXGP M37736MHBXXXGP P9 BHE ALE HLDA XOUT EVL0 EVL1 Left open Left open VCC HOLD RDY AVCC AVSS VREF BHE ALE HLDA XOUT EVL0 EVL1 Left open Left open Left open VCC HOLD RDY AVCC AVSS VREF VSS VSS Fig. 10 Examples of handling unused pins in memory expansionmode (External bus mode A) 7736 Group User's Manual 20-15 APPENDIX Appendix 7. Examples of handling unused pins 3. In memory expansion mode (External bus mode B) Table 3 Examples of handling unused pins in memory expansion mode (External bus mode B) Pins P42 -P47, P5-P8, P10 (Note 5) Handling example Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). Leave these pins open after writing data to the port P9 register (Note 6). Leave these pins open. (Note 3) P9 ____ ____ ____ WHE , WHL , RDE, _____ ___ ___ _____ HLDA , CS0 - CS 4, RSMP X OUT (Note 4) _____ ____ HOLD , RDY Leave this pin open. Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Leave these pins open. AVcc AVss, V REF EVL0, EVL1 Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the memory expansion mode by software. Therefore, a voltage level of this pin is undefined and the power source current may increase while this pin functions as an input port. 4: This is applied when an external clock is input to pin XIN . 5: Set pin P4 2 / 1 as pin P4 2 . (Clock 1 output is disabled.) And then, for this pin, do the same handling as that for pins P4 3 to P4 7, P5 to P8 and P10. 6: When leaving port P9 pins open after writing data to the port P9 register, note the following: these pins are in a floating state from reset until the data is written to the port P9 register by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. N When setting ports to input mode N When setting ports to output mode P42-P47, P5-P8, P10 M37736MHBXXXGP M37736MHBXXXGP P9 WEH WEL RDE HLDA RSMP XOUT CS0-CS4 EVL0 EVL1 P42-P47, P5-P10 Left open Left open VCC HOLD RDY AVCC AVSS VREF WEH WEL RDE HLDA RSMP XOUT CS0-CS4 EVL0 EVL1 HOLD RDY Left open Left open Left open VCC AVCC AVSS VREF VSS VSS Fig. 11 Examples of handling unused pins in memory expansion mode (External bus mode B) 20-16 7736 Group User's Manual APPENDIX Appendix 7. Examples of handling unused pins 4. In microprocessor mode (External bus mode A) Table 4 Examples of handling unused pins in microprocessor mode (External bus mode A) Pins Handling example P43-P4 7, P5-P8, P10 Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). P9 Leave these pins open after writing data to the port P9 register (Note 7). _____ BHE (Note 3), ALE (Note 4), HLDA , 1 Leave these pins open. (Note 3) XOUT (Note 6) Leave this pin open. _____ ____ HOLD, RDY Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Leave these pins open. AV CC AVSS , VREF EVL0, EVL1 Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: This is applied when "H" level is input to pin BYTE. 4: This is applied when "H" level is input to pin BYTE and the accessible area has a capacity of 64 Kbytes. 5: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the microprocessor mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. 6: This is applied when an external clock is input to pin XIN. 7: When leaving port P9 pins open after writing data to the port P9 register, note the following: these pins are in a floating state from reset until the data is written to the port P9 register by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. N When setting ports to input mode N When setting ports to output mode P43-P47, P5-P8, P10 P43-P47, P5-P10 M37736MHBXXXGP M37736MHBXXXGP P9 BHE ALE HLDA 1 XOUT EVL0 EVL1 Left open Left open VCC HOLD RDY AVCC AVSS VREF VSS BHE ALE HLDA 1 XOUT EVL0 EVL1 Left open Left open Left open VCC HOLD RDY AVCC AVSS VREF VSS Fig. 12 Examples of handling unused pins in microprocessor mode (External bus mode A) 7736 Group User's Manual 20-17 APPENDIX Appendix 7. Examples of handling unused pins 5. In microprocessor mode (External bus mode B) Table 5 Examples of handling unused pins in microprocessor mode (External bus mode B) Pins Processing example P43-P4 7, P5-P8, P10 Connect these pins to pin Vcc or Vss via resistors after these pins are set to the input mode, or leave these pins after they are set to the output mode (Notes 1 and 2). P9 Leave these pins open after writing data to the port P9 register (Note 5). ____ ____ ____ WHE , WHL , RDE, Leave these pins open. (Note 3) _____ _____ HLDA , 1, CS 0- CS 4, RSMP X OUT (Note 4) Leave this pin open. _____ ____ HOLD , RDY Connect these pins to pin Vcc via resistors after these pins are set to the input mode. (These pins are pulled high.) (Note 2) Connect this pin to pin Vcc. Connect these pins to pin Vss. Leave these pins open. AV CC AVSS , VREF EVL0, EVL1 Notes 1: When leaving these pins open after they are set to the output mode, note the following: these pins function as input ports from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. Software reliability can be enhanced when the contents of the above ports' direction registers are set periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 2: For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 3: When Vss level is applied to pin CNVss, note the following: these pins function as input ports from reset until the processor mode is switched to the microprocessor mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins function as input ports. 4: This is applied when an external clock is input to pin XIN . 5: When leaving port P9 pins open after writing data to the port P9 register, note the following: these pins are in a floating state from reset until the data is written to the port P9 register by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while they are in a floating state. N When setting ports to input mode N When setting ports to output mode P43-P47, P5-P8, P10 P43-P47, P5-P10 Left open P9 M37736MHBXXXGP M37736MHBXXXGP WEH WEL RDE HLDA 1 RSMP XOUT CS0-CS4 EVL0 EVL1 HOLD RDY AVCC Left open Left open VCC AVSS VREF WEH WEL RDE HLDA 1 RSMP XOUT CS0-CS4 EVL0 EVL1 HOLD RDY Left open Left open VCC AVCC AVSS VREF VSS VSS Fig. 13 Examples of handling unused pins in microprocessor mode (External bus mode B) 20-18 7736 Group User's Manual GLOSSARY This section briefly explains the terms used in this user's manual. Note that the terms defined here are applied to this manual only. Term Meaning verb Means one of the following: reading out, writing to, noun and both of them. Accessible area noun An accessible memory area. Its capacity is one of the following; a maximum of 16 Mbytes (for the 7733 Group or external bus mode A of the 7736 Group) and a maximum of 1 Mbytes (for the 7735 Group or external bus mode B of the 7736 Group). Access characteristics noun Indicates whether accessible or not. Branch verb Means moving the program's execution point (in other words, address) to another location regardless of conditions. __ ____ ____ ____ ____ Bus control signal noun A generic name for ALE,_____ E , RDE , WEL , WEH , RDY , _____ _____ HOLD, HLDA , BYTE, and RSMP signals Count down verb/ Means decrementing by 1 and counting. /Countdown noun Count source noun A signal which is counted by timers A, B, BRG, and the watchdog timer. It is f2, f 16, f 64 , or f 512, which is selected by the count source selection bits, etc. Count up/Countup verb/ Means incrementing by 1 and counting. noun Counter noun A value which can be read out when the timer Ai (Bi) contents(value) register is read out. Note that, at the reload timing, it is the reloaded value ("n"), and not "FFFF16" or "000016." ___ noun Chip select signal (for the 7735 Group or external bus CS mode B of the 7736 Group) noun Timer which correctly counts the number of external Event counter pulses without using a divider noun An accessible area for external devices. External area It has a capacity of 1 Mbytes. External bus noun A generic name for the external address bus and the external data bus noun A device connected externally to the microcomputer. External device A generic name for a memory, an I/O, and a peripheral IC. Fetch verb Means taking an op-code and operand from an instruction queue buffer into the CPU. noun A function which allows the user to control the count Gate function (of timer) source input of a timer Internal area noun An accessible internal area. A generic name for areas of the internal RAM, internal ROM, and SFR. noun A routine which is automatically executed when an Interrupt routine interrupt request is accepted. Set the start address of this routine into the interrupt vector table. noun An interrupt which is generated by a key input Key input interrupt Key matrix noun Switches which are arranged in lattice-like form noun A function which terminates the stop or the wait Key-on wakeup mode by using the key input LSB first noun A kind of data transfer format of serial I/O. It means transferring LSB (in other words, the least significant bit) first. noun A clock which is input from pin XIN Main clock MSB first noun A kind of data transfer format of serial I/O. It means transferring MSB (in other words, the most significant bit) first. Relevant term Access 7733/7735/7736 Group User's Manual Access Access Count up/Countup Count down /Countdown Internal area Prefetch External area Scan output Stop mode /Wait mode MSB first LSB first Term Overflow Power saving Prefetch Pull-down Pull-up Read-modify-write instruction Return input Scan output Signal required for accessing external device Stop mode Sub clock Synchronizing clock System clock UART Underflow Wait mode Meaning noun A state where the result obtained by the countup is greater than the counter resolution noun Means saving the power consumption by using the stop or wait mode, etc. verb Means taking an op-code and operand from a memory into an instruction queue buffer. noun Means connecting with Vss line for stabilizing its I/O level. noun Means connecting with Vcc line for stabilizing its I/O level. noun An instruction which reads the contents of SFR and RAM, modifies them, and writes them back to the same addresses. They are the ASL, CLB, DEC, INC, LSR, ROL, ROR, and SEB instructions noun Input signal from the key matrix to the microcomputer. It is used to detect a key input noun Output signal from the microcomputer to the key matrix. It is used to detect a key input. noun A generic name for a bus control signal, an address bus signal, a data bus signal, and a chip select signal. (Note that the chip select signal is only for the 7735 Group or external bus mode B of the 7736 Group.) noun A state where all of the oscillation circuits stop operating and the program execution is stopped. By executing the STP instruction, the microcomputer enters the stop mode. noun A clock which is input from pin XCIN noun A transfer clock for the clock synchronous serial I/O noun One of the following: the main clock, which is input from pin XIN or the sub clock, which is input from pin XCIN Note: In the microcomputers other than the 7733/7735/ 7736 Group, definition of "system clock" may be different. noun Clock asynchronous serial I/O. When it is used as the name of a functional block, this term also means the serial I/O which can be switched to the clock synchronous serial I/O. noun A state where the result obtained by the countdown is greater than the counter resolution noun A state where one or more oscillation circuits are operating (in other words, they are oscillating), however, the program execution is stopped. By executing the WIT instruction, the microcomputer enters the wait mode. 7733/7735/7736 Group User's Manual Relevant term Underflow Countup/Count up Stop mode Wait mode Fetch Pull-up Pull-down Scan output Return input Key matrix Bus control signal Wait mode Main clock Internal clock Clock synchronous serial I/O Overflow Count down/Countdown Stop mode REVISION DESCRIPTION LIST Rev. No. 7733/7735/7736 Group User's Manual Rev. date Revision Description 1.00 First Edition 970425 2.00 The following are revised. 980731 Page Previous Version PART 1 P2-8 (2) Bit 1: Zero flag (Z) This flag is ignored for an addition instruction in the decimal mode (the ADC instruction). PART 1 P2-19 Fig. 2.4.1 PART 1 P21-30 PART 1 P2-21 Fig. 2.4.3 Revised Version This flag is ignored for an addition and subtraction instructions (the ADC and the SBC instructions) in the decimal mode. Functions Functions ROM size (addresses) b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 : : : : : : : : ROM size b2 b1 b0 124 K (00100016 `01FFFF16) 120 K (00200016 `01FFFF16) Do not select. Do not select. Do not select. Do not select. 96 K (00800016 `01FFFF16) 32 K (00800016 `00FFFF16) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 : : : : : : : : 124 Kbytes, 120 Kbytes, 60 Kbytes, Do not select. 32 Kbytes, 16 Kbytes, 96 Kbytes, Do not select. RAM size 3968 bytes 3968 bytes 2048 bytes 2048 bytes 2048 bytes 3968 bytes Notes 1: ***** 2: When changing these bits, this change must be performed in an area which is internal ROM area before and after this change, for example addresses 008000 16 to 00FFFF 16. Also, when changing these bits, be sure to follow the procedure listed below. 3: In the M37733S4BFP, M37733S4LHP, M37735S4BFP, or M37735S4LHP, writing to address 6316 is disabled. Notes 1: ***** 2: When changing these bits, this change must be performed in an area which is internal ROM area before and after this change, for example addresses 00C000 16 to 00FFFF 16 . Also, when changing these bits, be sure to follow the procedure listed below. 3: This figure is applied only to the H37733MHBXXXFP. For the other microcomputers, please refer to the latest datasheets on the English document CDROM or our Web site. Omitted. Refer to pages 2 and 3. 2: When the counter operates as an 8-bit pulse width modulator, pin TAiOUT outputs "L" level of which width is the same as the PWM pulse's "H" level width which was set. And then, pin TAiOUT starts the PWM pulse output. 2: When the counter operates as an 8-bit pulse width modulator, after a trigger occurs, pin TAiOUT outputs "L" level of which width is the same as the PWM pulse's "H" level width which was set. And then, pin TAiOUT starts the PWM pulse output. PART 1 P21-3 Fig. 2 PART 2 P21-4 Fig. 2 PART 3 P20-4 Fig. 2 PART 1 P6-47 Line 23 (1) REVISION DESCRIPTION LIST 7733/7735/7736 Group User's Manual Revised Version * Memory allocation selection bits (b2, b1, b0)=(0,1,0) * ROM size: 60 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 00087F16 00100016 2048 bytes * Memory allocation selection bits (b2, b1, b0)=(1,0,0) * ROM size: 32 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 00087F16 Peripheral device control registers (SFR) 2048 bytes (1.9 Kbytes) (29.9 Kbytes) Bank 016 Internal ROM area 60 Kbytes Refer to Appendix 2. 00800016 Internal ROM area 32 Kbytes 00FFFF16 01000016 00000016 00007F16 00FFFF16 01000016 Interrupt vector table 00FFD616 A-D/UART2 trans./rece. UART1 transmission UART1 reception UART0 transmission Bank 116 UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input 01FFFF16 02000016 Bank 216 INT1 INT0 Watchdog timer DBC BRK instruction Zero divide 02FFFF16 00FFFE16 FF000016 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Bank FF16 FFFFFF 1 6 RESET FFFFFF 1 6 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes.") 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. (2) M7700-81-9801 1998 N1 16 oe 7733/7735/7736 Group User's Manual REVISION DESCRIPTION LIST Revised Version * Memory allocation selection bits (b2, b1, b0)=(1,0,1) * ROM size: 16 Kbytes * RAM size: 2048 bytes 00000016 SFR area 00007F16 00008016 Internal RAM area 00087F16 * Memory allocation selection bits (b2, b1, b0)=(1,1,0) * ROM size: 96 Kbytes * RAM size: 3968 bytes 00000016 00007F16 00008016 2048 bytes 000FFF16 00100016 Bank 016 (45.9 Kbytes) SFR area 00000016 Internal RAM area 3968 bytes Peripheral device control registers (SFR) (28 Kbytes) Refer to Appendix 2. 00800016 00C00016 00FFFF16 01000016 Internal ROM area 16 Kbytes Internal ROM area 32 Kbytes 00007F16 00FFFF16 01000016 Interrupt vector table 00FFD616 A-D/UART2 trans./rece. UART1 transmission UART1 reception Internal ROM area 64 Kbytes Bank 116 01FFFF16 02000016 UART0 transmission UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 01FFFF16 Timer A1 Timer A0 INT2/Key input Bank 216 INT1 INT0 Watchdog timer DBC BRK instruction Zero divide 02FFFF16 00FFFE16 RESET FF000016 : Unused area in the single-chip mode External memory area in the memory expansion or microprocessor mode Bank FF16 FFFFFF 1 6 FFFFFF 1 6 Notes 1: Access to internal ROM area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes.") 2: Banks 1016 to FF16 cannot be accessed in the 7735 Group and in external bus mode B of the 7736 Group. (3) REVISION DESCRIPTION LIST Rev. No. 2.00 7733/7735/7736 Group User's Manual Rev. date Revision Description Page PART 1 P7-31 Line 7 Previous Version Revised Version The timer Bi overflow flag is cleared to "0" when a value is written to the timer Bi mode register with the count start flag = "1." The timer Bi overflow flag is cleared to "0" at the next count timing of the count source when a value is written to the timer Bi mode register with the count start flag = "1." PART 1 P8-40 Fig.8.3.13 PART 1 P8-46 Table 8.4.4 PART 1 P8-59 Line 2 CLK CLKi CTSi RTSi 980731 CLK CLKi CTSi RTSi 14400 f 2 52(3F16) 14490.57 53(4016) 14467.59 14400 f2 52(3416) 14490.57 53(3516 ) 14467.59 And then, reception is started when ST is detected. And then, the transfer clock is generated when ST is detected, and reception is started. PART 1 P8-59 Fig.8.4.11 CTS PART 1 P8-60 Fig. 8.4.12 RTSi Transfer clock CTSi Transfer clock The transfer clock is generated at the falling edge of start bit, and reception is started. Reception is started at the falling edge of start bit. PART 1 P8-62 Line 20 PART 1 P11-17 Table 11.4.3 For the slave microcomputer whose address matches bits 6 to 0 in the receive data, clear the sleep mode. (Do not terminate the sleep mode for the other slave microcomputers.) Interrupt A-D con versio n inte rrup t RTSi Conditions for each function which generates interrupt request when clocks f2 and f512 are stopped when clocks f2 and f512 are not stopped Disabled Enabled For the slave microcomputer whose address matches bits 6 to 0 in the receive data, terminate the sleep mode. (Do not terminate the sleep mode for the other slave microcomputers.) Conditions for each function which generates interrupt request Interrupt A-D con versio n inte rrup t (4) when clocks f2 and f512 are stopped Disabled when clocks f2 and f512 are not stopped Enabled in one-shot mode and single sweep mode REVISION DESCRIPTION LIST 7733/7735/7736 Group User's Manual Rev. No. 2.00 Rev. date Revision Description Previous Version Page PART 1 P19-4 Table 19.1.3 PART 1 P21-80 Revised Version Memory allocation selection bits b2 b1 b0 0 0 0 0 0 1 1 1 1 1 Memory allocation selection bits Programmable area Programmable area b2 b1 b0 0100016 -1FFFF16 0 0 0 0100016-1FFFF16 0200016 -1FFFF16 0 0 1 0200016-1FFFF16 0 0800016 -1FFFF16 0 1 0 0100016-0FFFF16 1 0800016 -0FFFF16 1 0 0 0800016-0FFFF16 1 0 1 0C00016 -0FFFF16 1 1 0 0800016-1FFFF16 A A When writing data to the oscillation circuit control register 1 ...... When writing data to the oscillation circuit control register 1 ...... * When initializing the clock prescaler * When initializing the clock prescaler Write data "8016." (LDM instruction) Write data "8016." (LDM instruction) Clock prescaler is reset. Clock prescaler is reset. * When writing to bits 0 to 2 * When writing to bits 0 to 2 Write data "0101010116." (LDM instruction) Write data "010101012." (LDM instruction) Next instruction Write data "00000XXX16." (LDM instruction) Next instruction Write data "00001XXX2." (LDM instruction) (Note) Bits 0 to 2 are set. Bits 0 to 2 are set. When writing data to the memory allocation control register ...... Write data "0101010116." (LDM instruction) Next instruction Note: In the case of the 7735 Group, write data "00000XXX2." When writing data to the memory allocation control register ...... Write data "010101012." (LDM instruction) Write data "00001XXX16." (LDM instruction) Write data "00000XXX2 ." (LDM instruction) Bits 0 to 2 are set. Bits 0 to 2 are set. PART 1 P21-82 Line 18 980731 ***** addresses 00800016 to 00FFFF16 . ***** addresses 00C00016 to 00FFFF16. (5) Next instruction MITSUBISHI SEMICONDUCTORS USER'S MANUAL 7733 Group/7735 Group/7736 Group Mar. First Edition 1997 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. (c)1997 MITSUBISHI ELECTRIC CORPORATION User's Manual 7733 Group 7735 Group 7735 Group MITSUBISHI ELECTRIC CORPORATION HEAD OFFICE: MITSUBISHI DENKI BLDG., MARUNOUCHI, TOKYO 100. TELEX: J24532 CABLE: MELCO TOKYO H-EF493-A KI-9703 Printed in Japan (ROD) (c) 1997 MITSUBISHI ELECTRIC CORPORATION. New publication, effective Mar. 1997. Specifications subject to change without notice.