1
®
DAC7715
DAC7715
Copyright © 2000 Texas Instruments Incorporated PDS-1572A Printed in U.S.A. September, 2000
Quad, Serial Input, 12-Bit, Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
● LOW POWER: 250mW (max)
● UNIPOLAR OR BIPOLAR OPERATION
●SETTLING TIME: 10µs to 0.012%
● 12-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
● DOUBLE-BUFFERED DATA INPUTS
● SMALL SO-16 PACKAGE
APPLICATIONS
● PROCESS CONTROL
● ATE PIN ELECTRONICS
● CLOSED-LOOP SERVO-CONTROL
● MOTOR CONTROL
● DATA ACQUISITION SYSTEMS
● DAC-PER-PIN PROGRAMMERS
DESCRIPTION
The DAC7715 is a quad, serial input, 12-bit, voltage
output Digital-to-Analog Converter (DAC) with
guaranteed 12-bit monotonic performance over the
–40°C to +85°C temperature range. An asynchronous
reset clears all registers to either mid-scale (800H) or
zero-scale (000H), selectable via the RESETSEL pin.
The individual DAC inputs are double buffered to
allow for simultaneous update of all DAC outputs.
The device can be powered from a single +15V supply
or from dual +15V and –15V supplies.
Low power and small size makes the DAC7715 ideal
for automatic test equipment, DAC-per-pin program-
mers, data acquisition systems, and closed-loop servo-
control. The device is available in a SO-16 package
and is guaranteed over the –40°C to +85°C tempera-
ture range.
DAC A
DAC
Register A
Input
Register A
DAC B
DAC
Register B
Input
Register B
DAC C
DAC
Register C
Input
Register C
DAC D
DAC
Register D
Input
Register D
V
REFH
V
CC
V
SS
V
OUTD
V
OUTC
V
OUTB
V
OUTA
V
REFL
LOADDACS
GND
CLK
CS
12
SDI
RESETRESETSELLOADREG
Serial-to-
Parallel
Shift
Register
DAC
Select
DAC7715
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
http://www.burr-brown.com/ http://www.ti.com/
SBAS140
®
2
DAC7715
SPECIFICATIONS (Dual Supply)
At TA = –40°C to +85°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
DAC7715U DAC7715UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ACCURACY
Linearity Error ±2±1 LSB(1)
Linearity Matching(2) ±2±1 LSB
Differential Linearity Error ±1±1 LSB
Monotonicity TMIN to TMAX 12 ✻Bits
Zero-Scale Error Code = 000H±2✻LSB
Zero-Scale Drift 1✻ppm/°C
Zero-Scale Matching(2) ±2±1 LSB
Full-Scale Error Code = FFFH±2✻LSB
Full-Scale Matching(2) ±2±1 LSB
Power Supply Sensitivity At Full Scale 10 ✻ppm/V
ANALOG OUTPUT
Voltage Output(3) VREFL VREFH ✻✻V
Output Current –5 +5 ✻✻mA
Load Capacitance No Oscillation 500 ✻pF
Short-Circuit Current ±20 ✻mA
Short-Circuit Duration To VSS, VCC, or GND Indefinite ✻
REFERENCE INPUT
VREFH Input Range
VREFL +1.25
+10 ✻✻V
VREFL Input Range –10
VREFH – 1.25
✻✻V
Ref High Input Current –0.5 3.0 ✻✻mA
Ref Low Input Current –3.5 0 ✻✻mA
DYNAMIC PERFORMANCE
Settling Time To ±0.012%, 20V Output Step 8 10 ✻✻ µs
Channel-to-Channel Crosstalk
Full-Scale Step
0.25 ✻LSB
Digital Feedthrough 2 ✻nV-s
Output Noise Voltage f = 10kHz 65 ✻nV/√Hz
DIGITAL INPUT
Logic Levels
VIH IIH ≤ ±10µA 3.325 ✻V
VIL IIL ≤ ±10µA 1.575 ✻V
Data Format Straight Binary ✻
POWER SUPPLY REQUIREMENTS
VCC +14.25 +15.75 ✻✻V
VSS –15.75 –14.25 ✻✻V
ICC 6 8.5 ✻✻ mA
ISS –8 –6 ✻✻ mA
Power Dissipation 180 250 ✻✻ mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻°C
NOTES: (1) LSB means Least Significant Bit; if VREFH equals +10V and VREFL equals –10V, then one LSB equals 4.88mV. (2) All DAC outputs will match within
the specified error band. (3) Ideal output voltage does not take into account zero or full-scale error.
3
®
DAC7715
SPECIFICATIONS (Single Supply)
At TA = –40°C to +85°C, VCC = +15V, VSS = GND, VREFH = +10V, VREFL = 0V, unless otherwise noted.
DAC7715U DAC7715UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ACCURACY
Linearity Error(1) ±2±1 LSB(2)
Linearity Matching(3) ±2±1 LSB
Differential Linearity Error ±1±1 LSB
Monotonicity TMIN to TMAX 12 ✻Bits
Zero-Scale Error Code = 004H±4✻LSB
Zero-Scale Drift 2✻ppm/°C
Zero-Scale Matching(3) ±4±2 LSB
Full-Scale Error Code = FFFH±4✻LSB
Full-Scale Matching(3) ±4±2 LSB
Power Supply Sensitivity At Full Scale 20 ✻ppm/V
ANALOG OUTPUT
Voltage Output(4) VREFL VREFH ✻✻V
Output Current –5 +5 ✻mA
Load Capacitance No Oscillation 500 ✻pF
Short-Circuit Current ±20 ✻mA
Short-Circuit Duration To VCC or GND Indefinite ✻
REFERENCE INPUT
VREFH Input Range
VREFL +1.25
+10 ✻✻V
VREFL Input Range 0
VREFH – 1.25
✻✻V
Ref High Input Current –0.3 1.5 ✻✻mA
Ref Low Input Current –2.0 0 ✻✻mA
DYNAMIC PERFORMANCE
Settling Time(5) To ±0.012%, 10V Output Step 8 10 ✻✻ µs
Channel-to-Channel Crosstalk 0.25 ✻LSB
Digital Feedthrough 2 ✻nV-s
Output Noise Voltage f = 10kHz 65 ✻nV/√Hz
DIGITAL INPUT
Logic Levels
VIH IIH ≤ ±10µA 3.325 ✻V
VIL IIL ≤ ±10µA 1.575 ✻V
Data Format Straight Binary ✻
POWER SUPPLY REQUIREMENTS
VCC 14.25 15.75 ✻✻V
ICC 3.0 ✻✻ mA
Power Dissipation 45 ✻mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻°C
NOTES: (1) If VSS = 0V, specification applies at code 004H and above. (2) LSB means Least Significant Bit; if VREFH equals +10V and VREFL equals 0V, then one
LSB equals 2.44mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage does not take into account zero or full-scale error.
(5) Full-scale positive 10V step and negative step from code FFFH to 020H.
®
4
DAC7715
MAXIMUM MAXIMUM
LINEARITY DIFFERENTIAL PACKAGE SPECIFICATION
ERROR LINEARITY DRAWING TEMPERATURE ORDERING TRANSPORT
PRODUCT (LSB) (LSB) PACKAGE NUMBER RANGE NUMBER(1) MEDIA
DAC7715U ±2±1 SOIC-16 211 –40°C to +85°C DAC7715U Rails
"" """ "DAC7715U/1K Tape and Reel
DAC7715UB ±1±1 SOIC-16 211 –40°C to +85°C DAC7715UB Rails
"" """ "DAC7715UB/1K Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC7715UB/1K” will get a single 1000-piece Tape and Reel.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
ESD PROTECTION CIRCUITS
REF
H
Typical of Each
Logic Input Pin
Internal V
DD
REF
L
V
SS
V
OUT
V
SS
GND
V
CC
V
CC
ABSOLUTE MAXIMUM RATINGS(1)
VCC to VSS ...........................................................................–0.3V to +32V
VCC to GND......................................................................... –0.3V to +16V
VSS to GND .........................................................................+0.3V to –16V
VREFH to GND ....................................................................... –9V to +11V
VREFL to GND (VSS = –15V) ................................................. –11V to +9V
VREFL to GND (VSS = 0V) ....................................................–0.3V to +9V
VREFH to VREFL ....................................................................... –1V to +22V
Digital Input Voltage to GND .............................................. –0.3V to 5.8V
Digital Output Voltage to GND............................................ –0.3V to 5.8V
Maximum Junction Temperature................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
5
®
DAC7715
PIN CONFIGURATION—U Package
Top View SOIC
PIN DESCRIPTIONS—U Package
PIN LABEL DESCRIPTION
1V
CC Positive Supply Voltage, +15V nominal.
2V
OUTD DAC D Voltage Output
3V
OUTC DAC C Voltage Output
4V
REFL Reference Input Voltage Low. Sets minimum out-
put voltage for all DACs.
5V
REFH Reference Input Voltage High. Sets maximum out-
put voltage for all DACs.
6V
OUTB DAC B Voltage Output
7V
OUTA DAC A Voltage Output
8V
SS Negative Supply Voltage, 0V or –15V nominal.
9 GND Ground
10 SDI Serial Data Input
11 CLK Serial Data Clock
12 CS Chip Select Input
13 LOADDACS All DAC registers become transparent when
LOADDACS is LOW. They are in the latched state
when LOADDACS is HIGH.
14 LOADREG The selected input register becomes transparent
when LOADREG is LOW. It is in the latched state
when LOADREG is HIGH.
15 RESET Asynchronous Reset Input. Sets DAC and input
registers to either zero-scale (000H) or mid-scale
(800H) when LOW. RESETSEL determines which
code is active.
16 RESETSEL When LOW, a LOW on RESET will cause the DAC
and input registers to be set to code 000H. When
RESETSEL is HIGH, a LOW on RESET will set the
registers to code 800H.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
VOUTD
VOUTC
VREFL
VREFH
VOUTB
VOUTA
VSS
RESETSEL
RESET
LOADREG
LOADDACS
CS
CLK
SDI
GND
DAC7715U
®
6
DAC7715
TYPICAL PERFORMANCE CURVES: VSS = 0V
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 25°C
(Typical of Each Output Channel)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
LE (LSB)DLE (LSB)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
LE (LSB)DLE (LSB)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 85°C
(Typical of Each Output Channel)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel –40°C
(Typical of Each Output Channel)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
LE (LSB)DLE (LSB)
–30 –20 –10 0 10 20 30 40 50 60 70 80 90–40 Temperature (°C)
ZERO-SCALE ERROR vs TEMPERATURE
(Code 004
H
)
Zero-Scale Error (mV)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DAC A
DAC C
DAC B
DAC D
–30 –20 –10 0 10 20 30 40 50 60 70 80 90–40 Temperature (°C)
FULL-SCALE ERROR vs TEMPERATURE
(Code FFF
H
)
Full-Scale Error (mV)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DAC D DAC B
DAC C DAC A
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
V
REF
Current (mA)V
REF
Current (mA)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
CURRENT vs CODE
All DACs Set to Indicated Code
V
REFH
V
REFL
7
®
DAC7715
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
4.5
3.5
2.5
1.5
0.5
0
POWER SUPPLY CURRENT vs TEMPERATURE
Quiescent Current (mA)
Temperature (°C)
–40–30 –20 –10 0 10 20 30 40 50 60 70 80 90 100
I
CC
ICC
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
6.00
5.00
4.00
3.00
2.00
1.00
0
ICC (mA)
No Load, All DACs Set to Indicated Code
200H400H600H800HA00HC00HE00HFFFH
000HDigital Input Code
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
Time (1µs/div)
7FF
H
to 800
H
+5V
LOADDACS
0
Output Voltage (200mV/div)
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
Time (1µs/div)
800
H
to 7FF
H
+5V
LOADDACS
0
Output Voltage (200mV/div)
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +10V)
Output Voltage
Time (2µs/div)
Large Signal
Settling T ime: 5V/div
Small Signal
Settling T ime: 1LSB/div
+5V
LOADDACS
0
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to Code 020
H
)
Output Voltage
Time (2µs/div)
Large Signal
Settling T ime: 5V/div
Small Signal
Settling T ime: 1LSB/div
+5V
LOADDACS
0
®
8
DAC7715
TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.)
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
15
12
9
6
3
0
R
LOAD
(kW)
0.01 0.1 1 10 100
OUTPUT VOLTAGE vs R
LOAD
V
OUT
(V)
Source
Sink
SINGLE SUPPLY CURRENT LIMIT vs INPUT CODE
20
15
10
5
0
–5
–10
–15
–20
I
OUT
(mA)
200
H
400
H
600
H
800
H
A00
H
C00
H
E00
H
FFF
H
000
H
Digital Input Code
Short to Ground
Short to V
CC
+15V
POWER SUPPLY REJECTION RATIO vs FREQUENCY
Frequency (Hz)
PSRR (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 10
2
10
3
10
4
10
5
10
6
10
1
OUTPUT NOISE vs FREQUENCY
Frequency (kHz)
Noise (nV/√Hz)
1000
100
10 0.1 1 10 100 1000 100000
Code 020
H
Code FFF
H
9
®
DAC7715
TYPICAL PERFORMANCE CURVES: VSS = –15V
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 25°C
(Typical of Each Output Channel)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
LE (LSB)DLE (LSB)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 85°C
(Typical of Each Output Channel)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
LE (LSB)DLE (LSB)
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E00
H
FFF
H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel –40°C
(Typical of Each Output Channel)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
LE (LSB)DLE (LSB)
2.5
2.0
1.5
1.0
0.5
0
–0.5
V
REF
Current (mA)
CURRENT vs CODE
All DACs Set to Indicated Code
V
REFH
V
REFL
000
H
200
H
400
H
600
H
800
H
Digital Input Code
A00
H
C00
H
E000
H
FFF
H
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
V
REF
Current (mA)
–30 –20 –10 0 10 20 30 40 50 60 70 80 90–40 Temperature (°C)
BIPOLAR ZERO-SCALE ERROR vs TEMPERATURE
(Code 800H)
Bipolar Zero-Scale Error (mV)
DAC A DAC D
DAC C
DAC D
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0 –30 –20 –10 0 10 20 30 40 50 60 70 80 90–40 Temperature (°C)
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
(Code FFFH)
Positive Full-Scale Error (mV)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
DAC A
DAC B
DAC C
DAC D
®
10
DAC7715
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
–30 –20 –10 0 10 20 30 40 50 60 70 80 90–40 Temperature (°C)
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
(Code 000
H
)
Negative Full-Scale Error (mV)
DAC CDAC B
DAC A
DAC D
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
8
6
4
2
0
–2
–4
–6
–8
Data = FFF
H
(all DACs)
No Load
POWER SUPPLY CURRENT vs TEMPERATURE
Quiescent Current (mA)
Temperature (°C)
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
I
CC
I
SS
15
10
5
0
–5
–10
–15
R
LOAD
(kΩ)
0.01 0.1 1 10 100
OUTPUT VOLTAGE vs R
LOAD
V
OUT
(V)
Sink
Source
SUPPLY CURRENT vs CODE
8
6
4
2
0
–2
–4
–6
–8
Supply Current (mA)
I
SS
200
H
400
H
600
H
800
H
A00
H
C00
H
E00
H
FFF
H
000
H
Digital Input Code
I
CC
No Load, All 4 DACs Set to Indicated Code
OUTPUT VOLTAGE vs SETTLING TIME
(–10V to +10V)
Output Voltage
Time (2µs/div)
Large Signal
Settling T ime: 5V/div
Small Signal
Settling T ime: 0.5LSB/div
+5V
LOADDACS
0
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to –10V)
Output Voltage
Time (2µs/div)
Large Signal
Settling T ime: 5V/div
Small Signal
Settling T ime: 0.5LSB/div
+5V
LOADDACS
0
11
®
DAC7715
TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.)
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
DUAL SUPPLY CURRENT LIMIT vs INPUT CODE
SHORT T O GROUND
20
15
10
5
0
–5
–10
–15
–20
I
OUT
(mA)
200
H
400
H
600
H
800
H
A00
H
C00
H
E00
H
FFF
H
000
H
Digital Input Code
–15V
POWER SUPPLY REJECTION RATIO vs FREQUENCY
Frequency (Hz)
PSRR (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 10
2
10
3
10
4
10
5
10
6
10
1
+15V
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
Time (1µs/div)
+5V
LOADDACS
0
Output Voltage (200mV/div)
7FF
H
to 800
H
800
H
to 7FF
H
Noise at any code
OUTPUT NOISE vs FREQUENCY
Frequency (kHz)
Noise (nV/√Hz)
1000
100
10 0.1 1 10 100 1000 100000
BROADBAND NOISE
Time (1ms/div)
Noise Voltage (500µV/div)
®
12
DAC7715
THEORY OF OPERATION
The DAC7715 is a quad, serial input, 12-bit, voltage output
DAC. The architecture is a classic R-2R ladder configuration
followed by an operational amplifier that serves as a buffer,
as shown in Figure 1. Each DAC has its own R-2R ladder
network and output op amp, but all share the reference
voltage inputs. The minimum voltage output (“zero-scale”)
and maximum voltage output (“full-scale”) are set by external
voltage references (VREFL and VREFH, respectively). The
FIGURE 2. Basic Single-Supply Operation of the DAC7715.
NOTE: (1) As configured, RESET LOW sets all internal registers to code 000
H
(0V).
If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800
H
(5.00V).
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
V
OUTD
V
OUTC
V
REFL
V
REFH
V
OUTB
V
OUTA
V
SS
RESETSEL
RESET
LOADREG
LOADDACS
CS
CLK
SDI
GND
Reset DACs
(1)
Update Selected Register
Update All DAC Registers
Chip Select
Clock
Serial Data In
DAC7715
0.1µF
0.1µF
0V to +10V
1µF to 10µF
+15V
+
0V to +10V
0V to +10V
0V to +10V
+10.00V
R
2R
2R2R 2R 2R 2R 2R 2R 2R
VREFH
VOUT
RRRRRR
VREFL
RF
FIGURE 1. DAC7715 Architecture.
digital input is a 16-bit serial word that contains the 12-bit
DAC code and a 2-bit address code that selects one of the four
DACs (the two remaining bits are unused). The converter can
be powered from a single +15V supply or a dual ±15V
supply. Each device offers a reset function which immedi-
ately sets all DAC output voltages and internal registers to
either zero-scale (code 000H) or mid-scale (code 800H). The
reset code is selected by the state of the RESETSEL pin
(LOW = 000H, HIGH = 800H). See Figures 2 and 3 for the
basic operation of the DAC7715.
FIGURE 3. Basic Dual-Supply Operation of the DAC7715.
NOTE: (1) As configured, RESET LOW sets all internal registers to code 800H (0V).
If RESETSEL is LOW, RESET LOW sets all internal registers to code 000H (–10 V).
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
VOUTD
VOUTC
VREFL
VREFH
VOUTB
VOUTA
VSS
RESETSEL
RESET
LOADREG
LOADDACS
CS
CLK
SDI
GND
Reset DACs(1)
Update Selected Register
Update All DAC Registers
Chip Select
Clock
Serial Data In
DAC7715
0.1µF
0.1µF
–10V to +10V
1µF to 10µF
+15V
–15V
+
0.1µF
1µF to 10µF
+
–10V to +10V
–10.00V
0.1µF
+10.00V
–10V to +10V
–10V to +10V
+5V
13
®
DAC7715
ANALOG OUTPUTS
When VSS = –15V (dual supply operation), the output
amplifier can swing to within 4V of the supply rails, over
the –40°C to +85°C temperature range. With VSS = 0V
(single-supply operation), the output can swing to ground.
Note that the settling time of the output op amp will be
longer with voltages very near ground. Also, care must be
taken when measuring the zero-scale error when VSS = 0V.
If the output amplifier has a negative offset, the output
voltage may not change for the first few digital input codes
(000H, 001H, 002H, etc.) since the output voltage cannot
swing below ground.
At the negative offset limit of –4LSB (–9.76mV), for the
single-supply case, the first specified output starts at code
004H.
REFERENCE INPUTS
The reference inputs, VREFL and VREFH, can be any voltage
between VSS + 4V and VCC – 4V provided that VREFH is at
least 1.25V greater than VREFL. The minimum output of
each DAC is equal to VREFL – 1LSB plus a small offset
voltage (essentially, the offset of the output op amp). The
maximum output is equal to VREFH plus a similar offset
voltage. Note that VSS (the negative power supply) must
either be connected to ground or be in the range of –14.75V
to –15.25V. The voltage on VSS sets several bias points
within the converter. If VSS is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not guaranteed.
The current into the reference inputs depends on the DAC
output voltages and can vary from a few microamps to
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tDS
Data Valid to CLK Rising
25 ns
tDH
Data Held Valid after CLK Rises
20 ns
tCH
CLK HIGH
30 ns
tCL
CLK LOW
50 ns
tCSS
CS LOW to CLK Rising
55 ns
tCSH
CLK HIGH to CS Rising
15 ns
tLD1
LOADREG HIGH to CLK Rising
40 ns
tLD2
CLK Rising to LOADREG LOW
15 ns
tLDRW
LOADREG LOW Time
45 ns
tLDDW
LOADDACS LOW Time
45 ns
tRSSH
RESETSEL Valid to RESET LOW
25 ns
tRSTW
RESET LOW Time
70 ns
tS
Settling Time
10 µs
FIGURE 4. DAC7715 Timing.
approximately 3mA. The reference input appears as a vary-
ing load to the reference. If the reference can sink or source
the required current, a reference buffer is not required. See
“Reference Current vs Code” in the Typical Performance
Curves.
The analog supplies must come up before the reference
power supplies, if they are separate. If the power supplies for
the references come up first, then the VCC and VSS supplies
will be powered from the reference via the ESD protection
diodes (see page 4).
DIGITAL INTERFACE
Figure 4 and Table I provide the basic timing for the
DAC7715. The interface consists of a serial clock (CLK),
serial data (SDI), a load register signal (LOADREG), and a
TABLE I. Timing Specifications (TA = –40°C to +85°C).
A1
(MSB) (LSB)
SDI
CLK
CS
LOADREG
A0 X X D11 D10 D9 D3 D2 D1 D0
SDI
CLK
LOADDACS
RESET
V
OUT
tcss
t
LD1
t
CL
t
CH
t
DS
t
DH
t
LD2
t
LDRW
t
LDDW
t
S
t
RSTW
t
RSSH
t
CSH
t
S
1 LSB
ERROR BAND 1 LSB
ERROR BAND
RESETSEL
®
14
DAC7715
STATE OF
SELECTED SELECTED STATE OF
INPUT INPUT ALL DAC
A1 A0 LOADREG LOADDACS RESET REGISTER REGISTER REGISTERS
L(1) LLH
(2) H A Transparent Latched
L H L H H B Transparent Latched
H L L H H C Transparent Latched
H H L H H D Transparent Latched
X(3) X H L H NONE (All Latched) Transparent
X X H H H NONE (All Latched) Latched
X X X X L ALL Reset(4) Reset(4)
NOTES: (1) L = Logic LOW. (2) H = Logic HIGH. (3) X = Don’t Care. (4) Resets to either 000H or 800H, per the RESETSEL state (LOW = 000H, HIGH = 800H).
When RESET rises, all registers that are in their latched state retain the reset value.
TABLE II. Control Logic Truth Table.
CS(1) CLK(1) LOADREG RESET SERIAL SHIFT REGISTER
H(2) X(3) H H No Change
L(4) L H H No Change
L↑(5) H H Advanced One Bit
↑L H H Advanced One Bit
H(6) XL
(7) H No Change
H(6) XHL
(8) No Change
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH.
(3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition.
(6) A HIGH value is suggested in order to avoid a “false clock” from
advancing the shift register and changing the shift register. (7) If data is
clocked into the serial register while LOADREG is LOW, the selected input
register will change as the shift register bits “flow” through A1 and A0. This
will corrupt the data in each input register that has been erroneously
selected. (8) RESET LOW causes no change in the contents of the serial
shift register.
TABLE III. Serial Shift Register Truth Table.
CLK when CS rises at the end of a serial transfer. If CLK is
LOW when CS rises, the OR gate will provide a rising edge
to the shift register, shifting the internal data one additional
bit. The result will be incorrect data and possible selection of
the wrong input register.
If both CS and CLK are used, then CS should rise only when
CLK is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table III for more information.
The digital data into the DAC7715 is double-buffered. This
allows new data to be entered for each DAC without disturb-
ing the analog outputs. When the new settings have been
entered into the device, all of the DAC outputs can be
updated simultaneously. The transfer from the input regis-
ters to the DAC registers is accomplished with a HIGH to
LOW transition on the LOADDACS input.
Because the DAC registers become transparent when
LOADDACS is LOW, it is possible to keep this pin LOW
and update each DAC via LOADREG. However, as each
new data word is entered into the device, the corresponding
output will update immediately when LOADREG is taken
LOW.
Digital Input Coding
The DAC7715 input data is in Straight Binary format. The
output voltage is given by the following equation:
V V V V N
OUT REFL REFH REFL
= + ( – ) •
4096
where N is the digital input code (in decimal). This equation
does not include the effects of offset (zero-scale) or gain
(full-scale) errors.
“load all DAC registers” signal (LOADDACS). In addition,
a chip select (CS) input is available to enable serial commu-
nication when there are multiple serial devices. An asyn-
chronous reset input (RESET) is provided to simplify start-
up conditions, periodic resets, or emergency resets to a
known state.
The DAC code and address are provided via a 16-bit serial
interface as shown in Figure 4. The first two bits select the
input register that will be updated when LOADREG goes
LOW, as shown in Table II. The next two bits are not used.
The last 12 bits are the DAC code which is provided, most
significant bit first.
Note that CS and CLK are combined with an OR gate and
the output controls the serial-to-parallel shift register inter-
nal to the DAC7715 (see the block diagram on the front of
this data sheet). These two inputs are completely inter-
changeable. In addition, care must be taken with the state of
15
®
DAC7715
LAYOUT
A precision analog component requires careful layout, ad-
equate bypassing, and clean, well-regulated power supplies.
As the DAC7715 offers single-supply operation, it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switch-
ing speed, the more difficult it will be to achieve good
performance from the converter.
Because the DAC7715 has a single ground pin, all return
currents, including digital and analog return currents, must
flow through the GND pin. Ideally, GND would be con-
nected directly to an analog ground plane. This plane would
be separate from the ground connection for the digital
components until they were connected at the power entry
point of the system.
The power applied to VDD (as well as VSS, if not grounded)
should be well regulated and low noise. Switching power
supplies and DC/DC converters will often have high-fre-
quency glitches or spikes riding on the output voltage. In
addition, digital components can create similar high-fre-
quency spikes as their internal logic switches states. This
noise can easily couple into the DAC output voltage through
various paths between the power connections and analog
output.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC7715U ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7715U/1K ACTIVE SOIC DW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7715U/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7715UB ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7715UB/1K ACTIVE SOIC DW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7715UB/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7715UBG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC7715UG4 ACTIVE SOIC DW 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC7715U/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
DAC7715UB/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1