General Description
The MAX6958/MAX6959 compact multiplexed com-
mon-cathode display drivers interface microprocessors
to seven-segment numeric LED digits, or discrete LEDs
through an SMBus™- and I2C-compatible 2-wire serial
interface. The 2-wire serial interface uses fixed
0.8V/2.1V logic thresholds for compatibility with 2.5V
and 3.3V systems when the display driver is powered
from a 5V supply.
The MAX6958/MAX6959 drive up to four 7-segment
digits, with decimal points, plus four discrete LEDs, or
four 7-segment digits and eight discrete LEDs if the
digits’ decimal points are not used, or up to 36 discrete
LEDs. The MAX6959 also includes two input ports, one
or both of which may be configured as a key-switch
reader, which automatically scans and debounces a
matrix of up to eight switches. Key-switch status is
obtained by polling internal status registers or by con-
figuring the MAX6959 interrupt output.
Other on-chip features include a hexadecimal font for
seven-segment displays, multiplex scan circuitry,
anode and cathode drivers, and static RAM that stores
each digit. The peak segment current for the display
digits is set internally to 23mA. Display intensity is
adjusted using a 64-step internal digital brightness con-
trol. The MAX6958/MAX6959 include a low-power shut-
down mode, a scan-limit register that allows the user to
display from one to four digits, and a test mode, which
forces all LEDs on. The LED drivers are slew-rate-limit-
ed to reduce EMI.
The MAX6958/MAX6959 are available in 16-pin PDIP
and QSOP packages and are fully specified over the
-40°C to +125°C automotive temperature range.
Applications
Features
♦400kbps 2-Wire Serial Interface
♦3V to 5.5V Operation
♦Drive 4 Digits plus 4 or 8 Discrete LEDs
♦Drive Common-Cathode LED Digits
♦23mA Constant-Current LED Segment Drive
♦Hexadecimal Decode/No-Decode Digit Selection
♦64-Step Digital Brightness Control
♦Slew-Rate-Limited Segment Drivers Reduced EMI
♦Debounces Up to Eight Switches with n-Key
Rollover (MAX6959 Only)
♦IRQ Output When a Key Input Is Debounced
(MAX6959 Only)
♦20µA Low-Power Shutdown (Data Retained)
♦Automotive Temperature Range (-40°C to +125°C)
♦Compact 16-Pin PDIP and QSOP Packages
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2634; Rev 1; 11/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information continued at end of data sheet.
PART
TEMP
RANGE
SLAVE
ADDRESS
PIN-
PACKAGE
PKG
CODE
MAX6958AAEE
-40°C to
+125°C0111000
16 QS OP
E 16- 1
MAX6958AAPE
-40°C to
+125°C
0111000
16 DIP
P16-1
V+
DIG0–DIG3
SEG0–SEG8
SDA
SCL
IRQ/SEG9
INPUT1
µC
SDA
SCL
IRQ
8
INPUT2 GND
8 88 8
5V
Key0
DIG0/SEG0
Key1
DIG1/SEG1
Key2
DIG2/SEG2
Key3
DIG3/SEG3
Key4
DIG4/SEG4
Key5
DIG5/SEG5
Key6
DIG6/SEG6
Key7
DIG7/SEG7
MAX6959
Typical Operating Circuit
SMBus is a trademark of Intel Corp.
Set-Top Boxes
Panel Meters
White Goods
Audio/Video Equipment
Vending Machines
Industrial Controls
Pin Configuration, Functional Diagram, and Typical
Application Circuit appear at end of data sheet.
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V+ = 3V to 5.5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 5V, TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(Voltage with respect to GND.)
V+, SCL, SDA .......................................................-0.3V to +6V
All Other Pins............................................-0.3V to (V+ + 0.3V)
Current
DIG0/SEG0–DIG3/SEG3 Sink Current ..........................275mA
DIG0/SEG0–SEG9 Source Current .................................30mA
SCL, SDA, INPUT1, INPUT2 ...........................................20mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP (derate at 8.34mW/°C above +70°C).....667mW
16-Pin DIP (derate at 10.5mW/°C above +70°C).........842mW
Operating Temperature Range
MAX695_ (TMIN to TMAX)...............................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Operating Supply Voltage V+ 3 5.5 V
TA = +25°C 20 50
Shutdown Supply Current ISHDN Shutdown mode, all
digital inputs at V+
TA = TMIN to +85°C 125 µA
TA = +25°C 5.9 6.7
Operating Supply Current I+
Intensity set to full,
no display load
connected, INPUT1
and INPUT2 open
circuit
TA = TMIN to TMAX 7.5 mA
Display Scan Rate fSCAN 4 digits scanned TA = TMIN to TMAX
510 780 1050
Hz
Keyscan Debounce Time
tDEBOUNCE
TA = TMIN to TMAX
30.3
41 63 ms
TA = +25°C -19 -23 -29
VLED = 2.4V,
V+ = 4.5V to 5.5V TA = TMIN to TMAX -18 -30
TA = +25°C -16
-29.5
Segment Drive Source Current ISEG VLED = 2V,
V+ = 3V to 5.5V TA = TMIN to TMAX
-15.5 -30.5
mA
Segment Current Slew Rate
∆ISEG/∆t
11
mA/µs
∆ISEG 4%
LOGIC INPUTS AND OUTPUTS
Input Leakage Current SCL
and SDA IIH, IIL -1 +1 µA
Logic High Input Voltage SCL,
SDA VIH 2.1 V
Logic Low Input Voltage SCL,
SDA VIL 0.8 V
Input Leakage Current INPUT1,
INPUT2
IINH, IINL
INPUT_ = V+ -1 +1 µA
Logic High Input Voltage INPUT1,
INPUT2 VINH 0.7 ✕
V+ V
Logic Low Input Voltage INPUT1,
INPUT2 VINL 0.3 ✕
V+ V
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
_______________________________________________________________________________________ 3
Note 1: All parameters tested at TA=+25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 4: CB= total capacitance of one bus line in pF. tRand tFmeasured between 0.3V+ and 0.7V+.
Note 5: ISINK ≤6mA. CB= total capacitance of one bus line in pF. tRand tFmeasured between 0.3V+ and 0.7V+.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 3V to 5.5V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 5V, TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Pullup to V+ INPUT1, INPUT2
IPULLUP 26.5
µA
ISINK = 6mA, TA = -40°C to +85°C 0.4
IRQ/SEG9, SDA Output Low
Voltage VOLBK ISINK = 4mA, TA = TMIN to TMAX 0.4 V
SDA Output Low Voltage
VOL
(
SDA
)
ISINK = 6mA 0.4 V
TIMING CHARACTERISTICS
(V+ = 3V to 5.5V, TA= TMIN to TMAX, Figure 1, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency fSCL 400 kHz
Bus Free Time Between a STOP
and a START Condition tBUF 1.3 µs
Hold Time (Repeated) START
Condition
tHD
,
STA
0.6 µs
Repeated START Setup Time
tSU
,
STA
0.6 µs
STOP Condition Setup Time
tSU
,
STO
0.6 µs
Data Hold Time
tHD
,
DAT
(Note 3) 0.9 µs
Data Setup Time
tSU
,
DAT
100 ns
SCL Clock Low Period tLOW 1.3 µs
SCL Clock High Period tHIGH 0.6 µs
Rise Time of Both SDA and SCL
Signals, Receiving tR(Notes 2, 4) 20 +
0.1CB
300 ns
Fall Time of Both SDA and SCL
Signals, Receiving tF(Notes 2, 4) 20 +
0.1CB
300 ns
Fall Time of SDA Transmitting tF(Notes 2, 5) 20 +
0.1CB
250 ns
Pulse Width of Spike Suppressed
tSP (Note 6) 50 ns
Capacitive Load for Each Bus
Line CB
400
pF
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
4_______________________________________________________________________________________
Typical Operating Characteristics
(V+ = 5V, LED forward voltage = 2.4V, TA= +25°C, unless otherwise noted.)
SCAN RATE (fSCAN)
vs. TEMPERATURE
MAX6958/59 toc01
TEMPERATURE (°C)
SCAN RATE (Hz)
1008040 600 20-20
760
765
770
775
780
785
790
795
800
755
-40 120
5.5V
5V
3V
4.5V
KEYSCAN DEBOUNCE TIME (tDEBOUNCE)
vs. TEMPERATURE
MAX6958/59 toc02
TEMPERATURE (°C)
KEYSCAN DEBOUNCE TIME (ms)
100806040200-20
40.5
41.0
41.5
42.0
42.5
40.0
-40 120
4.5V
5V
3V
5.5V
SCAN RATE (fSCAN)
vs. SUPPLY VOLTAGE
MAX6958/59 toc03
SUPPLY VOLTAGE (V)
SCAN RATE (Hz)
5.04.54.03.5
765
770
775
780
785
790
760
3.0 5.5
KEYSCAN DEBOUNCE TIME (tDEBOUNCE)
vs. SUPPLY VOLTAGE
MAX6958/59 toc04
SUPPLY VOLTAGE (V)
KEYSCAN DEBOUNCE TIME (ms)
5.04.54.03.5
40.6
40.8
41.0
41.2
41.4
41.6
41.8
42.0
42.2
40.4
3.0 5.5
SEGMENT SOURCE CURRENT
vs. SUPPLY VOLTAGE
MAX6958/59 toc05
SUPPLY VOLTAGE (V)
SEGMENT SOURCE CURRENT (mA)
5.255.004.75
5
10
15
20
25
0
4.50 5.50
VLED = 2.4V
SEGMENT SOURCE CURRENT
vs. SUPPLY VOLTAGE
MAX6958/59 toc06
SUPPLY VOLTAGE (V)
SEGMENT SOURCE CURRENT (mA)
4.54.03.5
5
10
15
20
25
0
3.0 5.0 5.5
VLED = 2V
WAVEFORM AT DIG0/SEG0,
FULL INTENSITY
MAX6958/59 toc07
VDIG0/
SEG0
1V/div
200µs/div
INPUT PULLUP CURRENT
vs. TEMPERATURE
MAX6958/59 toc08
TEMPERATURE (°C)
INPUT PULLUP CURRENT (µA)
1008040 600 20-20
5
10
15
20
25
30
35
40
45
0
-40 120
5.5V
5V
3V
4.5V
Detailed Description
The MAX6958/MAX6959 serially interfaced display dri-
vers drive up to: four 7-segment digits plus four dis-
crete LEDs if the decimal points are used, or four
7-segment digits plus eight discrete LEDs if the deci-
mal points are not used, or 36 discrete LEDs. Table 1
lists the display connection scheme.
The MAX6958/MAX6959 include the hexadecimal font
map for seven-segment displays. The seven-segment
LED digits can be controlled directly or programmed to
use the hexadecimal font. Direct segment control
allows the MAX6958/MAX6959 to drive bar graphs and
discrete LED indicators.
The MAX6958/MAX6959 use a multiplexing scheme that
minimizes the connections between the driver and LED
display. The MAX6958/MAX6959 can drive monocolor
and bicolor single-digit type displays, and monocolor
dual-digit displays. Dual-digit displays internally
wire together the equivalent segments for each digit,
requiring only eight segment pins instead of 16. The
MAX6958/MAX6959 can also drive multidigit LED dis-
plays that have the segments individually pinned for
each digit.
To connect four single-digit displays to the MAX6958/
MAX6959, connect cathode outputs DIG0/SEG0–
DIG3/SEG3 to the cathodes of the four display digits as
shown in Table 1 (CC0–CC3). Drive eight additional
LEDs with SEG0 to SEG7. Four of the eight LEDs can
be the decimal point (DP) segments of the four dis-
plays, and the other four can be discrete LED indica-
tors.
To connect two dual-digit displays to the MAX6958/
MAX6959, connect cathode outputs DIG0/SEG0 and
DIG1/SEG1 to the cathodes of the first dual digit.
Connect DIG2/SEG2 and DIG3/SEG3 to the cathodes
of the second dual digit. SEG0 to SEG3 can only drive
discrete LEDs, not digit DP segments. SEG4 to SEG7
can drive the DP segments if required. Bicolor single-
digit displays are connected and treated as dual-digit
displays, each digit being one of the two colors.
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
_______________________________________________________________________________________ 5
Pin Description
PIN
MAX6958
MAX6959
NAME FUNCTION
11SDA Serial Data I/O
22SCL Serial Clock Input
3—SEG9 Segment Output. Segment driver sourcing current to a display anode.
—3IRQ/SEG9 Interrupt or Segment Output. May be segment driver sourcing current to a display
anode, or open-drain interrupt output, or open-drain logic output.
4–7, 11–15
4–7, 11–15 DIGX, SEGX
Digit and Segment Drivers. Digit X outputs sink current from the display common
cathode when acting as digit drivers. Segment X drivers source current to the display
anodes. Segment/digit drivers are high impedance when turned off.
88GND Ground
9, 10 — N.C. No Connect. Connect to V+ or leave open.
—9INPUT1 General-Purpose Input Port 1 with Internal Pullup. May be configured as general-
purpose logic input or keyscan input. Connect to V+ or leave open if unused.
—10INPUT2 General-Purpose Input Port 2 with Internal Pullup. May be configured as general-
purpose logic input or keyscan input. Connect to V+ or leave open if unused.
16 16 V+ Positive Supply Voltage
DIG0/SEG0 DIG1/SEG1 DIG2/SEG2 DIG3/SEG3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9/IRQ
LED Digit 0 CC0 SEG 0 SEG g SEG f SEG e SEG d SEG c SEG b SEG a SEG 4
LED Digit 1 SEG 1 CC1 SEG g SEG f SEG e SEG d SEG c SEG b SEG a SEG 5
LED Digit 2 SEG g SEG f CC2 SEG 2 SEG e SEG d SEG c SEG b SEG a SEG 6
LED Digit 3 SEG g SEG f SEG 3 CC3 SEG e SEG d SEG c SEG b SEG a SEG 7
Table 1. Standard Driver Connection to LED Displays
MAX6958/MAX6959
Differences Between MAX6958
and MAX6959
The MAX6958/MAX6959 have the same LED drive
capability, four common-cathode digits of nine seg-
ments per digit. The MAX6959 additionally contains two
logic input ports, INPUT1 and INPUT2. Each input port
can be individually configured as either a general-pur-
pose input port that is read through the serial interface,
or as a keyscan input. In keyscan mode, the input is
used to read and automatically debounce four key
switches. A maximum of eight key switches can be
read if both INPUT1 and INPUT2 are assigned to
keyscanning.
The MAX6958's SEG9 output is preconfigured as the
9th LED segment output. The IRQ/SEG9 output on the
MAX6959 can be configured as either an open-drain
logic output or the 9th segment output. This logic out-
put serves as either a general-purpose logic output, set
through the serial interface, or an interrupt (IRQ) output
that alerts a microcontroller of debounced key-switch
events. Key-switch status can also be obtained by
polling the internal status registers at any time.
Use the Option bit in the configuration register to detect
whether a MAX6958 or MAX6959 is present. The option
bit allows host software to establish whether a high-end
front panel (using the MAX6959 for keyscan support) or
a low-end panel (using a MAX6958 and no key switch-
es) is fitted to a product.
Serial Interface
Serial Addressing
The MAX6958/MAX6959 operate as a slave that sends
and receives data through a 2-wire interface. The inter-
face uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master, typically a microcon-
troller, initiates all data transfers to and from the
MAX6958/MAX6959, and generates the SCL clock that
synchronizes the data transfer (Figure 1).
The MAX6958/MAX6959 SDA line operates as both an
input and an open-drain output. A pullup resistor, typi-
cally 4.7kΩ, is required on the SDA bus. The MAX6958/
MAX6959 SCL line operates only as an input. A pullup
resistor, typically 4.7kΩ, is required on the SCL bus if
there are multiple masters on the 2-wire interface, or if
the master in a single-master system has an open-drain
SCL output.
Each transmission consists of a START condition
(Figure 2) sent by a master, followed by the MAX6958/
MAX6959 7-bit slave address plus R/Wbit (Figure 3), 1
or more data bytes, and finally a STOP condition
(Figure 2).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 2).
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
6_______________________________________________________________________________________
tLOW
SDA
tLOW
tSU, DAT tHD, DAT
tR
SCL
START
CONDITION
STOP
CONDITION
START
CONDITION
REPEATED START
CONDITION
tF
tHIGH
tHD, STA
tSU, STA
tHD, STA tSU, STO
tBUF
Figure 1. 2-Wire Serial Interface Timing Details
SDA
START
CONDITION
SCL
S
STOP
CONDITION
P
Figure 2. Start and Stop Conditions
Bit Transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX6958/MAX6959,
the MAX6958/MAX6959 generate the acknowledge bit
because the MAX6958/MAX6959 are the recipients.
When the MAX6958/MAX6959 are transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Slave Address
The MAX6958/MAX6959 have a 7-bit-long slave
address (Figure 3). The eighth bit following the 7-bit
slave address is the R/Wbit. Set the R/Wbit low for a
write command and high for a read command.
The MAX6958/MAX6959 are available in one of two
possible slave addresses (see Table 2 and Ordering
Information). The first 6 bits (MSBs) of the MAX6958/
MAX6959 slave address are always 011100. Slave
address bit A0 is internally hardwired to either GND in
the MAX695_A_, or V+ in the MAX695_B_. A maximum
of two MAX6958/MAX6959 devices can share a bus.
Message Format for Writing
A write to the MAX6958/MAX6959 comprises the trans-
mission of the MAX6958/MAX6959s’ slave address with
the R/Wbit set to zero, followed by at least 1 byte of
information. The first byte of information is the com-
mand byte, which determines the register that stores
the next byte written to the MAX6958/MAX6959. If a
STOP condition is detected after the command byte is
received, the MAX6958/MAX6959 take no further action
(Figure 6) beyond storing the command byte.
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
_______________________________________________________________________________________ 7
SDA
SCL
01 A0
MSB LSB
R/W ACK11 0 0
Figure 3. Slave Address
SDA
DATA STABLE,
DATA VALID
CHANGE OF
DATA ALLOWED
SCL
Figure 4. Bit Transfer
1
SCL
START
CONDITION
SDA
289
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 5. Acknowledge
MAX6958/MAX6959 DEVICE ADDRESS
SLAVE ADDRESS
BIT A0
A6 A5 A4 A3 A2 A1
A0
MAX695_A_
011100
0
MAX695_B_
011100
1
Table 2. MAX6958/MAX6959 Address Map
S A0SLAVE ADDRESS COMMAND BYTE
ACKNOWLEDGE FROM
MAX6958/MAX6959
R/W ACKNOWLEDGE FROM
MAX6958/MAX6959
D15 D14 D13 D12 D11 D10 D9 D8
COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION
AP
Figure 6. Command Byte Received
MAX6958/MAX6959
Bytes received after the command byte are data bytes.
The first data byte goes into the internal register of the
MAX6958/MAX6959 as selected by the command byte
(Figure 7).
The address pointer in the MAX6958/MAX6959 autoin-
crements after each data byte. If multiple data bytes
are transmitted before a STOP condition is detected,
these bytes are stored in subsequent MAX6958/
MAX6959 internal registers (Figure 8), unless the
address pointer has reached address 01111111. The
address pointer does not autoincrement once address
01111111 has been reached (Table 3).
Message Format for Reading
The MAX6958/MAX6959 are read using the internally
stored command byte as an address pointer the same
way the stored command byte is used as an address
pointer for a write. The pointer autoincrements after
each data byte read using the same rules as for a write
(Table 3). A read is initiated by first configuring the
MAX6958/MAX6959s’ command byte with a write com-
mand (Figure 6). The master can now read n consecu-
tive bytes from the MAX6958/MAX6959. The master
acknowledges receipt of each read byte during the
acknowledge clock pulse. The master must acknowl-
edge all consecutive bytes received except the last
byte. The final read byte must be followed by a not
acknowledge from the master and then a stop condi-
tion (Figure 9). The first data byte is read from the reg-
ister addressed by the initialized command byte
(Figure 8). Reset the address pointer when performing
read-after-write verification because the stored byte
address is autoincremented after the write. The
address pointer does not autoincrement if it points to
register 01111111 (Table 3).
Table 4 is the register address map.
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
8_______________________________________________________________________________________
A
0SLAVE ADDRESS COMMAND BYTE DATA BYTE
ACKNOWLEDGE FROM
MAX6958/MAX6959
R/W 1 BYTE
AUTOINCREMENT MEMORY WORD ADDRESS
ACKNOWLEDGE FROM MAX6958/MAX6959 ACKNOWLEDGE FROM MAX6958/MAX6959
D15 D14 D13 D12 D11 D10 D9 D8 D1 D0D3 D2D5 D4D7 D6
HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX6958/MAX6959s' REGISTERS
S AA P
Figure 7. Command and Single Data Byte Received
A
0SLAVE ADDRESS COMMAND BYTE DATA BYTE
ACKNOWLEDGE FROM
MAX6958/MAX6959
R/W n BYTES
AUTOINCREMENT MEMORY WORD ADDRESS
ACKNOWLEDGE FROM MAX6958/MAX6959 ACKNOWLEDGE FROM MAX6958/MAX6959
D15 D14 D13 D12 D11 D10 D9 D8 D1 D0D3 D2D5 D4D7 D6
HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX6958/MAX6959s' REGISTERS
S AA P
Figure 8. n Data Bytes Received
1SLAVE ADDRESS FIRST DATA BYTE DATA BYTE
ACKNOWLEDGE FROM MAX6958/MAX6959
R/W n BYTES
AUTOINCREMENT MEMORY WORD ADDRESS
ACKNOWLEDGE FROM THE MASTER NOT ACKNOWLEDGE FROM MASTER
D15 D14 D13 D12 D11 D10 D9 D8 D1 D0D3 D2D5 D4D7 D6
HOW THE MAX6958/MAX6959 SENDS DATA
TO THE MASTER
S AA P
AUTOINCREMENT MEMORY WORD ADDRESS
A
Figure 9. Reading n Data Bytes from the MAX6958/MAX6959
Operation with Multiple Masters
If the MAX6958/MAX6959 are operated on a 2-wire
interface with multiple masters, a master reading the
MAX6958/MAX6959 should use a repeated start
between the write, which sets the MAX6958/MAX6959s’
address pointer, and the read(s) that takes the data
from the location(s) set by the address pointer. It is
possible for master 2 to take over the bus after master
1 has set up the MAX6958/MAX6959s’ address pointer
but before master 1 has read the data. If master 2 sub-
sequently changes the MAX6958/MAX6959s’ address
pointer, then master 1's delayed read may be from an
unexpected location.
Command Address Autoincrementing
Address autoincrementing allows the MAX6958/
MAX6959 to be configured with the shortest number of
transmissions by minimizing the number of times the
command byte needs to be sent. The address pointer
stored in the MAX6958/MAX6959 increments after each
data byte is written or read, unless the address equals
01111111 (Table 3).
Digit Type Registers
The MAX6958/MAX6959 store display data in five regis-
ters. The four digit registers each control the seven
numeric segments of a seven-segment digit, but not
the DP segments. The segments register controls eight
individual LEDs, which can be any mix of discrete LEDs
and any or all of the DP segments of the four 7-seg-
ment digits (Table 5) (Figure 10).
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
_______________________________________________________________________________________ 9
COMMAND BYTE
ADDRESS RANGE
AUTOINCREMENT BEHAVIOR
00000000 to
01111110
Command byte address autoincrements
after byte read or written
01111111 Command byte address remains at
01111111 after byte written or read
Table 3. Command Address
Autoincrement Behavior
COMMAND ADDRESS
REGISTER
D15 D14 D13 D12 D11 D10 D9 D8
HEX
CODE
No-op 0 0 0 0 0 0 0 0 0x00
Decode mode 0 0 0 0 0 0 0 1 0x01
Intensity 0 0 0 0 0 0 1 0 0x02
Scan limit 0 0 0 0 0 0 1 1 0x03
Configuration 0 0 0 0 0 1 0 0 0x04
Factory reserved. Do not write to this register. 0 0 0 0 0 1 0 1 0x05
GPIO (MAX6959 only) 0 0 0 0 0 1 1 0 0x06
Display test 0 0 0 0 0 1 1 1 0x07
Read key debounced (MAX6959 only)
A write to this register is ignored. 000010000x08
Read key pressed (MAX6959 only)
A write to this register is ignored. 000011000x0C
Digit 0 0 0 1 0 0 0 0 0 0x20
Digit 1 0 0 1 0 0 0 0 1 0x21
Digit 2 0 0 1 0 0 0 1 0 0x22
Digit 3 0 0 1 0 0 0 1 1 0x23
Segments 0 0 1 0 0 1 0 0 0x24
Table 4. Register Address Map
a
b
c
d
e
f
g
dp
Figure 10. Segment Labeling for 7-Segment Display
MAX6958/MAX6959
The digit registers and segments register use 1 bit to
set the state of one segment. Each bit is high to turn a
segment on, or low to turn it off (Table 6).
Decode-Mode Register
The decode-mode register sets hexadecimal code
(0–9, A–F) or no-decode operation for each digit. Each
bit in the register corresponds to one digit. Logic high
selects hexadecimal decoding while logic low bypass-
es the decoder. Digits can be set for decode or no
decode in any combination. Bit assignment and exam-
ples of the decode mode control register format are
shown in Table 7.
In hexadecimal code-decode mode, the decoder looks
only at the lower nibble of the data in the digit register
(D3–D0), disregarding bits D7–D4. Table 7 lists the hexa-
decimal code font. When no decode is selected, data
bits D7–D0 correspond to the segment lines of the
MAX6958/MAX6959. Table 8 shows the one-to-one pair-
ing of each data bit to the appropriate segment line.
Initial Power-Up
On initial power-up, all control registers are reset, the
display is blanked, and the MAX6958/MAX6959 enter
shutdown mode (Table 9). At power-up, the MAX6958/
MAX6959 are initially set to scan four digits, do not
decode data in the digit registers or scan key switches
(MAX6959 only), and the intensity register is set to a
low value (4/64 intensity).
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
10 ______________________________________________________________________________________
REGISTER DATA
DIGIT/SEGMENT REGISTER
ADDRESS
CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0
Digit 0 0x20 X
SEG a SEG b SEG c SEG d SEG e SEG f
SEG g
Digit 1 0x21 X
SEG a SEG b SEG c SEG d SEG e SEG f
SEG g
Digit 2 0x22 X
SEG a SEG b SEG c SEG d SEG e SEG f
SEG g
Digit 3 0x23 X
SEG a SEG b SEG c SEG d SEG e SEG f
SEG g
Segments 0x24
SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1
SEG 0
Table 5. No-Decode Mode Data Bits and Corresponding Segment Lines
REGISTER BIT SEGMENT BEHAVIOR
0Segment off
1Segment on
Table 6. No-Decode Mode Data Bits and
Corresponding Segment Lines
REGISTER DATA
DECODE MODE ADDRESS
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1 D0
HEX
CODE
Bit assignment for each digit
0x01 XXXX
Digit 3 Digit 2 Digit 1 Digit 0
—
No decode for digits 3–0 0x01 XXXX0000
0xX0
Hexadecimal decode for digit
0; no decode for digits 3–1 0x01 XXXX0001
0xX1
———————————
Hexadecimal decode for digits
2–0; no decode for digit 3 0x01 XXXX0111
0xX7
Hexadecimal decode for digit
3; no decode for digits 2–0 0x01 XXXX1000
0xX8
———————————
Hexadecimal decode for digits
3–0 0x01 XXXX1111
0xXF
Table 7. Decode-Mode Register Examples
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
______________________________________________________________________________________ 11
REGISTER DATA ON SEGMENTS = 1
7-SEGMENT
CHARACTER
D7–D4
D3 D2 D1 D0 a b c d e f g
0X00001111110
1X00010110000
2X00101101101
3X00111111001
4X01000110011
5X01011011011
6X01101011111
7X01111110000
8X10001111111
9X10011111011
AX10101110111
BX10110011111
CX11001001110
DX11010111101
EX11101001111
FX11111000111
Table 8. Seven-Segment Mapping Decoder for Hexadecimal Font
REGISTER DATA
REGISTER POWER-UP CONDITION ADDRESS
CODE (HEX) D7 D6 D5 D4 D3 D2 D1
D0
Decode mode No decode for digits 3–0 0x01 X X X X 0000
Intensity 4/64 intensity 0x02 X X 0 00100
Scan limit Display 4 digits: 0 1 2 3 0x03 X X X X X X 1 1
Configuration Shutdown enabled 0x04 X X 0 X X X
D bit
0
GPIO*
IRQ/SEG9 is a segment output
(not IRQ or logic output);
INPUT2 and INPUT1 are logic
inputs; IRQ flag is clear
0x06 1 0 0 0 0 X X 0
Display test Normal operation 0x07 X X X XXXX0
Key debounced*
No key detected as debounced 0x08 0 0 0 00000
Key pressed* No key detected as pressed 0x0C 0 0 0 00000
Digit 0 Blank digit (because not decoded) 0x20 X 0 0 00000
Digit 1 Blank digit (because not decoded) 0x21 X 0 0 00000
Digit 2 Blank digit (because not decoded) 0x22 X 0 0 00000
Digit 3 Blank digit (because not decoded) 0x23 X 0 0 00000
Segments Blank segments 0x24 0 0 0 00000
Table 9. Initial Power-Up Register Status
*MAX6959 only.
MAX6958/MAX6959
Configuration Register
Use the configuration register to enter and exit shut-
down, check device type, and globally clear the digit
data (Tables 10–13). The S bit selects shutdown or nor-
mal operation (read/write). The D bit reports whether
the device is a MAX6958 or a MAX6959 (read only).
The R bit clears all the digit and segment data (data is
not stored-transient bit)
Scan-Limit Register
The scan-limit register sets the number of digits dis-
played, from one to four (Table 14). A bicolor digit is
connected as two monocolor digits. The scan-limit reg-
ister also limits the number of keys that can be
scanned. Since the number of scanned digits affects
the display brightness, the scan-limit register should
not be used to blank portions of the display (such as
leading zero suppression).
Intensity Register
An internal pulse-width modulator controlled by the
intensity register provides digital control of display
brightness. The modulator scales the average segment
current in 63 steps from a maximum of 63/64 down to
1/64 of the 23mA peak current. The minimum interdigit
blanking time is set to 1/64 of a cycle (Figure 11 and
Table 15).
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
12 ______________________________________________________________________________________
REGISTER DATA
MODE ADDRESS
CODE (HEX) D7 D6 D5 D4 D3 D2 D1
D0
Configuration register 0x04 X X R X X X D S
Table 10. Configuration Register Format
REGISTER DATA
MODE ADDRESS
CODE (HEX) D7 D6 D5 D4 D3 D2 D1
D0
Shutdown mode 0x04 X X R X X X D 0
Normal operation 0x04 X X R X X X D 1
Table 11. Shutdown Control (S Data Bit D0) Format
REGISTER DATA
MODE ADDRESS
CODE (HEX) D7 D6 D5 D4 D3 D2 D1
D0
MAX6958 0x04 X X R X X X 0 S
MAX6959 0x04 X X R X X X 1 S
Table 12. Device Readback (D Data Bit D1) Format
REGISTER DATA
MODE ADDRESS
CODE (HEX) D7 D6 D5 D4 D3 D2 D1
D0
Digit and segment data are unaffected 0x04 X X 0 X X X D S
Digit and segment data are cleared 0x04 X X 1 X X X D S
Table 13. Global Clear Digit Data (R Data Bit D5) Format
REGISTER DATA
SCAN LIMIT ADDRESS
CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0
HEX
CODE
Display digit 0 and segments 0, 4 0x03
XXXXXX00
0xX0
Display digits 0, 1 and segments 0, 1, 4, 5 0x03
XXXXXX01
0xX1
Display digits 0, 1, 2 and segments 0, 1, 2, 4, 5, 6
0x03
XXXXXX10
0xX2
Display digits 0, 1, 2, 3 and segments 0, 1, 2, 3, 4,
5, 6, 7 0x03
XXXXXX11
0xX3
Table 14. Scan-Limit Register Format
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
______________________________________________________________________________________ 13
DUTY CYCLE
TYPICAL SEGMENT
CURRENT (mA)
ADDRESS
CODE (HEX)
D7
D6
D5
D4
D3
D2
D1
D0
HEX CODE
1/64 (min on) 0.36 0x02
XX
0
0
00
0
00x00
2/64 0.72 0x02
XX
0
0
00
0
10x01
3/64 1.08 0x02
XX
0
0
00
1
00x02
4/64 1.44 0x02
XX
0
0
00
1
10x03
5/64 1.80 0x02
XX
0
0
01
0
00x04
6/64 2.16 0x02
XX
0
0
01
0
10x05
——0x02
XX——————
—
60/64 21.56 0x02
XX
1
1
10
1
10x3B
61/64 21.92 0x02
XX
1
1
11
0
00x3C
62/64 22.28 0x02
XX
1
1
11
0
10x3D
63/64 22.64 0x02
XX
1
1
11
1
00x3E
63/64 (max on)
22.64 0x02
XX
1
1
11
1
10x3F
Table 15. Global Intensity Register Format
1/64th
(MIN ON)
2/64th
3/64th
63/64th
61/64th
62/16th
63/64th
DIGIT 0 CATHODE
DRIVER INTENSITY
SETTINGS HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
LOW
LOW
LOW
LOW
LOW
LOW
LOW
MINIMUM 5µs INTERDIGIT BLANKING INTERVAL
(MAX ON)
ANODE (LIT) CURRENT SOURCE ENABLED
HIGH-Z
ANODE (UNLIT)
HIGH-Z
HIGH-Z
HIGH-Z
DIGIT 1 DIGIT 2 DIGIT 3DIGIT 0 DIGIT 0
START OF
NEXT CYCLE
ONE COMPLETE 1.28ms MULTIPLEX CYCLE AROUND 4 DIGITS
DIGIT 0's 320µs MULTIPLEX TIMESLOT
Figure 11. Multiplex Timing Diagram
MAX6958/MAX6959
Ports and Key Scanning
(MAX6959 Only)
The MAX6959 features two input ports, INPUT1 and
INPUT2. These two ports can be used as general-pur-
pose logic inputs, or configured to perform automatic
keyscanning. Both ports have internal pullup resistors
enabled in shutdown and normal operation for both
general-purpose input mode and keyscanning mode.
The ports can be read using the 2-wire interface.
The keyscan logic uses one or both of the INPUT1 and
INPUT2 logic inputs (Figure 12). An interrupt output that
flags key presses is optional. The interrupt flag can be
read (polled) through the serial interface instead, allow-
ing IRQ/SEG9 to be used as an open-drain general-
purpose logic output or as a segment driver.
One small-signal diode is required per key switch when
more than one key is connected to INPUT1 or INPUT2.
The diodes prevent two simultaneous key switch
depressions from shorting digit drivers together. For
example, if KEY0 and KEY1 were pressed together
(Figure 12) and the diodes were not fitted, DIG0/SEG0
and DIG1/SEG1 would be shorted together and the
LED multiplexing would be incorrect. These diodes can
be common-anode dual diodes in SOT23 like BAW56.
A diode is not required for a single key connection to
INPUT1 or INPUT2. Therefore, up to two key switches
can be directly connected without adding diodes
(Figure 13).
Resistors R1 and R2 are required if the MAX6959 is
operated with V+ greater than 4V. R1 and R2 are
optional if V+ is between 3V and 4V.
The keyscanning circuit utilizes the LED’s common-
cathode driver outputs as the keyscan drivers. The out-
puts DIG0/SEG0 to DIG3/SEG3 pulse low for nominally
320µs sequentially as the displays are multiplexed. The
actual low time varies from 5µs to 315µs due to pulse-
width modulation from 1/64th to 63/64th for intensity
control. The timing diagram (Figure 14) shows the typi-
cal situation when all four LED cathode drivers are used.
The maximum eight keys can be scanned only if the
scan-limit register is set to scan the maximum four dig-
its. If fewer than four digits are driven, then only (2 x n)
switches can be scanned, where n is the number of dig-
its (1, 2, 3, or 4) set in the scan-limit register (Table 14).
The keyscan cycle loops continuously over time, with
all eight keys experiencing a full keyscanning
debounce over 41ms (Figure 14). A key press is
debounced and an interrupt issued if at least one key
that was not pressed in a previous cycle is found
pressed during both sampling periods. The keyscan
circuit detects any combination of keys pressed during
each debounce cycle (n-key rollover).
Port Configuration Register
(MAX6959 Only)
The port configuration register configures INPUT1,
INPUT2, and IRQ/SEG9 ports for the MAX6959 (Table 16).
IRQ/SEG9 can be set to either an LED segment output
(driving four multiplexed LED segments), or an open-
drain logic output. The open-drain logic output can be
configured as either an IRQ output controlled by the
keyscan circuitry, or as a general-purpose logic output
controlled through the 2-wire interface. Connect a
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
14 ______________________________________________________________________________________
Key0
Key1
Key2
Key3
Key5
Key6
Key7
DIG0/SEG0
INPUT1
INPUT2
V+
V+
IRQ/SEG9
DIG1/SEG1
DIG2/SEG2
DIG3/SEG3
MICROCONTROLLER INTERRUPT
Key4
R2
39kΩ
R1
39kΩ
4.7kΩ
Figure 12. Maximum Keyscan Configuration
Key4
INPUT1
INPUT2
V+
V+
IRQ/SEG9
DIG0/SEG0
MICROCONTROLLER INTERRUPT
Key0
R2
39kΩ
R1
39kΩ
4.7kΩ
Figure 13. Keyscanning Two Keys Without Diodes
pullup resistor from IRQ/SEG9 to a voltage no greater
than 5.5V when configuring IRQ/SEG9 as an interrupt
or logic output.
INPUT1 and INPUT2 can be individually configured as
either general-purpose logic inputs or as keyscan
inputs. In either mode, the input structure is the same—
CMOS logic inputs with internal pullup resistors. The
pullups are always enabled, even in shutdown. Ensure
these inputs are either close to V+ or open circuit for
minimum shutdown supply current. If both INPUT1 and
INPUT2 are assigned to keyscan, then eight keys can
be debounced. If only INPUT1 or INPUT2 is assigned
to keyscan, then only four keys can be debounced.
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
______________________________________________________________________________________ 15
DIG1/SEG1
DIG2/SEG2
DIG3/SEG3
DIG0/SEG0
THE FIRST HALF OF A 41ms KEYSCAN CYCLE THE SECOND HALF OF A 41ms KEYSCAN CYCLE
A B
START OF NEXT KEYSCAN CYCLE
INTERRUPT ASSERTED IF REQUIRED
KEY DEBOUNCED REGISTER UPDATED
1.28ms MULTIPLEX
CYCLE 1
INPUT2
INPUT1 Key0
FIRST TEST OF KEYS SECOND TEST OF KEYS
tDEBOUNCE
Key1 Key2 Key3
Key4 Key5 Key6 Key7
Key0 Key1 Key2 Key3
Key4 Key5 Key6 Key7
C D E
A
1.28ms MULTIPLEX
CYCLE 2
1.28ms MULTIPLEX
CYCLE 3
1.28ms MULTIPLEX
CYCLE 4
1.28ms MULTIPLEX
CYCLE 15
1.28ms MULTIPLEX
CYCLE 16
1.28ms MULTIPLEX
CYCLE 1
1.28ms MULTIPLEX
CYCLE 2
1.28ms MULTIPLEX
CYCLE 15
1.28ms MULTIPLEX
CYCLE 16
5µs TO 315µs DIGIT PERIOD
Figure 14. Keyscan Timing Diagram
REGISTER DATA
MODE
ADDRESS
CODE
(HEX)
D7 D6 D5
D4 D3 D2 D1 D0
This is the bit assignment:
Read GPIO register 0x06
Read back
IRQ/SEG9
configuration
Read back
INPUT 2
configuration
Read back
INPUT 1
configuration
INPUT2
logic level
INPUT1
logic level
IRQ status
( 1 = i nter rup t)
Write GPIO register 0x06
Configure
IRQ/SEG9
output
Configure
INPUT 2:
0 = logic input
1 = keyscan
Configure
INPUT 1:
0 = logic input
1 = keyscan
XXX
Here are the IRQ/SEG9 allocation options, determined by the settings of D7, D6, D5:
IRQ/SEG9 is logic 0 output
0x06
000
XXXXX
IRQ/SEG9 is logic 1 output
0x06
001
XXXXX
IRQ/SEG9 is active-low
IRQ 0x06
010
XXXXX
IRQ/SEG9 is active-high
IRQ 0x06
011
XXXXX
IRQ/SEG9 is segment
driver 0x06
1XX
XXXXX
Table 16. Port Configuration Register Format
MAX6958/MAX6959
Key Debounced Register (MAX6959 Only)
The key debounced register shows which keys have
been detected as debounced by the keyscanning cir-
cuit (Table 17). Each bit in the register corresponds to
one key switch. The bit is set to 1 if the switch has been
correctly debounced since the last key debounced reg-
ister read operation.
Reading the key debounced register clears the register
(after the data has been read) so that future key presses
can be identified. If the key debounced register is not
read, the keyscan data accumulates. There is no FIFO
register in the MAX6959. Key-press order, or whether a
key has been pressed more than once, cannot be
determined unless the key debounced register is read
after each interrupt and before completion of the next
keyscan cycle.
Reading the key debounced register clears the IRQ
output. If a key is pressed and held down, the key is
reported as debounced (and an IRQ is issued) only
once. The key must be detected as released by the
keyscanning circuit before it is debounced again.
The key debounced register is read only. A write to
address 0x08 is ignored.
Key Pressed Register (MAX6959 Only)
The key pressed register shows which keys have been
detected as pressed by the keyscanning circuit during
the last test. Each bit in the register corresponds to one
key switch. The bit is set if the switch has been detect-
ed as pressed by the keyscanning circuit during the
last test. The bit is cleared if the switch has not been
detected as pressed by the keyscanning circuit during
the last test. Reading the key pressed register does not
clear either the key pressed register, or the key
debounced register, and does not clear the IRQ output.
The key pressed register is read only. A write to
address 0x0C is ignored.
Display Test Register
The display test register operates in two modes: normal
and display test (Table 19). Display test mode turns on
all LEDs by overriding, but not altering, all control and
digit registers (including the shutdown register) except
for the port configuration register. The duty cycle while
in display test mode is 28/64.
Applications Information
Driving Bicolor LEDs
Bicolor digits combine a red and a green die for each
display element, so that the element displays red or
green (or orange), depending on which die (or both) is
lit. The MAX6958/MAX6959 treat a bicolor digit as two
monocolor digits.
Low-Voltage Operation
The MAX6958/MAX6959 are guaranteed to drive a 23mA
segment current into 2.4V (or lower) LEDs when operat-
ed from a supply voltage of 4.5V to 5.5V. Operating the
MAX6958/MAX6959 from a supply voltage lower than
4.5V reduces the LED drive current. The drivers drive at
least 15.5mA segment current into 2V (or lower) LEDs
when operated from a 3V supply voltage.
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
16 ______________________________________________________________________________________
REGISTER DATA
WITH APPROPRIATE SWITCH NAMED BELOW
KEY DEBOUNCED REGISTER ADDRESS
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1
D0
Key debounced register 0x08
Key7 Key6 Key5 Key4 Key3 Key2 Key1
Key0
Table 17. Key Debounced Register Format
REGISTER DATA
WITH APPROPRIATE SWITCH NAMED BELOW
KEY PRESSED REGISTER ADDRESS
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1 D0
Key pressed register 0x0C
Key7 Key6 Key5 Key4 Key3 Key2 Key1 Key0
Table 18. Key Pressed Register Format
REGISTER DATA
MODE ADDRESS
CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0
Normal operation 0x07 XXXXXXX0
Display test mode 0x07 XXXXXXX1
Table 19. Display Test Register
Computing Power Dissipation
Determine the MAX6958/MAX6959 upper-limit power
dissipation (PD) with the following equation:
PD= (V+ ✕I+) + (V+ - VLED) (DUTY ✕ISEG ✕N)
where:
V+ = supply voltage
I+ = operating supply current
DUTY = duty cycle set by intensity register
N = number of segments driven (worst case is nine)
VLED = LED forward voltage at ISEG
ISEG = peak segment current
PD= power dissipation, in mW if currents are in mA
Dissipation example:
ISEG = 23mA, N = 9, DUTY = 63/64, VLED = 2.2V,
V+ = 5.25V
PD= 5.25V (5.9mA) + (5.25V - 2.2V)
(63/64 ✕23mA ✕9) = 0.652W
For a 16-pin DIP package (TJA = 1/0.0105 = +95.2°C/W
from Absolute Maximum Ratings), the maximum
allowed ambient temperature TAis given by:
TJ(MAX) = TA+ (PD✕TJA) = +150°C
= TA+ (0.652 ✕95.2°C/W)
Therefore, TA= +87.9°C.
Power Supplies
The MAX6958/MAX6959 operate from a single 3V to
5.5V power supply. Bypass V+ with a 0.1µF capacitor
to GND, as close to the device as possible. Bypass V+
with an additional 10µF capacitor if the MAX6958/
MAX6959 are not close to the board input’s bulk
decoupling capacitor.
Chip Information
TRANSISTOR COUNT: 17,340
PROCESS: CMOS
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
______________________________________________________________________________________ 17
Ordering Information (continued)
PART
TEMP
RANGE
SLAVE
ADDRESS
PIN-
PACKAGE
PKG
CODE
MAX6958BAEE
-40°C to
+125°C0111001
16 QSOP
E 16- 1
MAX6958BAPE
-40°C to
+125°C0111001
16 DIP
P16-1
MAX6959AAEE
-40°C to
+125°C0111000
16 QSOP
E 16- 1
MAX6959AAPE
-40°C to
+125°C0111000
16 DIP
P16-1
MAX6959BAEE
-40°C to
+125°C0111001
16 QSOP
E 16- 1
MAX6959BAPE
-40°C to
+125°C0111001
16 DIP
P16-1
CONFIGURATION
REGISTERS
DISPLAY RAM
AND HEX ROM
SCL
SDA 2-WIRE SERIAL INTERFACE
MULTIPLEX
LOGIC
4 LED DIGITS
KEYSCAN AND
LED
DRIVER
CURRENT
REFERENCE
MULTIPLEX
OSCILLATOR
PWM INTENSITY
CONTROL
PORT CONTROL
PORTS AND
KEYSCAN
IRQ
Functional Diagram
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
18 ______________________________________________________________________________________
V+
DIG0–DIG3
SEG0–SEG9
SDA
SCL
INPUT1
µC
SDA
SCL
9
INPUT2
GND
9 99 9
5V
Key0
DIG0/SEG0
Key1
DIG1/SEG1
Key2
DIG2/SEG2
Key3
DIG3/SEG3
Key4
DIG0/SEG0
Key5
DIG1/SEG1
Key6
DIG2/SEG2
Key7
DIG3/SEG3
MAX6959 0.1µF
39kΩ39kΩ
Typical Application Circuit
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
SDA V+
SEG8
SEG7
SEG6
SEG5
SEG4
(INPUT2)/N.C.
(INPUT1)/N.C.
TOP VIEW
MAX6958/
MAX6959
QSOP/DIP
SCL
(IRQ/SEG9) SEG9
DIG2/SEG2
DIG0/SEG0
DIG1/SEG1
DIG3/SEG3
GND
( ) MAX6959 ONLY
Pin Configuration
MAX6958/MAX6959
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QSOP.EPS
E
1
1
21-0055
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH