D000103103 - Zippy - Product.Network

VMDS-10210

Revision 4.1

September 2009

VSC8601

10/100/1000BASE-T PHY with RGMII

MAC Interface

Datasheet

Revision 4.1

September 2009 Page 2

Vitesse

Corporate Headquarters

741 Calle Plano

Camarillo , California 93012

United States

www.vitesse.com

Vitesse Semiconductor Corporation (“Vitesse”) retains the right to make changes to its

products or specifications to improve performance, reliability or manufacturability. All

information in this document, including descriptions of features, functions,

performance, technical specifications and availability, is subject to change without

notice at any time. While the information furnished herein is held to be accurate and

reliable, no responsibility will be assumed by Vitesse for its use. Furthermore, the

information contained herein does not convey to the purchaser of microelectronic

devices any license under the patent right of any manufacturer.

Vitesse products are not intended for use in products or applications, including, but not

limited to, medical devices (including life support and implantable medical devices),

nuclear products, or other safety-critical uses where failure of a Vitesse product could

reasonably be expected to result in personal injury or death. Anyone using a Vitesse

product in such an application without express written consent of an officer of Vitesse

does so at their own risk, and agrees to fully indemnify Vitesse for any damages that

may result from such use or sale.

Safety of Laser Products, IEC 60825. While Vitesse products support IEC 60825, use of

Vitesse products does not ensure compliance to IEC 60825. Buyers are responsible for

ensuring compliance to IEC 60825. Buyers must fully indemnify Vitesse for any

damages resulting from non-compliance to IEC 60825.

Vitesse Semiconductor Corporation is a registered trademark. All other products or

service names used in this publication are for identification purposes only, and may be

trademarks or registered trademarks of their respective companies. All other

trademarks or registered trademarks mentioned herein are the property of their

respective holders.

VSC8601 Datasheet

Contents

Revision 4.1

September 2009 Page 3

Contents

Revision History ..........................................................................................9

1 Introduction.....................................................................................13

2 Product Overview.............................................................................14

2.1 Features ...........................................................................................................14

2.2 Applications.......................................................................................................15

2.3 Block Diagram ...................................................................................................16

3 Functional Descriptions....................................................................17

3.1 Interface and Media............................................................................................17

3.2 MAC Interface....................................................................................................17

3.2.1 MAC Resistor Calibration..........................................................................17

3.2.2 RGMII MAC Interface Mode ......................................................................17

3.3 Cat5 Media Interface .......... .. .. ................................ .. .. .. ..................... ... .. .. ..........18

3.4 Cat5 Auto-Negotiation .. .. .. .. ....................................................... .........................19

3.5 Manual MDI/MDI-X Setting ..................................................................................20

3.6 Automatic Crossover and Polarity Detection ...........................................................20

3.7 Link Speed Downshift .........................................................................................21

3.8 Tra nsf o rme rless Ethe rne t................ ....................................................... ..............21

3.9 Ethernet Inline Pow ere d Dev ices ............... ........... .. .. ..................... .. .. ...................21

3.10 ActiPHY Power Management.................................................................................23

3.10.1 Low-Power State ............... .......... .. .. ... ..................... .. .. .. ..................... .. ..24

3.10.2 Link Partner Wake-Up State .....................................................................25

3.10.3 Normal Oper ating State.......... .. .. .. .. .. ... ............ ............. ............. ............ ..25

3.11 Serial Management Interface ............ ...................................................................25

3.11.1 SMI Fr ame s .................. .......... .. ........... .. .......... .. ... .......... .. ........... .. ........25

3.11.2 SMI Interrupts ......... ........... .. .. ........... .. .. .......... .. ... .......... .. .. ........... .. .. .. ..27

3.12 LED Interface ....................................................................................................28

3.12.1 Simple or Enhanced LED Method...............................................................28

3.12.2 LED Modes.............................................................................................28

3.12.3 LED Behavior .........................................................................................30

3.13 Testing Features................. .. .. ........... .. .. ..................... .. .. ........... .. .. ........... .. .. ......30

3.13.1 Ethernet Packet Genera tor (EPG)............ ....................... ....................... ....30

3.13.2 CRC Counters.........................................................................................31

3.13.3 Far-end Loopback.......................... .. ... .. .......... .. .. ...................... .. .. ..........31

3.13.4 Near- E n d Loop b a ck.......... .......... .. .. ........... .. .. ........... .. .......... .. ... .......... .. ..32

3.13.5 Connector Loopback................................................................................32

3.13.6 VeriPHY Cable Diagnostics ........................................................................33

3.13.7 I EEE 1149.1 JTAG Boundary Scan. .. ....................... .................... .. ............. 33

3.13.8 JTAG Instruction Codes............................................................................34

3.13.9 Boundary-Scan Register Cell Order............................................................36

4 Configuration ...................................................................................37

4.1 Registers...........................................................................................................37

4.1.1 Reserved Registers .................................................................................38

4.1.2 Reserved Bits.........................................................................................38

4.2 IEEE Standard and Main Registers ............. .. .. ................................ .. .. .. .................38

4.2.1 Mode Control ................................ .. ... .......... .. .. ........... .. .. ........... .. .. ........39

4.2.2 Mode Status........................ .. .. ........... .. .. .. .......... ... .. .......... .. .. ........... .. .. ..40

VSC8601 Datasheet

Contents

Revision 4.1

September 2009 Page 4

4.2.3 Device Identification ............ ............................... ... .. .. ..................... .. .. .. ..41

4.2.4 Auto-Negotiation Advertisement ...............................................................41

4.2.5 Link Partner Auto-Negotiation Capability....................................................42

4.2.6 Auto-Negotiation Expansion .....................................................................43

4.2.7 Transmit Auto-Negotiation Next Page.........................................................43

4.2.8 Auto-Negotiation Link Partner Next Page Receive ........................................44

4.2.9 1000BASE-T Control................................................................................44

4.2.10 1000BASE-T Status.................................................................................45

4.2.11 Main Registers Reserved Addresses...........................................................45

4.2.12 1000BASE-T Status Extension 1................................................................45

4.2.13 100BASE-TX Status Extension ..................................................................46

4.2.14 1000BASE-T Status Extension 2................................................................46

4.2.15 Bypass Control.............. .. .. ..................... .. .. .. ........... .. .. ..................... .. .. ..47

4.2.16 Receive Error Counter ................ .. .. ..................... ... .. .. ..................... .. .. .. ..48

4.2.17 False Carrier Sense Counter.....................................................................48

4.2.18 Disconnect Counter.................................................................................49

4.2.19 Extended Control and Status....................................................................49

4.2.20 Extended PHY Control Set 1 .....................................................................50

4.2.21 Extended PHY Control Set 2 .....................................................................50

4.2.22 Interrupt Mask .......................................................................................51

4.2.23 Interrupt Status .....................................................................................52

4.2.24 LED Control ...........................................................................................52

4.2.25 Auxiliary Control and Status.....................................................................53

4.2.26 Delay Skew Status..................................................................................54

4.2.27 Reserved Address Space..........................................................................54

4.3 Extended Page Registers.....................................................................................55

4.3.1 Extended Page Access.............................................................................56

4.3.2 Enhanced LED Method Select ...................................................................56

4.3.3 Enhanced LED Behavior............ .. .. ........... .. .. .. ........... .. .. ..................... .. .. ..57

4.3.4 CRC Good Counter..................................................................................58

4.3.5 MAC Resistor Calibration Control...............................................................58

4.3.6 Extended PHY Control 3...........................................................................59

4.3.7 EEPROM Interface Status and Control........................................................59

4.3.8 EEPROM Data Read/Write ........................................................................60

4.3.9 Extended PHY Control 4...........................................................................60

4.3.10 Reserved Extended Registers ...................................................................61

4.3.11 Extended PHY Control 5...........................................................................61

4.3.12 RGMII Skew Control................................................................................62

4.3.13 Ethernet Packet Generator (EPG) Control 1 ................................................63

4.3.14 Ethernet Packet Generator Co ntrol 2 ............................ ............ ............. ....64

4.4 CMODE.............................................................................................................64

4.4.1 CMODE Pins and R e lated Fun ctions ...........................................................64

4.4.2 Functions and Related CMODE Pi ns .......................... ....................... ..........65

4.4.3 CMODE Resistor V alue s... .. .. .......... .. .. ... ..................... .. .. .. ..................... .. ..65

4.5 EEPROM............................................................................................................66

4.5.1 EEPROM Contents Description ..................................................................66

4.5.2 Read/Write Access to the EEPROM ............................................................67

5 Electrical Specifications ...................................................................69

5.1 DC Characteristics..............................................................................................69

5.1.1 VDDIO at 3.3 V ......................................................................................69

5.1.2 VDDIO at 2.5 V ......................................................................................70

5.2 Current Consumption..........................................................................................70

5.2.1 Consumption with 1000BASE-T Link..........................................................70

5.2.2 Consumption with 100BASE-TX Link..........................................................71

VSC8601 Datasheet

Contents

Revision 4.1

September 2009 Page 5

5.2.3 Consumption with 10BASE-T Link..............................................................72

5.2.4 Consumption with No Link and ActiPHY Enabled. .........................................73

5.2.5 Consumption with No Link and ActiPHY Disabled .........................................73

5.2.6 Consumption in Power-Down Mode............................................................74

5.2.7 Consumption in Reset State .....................................................................75

5.3 AC Characteristics ..............................................................................................75

5.3.1 Reference Clock Input .............................................................................76

5.3.2 Clock Output..........................................................................................76

5.3.3 JTAG Interface .......................................................................................77

5.3.4 SMI Interface................................ .. ... ..................... .. .. .. ........... .. .. ..........77

5.3.5 Device Reset.......... .. .. ........... .. ........... .. .. .......... .. ... .......... .. .. ........... .. ......78

5.3.6 RGMII Uncompensated............................................................................80

5.3.7 RGMII Compensated ...............................................................................81

5.4 Operating Conditions ..........................................................................................82

5.5 Stress R atin gs ............. .. ........... .. .. .......... .. .. ........... .. .. ........... .. .. ..................... .. ..83

6 Pin Descriptions ...............................................................................84

6.1 Pin Diagram ......................................................................................................84

6.2 Pins by Function.................................................................................................85

6.2.1 Twisted Pair Interface................. .............................................................85

6.2.2 RGMII MAC Interface ..............................................................................86

6.2.3 Serial Management Interface (SMI)...........................................................87

6.2.4 JTAG.....................................................................................................88

6.2.5 Miscellaneous.........................................................................................88

6.2.6 Power Supply.........................................................................................89

6.2.7 Power Supply and Associated Function.......................................................90

6.3 Pins by Name ....................................................................................................91

6.4 Pins by Number .................................................................................................92

7 Package Information........................................................................93

7.1 Package Drawing................................................................................................93

7.2 Thermal Specifications........................................................................................95

7.3 Moisture Sensitivity............................................................................................95

8 Design Considerations .....................................................................96

8.1 RX_CLK Can Reach as High as 55% Duty Cycle ......................................................96

8.2 First SMI Write Fails after Software Reset ..............................................................96

8.3 Link-Up Issue In Forced 100BASE-TX Mode......................... .................................. . 96

8.4 Default 10Base-T Settings Are Marginal and Cause MAU Test Failure..........................97

8.5 On-Chip Pull-up Resistor Violation.........................................................................99

8.6 Setting the Internal RGMII Timing Compensation Value...........................................99

8.7 10BASE-T Harmonics at 30 MHz and 50 MHz Marginally Violate Specification.............. 99

8.8 Voltage Overshoot When Using On-Chip Switching Regulator.................................. 100

8.9 Long Link-Up Times Caused by Noise on the Twisted Pair Interface ......................... 100

8.10 High VDD33 and Low VDDIOMAC Supply............................................................. 101

9 Ordering Information.....................................................................102

VSC8601 Datasheet

Contents

Revision 4.1

September 2009 Page 6

Figures

Figure 1. Typical Application......................................................................................14

Figure 2. High-level Block Diag ram ............... .............................................................16

Figure 3. RGMII to Cat5 Block Diagram ......................................................................17

Figure 4. RGMII MAC Interface..................................................................................18

Figure 5. Cat5 Media Interface..................................................................................19

Figure 6. Inline Powered Ethernet Switch Diagram .......................................................22

Figure 7. ActiPHY State............................................................................................24

Figure 8. SMI Read Frame ........................................................................................26

Figure 9. SMI W rite Frame................... .. ................................................................. ..26

Figure 10. MDINT Configured as an Open-Drain (Active-Low) Pin.....................................27

Figure 11. MDINT Configured as an Open-Source (Active-High) Pin..................................27

Figure 12. Far-End Loopback ......................................................................................32

Figure 13. Near-End Loopback....................................................................................32

Figure 14. Connector Loopback...................................................................................32

Figure 15. Test Access Port and Boundary-Scan Architecture...........................................34

Figure 16. Register Space Diagram..............................................................................37

Figure 17. EEPROM Read and Write Register Flow..........................................................68

Figure 18. JTAG Interface Timing ................................................................................77

Figure 19. SMI Interface Timing........... .. .. ..................... .. .. .. ..................... .. ... .. .......... ..78

Figure 20. Reset Timing.............................................................................................79

Figure 21. RGMII Uncompensated Timing.....................................................................81

Figure 22. RGMII Compensated Timing ........................................................................82

Figure 23. Pin Diagram ..............................................................................................84

Figure 24. Package Drawing .......................................................................................94

VSC8601 Datasheet

Contents

Revision 4.1

September 2009 Page 7

Tables

Table 1. Interface and Media ...................................................................................17

Table 2. Supported MDI Pair Combinations ................................................................21

Table 3. LED Mode and Function Summary ................................................................28

Table 4. JTAG Device Identification Register Description ..............................................35

Table 5. JTAG Interface Instruction Codes .................................................................35

Table 6. IEEE 802.3 Standard Registers .............. ........................ .. .. .......................... 38

Table 7. Main Registers...........................................................................................38

Table 8. Mode Control, Address 0 (0x00)...................................................................39

Table 9. Mode Status, Address 1 (0x01)....................................................................40

Table 10. Identifier 1, Address 2 (0x02)......................................................................41

Table 11. Identifier 2, Address 3 (0x03)......................................................................41

Table 12. Device Auto-Negotiation Advertisement, Address 4 (0x04) ..............................41

Table 13. Auto-Negotiation Link Partner Ability, Address 5 (0x05)...................................42

Table 14. Auto-Negotiation Expansion, Address 6 (0x06)...............................................43

Table 15. Auto-Negotiation Next Page Transmit, Address 7 (0x07).................................. 43

Table 16. Auto-Negotiation LP Next Page Receive, Address 8 (0x08)...............................44

Table 17. 1000BASE-T Control, Address 9 (0x09).........................................................44

Table 18. 1000BASE-T Status, Address 10 (0x0A) ........................................................45

Table 19. 1000BASE-T Status Extension 1, Address 15 (0x0F) .......................................45

Table 20. 100BASE-TX Status Extension, Address 16 (0x10)..........................................46

Table 21. 1000BASE-T Status Extension 2, Address 17 (0x11) .......................................46

Table 22. Bypass Control, Address 18 (0x12)...............................................................47

Table 23. Receive Error Counter, Address 19 (0x13) .....................................................48

Table 24. False Carrier Sense Counter, Address 20 (0x14).............................................48

Table 25. Disconnect Counter, Address 21 (0x15).........................................................49

Table 26. Extended Control and Status, Address 22 (0x16) ...........................................49

Table 27. Extended PHY Control 1, Address 23 (0x17) ..................................................50

Table 28. Extended PHY Control 2, Address 24 (0x18) ..................................................50

Table 29. Interrupt Mask, Address 25 (0x19)...............................................................51

Table 30. Interrupt Status, Address 26 (0x1A).............................................................52

Table 31. LED Control, Address 27 (0x1B)...................................................................52

Table 32. Auxiliary Control and Status, Address 28 (0x1C) ............................................53

Table 33. Delay Skew Status, Address = 29 (0x1D)......................................................54

Table 34. Extended Registers Page Space....................................................................55

Table 35. Extended Page Access, Address 31 (0x1F).....................................................56

Table 36. Enhanced LED Method Select, Address 16E (0x10) .........................................56

Table 37. Available LED Mode Settings........................................................................56

Table 38. Enhanced LED Behavior, Address 17E (0x11).................................................57

Table 39. CRC Good Counter, Address 18E (0x12)........................................................58

Table 40. MAC Resistor Calibration Control, Address 19E (0x13).....................................58

Table 41. Extended PHY Control 3, Address 20E (0x14).................................................59

Table 42. EEPROM Interface Status and Control, Address 21E (0x15)..............................59

Table 43. EEPROM Read or Write, Address 22E (0x16)..................................................60

Table 44. Extended PHY Control 4, Address 23E (0x17).................................................60

Table 45. Extended PHY Control 5, Address 27E (0x1B) ................................................61

Table 46. RGMII Skew Control, Address 28E (0x1C) .....................................................62

Table 47. EPG Control Register 1, Address 29E (0x1D)..................................................63

Table 48. EPG Control Register 2, Address 30E (0x1E)..................................................64

Table 49. CMODE Configuration Pins and Device Functions ............................................64

Table 50. Device Functions and Associated CMODE Pins ................................................65

Table 51. CMODE Resistor Values and Resultant Bit Settings..........................................65

Table 52. EEPROM Configuration Contents...................................................................67

Table 53. DC Characteristics for VDD33, VDDIOMAC, or VDDIOMICRO at 3.3 V ................69

VSC8601 Datasheet

Contents

Revision 4.1

September 2009 Page 8

Table 54. DC Characteristics for VDDIOMAC or VDDIOMICRO at 2.5 V.............................70

Table 55. Current Consumption: 1000BASE-T, Regulator Enabled ................................... 70

Table 56. Current Consumption: 1000BASE-T, Regulator Disabled.......... .........................71

Table 57. Current Consumption: 100BASE-TX, Regulator Enabled................................... 71

Table 58. Current Consumption: 100BASE-TX, Regulator Disabled.... ............ ............. ..... 71

Table 59. Current Consumption: 10BASE-T, Regulator Enabled.......................................72

Table 60. Current Consumption: 10BASE-T, Regulator Disabled......................................72

Table 61. Current Consumption: No Link, ActiPHY Enabled, Regulator Enabled .................73

Table 62. Current Consumption: No Link, ActiPHY Enabled, Regulator Disabled ................73

Table 63. Current Consumption: No Link, ActiPHY Disabled, Regulator Enabled ............... . 73

Table 64. Current Consumption: No Link, ActiPHY Disabled, Regulator Disabled................74

Table 65. Current Consumption: Power-Down, Regulator Enabled................................... 74

Table 66. Current Consumption: Power-Down, Regulator Disabled.................................. 75

Table 67. Current Consumption: Reset State ...............................................................75

Table 68. AC Characteristics for REFCLK Input .............................................................76

Table 69. AC Characteristics for REFCLK Input with 25 MHz Clock Input ..........................76

Table 70. AC Characteristics for the CLKOUT Pin ..........................................................76

Table 71. AC Characteristics for the JTAG Interface.......................................................77

Table 72. AC Characteristics for the SMI Interface........................................................77

Table 73. AC Characteristics for Device Reset ..............................................................78

Table 74. AC Characteristics for RGMII Uncompensated ................................................80

Table 75. AC Characteristics for RGMII Compensated....................................................81

Table 76. Recommended Operating Conditions.............................................................82

Table 77. Stress Ratings ...........................................................................................83

Table 78. Pin Type Symbols.......................................................................................85

Table 79. Twisted Pair Interface Pins...........................................................................85

Table 80. RGMII MAC Interface Pins ...........................................................................86

Table 81. SMI Pins...................................................................................................87

Table 82. JTAG Pins..................................................................................................88

Table 83. Miscellaneous Pins .....................................................................................88

Table 84. Power Supply Pins......................................................................................89

Table 85. Power Supply Pins and Associated Function Pins.............................................90

Table 86. Thermal Resistances...................................................................................95

Table 87. Ordering Information................................................................................ 102

VSC8601 Datasheet

Revision History

Revision 4.1

September 2009 Page 9

Revision History

This section describes the changes that were implemented in this document. The

changes are listed by revision, starting with the most current publication.

Revision 4.1

Revision 4.1 of this datasheet was published in September 2009. In revision 4.1 of the

document, design considerations were added. For more information, see “Design

Considerations,” page 96.

Revision 4.0

Revision 4.0 of this datasheet was published in November 2007. The following is a

summary of the changes implemented in the datasheet:

• The VSC8601KN package was removed. VSC8601XKN remains available.

• The electrostatic discharge voltage values were added. For charged device model, it

is ±500. For human body model, it is ±1500.

• The moisture sensitivity is now specified as level 3.

• In the jumbo packet register settings (28E.11:10), the packet lengths were

updated.

• In several current consumption specifications, the values for total power at 2.5 V

were corrected. The previous values were slightly elevated.

• In the DC characteristics for VDDIO at 3.3 V, both the input and output leakage

current parameters (IILEAK and IOLEAK) were increased from ±36 µA to ±43 µA.

• In the DC characteristics for VDDIO at 2.5 V, the minimum input high voltage (VIH)

was increased from 1.7 V to 2.0 V. Both the input and output leakage current

parameters (IILEAK and IOLEAK) were increased from ±25 µA to ±35 µA.

• Current consumption specifications were added fo r both the power-down mode and

the reset state.

• In the AC characteristics for the CLKOUT pin, the duty cycle (%DUTY) was modified

from 40% minimum to 44% minimum and from 60% maximum to 56% maximum.

Also, the total jitter (JCLK) was raised from 491 ps maximum to 600 ps maximum,

with the qualifier “time interval error” added to the condition.

• In the SMI specifications, the MDC rise and fall times were corrected from minimum

values to maximum values.

• For the device reset rise time specification, a condition was added that it is

measured from a 10% level to a 90% level.

• In the AC characteristics for RGMII uncompensated, the 1000BASE-T duty cycle

(tDUTY1000) was separated into two sets of v alues. In the first set, the values remain

the same, but the added condition is: at room temperatu re and nominal supply and

VSC8601 Datasheet

Revision History

Revision 4.1

September 2009 Page 10

maximum is 60% and the condition is: register 28E.13:12 set to 00 or 01.

• In the AC characteristics for RGMII compensated, all of the setup and hold times

were modified from 0 ns maximum to 3 ns maximum.

• In the description of pin MDIO, the type was corrected from open drain (OD) to

input and output (I/O).

• The PLLMODE pin description was updated with additional clocking information. If a

crystal or an external 25 MHz clock is used, PLLMODE must be pulled low. If an

external 125 MHz clock is used, PLLMODE must be pulled high.

• A design guideline was added regarding writes from the serial management

interface (SMI) after a software reset.

• A design guideline was added regarding delays in the link-up process while in the

forced 100BASE-TX mode with the automatic MDI/MDI-X detection feature enabled.

• The following design guidelines were removed, because they no longer apply to the

device: Remote Fault Status; DSP Optimization Script Required; Default Port Type

Incorrect; and Core 1.2 V Supply Needs to Meet Specific Range.

Revision 2.2

Revision 2.2 of this datasheet was published in July 2006. The following is a summary

of the changes implemented in the datasheet:

• In the inline powered Ethernet switch diagram, a reference to “SGMII interface”

was corrected to “RGMII interface.”

• In the description of CRC counters, the CRC good counter’s highest value was

corrected from 10,000 to 9,999 packets, after which the counter clears.

• The device revision number definition was updated from 0000 to 0001 in the

identifier 2 register (address 3) and the JTAG devic e identification.

• In the DC Characteristics for VDD33, VDDIOMAC, or VDDIOMICRO at 3.3 V, the output

leakage (IOLEAK) was changed to match the same values as the input leakage

(IILEAK) with the same condition (internal resistor included). Specifically, the values

were changed from –10 µA minimum and 10 µA maximum to –36 µA minimum and

36 µA maximum.

• In the DC Characteristics for VDDIOMAC or VDDIOMICRO at 2.5 V, the output leakage

(IOLEAK) was changed to match the same values as the input leakage (IILEAK) with

the same condition (internal resistor included). Specifically, the values were

changed from –10 µA minimum and 10 µA maximum to –25 µA minimum and

25 µA maximum.

• In the DC characteristics for VDDIOMAC or VDDIOMICRO at 2.5 V, the output high

voltage p arameter (VOH) incorrectly state d IOH = 1.0 mA as a condition. It is now

corrected to the condition IOH = –1.0 mA.

• For all the current consumption specifications with the on-chip switching regulator

enabled, the specification values for IVDD12 and IVDD12A were removed because

VSC8601 Datasheet

Revision History

Revision 4.1

September 2009 Page 11

they were inadvertently added in a prior revision of this document. The IVDD12 and

IVDD12A values are kept for current consumption with the regulator disabled.

• For the 100BASE current consumption specifications, all references to the speed

were corrected from 100BASE-X to 100BASE-T X.

• In the AC characteristics for the CLKOUT pin, the total jitter specifications were

added. They are 217 ps typical and 491 ps maximum.

• F or device reset, both the reset characteristics and timing diagr am were updated to

include new parameters: reset rise time (tRST_RISE) an d supply stable time

(tVDDSTABLE).

• In the stress ratings, the power supply voltage parameter was removed because it

was redundant.

• In the pin description for TX_CLK, the rate was clarified to be 2.5 MHz for 10 Mbps

mode, 25 MHz for 100 Mbps mode, or 125 MHz for 1000 Mbps mode.

• The errata item “RX_CLK Can Reach as High as 55% Duty Cycle” remains in effect

but all other errata items no longer apply to the latest part revision.

Revision 2.1

Revision 2.1 of this datasheet was published in February 2006. The following is a

summary of the changes implemented in the datasheet:

• In the high-level block diagram, representation of the XTAL pin was corrected from

“XTAL 1/2” to “XTAL1” and “XTAL2.”

• In the RGMII to Cat5 block diagram, the interface name was corrected from GMII to

RGMII.

• New information was added about how to manually force the device to use

MDI/MDI-X.

• The VSC8601 device switches between the low-power state and LP wake-up state

every two seconds; the rate is not programmable, as was originally stated.

• In the link partner wake-up state, the device sends FLP bursts for two seconds;

they are not limited to three bursts, as was originally stated.

• In the description of the PHY address for the serial management interface (SMI),

the physical address was corrected from 3:0 to 4:0.

• For the enhanced LED method, controlled by MII Register 16E, two of the LED

modes have changed. Mode 11, TX activity, and mode 13, RX activity, are now both

reserved.

• In the description of the far-end loopback testing feature, the controlling register

bit was corrected from 23.3 to 27E.10.

• For the JTAG interface instructions EXTEST and SAMPLE/PRELOAD, the values for

• For the Mode Control register (address 0), when bit 11 (power-down) is set, RGMII

in-band signaling will not function.

VSC8601 Datasheet

Revision History

Revision 4.1

September 2009 Page 12

• In the Identifier 2 register (address 3), which enables device identification, the

default for bits 9:4 was modified from TBD to 000010.

• In the LED Control register (address 27), the name for bits 2 and 1 was corrected

from “link/activity” to simply “activity.”

• In the ActiPHY Control (address 20E), bit 5 was reassigned from being reserved to

being the MAC RX_CLK disable parameter.

• In the extended PHY control 4 register (address 23E), all the bit settings were

mistakenly omitted. They are now restored.

• In the Extended PHY Control 5 register (address 27E), the settings have changed

for bits 8:6 and 5:3 (100BASE-TX and 1000 BASE-T transmitter amplitude control).

For bits 8:6 (100BASE-TX), the setting 011 changed from +5 amplitude to

reserved, making bit setting 010 (+4 amplitude) the largest. For bits 5:3

(1000BASE-T), the setting 011 changed from +3 amplitude to reserved, making bit

setting 010 (+2 amplitude) the largest.

• F or added clarity, the table that lists device functions and related CMODE pins now

references the associated register and bit for each function.

• For the EEPROM Configuration Contents table, some address locations were added

and the introductory text was corrected.

• For the DC electrical specifications with VDDIO at 3.3 V and with VDDIO at 2.5 V, an

additional condition was added. The specifications may be considered valid only

when VDDREG = 3.3 V.

• The current consumption specifications were replaced with a new set of

specifications.

• In the recommended operating conditions, the minimum and maximum values

were modified for the VDDIOMICRO, VDDIOMAC, and VDD33 parameters at 3.3 V.

For all of these parameters, the minimum changed from 3.13 V to 3.0 V and the

maximum changed from 3.47 V to 3.6 V. The VDDREG parameter was added to the

recommended operating conditions.

• In the stress ratings, a new rating was added for the VDDREG parameter.

• An errata section was added.

Revision 2.0

Revision 2.0 of this datasheet was published in December 2005. This was the first

publication of the document.

VSC8601 Datasheet

Introduction

Revision 4.1

September 2009 Page 13

1Introduction

This document consists of descriptions and specifications for both functional and

physical aspects of the VSC8601 10/100/1000BASE-T PHY with RGMII MAC Interface.

In addition to the datasheet, Vitesse maintains an extensive device-specific library of

support and collateral materials that you may find useful in developing your own

product. Depending upon the Vitesse device, this library may include:

• Software Development Kits with sample commands and scripts

• Reference designs showing the Vitesse device built in to applications in ways

intended to exploit its relative strengths

• Presentations highlighting the operational features and specifications of the device

to assist in developing your own product road map

• Input/Output Buffer Information specification (IBIS) models to help you create and

support the interfaces available on the particular Vitesse product

• Application notes that provide detailed descriptions of the use of the particular

Vitesse product to solve real-world problems

• White papers published by industry experts that provide ancillary and background

information useful in developing products that take full advantage of Vitesse

product designs and capabilities

• User guides that describe specific techniques for interfacing to the particular Vitesse

products

Visit and register as a user on the Vitesse Web site to keep abreast of the latest

innovations from research and development teams and the most current product and

application documentation. The address of the Vitesse Web site is www.vitesse.com.

VSC8601 Datasheet

Product Overview

Revision 4.1

September 2009 Page 14

2 Product Overview

The VSC8601 device is a low-power Gigabit Ethernet (GbE) tr ansceiver ideal for Gigabit

LAN-on-Motherboard applications. The device’s compact, plastic low-profile quad flat

package (LQFP) with an exposed pad is optimal for footprint-sensitive applications.

Vitesse’s mixed signal and digital signal processing (DSP) architecture assures robust

performance. It supports both half -duplex and full-duplex 10BASE-T, 100BASE-TX, and

1000BASE-T communication speeds over Category 5 (Cat5) unshielded twisted pair

(UTP) cable at distances greater than 140 m, displaying excellent tolerance to NEXT,

FEXT, echo, and other types of ambient environment and system electronic noise.

The following illustration shows a high-level, generic view of a VSC8601 application.

Figure 1. Typical Application

2.1 Features

This section lists key aspects of the VSC8601 device functionality and design that

distinguish it from similar products:

• 10/100/1000BASE-T PHY with industry’s lowest power consumption.

• Compliant with IEEE 802.3 (10BASE-T, 100BASE-TX, 1000BASE-T) specifications.

• Supports RGMII versions 1.3 and 2.0 (2.5 V, 3.3 V) MAC interface.

• Low EMI line driver with integrated line side termination resistors.

• Up to 16 kB jumbo frame support in all speeds.

• Three programmable direct drive LEDs.

• Suite of test modes, including loopback paths, Ethernet packet generators, and CRC

counters.

•The VeriPHY

® suite provides extensive network cable information such as cable

length, termination status, and open/short fault location.

•ActiPHY

TM power saving modes.

• Adv anced power management complies with Wake-on-LANTM and PCI2.2 power

requirements.

VSC8601

10/100/1000BASE-T

Transceiver

RJ45+Magnetics

RGMII

Management I/F (MDC / MDIO)

10/100/1000BASE-T MAC,

Switching ASIC,

or Network Processor

25 MHz

3.3 V

VSC8601 Datasheet

Product Overview

Revision 4.1

September 2009 Page 15

• Legacy Power-over-Ethernet (POE) support.

• Powered by a single 3.3 V supply by using the optional on-chip switching regulator.

• IEEE 1149.1 JTAG boundary-scan support.

• 10 mm × 10 mm, 64-pin, plastic LQFP package with an exposed pad.

2.2 Applications

Suggested applications for the VSC8601 device include:

• LAN-on-Motherboards, NICs, and mobile PCs

• iSCSI and TOE applications

• Workgroup and desktop switches and routers

• Gigabit Ethernet SAN, NAS, and MAN systems

• Network-enabled devices such as printers, IP phones, and gaming appliances

•ATCA

TM 3.0 and PICMGTM 2.16 Ethernet backplane applications

VSC8601 Datasheet

Product Overview

Revision 4.1

September 2009 Page 16

2.3 Block Diagram

The following illustration shows the primary functional blocks of the VSC8601 device.

Figure 2. High-level Block Diagram

LED Interface

10/100/

1000BASE-T

PCS

LED[2:0]

CLKOUT

XTAL1

TXD[3:0]

TX_CTL

RXD[3:0]

RX_CTL

RGMII MAC

Interface

Jumbo Packet

FIFO

TXVPA

TXVNA

TXVPB

TXVNB

TXVPC

TXVNC

TXVPD

TXVND

PLL

JTAG

Management

and Control

Interface

TDI

NTRST

TMS

TCK

TDO

CMODE[3:0]

NRESET

EECLK

EEDAT

MDINT

MDIO

MDC

MDI

Twisted Pair

Interface

10/100/

1000BASE-T

PMA

REF_FILT

REF_REXT

TX_CLK

RX_CLK

Power Regulation REG_OUT

REG_EN

NSRESET

MDI Reference

XTAL2

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 17

3 Functional Descriptions

This section provides detailed information about how the VSC8601 device works, what

configurations and operational features are available, and how to test its functions. It

includes descriptions of the various device interfaces and how to set them up.

3.1 Interface and Media

The VSC8601 device operates with the interface and media shown in the following table

and illustration.

Figure 3. RGMII to Cat5 Block Diagram

3.2 MAC Interface

The VSC8601 supports RGMII versions 1.3 and 2.0 (2.5 V, 3.3 V) MAC interface.

3.2.1 MAC Resistor Calibration

To simplify board design, the VSC8601 MAC interface uses SimpliPINTM outputs that can

self-calibrate to a desired impedance characteristic to eliminate the need for series

termination resistors. By default, these RX output pins calibrate to 50 Ω. In addition,

MII Register 19E, bits 15:14 can be used to select different target impedances. For

more information, see “MAC Resistor Calibration Control,” page 58.

3.2.2 RGMII MAC Interface Mode

The RGMII interface can support all three speeds (10 Mbps, 100 Mbps, and 1000 Mbps)

and is used as an interface to an RGMII-compatible MAC.

Table 1. Interface and Media

Operating Mode MAC Interface Supported Media

RGMII - Cat5 RGMII 10/100/1000BASE-T

MAC Cat5RGMII VSC8601 Cat5

Link Partner

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 18

Figure 4. RGMII MAC Interface

3.3 Cat5 Media Interface

The twisted pair interface on the VSC8601 is compliant with the IEEE802.3-2000

specifications for Cat5 media. The VSC8601, unlike other Gigabit PHYs, has all passive

components (required to connect the PHY’s Cat5 interface to an external 1:1

transformer) fully integrated into the device. The connection of the twisted pair

interface is shown in the following figure.

RGMII MAC SimpliPHY

TXD[3]

TXD[2]

TXD[1]

TXD[0]

TX_CLK

TX_CTL

RXD[3]

RXD[2]

RXD[1]

RXD[0]

RX_CLK

RX_CTL

TD[3]

TD[2]

TD[1]

TD[0]

TXC

TX_CTL

RD[3]

RD[2]

RD[1]

RD[0]

RXC

RX_CTL

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 19

Figure 5. Cat5 Media Interface

3.4 Cat5 Auto-Negotiation

The VSC8601 device supports twisted pair auto-negotiation as defined by clause 28 of

the IEEE standard 802.3-2000.

The auto-negotiation process consists of the evaluation of the advertised capabilities of

the PHY and its link partner to determine the best possible operating mode , throughput

speed, duplex configuration, and master or slave operating modes in the case of

1000BASE-T setups. Auto-negotiation also allows a connected MAC to communicate

with its link partner MAC through the VSC8601 device using the optional “next pages,”

which set attributes that may not otherwise be defined by the IEEE standard.

In installations where the Cat5 link partner does not support auto-negotiation, the

VSC8601 automatically switches to use parallel detection to select the appropriate link

speed.

Clearing VSC8601 device register 0, bit 12 disables clause 28 twisted-pair

auto-negotiation. If auto-negotiation is disabled, the state of register bits 0.6, 0.13,

TXVP_A_n

RJ-45

A+

A-

B+

B-

C+

C-

D+

D-

SimpliPHY

1000pF, 2kV

0.1 µF

TXVN_A_n

TXVP_B_n

TXVN_B_n

TXVP_C_n

TXVN_C_n

TXVP_D_n

TXVN_D_n

Transformer

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 20

and 0.8 determine the device operating speed and duplex mode. For more information

about configuring auto-negotiation, see “IEEE Standard and Main Registers,” page 38.

3.5 Manual MDI/MDI-X Setting

As an alternative to automatic MDI/MDI -X detection (using HP Auto-MDIX technology),

you can force the PHY to select MDI or MDI-X using the following scripts.

Format:

Phywrite ( register(dec), data(hex) )

Phywritemask ( register(dec), data(hex), mask(hex) )

To force MDI:

Phywrite ( 31, 0x2A30 )

Phywritemask ( 5, 0x0010, 0x0018 )

Phywrite ( 31, 0x0000 )

To force MDI-X:

Phywrite ( 31, 0x2A30 )

Phywritemask ( 5, 0x0018, 0x0018 )

Phywrite ( 31, 0x0000 )

To resume MDI/MDI-X setting based on register 18, bits 7 and 5:

Phywrite ( 31, 0x2A30 )

Phywritemask ( 5, 0x0000, 0x0018 )

Phywrite ( 31, 0x0000 )

3.6 Automatic Crossover and Polarity Detection

For trouble-free configuration and management of Ethernet links, the VSC8601 device

includes a robust, automatic, media-dependent and crossed media-dependent

detection feature, HP Auto-MDIX, in all of its three available speeds (10BASE-T,

100BASE- T, and 1000BASE-T). The function is fully compliant with clause 40 of the IEEE

standard 802.3-2002.

Additionally, the device detects and corrects polarity errors on all MDI pairs—a useful

capability that exceeds the requirements of the standard.

Both HP Auto-MDIX detection and polarity correction are enabled in the device by

default. The default settings are adjustable using device register bits 18.5:4. Status

bits for each of these functions are located in register 28.

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 21

The VSC8601 device’s algorithm for HP Auto-MDIX successfully detects, corrects, and

operates with any of the MDI wiring pair combinations listed in the following table.

Note The VSC8601 device can be configured to perform HP Auto-MDIX even when its

auto-negotiation feature is disabled (setting register 0.12 to 0) and the link is forced

into 10/100 speeds. To enable this feature, set register 27E.15 = 0.

3.7 Link Speed Downshift

For operation in cabling environments that are incompatible with 1000BASE-T, the

VSC8601 device provides an automatic link speed “downshift” option. When enabled,

the device automatically changes its 1000BASE-T auto-negotiation advertisement to

the next slower speed after a set number of failed attempts at 1000BASE-T.

This is useful in networks using older cable installations that may include only pairs A

and B and not pairs C and D.

To configure and monitor link speed downshifting, use register bits 20E.4:1. For more

information, see “Extended PHY Control Set 1,” page 50.

3.8 Transformerless Ethernet

The Cat5 media interface supports 10/100/1000B T Ethernet for backplane applications

such as those specified by the PICMGTM 2.16 and ATCATM 3.0 specifications for

eight-pin channels. With proper AC coupling, the typical Cat5 transformer can be

removed and replaced with capacitors.

3.9 Ethernet Inline Powered Devices

The VSC8601 device can detect inline powered devices in Ethernet network

applications. Its inline powered detection capability can be part of a system that allows

for IP-phone and other devices, such as wireless access points, to receive power

directly from their Ethernet cable, similar to office digital phones receiving power from

a Private Branch Exchange (PBX) office switch over the telephone cabling. This can

eliminate the need for an IP-phone to have an external power supply. It also enables

the inline powered device to remain active during a power outage (assuming the

Ethernet switch is connected to an uninterrupted power supply, battery, back-up power

generator, or some other uninterruptible power source).

For more information about inline powered device detection, visit the Cisco Web site at

www.cisco.com.

Table 2. Supported MDI Pair Combinations

RJ-45 Pin Pairings

1, 23, 64, 57, 8Mode

A B C D Normal MDI

B A D C Normal MDI-X

A B D C Normal MDI with pair swap on C and D pair

B A C D Normal MDI-X with pair swap on C and D pair

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 22

The VSC8601 device is compatible with switch designs that are intended for use in

systems that supply power to Data Terminal Equipment (D TE) using the MDI or twisted

pair cable, as described in clause 33 of the IEEE standard 802.3af. The following

illustration shows an example of this type of application.

Figure 6. Inline Powered Ethernet Switch Diagram

The following procedure describes the process that an Ethernet switch must perform to

process inline power requests made by a link partner (LP) that is, in turn, capable of

receiving inline power.

1. Enable the inline powered device detection mode on each VSC8601 PHY using its

serial management interface. Set register bit 23E.10 to 1.

2. Ensure that the VSC8601 device auto-negotiation enable bit (register 0.12) is also

set to 1. In the application, the device sends a special Fast Link Pulse (FLP) signal

to the LP. Reading register bit 23E.9:8 returns 00 during the search for devices that

require Power-o ver-Ethernet (Po E).

3. The VSC8601 PHY monitors its inputs for the FLP signal looped back by the LP. An

LP capable of receiving Po E will loopback the FLP pulses when it is in a

powered-down state. This is reported when VSC8601 device register bit 23E.9 :8

reads back 01. It can also be verified as an inline power detection interrupt by

SMI

Control

Processor

Gigabit Switch

PHY_0

RGMII

Interface

PHY_1

X-former

RJ-45

I/F

PHY_n

RJ-45

I/F

X-former

RJ-45

I/F

Inline

Power

Supply Unit

Cat5

X-former

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 23

reading VSC8601 device register bit 26.9, which should be a 1, and which is

subsequently cleared and the interrupt de-asserted after the read.

If an LP device does not loop back the FLP after a specific time, VSC8601 device

4. If the VSC8601 PHY reports that the LP needs P oE, the Ethernet switch must enable

inline power on this port, externally of the PHY.

5. The PHY automatically disables inline powered device detection if the VSC8601

device register bit 23E.9:8 automatically resets to 10, and then automatically

changes to its normal auto-negotiation process. A link is then auto-negotiated and

established when the link status bit is set (register bit 1.2 is set to 1).

6. In the event of a link failure (indicated when VSC8601 device register bit 1.2 reads

0), the inline power should be disabled to the inline powered device external to the

PHY. The VSC8601 PHY disables its normal auto-negotiation process and re-enables

its inline powered device detection mode.

3.10 ActiPHY Power Management

In addition to the IEEE-specified power-down control bit (device register bit 0.11), the

device also includes an ActiPHY™ power management mode for each PHY. This mode

enables support for power-sensitive applications such as laptop computers with

Wake-on-LAN™ capability. It utilizes a signal-detect function that monitors the media

interface for the presence of a link to determine when to automatically power-down the

PHY. The PHY “wakes up” at a programmable interval and attempts to “wake up” the

link partner PHY by sending a burst of FLP over copper media.

The ActiPHY power management mode in the VSC8601 device can be enabled during

normal operation at any time by setting register bit 23.5 to 1.

There are three operating states possible when ActiPHY mode is enabled:

• Low-power state

•LP wake-up state

• Normal operating state (link-up state)

The VSC8601 device switches between the low-power state and LP w ake-up state every

two seconds until signal energy is detected on the media interface pins. When signal

energy is detected, the PHY enters the normal operating state. If the PHY is in its

normal operating state and the link fails, the PHY returns to the low-power state after

the link status time-out timer has expired. After reset, the PHY enters the low-power

state.

When auto-negotiation is enabled in the PHY, the ActiPHY state machine operates as

described. If auto-negotiation is disabled and the link is forced to 10BT or 100BTX

modes while the PHY is in its low-power state, the PHY continues to transition between

the low-power and LP wake-up states until signal energy is detected on the media pins.

At that time, the PHY transitions to the normal operating state and stays in that state

even when the link is drop p ed. If auto-neg otiation is disabled while the PHY is in the

normal operation state, the PHY stays in that state when the link is dropped and does

not transition back to the low-power state.

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 24

The following illustration shows the relationship between ActiPHY states and timers.

Figure 7. ActiPHY State

3.10.1 Low-Power State

In the low-power state, all major digital blocks are powered down. However, the

following functionality is provided:

• SMI interface (MDC, MDIO, MDINT)

•CLKOUT

In this state, the PHY monitors the media interface pins for signal energy. The PHY

comes out of low-power state and transitions to the normal oper ating state when signal

energy is detected on the media. This happens when the PHY is connected to one of the

following:

• Auto-negotiation capable link partner

• Auto-negotiation incapable (blink/forced) link partner (100BASE-TX or 10BASE-T)

• Another PHY in ActiPHY LP wake-up state

In the absence of signal energy on the media pins, the PHY transitions from the

low-power state to the LP wake-up state periodically based on the progr ammable sleep

timer (register bits 20E.14:13). The actual sleep time duration is randomized from

–80 ms to +60 ms to avoid two linked PHYs in ActiPHY Mode entering a lock-up state

during operation.

Low-Power State

LP Wake-up

State

Normal

Operation

FLP Burst

Signal Sent

Sleep Timer Expires

Timeout Timer Expires and

Auto-Negotiation Enabled

Signal Energy Detected on

Media

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 25

3.10.2 Link Partner Wake-Up State

In this state, the PHY attempts to wake up the link partner. FLP bursts are sent on

alternating pairs A and B of the Cat5 media for a duration of two seconds.

In this state, the following functionality is provided:

• SMI interface (MDC, MDIO, MDINT)

•CLKOUT

After sending signal energy on the relevant media, the PHY returns to the low-power

state.

3.10.3 Normal Operating State

In this state, the PHY establishes a link with a link partner. When the media is

unplugged or the link partner is powered down, the PHY waits for the duration of the

programmable link status time-out timer, which is set using register bit 28.7 and

bit 28.2. It then enters the low-power state.

3.11 Serial Management Interface

The VSC8601 device includ es an IEEE 802.3-compliant serial management interface

(SMI) that is affected by use of its MDC and MDIO pins. The SMI provides access to

device control and status registers. The register set that controls the SMI consists of 32

16-bit registers, including all required IEEE-specified registers. Also, there are

additional pages of registers accessible by means of device register 31.

For more information, see “Extended Page Registers,” page 55.

The SMI is a synchronous serial interface with bidirectional data on the MDIO pin that is

clocked on the rising edge of the MDC pin. The interface can be clocked at a rate from

0 MHz to 25 MHz, depending upon the total load on MDIO. An external, 2 kΩ pull-up

resistor is required on the MDIO pin.

3.11.1 SMI Frames

Data is transferred over the SMI using 32-bit frames with an optional and arbitrary

length preamble. The following illustrations show the SMI frame format for the read

operation and write operation.

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 26

Figure 8. SMI Read Frame

Figure 9. SMI Write Frame

The following provides additional information about the terms used in Figure 8 and

Figure 9.

Idle During idle, the MDIO node goes to a high-impedance state. This allows an

external pull-up resistor to pull the MDIO node up to a logical 1 state. Because the idle

mode should not contain any transitions on MDIO, the number of bits is undefined

during idle.

Preamble By default, preambles are not expected nor required. The preamble is a

string of ones. If it exists, the preamble must be at least one bit; otherwise, it may be

of an arbitrary length.

Start of Frame (SFD) A pattern of 01 indicates the start of frame. If the pattern is

not 01, all following bits are ignored until the next preamble pattern is detected.

Read or Write Opcode A pattern of 10 indicates a read. A pattern of 01 indicates a

write. If these bits are not either 01 or 10, all following bits are ignored until the next

preamble pattern is detected.

PHY Address The VSC8601 responds to a message frame only when the received

PHY address matches its physical address. The physical address is five bits long (4:0).

The bits are set by the CMODE pins.

Turn-around The two bits used to avoid signal contention when a read operation is

performed on the MDIO are called the turn-around (TA) bits. During read operations,

the VSC8601 device drives the second TA bit, which is a logical 0.

Data The 16-bits read from or written to the device are considered the data or data

stream. When data is read from a PHY, it is valid at the output from one rising edge of

MDC

MDIO

Preamble

(optional)

SFD

1Z10

Read

1 0

PHY Address

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

to PHY

TA Register Data from PHY

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Z Z

IdleIdle

Station Manager Drives MDIO PHY Drives MDIO

MDC

MDIO

Preamble

(optional)

SFD

1Z10

Write

PHY Address

A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

to PHY

TA Register Data from PHY

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Z Z

IdleIdle

Station Manager Drives MDIO (PHY tristates MDIO during entire sequence)

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 27

MDC to the next rising edge of MDC. When data is being written to the PHY, it must be

valid around the rising edge of MDC.

Idle The sequence is repeated.

3.11.2 SMI Interrupts

The SMI also includes an output interrupt signal, MDINT, for signaling the station

manager when certain events occur in the PHY.

The MDINT pin can be configured for open-drain (active-low) by tying the pin to a

pull-up resistor and to VDDIO. The following illustration shows this configuration.

Figure 10. MDINT Configured as an Open-Drain (Active-Low) Pin

Alternatively, each MDINT pin can be configured for open-source (activ e-h igh) by tying

the pin to a pull-down resistor and to VSS. The following illustration shows this

configuration.

Figure 11. MDINT Configured as an Open-Source (Active-High) Pin

When a PHY generates an interrupt, the MDINT pin is asserted (driven high or low,

depending on resistor connection) if the interrupt pin enable bit (MII Register 25.15) is

set.

MDINT

(to Station Manager)

Interrupt Pin Enable

(MII Register 25.15)

Interrupt Pin Status

(MII Register 26.15)

External Pull-up

at Station Manager

for Open-Drain

(Active Low Mode)

VDDIO

MDINT

(to Station Manager)

Interrupt Pin Enable

(MII Register 25.15)

Interrupt Pin Status

(MII Register 26.15) External Pull-Down at

Station Manager

for Open Source

(Active-High Mode)

VDDIO

MDINT

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 28

3.12 LED Interface

The VSC8601 device drives up to three LEDs directly. All LED outputs are active-low

and are driven using 3.3 V from the VDD33 power supply. When active, the pins are

mainly used to sink current of the cathode side of an LED, but the pins can also supply

source power to the anode portion of LEDs when they are not in the active state. This

allows for two LED pins to be used to drive a multi-status, bi-colored LED.

3.12.1 Simple or Enhanced LED Method

The VSC8601 provides two methods for controlling its LEDs: simple or enhanced. The

simple LED method is backward-compatible to the LED control found in prior Vitesse

Ethernet PHY devices. The simple LED method eases software backward compatibility

for customers switching to the VSC8601. The simple LED method is controlled by MII

For added flexibility, the VSC8601 LED can be controlled using the enhanced LED

method. The enhanced LED method is enabled by setting MII R egister 17E.4 = 1. When

enabled, then the LEDs are controlled by MII Registers 16E and 17E. In this method,

the MII Register 27 settings are ignored.

Simple LED Method When MII Register 17E.4 = 0, the LEDs are controlled by the

simple LED method. This LED method is enabled on power-up and is controlled by MII

see “LED Control,” page 52.

Enhanced LED Method When MII Register 17E.4 = 1, the LEDs are controlled by the

enhanced LED method. In this method, MII R egister 16E and 17E control the LEDs. For

more information, see “Enhanced LED Method Select,” page 56 and “Enhanced LED

Behavior,” page 57.

3.12.2 LED Modes

If you are using the enhanced LED method, there are several LED modes available.

They are found in MII Register 16E. Each LED pin can be configured to display different

status information. Set the LED mode either by using register 16E or with the CMODE

pin setting. The following table summarizes the LED functions.

Note The modes listed in the following table are equivalent to the setting used in

(de-asserted), 0 = pin held low (asserted), and blink/pulse-stretch is dependent on the

LED behavior setting in register 17E.

Table 3. LED Mode and Function Summary

Mode Function Name LED State and Description

0 Link/activity 1 = No link in any speed on any media interface.

0 = Valid link at any speed on any media interface.

Blink or pulse-stretch = Valid link at any speed on any media interface and

with activity present.

1 Link1000/activity 1 = No link in 1000BASE-T.

0 = Valid 1000BASE-T link.

Blink or pulse-stretch = Valid 1000BASE-T link with activity present.

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 29

2 Link100/activity 1 = No link in 100BASE-TX.

0 = Valid 100BASE-TX link.

Blink or pulse-stretch = Valid 100BASE-TX link with activity present.

3 Link10/activity 1 = No link in 10BASE-T.

0 = Valid 10BASE-T l ink.

Blink or pulse-stretch = Valid 10BASE-T link with activity present.

4 Link100/1000/activity 1 = No link in 100BASE-TX or 1000BASE-T.

0 = Valid 100BASE-TX or 1000BASE-T link.

Blink or pulse-stretch = Valid 100BASE-TX or 1000BASE-T link with activity

present.

5 Link10/1000/activity 1 = No link in 10BASE-T or 1000BASE-T.

0 = Valid 10BASE-T or 1000BASET-T link.

Blink or pulse-stretch = Valid 10BASE-T or 1000BASE-T link with activity

present.

6 Link10/100/activity 1 = No link in 10BASE-T or 100BASE-TX.

0 = Valid 10BASE-T or 100BASE-T X link.

Blink or pulse-stretch = Valid 10BASE-T or 100BASE-TX link with activity

present.

7 Reserved

8 Duplex/collision 1 = Link established in half-duplex mode, or no link established.

0 = Link establi shed in full-duplex mode.

Blink or pulse-stretch = Link established in half-duplex mode but collisions are

present.

9 Collision 1 = No collision det ected.

Blink or pulse-stretch = Collision detected.

10 Activity 1 = No activity present.

Blink or pulse-stretch = Activity presen t (becomes TX activity present if

11 Reserved

12 Auto-negotiation fault 1 = No auto-negotiation fault present.

0 = Auto-negotiation fault occurred.

13 Reserved

14 Force LED off 1 = De-asserts the LED.

15 Force LED on 0 = Asserts the LED.

Table 3. LED Mode and Function Summary (continued)

Mode Function Name LED State and Description

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 30

3.12.3 LED Behavior

Several LED behaviors can be programmed into the VSC8601 device. Use the settings

in register 17E to program LED behavior, which includes the following:

LED Combine Enables an LED to display status for a combination of primary and

secondary modes. This can be enabled or disabled for each LED pin. For example, a

copper link running in 1000BASE- T mode and activity present can be displa yed with one

LED by configuring an LED pin to Link1000/Activity mode. The LED asserts when linked

to a 1000BASE-T partner and also blinks or pulse-stretches whe n activity is either

transmitted by the PHY or received by the link partner. The combine feature when

disabled only allows status of the primary function selected. In this example, only

Link1000 asserts the LED, and the secondary mode, activity, does not display if the

combine feature is disabled.

LED Blink or Pulse-Stretch This behavior is used for activity and collision indication.

This can be uniquely configured for each LED pin. Activity and collision events can occur

randomly and intermittently throughout the link -up period. For activity or collision to be

visually seen, these two modes are provided. Blink is a 50% duty cycle oscillation of

asserting and de-asserting an LED pin. Pulse-stretch guarantees that an LED is asserted

and de-asserted for a specific period of time when activity is either present or not

present. These rates can also be configured using a register setting.

Rate of LED Blink or Pulse-Stretch This controls the LED blink rate or pulse-stretch

length when blink/pulse-stretch is enabled on an LED pin. The blink rate, which

alternates between a high and low voltage level at a 50% duty cycle, can be set to

2.5 Hz, 5 Hz, 10 Hz, or 20 Hz. For pulse-stretch, this can be set to 50 ms, 100 ms,

200 ms, or 400 ms.

LED Pulsing Enable To provide additional power savings, the LEDs (when asserted)

can be pulsed at 5 kHz, 20% duty cycle.

3.13 Testing Features

The VSC8601 device includes several testing features designed to make it easier to

perform system-level debugging and in-system production testing. This section

describes the available features.

3.13.1 Ethernet Packet Generator (EPG)

The device EPG can be used at each of the 10/100/1000BASE-T speed settings to

isolate problems between the MAC and the VSC8601 device, or between a locally

connected PHY and its remote link partner. Enabling the EPG feature effectively disables

all MAC interface transmit pins and selects the EPG as the source for all data

transmitted onto the twisted pair interface.

Note The EPG is intended for use with laboratory or in-system testing equipment only.

Do not use the EPG testing feature when the VSC8601 device is connected to a live

network.

To enable the VSC8601 device EPG feature, set the device register bit 29E.15 to 1.

When the EPG is enabled, packet loss occurs during transmission of packets from the

MAC to the PHY. However, the PHY receive output pins to the MAC are still active when

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 31

the EPG is enabled. If it is necessary to disable the MAC receive pins as well, set

When the device register bit 29E.14 is set to 1, the PHY begins transmitting Ethernet

packets based on the settings in registers 29E and 30E. These registers set:

• Source and destination addresses for each packet

•Packet size

•Inter-packet gap

• FCS state

• Tra nsm it d uration

• Payload pattern

If register bit 29E.13 is set to 0, register bit 29E.14 is cleared a utomatically after

30,000,000 packets are transmitted.

3.13.2 CRC Counters

Two separate cyclical redundancy checking (CRC) counters are available in the

VSC8601 device. There is a 14-bit CRC good counter available in register bits 18E.13:0

and a separate 8-bit CRC error counter available in register bits 23E.7:0.

The device CRC counters operate in 10/100/1000BASE-T testing as follows:

• After receiving a packet on the media interface, register bit 18E.15 is set and

cleared after being read. The packet then is counted by either the CRC good

counter or the CRC error counter. Both CRC counters are also automatically cleared

when read.

• The CRC good counter’s highest value is 9, 999 packets. Upon receiving the next

packet, the counter clears and continues to count additional packets beyond that

value. The CRC error counter saturates when it reaches its maximum counter limit

of 255 packets.

3.13.3 Far-end Loopback

The far-end loopback testing feature is enabled by setting register bit 27E.10 to 1.

When enabled, it forces incoming data from a link partner on the current media

interface to be retransmitted back to the link partner on the media interface as shown

in the following illustration. In addition, the incoming data also appears on the receive

data pins of the MAC interface. Data present on the transmit data pins of the MAC

interface is ignored when using this testing feature.

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 32

Figure 12. Far-End Loopback

3.13.4 Near-End Loopback

When the near-end loopback testing feature is enabled (by setting the device register

bit 0.14 to 1), data on the transmit data pins (TXD) is looped back onto the device

received data pins (RXD) as illustrated in the following illustration. When using this

testing feature, no data is transmitted over the network.

Figure 13. Near-End Loopback

3.13.5 Connector Loopback

The connector loopback testing feature allows for the twisted pair interface to be looped

back externally. When using this feature, the PHY must be connected to a loopback

connector or a loopback cable. Pair A should be connected to pair B and pair C to

pair D, as shown in the following illustration. The connector loopback feature functions

at all available interface speeds.

Figure 14. Connector Loopback

When using the connector loopback testing feature, the device auto-negotiation, speed,

and duplex configuration is set using device registers 0, 4, and 9. For 1000BASE-T

Link Partner SimpliPHY MAC

RXD

TXD

Cat5

Link Partner SimpliPHY MAC

RXD

TXD

Cat5

SimpliPHY MAC

RXD

TXD

Cat5

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 33

connector loopback, only the following additional writes are required. Execute the

additional writes in the following order:

1. Enable the 1000BASE-T connector loopback. Set register bit 24.0 to 1.

2. Disable the pair swap correction. Set register bit 18.5 to 1.

3.13.6 VeriPHY Cable Diagnostics

The VSC8601 device includes a comprehensive suite of cable diagnostic functions that

are available using SMI reads and writes. These functions enable a variety of cable

operating conditions and status to be accessed and checke d. The VeriPHY suite has the

ability to identify the cable length and operating conditions and to isolate a variety of

common faults that can occur on the Cat5 twisted pair cabling.

For more information, refer to the PHY API Software and Programmers Guide on the

Vitesse Web site at www.vitesse.com.

Note If a link is established on the twisted pair interface in 1000BASE-T mode,

VeriPHY can run without disrupting the link or any data transfer. However, if a link is

established in 100BASE-TX or 10BASE-T, VeriPHY causes the link to drop while the

diagnostics are running. After the diagnostics are finished, the link is then

re-established.

The following diagnostic functions are part of the VeriPHY suite:

• Detection of coupling between cable pairs

• Detection of cable pair termination

• Determination of cable length

Coupling Between Cable Pairs Shorted wires, improper termination, or high

crosstalk resulting from an incorrect wire map can cause error conditions, such as

anomalous coupling between cable pairs. These conditions can all prevent the device

from establishing a link at any speed.

Cable Pair Termination Proper termination of Cat5 cable requires 100-Ω differential

impedance between the positive and negative cable terminals. The IEEE standard 802.3

allows for a termination of as high as 115 Ω or as low as 85 Ω. If the termination falls

outside of this range, it is reported by the VeriPHY diagnostics as an anomalous

termination. The diagnostics can also determine the presence of an open or shorted

cable pair.

Cable Length When the Cat5 cable in an installation is properly terminated, VeriPHY

reports the approximate cable length in meters.

3.13.7 IEEE 1149.1 JTAG Boundary Scan

The VSC8601 device supports the Test Access Port (TAP) and boundary-scan

architecture described in the IEEE standard 1149.1. The device includes an IEEE

1149.1-compliant test interface, often referred to as a “JTAG TAP Interface.”

The JT AG boundary-scan logic on the VSC8601 device, accessed using its T AP interface,

consists of a boundary-scan register and other logic control blocks. The TAP controller

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 34

includes all IEEE-required signals (TMS, TCK, TDI, and TDO), in addition to the optional

asynchronous reset signal NTRST.

The following illustration shows the TAP and boundary-scan architecture.

Figure 15. Test Access Port and Boundary-Scan Architecture

After a TAP reset, the Device Identification register is serially connected between TDI

and TDO by default. The TAP Instruction register is loaded either from a shift register

(when a new instruction is shifted in) or, if there is no new instruction in the shift

a valid code in the instruction register, and the problem of toggling instruction bits

during a shift is avoided. Unused codes are mapped to the BYPASS instruction.

3.13.8 JTAG Instruction Codes

The VSC8601 device supports the following instruction codes:

EXTEST Allows testing of off-chip circuitry and board-level interconnections by

sampling input pins and loading data onto output pins. Outputs are driven by the

contents of the boundary-scan cells, which have to be updated with valid values (with

the PRELOAD instruction) prior to the EXTEST instruction.

Boundary-Scan

Device Identification

Bypass Register

Instruction Register,

Instruction Decode,

Control

Test Access Port

Controller

NTRST

TMS

TDI

TCK

Select

Control

tdoenable

Control Mux,

DFF

TDO

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 35

SAMPLE/PRELOAD Allows a snapshot of inputs and outputs during normal system

operation to be taken and examined. It also allows data values to be loaded into the

boundary-scan cells prior to the selection of other boundary-scan test instructions.

IDCODE Provides the version number (bits 31:28), part number (bits 27:12), and the

manufacturer identity (bits 11:1) to be serially read from the device.

The following table provides information about the meaning of IDCODE binary values

stored in the device JTAG registers.

CLAMP Allows the state of the signals driven from the component pins to be

determined from the boundary -scan register while the bypass register is selected as the

serial path between TDI and TDO. While the CLAMP instruction is selected, the signals

driven from the component pins do not change.

HIGHZ Places the component in a state in which all of its system logic outputs are

placed in a high impedance state. In this state, an in-circuit test system may drive

signals onto the connections normally driven by a component output without incurring a

risk of damage to the component. This makes it possible to use a board where not all of

the components are compatible with the IEEE 1149.1 standard.

BYPASS The bypass register contains a single shift-register stage and is used to

provide a minimum-length serial path (one TCK clock period) between TDI and TDO to

bypass the device when no test operation is required.

The following table provides more information about the location and IEEE compliance

of the JTAG instruction codes used in the VSC8601.

Table 4. JTAG Device Identification Register Description

Description

Device Version

Number Model Number

Manufacturing

Identity LSB

Bit field 31 through 28 27 th rough 12 11 through 1 0

Binary value 0001 1000 0110 0000 0001 000 0111 0100 1

Table 5. JTAG Interface Instruction Codes

Instruction Code Selected Register

Width

IEEE 1149.1

Specification

EXTEST 0000 Boundary-scan 45 Mandatory

SAMPLE/PRELOAD 0001 Boundary-scan 45 Mandatory

IDCODE 0110 Device identification 32 Optional

CLAMP 0010 Bypass register 1 Optional

HIGHZ 0011 Bypass register 1 Optional

BYPASS 1111 Bypass register 1 Mandatory

RESERVED 0100, 0101,

0111, 1000-1110

VSC8601 Datasheet

Functional Descriptions

Revision 4.1

September 2009 Page 36

3.13.9 Boundary-Scan Register Cell Order

All inputs and outputs are observed in the boundary-scan register cells. All outputs are

additionally driven by the contents of boundary-scan register cells. Bidirectional pins

have all three related boundary-scan register cells: input, output, and control.

The complete boundary-scan cell order is av ailable as a BSDL file format on the Vitesse

Web site at www.vitesse.com.

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 37

4 Configuration

The VSC8601 device can be configured using thre e diff ere nt me thod s:

• Setting internal memory registers using the management interface.

• Setting a combination of CMODE pins and registers.

• Loading a configur ation into an external EEPROM and connecting that device so that

it writes configuration information at system startup.

4.1 Registers

This section provides information about how to configure the VSC8601 device using its

internal memory registers and the management interface. For information about

configuring the device using the CMODE pins, see “CMODE,” page 64. For information

about setting up an external EEPROM to perform startup configuration, see “EEPROM,”

page 66.

The following illustration shows the relationship between the device registers and their

address spaces.

Figure 16. Register Space Diagram

IEEE 802.3

Standard

Registers

Extended Page

Registers

Main

Registers

0x0000 0x0001

16E

17E

18E

19E

30E

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 38

4.1.1 Reserved Registers

For main registers 16 through 31 and extended page registers 16E through 30E, any

bits marked as “Reserved” should be processed as read only and their states as

undefined.

4.1.2 Reserved Bits

In writing to registers with reserved bits, use a “read-modify-then-write” technique,

where the entire register is read but only the intended bits to be changed are modified.

Reserved bits cannot be changed and their read state cannot be considered static or

unchanging.

4.2 IEEE Standard and Main Registers

In the VSC8601 device, the standard registers’ page space consists of the IEEE

standard registers and the Vitesse standard registers. The following table lists the

names of the registers associated with the addresses as dictated by the IEEE standard.

The following table lists the names of the registers in the main page space of the

device. These registers are accessible only when register address 31 is set to 0x0000.

Table 6. IEEE 802.3 Standard Registers

0Mode control

1Mode status

2 PHY identifier 1

3 PHY identifier 2

4 Auto-negotiation advertisement

5 Auto-negotiation link partner ability

6 Auto-negotiation expansion

7 Auto-negotiation next-page transmit

8 Auto-negotiation link partner next-page receive

9 1000BASE-T control

10 1000BASE-T status

11 Reserved

12 Reserved

13 Reserved

14 Reserved

15 1000BASE-T status extension 1

Table 7. Main Registers

16 100BASE-TX status extension

17 1000BASE-T status extension 2

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 39

4.2.1 Mode Control

The device register at memory address 0.00.15:0 controls several aspects of VSC8601

functionality. The following table lists the available bit settings in this register and what

they control.

18 Bypass control

19 Receive error counter

20 False carrier sense counter

21 Disconnect counter

22 Extended control and status

23 Extended PHY control 1

24 Extended PHY control 2

25 Interrupt mask

26 Interrupt status

27 LED control

28 Auxiliary control and status

29 Delay sk ew stat us

30 Reserved

31 Extended register page access

Table 8. Mode Control, Address 0 (0x00)

Bit Name Access Description Default

15 Software reset R/W This is a self-clearing bit that restores all

serial management inte rface (SMI) registers

to their default state, except for sticky and

super sticky bits.

1 = Reset asserted.

0 = Reset de-asserted.

You must wait 4 µs after setting this bit to

initiate another SMI register acce ss.

14 Loopback R/W 1 = Loopback enabled.

0 = Loopback disabled.

When loop back is enabled, the device

functions at the current speed setting and

with the current duplex mode setting (bit 8

of this register).

13, 6 Forced speed

selection R/W LSB = bit 13, MSB = bit 6.

00 = 10 Mbps.

01 = 100 Mbps.

10 = 1000 Mbps.

11 = Reserved.

12 Auto-negotiation

enable R/W 1 = Auto-negotiation enabled.

0 = Auto-negotiation disabled. 1

Table 7. Main Registers (continued)

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 40

4.2.2 Mode Status

The register at 1.01.15:0 in the device main registers space displays the currently

enabled mode setting. The following table lists possible readouts of this register.

11 Power-down R/W 1 = Power-down enabled.

If power-down is enabled, the RGMII’s

in-band signaling is disabled. When this bit

is set, RGMII in-band signaling does not

function.

10 Isolate R/W 1 = Disable MAC interface outputs and

ignore MAC interface inputs. 0

9Restart

auto-negotiation R/W This is a self-clearing bit.

1 = Restart auto-negotiation on media

interface.

8 Duplex R/W 1 = Full-duplex.

0 = Half-duplex. 0

7 Collision test enable R/W 1 = Collision test enabled. 0

6 MSB for speed

selection R/W See bit 13 above. 1

5:0 Reserved 000000

Table 9. Mode Status, Address 1 (0x01)

Bit Name Access Description Default

15 100BASE-T4

capability RO 1 = 100BASE-T4 capable. 0

14 100BASE-X FDX

capability RO 1 = 100BASE-X FDX capable. 1

13 100BASE-X HDX

capability RO 1 = 100BASE-X DDX capable. 1

12 10BASE-T FDX

capability RO 1 = 10BASE-T FDX ca pable. 1

11 10BASE-T HDX

capability RO 1 = 10BASE-T HDX capable. 1

10 100BASE-T2 FDX

capability RO 1 = 100BASE-T2 FDX capable. 0

9 100BASE-T2 HDX

capability RO 1 = 100BASE-T2 HDX capable. 0

8 Extended status

enable RO 1 = Extended status information present in

7 Reserved RO 0

6Preamble

suppression

capability

RO 1 = MF preamble may be suppressed.

0 = MF always required. 1

5 Auto-negotiation

complete RO 1 = Auto-negotiation complete. 0

Table 8. Mode Control, Address 0 (0x00) (continued)

Bit Name Access Description Default

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 41

4.2.3 Device Identification

All 16 bits in both register 2 and register 3 in the VSC8601 device are used to provide

information associated with aspects of the device identification. The following tables list

the possible readouts.

4.2.4 Auto-Negotiation Advertisement

The bits in address 4 in the main registers space control the VSC8601 device ability to

notify other devices of the status of its auto-negotiation feature. The following table

lists the available settings and readouts.

4 Remote fault R O Th is bit latc hes high.

1 = Far-end fault detected. 0

3 Auto-negotiation

capability RO 1 = Auto-negotiation capable. 1

2 Link status RO This bit latches low.

1 = Link is up. 0

1 Jabber detect RO This bit latches high.

1 = Jabber condition detected. 0

0 Extended capability RO 1 = Extended register capable. 1

Table 10. Identifier 1, Address 2 (0x02)

Bit Name Access Description Default

15:0 Organizationally

unique identifier

(OUI)

RO OUI most significant bits (3:18) 0x0007

Table 11. Identifier 2, Address 3 (0x03)

Bit Name Access Description Default

15:10 OUI RO OUI least sign ificant bits (19:2 4) 0x0001

9:4 Vitesse model

number RO VSC8601 000010

3:0 Devic e revision

number RO 0001

Table 12. Device Auto-Negotiation Advertisement, Address 4 (0x04)

Bit Name Access Description Default

15 Next page

transmission

request

R/W 1 = Re quest enabled 0

14 Reserved RO 0

13 Transmit remote

fault R/W 1 = Enabled 0

Table 9. Mode Status, Address 1 (0x01) (continued)

Bit Name Access Description Default

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 42

4.2.5 Link Partner Auto-Negotiation Capability

The bits in main register 5 enable you to determine if the Cat5 link partner (LP) used

with the VSC8601 device is compatible with the auto-negotiation functionality.

12 Reserved

technologies R/W 0

11 Advertise

asymmetric pause R/W 1 = Advertises asymmetric pause CMODE

10 Advertise symmetric

pause R/W 1 = Advertises symme tric pause CMODE

9Advertise

100BASE-T4 R/W 1 = Advertises 100BASE-T4 0

8Advertise

100BASE-TX FDX R/W 1 = Advertise 100BASE-TX FDX CMODE

7Advertise

100BASE-TX HDX R/W 1 = Advertises 100BASE-TX HDX CMODE

6Advertise

10BASE-T FDX R/W 1 = Advertises 10BASE-T FDX CMODE

5Advertise

10BASE-T HDX R/W 1 = Advertises 10BASE-T HDX CMODE

4:0 A dvertise selector R/W 00001

Table 13. Auto-Negotiation Link Partner Ability, Address 5 (0x05)

Bit Name Access Description Default

15 LP next page

transmission

request

RO 1 = Requested 0

14 LP acknowledge RO 1 = Acknowledge 0

13 LP remote fault RO 1 = Remote fault 0

12 Reserved RO 0

11 LP advertise

asymmetric pause RO 1 = Capable of asymmetric pause 0

10 LP advertise

symmetric pause RO 1 = Capable of symmetric pause 0

9LP advertise

100BASE-T4 RO 1 = Capable of 100BASE-T4 0

8LP advertise

100BASE-TX FDX RO 1 = Capable of 100BASE-TX FDX 0

7LP advertise

100BASE-TX HDX RO 1 = Capable of 100BASE-TX HDX 0

6LP advertise

10BASE-T FDX RO 1 = Capable of 10BASE-T FDX 0

5LP advertise

10BASE-T HDX RO 1 = Capable of 10BASE-T HDX 0

4:0 LP advertise selector RO 00000

Table 12. Device Auto-Negotiation Advertisement, Address 4 (0x04)

Bit Name Access Description Default

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 43

4.2.6 Auto-Negotiation Expansion

The bits in main register 6 work together with those in register 5 to indicate the status

of the LP auto-negotiation. The following table lists the available settings and readouts.

4.2.7 Transmit Auto-Negotiation Next Page

The settings in register 7 in the main registers space provide information about the

number of pages in an auto-negotiation sequence. The following table lists the settings

available.

Table 14. Auto-Negotiation Expansion, Address 6 (0x06)

Bit Name Access Description Default

15:5 Reserved RO 00000000000

4 Parallel detect ion

fault RO This bit la tches high.

1 = Parallel dete ction fault. 0

3 LP next page

capable RO 1 = LP is next page capable. 0

2 Local PHY next page

capable RO 1 = Local PHY is next page capable. 1

1 Page received RO This bit latches low.

1 = New page has been received. 0

0LP is

auto-negotiation

capable

RO 1 = LP is capable of auto-negotiation. 0

Table 15. Auto-Negotiation Next Page Transmit, Address 7 (0x07)

Bit Name Access Description Default

15 Next page R/W 1 = More pages follow 0

14 Reserved RO 0

13 Message page R/W 1 = Message page

0 = Unformatted page 1

12 Acknowledge 2 R/W 1 = Complies with request

0 = Cannot comply with request 0

11 Toggle RO 1 = Previous transmitted LCW = 0

0 = Previous transmitted LCW = 1 0

10:0 Message/unformatted

code R/W 00000000001

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 44

4.2.8 Auto-Negotiation Link Partner Next Page Receive

The bits in register 8 of the main register space work together with register 7 to

determine certain aspects of the LP auto-negotiation. The following table lists the

possible readouts.

4.2.9 1000BASE-T Control

The VSC8601 device’s 1000BASE-T functionality is controlled by the bits in register 9 of

the main register space. The following table lists the settings and readouts available.

Note Transmitter Test Mode (bits 15:13) operates in the manner described in IEEE

standard 802.3, section 40.6.1.1.2.

Table 16. Auto-Negotiation LP Next Page Receive, Address 8 (0x08)

Bit Name Access Description Default

15 LP next page RO 1 = More pages follow 0

14 Acknowledge RO 1 = LP acknowledge 0

13 LP message page RO 1 = Message page

0 = Unformatted page 0

12 LP Acknowledge 2 RO 1 = LP complies with request 0

11 LP toggle RO 1 = Previous transmitted LCW = 0

0 = Previous transmitted LCW = 1 0

10:0 LP message /

unformatted code RO 00000000000

Table 17. 1000BASE-T Control, Address 9 (0x09)

Bit Name Access Description Default

15:13 Transmitter

test mode R/W 000 = Normal.

001 = Mode 1: Transmit waveform test.

010 = Mode 2: Transmit jitter test as master.

011 = Mode 3: Transmit jitter test as slave.

100 = Mode 4: Transmitter distortion test .

101 to 111 = Reserved: Operation not defined.

000

12 Master/slave

manual

configuration

R/W 1 = Master/slave manual configuration enabled. 0

11 Master/slave

value R/W This register is only valid when bit 9.12 is set to 1.

1 = Configure PHY as master during negotiation.

0 = Configure PHY as slave during negotiation.

10 Port type R/W 1 = Multi-port device.

0 = Single-po rt device. 0

9 1000BASE-T

FDX capability R/W 1 = PHY is 1000BASE-T FDX capable. CMODE

8 1000BASE-T

HDX capability R/W 1 = PHY is 1000BASE-T HDX capable. CMODE

7:0 Reserved R/W 0x00

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 45

4.2.10 1000BASE-T Status

The bits in register 10 of the main register space allow you to read the status of the

1000BASE-T communications enabled in the device. The following table lists these

readouts.

4.2.11 Main Registers Reserved Addresses

In the VSC8601 device main registers page space, registers 11 through 15 (0x0B

through 0x0E) are reserved.

4.2.12 1000BASE-T Status Extension 1

1000BASE-T communications. The following table lists the readouts available.

Table 18. 1000BASE-T Status, Address 10 (0x0A)

Bit Name Access Description Default

15 Master/slave

configuration fault RO This bi t latches high.

1 = Master/slave configuration fault

detected.

0 = No master/slave configuration fault

detected.

14 Master/slave

configuration

resolution

RO 1 = Local PHY configuration resolved to

master.

0 = Local PHY configuration resolved to

slave.

13 Local receiver status RO 1 = Local receiver okay. 0

12 Remote receiver

status RO 1 = Remote receiver OK. 0

11 LP 1000BASE-T FDX

capability RO 1 = LP 1000BASE-T FDX capable. 0

10 LP 1000BASE-T HDX

capability RO 1 = LP 1000BASE-T HDX capable. 0

9:8 Reserved RO 00

7:0 Idle error count RO This is a self-clearing bit. 0x00

Table 19. 1000BASE-T Status Extension 1, Address 15 (0x0F)

Bit Name Access Description Default

15 1000BASE-X FDX

capability RO 1 = PHY is 1000BASE-X FDX capable 0

14 1000BASE-X HDX

capability RO 1 = PHY is 1000BASE-X HDX capable 0

13 1000BASE-T FDX

capability RO 1 = PHY is 1000BASE-T FDX capable 1

12 1000BASE-T HDX

capability RO 1 = PHY is 1000BASE-T HDX capable 1

11:0 Reserved RO 0x000

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 46

4.2.13 100BASE-TX Status Extension

information about the status of the device’s 100BASE-TX operation.

4.2.14 1000BASE-T Status Extension 2

The second status extension register is at address 17 in the device main registers

space. It provides information about another set of parameters associated with

1000BASE-T communications. For information about the first status extension register,

see Table 20, page 46. The following table lists the settings available.

Table 20. 100BASE-TX Status Extension, Address 16 (0x10)

Bit Name Access Description Default

15 100BASE-TX

descrambler RO 1 = Descrambler locked. 0

14 100BASE-TX lock

error RO This is a self-clearing bit.

1 = Lock error detected. 0

13 100BASE-TX

disconnect state RO This is a self-clearing bit.

1 = PHY 100BASE-TX link disconnect

detected.

12 100BASE- TX current

link status RO 1 = PHY 100BASE-TX link active. 0

11 100BASE- TX receive

error RO This is a self-clearing bit.

1 = Receive error detected. 0

10 100BASE-TX

transmit error RO This is a self-clearing bit.

1 = Transmit error detected. 0

9 100BASE-TX SSD

error RO This is a self-clearing bit.

1 = Start-of-stream delimiter error detected. 0

8 100BASE-TX ESD

error RO This is a self-clearing bit.

1 = End-of-stream delimiter error detected. 0

7:0 Reserved RO

Table 21. 1000BASE-T Status Extension 2, Address 17 (0x11)

Bit Name Access Description Default

15 1000BASE-T

descrambler RO 1 = Descrambler locked. 0

14 1000BASE-T lock

error RO This is a self-clearing bit.

1 = Lock error detected. 0

13 1000BASE-T

disconnect state RO This is a self-clearing bit.

1 = PHY 1000BASE-T link disconnect

detected.

12 1000BASE- T c urrent

link status RO 1 = PHY 1000BASE-T link active. 0

11 1000BASE-T receive

error RO This is a self-clearing bit.

1 = Receive error detected. 0

10 1000BASE-T

transmit error RO This is a self-clearing bit.

1 = Transmit error detected. 0

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 47

4.2.15 Bypass Control

The bits in the Bypass Control register in the VSC8601 device control aspects of

functionality in effect when the device is disabled so that traffic can bypass it in your

design. The following table lists the settings available.

9 1000BASE-T SSD

error RO This is a self-clearing bit.

1 = Start -of-stream delimiter error det ected. 0

8 1000BASE-T ESD

error RO This is a self-clearing bit.

1 = End-of-stream delimiter error detected. 0

7 1000BASE-T carrier

extension error RO This is a self-clearing bit.

1 = Carrier extension error detected. 0

6 Non-compliant

BCM5400 detected RO 1 = Non-compliant BCM5400 detected. 0

5 MDI crossover error RO 1 = MDI crossover error detected. 0

4:0 Reserved RO

Table 22. Bypass Control, Address 18 (0x12)

Bit Name Access Description Default

15 Transmit disable R/W 1 = PHY transmitter disabled. 0

14:9 Reserved RO

8 1000BASE-T

transmitter test

clock

R/W 1 = Enabled. 0

7 Force non-compliant

BCM5400 detection R/W This is a sticky bit.

1 = Force non-compliant BCM5400

detection.

6 Non-compliant

BCM5400 detection

disable

R/W This is a sticky bit.

1 = Non-compliant BCM5400 detection

disable.

5 Disable pair swap

correction R/W This is a sticky bit.

1 = Disable the automatic pair swap

correction.

4 Disable polarity

correction R/W This is a sticky bit.

1 = Disable polarity inversion correction on

each subchannel.

3 Parallel detect

control R/W This is a sticky bit.

1 = Do not ignore advertised ability.

0 = Ignore advertised ability.

2 Reserved RO

1 Disable automatic

1000BASE-T next

page exchange

R/W This is a sticky bit.

1 = Disable automatic 1000BASE-T next

page exchanges.

0CLKOUT output

enable R/W This is a sticky bit.

1 = Enable clock output pin. CMODE

Table 21. 1000BASE-T Status Extension 2, Address 17 (0x11) (continued)

Bit Name Access Description Default

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 48

Note If bit 1 is set to 1 in this register, automatic exchange of next pages is disabled,

and control is returned to the user through the SMI after the base page is exchanged.

The user then must send the correct sequence of next pages to the link partner,

determine the common capabilities, and force the device into the correct configuration

following the successful exchange of pages.

4.2.16 Receive Error Counter

The following table lists the readouts you can expect.

4.2.17 False Carrier Sense Counter

The following table lists the readouts you can expect.

Table 23. Receive Error Counter, Address 19 (0x13)

Bit Name Access Description Default

15:8 Reserved RO 00000000

7:0 Receive error

counter RO This is a self-clearing bit.

Counts the numbe r of non-collision

packets with rece i ve errors since last

read. Each time th e PHY detects a

non-collision packet containing at least

one error, these bits are incremented.

The counter stops counting at 0FFh.

This register is cleared only when read,

or upon either a hardware or software

reset. These bits are valid only in

100BASE-TX and 1000BASE-T modes.

00000000

Table 24. False Carrier Sense Counter, Address 20 (0x14)

Bit Name Access Description Default

15:8 Reserved RO 00000000

7:0 False carrier

sense counter RO This is a self-clearing bit.

Counts the number of false carrier

events since last read. The PHY

increments these bits each time it

detects a false carrier on the receive

input. The counter stops count ing at

0FFh.

This register is cleared only when read,

or upon either a hardware or software

reset. These bits are valid only in

100BASE-TX and 1000BASE-T modes.

00000000

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 49

4.2.18 Disconnect Counter

The following table lists the readouts you can expect.

4.2.19 Extended Control and Status

The bits in register 22 provide additional device control and readouts. The following

table lists the settings available.

The following information applies to the extended control and status bits:

• When bit 15 is set, the link integrity state machine is bypassed and the PHY is

forced into a link pass status.

Table 25. Disconnect Counter, Address 21 (0x15)

Bit Name Access Description Default

15:8 Reserved RO 00000000

7:0 Disconnect

counter RO This is a self-clearing bit.

Counts the numbe r of non-collision

packets wi th receive errors after the l ast

read. The PHY increments these bits

each time the Carrier Integrity Monitor

(CIM) enters the link unstable state. The

counter stops counting at 0FFh. This

upon a hardware or software reset.

00000000

Table 26. Extended Control and Status, Address 22 (0x16)

Bit Name Access Description Default

15 Force 10BASE-T

link high R/W This is a sticky bit.

1 = Bypass link integrity test.

0 = Enable link integrity test.

14 Jabber detect

disable R/W This is a sticky bit.

1 = Disable jabber detect. 0

13 Disable 10BASE- T

echo R/W This is a sticky bit.

1 = Disable 10BASE-T echo. 1

12 SQE disable mode R/W 1 = Disable SQE transmit. 1

11:10 10BASE-T squelch

control R/W This is a sticky bit.

00 = Normal squelch.

01 = Low squelch.

10 = High squelch.

11 = Reserv e d .

9 Reserved

8 EOF Error RO This bit is self-clearing.

1 = EOF error detected. 0

710BASE-T

disconnect state RO This bit is self-clearing.

1 = 10BASE-T link disconnect detected. 0

610BASE-T link

status RO 1 = 10BASE-T link active. 0

5:0 Reserved RO

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 50

• When bits 11:0 are set to 00, the squelch threshold levels are based on the IEEE

standard for 10BASE-T. When set to 01, the squelch level is decreased, which may

improve the bit error rate performance on long loops. When set to 10, the squelch

level is increased and may improve the bit error rate in high-noise environments.

4.2.20 Extended PHY Control Set 1

The bits in the extended control set control the MAC auto-negotiation functioning,

SGMII alignment errors, and EEPROM status. The following table lists the available

settings.

Note After configuring bit 12 of the extended PHY control register set 1, a software

reset (register 0, bit 15) must be written to change the device operating mode. Bit 1

allows for flexibility in printed circuit board lay outs because it can reorder the TXD pins.

4.2.21 Extended PHY Control Set 2

The second set of extended controls is located in register 24 in the main register space

for the device. The following table lists the settings and readouts available.

Table 27. Extended PHY Control 1, Address 23 (0x17)

Bit Name Access Description Default

15:9 Reserved RO

8 RGMII skew timing

compensation

enable

R/W This is a sticky bit.

0 = Disabled.

1 = Adds 2 ns delay to the RX_CLK and

TX_CLK pins.

CMODE

7:6 Reserved RO

5ActiPHY mode

enable R/W This is a sticky bit.

1 = Enabled. CMODE

4:1 Reserved RO

0 Reserved RO

Table 28. Extended PHY Control 2, Address 24 (0x18)

Bit Name Access Description Default

15:13 100BASE-TX edge

rate control R/W This is a sticky bit.

011 = +5 Edge rate (slowest).

010 = +4 Edge rate.

001 = +3 Edge rate.

000 = +2 Edge rate.

111 = +1 Edge rate.

110 = Default edge rate.

101 = –1 Edge rate.

100 = –2 Edge rate (fastest).

110

12:4 Reserved RO

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 51

4.2.22 Interrupt Mask

The bits in register 25 control the device interrupt mask. The following table lists the

settings available.

Note When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this

pin reflects the state of bit 26.15. Clearing this bit only inhibits the MDINT pin from

being asserted.

3:1 Cable length status RO The following are approximate lengths:

000 = < 10 m.

001 = 10—20 m.

010 = 20—40 m.

011 = 40—80 m.

100 = 80—100 m.

101 = 100—140 m.

110 = 140—180 m.

111 = >180 m.

000

0 1000BASE-T

connector loopback R/W 1 = Enabled. 0

Table 29. Interrupt Mask, Address 25 (0x19)

Bit Name Access Description Default

15 MDINT interrupt status enable R/W This is a sticky bit.

1 = Enabled. 0

14 Speed state change mask R/W This is a sticky bit.

1 = Enabled. 0

13 Link state change mask R/W This is a sticky bit.

1 = Enabled. 0

12 FDX state change mask R/W This is a sticky bit.

1 = Enabled. 0

11 Auto-negotiation error mask R/W 1 = Enabled. 0

10 Auto-negotiation complete mask R/W This is a sticky bit.

1 = Enabled. 0

9 Inline powered device detect mask R/W This is a sticky bit.

1 = Enabled. 0

8:3 Reserved RO

2 Link speed downshift detect mask R/W This is a sticky bit.

1 = Enabled. 0

1 Master/Slave resolution erro r mask R/W This is a sticky bit.

1 = Enabled. 0

0 Reserved RO

Table 28. Extended PHY Control 2, Address 24 (0x18) (continued)

Bit Name Access Description Default

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 52

4.2.23 Interrupt Status

The status of interrupts already written to the device are available for reading from

expect.

The following information applies to the interrupt status bits:

• All set bits in this register are cleared after being read (self-clearing). If bit 26.15 is

set, the cause of the interrupt can be read by reading bits 26.14:0.

• For bits 26.14 and 26.12, bit 0.12 must be set for this interrupt to assert.

• For bit 26.2, bits 4.8:5 must be set for this interrupt to assert.

4.2.24 LED Control

If you are using the simple LED method of control, you can control the LEDs using the

following settings. If you are using the enhanced LED method, there are different

settings, see “Enhanced LED Method Select,” page 56.

Table 30. Interrupt Status, Address 26 (0x1A)

Bit Name Access Description Default

15 Interrupt status RO This is a self-clearing bit.

1 = Interrupt pending. 0

14 Speed state change statu s RO This is a self-clearing bit.

1 = Interrupt pending. 0

13 Lin k state change status RO This is a self-clearing bit.

1 = Interrupt pending. 0

12 FDX state change status RO This is a self-clearing bit.

1 = Interrupt pending. 0

11 Auto-negotiation error status RO This is a self-clearing bit.

1 = Interrupt pending.

10 Auto-negotiation complete status RO This is a self-clearing bit.

1 = Interrupt pending. 0

9 Inline powered device detect status RO This is a self-clearing bit.

1 = Interrupt pending. 0

8:3 Reserved RO

2 Link speed downshift detect status RO This is a self-clearing bit.

1 = Interrupt pending. 0

1 Master/Slave resolution error status RO This is a self-clearing bit.

1 = Interrupt pending. 0

0 Reserved RO

Table 31. LED Control, Address 27 (0x1B)

Bit Name Access Description Default

15:14 Reserved RO

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 53

4.2.25 Auxiliary Control and Status

The following table lists the settings available.

13 Link 100 LED force on (LED2 pin) R/W This is a sticky bit.

1 = Forced on.

0 = Default.

12 Link 100 LED disab le (LED2 pin) R/W This is a sticky bit.

1 = Disabled.

0 = Default.

11 Link 1000 LED force on (LED1 pin) R/W This is a sticky bit.

1 = Forced on.

0 = Default.

10 Link 1000 LED disable (LED1 pin) R/W This is a sticky bit.

1 = Disabled.

0 = Default.

9:8 Reserved RO

7 Activity LED force on (LED0 pin) R/W This is a sticky bit.

1 = Forced on.

0 = Default.

6 Activity LED disable (LED0 pin) R/W This is a sticky bit.

1 = Disabled.

0 = Default.

5:4 Reserved RO

3 LED pulse enable RW This is a sticky bit.

0 = Normal operation.

1 = LEDs pulse with a

5KHz, 20% duty cycle

when active.

2 Activity LED blink enable RW This is a sticky bit.

1 = Enable. 0

1 Activity LED blink rate RW This is a sticky bit.

1 = 10 Hz blink rate.

0 = 5 Hz blink rate.

0Reserved RO

Table 32. Auxiliary Control and Status, Address 28 (0x1C)

Bit Name Access Description Default

15 Auto-negotiation complete RO Duplicate of bit 1.5. 0

14 Auto-negotiation disabled RO Inverted duplicate of bit 0.12. 0

13 MDI/MDI-X crossover

indication RO 1 = MDI/MDI-X crossover

performed internally. 0

12 CD pair swap RO 1 = CD pairs are swapped. 0

11 A polarity inversion RO 1 = Polarity swap on pair A. 0

10 B polarity inversion RO 1 = Polarity swap on pair B. 0

9 C polarity inversion RO 1 = Polarity swap on pair C. 0

Table 31. LED Control, Address 27 (0x1B) (continued)

Bit Name Access Description Default

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 54

4.2.26 Delay Skew Status

The following table lists the settings available.

4.2.27 Reserved Address Space

The bits in register 30 (0x1E) are reserved.

8 D polarity inversion RO 1 = Polarity swap on pair D. 0

7:6 Reserved RO

5 FDX status RO 1 = Full duplex.

0 = Half duplex. 0

4:3 Speed status RO 00 = Speed is 10BASE-T.

01 = Speed is 100BASE-TX.

10 = Speed is 1000BASE-T.

11 = Reserved.

2Reserved RO

1 Sticky Reset Enable R/W This is a super-sticky bit.

1 = Enabled. When enabled, all MII

their values during a software

reset.

0 = Disabled. When disabled, all

MII register bits listed as sticky

change to their default values

during a software reset.

Note that bits listed as super sticky

retain their values during a

software reset regardless of this

setting.

0Reserved RO

Table 33. Delay Skew Status, Address = 29 (0x1D)

Bit Name Access Description Default

15 Reserved RO

14:12 Pair A delay skew RO Skew in integral symbol times 000

11 Reserved RO

10:8 Pair B delay skew RO Skew in integral symbol times 000

7 Reserved RO

6:4 Pair C delay skew RO Skew in integral symbol times 000

3 Reserved RO

2:0 Pair D delay skew RO Skew in integral symbol times 000

Table 32. Auxiliary Control and Status, Address 28 (0x1C) (continued)

Bit Name Access Description Default

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 55

4.3 Extended Page Registers

To provide functionality beyond the IEEE802.3-specified 32 registers and main device

registers, the VSC8601 device includes an extended set of registers that provide an

additional 15 register spaces.

To access the extended page registers (16E through 30E), enable extended register

access by writing 0x0001 to register 31. For more information, see Table 35, page 56.

When extended page register access is enabled, reads and writes to registers 16

through 30 affect the extended registers 16E through 30E instead of those same

registers in the IEEE-specified register space. Registers 0 through 15 are not affected

by the state of the extended page register access.

Writing 0x0000 to register 31 restores the normal register access.

The following table lists the addresses and register names in the extended register

page space. These registers are accessible only when the device register 31 is set to

0x0001.

Table 34. Extended Registers Page Space

16E Enhanced LED method select

17E Enhanced LED behavior

18E CRC good counter

19E MAC resistor c a libration control

20E Extended PHY control 3

21E EEPROM interface status and control

22E EEPROM data read or write

23E Extended PHY control 4

24E Reserved

25E Reserved

26E Reserved

27E Extended PHY control 5

28E RGMII skew control

29E Ethernet packet generator (EPG) 1

30E Ethernet packet generator (EPG) 2

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 56

4.3.1 Extended Page Access

The register at address 31 controls the access to the extended page registers for the

VSC8601 device. The following table lists the settings available.

4.3.2 Enhanced LED Method Select

If you are using the enhanced LED method of control, you can control the LEDs using

the following settings. If you are using the simple LED method, there are different

see “LED Control,” page 52.

The following table shows the LED functional modes that can be programmed into any

of the device’ s LED outputs. F or more inform ation about accessing or reading the status

of the outputs, see Table 36, page 56.

Table 35. Extended Page Access, Address 31 (0x1F)

Bit Name Access Description Default

15:0 Extended page

accesses main register space

0x0001 = MII register 16 through 30

accesses extended register space

0x0000

Table 36. Enhanced LED Method Select, Address 16E (0x10)

Bit Name Access Description Default

15:12 Reserved RO

11:8 LED2 mode select R/W This is a sticky bit.

Select from LED modes 0-15 listed below. 0010

7:4 LED1 mode select R/W This is a sticky bit.

Select from LED modes 0-15 listed below. 0001

3:0 LED0 mode select R/W This is a sticky bit.

Select from LED modes 0-15 listed below. 1010

Table 37. Available LED Mode Settings

Mode Bit Setting LED Indicates

0 0000 Link/Activity

1 0001 Link1000/Activity

2 0010 Link100/Activity

3 0011 Link10/Activity

4 0100 Link100/1000/Activity

5 0101 Link10/1000/Activity

6 0110 Link10/100/Activity

7 0111 Reserved

8 1000 Duplex/Collision

9 1001 Collision

10 1010 Activity

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 57

4.3.3 Enhanced LED Behavior

The following table lists the settings available.

11 Reserved

12 1100 Autoneg_Fault

13 Reserved

14 1110 Force LED off

15 1111 Force LED on

Table 38. Enhanced LED Behavior, Address 17E (0x11)

Bit Name Access Description Default

15:13 Reserved RO

12 LED pulsing enable R/W This is a sticky bit .

0 = Normal operation.

1 = LEDs pulse with a 5 KHz, 20% duty cycle

when active.

11:10 LED b link /

pulse-stretch rate R/W This is a sticky bit.

00 = 2.5 Hz blink rate / 400 ms

pulse-stretch.

01 = 5 Hz blink rate / 200 ms pulse-stretch.

10 = 10 Hz blink rate / 100 ms pulse-stretch.

11 = 20 Hz blink rate / 50 ms pulse-stretch.

9:8 Reserved RO

7LED2 pulse-stretch /

blink select R/W This is a sticky bit.

1 = Pulse-stretch.

0 = Blink.

6LED1 pulse-stretch /

blink select R/W This is a sticky bit.

1 = Pulse-stretch.

0 = Blink.

5LED0 pulse-stretch /

blink select R/W This is a sticky bit.

1 = Pulse-stretch.

0 = Blink.

4 LED mode R/W This is a sticky bit.

1 = Enhanced LED method (controlled by MII

0 = Simple LED method (controlled by MII

3 Reserved RO

2LED2 combine

feature disable R/W This is a sticky bit.

0 = Combine enabled (Link/Activity,

Duplex/Collision).

1 = Disable Combination (Link only, Duplex

only).

Table 37. Available LED Mode Settings (continued)

Mode Bit Setting LED Indicates

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 58

Note Bit 4 must be set to 1 before register 16E and 17E are enabled for enhanced

LED control. If set to 0, then the LED features in 16E and 17E are not relevant. If set to

1, then the LED features in register 27 are not relevant.

4.3.4 CRC Good Counter

number of CRC routines that have executed successfully. The following table lists the

possible readouts.

4.3.5 MAC Resistor Calibration Control

The following table lists the settings available.

1LED1 combine

feature disable R/W This is a sticky bit.

0 = Combine enabled (Link/Activity,

Duplex/Collision).

1 = Disable Combination (Link only, Duplex

only).

0LED0 combine

feature disable R/W This is a sticky bit.

0 = Combine enabled (Link/Activity,

Duplex/Collision).

1 = Disable Combination (Link only, Duplex

only).

Table 39. CRC Good Counter, Address 18E (0x12)

Bit Name Access Description Default

15 Packet since last

read RO This is a self-clearing bit.

1 = Packet received since last read. 0

14 Reserved RO

13:0 CRC good counter

contents RO This is a self-clearing bit.

Counter containing the number of packets

with valid CRCs. This counter does not stop

counting and will roll over.

0x000

Table 40. MAC Resistor Calibration Control, Address 19E (0x13)

Bit Name Access Description Default

15:14 MAC resistor

calibration control

setting

R/W This is a sticky bit.

00 = 50 Ω.

01 = 60 Ω.

10 = 30 Ω.

11 = 45 Ω.

CMODE

13:0 Reserved RO

Table 38. Enhanced LED Behavior, Address 17E (0x11) (continued)

Bit Name Access Description Default

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 59

4.3.6 Extended PHY Control 3

CLKOUT signal, and its link speed downshifting feature. The following table lists the

settings available.

4.3.7 EEPROM Interface Status and Control

a startup EEPROM into your design.

Table 41. Extended PHY Control 3, Address 20E (0x14)

Bit Name Access Description Default

15 Reserved RO

14:13 ActiPHY sleep timer R/W This is a sticky bit.

00 = 1 second.

01 = 2 seconds.

10 = 3 seconds.

11 = 4 seconds.

12:11 Reserved RO

10:9 ActiPHY link status

time-out control R/W 00 = 1 second.

01 = 2 second.

10 = 3 second.

11 = 4 second.

8:6 Reserved RO

5MAC RX_CLK

Disable R/W 1 = RX _CLK is held low.

0 = RX_CLK is in normal operation. 0

4 Enable link speed

auto-downshift

feature

R/W This is a sticky bit.

1 = Enable auto link speed downshift from

1000BASE-T.

CMODE

3:2 L ink speed

auto-downshift

control

R/W This is a sticky bit.

00 = Downshift after two failed 1000BASE-T

auto-negotiation attempts.

01 = Downshift after three fai led 1000BASE-T

auto-negotiation attempts.

10 = Downshift after four failed 1000BASE-T

auto-negotiation attempts.

11 = Downshift after five failed 1000BASE-T

auto-negotiation attempts.

1Link speed

auto-downshift

status

RO 0 = No downshift.

1 = Downshift is required or has occurred. 0

0 Reserved RO

Table 42. EEPROM Interface Status and Control, Address 21E (0x15)

Bit Name Access Description Default

15 Reserved RO

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 60

4.3.8 EEPROM Data Read/Write

external EEPROM in your design. The following table lists the writes needed to obtain

the data from the external device.

4.3.9 Extended PHY Control 4

The register at address 23E consists of the fourth set bits that control various aspects

of inline powering and the CRC error counter in the VSC8601 device.

14 Re-read EEPROM

after software reset R/W This is a s uper-sticky bit.

1 = Contents of EEPROM to be re-read

after software reset.

13 Enable EEPROM

access R/W This is a self-clearing bit.

1 = Execute read or write EEPROM

based on the settings of register 21E,

bit 12.

12 EEPROM read or

write R/W 1 = Read from EEPROM.

0 = Write to EEPROM. 1

11 EEPROM ready RO 1 = EEPROM is ready for read or

write. 1

10:0 EEPROM address R/W Sets the address of the EEPROM to

which the read or write is to be

directed.

00000000000

Table 43. EEPROM Read or Write, Address 22E (0x16)

Bit Name Access Description Default

15:8 EEPROM read data RO Eight-bit data read from EEPROM;

requires setting register 21E, bit 13. 0x00

7:0 EEPROM write data R/W Eight-bit data to be written to EEPROM. 0x00

Table 44. Extended PHY Control 4, Address 23E (0x17)

Bit Name Access Description Default

15:11 PHY address RO PHY address; latched on reset. CMODE

10 Inline powered

device detection R/W This is a sticky bit.

1 = Enabled. 0

9:8 Inline powered

device detection

status

RO 00 = Searching for devices.

01 = Device found; requires inline power.

10 = Device found; does not require

inline power.

11 = Reserved.

Table 42. EEPROM Interface Status and Control, Address 21E (0x15)

Bit Name Access Description Default

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 61

Note Bits 9:8 are only valid if bit 10 is set.

4.3.10 Reserved Extended Registers

The bits in the extended register page space at addresses 24E, 25E, and 26E (0x18,

0x19, and 0x1A , res p e c ti vely) are res e rved.

4.3.11 Extended PHY Control 5

The following table lists the settings available.

7:0 CRC error counter RO This is a self-clearing bit.

CRC error counter for the Ethernet pack et

generator. T he value saturates a t 0xFF

and subsequently clears when read and

restarts count.

0x00

Table 45. Extended PHY Control 5, Address 27E (0x1B)

Bit Name Access Description Default

15 HP Auto-MDIX in

forced 10/100 R/W This is a sticky bit.

1 = Disabled.

For more information about HP Auto-MDIX,

see “Automatic Crossover and Polarity

Detection,” page 20.

14 Reserved RO

13:12 CRS behavior

control R/W This is a sticky bit.

Controls the CRS Behavior. The effect of

each setting depends on whether it is

half-duplex or full-duplex operation.

For half-duplex operation:

00: CRS = RX_DV + TX_EN

01: CRS = RX_DV + TX_EN

10: CRS = RX_DV

11: CRS = RX_DV.

For full-duplex operation:

00: CRS = RX_DV

01: CRS = 0

10: CRS = RX_DV

11: CRS = 0.

11 EEPROM present RO 1 = Configuration EEPROM detected on the

EECLK and EEDAT pin s. 0

10 Far End loopback

mode R/W 1 = Enabled. 0

9 PICMG 2.16 reduced

power mode R/W This is a sticky bit.

1 = Enabled. 0

Table 44. Extended PHY Control 4, Address 23E (0x17) (continued)

Bit Name Access Description Default

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 62

4.3.12 RGMII Skew Control

The following table lists the settings available.

8:6 100BASE-TX

transmitter

amplitude control

R/W This is a sticky bit.

011 = Reserved.

010 = +4 amplitude setting (largest).

001 = +3 amplitude setting.

000 = +2 amplitude setting.

111 = +1 amplitude setting.

110 = Default amplitude.

101 = –1 amplitude setting.

100 = –2 amplitude setting (smallest).

110

5:3 1000BASE-T

transmitter

amplitude control

R/W This is a sticky bit.

011 = Reserved.

010 = +2 amplitude setting (largest).

001 = +1 amplitude setting.

000 = Default amplitude.

111 = –1 amplitude setting.

110 = –2 amplitude setting.

101 = –3 amplitude setting.

100 = –4 amplitude setting (smallest)

000

2:0 1000BASE-T edge

rate control R/W This is a sticky bit.

011 = +4 edge rate (slowest).

010 = +3 edge rate.

001 = +2 edge rate.

000 = +1 edge rate.

111 = default edge rate.

110 = –1 edge rate.

101 = –2 edge rate.

100 = –3 edge rate (fastest)

111

Table 46. RGMII Skew Control, Address 28E (0x1C)

Bit Name Access Description Default

15:14 RGMII TX skew

compensation

enable

R/W This is a sticky bit.

00 = 0 ns.

01 = 1.4 ns.

10 = 1.7 ns.

11 = 2.0 ns.

CMODE

13:12 RGMII RX skew

compensation

enable

R/W This is a sticky bit.

00 = 0 ns.

01 = 1.4 ns.

10 = 1.7 ns.

11 = 2.0 ns.

CMODE

11:10 Jumbo packet mode R/ W Thi s is a sticky bit.

00 = Normal IEEE 1.5 kB packet length .

01 = Normal IEEE 9 kB packet length.

10 = Normal IEEE 12 kB packet length.

11 = Normal IEEE 16 kB packet length.

9 10BASE-T no

preamble mode R/W Thi s is a sticky bit.

1 = Enabled, no preamble required.

0 = Disabled, preamble required.

Table 45. Extended PHY Control 5, Address 27E (0x1B) (continued)

Bit Name Access Description Default

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 63

4.3.13 Ethernet Packet Generator (EPG) Control 1

The EPG control register provides access to and control of va rious aspects of the EPG

testing feature. There are two, separate EPG control registers. The following table lists

the setting available in the first register.

The following information applies to the EPG control number 1:

• Do not run the EPG when the VSC8601 device is connected to a live network.

• Bit 29E.13 (Continuous EPG mode control): When enabled, this mode causes the

device to send continuous packets. When disabled, the device continues to send

packets only until it reaches the next 10,000-packet increment mark. It then

ceases to send packets.

• The six-byte destination address in bits 9:6 is assigned one of 16 addresses in the

range of 0xFF FF FF FF FF F0 through 0xFF FF FF FF FF FF.

• The six-byte source address in bits 5:2 is assigned one of 16 addresses in the range

of 0xFF FF FF FF FF F0 through 0xFF FF FF FF FF FF.

• If any of bits 13:0 are changed while the EPG is running (bit 14 is set to 1), bit 14

must be cleared and then set back to 1 for the change to take effect and to restart

the EPG.

8:0 Reserved RO

Table 47. EPG Control Register 1, Address 29E (0x1D)

Bit Name Access Description Default

15 E PG enable R/W 1 = Enable EPG 0

14 EPG run or stop R/W 1 = Run EPG 0

13 Transmission

duration R/W 1 = Continuous (sends in 10,000-packet

increments)

0 = Send 30,000,000 packets and stop

12:11 Packet length R/W 00 = 125 bytes

01 = 64 bytes

10 = 1518 bytes

11 = 10,000 bytes (Jumbo packet)

10 Inter-packet gap R/W 1 = 8,192 ns

0 = 96 ns 0

9:6 Destina tion address R/W Lowest nibble of the six-byte destination

address 0001

5:2 Source address R /W Lowest nibble of the six-byte destination

address 0000

1 Payload type R/W 1 = Randomly generated payload pattern

0 = Fixed based on payload pattern 0

0 Bad frame check

sequence (FCS)

generation

R/W 1 = Generate packets with bad FCS

0 = Generate packets with good FCS 0

Table 46. RGMII Skew Control, Address 28E (0x1C) (continued)

Bit Name Access Description Default

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 64

4.3.14 Ethernet Packet Generator Control 2

The register at address 30E consists of the second of bits that provide access to and

control over various aspects of the EPG testing feature. For information about the first

set of EPG control bits, see Table 47, page 63. The following table lists the settings

available.

Note If any of bits 15:0 in this register are changed while the EPG is running (bit 14

of register 29E is set to 1), that bit (29E.14) must first be cleared and then set back to

1 for the change to take effect and to restart the EPG.

4.4 CMODE

The information in this section consists of a detailed description of the methods to

configure the VSC8601 device using its CMODE pins. It includes descriptions of the

registers that work together with the CMODE pins to control the device function.

There are four configuration mode (CMODE) pins on the VSC8601 device. For more

information about the physical location of the CMODE pins, see “Pin Descriptions,”

page 84. Each CMODE pin maps to a configuration bit, which means there are 16

possible settings for the device.

4.4.1 CMODE Pins and Related Functions

The following table lists the pin numbers and device functionality that is controlled by

each configuration bit.

Table 48. EPG Control Register 2, Address 30E (0x1E)

Bit Name Access Description Default

15:0 EPG packet payload R/W Data pattern repeated in the payload of

packets generated by th e EPG 0x00

Table 49. CMODE Configuration Pins and Device Functions

CMODE Pin Bit 3 (MSB) Control Bit 2 Controls Bit 1 Controls Bit 0 (LSB) Controls

3 PHY address [3] PHY address [4] MAC calibration

setting[1] MAC calibration

setting[0]

2 PHY address [2] ActiPHY RGMII clock skew[1] RGMII clock skew[ 0]

1 PHY address [1] Link speed downshift Speed/Duplex Modes

[1] Speed/Duplex modes [0]

0 PHY address [0] CLKOUT enable Advertise asymmetric

pause Advertise sym met ric

pause

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 65

4.4.2 Functions and Related CMODE Pins

The following table lists the pin and bit settings according to the device function and

CMODE pin used to configure it.

4.4.3 CMODE Resistor Values

To affect the VSC8601 device configur ation, find the par a meter in Table 49, page 64 or

in Table 50, page 65 , and connect the associated pin to the resistor specified in the

following table. This sets the bits as shown.

Table 50. Device Functions and Associated CMODE Pins

Function

CMODE

Pin Bit

Associated

PHY Address

[4:0] 3 to 0 3 and 2 Sets the PHY address.

Link speed

downshift 1 2 Register 20E,

bit 4 0 = Link only according to t he auto-negotiation

resolution.

1 = Enable link speed downshift feature.

Speed and

duplex 1 1 and 0 Register 4,

bits 8:5 and

bits 9:8

00 = 10/100/1000BASE-T FDX/HDX.

01 = 10/100/1000BASE-T FDX; 10/100BASE-T HDX.

10 = 1000BASE-T FDX only.

11 = 10/100BASE-T FDX/HDX.

RGMII clock

skew 2 1 and 0 Register 23,

bit 8 00 = No skew on RX_CLK and TX_CLK.

01 = 1.4 ns skew on RX_CLK and TX_CLK.

10 = 1.7 ns skew on RX_CLK and TX_CLK.

11 = 2.0 ns skew on RX_CLK and TX_CLK.

Advertise

asymmetric

pause

01Register 4,

bit 11 0 = Not advertised.

1 = Advertised.

Advertise

symmetric

pause

00Register 4,

bit 10 0 = Not advertised.

1 = Advertised.

CLKOUT enable 0 2 Register 18,

bit 0 0 = Disabled.

1 = Enabled.

ActiPHY 2 2 Register 23,

bit 5 0 = Disabled.

1 = Enabled.

MAC resistor

calibration

setting

3 1 and 0 Register 19E,

bits 15:14 00 = 50 Ω.

01 = 60 Ω.

10 = 30 Ω.

11 = 45 Ω.

Table 51. CMODE Resistor Values and Resultant Bit Settings

With CMODE

Pin Tied To

With 1%

Resistor

Value

Set

Bit 3 (MSB) to:

Set

Bit 2 to:

Set

Bit 1 to:

Set

Bit 0 (LSB) to:

VSS 0 0 0 0 0

VSS 2.26 kΩ0001

VSS 4.02 kΩ0010

VSS 5.90 kΩ0011

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 66

Using resistors with the CMODE pins can be optional in designs that access the device’ s

MDC/MDIO pins. In designs that do this, all configurations otherwise affected on the

device by using the CMODE pins can be changed using the regular device register

settings, and all the CMODE pins can be pulled to VSS (ground). However, the

PHYADDR [4:0] still requires CMODE configuration.

4.5 EEPROM

The VSC8601 device EEPROM interface makes it possible to set up the device to

self-configure its internal registers based on the information programmed into and

stored in an external device. To accomplish this, the EEPROM is read on power-up or

de-assertion of the NRESET bit. For field configuration, the EEPROM can also be

accessed using VSC8601 device registers 21E and 22E.

The EEPROM used to interface to the VSC8601 device must have a two- wire interface. A

device such as the Atmel part AT24CXXX is suggested.

As defined by the interface, data is clocked from the VSC8601 device on the falling

edge of EECLK. The device determines that an external EEPROM is present if EEDAT is

connected to a 4.7 kΩ external pull-up resistor. The EEDAT pin can be left floating or

grounded to indicate that no EEPROM is present.

4.5.1 EEPROM Contents Description

When an EEPROM is present, the VSC8601 device looks for the command header,

0xBDBD at address 0 and 1 of the EEPROM. The address is incremented by 256 until

the header is found. If the header is not found or no EEPROM is connected, the

VSC8601 device bypasses the EEPROM read step.

When an EEPROM is present, the VSC8601 device waits for an acknowledgement for

approximately three seconds (in accordance with the A TMEL EEPROM protocol). If there

VSS 8.25 kΩ0100

VSS 12.1 kΩ0101

VSS 16.9 kΩ0110

VSS 22.6 kΩ0111

VDD33 0 1 0 0 0

VDD33 2.26 kΩ1001

VDD33 4.02 kΩ1010

VDD33 5.90 kΩ1011

VDD33 8.25 kΩ1100

VDD33 12.1 kΩ1101

VDD33 16.9 kΩ1110

VDD33 22.6 kΩ1111

Table 51. CMODE Resistor Values and Resultant Bit Settings (continued)

With CMODE

Pin Tied To

With 1%

Resistor

Value

Set

Bit 3 (MSB) to:

Set

Bit 2 to:

Set

Bit 1 to:

Set

Bit 0 (LSB) to:

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 67

is no acknowledgement for three seconds, the VSC8601 device aborts its attempt to

connect to the EEPROM and reverts to its otherwise normal operating mode.

After the header value is found, the two-byte address value shown in the following table

indicates the EEPROM word address where the base address location for the device is

located. At the base address location, the next set of bytes indicates where the

configuration data contents to be programmed into the VSC8601 device are located. At

the programming location, the first two bytes represent the total number of bytes

(11 bits long, with MSB first) where the Total_Number_Bytes[10:0] is equal to the

number of SMI writes multiplied by 3 (one byte for SMI port and register address and

two bytes for data). Data is read from the EEPROM sequentially until all SMI write

commands are completed.

4.5.2 Read/Write Access to the EEPROM

The VSC8601 device also has the ability to read from and write to an EEPROM such as

an ATMEL AT24CXXX that is directly connected to its EECLK and EEDAT pins. If it is

Table 52. EEPROM Configuration Contents

10-bit Address Content (Bits 7:0)

00xBD

10xBD

2 PHY_ADDR[4:0], Base_Address_Location[10:8]

3 Base_Address_Location[7:0] (K)

Address length not specified

K 00000, Config Location[10:8]

K+1 Config_Location[7:0] (X)

Address length not specified

X 00000, Total_Number_Bytes[10:8]

X+1 Total_Number_Bytes [7:0] (M)

X+2 Register address a

X+3 Data[15:8] to be written to register address a

X+4 Data[7:0] to be written to register address a

X+5 Register address b

X+6 Data[15:8] to be written to register address b

X+7 Data[7:0] to be written to register address b

Address length not specified

X+(M–2) Register address x

X+(M–1) Data[15:8] to be written to register address x

X+M Data[7:0] to be written to register address x

Address length not specified

Max Address

VSC8601 Datasheet

Configuration

Revision 4.1

September 2009 Page 68

required to be able to write to the EEPROM, refer to the EEPROM’ s specific datasheet to

ensure that write protection on the EEPROM is not set.

The following illustration shows the interaction of the VSC8601 device and the EEPROM.

Figure 17. EEPROM Read and Write Register Flow

To read a value from a specific address of the EEPROM:

1. Read the VSC8601 device register bit 21E.11 and ensure that it is set.

2. Write the EEPROM address to be read to register bits 21E.10:0.

3. Set both register bits 21E.12 and 21E.13 both to 1.

4. When register bit 21E.11 changes to 1, read the 8-bit data value found at register

bits 22E.15:8. This is the contents of the address just read by the PHY.

To write a value to a specific address of the EEPROM:

1. Read the VSC8601 device register bit 21E.11 and ensure that it is set.

2. Write the address to be written to register bits 21E.10:0.

3. Set register bit 21E.12 to 0.

4. Set register bits 22E.7:0 with the 8-bit value to be written to the EEPROM.

5. Set register bit 21E.13 to 1.

6. To avoid collisions during read and write transactions, always wait until register bit

21E.11 changes to 1 before performing another EEPROM read or write operation.

Wait for Ready

21E.11 = 0

21E.11 = 1

Read or Write

21E.10:0 = Write Address

21E.12 = 0

22E.7:0 = Data to Write

Write EEPROM

Data

21E.10:0 = Address to Read

21E.12 = 1

21E.13 = 1

Wait for Ready

21E.11 = 0

21E.11 = 1

Read EEPROM

Data

Read Data = 22E.15:8

START

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 69

5 Electrical Specifications

This section provides the DC characteristics, AC characteristics, recommended

operating conditions, and stress ratings for the VSC8601 device. It includes information

on the various timing functions of the device.

5.1 DC Characteristics

In addition to any parameter-specific conditions, the specifications listed in the

following table may be considered valid only in the environment characterized by the

specifications listed as recommended operating conditions for the VSC8601 device. For

more information about the recommended operating conditions, see “Operating

Conditions,” page 82.

5.1.1 VDDIO at 3.3 V

In addition to any parameter-specific conditions, the specifications listed in the

following table may be considered valid only when all of these apply:

•V

DDIO is 3. 3 V

•V

DD33 is 3.3 V

•V

DD12 is 1.2 V

•V

DD12A is 1.2 V

•V

DDREG is 3.3 V

Table 53. DC Characteristics for VDD33, VDDIOMAC, or VDDIOMICRO at 3.3 V

Parameter Symbol Minimum Maximum Unit Condition

Output hi gh voltage VOH 2.4 3.6 V IOH = –4 mA

Output low voltage V OL 00.5VI

OL = 4 mA

Input high voltage VIH 2.0 5.0 V For JTAG pins

Input high voltage VIH 2.1 3.6 V For all other input pins

Input low voltage VIL –0.3 0.9 V

Input leakage

current IILEAK –43 43 μAInternal resistor included

Output leakage

current IOLEAK –43 43 μAInternal resistor included

Output low current

drive strength IOL 11 mA

Output high current

drive strength IOH –20 mA

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 70

5.1.2 VDDIO at 2.5 V

In addition to any parameter-specific conditions, the specifications listed in the

following table may be considered valid only when all of these apply:

•V

DDIO is 2. 5 V

•V

DD33 is 3.3 V

•V

DD12 is 1.2 V

•V

DD12A is 1.2 V

•V

DDREG is 3.3 V

5.2 Current Consumption

The current consumption values listed in this section are based on nominal values and

the PHY operating with full-duplex enabled and a 64-bit random data pattern at 100%

utilization. Values are grouped by the type of link and whether the on-chip switching

regulator is enabled.

5.2.1 Consumption with 1000BASE-T Link

The following table shows the current consumption values with a 1000BASE-T link and

the on-chip switching regulator enabled.

Table 54. DC Characteristics for VDDIOMAC or VDDIOMICRO at 2.5 V

Parameter Symbol Minimum Maximum Unit Condition

Output hi gh voltage VOH 2.0 2.8 V IOH = –1.0 mA

Output low voltage VOL –0.3 0.4 V IOL = 1.0 mA

Input high voltage VIH 2.0 3.0 V For all other pins

Input low voltage VIL –0.3 0.7 V

Input leakage current IILEAK –35 35 μAInternal resistor included

Output leakage

current IOLEAK –35 35 μAInternal resistor included

Output low current

drive strength IOL 9mA

Output high current

drive strength IOH –11 mA

Table 55. Current Consumption: 1000BASE-T, Regulator Enabled

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 115 mA

Current with VDDREG I

VDDREG 75 mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC 32 mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC 23 mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO < 1 mA

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 71

The following table shows the current consumption values with a 1000BASE-T link and

the on-chip switching regulator disabled.

5.2.2 Consumption with 100BASE-TX Link

The following table shows the current consumption values with a 100BASE-TX link and

the on-chip switching regulator enabled.

The following table shows the current consumption values with a 100BASE-TX link and

the on-chip switching regulator disabled.

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO < 1 mA

Total power at 3.3 V 734 mW

Total power at 2.5 V 686 mW

Table 56. Current Consumption: 1000BASE-T, Regulator Disabled

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 115 mA

Current with VDDREG I

VDDREG < 1 mA

Current with VDD12 at 1.2 V IVDD12 136 mA

Current with VDD12A at 1.2 V IVDD12A 34 mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC 32 mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC 23 mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO < 1 mA

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO < 1 mA

Total power at 3.3 V 689 mW

Total power at 2.5 V 641 mW

Table 57. Current Consumption: 100BASE-TX, Regulator Enabled

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 94 mA

Current with VDDREG IVDDREG 35 mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC 5mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC 3mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO < 1 mA

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO < 1 mA

Total power at 3.3 V 442 mW

Total power at 2.5 V 433 mW

Table 58. Current Consumption: 100BASE-TX, Regulator Disabled

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 94 mA

Table 55. Current Consumption: 1000BASE-T, Regulator Enabled (continued)

Parameter Symbol Typical Unit

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 72

5.2.3 Consumption with 10BASE-T Link

The following table shows the current consumption v alues with a 10BASE- T link and the

on-chip switching regulator enabled.

The following table shows the current consumption v alues with a 10BASE- T link and the

on-chip switching regulator disabled.

Current with VDDREG I

VDDREG < 1 mA

Current with VDD12 at 1.2 V IVDD12 55 mA

Current with VDD12A at 1.2 V IVDD12A 24 mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC 5mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC 3mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO < 1 mA

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO < 1 mA

Total power at 3.3 V 422 mW

Total power at 2.5 V 413 mW

Table 59. Current Consumption: 10BASE-T, Regulator Enabled

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 155 mA

Current with VDDREG I

VDDREG 19 mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC < 1 mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC < 1 mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO < 1 mA

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO < 1 mA

Total power at 3.3 V 573 mW

Total power at 2.5 V 573 mW

Table 60. Current Consumption: 10BASE-T, Regulator Disabled

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 155 mA

Current with VDDREG I

VDDREG < 1 mA

Current with VDD12 at 1.2 V IVDD12 24 mA

Current with VDD12A at 1.2 V IVDD12A 18 mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC < 1 mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC < 1 mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO < 1 mA

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO < 1 mA

Total power at 3.3 V 562 mW

Total power at 2.5 V 562 mW

Table 58. Current Consumption: 100BASE-TX, Regulator Disabled (continued)

Parameter Symbol Typical Unit

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 73

5.2.4 Consumption with No Link and ActiPHY Enabled

The following table shows the current consumption values with no link, ActiPHY

enabled, and the on-chip switching regulator enabled.

The following table shows the current consumption values with no link, ActiPHY

enabled, and the on-chip switching regulator disabled.

5.2.5 Consumption with No Link and ActiPHY Disabled

The following table shows the current consumption values with no link, ActiPHY

disabled, and the on-chip switching reg ulator enab led.

Table 61. Current Consumption: No Link, ActiPHY Enabled, Regulator Enabled

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 21 mA

Current with VDDREG I

VDDREG 21 mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC 12 mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC 8mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO < 1 mA

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO < 1 mA

Total power at 3.3 V 178 mW

Total power at 2.5 V 158 mW

Table 62. Current Consumption: No Link, ActiPHY Enabled, Regulator Disabled

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 21 mA

Current with VDDREG I

VDDREG < 1 mA

Current with VDD12 at 1.2 V IVDD12 27 mA

Current with VDD12A at 1.2 V IVDD12A 20 mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC 12 mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC 8mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO < 1 mA

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO < 1 mA

Total power at 3.3 V 165 mW

Total power at 2.5 V 146 mW

Table 63. Current Consumption: No Link, ActiPHY Disabled, Regulator Enabled

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 107 mA

Current with VDDREG I

VDDREG 22 mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC 12 mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC 8mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO < 1 mA

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 74

The following table shows the current consumption values with no link, ActiPHY

disabled, and the on-chip switching reg ulator disab led .

5.2.6 Consumption in Power-Down Mode

The following table shows the current consumption values in power-down mode

(register address 0.11 = 1) with the regulator enabled.

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO < 1 mA

Total power at 3.3 V 466 mW

Total power at 2.5 V 446 mW

Table 64. Current Consumption: No Link, ActiPHY Disabled, Regulator Disabled

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 107 mA

Current with VDDREG I

VDDREG < 1 mA

Current with VDD12 at 1.2 V IVDD12 27 mA

Current with VDD12A at 1.2 V IVDD12A 23 mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC 12 mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC 8mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO < 1 mA

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO < 1 mA

Total power at 3.3 V 453 mW

Total power at 2.5 V 433 mW

Table 65. Current Consumption: Power-Down, Regulator Enabled

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 15 mA

Current with VDDREG I

VDDREG 15 mA

Current with VDD12 at 1.2 V IVDD12 0mA

Current with VDD12A at 1.2 V IVDD12A 0mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC 0mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC 0mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO 0mA

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO 0mA

Total power at 3.3 V 99 mW

Table 63. Current Consumption: No Link, ActiPHY Disabled, Regulator Enabled

Parameter Symbol Typical Unit

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 75

The following table shows the current consumption values in power-down mode

(register address 0.11 = 1) with the regulator disabled.

5.2.7 Consumption in Reset State

The following table shows the current consumption values in the reset state

(NRESET pin pulled low).

5.3 AC Characteristics

The AC specifications are grouped according to specific device pins and associated

timing characteristics.

Table 66. Current Consumption: Power-Down, Regulator Disabled

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 15 mA

Current with VDDREG I

VDDREG 0mA

Current with VDD12 at 1.2 V IVDD12 12 mA

Current with VDD12A at 1.2 V IVDD12A 20 mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC 0mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC 0mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO 0mA

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO 0mA

Total power at 3.3 V 87.9 mW

Table 67. Current Consumption: Reset State

Parameter Symbol Typical Unit

Current with VDD33 at 3.3 V IVDD33 7mA

Current with VDDREG I

VDDREG 0mA

Current with VDD12 at 1.2 V IVDD12 0mA

Current with VDD12A at 1.2 V IVDD12A 0mA

Current with VDDIOMAC at 3.3 V IVDDIOMAC 0mA

Current with VDDIOMAC at 2.5 V IVDDIOMAC 0mA

Current with VDDIOMICRO at 3.3 V IVDDIOMICRO 0mA

Current with VDDIOMICRO at 2.5 V IVDDIOMICRO 0mA

Total power at 3.3 V 23.1 mW

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 76

5.3.1 Reference Clock Input

The following table lists the specifications for the reference clock input frequency

including various frequencies, duty cycle, and accuracy.

When using the 25 MHz crystal clock input option, the additional specifications in the

following table are required.

5.3.2 Clock Output

The specifications in the following table show the AC characteristics for the clock output

of the VSC8601 device.

Table 68. AC Characteristics for REFCLK Input

Parameter Symbol Minimum Typical Maximum Unit

Frequency with 25 MHz input fCLK25 25 MHz

Frequency with 125 MHz input fCLK125 125 MHz

Frequency accuracy fTOL 50 ppm

Duty cycle %DUTY 40 60 %

Rise time with 25 MHz input (20% to 80%) tR25 4ns

Rise time with 125 MHz input (20% to

80%) tR125 1ns

Table 69. AC Characteristics for REFCLK Input with 25 MHz Clock Input

Parameter Minimum Typical Maximum Unit

Crystal parallel load capacitance 18 20 pF

Crystal equivalent series resistance 10 30 Ω

Table 70. AC Characteristics for the CLKOUT Pin

Parameter Symbol Minimum Typical Maximum Unit Condition

CLKOUT frequency fCLK 125.00 MHz 125 MHz output

clock

CLKOUT cycle time tCYC 8.0 ns 125 MHz o u tput

clock

Frequency stability fSTABILITY 50 ppm

Duty cycle %DUTY 44 50 56 %

Clock rise and fall

times (20% to 80%) tR and tF1ns

Total jitter JCLK 217 6 00 ps Measured

peak-to-peak,

time interval

error

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 77

5.3.3 JTAG Interface

The following table lists the characteristics for the JTAG testing feature. F or information

about the JTAG interface timing, see Figure 18, page 77.

Figure 18. JTAG Interface Timing

5.3.4 SMI Interface

Use the information in the following table when incorporating the VSC8601 device SMI

interface into your own design. For information about the SMI interface timing, see

Figure 19, page 78.

Table 71. AC Characteristics for the JTAG Interface

Parameter Symbol Minimum Maximum Unit

TCK frequency fCLK 10 MHz

TCK cycle time tCYC 100 ns

TCK time high tWH 45 ns

TCK time low tWL 45 ns

Setup time to TCK rising tSU 10 ns

Hold time from TCK rising tH10 ns

TCK to TDO valid tCO 15 ns

Table 72. AC Characteristics for the SMI Interface

Parameter Symbol Minimum Typical Maximum Unit Condition

MDC frequency(1) fCLK 2.5 12.5 MHz

MDC cycle ti me tCYC 80 400 ns

TCK

TDI

TMS

tSU tH

tCYC

tWH tWL

tCO

TDO

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 78

Figure 19. SMI Interface Timing

5.3.5 Device Reset

The following specifications apply to the device reset functionality. For more information

about the reset timing, see Figure 20, page 79.

MDC time high tWH 20 50 ns

MDC time low tWL 20 50 ns

Setup to MDC rising tSU 10 ns

Hold from MDC rising tH10 ns

MDC rise time tR100

tCYC × 10%(1) ns For MDC = 0 – 1 MHz

For MDC = 1 MHz – fCLK(MAX)

MDC fall time tF100

tCYC × 10%(1)

MDC to MDIO valid tCO 10 300 ns Time dependant on value of

external pull-up resistor on

MDIO pin

1. For fCLK above 1 MHz, the maximum rise time and fall time is in relation to the frequency of the MDC clock

period. For example, if fCLK is 2 MHz, the maximum clock rise time and fall time is 50 ns.

Table 73. AC Characteristics for Device Reset

Parameter Symbol Minimum Maximum Unit Condition

NRESET assertion time tRESET 100 ns

Wait time between NRESET

de-assert and access of the

SMI interface

tWAIT 20

220 ms

ms Register 21E.14 = 0

Table 72. AC Characteristics for the SMI Interface (continued)

Parameter Symbol Minimum Typical Maximum Unit Condition

tSU

Data

MDC

tWL tWH

tCO

Data

tCYC

MDIO

(write)

MDIO

(read)

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 79

Figure 20. Reset Timing

Note The NRESET and NSRESET are mutually exclusive.

Soft reset (pin) assertion tSRESET_ASSERT 4ms

Soft reset (pin)

de-assertion tSRESET_DEASSERT 4ms

Reset rise time tRST_RISE 0

25 ms

ms If REG_EN pin = 0

If REG_EN pin = 1

Measured from a 10% level to a

90% level

Supply stable time tVDDSTABLE 10 ms

Wait time between soft

reset pin de-assert and

access of the SMI interface

tSWAIT 4

300

200

µs

Registers 28.1 = 1, 21E.14 = 0

Registers 28.1 = 0, 21E.14 = 0

Registers 28.1 = 0, 21E.14 = 1

Registers 28.1 = 1, 21E.14 = 1

Soft reset MII registe r 0.15

assertion tSREG_RESET 100 ns

Wait time between Soft

Reset (MII Register 0.15)

de-assert and access to the

SMI interface

tSREG_WAIT 4

300

200

µs

Registers 18.1 = 1, 21E.14 = 0

Registers 18.1 = 0, 21E.14 = 0

Registers 18.1 = 0, 21E.14 = 1

Registers 18.1 = 1, 21E.14 = 1

Table 73. AC Characteristics for Device Reset (continued)

Parameter Symbol Minimum Maximum Unit Condition

NRESET tRESET

REFCLK

tWAIT

MDIO

Soft Reset

(MII Register 0.15)

tSREG_RESET

tSREG_WAIT

Undefined State

MDC

NSRESET tSRESET_ASSERT

tSWAIT

tSRESET_DEASSERT

tRST_RISE

VDD33

tVDDSTABLE

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 80

5.3.6 RGMII Uncompensated

The following table lists the characteristics when using the device in RGMII

uncompensated mode. For more information about the RGMII uncompensated timing,

see Figure 21, page 81.

Table 74. AC Characteristics for RGMII Uncompensated

Parameter Symbol Minimum Typical Maximum Unit Condition

Clock

frequency 125

2.5

MHz 1000BASE-T operation

100BASE-TX operation

10BASE-T operation

1000BASE-T

duty cycle tDUTY1000 45 50 55 % At room temperature

and nominal supply

and register 28E.13: 12

set to 10 or 11

1000BASE-T

duty cycle tDUTY1000 40 50 60 % Register 28E.13 :12 s et

to 00 or 01

10/100BASE-T

duty cycle tDUTY10/100 40 50 60 %

Data to clock

output s kew

(at PHY)

tSKEWT –500 0 500 ps

Data to clock

output s kew

(at receiver)

tSKEWR1.01.8 2.6ns

TX_CLK

switching

threshold

VTHRESH 1.25

1.65 V

VVDDIOMAC = 2.5 V

VDDIOMAC = 3.3 V

TX_CLK rise

and fall times tR and tF750 ps

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 81

Figure 21. RGMII Uncompensated Timing

5.3.7 RGMII Compensated

The following table lists the characteristics when using the device in RGMII

compensated mode. For more information about the RGMII compensated timing, see

Figure 22, page 82.

Table 75. AC Characteristics for RGMII Compensated

Parameter Symbol Minimum Typical Maximum Unit Condition

Data to clock output

setup (at PHY

integrated delay)

tSETUPT1.2 2.0 3 ns

Data to clock output

setup (at receiver

integrated delay)

tSETUPR1.0 2.0 3 ns

Data to clock output

hold (at transmitter

integrated delay)

tHOLDT1.2 2.0 3 ns

TSKEWT

TXD[3:0]

TX_CTL

TX_CLK (at Transmitter)

TX_CLK (at Receiver)

TSKEWR

TXD[3:0] TXD[7:4]

TXEN TXERR

TSKEWT

RXD[3:0]

RX_CTL

RX_CLK (at Transmitter)

RX_CLK (at Receiver)

TSKEWR

RXD[3:0] RXD[7:4]

RXDV RXERR

TCYC

80%

20%

TR, TF

VTHRESH

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 82

Figure 22. RGMII Compensated Timing

5.4 Operating Conditions

The following table lists the recommended operating conditions for the VSC8601

device.

Data to clock output

hold (at PHY

integrated delay)

tHOLDR1.0 2.0 3 ns

TX_CLK switching

threshold vTHRESH 1.25

1.65 V

VVDDIOMAC = 2.5 V

VDDIOMAC = 3.3 V

Table 76. Recommended Operating Conditions

Parameter Symbol Minimum Typical Maximum Unit

Power supply voltage for VDDIOMICRO

at 2.5 V VDDIOMICRO 2.37 2.5 2.63 V

Table 75. AC Characteristics for RGMII Compensated (continued)

Parameter Symbol Minimum Typical Maximum Unit Condition

TSETUPT

TXD[3:0]

TX_CTL

TX_CLK (at Transmitter)

TX_CLK (at Receiver)

TSETUPR

TXD[3:0] TXD[7:4]

TXEN TXERR

RXD[3:0]

RX_CTL

RX_CLK (at Transmitter)

RX_CLK (at Receiver)

RXD[3:0] RXD[7:4]

RXEN RXERR

TX_CLK with

Internal

Delay Added

THOLDR

THOLDT

TSETUPT

RX_CLK with

Internal

Delay Added

THOLDR

THOLDT

Delay = 2.0 ns

VTHRESH

VSC8601 Datasheet

Electrical Specifications

Revision 4.1

September 2009 Page 83

5.5 Stress Ratings

This section contains the stress ratings for the VSC8601 device.

Warning Stresses listed in the following table may be applied to devices one at a time

without causing permanent damage. Functionality at or exceeding the values listed is

not implied. Exposure to these values for extended periods may affect device reliability.

Warning This device can be damaged by electrostatic discharge (ESD) voltage.

Vitesse recommends that all integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and installation procedures may

adversely affect reliability of the device.

Power supply voltage for VDDIOMICRO

at 3.3 V VDDIOMICRO 3.0 3.3 3.6 V

Power supply v oltage for VDDIOMAC at

2.5 V VDDIOMAC 2.37 2.5 2.63 V

Power supply v oltage for VDDIOMAC at

3.3 V VDDIOMAC 3.0 3.3 3.6 V

Power supply voltage for VDD33 VDD33 3.0 3.3 3.6 V

Power supply voltage for VDDREG VDDREG 3.0 3.3 3.6 V

Power supply voltage for VDD12 VDD12 1.14 1.2 1.26 V

Power supply voltage for VDD12A VDD12A 1.14 1.2 1.26 V

Operating temperature(1) T0 90°C

1. Lower limit of specification is ambient temperature, and upper limit is case temperature.

Table 77. Stress Ratings

Parameter Symbol Minimum Maximum Unit

DC input voltage on VDDIOMICRO supply pin VDDIOMICRO –0.5 4.0 V

DC input voltage on VDDIOMAC supply pin VDDIOMAC –0.5 4.0 V

DC input voltage on VDD33 supply pin VDD33 –0.5 4.0 V

DC input voltage on VDDREG supply pin VDDREG –0.5 4.0 V

DC input voltage on VDD12 supply pin VDD12 –0.5 1.5 V

DC input voltage on VDD12A supply pin VDD12A –0.5 1.5 V

DC input voltage on JTAG pins, 5 V tolerant VDD(5 V) –0.5 5.5 V

DC input voltage on any non-supply pin VDD(PIN) –0.5 VDD + 0.5 V

Storage temperature TS–65 150 oC

Electrost ati c discha rge vo ltage, charged dev ice

model VESD_CDM –500 500 V

Electrostatic discharge voltage, human body

model VESD_HBM –1500 1500 V

Table 76. Recommended Operating Conditions (continued)

Parameter Symbol Minimum Typical Maximum Unit

VSC8601 Datasheet

Pin Descriptions

Revision 4.1

September 2009 Page 84

6 Pin Descriptions

The VSC8601 device has 64 pins, which are described in this section.

The pin information is also provided as an attached Microsoft Excel file, so that y ou can

copy it electronically. In Adobe Reader, double-click the attachment icon.

6.1 Pin Diagram

The following illustration shows the pin diagram for the VSC8601 device.

Note The exposed pad is internally connected to ground and should be connected to

VSS on the board as well.

Figure 23. Pin Diagram

VDD33

TDO

TDI

VDD12

TMS

TCK

NTRST

NRESET

EEDAT

EECLK

VDDIOMICRO

MDINT

MDC

MDIO

VDD12

VDDIOMAC

PLLMODE

REG_OUT

VDDREG

REG_EN

OSCEN/CLKOU

LED0

LED1

LED2

VDD33

CMODE3

CMODE2

CMODE1

CMODE0

VDD12

VDDIOMAC

NSRESET

TX_CTL

TXD0

TXD1

TXD2

TXD3

TX_CLK

VDDIOMAC

RX_CLK

RXD0

RXD1

RXD2

RXD3

VDDIOMAC

RX_CTL

VSS

REF_FILT

REF_REXT

VDD33

VDD12A

TXVPA

TXVNA

TXVPB

TXVNB

VDD33

TXVPC

TXVNC

TXVPD

TXVND

VDD33

XTAL2

XTAL1/REFCLK

VSC8601

Exposed

Pad

VSC8601 Datasheet

Pin Descriptions

Revision 4.1

September 2009 Page 85

6.2 Pins by Function

This section contains the functional pin descriptions for the VSC8601 device. The

following table contains notations for definitions of the various pin types.

6.2.1 Twisted Pair Interface

The following table lists the device pins associated with the device two-wire, twisted

pair interface.

Table 78. Pin Type Symbols

Symbol Pin Type Description

I Input Input with no on-chip pull-up or pull-down resistor.

I/O Input and Output Input and output signal with no on-chip pull-up or

pull-down resistor.

IPU Input with pull-up Input with on-chip 100 kΩ pull-up resistor to VDDIO.

IPD Input with pull-down Input with on-chip 100 kΩ pull-down resistor to VSS.

IPD/O Bidirectional with

pull-down Input and output signal with on-chip 100 kΩ pull-down

resistor to VSS.

IPU/O Bidirectional with

pull-up Input and output signal with on-chip 100 kΩ pull-up

resistor to VDDIO or VDD33.

O Output Output signal.

OZC Impedance controlled

output Integrated (on-chip) source series terminated, output

signal.

OD Open drain Open drain output.

OS Open source Open source output.

ADIFF Analog differential Analog differential signal pair for twisted pair interface.

ABIAS Analog bias Analog bias pin.

IAAnalog input Analog Input for sensing variable voltage levels.

IPU5V Input with pull-up Input with on-chip 100 kΩ pull-up resistor to VDD33.

These pins are 5 V tolerant.

OCRYST Crystal output Crystal clock output pin. If not used, leave unconnected.

NC No connect No connect pins must be left floating.

Table 79. Twisted Pair Interface Pins

Pin Name Type Description

53 TXVPA ADIFF TX/RX channel A positive signal

54 TXVNA ADIFF TX/RX channel A negative signal

55 TXVPB ADIFF TX/RX channel B positive signal

56 TXVNB ADIFF TX/RX channel B negative signal

58 TXVPC ADIFF TX/RX channel C positive signal

59 TXVNC ADIFF TX/RX channel C negative signal

60 TXVPD ADIFF TX/RX channel D positive signal

61 TXVND ADIFF TX/RX channel D negative signal

VSC8601 Datasheet

Pin Descriptions

Revision 4.1

September 2009 Page 86

6.2.2 RGMII MAC Interface

The following table lists the device pins associated with the RGMII MAC interface. Note

that the pins in this table are referenced to VDDIOMAC and can be set to a 2.5 V or

3.3 V power supply.

Table 80. RGMII MAC Interface Pins

Pin Name Type Description

RXD3

RXD2

RXD1

RXD0

OZC Multiplexed receive data. Bits[3:0] are

synchronously output on the rising edge of

RX_CLK and bits[7:4] on the falling edge of

RX_CLK.

24 RX_CLK OZC Receive clock. Receive data is sourced from the

PHY synchronously on the rising edge of RX_CLK

and is the recovered clock from the media.

18 RX_CTL OZC Multiplexed receive data valid, receive error. This

output is sampled by the MAC on opposite edges

of RX_CLK to indicate two receive conditions from

the PHY:

1. On the rising edge of RX_CLK, this output

serves as RXDV and signals valid data is available

on the RXD input data bus.

2. On the falling edge of RX_CLK, this output

signals a receive error from the PHY, based on a

logical derivative of RXDV and RXER, as stated by

the RGMII specification.

TXD3

TXD2

TXD1

TXD0

IPD Multiplexed transmit data. Bits[3:0] are

synchronously output on the rising edge of

TX_CLK and bits[7:4] on the falling edge of

TX_CLK.

26 T X_CLK I Transmit clock. This clock is 2.5 MHz for 10 Mbps

mode, 25 MHz for 100 Mbps mode, and 125 MHz

for 1000 Mbps mode. If left unconnected, these

pins require a pull-down resistor to ground.

31 TX_CTL IPD Multiplexed transmit enable, transmit error. This

input is sampled by the PHY on opposite edges of

TX_CLK to indic ate two transmit conditions o f the

MAC:

1. On the rising edge of TX_CLK, this input serves

as TXEN, indicating valid data is available on the

TXD input data bus.

2. On the falling edge of TX_CLK, this input signals

a transmit error from the MAC, based on a logical

derivative of TXEN and TXER, as stated by the

RGMII specification.

32 NSRESET IPU Soft Rese t. Activ e low input that places t he device

in a low-power state. Although the device is

powered down, the sticky serial management

interface registers retain their value.

VSC8601 Datasheet

Pin Descriptions

Revision 4.1

September 2009 Page 87

6.2.3 Serial Management Interface (SMI)

The following table lists the device pins associated with the device serial management

interface (SMI). Note that the pins in this table are referenced to VDDIOMICRO and can

be set to a 2.5 V, or 3.3 V power supply.

43 OSCEN/CLKOUT IPU/O OSCEN. This pin is sampled on the rising edge of

NRESET. If HI GH (or left floating), then the

on-chip oscillator circuit is enabled. If LOW, the

oscillator circuit is disabled and the device must be

supplied with a 25 MHz or 125 MHz reference

clock to the REFCLK pin.

CLKOUT. After NRESET is deasserted and OSCEN

state is established, this pin becomes the clock

output. The clock output can be enabled or

disabled through a CMODE pin setting. Also, it can

generate a reference clock frequency of 125 MHz.

This pin is not active when NRESET is asserted.

When disabled, the pin is held low.

Table 81. SMI Pins

Pin Name Type Description

13 MDC IPU Management data clock. A 0 MHz to 12.5 MHz

reference input is used to clock serial MDIO data

into and out of the PHY.

14 MDIO I/O Management data input/output pin. Serial data is

written or read from this pin bidirectionally

between the PHY and st ation manager,

synchronously on the positive edge of MDC. One

external pull-up resistor is required at the station

manager, and its value depends on the MDC clock

frequency and the total sum of the capacit ive loads

from the MDIO pins.

12 MDINT OS/OD Management interrupt signal. After reset, the

device configures this pin, along with others from

other devices, as active -low (open drain) or

active-high (open source) based on the polarity of

an external 10 kΩ resistor conn ection. These pins

can be tied together in a wired-OR configuration

with only a single pull-up or pull-down resistor.

9 EEDAT IPD/O (Optional) EEPROM serial I/O data. Used to

configure PHYs in a system without a station

manager. Connect to the SDA pin of the ATMEL

“AT24CXXX” serial EEPROM device family.

The VSC8601 determines t hat an external EEPROM

is present by monitoring the EEDAT pin at

power-up or when NRESET is de-asserted. If

EEDAT has a 4.7 kΩ external pull-up resistor, the

VSC8601 assumes an EEPROM is present. The

EEDAT pin can be left floating or grounded to

indicate no EEPROM.

Table 80. RGMII MAC Interface Pins (continued)

Pin Name Type Description

VSC8601 Datasheet

Pin Descriptions

Revision 4.1

September 2009 Page 88

6.2.4 JTAG

The following table lists the device pins associated with the device JTAG testing facility.

6.2.5 Miscellaneous

The following table lists the device pins associated with a particular interface or facility

on the device.

10 EECLK OZC (Opt ional) EEPROM Serial Output Clock. Used to

configure PHYs in a system without a station

manager. Connect to the SCL pin of the ATMEL

“AT24CXXX” serial EEPROM device family.

8 NRESET IPU Device Reset. Active low input that powers down

the device and sets the register bits to their default

state.

Table 82. JTAG Pins

Pin Name Type Description

3 TDI IPU5V JTAG test serial data input.

2 TDO O JTAG test serial data output.

5 TMS IPU5V JTAG test mode select.

6 TCK IPU5V JTAG test clock input.

7 NTRST IPU5V JTAG reset. If JTAG is not used, then tie this pin

to VSS (ground) with a pull-down resistor.

Table 83. Miscellaneous Pins

Pin Name Type Description

CMODE3

CMODE2

CMODE1

CMODE0

IAConfiguration mode (CMODE) pins. For more

informat ion, see “CMODE,” page 64.

64 XTAL1/REFCLK I Crystal oscillator input. If OSCEN=high, then a

25 MHz parallel resonant crystal with ±50 ppm

frequency tolerance should be connected across

XTAL1 and XTAL2. A 33 pF capacitor should also tie

the XTAL1 pin to ground.

Refere nc e cl ock input. If OSCEN=low, the clock input

frequency can either be 25 MHz (PLLMODE=0) or

125 MHz (PLLMODE is high).

63 XTAL2 OCRYST Crystal oscillator output. The crystal should be

connected across XTAL1 and XTAL2. A 33 pF

capacitor should also tie the XTAL2 pin to ground. If

not using a crystal oscillator, this output pin can be

left floating if driving XTAL1/REFCLK with a reference

clock.

Table 81. SMI Pins (continued)

Pin Name Type Description

VSC8601 Datasheet

Pin Descriptions

Revision 4.1

September 2009 Page 89

6.2.6 Power Supply

The following table lists the device power supply pins.

47 PLLMODE I PLL mode input select. Sampled on power-up or

reset. If PLLMODE is low, then REFCLK must be

25 MHz. If PLLMODE is high, then REFCLK must be

125 MHz.

If a crystal or an external 25 MHz clock is used,

PLLMODE must be pulled low. If an external 125 MHz

clock is used, PLLMODE must be pulled high.

LED2

LED1

LED0

O LED direct-drive outputs. All LEDs pins are active-low .

For more information about LED operation, see “LED

Interface,” page 28.

50 REF_REXT ABIAS Reference external connects to an external 2 kΩ

(1%) resistor to analog ground.

49 REF_FILT ABIAS R eference filter connects to an external 1 μF capacitor

to analog ground.

44 REG_EN I Regulator enable. Ac tive high input enables the

on-chip switching regulator and generates a 1.2 V

supply voltage.

46 REG_OUT ABIAS Regulator output. When REG_EN is enabled,

REG_OUT supplies a 1.2 V supply that has been

regulated from the 3.3 V supply. When connecting to

the 1.2 V supply pins, additional requirements are a

4.7 μH to 5.1 μH inductor in series as well as 10 μF

and 1 μF capacitors to ground. The on-chip switching

regulator is optional, and 1.2 V power can be

supplied externally.

48 NC NC No connects. Do not connect them together or to

ground. Leave these pins unconnected (floating).

Table 84. Power Supply Pins

Pin Name Type Description

1, 39, 51, 57, 62 VDD33 3.3 V G eneral 3.3 V supp ly.

45 VDDREG 3.3 V On-chip switching regulator 3.3 V supply.

11 VDDIOMICRO 3.3 V

2.5 V I/O micro power supply.

16, 19, 25, 33 VDDIOMAC 3.3 V

2.5 V I/O MAC power supply.

4, 15, 34 VDD1 2 1.2 V Internal digital core voltage.

52 VDD12A 1.2 V 1.2 V analog power requiring additional

PCB power supply filtering.

17 , PAD(1)

1. Exposed pad is on the bottom of the package.

VSS 0 V General device ground.

Table 83. Miscellaneous Pins (continued)

Pin Name Type Description

VSC8601 Datasheet

Pin Descriptions

Revision 4.1

September 2009 Page 90

6.2.7 Power Supply and Associated Function

Although certain function pins may not be used for a specific application, all power

supply pins must be connected to their respective voltage input.

Table 85. Power Supply Pins and Associated Function Pins

Pins Nominal Voltage Associated Functional Pins

VDD33 3.3 V LED[2:0], CLKOUT, NRESET, JTAG (5), XTAL1, XTAL2,

CMODE, TXVP, TXVN, REF_FILT, REF_REXT

VDDIOMICRO 2.5 V, 3.3 V MDC, MDIO, MDINT, EECLK, EEDAT

VDDIOMAC 2.5 V, 3.3 V RXD, RX_CTL, RX_CLK, TXD, TX_CTL, TX_CLK, NSRESET

VSC8601 Datasheet

Pin Descriptions

Revision 4.1

September 2009 Page 91

6.3 Pins by Name

This section provides an alphabetical list of the VSC8601 pins.

CMODE0 35

CMODE1 36

CMODE2 37

CMODE3 38

EECLK 10

EEDAT 9

LED0 42

LED1 41

LED2 40

MDC 13

MDINT 12

MDIO 14

NC 48

NRESET 8

NSRESET 32

NTRST 7

OSCEN/CLKOUT 43

PLLMODE 47

REF_FILT 49

REF_REXT 50

REG_EN 44

REG_OUT 46

RX_CLK 24

RX_CTL 18

RXD0 23

RXD1 22

RXD2 21

RXD3 20

TCK 6

TDI 3

TDO 2

TMS 5

TX_CLK 26

TX_CTL 31

TXD0 30

TXD1 29

TXD2 28

TXD3 27

TXVNA 54

TXVNB 56

TXVNC 59

TXVND 61

TXVPA 53

TXVPB 55

TXVPC 58

TXVPD 60

VDD12 4

VDD12 15

VDD12 34

VDD12A 52

VDD33 1

VDD33 39

VDD33 51

VDD33 57

VDD33 62

VDDIOMAC 16

VDDIOMAC 19

VDDIOMAC 25

VDDIOMAC 33

VDDIOMICRO 11

VDDREG 45

VSS 17

XTAL1/REFCLK 64

XTAL2 63

VSC8601 Datasheet

Pin Descriptions

Revision 4.1

September 2009 Page 92

6.4 Pins by Number

This section provides a numeric list of the VSC8601 pins.

1 VDD33

2TDO

3TDI

4 VDD12

5TMS

6TCK

7NTRST

8NRESET

9EEDAT

10 EECLK

11 VDDIOMICRO

12 MDINT

13 MDC

14 MDIO

15 VDD12

16 VDDIOMAC

17 VSS

18 RX_CTL

19 VDDIOMAC

20 RXD3

21 RXD2

22 RXD1

23 RXD0

24 RX_CLK

25 VDDIOMAC

26 TX_CLK

27 TXD3

28 TXD2

29 TXD1

30 TXD0

31 TX_CTL

32 NSRESET

33 VDDIOMAC

34 VDD12

35 CMODE0

36 CMODE1

37 CMODE2

38 CMODE3

39 VDD33

40 LED2

41 LED1

42 LED0

43 OSCEN/CLKOUT

44 REG_EN

45 VDDREG

46 REG_OUT

47 PLLMODE

48 NC

49 REF_FILT

50 REF_REXT

51 VDD33

52 VDD12A

53 TXVPA

54 TXVNA

55 TXVPB

56 TXVNB

57 VDD33

58 TXVPC

59 TXVNC

60 TXVPD

61 TXVND

62 VDD33

63 XTAL2

64 XTAL1/REFCLK

VSC8601 Datasheet

Package Information

Revision 4.1

September 2009 Page 93

7 Package Information

The VSC8601 package is a lead(Pb )-free, 64-pin, plastic low-profile quad flat package

(LQFP) with an exposed pad, 10 mm × 10 mm body size, 1.4 mm body thickness,

0.5 mm pin pitch, and 1.6 mm maximum height.

Lead(Pb)-free products from Vitesse comply with the temperatures and profiles defined

in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see

the IPC and JEDEC standard.

This section provides the package drawing, thermal specifications, and moisture

sensitivity rating for the VSC8601 device.

7.1 Package Drawing

The following illustration shows the package drawing for the VSC8601 device. The

drawing contains the top view, bottom view, side view, detail views, dimensions,

tolerances, and notes.

VSC8601 Datasheet

Package Information

Revision 4.1

September 2009 Page 94

Figure 24. Package Drawing

ccc

SL0.25

4.000

Exposed

pad

Dimensions and Tolerances

A2 A1

Seating

plane

0.05 S

Gage plane

See Detail A

116

Reference Minimum Nominal Maximum

ddd M C A-B S D S

bbb H A-B D

aaa C A-B D

aaa

bbb

ccc

ddd

1.60

0.15

1.45

0.05

1.35 1.40

12.00

10.00

12.00

10.00

0.08

0.09

0.45

0.20

0.17

0.20

0.75

0.27

3.5

0.60

1.00

0.20

0.50

7.50

0.20

0.08

Top View Bottom View

Side View

Detail A

Notes

1. All dimensions and tolerances are in millimeters (mm).

2. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is 0.25 mm per side. D1 and E1 are

maximum plastic body size dimensions including mold

mismatch.

3. Dimension b does not include dambar protrusion.

Allowable dambar protrusion does not cause the lead

width to exceed the maximum b dimension by more than

0.08 mm.

VSC8601 Datasheet

Package Information

Revision 4.1

September 2009 Page 95

7.2 Thermal Specifications

Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2

and have been modeled using a four-layer test board with two signal layers, a power

plane, and a ground plane (2s2p PCB). For more information, see the JEDEC standard.

To achieve results similar to the modeled thermal resistance measurements, the

guidelines for board design described in the JEDEC standard EIA/JESD51 series must be

applied. For information about specific applications, see the following:

EIA/JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct

Thermal Attachment Mechanisms

EIA/JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface

Mount Packages

EIA/JESD51-9, Test Boards for Area Array Surface Mount Package Thermal

Measurements

EIA/JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal

Measurements

EIA/JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal

Measurements

7.3 Moisture Sensitivity

This device is rated moisture sensitivity level 3 or better as specified in the joint IPC

and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and

JEDEC standard.

Table 86. Thermal Resistances

θJA (°C/W) vs. Airflow (ft/min)

Part Order Number θJC θJB 0 100 200

VSC8601XKN 18.5(1)

6.4(2)

1. Simulated on th e top of the mold c ompound with the exposed pad soldered to a ground pad on

the PCB.

2. Calculated on the exposed pad soldered to a ground pad on the PCB.

22 33 30 28

VSC8601 Datasheet

Design Considerations

Revision 4.1

September 2009 Page 96

8 Design Considerations

This section explains various issues associated with the VSC8601 device.

8.1 RX_CLK Can Reach as High as 55% Duty Cycle

Issue: When register 23, bit 8 = 0 (no internal clock skew) for RGMII, then the RX_CLK

duty cycle has been measured as high as 55%.

Implications: There is a possibility that the duty cycle can go beyond this value, which

then violates what is specified in the datasheet. This has only been observed when the

skew setting is set to 0.

Workaround: Avoid using an RGMII skew setting of 0.

8.2 First SMI Write Fails after Software Reset

Issue: After applying software reset (using either register 0, bit 15 or the NSRESET

pin), the first subsequent SMI write operation into register 4 (auto-negotiation

advertisement) or register 9 (1000BASE-T control) does not work. This issue only

occurs if the first SMI write after software reset is into register 4 or 9. This issue does

not occur if any kind of SMI transaction (either read or write) is applied to any register

between the time of the software reset and the SMI write into register 4 or 9.

Implications: The PHY may operate unexpectedly, because settings for registers 4

and 9 remain at the reset value. There are no such implications after either hardware

reset or power-down events.

Workaround: Writing “0x0000” into register 31 after every software reset avoids this

issue, and subsequent SMI writes into register 4 or 9 succeed.

8.3 Link-Up Issue In Forced 100BASE-TX Mode

Issue: While in the forced 100BASE-TX mode with the automatic crossover detection

feature (HP Auto-MDIX) enabled, it can take up to several minutes for the link-up

process between the VSC8601 device and a link partner that also has its automatic

crossover detection feature enabled. The problem has not been observed in any other

operation modes.

Implications: While working against some link partners, such as those by Marvell, it can

take up to several minutes for the link-up process to complete.

Workaround: When forcing 100BASE-TX mode, use the following script to alter the

internal method that the VSC8601 uses to perform crossover detection. For more

information, see PHY API Software and Programmers Guide, which is available on the

Vitesse Web site at www.vitesse.com.

PhyWrite (PortNo, reg_num(dec), 16_bit_unsigned_data(hex))

PhyWriteMsk (PortNo, reg_num(dec), 16_bit_unsigned_data(hex), mask(hex))

VSC8601 Datasheet

Design Considerations

Revision 4.1

September 2009 Page 97

PhyWrite (PortNo, 31, 0x52B5); // Select internal register page

PhyWrite (PortNo, 16, 0xA7F8); // Request read of internal register

PhyWriteMsk (PortNo, 17, 0x0018, 0x0018); // Set for forced 100BASE-TX

PhyWriteMsk (PortNo, 18, 0, 0); // Necessary read & re-write register 18

PhyWrite (PortNo, 16, 0x87F8); // Write back modified internal register

PhyWrite (PortNo, 31, 0); // Select main register page

When returning from forced 100BASE-TX mode to auto-negotiation mode, use the

following script to restore the standard method that VSC8601 uses to perform

crossover detection:

PhyWrite (PortNo, 31, 0x52B5); // Select internal register page

PhyWrite (PortNo, 16, 0xA7F8); // Request read of internal register

PhyWriteMsk (PortNo, 17, 0x0000, 0x0018); // Set for auto-negotiation

PhyWriteMsk (PortNo, 18, 0, 0); // Necessary read & re-write register 18

PhyWrite (PortNo, 16, 0x87F8); // Write-back modified internal register

PhyWrite (PortNo, 31, 0); // Select main register page

Note It is not important which order is used for writes to the SMI register with respect

to writes to Register 0, which disable and enable the auto-negotiation feature.

8.4 Default 10Base-T Settings Are Marginal and Cause

MAU Test Failure

Issue: Default 10Base-T settings are marginal for PHY silicon and magnetic module

variations.

Implications: It often causes the output 10Base-T signal to violate the IEEE waveform

templates.

W orkaround: During device initialization, use the following script. F or more information,

see PHY API Software and Programmers Guide, which is available on the Vitesse Web

site at www.vitesse.com.

PhyWrite (PortNo, reg_num(dec), 16_bit_unsigned_data(hex))

PhyRead (PortNo, reg_num(dec))

~ -- Logical NOT

& -- Logical AND

| -- Logical OR

= -- Assign value to variable

PhyWrite (PortNo, 31, 0x52b5); // Select internal register page

PhyWrite (PortNo, 18, 0x9e); // Necessary write of internal register

PhyWrite (PortNo, 17, 0xdd39); // Necessary write of internal register

PhyWrite (PortNo, 16, 0x87aa); // Necessary write of internal register

PhyWrite (PortNo, 16, 0xa7b4); // Necessary write of internal register

reg = PhyRead (PortNo, 18); // Read internal reg. and assign it to var.

PhyWrite (PortNo, 18, reg); // Necessary write of internal register

reg = PhyRead (PortNo, 17); // Read internal reg. and assign it to var.

reg = (reg & ~0x003f) | 0x003c;// Modify variable value

PhyWrite (PortNo, 17, reg); // Write back modified internal register

VSC8601 Datasheet

Design Considerations

Revision 4.1

September 2009 Page 98

PhyWrite (PortNo, 16, 0x87b4); // Necessary write of internal register

PhyWrite (PortNo, 16, 0xa794); // Necessary write of internal register

reg = PhyRead (PortNo, 18); // Read internal reg. and assign it to var.

PhyWrite (PortNo, 18, reg); // Necessary write of internal register

reg = PhyRead (PortNo, 17); // Read internal reg. and assign it to var.

reg = (reg & ~0x003f) | 0x003e;// Modify variable value

PhyWrite (PortNo, 17, reg); // Write back modified internal register

PhyWrite (PortNo, 16, 0x8794); // Necessary write of internal register

PhyWrite (PortNo, 18, 0xf7); // Necessary write of internal register

PhyWrite (PortNo, 17, 0xbe36); // Necessary write of internal register

PhyWrite (PortNo, 16, 0x879e); // Necessary write of internal register

PhyWrite (PortNo, 16, 0xa7a0); // Necessary write of internal register

reg = PhyRead (PortNo, 18); // Read internal reg. and assign it to var.

PhyWrite (PortNo, 18, reg); // Necessary write of internal register

reg = PhyRead (PortNo, 17); // Read internal reg. and assign it to var.

reg = (reg & ~0x003f) | 0x0034;// Modify variable value

PhyWrite (PortNo, 17, reg); // Write back modified internal register

PhyWrite (PortNo, 16, 0x87a0); // Necessary write of internal register

PhyWrite (PortNo, 18, 0x3c); // Necessary write of internal register

PhyWrite (PortNo, 17, 0xf3cf); // Necessary write of internal register

PhyWrite (PortNo, 16, 0x87a2); // Necessary write of internal register

PhyWrite (PortNo, 18, 0x3c); // Necessary write of internal register

PhyWrite (PortNo, 17, 0xf3cf); // Necessary write of internal register

PhyWrite (PortNo, 16, 0x87a4); // Necessary write of internal register

PhyWrite (PortNo, 18, 0x3c); // Necessary write of internal register

PhyWrite (PortNo, 17, 0xd287); // Necessary write of internal register

PhyWrite (PortNo, 16, 0x87a6); // Necessary write of internal register

PhyWrite (PortNo, 16, 0xa7a8); // Necessary write of internal register

reg = PhyRead (PortNo, 18); // Read internal reg. and assign it to var.

PhyWrite (PortNo, 18, reg); // Necessary write of internal register

reg = PhyRead (PortNo, 17); // Read internal reg. and assign it to var.

reg = (reg & ~0x0fff) | 0x0125;// Modify variable value

PhyWrite (PortNo, 17, reg); // Write back modified internal register

PhyWrite (PortNo, 16, 0x87a8); // Necessary write of internal register

PhyWrite (PortNo, 31, 0); // Select main register page

VSC8601 Datasheet

Design Considerations

Revision 4.1

September 2009 Page 99

8.5 On-Chip Pull-up Resistor Violation

Issue: According to the IEEE standard 802.3, the MDIO pin on a slave device should be

an open-drain pad type and drive a low value onto the MDIO shared bus. The MDIO

shared bus should be pulled high with a pull-up resistor on the PCB or SMI bus master.

The VSC8601 device includes a 100 kΩ pull-up on-chip resistor that violates this IEEE

specification.

Implication: The VSC8601 device requires an off-chip and on-chip pull-up resistor for

the interface to operate correctly. The typical value of the off-chip resistor is relatively

small at <1 kΩ, which maintains a short rise time of the MDIO signal. Adding a 100 kΩ

pull-up on-chip resistor in parallel with the off-chip pull-up resistor, does not have any

practical implications.

Workaround: No workaround is needed.

8.6 Setting the Internal RGMII Timing Compensation

Value

Issue: There are two inter-related registers to control the internal RGMII skew timing

compensation. The finest level of control is through register 28E.15:12, which has four

settings (0 ns, 1.4 ns, 1.7 ns, and 2.0 ns) for either Rx or Tx. Alternatively, register

23.8 provides a simpler level of control (0 ns or 1.7 ns for both Rx and Tx) for

compatibility with legacy Vitesse PHY software. A write to either register automatically

affects the other so that they are logically consistent. However, this relationship means

the legacy control of register 23.8 can potentially overwrite the finer-level controls in

Implication: If you intend to use the skew compensation settings in 28E, always write

to this register after, not before, a write to register 23. For example, suppose

the resulting delay is 1.4 ns. A subsequent write to register 23, even if bit 8 is kept

as 1, automatically changes register 28E to 1010 (1.7 ns).

Workaround: Before performing a write to register 23, first read and store the settings

in register 28E. After writing to register 23, write the stored value back to register 28E.

8.7 10BASE-T Harmonics at 30 MHz and 50 MHz

Marginally Violate Specification

Issue: The IEEE 802.3 specification states that in 10BASE-T mode, when the DO circuit

is driven by an all-ones, Manchester-encoded signal, an y harmonic measured on the TD

circuit must be at least 27 dB below the fundamental. In VSC8601, this specification is

marginally violated at 30 MHz and 50 MHz when this measurement is made under

corner conditions. Under nominal conditions, this measurement meets the IEEE

specification limits.

Implications: This violation has no practical implication on the performance of the

device. 10BASE-T mode has been validated to work without any issues with cables far

exceeding the IEEE-specified, worst-case limits.

Workaround: None required.

VSC8601 Datasheet

Design Considerations

Revision 4.1

September 2009 Page 100

8.8 Voltage Overshoot When Using On-Chip Switching

Regulator

Issue: The device’s on-chip switching regulator generates notable voltage overshoot.

Implications: The voltage overshoot from the on-chip switching regulator may lead to

device performance issues such as CRC errors, jitter, or both.

Workaround: When using the on-chip regulator, dampen the overshoot by adding a

snubber circuit on the output of the regulator pins (REG_OUT). This circuit consists of a

15 Ω resistor and 0.001 µF capacitor connected in series to the REG_OUT pins and

ground. For more information about the regulator circuitry connection, see VSC8601

Design and Layout Guide, which is available on the Vitesse Web site at

www.vitesse.com.

8.9 Long Link-Up Times Caused by Noise on the

Twisted Pair Interface

Issue: The VSC8601 may experience longer link-up times during the link-up

auto-negotiation process when there is signal noise coming from the link partner.

Implications: Normally, the VSC8601 device successfully links during auto-negotiation

when there is signal noise coming from the link partner. However, on rare occasions,

the link-up time can be significantly increased for successful auto-negotiation.

Workaround: During device initialization, it is strongly recommended that the following

software script is implemented. For more information, see PHY API Software and

Programmers Guide, which is available on the Vitesse Web site at www.vitesse.com.

PhyWrite (PortNo, reg_num(dec), 16_bit_unsigned_data(hex))

PhyRead (PortNo, reg_num(dec))

~ -- Logical NOT

& -- Logical AND

| -- Logical OR

= -- Assign value to variable

PHY_Write (PortNo, 31, 0x52b5); // Select internal register page

PHY_Write (PortNo, 16, 0xa7fa); // Necessary write of internal register

reg = PHY_Read (PortNo, 18); // Read internal register and assign it to

var.

PHY_Write (PortNo, 18, reg); // Necessary write of internal register

reg = PHY_Read (PortNo, 17); // Read internal register and assign it to

var.

reg = (reg | 0x0008); // Modify variable value

PHY_Write (PortNo, 17, reg); // Write back modified internal register

PHY_Write (PortNo, 16, 0x87fa) // Necessary write of internal register

PHY_Write (PortNo, 31, 0x0000); // Select main register page

VSC8601 Datasheet

Design Considerations

Revision 4.1

September 2009 Page 101

8.10 High VDD33 and Low VDDIOMAC Supply

Issue: If VDD33 is set to the maximum allowed 3.3 V supply and VDDIOMAC is set to

the minimum allowed 3.3 V supply, the VSC8601 device can experience performance

issues. These issues generally occur in a lab environment and not in typical

applications.

Implications: When VDDIOMAC is set to 3.3 V, VDD33 and VDDIOMAC cannot be

sourced by two different 3.3 V supplies.

Workaround: If using VDDIOMAC in 3.3 V mode, use the same 3.3 V source supply as

the VDD33, using a proper filtering scheme. For more information, see VSC8601 Design

and Layout Guide, which is available on the Vitesse Web site at www.vitesse.com.

VSC8601 Datasheet

Ordering Information

Revision 4.1

September 2009 Page 102

9 Ordering Information

The VSC8601 package is a lead(Pb )-free, 64-pin, plastic low-profile quad flat package

(LQFP) with an exposed pad, 10 mm × 10 mm body size, 1.4 mm body thickness,

0.5 mm pin pitch, and 1.6 mm maximum height.

Lead(Pb)-free products from Vitesse comply with the temperatures and profiles defined

in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see

the IPC and JEDEC standard.

The following table lists the ordering information for the VSC8601 device.

Table 87. Ordering Information

Part Order Number Description

VSC8601XKN Lead(Pb)-free, 64-pin, plastic LQFP with an exposed pad,

10 mm × 10 mm body size, 1.4 m m body thickness, 0.5 mm pin pitch,

and 1.6 mm maximum height