50 MHz to 525 MHz Quadrature
Demodulator with Fractional-N PLL and VCO
Data Sheet ADRF6806
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
FEATURES
IQ demodulator with integrated fractional-N PLL
LO frequency range: 50 MHz to 525 MHz
For the following specifications (LPEN = 0)/(LPEN = 1):
Input P1dB: 12.2 dBm/10.6 dBm
Input IP3: 28.5 dBm/25.2 dBm
Noise figure (DSB): 12.2/11.4
Voltage conversion gain: 1 dB/4.2 dB
Quadrature demodulation accuracy
Phase accuracy: <0.5°
Amplitude accuracy: <0.1 dB
Baseband demodulation: 135 MHz, 3 dB bandwidth
SPI serial interface for PLL programming
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
QAM/QPSK RF/IF demodulators
Cellular W-CDMA/CDMA/CDMA2000
Microwave point-to-(multi)point radios
Broadband wireless and WiMAX
GENERAL DESCRIPTION
The ADRF6806 is a high dynamic range IQ demodulator with
integrated PLL and VCO. The fractional-N PLL/synthesizer
generates a frequency in the range of 2.8 GHz to 4.2 GHz. A
programmable quadrature divider (divide ratio = 4 to 80) divides
the output frequency of the VCO down to the required local
oscillator (LO) frequency to drive the mixers in quadrature.
Additionally, an output divider (divide ratio = 4 to 8) generates
a divided-down VCO signal for external use.
The PLL reference input is supported from 10 MHz to 160 MHz.
The phase detector output controls a charge pump whose output
is integrated in an off-chip loop filter. The loop filter output is
then applied to an integrated VCO.
The IQ demodulator mixes the differential RF input with the
complex LO derived from the quadrature divider. The differential
I and Q output paths have excellent quadrature accuracy and
can handle baseband signaling or complex IF up to 120 MHz.
A reduced power mode of operation is also provided by
programming the serial interface registers to reduce current
consumption, with slightly degraded input linearity and output
current drive.
The ADRF6806 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, exposed-paddle,
RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is
specified over the −40°C to +85°C temperature range.
FUNCTIONAL BLOCK DIAGRAM
MUX
RSET GND
LON
LOP
MUX
TEMP
SENSOR
GND
DECL3
VCCRF
V
CCLO
BUFFER
BUFFER
QBBN
V
CCLO
–
+CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
PRESCALER
÷2
VCO LDO2.5V LDO
LE
CLK SPI
INTERFACE
DATA
MUXOUT
REFIN
ADRF6806
34
GND LOSEL
35
19
QBBP
18
17
16
DECL1
40
VTUNE
39
DECL2 VCC2
9105
VCC1
2
VCC1
1
8
6
GND
7
14
GND
15
13
12
38
GND
11
37
36
GND
31
IBBNIBBP
3233
28
GND
27
RFIN
26
RFIP
25
GND
24
VOCM
23
VCCBB
22
GND
GND
21
20
29
30
PHASE
FREQUENCY
DETECTOR
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRACTION
REG MODULUS INTEGER
REG
N COUNTER
GND
4
CPOUT
3
×2
÷2
÷4
DIVIDER
÷2
TO
÷40
VCO
CORE
09335-001
BUFFER
CTRL
QUAD
÷2
DIV
÷4,
÷6,
÷8
Figure 1.
ADRF6806 Data Sheet
Rev. B | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Synthesizer/PLL .......................................................................... 12
Complementary Cumulative Distribution Functions (CCDF)
....................................................................................................... 13
Circuit Description......................................................................... 14
LO Quadrature Drive................................................................. 14
V-to-I Converter......................................................................... 14
Mixers .......................................................................................... 14
Emitter Follower Buffers ........................................................... 14
Bias Circuitry .............................................................................. 14
Register Structure....................................................................... 14
LO Divider Programming......................................................... 21
Programming Example.............................................................. 21
Applications Information.............................................................. 22
Basic Connections...................................................................... 22
Supply Connections ................................................................... 22
Synthesizer Connections........................................................... 22
I/Q Output Connections........................................................... 23
RF Input Connections ............................................................... 23
Charge Pump/VTUNE Connections ...................................... 23
LO Select Interface ..................................................................... 23
External LO Interface ................................................................ 23
Setting the Frequency of the PLL............................................. 23
Register Programming............................................................... 23
EVM Measurements .................................................................. 24
Evaluation Board Layout and Thermal Grounding................... 25
ADRF6806 Software .................................................................. 30
Characterization Setups................................................................. 32
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
REVISION HISTORY
3/12—Rev. A to Rev. B
Changes to Phase Noise—Using 67 kHz Loop Filter Parameter,
Table 1; Added Phase Noise—Using 2.5 kHz Loop Filter
Parameter, Table 1; Added PLL Figure of Merit (FOM)
Parameter, Table 1 ........................................................................ 4
Changes to Figure 21 and Figure 24 to Figure 26....................... 12
Changes to Figure 34...................................................................... 16
Changes to Figure 37...................................................................... 18
Changes to Figure 38...................................................................... 19
Changes to Figure 39...................................................................... 20
Changes to EVM Measurements Section and Figure 42,
Deleted Figure 43; Renumbered Sequentially ........................ 24
Changes to Figure 43...................................................................... 25
Added Figure 44.............................................................................. 26
Changes to Figure 46 and Figure 47............................................. 27
Changes to Table 7.......................................................................... 29
Changes to Figure 48...................................................................... 30
Changes to Figure 49...................................................................... 31
6/11—Rev. Sp0 to Rev. A
Data Sheet ADRF6806
Rev. B | Page 3 of 36
SPECIFICATIONS
VS1 (VVCCBB and VVCCRF) = 5 V, and VS2 (VVCC1, VVCC2, and VVCCLO) = 3.3 V; ambient temperature (TA) = 25°C; fREF = 26 MHz, fLO = 140 MHz,
fBB = 4.5 MHz, RLOAD = 450 differential, RF port driven from a 1:2 balun to step up the 50 Ω source impedance to match the 100 Ω
differential RF input port impedance, all register and PLL settings use the recommended values shown in the Register Structure section,
unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 50 525 MHz
RF INPUT @ 140 MHz RFIP, RFIN pins
Input Return Loss Relative to 100 Ω −11.7 dB
Input P1dB LPEN = 0 (standard power mode) 12.2 dBm
LPEN = 1 (low power mode) 10.6 dBm
Second-Order Input Intercept (IIP2) LPEN = 0; −5 dBm each tone >65 dBm
LPEN = 1; −5 dBm each tone >60 dBm
Third-Order Input Intercept (IIP3) LPEN = 0; −5 dBm each tone 28.5 dBm
LPEN = 1; −5 dBm each tone 25.2 dBm
Noise Figure Double sideband from RF to either I or Q output; LPEN = 0 12.2 dB
Double sideband from RF to either I or Q output; LPEN = 1 11.4 dB
With a −5 dBm interferer 5 MHz away 14 dB
LO-to-RF Leakage At 1×LO frequency, 100 Ω termination at the RF port −70 dBm
I/Q BASEBAND OUTPUTS IBBP, IBBN, QBBP, QBBN pins
Voltage Conversion Gain 450 Ω differential load across IBBP, IBBN (or QBBP, QBBN);
LPEN = 0
1 dB
450 Ω differential load across IBBP, IBBN (or QBBP, QBBN);
LPEN = 1
4.2 dB
Demodulation Bandwidth 1 V p-p signal 3 dB bandwidth; LPEN = 0 170 MHz
1 V p-p signal 3 dB bandwidth; LPEN = 1 135 MHz
Quadrature Phase Error 0.3 Degrees
I/Q Amplitude Imbalance 0.05 dB
Output DC Offset (Differential) ±8 mV
Output Common-Mode Reference VOCM applied input voltage 1.55 1.65 1.75 V
Common-Mode Offset |(VIBBP + VIBBN)/2 − VVOCM|, |(VQBBP + VQBBN)/2 − VVOCM| 25 mV
Gain Flatness Any 5 MHz 0.2 dB p-p
Maximum Output Swing Differential 450 Ω load 3 V p-p
Differential 200 Ω load 2.4 V p-p
Maximum Output Current Each pin 6 mA p-p
LO INPUT/OUTPUT LOP, LON
Output Level (LPEN = 0) Into a differential 50 Ω load, LO buffer enabled (output
frequency = 800 MHz)
1 dBm
Output Level (LPEN = 1) Into a differential 50 Ω load, LO buffer enabled (output
frequency = 800 MHz)
−0.75 dBm
Input Level Externally applied 2×LO, PLL disabled 0 dBm
Input Impedance Externally applied 2×LO, PLL disabled 50 Ω
LO Main Divider Range VCO to mixer, including quadrature divider, see Table 5 for
supported divider modes
8 80
VCO Output Divider Range VCO to (LOP, LON), see Table 6 for supported output divider
modes
4 8
VCO Operating Frequency 2800 4200 MHz
SYNTHESIZER SPECIFICATIONS All synthesizer specifications measured with recommended
settings provided in Figure 33 through Figure 40
Channel Spacing fPFD = 26 MHz 25 kHz
PLL Bandwidth Can be adjusted with off-chip loop filter component values
and RSET
67 kHz
ADRF6806 Data Sheet
Rev. B | Page 4 of 36
Parameter Test Conditions/Comments Min Typ Max Unit
SPURS fLO = 140 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured at BB
outputs with fBB = 50 MHz
Reference Spurs fREF = 26 MHz, fPFD = 26 MHz −95 dBc
f
REF/2 −106 dBc
f
REF × 2 −100 dBc
f
REF × 3 −105 dBc
PHASE NOISE—USING 67 kHz LOOP
FILTER
fLO = 140 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured at BB
outputs with fBB = 50 MHz
@ 1 kHz offset −117 dBc/Hz
@ 10 kHz offset −124 dBc/Hz
@ 100 kHz offset −127 dBc/Hz
@ 500 kHz offset −146 dBc/Hz
@ 1 MHz offset −149 dBc/Hz
@ 5 MHz offset −151 dBc/Hz
@ 10 MHz offset −153 dBc/Hz
Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.03 °rms
PHASE NOISE—USING 2.5 kHz LOOP
FILTER
fLO = 900 MHz, fREF = 26 MHz, fPFD = 26 MHz, measured at BB
outputs with fBB = 50 MHz
@ 1 kHz offset −95 dBc/Hz
@ 10 kHz offset −110 dBc/Hz
@ 100 kHz offset −136 dBc/Hz
@ 500 kHz offset −149 dBc/Hz
@ 1 MHz offset −149.5 dBc/Hz
@ 5 MHz offset −151 dBc/Hz
@ 10 MHz offset −153 dBc/Hz
PLL FIGURE OF MERIT (FOM) Measured with fREF = 26 MHz, fPFD = 26 MHz −215.4 dBc/Hz/Hz
Measured with fREF = 104 MHz, fPFD = 26 MHz −220.9 dBc/Hz/Hz
Phase Detector Frequency 20 26 40 MHz
REFERENCE CHARACTERISTICS REFIN, MUXOUT pins
REFIN Input Frequency Usable range 9 160 MHz
REFIN Input Capacitance 4 pF
MUXOUT Output Level VOL (lock detect output selected) 0.25 V
V
OH (lock detect output selected) 2.7 V
REFOUT Duty Cycle 50 %
CHARGE PUMP
Pump Current 500 μA
Output Compliance Range 1 2.8 V
LOGIC INPUTS CLK, DATA, LE pins
Input High Voltage, VINH 1.4 3.3 V
Input Low Voltage, VINL 0 0.7 V
Input Current, IINH/IINL 0.1 μA
Input Capacitance, CIN 5 pF
POWER SUPPLIES VCC1, VCC2, VCCLO, VCCBB, VCCRF pins
Voltage Range (3.3 V) VCC1, VCC2, VCCLO 3.135 3.3 3.465 V
Voltage Range (5 V) VCCBB, VCCRF 4.75 5 5.25 V
Supply Current (3.3 V) (LPEN = 0) Normal Rx mode 209 mA
Rx mode with LO buffer enabled 270 mA
Supply Current (5 V) (LPEN = 0) Normal Rx mode 86 mA
Rx mode with LO buffer enabled 86 mA
Supply Current (3.3 V) (LPEN = 1) Normal Rx mode 205 mA
Rx mode with LO buffer enabled 258 mA
Data Sheet ADRF6806
Rev. B | Page 5 of 36
Parameter Test Conditions/Comments Min Typ Max Unit
Supply Current (5 V) (LPEN = 1) Normal Rx mode 75 mA
Rx mode with LO buffer enabled 75 mA
Supply Current (5 V) Power-down mode 10 mA
Supply Current (3.3 V) Power-down mode 15 mA
TIMING CHARACTERISTICS
VS1 (VVCCBB and VVCCRF) = 5 V, and VS2 (VVCC1, VVCC2, and VVCCLO) = 3.3 V.
Table 2.
Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments
t1 20 ns min LE Setup Time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width
C
LOC
K
DATA
LE
LE
DB23 (MSB) DB22 DB2 DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
09335-002
Figure 2. Timing Diagram
ADRF6806 Data Sheet
Rev. B | Page 6 of 36
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage, VCCBB and VCCRF (VS1) −0.5 V to +5.5 V
Supply Voltage, VCC1, VCC2, and VCCLO (VS2) −0.5 V to +3.6 V
Digital I/O, CLK, DATA, and LE −0.3 V to +3.6 V
RFIP and RFIN (Each Pin AC-Coupled) 13 dBm
θJA (Exposed Paddle Soldered Down) 30°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Data Sheet ADRF6806
Rev. B | Page 7 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
30
29
28
4
5
6
7
8
22
23
24
25
26
27
9
10 21
40
39
38
VCCLO
IBBN
LOSEL
IBBP
GND
32
33
34
35
36
37
31
20
19
18
12
13
14
15
16
17
11
RFIN
GND
LON
LOP
DECL1
GND
RSET
VCC1
CPOUT
VCC2
REFIN
DECL2
VCC1
THIRD-ORDER
SDM
VCO
BAND
CURRENT
CAL/SET
VCO
2800MHz
TO
2H400MHz
PHASE DETECTOR
AND
CHARGE PUMP
QUADRATURE
÷2
SERIAL
PORT
×2
ENABLE
VTUNE
PROGRAMABLE
DIVIDER
÷4
MUX
PRESCALER
÷2
VCO
LDO
2.5V
LDO
MUX
INTEGER
FRACTION
6
6
BLEED
SCALE
QBBN
GND
CLK
DATA
QBBP
VCCLO
LE
GND
GND
GND
VOCM
DECL3
GND
VCCBB
VCCRF
GND
GND
RFIP
GND
DIV
÷2
TO
÷40
DIV
÷4, ÷6, ÷8
MODULUS
BUFFER
CTRL
DIV
CTRL GND
COMMON-
MODE
LEVEL
CONTROL
MUXOUT
NOTES
1. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE.
÷2
DIV
CTRL
09335-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2 VCC1 The 3.3 V power supply for VCO and PLL.
3 CPOUT Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter.
4, 7, 11, 15, 16, 20,
21, 24, 27, 30, 31, 35
GND Connect these pins to a low impedance ground plane.
5 RSET
Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1 mA
using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this mode, no
external RSET is required. If DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be
externally tweaked according to the following equation where the resulting value is in units of ohms.
8.37
4.217 −
⎥
⎦
⎤
⎢
⎣
⎡×
=
NOMINAL
CP
SET I
I
R
6 REFIN Reference Input. Nominal input level is 1 V p-p. Input range is 9 MHz to 160 MHz.
ADRF6806 Data Sheet
Rev. B | Page 8 of 36
Pin No. Mnemonic Description
8 MUXOUT
Multiplexer Output. This output can be programmed to provide the reference output signal or the
lock detect signal. The output is selected by programming the appropriate register.
9 DECL2 Connect a 0.1 μF capacitor between this pin and ground.
10 VCC2 The 3.3 V power supply for the 2.5 V LDO.
12 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits.
13 CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
14 LE
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into
one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word.
17, 34 VCCLO The 3.3 V power supply for the LO path blocks.
18, 19 QBBP, QBBN Demodulator Q-Channel Differential Baseband Outputs (Differential Output Impedance of 28 Ω).
22 VCCBB The 5 V power supply for the demodulator blocks.
23 VOCM
Baseband Common-Mode Reference Input; 1.65 V nominal. It sets the dc common-mode level of
the IBBx and QBBx outputs.
25, 26 RFIP, RFIN Differential 100 Ω, Internally Biased RF Inputs. These pins must be ac-coupled.
28 VCCRF The 5 V power supply for the demodulator blocks.
29 DECL3 Connect a 2.2 μF capacitor between this pin and ground.
32, 33 IBBN, IBBP Demodulator I-Channel Differential Baseband Outputs (Differential Output Impedance of 28 Ω).
36 LOSEL
LO Select. Connect this pin to ground for the simplest operation and to completely control the LO
path and input/output direction from the register SPI programming.
For additional control without register reprogramming, this input pin can determine whether the
LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is set
low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The externally
applied LO drive must be at M×LO frequency (where M corresponds to the main LO divider setting). LON
and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set high and
the LXL bit of Register 5 (DB4) low. The output frequency is controlled by the LO output divider bits
in Register 7. This pin should not be left floating.
37, 38 LON, LOP Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency
divided version of the internal VCO is available on these pins. When the internal LO generation is
disabled, an external M×LO frequency signal can be applied to these pins (where M corresponds to
the main divider setting). (Differential Input/Output Impedance of 50 Ω)
39 VTUNE
VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input
voltage range on this pin is 1.0 V to 2.8 V.
40 DECL1
Connect a 10 μF capacitor between this pin and ground as close to the device as possible because
this pin serves as the VCO supply and loop filter reference.
EP Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
Data Sheet ADRF6806
Rev. B | Page 9 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
VS1 = 5 V, VS2 = 3.3 V, TA = 25°C, RF input balun loss is de-embedded, unless otherwise noted. LO = 50 MHz to 525 MHz; Mini-Circuits
ADTL2-18 balun on RF inputs.
0
2
4
6
8
10
12
14
16
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
CONVERSION GAIN (dB) AND INPUT P1dB (dBm)
LO FREQUENCY (MHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
LPEN = 0
LPEN = 1
IP1dB
GAIN
09335-004
Figure 4. Conversion Gain and Input P1dB vs. LO Frequency
20
22
24
26
28
30
32
34
36
38
40
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
INPUT IP3 (dBm)
LO FREQUENCY (MHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
LPEN = 0
LPEN = 1
09335-005
Figure 5. Input IP3 vs. LO Frequency
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
IQ GAIN MISM
A
TCH (dB)
LO FREQUENCY (MHz)
TA = +85°C
TA = +25°C
TA = –40°C
LPEN = 0
LPEN = 1
09335-006
Figure 6. IQ Gain Mismatch vs. LO Frequency
50
55
60
65
70
75
80
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
INPUT IP2 (dBm)
LO FREQUENCY (MHz)
LPEN = 1
LPEN = 0
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
I CHANNEL
Q CHANNEL
09335-007
Figure 7. Input IP2 vs. LO Frequency
5
6
7
8
9
10
11
12
13
14
15
16
17
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
NOISE FIGURE (dB)
LO FREQUENCY (MHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
LPEN = 0
LPEN = 1
09335-008
Figure 8. Noise Figure vs. LO Frequency
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
IQ QUAD
R
A
TURE PHASE ERROR (Degrees)
LO FREQUENCY (MHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
LPEN = 0
LPEN = 1
0
9335-009
Figure 9. IQ Quadrature Phase Error vs. LO Frequency
ADRF6806 Data Sheet
Rev. B | Page 10 of 36
–90
–85
–80
–75
–70
–65
–60
–55
–
50
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
LO-TO-RF FEEDTHROUGH (dBm)
LO FREQUENCY (MHz)
LPEN = 0
LPEN = 1
0
9335-010
Figure 10. LO-to-RF Feedthrough vs. LO Frequency, LO Output Turned Off
–70
–65
–60
–55
–50
–45
–40
–35
–
30
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
LO-TO-BB FEEDTHROUGH (dBV rms)
LO FREQUENCY (MHz)
LPEN = 0
LPEN = 1
09335-011
Figure 11. LO-to-BB Feedthrough vs. LO Frequency, LO Output Turned Off
–70
–65
–60
–55
–50
–45
–40
–35
–
30
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
RF-TO-BB FEEDTHROUGH (dBc)
RF FREQUENCY (MHz)
LPEN = 0
LPEN = 1
09335-012
Figure 12. RF-to-BB Feedthrough vs. RF Frequency
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
1 10 100 400
NORMALIZED BASEBAND
FREQUENCY RESPONSE (dB)
BASEBAND FREQUENCY (MHz)
LPEN = 0
LPEN = 1
09335-013
Figure 13. Normalized BB Frequency Response
0
10
20
30
40
50
60
70
80
5 101520253035404550
INPUT P1dB (dBm), INPUT IP2 (dBm),
AND INPUT IP3 (dBm)
BASEBAND FREQUENCY (MHz)
IP1dB
IIP3
IIP2
LPEN = 0
LPEN = 1
LPEN = 0
LPEN = 1
LPEN = 0
LPEN = 1
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
I CHANNEL
Q CHANNEL
09335-014
Figure 14. Input P1dB, Input IP2, and Input IP3 vs. BB Frequency
8
10
12
14
16
18
20
22
24
26
28
30
–30 –25 –20 –15 –10 –5 0 5 10
NOISE FIGURE (dB)
INPUT BLOCKER POWER (dBm)
LPEN = 0
LPEN = 1
0
9335-015
Figure 15. Noise Figure vs. Input Blocker Level,
fLO = 140 MHz (RF Blocker 5 MHz Offset)
Data Sheet ADRF6806
Rev. B | Page 11 of 36
–30
–28
–26
–24
–22
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
RF RETURN LOSS (dB)
RF FREQUENCY (MHz)
09335-016
Figure 16. RF Input Return Loss vs. RF Frequency,
Measured Through ADTL2-18 2-to-1 Input Balun
–30
–28
–26
–24
–22
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
350
400
450
500
550
600
650
700
750
800
850
900
950
1000
1050
LO OUTPUT RETURN LOSS (dB)
LO OUTPUT FREQUENCY (MHz)
09335-017
Figure 17. LO Output Return Loss vs. LO Output Frequency,
LO Output Enabled (350 MHz to 1050 MHz)
60
85
110
135
160
185
210
235
260
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
CURRENT (mA)
LO FREQUENCY (MHz)
3.3V SUPPLY
5V SUPPLY
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
LPEN = 0
LPEN = 1
09335-018
Figure 18. 5 V and 3.3 V Supply Currents vs. LO Frequency,
LO Output Disabled
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
–40 –20 0 20 40 60 80
VPT
A
T VOLTAGE (V)
TEMPERATURE (°C)
LPEN = 0
LPEN = 1
09335-019
Figure 19. VPTAT vs. Temperature
0.5
1.0
1.5
2.0
2.5
3.0
3.5
350 370 390 410 430 450 470 490 510
VTUNE VOLTAGE (V)
LO FREQUENCY (MHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
09335-020
Figure 20. VTUNE vs. LO Frequency
ADRF6806 Data Sheet
Rev. B | Page 12 of 36
SYNTHESIZER/PLL
VS1 = 5 V, VS2 = 3.3 V, see the Register Structure section for recommended settings used. External loop filter bandwidth of ~67 kHz, fREF =
fPFD = 26 MHz, measured at BB output, fBB = 50 MHz, unless otherwise noted.
–160
–150
–140
–130
–120
–110
–100
–90
–
80
1k 10k 100k 1M 10M
PHASE NOISE (dBc/Hz)
OFFSET FREQUENCY (Hz)
2.5kHz LOOP FILTER
67kHz LOOP FILTER
T=‐
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
09335-021
Figure 21. Phase Noise vs. Offset Frequency, fLO = 140 MHz
–110
–105
–100
–95
–90
–85
–80
–75
–
70
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
PLL REFERENCE SPURS (dBc)
LO FREQUENCY (MHz)
1× PFD FREQUENCY
3× PFD FREQUENCY
0.5× PFD FREQUENCY
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
09335-022
Figure 22. PLL Reference Spurs vs. LO Frequency
–110
–105
–100
–95
–90
–85
–80
–75
–
70
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
PLL REFERENCE SPURS (dBc)
LO FREQUENCY (MHz)
2× PFD FREQUENCY
4× PFD FREQUENCY
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
09335-123
Figure 23. PLL Reference Spurs vs. LO Frequency
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
50 100 150 200 250 300 350 400 450 500
INTEGR
A
TED PHASE NOISE (°rms)
LO FREQUENCY (MHz)
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
09335-024
Figure 24. Integrated Phase Noise vs. LO Frequency (Spurs Omitted)
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–
60
40 90 140 190 240 290 340 390 440 490
PHASE NOISE (dBc/Hz)
LO FREQUENCY (MHz)
5MHz OFFSET
10kHz OFFSET
1kHz OFFSET
67kHz LOOP FILTER BANDWIDTH
2.5kHz LOOP FILTER BANDWIDTH
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
09335-125
Figure 25. Phase Noise vs. LO Frequency (1 kHz, 10 kHz, and 5 MHz Offsets)
TA = +85°C
TA = +25°C
TA = –40°C
–160
–150
–140
–130
–120
–110
–100
–90
–
80
40 90 140 190 240 290 340 390 440 490
PHASE NOISE (dBc/Hz)
LO FREQUENCY (MHz)
1MHz OFFSET
100kHz OFFSET
67kHz LOOP FILTER BANDWIDTH
2.5kHz LOOP FILTER BANDWIDTH
09335-126
Figure 26. Phase Noise vs. LO Frequency (100 kHz and 1 MHz Offsets)
Data Sheet ADRF6806
Rev. B | Page 13 of 36
COMPLEMENTARY CUMULATIVE DISTRIBUTION FUNCTIONS (CCDF)
VS1 = 5 V, VS2 = 3.3 V, fLO = 140 MHz, fBB = 4.5 MHz.
0
10
20
30
40
50
60
70
80
90
100
02468101214
CUMUL
A
TIVE DISTRIBUTION PERCENTAGE (%)
GAIN (dB) AND INPUT P1dB (dBm)
IP1dB
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
LPEN = 0
LPEN = 1
GAIN
09335-025
Figure 27. Gain and Input P1dB
0
10
20
30
40
50
60
70
80
90
100
20 22 24 26 28 30 32 34
CUMUL
A
TIVE DISTRIBUTION PERCENTAGE (%)
INPUT IP3 (dBm)
LPEN = 0
LPEN = 1
09335-026
TA = +85°C
TA = +25°C
TA = –40°C
I CHANNEL
Q CHANNEL
Figure 28. Input IP3
0
10
20
30
40
50
60
70
80
90
100
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
CUMUL
A
TIVE DISTRIBUTION PERCENTAGE (%)
IQ GAIN MISMATCH (dB)
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
LPEN = 0
LPEN = 1
09335-027
Figure 29. IQ Gain Mismatch
0
10
20
30
40
50
60
70
80
90
100
50 55 60 65 70 75 80
CUMUL
A
TIVE DISTRIBUTION PERCENTAGE (%)
INPUT IP2 (dBm)
LPEN = 1
LPEN = 0
TA = +85°C
TA = +25°C
TA = –40°C
I CHANNEL
Q CHANNEL
09335-028
Figure 30. Input IP2
0
10
20
30
40
50
60
70
80
90
100
0 2 4 6 8 101214161820
CUMUL
A
TIVE DISTRIBUTION PERCENTAGE (%)
NOISE FIGURE (dB)
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
LPEN = 0
LPEN = 1
0
9335-029
Figure 31. Noise Figure
0
10
20
30
40
50
60
70
80
90
100
–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
CUMUL
A
TIVE DISTRIBUTION PERCENTAGE (%)
IQ QUADRATURE PHASE ERROR (Degrees)
TA = +85°C
TA = +25°C
TA = –40°C
LPEN = 0
LPEN = 1
09335-030
Figure 32. IQ Quadrature Phase Error
ADRF6806 Data Sheet
Rev. B | Page 14 of 36
CIRCUIT DESCRIPTION
The ADRF6806 integrates a high performance IQ demodulator
with a state-of-the-art fractional-N PLL. The PLL also integrates
a low noise VCO. The SPI port allows the user to control the
fractional-N PLL functions, the demodulator LO divider functions,
and optimization functions, as well as allowing for an externally
applied LO.
The ADRF6806 uses a high performance mixer core that results
in an exceptional input IP3 and input P1dB, with a very low
output noise floor for excellent dynamic range.
LO QUADRATURE DRIVE
A signal at 2× the desired mixer LO frequency is delivered to
a divide-by-2 quadrature phase splitter followed by limiting
amplifiers which then drive the I and Q mixers, respectively.
V-TO-I CONVERTER
The differential RF input signal is applied to a V-to-I converter
that converts the differential input voltage to output currents. The
V-to-I converter provides a differential 100 Ω input impedance.
The V-to-I bias current can be reduced by putting the device in
low power mode (setting LPEN = 1 by setting Register 5, DB5 = 1).
Generally with LPEN = 1, input IP3 and input P1dB degrade,
but the noise figure is slightly better. Overall, the dynamic range
is reduced by setting LPEN = 1.
MIXERS
The ADRF6806 has two double-balanced mixers: one for the in-
phase channel (I channel) and one for the quadrature channel
(Q channel). These mixers are based on the Gilbert cell design
of four cross-connected transistors. The output currents from
the two mixers are summed together in the resistive loads that
then feed into the subsequent emitter follower buffers. When
the part is put into its low power mode (LPEN = 1), the mixer
core load resistors are increased, which does increase the gain by
roughly 3 dB; however, as previously stated in the V-to-I Converter
section, the overall dynamic range does decrease slightly.
EMITTER FOLLOWER BUFFERS
The output emitter followers drive the differential I and Q signals
off chip. The output impedance is set by on-chip 14 Ω series
resistors that yield a 28 Ω differential output impedance for each
baseband port. The fixed output impedance forms a voltage divider
with the load impedance that reduces the effective gain. For example,
a 500 Ω differential load has ~0.5 dB lower effective gain than a
high (10 kΩ) differential load impedance.
The common-mode dc output levels of the emitter follower
outputs are set by the voltage applied to the VOCM pin. The
VOCM pin must be driven with a voltage (typically 1.65 V) for
the emitter follower buffers to function. If the VOCM pin is left
open, the emitter follower outputs do not bias up properly.
BIAS CIRCUITRY
There are several band gap reference circuits and two low
droput regulators (LDOs) in the ADRF6806 that generate the
reference currents and voltages used by different sections. One of
the LDOs is the 2.5V_LDO, which is always active and provides
the 2.5 V supply rail used by the internal digital logic blocks.
The 2.5V_LDO output is connected to the DECL2 pin (Pin 9)
for the user to provide external decoupling. The other LDO is
the VCO_LDO, which acts as the positive supply rail for the
internal VCO. The VCO_LDO output is connected to the DECL1
pin (Pin 40) for the user to provide external decoupling. The
VCO_LDO can be powered down by setting Register 6, DB18 = 0,
which allows the user to save power when not using the VCO.
Additionally, the bias current for the mixer V-to-I stage, which
drives the mixer core, can be reduced by putting the device in
low power mode (setting LPEN = 1 by setting Register 5, DB5 = 1).
REGISTER STRUCTURE
The ADRF6806 provides access to its many programmable features
through a 3-wire SPI control interface that is used to program
the seven internal registers. The minimum delay and hold times
are shown in the timing diagram (see Figure 2). The SPI provides
digital control of the internal PLL/VCO as well as several other
features related to the demodulator core, on-chip referencing,
and available system monitoring functions. The MUXOUT pin
provides a convenient, single-pin monitor output signal that can
be used to deliver a PLL lock-detect signal or an internal voltage
proportional to the local junction temperature.
Note that internal calibration for the PLL must run when the
ADRF6806 is initialized at a given frequency. This calibration is
run automatically whenever Register 0, Register 1, or Register 2 is
programmed. Because the other registers affect PLL performance,
Register 0, Register 1, and Register 2 must always be programmed
last. For ease of use, starting the initial programming with
Register 7 and then programming the registers in descending
order ending with Register 0 is recommended. Once the PLL
and other settings are programmed, the user can change the
PLL frequency simply by programming Register 0, Register 1,
or Register 2 as necessary.
Data Sheet ADRF6806
Rev. B | Page 15 of 36
DIVIDE
MODE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0000000000000DMID6ID5ID4ID3ID2ID1ID0C3(0)C2(0)C1(0)
DM
0
1
ID6 ID5 ID4 ID3 ID2 ID1 ID0
0010101
0010110
0010111
0011000
... ... ... ... ... ... ...
... ... ... ... ... ... ...
0111000
... ... ... ... ... ... ...
... ... ... ... ... ... ...
1110111
1111000
1111001
1111010
1111011
...
...
119
120 (INTEGER MODE ONLY)
DIVIDE RATIO
21 (INTEGER MODE ONLY)
22 (INTEGER MODE ONLY)
23 (INTEGER MODE ONLY)
24
...
...
56 (DEFAULT)
INTEGER
INTEGER DIVIDE RATIO CONTROL BITS
DIVIDE MODE
FRACTIONAL (DEFAULT)
121 (INTEGER MODE ONLY)
122 (INTEGER MODE ONLY)
123 (INTEGER MODE ONLY)
09335-031
Figure 33. Integer Divide Control Register (R0)
Register 0—Integer Divide Control
With R0[2:0] set to 000, the on-chip integer divide control register
is programmed as shown in Figure 33. The internal VCO
frequency (fVCO) equation is
fVCO = fPFD × (INT + (FRAC/MOD)) × 2 (1)
where:
fVCO is the output frequency of the internal VCO.
INT is the preset integer divide ratio value (21 to 123 for integer
mode, 24 to 119 for fractional mode).
MOD is the preset fractional modulus (1 to 2047).
FRAC is the preset fractional divider ratio value (0 to MOD − 1).
The integer divide ratio sets the INT value in Equation 1. The
INT, FRAC, and MOD values make it possible to generate output
frequencies that are spaced by fractions of the PFD frequency.
Note that the demodulator LO frequency is given by fLO = fVCO/M,
where M is the programmed LO main divider (see Table 5).
Divide Mode
Divide mode determines whether fractional mode or integer mode
is used. In integer mode, the VCO output frequency, fVCO, is
calculated by
fVCO = fPFD × (INT) × 2 (2)
ADRF6806 Data Sheet
Rev. B | Page 16 of 36
Register 1—Modulus Divide Control
With R1[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in Figure 34. The MOD value is the preset
fractional modulus ranging from 1 to 2047.
MODULUS DIVIDE RATIO
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1)
MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0
0 0000000001
0 0000000010
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
1 1000000000
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
1 1111111111
MODULUS VALUE
...
...
2047
CONTROL BITS
1
1536 (DEFAULT)
2
...
...
09993-032
Figure 34. Modulus Divide Control Register (R1)
Register 2—Fractional Divide Control
With R2[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 35. The FRAC value is the preset
fractional modulus ranging from 0 to MOD − 1.
FD10FD9FD8FD7FD6FD5FD4FD3FD2FD1FD0
0 0000000000
0 0000000001
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
0 1100000000
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
FRACTIONAL VALUE MUST BE LESS THAN MODULUS
FRACTIONAL VALUE
0
1
...
...
768 (DEFAULT)
...
...
<MDR
FRACTIONAL DIVIDE RATIO
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CONTROL BITS
0000000000FD10FD9FD8FD7FD6FD5FD4FD3FD2FD1FD0C3(0)C2(1) C1(0)
09335-033
Figure 35. Fractional Divide Control Register (R2)
Register 3—Σ-Δ Modulator Dither Control
With R3[2:0] set to 011, the on-chip Σ- modulator dither control register is programmed as shown in Figure 36. The dither restart value
can be programmed from 0 to 217 to 1, though a value of 1 is typically recommended.
DITHER
ENABLE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 DITH1 DITH0 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)
DITH1 DITH0
00
01
10
11
DEN
0
1
DITHER
MAGNITUDE DITHER RESTART VALUE CONTROL BITS
DITHER MAGNITUDE
15 (DEFAULT)
7
3
1 (RECOMMENDED)
DITHER ENABLE
DISABLE
ENABLE (DEFAULT, RECOMMENDED)
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
00000000000000001
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
11111111111111111
0x00001 (DEFAULT)
...
...
0x1FFFF
DITHER RESTART
VALUE
09335-034
Figure 36. Σ-Δ Modulator Dither Control Register (R3)
Data Sheet ADRF6806
Rev. B | Page 17 of 36
Register 4—Charge Pump, PFD, and Reference Path
Control
With R4[2:0] set to 100, the on-chip charge pump, PFD, and
reference path control register is programmed as shown in
Figure 37.
The charge pump current is controlled by the base charge pump
current (ICP, BASE), and the value of the charge pump current
multiplier (ICP, MULT).
The base charge pump current can be set using an internal or
external resistor (according to DB18 of Register 4). When using
an external resistor, the value of ICP, BASE can be varied according to
[]
8.37
250
4.217
,−
⎥
⎦
⎤
⎢
⎣
⎡×
=BASECP
SET
I
R
The actual charge pump current can be programmed to be a
multiple (1, 2, 3, or 4) of the charge pump base current. The
multiplying value (ICP, MULT) is equal to 1 plus the value of the
DB11 and DB10 bits in Register 4.
The PFD phase offset multiplier (θPFD, OFS), which is set by Bit
DB16 to Bit DB12 of Register 4, causes the PLL to lock with a
nominally fixed phase offset between the PFD reference signal
and the divided-down VCO signal. This phase offset is used to
linearize the PFD-CP transfer function and can improve
fractional spurs. The magnitude of the phase offset is
determined by
MULTCP
OFSPFD
I,
,
5.22[deg]Φ
θ
=
Finally, the phase offset can be either positive or negative
depending on the value of the DB17 bit in Register 4.
The reference frequency applied to the PFD can be manipulated
using the internal reference path source. The external reference
frequency applied can be internally scaled in frequency by 2×,
1×, 0.5×, or 0.25×. This allows a broader range of reference
frequency selections while keeping the reference frequency
applied to the PFD within an acceptable range.
The ADRF6801 also provides a MUXOUT pin that can be
programmed to output a selection of several internal signals. The
default mode provides a lock-detect output that allows users to
verify when the PLL has locked to the target frequency. In addition,
several other internal signals can be routed to the MUXOUT pin as
described in Figure 37.
ADRF6806 Data Sheet
Rev. B | Page 18 of 36
CHARGE
PUMP
REF
PDF
PHASE
OFFSET
POLARITY
CP
CNTL
SRC
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)
CPC1 CPC0
00
01
10
11
CPS
0
1
CPP1 CPP0
00
01
10
11
CPB4 CPB3 CPB2 CPB1 CPB0
00000
00001
00110
01010
... ... ... ... ...
11111
CPBD
0
1
CPM
0
1
RS1 RS0
00
01
10
11
RMS2 RMS1 RMS0
000
001
010
011
100
101
110
111
10 × 22.5°/I
CP, MULT
(DEFAULT)
...
31 × 22.5°/I
CP, MULT
PFD PHASE OFFSET MULTIPLIER
0 × 22.5°/I
CP, MULT
1 × 22.5°/I
CP, MULT
6 × 22.5°/I
CP, MULT
(RECOMMENDED)
BOTH ON
PUMP DOWN
PUMP UP
TRISTATE (DEFAULT)
OUPUT MUX
SOURCE
INPUT REF
PATH
SOURCE
PFD PHASE OFFSET
MULTIPLIER VALUE
CHARGE
PUMP
CURRENT
MULTIPLIER
CHARGE
PUMP
CONTROL
PFD EDGE
SENSITIVITY CONTROL BITS
PFD ANTI-
BACKLASH
DELAY
PE0
0
1
REFERENCE PATH EDGE
SENSITIVITY
FALLING EDGE (RECOMMENDED)
RISING EDGE (DEFAULT)
PAB1 PAB0
00
01
10
11
PFD ANTIBACKLASH
DELAY
0ns (DEFAULT,
RECOMMENDED)
0.5ns
0.75ns
0.9ns
CHARGE PUMP
CONTROL
BUFFERED VERSION OF 0.5 × REFERENCE INPUT
CHARGE PUMP CONTROL SOURCE
CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL)
CONTROL FROM PFD (DEFAULT)
OUTPUT MUX SOURCE
LOCK DETECT (DEFAULT)
VPTAT
BUFFERED VERSION OF REFERENCE INPUT
PFD PHASE OFFSET POLARITY
NEGATIVE
POSITIVE (DEFAULT, RECOMMENDED)
CHARGE PUMP CURRENT
REFERENCE SOURCE
INTERNAL (DEFAULT)
EXTERNAL
0.25 × REFERENCE INPUT
CHARGE PUMP
CURRENT MULTIPLIER
1
2 (DEFAULT, RECOMMENDED)
3
4
INPUT REFERENCE
PATH SOURCE
2 × REFERENCE INPUT
REFERENCE INPUT (DEFAULT)
0.5 × REFERENCE INPUT
BUFFERED VERSION OF 2 × REFERENCE INPUT
TRISTATE
RESERVED (DO NOT USE)
PE1
0
1
DIVIDER PATH EDGE
SENSITIVITY
FALLING EDGE (RECOMMENDED)
RISING EDGE (DEFAULT)
... ... ... ... ... ...
... ... ... ... ... ...
RESERVED (DO NOT USE)
09335-035
Figure 37. Charge Pump, PFD, and Reference Path Control Register (R4)
Data Sheet ADRF6806
Rev. B | Page 19 of 36
Register 5—LO Path and Demodulator Control
With R5[DB5] = 1, the ADRF6806 is in a lower power operating
mode. The device is still fully functional in this lower power
mode, but the mixer performance is shifted (see the Typical
Performance Characteristics section for details on performance
differences). Setting R5[DB5] = 0 causes the ADRF6806 mixer
stage to run at a higher current, thereby achieving a higher IIP3.
Register 5 also controls whether the LOIP and LOIN pins act as
an input or output and whether the output driver is enabled as
detailed in Figure 38.
DEMOD
BIAS
ENABLE
LOW
POWER
MODE
ENABLE
LO
IN/OUT
CTRL
LO
OUTPUT
DRIVER
ENABLE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
DMBE
DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 LPEN LXL LDRV C3(1) C2(0) C1(1)
LDRV
0
1
LXL
0
1
LPEN
0
1
DISABLED
ENABLED (DEFAULT)
LO OUTPUT DRIVER
ENABLE
DRIVER OFF (DEFAULT)
DRIVER ON
DMBE
0
1
DISABLE
ENABLE (DEFAULT)
DEMOD BIAS ENABLE
LO IN/OUT CONTROL
LO OUTPUT (DEFAULT)
LO INPUT
LOW POWER MODE
CONTROL BITS
000 0 0000000 0
09335-036
Figure 38. LO Path and Demodulator Control Register (R5)
ADRF6806 Data Sheet
Rev. B | Page 20 of 36
Register 6—VCO Control and Enables
With R6[2:0] set to 110, the VCO control and enables register is
programmed as shown in Figure 39.
VCO band selection is normally selected based on BANDCAL
calibration; however, the VCO band can be selected directly using
Register 6. The VCO BS SRC determines whether the BANDCAL
calibration determines the optimum VCO tuning band or if the
external SPI interface is used to select the VCO tuning band
based on the value of the VCO band select.
The VCO amplitude can be controlled through Register 6. The
VCO amplitude setting can be controlled between 0 and 31
decimal, with a default value of 24.
The internal VCO can be disabled using Register 6. The internal
VCO LDO can be disabled if an external clean 3.0 V supply is
available.
The internal charge pump can be disabled through Register 6.
Normally, the charge pump is enabled.
CHARGE
PUMP
ENABLE
3.3V
SWITCH
ENABLE
VCO
ENABLE
VCO
SWITCH
VCO
BS
CSR
VBSRC
0
1
VCO EN
VCO LDO
ENABLE VCO AMPLITUDE VCO BAND SELECT
CHARGE PUMP ENABLE
VCO BAND CAL AND SW SOURCE CONTROL
BAND CAL (DEFAULT)
VCO SW
0
1
VCO SWITCH CONTROL FROM SPI
REGULAR (DEFAULT)
BAND CAL
SPI
VCO ENABLE
DISABLE
ENABLE (DEFAULT)
DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CONTROL BITS
DB23
CPEN L3EN VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)
LVEN
0
1
LVEN VCO LDO ENABLE
DISABLE
ENABLE (DEFAULT)
0
1
L3EN 3.3V SWITCH ENABLE
DISABLE
ENABLE (DEFAULT)
0
1
CPEN
DISABLE
ENABLE (DEFAULT)
0
1
000
VC5 VC4 VC3 VC2 VC1
00000
... ... ... ... ...
... ... ... ... ...
... ... ... ... ...
10111
...
63
VCO AMPLITUDE
0
...
...
01100 24 (RECOMMENDED)
01111
VC0
0
...
...
...
1
0
147
VBS5 VBS4 VBS3 VBS2 VBS1
00000
... ... ... ... ...
... ... ... ... ...
VCO BAND SELECT
FROM SPI
0
...
...
10000 32 (DEFAULT)
11111
VBS0
0
...
...
0
163
... ... ... ... ...
00100
...
0
...
8 (DEFAULT)
09335-037
Figure 39. VCO Control and Enables (R6)
Data Sheet ADRF6806
Rev. B | Page 21 of 36
Register 7—LO Divider Control
Register 7 controls the LO path main divider settings as well as the LO output path divider setting. Table 5 indicates how to program this
register to achieve various divider modes.
DIVIDER
SELECT
DIV A/B
CONTROL
OUTPUT DIV
CONTROL
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
DIVS1
DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 DIVAB1 DIVAB0 DIVS0 ODIV1 ODIV0 0 C3(1) C2(1) C1(1)
DIVAB1
0
0
2 (DEFAULT)
3
DIVIDE RATIO
CONTROL BITS
DIVAB0
0
1
1
1
4 (NOT VALID FOR DIVB)
5 (NOT VALID FOR DIVB)
0
1
DIVS1
0
0
DIV B ONLY (DEFAULT)
DIV A FOLLOWED BY ÷ 2
DIVIDE RATIODIVS0
0
1
1
1
DIV A FOLLOWED BY ÷ 4
DIV A FOLLOWED BY ÷ 8
0
1
ODIV1
0
0
4 (DEFAULT)
4
DIVIDE RATIOODIV0
0
1
1
1
6
8
0
1
00000000000 0
09335-038
Figure 40. LO Divider Control Register (R7)
LO DIVIDER PROGRAMMING
Table 5. Main Divider (Only Divide Ratios and Combinations Specified Are Guaranteed)
Divider Cascade
fLO (MHz)
LO Divider
Ratio fVCO (MHz) Divide-by-2 to Divide-by-5
Divide-by-2, Divide-by-4, or
Divide-by-8
Quadrature
Divide-by-2
Register 7
DB[9:6]
35 to 52.5 80 2800 to 4200 5 8 2 11 11
43.75 to 65.62 64 2800 to 4200 4 8 2 10 11
58.33 to 87.5 48 2800 to 4200 3 8 2 01 11
70 to 105 40 2800 to 4200 5 4 2 11 10
87.5 to 131.25 32 2800 to 4200 4 4 2 10 10
116.7 to 175 24 2800 to 4200 3 4 2 01 10
140 to 210 20 2800 to 4200 5 2 2 11 01
175 to 262.5 16 2800 to 4200 4 2 2 10 01
233.3 to 350 12 2800 to 4200 3 2 2 01 01
350 to 525 8 2800 to 4200 2 2 2 00 01
Table 6. Output Divider
fLO Output (MHz) Output Divider Ratio fVCO (MHz) Register 7DB[5:4]
350 to 525 8 2800 to 4200 11
466.67 to 700 6 2800 to 4200 10
700 to 1050 4 2800 to 4200 01
PROGRAMMING EXAMPLE
For example, internal LO frequency = 140 MHz. This can be accomplished with the VCO/PLL frequency at 2800 MHz and an LO divide
ratio of 20. The choice of output divider ratio of 8 gives an output frequency of 350 MHz. To achieve this combination, a binary code of
11 01 11 should be programmed into DB[9:4] of Register 7.
ADRF6806 Data Sheet
Rev. B | Page 22 of 36
APPLICATIONS INFORMATION
BASIC CONNECTIONS
The basic circuit connections for a typical ADRF6806 application
are shown in Figure 41.
SUPPLY CONNECTIONS
The ADRF6806 has several supply connections and on-board
regulated reference voltages that should be bypassed to ground
using low inductance bypass capacitors located in close proximity
to the supply and reference pins of the ADRF6806. Specifically
Pin 1, Pin 2, Pin 9, Pin 10, Pin 17, Pin 22, Pin 23, Pin 28, Pin 29,
Pin 34, and Pin 40 should be bypassed to ground using individual
bypass capacitors. Pin 40 is the decoupling pin for the on-board
VCO LDO, and for best phase noise performance, several bypass
capacitors ranging from 100 pF to 10 µF may help to improve
phase noise performance. For additional details on bypassing the
supply nodes, see the evaluation board schematic in Figure 43.
SYNTHESIZER CONNECTIONS
The ADRF6806 includes an on-board VCO and PLL for LO
synthesis. An external reference must be applied for the PLL to
operate. A 1 V p-p nominal external reference must be applied
to Pin 6 through an ac coupling capacitor. The reference is
compared to an internally divided version of the VCO output
frequency to create a charge pump error current to control and
lock the VCO. The charge pump output current is filtered and
converted to a control voltage through the external loop filter
that is then applied to the VTUNE pin (Pin 39). ADIsimPLL™
can be a helpful tool when designing the external charge pump
loop filter. The typical Kv of the VCO, the charge pump output
current magnitude, and PFD frequency should all be considered
when designing the loop filter. The charge pump current magnitude
can be set internally or with an external RSET resistor connected to
Pin 5 and ground, along with the internal digital settings applied to
the PLL (see the Register 4—Charge Pump, PFD, and Reference
Path Control section for more details).
40 39 38 37 36 35 34 33 32 31
11
12 13 14 15 16 17 18 19 20
1
2
3
4
5
6
7
8
9
10 21
22
23
24
25
26
27
28
29
30
IBBN
LOSEL
IBBP
GND
VCCLO
LON
LOP
DECL1
VTUNE
GND
RFIN
VOCM
GND
VCCBB
GND
GND
RFIP
GND
VCCRF
DECL3
QBBN
GND
CLK
DATA
QBBP
VCCLO
LE
GND
GND
GND
MUXOUT
GND
RSET
VCC1
GND
CPOUT
VCC2
REFIN
VCC1
DECL2
ADRF6806
+3.3V
+3.3
V
+5V
RF INPUT
+5V
+3.3V
EXTERNAL
REFERENCE
MONITOR
OUTPUT
R2
OPEN
+3.3V
SPI CONTROL
BB Q-OUTPUT
BALUN IF Q-OUTPUT
RF INPUT
BALUN
BB I-OUTPUT
BALUN IF I-OUTPUT
CHARGE PUMP
LOOP FILTER
+1.65V
+3.3V
09335-039
Figure 41. Basic Connections
Data Sheet ADRF6806
Rev. B | Page 23 of 36
I/Q OUTPUT CONNECTIONS
The ADRF6806 has I and Q baseband outputs. Each output
stage consists of emitter follower output transistors with a low
differential impedance of 28 Ω and can source up to 12 mA p-p
differentially. A Mini-Circuits TCM9-1+ balun is used to trans-
form a single-ended 50 Ω load impedance into a nominal 450 Ω
differential impedance.
RF INPUT CONNECTIONS
The ADRF6806 uses a Mini-Circuits ADTL2-18+ balun with a 2:1
impedance ratio to transform a single-ended 50 Ω impedance
into a differential 100 Ω impedance. Coupling capacitors whose
impedance is small compared to 100 Ω at the frequency of operation
are used to isolate the dc bias points of the RF input stage.
CHARGE PUMP/VTUNE CONNECTIONS
The ADRF6806 uses a loop filter to create the VTUNE voltage
for the internal VCO. The loop filter in its simplest form is an
integrating capacitor. It converts the current mode error signal
coming out of the CPOUT pin into a voltage in which to control
the VCO via the VTUNE voltage. The stock filter on the
evaluation board has a bandwidth of 67 kHz. The loop filter
contains five components, three capacitors, and two resistors.
Changing the values of these components changes the
bandwidth of the loop filter.
LO SELECT INTERFACE
The ADRF6806 has the option of either monitoring a scaled
version of the internally generated LO (LOSEL pin driven high
at 3.3 V) or providing an external LO source (LOSEL pin driven
low to ground, the LDRV bit in Register 5 set low, and the LXL bit
in Register 5 set high). See the Pin Configuration and Function
Descriptions section for full operation details.
EXTERNAL LO INTERFACE
The ADRF6806 provides the option to use an external signal
source for the LO into the IQ demodulating mixer core. It is
important to note that the applied LO signal is divided down by
a divider (programmable to between 4 and 80) prior to the actual
IQ demodulating mixer core. The divider is determined by the
register settings in the LO path and mixer control register (see
the Register 5—LO Path and Demodulator Control section).
The LO input pins (Pin 37 and Pin 38) present a broadband
differential 50 Ω input impedance. The LOP and LON input
pins must be ac-coupled. This is achieved on the evaluation
board via a Mini-Circuits TC1-1-13+ balun with a 1:1 impedance
ratio. When not in use, the LOP and LON pins can be left
unconnected.
SETTING THE FREQUENCY OF THE PLL
The frequency of the VCO/PLL, once locked, is governed by the
values programmed into the PLL registers, as follows:
fPLL = fPFD × 2 × (INT + FRAC/MOD)
where:
fPLL is the frequency at the VCO when the loop is locked.
fPFD is the frequency at the input of the phase frequency detector.
INT is the integer divide ratio programmed into Register 0.
MOD is the modulus divide ratio programmed into Register 1.
FRAC is the fractional value programmed into Register 2.
The practical lower limit of the reference input frequency is
determined by the combination of the desired fPLL and the maximum
programmable integer divide ratio of 119 and reference input
frequency multiplier of 2. For a maximum fPLL of 4200 MHz,
fREF > ~fPLL/(fPFD × 2 × 2), or 8.8 MHz.
A lock detect signal is available as one of the selectable outputs
through the MUXOUT pin, with logic high signifying that the
loop is locked.
REGISTER PROGRAMMING
Because Register 6 controls the powering of the VCO and
charge pump, it must be programmed once before programming
the PLL frequency (Register 0, Register 1, and Register 2).
The registers should be programmed starting with the highest
register (Register 7) first and then sequentially down to Register 0
last. When Register 0, Register 1, or Register 2 is programmed,
an internal VCO calibration is initiated that must execute when
the other registers are set. Therefore, the order must be Register 7,
Register 6, Register 5, Register 4, Register 3, Register 2, Register 1,
and then Register 0. Whenever Register 0, Register 1, or Register 2
is written to, it initializes the VCO calibration (even if the value
in these registers does not change). After the device has been
powered up and the registers configured for the desired mode of
operation, only Register 0, Register 1, or Register 2 must be
programmed to change the LO frequency.
If none of the register values is changing from their defaults,
there is no need to program them.
ADRF6806 Data Sheet
Rev. B | Page 24 of 36
EVM MEASUREMENTS Figure 42 shows that the ADRF6806 exhibited excellent EVM
performance, with the EVM being better than −40 dB over an
RF input range of about +35 dB for a 4 QAM modulated signal
at a 5 MHz symbol rate at a 0 Hz IF. The pulse shaping filter’s
roll-off, or alpha, was set to 0.35. EVM and was tested for both
power modes: lower power mode disabled (LPEN = 0) and low
power mode enabled (LPEN = 1). When low power mode was
enabled, the EVM was better at lower RF input signal levels due
to less noise while running in low power mode. While in normal
power mode (LPEN = 0), the EVM remained undegraded at
higher RF input signal levels.
EVM is a measure used to quantify the performance of a digital
radio transmitter or receiver. A signal received by a receiver has
all constellation points at their ideal locations; however, various
imperfections in the implementation (such as magnitude
imbalance, noise floor, and phase imbalance) cause the actual
constellation points to deviate from their ideal locations.
In general, a demodulator exhibits three distinct EVM limitations
vs. received input signal power. As signal power increases, the
distortion components increase. At large enough signal levels,
where the distortion components due to the harmonic non-
linearities in the device are falling in-band, EVM degrades
as signal levels increase. At medium signal levels, where the
demodulator behaves in a linear manner and the signal is well
above any notable noise contributions, the EVM has a tendency to
reach an optimal level determined dominantly by either quadrature
accuracy and I/Q gain match of the demodulator or the precision
of the test equipment. As signal levels decrease, such that the
noise is a major contribution, the EVM performance vs. the signal
level exhibits a decibel-for-decibel degradation with decreasing
signal level. At lower signal levels, where noise proves to be the
dominant limitation, the decibel EVM proves to be directly
proportional to the SNR.
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
EVM (dB)
RF INPUT POWER (dBm)
09335-142
–60 –50 –40 –30 –20 –10 0 10 20
LPEN = 0
LPEN = 1
The basic test setup to test EVM for the ADRF6806 consisted of an
Agilent E4438C, which was used as a signal source. The 140 MHz
modulated signal was driven single-ended into the RFIN SMA
connector of the ADRF6806 evaluation board. The IQ baseband
outputs were taken differentially into a pair of AD8130 difference
amplifiers to convert the differential signals to single-ended. The
output impedance driven by the ADRF6806 was set to 450 Ω
differential. The single-ended I and Q signals were then sampled
by an Agilent DSO7104B oscilloscope. The Agilent 89600 VSA
software was used to calculate the EVM of the signal. The signal
source used for the reference input was a Wenzel 100 MHz quartz
oscillator set to an amplitude of 1 V p-p. The reference path was
set to divide-by-four, resulting in a PFD frequency of 25 MHz.
Figure 42. EVM Measurements @ 140 MHz 16 QAM; Symbol Rate = 5 MHz;
BB IF Frequency of 5 MHz
Data Sheet ADRF6806
Rev. B | Page 25 of 36
EVALUATION BOARD LAYOUT AND THERMAL GROUNDING
An evaluation board is available for testing the ADRF6806. The
evaluation board schematic is shown in Figure 43.
Tabl e 7 provides the component values and suggestions for
modifying the component values for the various modes of
operation.
40 39 38 37 36 35 34 33 32 31
11
12 13 14 15 16 17 18 19 20
1
2
3
4
5
6
7
8
9
10 21
22
23
24
25
26
27
28
29
30
IBBN
LOSEL
IBBP
GND
VCCLO
LON
LOP
DECL1
VTUNE
GND
RFIN
VOCM
GND
VCCBB
GND
GND
RFIP
GND
VCCRF
DECL3
QBBN
GND
CLK
DATA
DATA
QBBP
VCCLO
LE
GND
GND
GND
MUXOUT
GND
RSET
VCC1
GND
CPOUT
VCC2
REFIN
VCC1
DECL2
ADRF6806
VCC3
0.1µF 100pF
CP
LO VCC_LO
10µF
DECL3
100pF
VCC_RF
1nF
1nF
RFIN
100pF
VCC_BB
1000pF
1000pF
C14
300pF C15
6.2nF
R10
1.6kΩ
9
R
QOUT_SE
0.1µF
100pF
VCC_LO
REFIN
REFOUT
2P5V 0Ω
0Ω
0Ω
0Ω
0Ω
VCC2
NET NAME
TEST POINT
49.9Ω
1nF
R47
R48
R44
R43
R42
C29
0.1µF
T3
P3
T4
T1
R2
R8
C12
C11
C10
100pF
C9
0.1µF
R7
C36
100pF
C26
C24
R28
C25
R6
0Ω
C8
100pF
C7
0.1µF
C6 C5
R37
R38
5.6kΩ
C13
62pF
R1
R12
R11
C1
100pF
C2
0.1µF
VCO_LDO
C31
R26
R16
R18
C16
100pF
C17
0.1µF
C27
10µF
2P5V_LDO
R17
C18
100pF
C19
0.1µF
10µF
C3
OPEN
R50
OPEN
CLK
C32
OPEN
R51
OPEN
C33 OPEN
R52
OPEN
C34
LE
GND
GND1
GND2
C21 C20
R24
C22 C23
R25
C38
C39
VCC_RF VCC_BB
R29 R32
VCC
C28
10µF
OPEN
OPEN
OPEN
C4
10µF
R15
R13
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
R27
R34
10µF
C37
R14
VCC3
3.3V_FORCE
3.3V_SENSE
R21
R22
2
4
5
1
3
QBBP
QBBN
R23
OPEN
OPEN
C40
4
61
3
IOUT_SE
R41
R40
R39
C30
0.1µF
0.1µF
0.1µF
0.1µF
T2
0Ω
R4
2
4
51
3
IBBP
IBBN
R3
OPEN
OPEN
R46
OPEN
R45
R56
R55
10kΩ
10kΩ
VCC
S1
13
452
C35
10µF
OPEN
R49
3P3V1
3P3V2
VCC_LO1
DIG_GND
VCC_BB1
VOCM
R62
4.99kΩ
4.99kΩ
R63
3P3V_FORCE
VOCM
P1
VCC_RF
R31
0Ω
3P3V_FORCE
VCC_LO VCC
P2
0Ω
0Ω
0Ω
0Ω0Ω
R5
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
09993-042
OPEN
DATA CLK LE
JP1
SMA INPUT/OUTPUT
Figure 43. Evaluation Board Schematic
ADRF6806 Data Sheet
Rev. B | Page 26 of 36
56 55 54 53 52 51 50 49
15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
835
36
37
38
39
40
41
42
PD7_FD15
PD4_FD12
PD6_FD14
PD5_FD13
GND
CLKOUT
GND
VCC
PA5_FIFOARD1
PA2_SLOE
RESET_N
PA3_WU2
PA4_FIFOARD0
PA6_PKTEND
PA7_FLAGD_SCLS_N
GND
VCC
SDA
PB4_FD4
PB3_FD3
PB0_FD0
SCL
PB1_FD1
PB2_FD2
DPLUS
XTALOUT
XTALIN
RDY1_SLWR
AVCC
AVCC
AGND
RDY0_SLRD
CY7C68013A-56LTXC
U4
LE
9DMINUS
10 AGND
11 VCC
12 GND
13 IFCLK
14 RESERVED
23
PB5_FD5
24
PB6_FD6
27
VCC
25
PB7_FD7
26
GND
28
GND
29
30
31
32
33
34
CTL1_FLAGB
PA1_INT1_N
CTL0_FLAGA
CTL2_FLAGC
VCC
PA0_INT0_N
48 47 46 45 44 43
WAKEUP
VCC
PD0_FD8
PD1_FD9
PD3_FD11
PD2_FD10
CLK
DATA
3V3_USB
3V3_USB
3V3_USB
C48
10pF
C49
0.1µF
3V3_USB
3V3_USB
R61
2kΩ
CR2
3V3_USB
R64
100kΩ
C58
0.1µF
C45
0.1µF
R62
100kΩ
3V3_USB
Y1
24MHz
3
4 2
1
C54
22pF
C51
22pF
1
2
3
4
5
G1
G2
G3
G4
5V_USB
P5
A0
A1
A2
GND
SDA
SCL
WC_N
VCC
3V3_USB
3V3_USB
24LC64-I_SN
U2
ADP3334
U3
18
2
3
4
7
6
5
OUT1
OUT2
FB
NC
IN2
IN1
SD
GND
1
8
2
3
4
7
6
5
C47
1.0µF R65
2kΩ
CR1
5V_USB
R69
78.7kΩ
C50
1000pF
R70
140kΩ
C52
1.0µF
3V3_USB
DGND
C53
0.1µF
C42
0.1µF
C55
0.1µF
C41
0.1µF
C43
0.1µF
C44
0.1µF
C46
0.1µF
3V3_USB
R60
2kΩ
R19
2kΩ
C56
10pF
C57
0.1µF
09335-046
Figure 44.
Data Sheet ADRF6806
Rev. B | Page 27 of 36
The package for the ADRF6806 features an exposed paddle on
the underside that should be well soldered to an exposed
opening in the solder mask on the evaluation board. Figure 45
illustrates the dimensions used in the layout of the ADRF6806
footprint on the ADRF6806 evaluation board (1 mil. = 0.0254 mm).
Note the use of nine via holes on the exposed paddle. These
ground vias should be connected to all other ground layers on
the evaluation board to maximize heat dissipation from the device
package. Under these conditions, the thermal impedance of the
ADRF6806 was measured to be approximately 30°C/W in still air.
0.168
0.232
0.177
0.035
0.050
0.012
0.025
0.020
0
9335-043
Figure 45. Evaluation Board Layout Dimensions for the ADRF6806 Package
09335-044
Figure 46. ADRF6806 Evaluation Board Top Layer
0
9335-045
Figure 47. ADRF6806 Evaluation Board Bottom Layer
ADRF6806 Data Sheet
Rev. B | Page 28 of 36
Table 7. Evaluation Board Configuration Options
Component Function Default Condition
VCC, VCC2, VCC_LDO, VCC_LO,
VCC_LO1, VCC_RF, VCC_BB1, 3P3V1,
3P3V2, 3P3V_FORCE, 2P5V, CLK,
DATA, LE, CP, DIG_GND, GND, GND1,
GND2
Power supply, ground and other test points.
Connect a 5 V supply to VCC. Connect a 3.3 V
supply to 3P3V_FORCE.
VCC, VCC2, VCC_LO, VCC_RF, VCC_BB1,
VCC_LO1, VCO_LDO, 3P3V1, 3P3V2, 2P5V =
Components Corporation TP-104-01-02,
CP, LE, CLK, DATA, 3P3V_FORCE =
Components Corporation TP-104-01-06,
GND, GND1, GND2, DIG_GND =
Components Corporation TP-104-01-00
R1, R6, R7, R8, R13, R14, R15, R17,
R18, R24, R25, R27, R28, R29, R31,
R32, R34, R36, R49
Power supply decoupling. Shorts or power supply
decoupling resistors.
R1, R6, R7, R8 = 0 Ω (0402),
R13, R14, R15, R17 = 0 Ω (0402),
R18, R24, R25, R27 = 0 Ω (0402),
R28, R29, R31, R32 = 0 Ω (0402),
R34, R36 = 0 Ω (0402),
R49 = open (0402)
C1, C2, C3, C4, C7, C8, C9, C10, C11,
C12, C16, C17, C18, C19, C20, C21,
C22, C23, C24, C25, C26, C27, C28,
C35, C36, C37, C40
The capacitors provide the required decoupling of
the supply-related pins.
C1, C8, C10, C12 = 100 pF (0402),
C16, C18, C21, C22 = 100 pF (0402),
C24, C26 = 100 pF (0402),
C2, C7, C9, C11 = 0.1 μF (0402),
C17, C19, C20, C23 = 0.1 μF (0402),
C25, C40 = 0.1 μF (0402),
C3, C4, C27, C35 = 10 μF (0603),
C36, C37 = 10 μF (0603),
C28 = 10 μF (3216)
T1, C5, C6 External LO path. The T1 transformer provides
single-ended-to-differential conversion. C5 and C6
provide the necessary ac coupling.
C5, C6 = 1 nF (0603),
T1 = TC1-1-13+ Mini-Circuits
R16, R26, R58, C31 REFIN input path. R26 provides a broadband 50 Ω
termination followed by C31, which provides the
ac coupling into REFIN. R16 provides an external
connectivity to the MUXOUT feature described in
Register 4. R58 provides option for connectivity to
the P1-6 line of a 9-pin D-sub connector for dc
measurements.
R26 = 49.9 Ω (0402),
R16 = 0 Ω (0402),
R58 = open (0402),
C31 = 1 nF (0603)
R2, R9, R10, R11, R12, R37, R38, R59,
C14, C15, C13
Loop filter component options. A variety of loop
filter topologies is supported using component
placements C13, C14, C15, R9, and R10. R38 and
R59 provide connectivity options to numerous test
points for engineering evaluation purposes. R2
provides resistor programmability of the charge
pump current (see Register 4 description). R37
connects the charge pump output to the loop filter.
R12 references the loop filter to the VCO_LDO.
R12, R37, R38 = 0 Ω (0402),
R59 = open (0402),
R9 = 5.6 kΩ (0402),
R10 = 1.6 kΩ (0402),
R2, R11 = open (0402),
C13 = 62pF (0402),
C14 = 300pF (0402),
C15 = 6.2nF (1206)
R3, R4, R5, R21, R22, R23, R39, R40,
R41, R42, R43, R44, R45, R46, R47,
R48, C29, C30, T2, T3, P2, P3
IF I/Q output paths. The T2 and T3 baluns provide a
9:1 impedance transformation; therefore, with a 50 Ω
load on the single-ended IOUT/QOUT side, the center
tap side of the balun presents a differential 450 Ω
to the ADRF6806. The center taps of the baluns are
ac grounded through C29 and C30. The baluns create
a differential-to-single-ended conversion for ease
of testing and use, but an option to have straight
differential outputs is achieved via populating R3,
R39, R23, and R42 with 0 Ω resistors and removing
R4, R5, R21, and R22. P2 and P3 are differential
measurement test points (not to be used as jumpers).
R4, R5, R21, R22, = 0 Ω (0402),
R40, R43, R45, R46 = 0 Ω (0402),
R47, R48 = 0 Ω (0402),
R3, R23, R39, R41, R42, R44 = open (0402),
C29, C30, = 0.1 μF (0402),
T2, T3 = TCM9-1+ Mini-Circuits,
P2, P3 = Samtec SSW-102-01-G-S
C38, C39, T4 RF input interface. T4 provides the single-ended-
to-differential conversion required to drive RFIP and
RFIN. T4 provides a 2:1 impedance transformation.
A single-ended 50 Ω load on the RFIN SMA
connector transforms to a differential 100 Ω
presented across the RFIP (Pin 25) and RFIN (Pin 26)
pins. C38 and C39 are ac coupling capacitors.
C38, C39 = 1000 pF (0402),
T4 = ADTL2-18+ Mini-Circuits
Data Sheet ADRF6806
Rev. B | Page 29 of 36
Component Function Default Condition
R50, R51, R52, C32, C33, C34 Serial port interface. Optional RC filters can be
installed on the CLK, DATA, and LE lines to filter the
PC signals through R50 to R52 and C32 to C34. CLK,
DATA, and LE signals can be observed via test points
for debug purposes.
R50, R51, R52 = open (0402),
C32, C33, C34 = open (0402)
R33, R55, R56, S1 LO select interface. The LOSEL pin, in combination
with the LDRV and LXL bits in Register 5, controls
whether the LOP and LON pins operate as inputs or
outputs. A detailed description of how the LOSEL pin,
LDRV bit, and the LXL bit work together to control
the LOP and LON pins is found in Table 4 under the
LOSEL pin description. Using the S1 switch, the
user can pull LOSEL to a logic high (VCC/2) or a logic
low (ground). Resistors R55 and R56 form a resistor
divider to provide a logic high of VCC/2. LO select
can also be controlled through Pin 9 of J1. The 0 Ω
jumper, R33, must be installed to control LOSEL via J1.
R33 = 0 Ω (0402),
R55, R56 = 10 kΩ (0402),
S1 = Samtec TSW-103-08-G-S
J1, P1, R62, R63 Engineering test points and external control. J1 is a
10-pin connector connected to various important
points on the evaluation board that the user can
measure or force voltages upon. R62 and R63 form
a voltage divider to force a voltage of 1.65 V on
VOCM. Note that Jumper P5 must be connected to
drive VOCM with the resistor divider.
R62 = R63 = 4.99 kΩ (0402),
P1 = Samtec SSW-102-01-G-S,
J1 = Molex Connector Corp. 10-89-7102
U2, U3, U4, P5 Cypress microcontroller, EEPROM, and LDO. U2 = Microchip Technology Inc. MICRO24LC64,
U3 = Analog Devices, Inc., ADP3334ACPZ,
U4 = Cypress Semiconductor
CY7C68013A-56LTXC,
P5 = mini USB connector
C41, C42, C43, C44, C46, C53, C55 3.3 V supply decoupling. Several capacitors are
used for decoupling the 3.3 V supply.
C41, C42, C43, C44, C46, C53, C55 = 0.1 μF
(0402)
C45, C47, C48, C49, C50, C52, C56,
C57, C58, R19, R60, R61, R62, R64,
R65, R69, R70, CR1, CR2
USB microcontroller section components C47, C52 = 1 μF (0402),
C48, C56 = 10 pF (0402),
C45, C49, C57, C58 = 0.1 μF (0402),
C50 = 1000 pF (0402),
R19, R60, R61 = 2 kΩ (0402),
R62, R64 = 100 kΩ (0402),
R65 = 2 kΩ (0402),
R69 = 78.7 kΩ (0402),
R70 = 140 kΩ (0402),
CR1 = ROHM Semiconductor SML-21OMTT86,
CR2 = ROHM Semiconductor SML-21OMTT86
Y1, C51, C54 Crystal oscillator (24 MHz) and components. Y1 = NDK NX3225SA-24MHz,
C51, C54 = 22 pF (0402)
ADRF6806 Data Sheet
Rev. B | Page 30 of 36
ADRF6806 SOFTWARE
The ADRF6806 evaluation board can be controlled from PCs
using a USB adapter board, which is also available from Analog
Devices, Inc.. The USB adapter evaluation documentation and
ordering information can be found on the EVAL-ADF4XXXZ-USB
product page. The basic user interfaces are shown in Figure 48 and
Figure 49.
The software allows the user to configure the ADRF6806 for
various modes of operation. The internal synthesizer is controlled
by clicking on any of the numeric values listed in RF Section.
Attempting to program Ref Input Frequency, PFD Frequency,
VCO Frequency (2×LO), LO Frequency, or other values in RF
Section launches the Synth Form window shown in Figure 49.
Using Synth Form, the user can specify values for Local Oscillator
Frequency (MHz) and External Reference Frequency (MHz).
The user can also enable the LO output buffer and divider options
from this menu. After setting the desired values, it is important
to click Upload all registers for the new setting to take effect.
09993-148
Figure 48. Evaluation Board Software Main Window
Data Sheet ADRF6806
Rev. B | Page 31 of 36
09993-149
Figure 49. Evaluation Board Software Synth Form Window
ADRF6806 Data Sheet
Rev. B | Page 32 of 36
CHARACTERIZATION SETUPS
Figure 50 to Figure 52 show the general characterization bench
setups used extensively for the ADRF6806. The setup shown in
Figure 50 was used to do the bulk of the testing. An automated
Agilent VEE program was used to control the equipment over the
IEEE bus. This setup was used to measure gain, input P1dB, output
P1dB, input IP2, input IP3, IQ gain mismatch, IQ quadrature
accuracy, and supply current. The evaluation board was used to
perform the characterization with a Mini-Circuits TCM9-1+ balun
on each of the I and Q outputs. When using the TCM9-1+ balun
below 5 MHz (the specified 1 dB low frequency corner of the
balun), distortion performance degrades; however, this is not
the ADRF6806 degrading, merely the low frequency corner of
the balun introducing distortion effects. Through this balun, the
9-to-1 impedance transformation effectively presented a 450 Ω
differential load at each of the I and Q channels. The use of the
broadband Mini-Circuits ADTL2-18+ balun on the input provided
a differential balanced RF input. The losses of both the input and
output baluns were de-embedded from all measurements.
To do phase noise and reference spur measurements, the setup
shown in Figure 52 was used. Phase noise was measured at the
baseband output (I or Q) at a baseband carrier frequency of
50 MHz. The baseband carrier of 50 MHz was chosen to allow
phase noise measurements to be taken at frequencies of up to
20 MHz offset from the carrier. The noise figure was measured
using the setup shown in Figure 51 at a baseband frequency
of 10 MHz.
Data Sheet ADRF6806
Rev. B | Page 33 of 36
R&S SMT03 SIGNAL GENERATOR
R&S SMT03 SIGNAL GENERATOR
AGILENT E3631A
POWER SUPPLY
MINI CIRCUITS
ZHL-42W AMPLIFIER
(SUPPLIED WITH +15VDC
FOR OPERATION)
AGILENT 11636A
POWER DIVIDER
(USED AS COMBINER)
REF
RF2
RF1
RF SWITCH MATRIX
ADRF6806
EVALUATION BOARD
RF
6dB 3dB
3dB
3dB
3dB
3dB
6dB
I CH
AGILENT 34980A
MULTIFUNCTION
SWITCH
(WITH 34950 AND 2×
34921 MODULES)
10-PIN
CONNECTION
(+5V VPOS1,
+3.3V VPOS2,
DC MEASURE)
9-PIN D-SUB CONNECTION
(VCO AND PLL PROGRAMMING)
RF
IE
IEEE
IEEE
AGILENT DMM
(FOR I 3.3V VP2 MEAS.)
R&S SMA100
SIGNAL GENERATOR
AGILENT MXA
SPECTRUM ANALYZER
HP 8508A
VECTOR
VOLTMETER
Q CH
AGILENT DMM
(FOR I-5V VP1 MEAS.)
REF
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
CH A
CH B
6dB
09335-048
IEEE
Figure 50. General Characterization Setup
ADRF6806 Data Sheet
Rev. B | Page 34 of 36
AGILENT E3631A
POWER SUPPLY
REF
RF SWITCH MATRIX
ADRF6806
EVALUATION BOARD
RF
6dB 3dB 6dB
I CH
10-PIN
CONNECTION
(+5V VPOS1,
+3.3V VPOS2,
DC MEASURE)
9-PIN D-SUB CONNECTION
(VCO AND PLL PROGRAMMING)
IE
IEEE
AGILENT DMM
(FOR I 3.3V VP2 MEAS.)
Q CH
AGILENT DMM
(FOR I-5V VP1 MEAS.)
REF
EIEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
6dB
RF1
AGILENT N8974A
NOISE FIGURE ANALYZER
AGILENT 346B
NOISESOURCE
AGILENT 8665B
LOW NOISE SYN
SIGNAL GENERATOR
10MHz
LOW-PASS FILTER
RF
3dB
09335-049
IEEE
AGILENT 34980A
MULTIFUNCTION
SWITCH
(WITH 34950 AND 2×
34921 MODULES)
Figure 51. Noise Figure Characterization Setup
Data Sheet ADRF6806
Rev. B | Page 35 of 36
AGILENT E3631A
POWER SUPPLY
REF
RF SWITCH MATRIX
ADRF6806
EVALUATION BOARD
RF
6dB 3dB 6dB
I CH
10-PIN
CONNECTION
(+5V VPOS1,
+3.3V VPOS2,
DC MEASURE)
9-PIN D-SUB CONNECTION
(VCO AND PLL PROGRAMMING)
IE
IEEE
AGILENT DMM
(FOR I 3.3V VP2 MEAS.)
Q CH
AGILENT DMM
(FOR I-5V VP1 MEAS.)
REF
EIEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
6dB
RF1
RF
3dB
AGILENT MXA
SPECTRUM ANALYZER
AGILENT E5052 SIGNAL SOURCE
ANALYZER
R&S SMA100
SIGNAL GENERATOR
R&S SMA100
SIGNAL GENERATOR
100MHz
LOW-PASS FILTER
09335-050
IEEE
AGILENT 34980A
MULTIFUNCTION
SWITCH
(WITH 34950 AND 2×
34921 MODULES)
Figure 52. Phase Noise Characterization Setup
ADRF6806 Data Sheet
Rev. B | Page 36 of 36
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
122107-A
1
40
10
11
29
28
20
19
4.45
4.30 SQ
4.15
TOP
VIEW
6.00
BSC SQ
5.75
BSC SQ
COPLANARITY
0.08
4.50
REF
0.50
0.40
0.30
0.50
BSC
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
0.25 MIN
EXPOSED
PAD
(BOT TOM VIEW)
PIN 1
INDICATOR
0.30
0.23
0.18
0.20 REF
12° MAX 0.80 MAX
0.65 TYP
1.00
0.85
0.80 0.05 MAX
0.02 NOM
S
EATING
PLANE
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 53. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
Ordering
Quantity
ADRF6806ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-4 750
ADRF6806-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09335-0-3/12(B)
