PRELIMINARY
16K/32K/64K x16/18
Synchronous Dual Port Static RAM
CY7C09269/79/89
CY7C09369/79/89
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 23, 1998
0
25/0251
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 6 Flow-Through/Pipelined devices
—16K x 16/18 organization (CY7C09269/369)
—32K x 16/18 organization (CY7C09279/379)
—64K x 16/18 organization (CY7C09289/389)
• 3 Modes
—Flow-Through
—Pipelined
—Burst
• Pipelined output mode on both ports allows fast
100-MH z c ycle time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5/7.5/9/12 ns (max.)
• Low operating po w er
—Active= 195 mA (typical)
—Standby= 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
—Short en cycle times
—Minimize bus noise
—Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automati c power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to
IDT709269, IDT70927, and IDT709279
Notes:
1. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
2. I/O0–I/O7 for x16 devices. I/O0–I/O8 for x18 devices.
3. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices.
Logic Block Diagram
R/WL
1
0
0/1
CE0L
CE1L
LBL
OEL
UBL
1b
0/1 0b 1a 0a
ba
FT/PipeL
I/O8/9L–I/O15/17L
I/O0L–I/O7/8L
I/O
Control
Counter/
Address
Register
Decode
A0L–A13/14/15L
CLKL
ADSL
CNTENL
CNTRSTL
True Dual-Ported
RAM Array
R/WR
1
0
0/1
CE0R
CE1R
LBR
OER
UBR
1b0/1
0b1a0a ba FT/PipeR
I/O
Control
Counter/
Address
Register
Decode
14/15/16
8/9
8/9 I/O8/9R–I/O15/17R
I/O0R–I/O7/8R
A0R–A13/14/15R
CLKR
ADSR
CNTENR
CNTRSTR
14/15/16
8/9
8/9
[1]
[2]
[1]
[2]
[3] [3]
For the most recent infor mation, visit the Cypress web site at www.cypress.com
CY7C09269/79/89
CY7C09369/79/89
2
PRELIMINARY
Functional Description
The CY7C09269/79/89 and CY7C09369/79/89 are high
speed synchronous CMOS 16K, 32K, and 64K x 16/18 du-
al-port static RAMs. Two ports are provided, permitting inde-
pendent, simultaneous access for reads and writes to any lo-
cation in memory.[4] Registers on control, address, and data
lines allo w for minimal s et-u p and hold ti me s . In p ipe li ned out-
put mode, data is registered for decreased cycle time. Clock
to data v alid tCD2 = 6.5 n s (pip elined ). Flo w-t hrough mode can
also be used to bypass the pipelined output register to elimi-
nate access l atency. In flow-th rough m ode data will be avail-
able tCD1 = 15 ns after the address is clocked into the device.
Pipelined output or flow-through mode is selected via the
FT/PIPE pin.
Each p ort contains a bu rst c ounter on t he input addre ss re gis-
ter. The internal write pulse width is independent of the
LOW-to-HIGH transition of the clock signal. The internal write
pulse is self-timed to allow the shortest possible cycl e times.
A HIGH on CE0 or LOW on CE1 f or one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion . The us e of mu ltiple Chip E nables al lows easi er ba nking
of multiple chips for depth expansion configurations. In the
pipelin ed mode, one cycle is requi red wi th CE0 L OW and CE 1
HIGH to reactivate the outputs.
Counter enab le inputs are pro vided to stall the oper ation of the
address input and utilize the internal address generated b y the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s address strobe
(ADS). When the port’s count enable (CNTEN) is asserted, the
address counter will increment on each LOW-to-HIGH transi-
tion of that port’s clock signal. This will read/write one word
from/into each successive address location until CNTEN is
deasserted. The counter can address the entire memory array
and will loop back to the start. Counter reset (CNTRST) is used
to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Pin Configurations
Notes:
4. When writing simultaneously to the same location, the final value cannot
be guaranteed.
5. This pin is NC for CY7C09269.
6. This pin is NC for CY7C09269 and CY7C09279.
7. F or CY7C09269 and CY7C09279, pin #18 connected to VCC is equivalent
to an IDT x16 pipelined device; connecting pin #18 and #58 to GND is
equivalent to an IDT x16 flow-through device.
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A9R
A10R
A11R
A12R
A13R
A14R
UBR
NC
LBR
CE1R
CNTRSTR
OER
FT/PIPER
NC
A15R
GND
R/WR
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
CE0R
58
57
56
55
54
53
52
51
A9L
A10L
A11L
A12L
A13L
A14L
UBL
NC
LBL
CE1L
CNTRSTL
OEL
FT/PIPEL
NC
A15L
VCC
R/WL
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
CE0L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8L
A7L
A6L
A5L
A4L
A3L
CLKL
A1L
CNTENL
GND
ADSR
A0R
A1R
A0L
A2L
CLKR
CNTENR
A2R
A3R
A4R
A5R
A6R
A7R
A8R
ADSL
34 35 36 424139 403837 43 44 45 5048 494746
NC
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/01R
I/O4R
I/O2R
GND
I/O0L
I/O2L
I/O3L
I/O3R
I/O5R
I/O1L
GND
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
I/O0R
3332313029282726
100-Pin TQFP (Top View)
[Note 5]
[Note 6]
[Note 5]
[Note 6]
[Note 7] [Note 7]
CY7C09279 (32K x 16)
CY7C09269 (16K x 16)
CY7C09289 (64K x 16)
CY7C09269/79/89
CY7C09369/79/89
3
PRELIMINARY
Pin Configurations (continued)
Notes:
8. This pin is NC for CY7C09369.
9. This pin is NC for CY7C09369 and CY7C09379.
Selection Guide
CY7C09269/79/89
CY7C09369/79/89
-6
CY7C09269/79/89
CY7C09369/79/89
-7
CY7C09269/79/89
CY7C09369/79/89
-9
CY7C09269/79/89
CY7C09369/79/89
-12
fMAX2 (MHz) (Pipelined) 100 83 67 50
Max Access Time (ns) (Clock to Data,
Pipelined) 6.5 7.5 9 12
Typical Operating Current ICC (mA) 250 235 215 195
Typical Standby Current for ISB1 (mA)
(Both ports TTL Level) 45 40 35 30
Typical Standby Current for ISB3 (mA)
(Both ports CMOS level) 0.05 0.05 0.05 0.05
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
A8R
A9R
A10R
A11R
A12R
A13R
CE0R
A15R
UBR
CNTRSTR
R/WR
FT/PIPER
I/O17R
LBR
A14R
GND
OER
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
CE1R
58
57
56
55
54
53
52
51
A9L
A10L
A11L
A12L
A13L
A14L
CE1L
LBL
CE0L
R/WL
OEL
I/O17L
I/O16L
UBL
A15L
VCC
FT/PIPEL
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O11L
I/O10L
CNTRSTL
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
A8L
A7L
A6L
A5L
A4L
A3L
CLKL
A1L
CNTENL
GND
GND
CNTENR
A0R
A0L
A2L
ADSR
CLKR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
ADSL
34 35 36 424139 403837 43 44 45 5048 494746
I/10R
I/O9R
I/O8R
I/O7R
VCC
I/O6R
I/01R
I/O4R
I/O2R
GND
I/O0L
I/O2L
I/O3L
I/O3R
I/O5R
I/O1L
GND
I/O4L
I/O5L
I/O6L
I/O7L
VCC
I/O8L
I/O9L
I/O0R
3332313029282726
100-Pin TQFP (Top View)
[Note 8]
[Note 9]
[Note 8]
[Note 9]
CY7C09379 (32K x 18)
CY7C09369 (16K x 18)
CY7C09389 (64K x 18)
CY7C09269/79/89
CY7C09369/79/89
4
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature................................. –65°C to +150°C
Ambient Temperature with Power Applied..–55°C to +125°C
Supply Voltage to Ground Potential...............–0.3V to +7.0V
DC Voltage Applied to
Outputs in High Z State .................................–0.5V to +7.0V
DC Input Voltage............................................–0.5V to +7.0V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage ...........................................>1100V
Latch-Up Current.....................................................>200 mA
Pin Definitions
Left Port Right Port Description
A0L–A15L A0R–A15R Address Inputs (A0–A14 for 32K, A0–A13 for 16 K devices).
ADSLADSRAddress Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied a ddress. Asserting this s ignal LO W also loads the
burst counter with the address present on the address pins.
CE0L,CE1L CE0R,CE1R Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted
to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKLCLKRClock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENLCNTENRCounter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTLCNTRSTRCounter Res et Inpu t. Asse rting this sign al LO W resets the b urs t add ress cou nter of its re spec-
tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O17L I/O0R–I/O17R Data Bus Input/Output (I/O0–I/O15 for x16 devices).
LBLLBRLower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lowe r by te. (I/O0–I/O8 f or x 18, I/O0–I/O7 f or x16) of the memory arra y. F or read op erat ions bot h
the LB an d OE sig nals must be as serted to drive out put data on the lowe r byte of the data pin s.
UBLUBRUpper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L).
OELOEROutput Enab le Input. This signal must be asserted LO W to enab le the I/O data pins during read
operations.
R/WLR/WRRead/Write Ena ble Input. This si gnal is as serted LOW to write to the dual port memory arr ay.
For read operations, asser t this pin HIGH.
FT/PIPELFT/PIPERFlow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
GND Ground Input.
NC No Connect.
VCC Power Input.
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Shaded ar ea contains advance informati on.
CY7C09269/79/89
CY7C09369/79/89
5
PRELIMINARY
Shaded area contains advance information.
Note:
10. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
Electrical Characteristi cs Over the Operating Range
Symbol Parameter
CY7C09269/79/89
CY7C09369/79/89
Units
-6 -7 -9 -12
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
VOH Output HIGH Voltage (VCC=Min,
IOH=–4.0 mA) 2.4 2.4 2.4 2.4 V
VOL Out put LOW Voltage (VCC=Min ,
IOH= +4.0 mA) 0.40.40.40.4V
VIH Input HIGH Voltage 2.2 2.2 2.2 2.2 V
VIL Input LOW Voltage 0.8 0.8 0.8 0.8 V
IOZ Output Lea kage Current –10 1 0 –10 1 0 -10 10 –10 10 µA
ICC Operating Current
(VCC=Max, IOUT=0 mA)
Outputs Disabled
Com’l. 250 450 235 420 215 360 195 300 mA
Indust. 260 445 245 410 225 375 mA
ISB1 Standby Current (Both
P orts TTL Lev el)[10] CEL
& CER ≥ VIH, f=fMAX
Com’l. 45 115 40 105 35 95 30 85 mA
Indust. 55 120 50 110 45 100 mA
ISB2 Standby Current (One
P ort TTL Le ve l)[10] CEL |
CER ≥ VIH, f=fMAX
Com’l. 175 235 160 220 145 205 125 190 mA
Indust. 175 235 160 220 140 205 mA
ISB3 Standby Current (Both
Ports CMOS Level)[10]
CEL & CER ≥ VCC – 0.2V ,
f=0
Com’l. 0.05 0.25 0.05 0.25 0.05 0.25 0.05 0.25 mA
Indust. 0.05 0.25 0.05 0.25 0.05 0.25 mA
ISB4 Standby Current (One
Port CMOS Level)[10]
CEL | CER ≥ VIH, f=fMAX
Com’l. 160 200 145 185 130 170 110 150 mA
Indust. 160 200 145 185 125 165 mA
Capacitance
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 10 pF
COUT Output Capacitance 10 pF
AC Test Loads
3.0V
GND 90% 90%
10%
3ns 3ns
10%
ALLINPUTPULSES
(a) Normal Load (Load 1)
R1 = 893Ω
5V
OUTPUT
R2 = 347Ω
C= 30pF
VTH =1.4V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay(Load 2)
R1 = 893Ω
R2 = 347Ω
5V
OUTPUT
C= 5pF
RTH = 250Ω
≤≤
(Used f or tCKLZ, tOLZ, & tOHZ
including scope and jig)
CY7C09269/79/89
CY7C09369/79/89
6
PRELIMINARY
Notes:
11. Test conditions used are Load 2.
12. This parameter is guaranteed by design, but it is not production tested.
Switching Characteristics Over the Operating Range
Symbol Parameter
CY7C09269/79/89
CY7C09369/79/89
Units
-6 -7 -9 -12
MinMaxMinMaxMinMaxMinMax
fMAX1 fMax Flow-Through 53454033MHz
fMAX2 fMax Pipelined 100 83 67 50 MHz
tCYC1 Clock Cycle Time - Flow-Through 19 22 25 30 ns
tCYC2 Clock Cycle Time - Pipelined 10 12 15 20 ns
tCH1 Clock HIGH Time - Flow-Through 6.5 7.5 12 12 ns
tCL1 Clock LOW Time - Flow-Through 6.5 7.5 12 12 ns
tCH2 Clock HIGH Time - Pipelined 4568ns
tCL2 Clock LOW Time - Pipelined 4568ns
tRClock Rise Time 3333ns
tFClock Fall Time 3333ns
tSA Address Set-Up Time 3.5 4 4 4 ns
tHA Address Hold Time 0011ns
tSC Chip Enable Set-Up Time 3.5 4 4 4 ns
tHC Chip Enable Hold Time 0011ns
tSW R/W Set-Up Time 3.5 4 4 4 ns
tHW R/W Hold Time 0011ns
tSD Input Data Set-Up Time 3.5 4 4 4 ns
tHD Input Data Hold Time 0011ns
tSAD ADS Set-Up Time 3.5 4 4 4 ns
tHAD ADS Hold Time 0011ns
tSCN CNTEN Set-Up Time 3.5 4 4 4 ns
tHCN CNTEN Hold Time 0011ns
tSRST CNTRST Set-Up Time 3.5 4 4 4 ns
tHRST CNTRST Hold Time 0011ns
tOE Output Enable to Data Valid 8 9 10 12 ns
tOLZ[11,12] OE to Low Z 2222ns
tOZ[11,12] OE to High Z 17171717ns
tCD1 Clock to Data Valid - Flow-Thro ugh 15 18 20 25 ns
tCD2 Clock to Data Valid - Pipelined 6.5 7.5 9 12 ns
tDC Data Output Hold After Clock HIGH2222ns
tCKHZ[11,12] Clock HIGH to Output High Z 29292929ns
tCKLZ[11,12] Clock HIGH to Output Low Z 2222ns
Port to Port Delays
tCWDD Write P ort Clock HIGH to Read Data Delay 30 35 40 40 ns
tCCS Clock to Clock Set-Up Time 9 10 15 15 ns
CY7C09269/79/89
CY7C09369/79/89
7
PRELIMINARY
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = VIL)[13,14,15,16]
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[13,14,15,16]
Notes:
13. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
14. ADS = VIL, CNTEN and CNTRST = VIH.
15. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the ne xt rising edge of the clock.
16. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only .
tCH1 tCL1
tCYC1
tSC tHC
tDC
tOHZ
tOE
tSC tHC
tSW tHW
tSA tHA
tCD1 tCKHZ
tDC
tOLZ
tCKLZ
AnAn+1 An+2 An+3
QnQn+1 Qn+2
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
tCH2 tCL2
tCYC2
tSC tHC
tSW tHW
tSA tHA
AnAn+1
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
An+2 An+3
tSC tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
QnQn+1 Qn+2
1 Latency
CY7C09269/79/89
CY7C09369/79/89
8
PRELIMINARY
Bank Select Pipelined Read[17,18]
Left Port Write to Flow-Through Right Port Read[19,20,21,22]
Notes:
17. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; each Bank consists of one Cypress dual-port device from this datasheet.
ADDRESS(B1) = ADDRESS(B2).
18. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
19. The same waveforms apply for a right port write to flow-through left port read.
20. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
21. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
22. It tCCS ≤ maximum specified, then data from right port READ is not v alid until the maximum specified f or tCWDD. If tCCS>maximum specified, then data is not valid
until tCCS + tCD1. tCWDD does not apply in this case.
Switching Waveforms (continued)
D3
D1
D0
D2
A0A1A2A3A4A5
D4
A0A1A2A3A4A5
tSA tHA
tSC tHC
tSA tHA
tSC tHC
tSC tHC
tSC tHC tCKHZ
tDC
tDC
tCD2
tCKLZ
tCD2 tCD2 tCKHZ
tCKLZ
tCD2 tCKHZ
tCKLZ
tCD2
tCH2 tCL2
tCYC2
CLKL
ADDRESS(B1)
CE0(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE0(B2)
tSA tHA
tSW tHW
tSD tHD
MATCH
VALID
tCCS
tSW tHW
tDC
tCWDD
tCD1
MATCH
tSA tHA
MATCH
NO
MATCH
NO
VALID VALID
tDC
tCD1
CLKL
R/WL
ADDRESSL
DATAINL
ADDRESSR
DATAOUTR
CLKR
R/WR
CY7C09269/79/89
CY7C09369/79/89
9
PRELIMINARY
Pipelined Read-to-Write-to-Read (OE = VIL)[16,23,24,25]
Pipelined Read-to-Write-to-Read (OE Controlled)[16,23,24,25]
Notes:
23. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
24. CE0 and A DS = VIL; CE1, CNTEN, and CNTRST = VIH.
25. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Switching Waveforms (continued)
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
tHW
tSW
tCD2 tCKHZ
tSD tHD
tCKLZ tCD2
NO OPERATIO N WRITEREAD READ
CLK
CE0
CE1
R/W
ADDRESS
DATAIN
DATAOUT
AnAn+1 An+2 An+2
Dn+2
An+3 An+4
QnQn+3
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
AnAn+1 An+2 An+3 An+4 An+5
tHW
tSW
tSD tHD
Dn+2
tCD2
tOHZ
READ READWRITE
Dn+3 tCKLZ tCD2
QnQn+4
CLK
CE0
CE1
R/W
ADDRESS
DATAIN
DATAOUT
OE
CY7C09269/79/89
CY7C09369/79/89
10
PRELIMINARY
Flow-Through Read-to-Write-to-Read (OE = VIL)[14,16,23,24]
Flow-Through Read-to-Write-to-Read (OE Cont rolled )[14,16,23,24]
Switching Waveforms (continued)
tCH1 tCL1
tCYC1
tSC tHC
tSW tHW
tSA tHA
tSW tHW
tSD tHD
AnAn+1 An+2 An+2 An+3 An+4
Dn+2
QnQn+1 Qn+3
tCD1 tCD1
tDC tCKHZ
tCD1 tCD1
tCKLZ tDC
READ NO
OPERATION WRITE READ
CLK
CE0
CE1
ADDRESS
R/W
DATAIN
DATAOUT
Qn
tCH1 tCL1
tCYC1
tSC tHC
tSW tHW
tSA tHA
tCD1 tDC
tOHZ
READ
AnAn+1 An+2 An+3 An+4 An+5
Dn+2 Dn+3
tSW tHW
tSD tHD
tCD1 tCD1
tCKLZ tDC
Qn+4
tOE
WRITE READ
CLK
CE0
CE1
ADDRESS
R/W
DATAIN
DATAOUT
OE
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PRELIMINARY
Pipelined Read with Address Counter Advance[26]
Flow-Through Read with Address Counter Adva nce[26]
Note:
26. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH.
Switching Waveforms (continued)
COUNTER HOLD
READ WITH COUNTER
tSA tHA
tSAD tHAD
tSCN tHCN
tCH2 tCL2
tCYC2
tSAD tHAD
tSCN tHCN
Qx-1 QxQnQn+1 Qn+2 Qn+3
tDC
tCD2
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
CLK
ADDRESS
ADS
DATAOUT
CNTEN
An
tCH1 tCL1
tCYC1
tSA tHA
tSAD tHAD
tSCN tHCN
QxQnQn+1 Qn+2 Qn+3
An
tSAD tHAD
tSCN tHCN
tDC
tCD1
COUNTER HOLD
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
CLK
ADDRESS
ADS
DATAOUT
CNTEN
CY7C09269/79/89
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12
PRELIMINARY
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[27,28]
Notes:
27. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
28. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
AnAn+1 An+2 An+3 An+4
Dn+1 Dn+1 Dn+2 Dn+3 Dn+4
An
Dn
tSAD tHAD
tSCN tHCN
tSD tHD
WRITE EX T ERNA L WRITE WITH COUNTER
ADDRESS WRITE WITH
COUNTER WRITE COUNTER
HOLD
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
tSA tHA
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PRELIMINARY
Counter Reset (Pipelined Outputs)[16,28,29,30]
Notes:
29. CE0, UB, and LB = VIL; CE1 = VIH.
30. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
CNTRST
R/W
DATAOUT Q0Q1Qn
D0
AX01A
nAn+1
tSAD tHAD
tSCN tHCN
tSRST tHRST
tSD tHD
tSW tHW
AnAn+1
tSA tHA
COUNTER
RESET WRITE
ADDRESS 0 READ
ADDRESS 0 READ
ADDRES S 1 READ
ADDRESS n
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PRELIMINARY
Notes:
31. “X” = Don’t Care, “H” = VIH, “L” = VIL.
32. ADS, CNTEN, CNTRST = Don’t Care.
33. OE is an asynchronous input signal.
34. When C E changes state in the pipelined mode, deselection and read happen in the following clock cycle.
35. CE0 and OE = VIL; CE1 and R/W = VIH.
36. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
37. Counter operation is independent of CE0 and CE1.
Read/Write and Enable Ope rat ion[31,32,33]
Inputs Outputs
OE CLK CE0CE1R/W I/O0–I/O17 Operation
X H X X High-Z Deselected[34]
X X L X High-Z Deselected[34]
X L H L DIN Write
L L H H DOUT Read[34]
H X L H X High-Z Outputs Disabled
Address Counter Control Operation[31,35,36,37]
Address Previous
Address CLK ADS CNTEN CNTRST I/O Mode Operation
X X X X L Dout(0) Reset Counter Reset to Address 0
AnX L X H Dout(n) Load Address Load into Counter
X AnH H H Dout(n) Hold External Address Blocked—Counter
Disabled
X AnH L H Dout(n+1) Increment Counter Enabled—Internal Address
Generation
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PRELIMINARY
Ordering Information
16K x16 Synchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
6.5 CY7C09269-6AC A100 100-Pin T hin Quad Flat Pack Commercial
7.5 CY7C09269-7AC A100 100-Pin T hin Quad Flat Pack Commercial
CY7C09269-7AI A100 100-Pin T hin Quad Flat Pack Industrial
9CY7C09269-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09269-9AI A100 100-Pin T hin Quad Flat Pack Industrial
12 CY7C09269-12AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09269-12AI A100 100-Pin T hin Quad Flat Pack Industrial
Shaded area contains advance information.
32K x16 Synchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
6.5 CY7C09279-6AC A100 100-Pin T hin Quad Flat Pack Commercial
7.5 CY7C09279-7AC A100 100-Pin T hin Quad Flat Pack Commercial
CY7C09279-7AI A100 100-Pin T hin Quad Flat Pack Industrial
9CY7C09279-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09279-9AI A100 100-Pin T hin Quad Flat Pack Industrial
12 CY7C09279-12AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09279-12AI A100 100-Pin T hin Quad Flat Pack Industrial
Shaded area contains advance information.
64K x16 Synchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
6.5 CY7C09289-6AC A100 100-Pin T hin Quad Flat Pack Commercial
7.5 CY7C09289-7AC A100 100-Pin T hin Quad Flat Pack Commercial
CY7C09289-7AI A100 100-Pin T hin Quad Flat Pack Industrial
9CY7C09289-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09289-9AI A100 100-Pin T hin Quad Flat Pack Industrial
12 CY7C09289-12AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09289-12AI A100 100-Pin T hin Quad Flat Pack Industrial
Shaded area contains advance information.
CY7C09269/79/89
CY7C09369/79/89
16
PRELIMINARY
Ordering Information (continued)
Document #: 38–00664–D
16K x18 Synchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
6.5 CY7C09369-6AC A100 100-Pin T hin Quad Flat Pack Commercial
7.5 CY7C09369-7AC A100 100-Pin T hin Quad Flat Pack Commercial
CY7C09369-7AI A100 100-Pin T hin Quad Flat Pack Industrial
9CY7C09369-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09369-9AI A100 100-Pin T hin Quad Flat Pack Industrial
12 CY7C09369-12AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09369-12AI A100 100-Pin T hin Quad Flat Pack Industrial
Shaded area contains advancd information.
32K x18 Synchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
6.5 CY7C09379-6AC A100 100-Pin T hin Quad Flat Pack Commercial
7.5 CY7C09379-7AC A100 100-Pin T hin Quad Flat Pack Commercial
CY7C09379-7AI A100 100-Pin T hin Quad Flat Pack Industrial
9CY7C09379-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09379-9AI A100 100-Pin T hin Quad Flat Pack Industrial
12 CY7C09379-12AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09379-12AI A100 100-Pin T hin Quad Flat Pack Industrial
Shaded area contains advance information.
64K x18 Synchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
6.5 CY7C09389-6AC A100 100-Pin T hin Quad Flat Pack Commercial
7.5 CY7C09389-7AC A100 100-Pin T hin Quad Flat Pack Commercial
CY7C09389-7AI A100 100-Pin T hin Quad Flat Pack Industrial
9CY7C09389-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09389-9AI A100 100-Pin T hin Quad Flat Pack Industrial
12 CY7C09389-12AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09389-12AI A100 100-Pin T hin Quad Flat Pack Industrial
Shaded area contains advance information.
CY7C09269/79/89
CY7C09369/79/89
PRELIMINARY
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other than cir cuitry embodied in a Cy press Semiconductor product. Nor d oes it con vey or imply any license under patent or other rights. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
P ac kage Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-A
