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Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FAN53555 5 A, 2.4 MHz, Digitally Programmable TinyBuck(R) Regulator Features Description The FAN53555 is a step-down switching voltage regulator that delivers a digitally programmable output from an input voltage supply of 2.5 V to 5.5 V. The output voltage is 2 programmed through an I C interface capable of operating up to 3.4 MHz. Fixed-Frequency Operation: 2.4 MHz Best-in-Class Load Transient Continuous Output Current Capability: 5 A Pulse Current Capability: 6.5 A (05 Option) 2.5 V to 5.5 V Input Voltage Range Digitally Programmable Output Voltage: - 00/01/03/05/08/18 Options: 0.6-1.23 V in 10 mV Steps - 04/042/09/ Options: 0.603-1.411 V in 12.826 mV Steps - 23 Option: 0.60-1.3875 V in 12.5 mV Steps - 24 Option: 0.603-1.420 V in 12.967 mV Steps - 13 Option: 0.8-1.43 V in 10 mV Steps Programmable Slew Rate for Voltage Transitions 2 I C-Compatible Interface Up to 3.4 Mbps PFM Mode for High Efficiency in Light Load Quiescent Current in PFM Mode: 60 A (Typical) Internal Soft-Start Input Under-Voltage Lockout (UVLO) Thermal Shutdown and Overload Protection 20-Bump Wafer-Level Chip Scale Package (WLCSP) Using a proprietary architecture with synchronous rectification, the FAN53555 is capable of delivering 5 A continuous at over 80% efficiency, while maintaining over 80% efficiency at load currents as low as 10 mA. Pulse currents as high as 6.5 A can be supported by the 05 option. The regulator operates at a nominal fixed frequency of 2.4 MHz, which reduces the value of the external components to 330 nH for the output induction and as low as 20 F for the output capacitor. Additional output capacitance can be added to improve regulation during load transients without affecting stability. Inductance up to 1.2 H may be used with additional output capacitance. At moderate and light loads, Pulse Frequency Modulation (PFM) is used to operate in Power-Save Mode with a typical quiescent current of 60 A. Even with such a low quiescent current, the part exhibits excellent transient response during large load swings. At higher loads, the system automatically switches to fixed-frequency control, operating at 2.4 MHz. In Shutdown Mode, the supply current drops below 1 A, reducing power consumption. PFM Mode can be disabled if constant frequency is desired. The FAN53555 is available in a 20-bump, 1.6 x 2 mm, WLCSP. Applications Application, Graphic, and DSP Processors - ARMTM, KraitTM, OMAPTM, NovaThorTM, ARMADATM PVIN Hard Disk Drives SDA Tablets, Netbooks, Ultra-Mobile PCs SCL Smart Phones Gaming Devices CIN1 EN VSEL CIN VOUT FAN53555 L1 SW VDD COUT Core Processor (System Load) GND AGND GND Figure 1. Typical Application All trademarks are the property of their respective owners. (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator August 2015 Power-Up Defaults Part Number VSEL0 VSEL1 2 I C Slave A1 PIN Address Function Max. Max. Pulse Temperature Packing RMS Package Current Range Method Current (50 ms) FAN53555UC00X 1.05 1.20 VSEL 5A N/A FAN53555UC01X 0.90 OFF VSEL 5A N/A FAN53555UC03X 0.90 N/A PGOOD 5A N/A FAN53555UC04X 1.10 1.20 VSEL 5A N/A FAN53555UC05X 0.90 OFF VSEL 5A 6.5 A FAN53555BUC05X 0.90 OFF VSEL 5A 6.5 A FAN53555UC08X (1) 1.02 1.15 VSEL 4A N/A (1) 1.02 1.15 VSEL 4A N/A (1) FAN53555BUC09X 1.10 1.10 VSEL 3A N/A FAN53555UC09X 1.10 1.10 VSEL 3A N/A FAN53555UC13X FAN53555BUC08X C0 1.15 1.15 VSEL 5A N/A FAN53555BUC13X 1.15 1.15 VSEL 5A N/A FAN53555UC18X (1) 1.02 1.15 VSEL 5A N/A (1) 1.02 1.15 VSEL 5A N/A FAN53555BUC23X (1) 1.15 1.15 VSEL 5A N/A FAN53555UC24X FAN53555BUC18X 1.225 1.212 VSEL 4A N/A (1) 1.225 1.212 VSEL 4A N/A (2) 1.10 1.20 VSEL 5A N/A FAN53555BUC24X FAN53555UC042X C4 -40 to 85C WLCSP20 Tape & Reel Notes: 1. The FAN53555BUC05X, FAN53555BUC08X, FAN53555BUC09X, FAN53555BUC13X, FAN53555BUC18X, FAN53555BUC23X, and FAN53555BUC24X, include backside lamination. 2 2. The 042 option is the same as the 04 option, except the I C slave addresses. Recommended External Components Table 1. Recommended External Components for 5 A Maximum Load Current Component Description Vendor L1 330 nH Nominal See Table 2 COUT 2 Pieces; 22 F, 6.3 V, X5R, 0805 CIN CIN1 Parameter Typ. Unit L 0.33 H DCR 13 m GRM21BR60J226M (Murata) C2012X5R0J226M (TDK) C 44 1 Piece; 10 F, 10 V, X5R, 0805 LMK212BJ106KG-T (Taiyo Yuden) C2012X5R1A106M (TDK) C 10 2 Pieces; 10 F, 6.3 V, X5R, 0805 GRM21BR60J106M (Murata) C2012X5R0J106M (TDK) C 20 10 nF, 25 V, X7R, 0402 GRM155R71E103K (Murata) C1005X7R1E103K (TDK) C 10 (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 F nF www.fairchildsemi.com 2 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Ordering Information Component Dimensions Manufacturer Part# L (nH) DCR (m) Vishay IHLP1616ABERR47M01 470 20.0 Mag. Layers (4) IMAXDC (3) L W H 5.0 4.5 4.1 1.2 MMD-04ABNR33M-M1-RU 330 12.5 7.5 4.5 4.1 1.2 Mag. Layers MMD-04ABNR47M-M1-RU 470 20.0 5.0 4.5 4.1 1.2 Inter-Technical SM1608-R33M 330 9.6 9.0 4.5 4.1 2.0 Bournes SRP4012-R33M 330 15.0 6.7 4.7 4.2 1.2 Bournes SRP4012-R47M 470 20.0 5.0 4.7 4.2 1.2 TDK VLC5020T-R47M 470 15.0 5.4 5.0 5.0 2.0 Notes: 3. IMAXDC is the lesser current to produce 40C temperature rise or 30% inductance roll-off. 4. Preferred inductor value is 330 nH and all dynamic characterization was performed with this coil. FAN53555-24, -08, and -09 Reduced Output Current (4 A Max. RMS. for 08, and 24, 3 A Max. RMS for 09) Smaller Footprint Application The FAN53555-24, -08, and -09 were developed to provide power for core processors with high-performance graphics acceleration in Li-Ion-powered handheld devices. These applications require a very compact solution. The smaller input and output capacitors in the table below assume that additional bypass capacitance exists across the battery in fairly close proximity to the regulator(s). The CIN capacitors specified below are the capacitors that are required in very close proximity to VIN and PGND (see layout recommendations in Figure 2 below). Table 3. Recommended External Components for Lower-Current Applications with FAN53555-08-09-24 Component Description L1 470 or 330 nH, 2016 case size COUT Vendor Parameter Typ. Unit See Table 4 -08, ,24 Option 2 Pieces 22 F, 6.3 V, X5R, 0603 44 C1608X5R0J226M (TDK) -09 Option 1 Piece 22 F, 6.3 V, X5R, 0603 C 22 CIN 1 Piece; 10 F, 10 V, X5R, 0402 GRM155R61A106M (Murata) C 10 CIN1 10 nF, 25 V, X5R, 0201 TMK063CG100DT-F (Taiyo Yuden) C 10 F nF Table 4. Recommended Inductors for Lower-Current Applications with FAN53555-08-09-24 Component Dimensions DCR (m Typ.) IMAXDC Manufacturer Part# L (nH) Toko DFE201612R-H-R33N 330 25 (5) L W H 3.2 2.0 1.6 1.2 Toko DFE201612C-R47N 470 40 3.2 2.0 1.6 1.2 Cyntek PIFE20161B-R47MS-39 470 30 3.1 2.0 1.6 1.2 SEMCO CIGT201610HMR47SCE 470 30 3.1 2.0 1.6 0.9 Note: 5. IMAXDC is the lesser current to produce 40C temperature rise or 30% inductance roll-off. (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 3 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Table 2. Recommended Inductors for High-Current Applications Figure 2. Reduced-Footprint Layout Pin Configuration VSEL* EN SCL VOUT A1 A2 A3 A4 B2 B3 SDA AGND B1 C2 C3 VIN A3 A2 A1 B4 B3 B2 B1 C4 C3 C2 C1 D4 D3 D2 D1 E4 E3 E2 E1 B4 GND C1 A4 C4 SW D1 D2 D3 D4 E1 E2 E3 E4 A1 = VSEL for 00, 01, 04, 05, 08, 09, 13, 18, 23, 24 A1 = PGOOD for 03 Figure 3. Top View Figure 4. Bottom View Pin Definitions Pin # A1 Name Description VSEL Voltage Select. When this pin is LOW, VOUT is set by the VSEL0 register. When this pin is HIGH, VOUT (Except is set by the VSEL1 register. 03 Option) PGOOD (03) Power Good. This open-drain pin pulls LOW if an overload condition occurs or soft-start is in progress. A2 EN Enable. The device is in Shutdown Mode when this pin is LOW. All register values are kept during shutdown. Options 00, 01, 03, 05, 08 09, 13, 18, and 23 do not reset register values when EN is raised. The 04, 24, and 042 options reset all registers to default values when EN pin is LOW. If pulled up to a low-impedance voltage source greater than 1.8 V, use at least 100 series resistor. A3 SCL I C Serial Clock A4 VOUT B1 SDA I C Serial Data B2, B3, C1 - C4 GND Ground. Low-side MOSFET is referenced to this pin. CIN and COUT should be returned with a minimal path to these pins. B4 AGND Analog Ground. All signals are referenced to this pin. Avoid routing high dV/dt AC currents through this pin. D1, D2, E1, E2 VIN Power Input Voltage. Connect to the input power source. Connect to CIN with minimal path. D3, D4, E3, E4 SW Switching Node. Connect to the inductor. 2 VOUT. Sense pin for VOUT. Connect to COUT. 2 (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 4 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Layout Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Voltage on SW, VIN Pins VIN VOUT Voltage on EN Pin Min. Max. IC Not Switching -0.3 7.0 IC Switching -0.3 6.5 -0.3 2.0 Tied without Series Resistance ) -0.3 (6) VIN Voltage on All Other Pins IC Not Switching -0.3 VIN Voltage on VOUT Pin -0.3 Tied through Series Resistance of at Least 100 (6) VINOV_SLEW Maximum Slew Rate of VIN > 6.5 V, PWM Switching Human Body Model per JESD22-A114 2000 Charged Device Model per JESD22-C101 1500 Unit V V V 3.0 V 100 V/ms ESD Electrostatic Discharge Protection Level TJ Junction Temperature -40 +150 C TSTG Storage Temperature -65 +150 C +260 C TL Lead Soldering Temperature, 10 Seconds V Note: 6. Lesser of 7 V or VIN+0.3 V. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VIN Supply Voltage Range IOUT Output Current L CIN COUT Min. Max. Unit 2.5 5.5 V 0 5 A Inductor Typ. 0.33 H Input Capacitor 10 F Output Capacitor 44 F TA Operating Ambient Temperature -40 +85 C TJ Operating Junction Temperature -40 +125 C Max. Unit Thermal Properties Symbol JA Parameter Junction-to-Ambient Thermal Resistance Min. (7) Typ. 38 C/W Note: 7. See Thermal Considerations in the Application Information section. (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 5 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Absolute Maximum Ratings Minimum and maximum values are at V IN=2.5 V to 5.5 V, TA=-40C to +85C, unless otherwise noted. Typical values are at TA=25C, VIN=5 V, and EN=HIGH. Symbol Parameter Condition Min. Typ. Max. Unit ILOAD=0 60 100 ILOAD=0, MODE Bit=1 (Forced PWM) 43 H/W Shutdown Supply Current EN=GND 0.1 5.0 A S/W Shutdown Supply Current EN= VIN, BUCK_ENx=0 41 75 A VUVLO Under-Voltage Lockout Threshold VIN Rising 2.35 2.45 VUVHYST Under-Voltage Lockout Hysteresis Power Supplies IQ I SD Quiescent Current A mA 350 V mV EN, VSEL, SDA, SCL VIH HIGH-Level Input Voltage VIL LOW-Level Input Voltage VLHYST IIN 1.1 0.4 Logic Input Hysteresis Voltage Input Bias Current V 160 Input Tied to GND or VIN 0.01 V mV 1.00 A 1 mA 1.00 A -1.5 1.5 % PGOOD (03 Option) IOUTL PGOOD Pull-Down Current IOUTH PGOOD HIGH Leakage Current 0.01 VOUT Regulation IOUT(DC)=0, Forced PWM, VOUT=VSEL0 Default Value VREG 08, 24 Options 2.5 V VIN 4.5 V, VOUT from Minimum to Maximum, IOUT(DC)=0 to 4 A, Auto PFM/PWM -2.0 4.0 % 09 Option 2.5 V VIN 4.5 V, VOUT from Minimum to Maximum, IOUT(DC)=0 to 3 A, Auto PFM/PWM -2.0 4.0 % 13, 18, 23 Options 2.5 V VIN 4.5 V, VOUT from Minimum to Maximum, IOUT(DC)=0 to 5 A, Auto PFM/PWM -2.0 4.0 % All Other Options 2.5 V VIN 5.5 V, VOUT from Minimum to Maximum, IOUT(DC)=0 to 5 A, Auto PFM/PWM -3.0 5.0 % VOUT DC Accuracy VOUT ILOAD Load Regulation IOUT(DC)=1 to 5 A -0.1 %/A VOUT VIN Line Regulation 2.5 V VIN 5.5 V, IOUT(DC)=1.5 A 0.01 %/V VTRSP Transient Response ILOAD Step 0.1 A to 1.5 A, tr=tf=100 ns, VOUT=1.2 V 40 mV Continued on the following page... (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 6 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Electrical Characteristics Minimum and maximum values are at V IN=2.5 V to 5.5 V, TA=-40C to +85C, unless otherwise noted. Typical values are at TA=25C, VIN=5 V, and EN=HIGH. Symbol Parameter Condition Min. Typ. Max. Unit Power Switch and Protection RDS(ON)P P-Channel MOSFET On Resistance VIN=5 V 28 m RDS(ON)N N-Channel MOSFET On Resistance VIN=5 V 17 m ILIMPK P-MOS Peak Current Limit 00, 01, 03, 04, 13, 18, 23, 042 Options 6.3 7.4 8.5 A 05 Option 8.5 10.0 11.5 A 08, 24 Options 5.0 5.9 6.8 A 09 Option 4.0 4.75 5.5 TLIMIT Thermal Shutdown 150 C THYST Thermal Shutdown Hysteresis 17 C VSDWN Input OVP Shutdown 6.15 V 5.50 5.85 V 2.05 2.40 Rising Threshold Falling Threshold Frequency Control fSW Oscillator Frequency 2.75 MHz DAC Resolution 6 Differential Nonlinearity Bits (8) 0.5 LSB Timing 2 I CEN 2 EN=HIGH to I C Start 100 s Soft-Start tSS ROFF Regulator Enable to Regulated VOUT VOUT Pull-Down Resistance, Disabled RLOAD > 5 ; to VOUT=1.2 V; 00, 01, 03, 04, 042, 05, 09, 13, and 23 Options 300 2.5 V VIN 4.5 V; RLOAD =2 ; to VOUT=1.127 V with 1.1 V Pre-Bias Voltage; 08 and 18 Options 135 EN=0 or VIN<VUVLO 160 s 175 s Note: 8. Monotonicity assured by design. (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 7 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Electrical Characteristics Guaranteed by design. Symbol Parameter Condition Min. Typ. Standard Mode fSCL tBUF SCL Clock Frequency Bus-Free Time between STOP and START Conditions tLOW START or REPEATED START Hold Time SCL LOW Period Fast Mode 400 Fast Mode Plus 1000 High-Speed Mode, CB 100 pF 3400 High-Speed Mode, CB 400 pF 1700 Standard Mode 4.7 Fast Mode 1.3 Fast Mode Plus 0.5 tSU;STA tSU;DAT SCL HIGH Period REPEATED START Setup Time Data Setup Time tRCL Data Hold Time SCL Rise Time s 4 s 600 ns Fast Mode Plus 260 ns High-Speed Mode 160 ns Standard Mode 4.7 s Fast Mode 1.3 s Fast Mode Plus 0.5 s High-Speed Mode, CB 100 pF 160.0 ns High-Speed Mode, CB 400 pF 320.0 ns 4 s Fast Mode 600 ns Fast Mode Plus 260 ns High-Speed Mode, CB 100 pF 60 ns High-Speed Mode, CB 400 pF 120 ns Standard Mode 4.7 s Fast Mode 600.0 ns Fast Mode Plus 260.0 ns High-Speed Mode 160.0 ns Standard Mode 250 Fast Mode 100 Fast Mode Plus 50 High-Speed Mode tHD;DAT kHz Fast Mode Standard Mode tHIGH Unit 100 Standard Mode tHD;STA Max. ns 10 Standard Mode 0 3.45 s Fast Mode 0 900.00 ns Fast Mode Plus 0 450.00 ns High-Speed Mode, CB 100 pF 0 70.00 ns High-Speed Mode, CB 400 pF 0 150.00 ns Standard Mode 20+0.1CB 1000 Fast Mode 20+0.1CB 300 Fast Mode Plus 20+0.1CB 120 High-Speed Mode, CB 100 pF 10 80 High-Speed Mode, CB 400 pF 20 160 ns Continued on the following page... (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 8 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator I2C Timing Specifications Guaranteed by design. Symbol tFCL tRCL1 tRDA tFDA Parameter SCL Fall Time Rise Time of SCL After a REPEATED START Condition and After ACK Bit SDA Rise Time SDA Fall Time Condition CB Stop Condition Setup Time Max. 20+0.1CB 300 Fast Mode 20+0.1CB 300 Fast Mode Plus 20+0.1CB 120 High-Speed Mode, CB 100 pF 10 40 High-Speed Mode, CB 400 pF 20 80 High-Speed Mode, CB 100 pF 10 80 High-Speed Mode, CB 400 pF 20 160 Standard Mode 20+0.1CB 1000 Fast Mode 20+0.1CB 300 Fast Mode Plus 20+0.1CB 120 High-Speed Mode, CB 100 pF 10 80 High-Speed Mode, CB 400 pF 20 160 Standard Mode 20+0.1CB 300 Fast Mode 20+0.1CB 300 Fast Mode Plus 20+0.1CB 120 High-Speed Mode, CB 100 pF 10 80 High-Speed Mode, CB 400 pF 20 160 Unit ns ns ns ns 4 s Fast Mode 600 ns Fast Mode Plus 120 ns High-Speed Mode 160 Capacitive Load for SDA and SCL (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 Typ. Standard Mode Standard Mode tSU;STO Min. ns 400 pF www.fairchildsemi.com 9 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator I2C Timing Specifications (Continued) tF tSU;STA tBUF SDA tR TSU;DAT tHD;STO tHIGH SCL tLOW tHD;STA tHD;DAT tHD;STA REPEATED START START STOP START 2 Figure 5. I C Interface Timing for Fast Plus, Fast, and Slow Modes tFDA tRDA REPEATED START tSU;DAT STOP SDAH tSU;STA tRCL1 tFCL tRCL tSU;STO tHIGH SCLH tLOW tHD;STA tHD;DAT REPEATED START note A = MCS Current Source Pull-up = RP Resistor Pull-up Note A: First rising edge of SCLH after Repeated Start and after each ACK bit. 2 Figure 6. I C Interface Timing for High-Speed Mode (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 10 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Timing Diagrams Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25C; circuit and components according to Figure 1 and Table 1. 92% 92% -40C 2.7 VIN 90% 90% 3.6 VIN +25C +85C 88% 88% 86% 86% Efficiency Efficiency 5.0 VIN 84% 84% 82% 82% 80% 80% 78% 78% 76% 76% 0 1000 2000 3000 4000 5000 0 1000 2000 Load Current (mA) 4000 5000 Load Current (mA) Figure 7. Efficiency vs. Load Current and Input Voltage Figure 8. Efficiency vs. Load Current and Temperature 90% 90% 2.7 VIN 88% 88% 3.6 VIN 86% 86% 5.0 VIN 84% 84% 82% 82% Efficiency Efficiency 3000 80% 78% 80% 78% 76% 76% 74% 74% 72% 72% 70% 70% -40C +25C +85C 0 1000 2000 3000 4000 0 5000 1000 2000 3000 4000 5000 Load Current (mA) Load Current (mA) Figure 9. Efficiency vs. Load Current and Input Voltage, VOUT=0.9 V Figure 10. Efficiency vs. Load Current and Temperature, VIN=5 V, VOUT=1.2 V 90% 90% 2.7 VIN 3.6 VIN 85% 85% 5.0 VIN 80% Efficiency Efficiency 80% 75% 70% 75% 3.6VIN, 1.2VOUT, L=MMD-04ABNR33M 70% 3.6VIN, 1.2VOUT, L=VLC5020T-R47M 5.0VIN, 1.2VOUT, L=MMD-04ABNR33M 65% 65% 60% 60% 5.0VIN, 1.2VOUT, L=VLC5020T-R47M 5.0VIN, 0.9VOUT, L=MMD-04ABNR33M 5.0VIN, 0.9VOUT, L=VLC5020T-R47M 0 1000 2000 3000 4000 5000 0 Load Current (mA) 2000 3000 4000 5000 6000 7000 Load Current (mA) Figure 11. Efficiency vs. Load Current and Input Voltage, VOUT=0.6 V (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 1000 Figure 12. Efficiency vs. Load Current, VIN=3.6 V and 5 V, VOUT=1.2 V and 0.9 V www.fairchildsemi.com 11 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Typical Characteristics Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25C; circuit and components according to Figure 1 and Table 1. 25 20 2.7 VIN 2.7 VIN 3.6 VIN 5.0 VIN 16 VOUT Shift (mV) VOUT Shift (mV) 3.6 VIN 5.0 VIN 20 15 10 5 12 8 4 0 0 0 1000 2000 3000 4000 5000 0 1000 Load Current (mA) Figure 13. Output Regulation vs. Load Current and Input Voltage, VOUT=1.2 V 3000 4000 5000 Figure 14. Output Regulation vs. Load Current and Input Voltage, VOUT=0.9 V 1,000 1,000 Load Current (mA) 800 Load Current (mA) 2000 Load Current (mA) 600 400 800 600 400 PFM Exit PFM Exit PFM Enter PFM Enter 200 2.5 3.0 3.5 4.0 4.5 5.0 200 5.5 2.5 3.0 Input Voltage (V) 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) Figure 15. PFM Entry / Exit Level vs. Input Voltage, VOUT=1.2 V Figure 16. PFM Entry / Exit Level vs. Input Voltage, VOUT=0.9 V 25 3,000 3.6VIN, 1.2VOUT, Auto 3.6VIN, 1.2VOUT, PWM Switching Frequency (KHz) Output Ripple (mVpp) 2,500 5.0VIN, 1.2VOUT, Auto 20 5.0VIN, 1.2VOUT, PWM 5.0VIN, 0.9VOUT, Auto 15 10 5 2,000 1,500 1,000 3.6VIN, 1.2VOUT, Auto 3.6VIN, 0.9VOUT, Auto 500 5.0VIN, 1.2VOUT, Auto 5.0VIN, 0.9VOUT, Auto 0 0 0 1000 2000 3000 4000 5000 0 Load Current (mA) 2000 3000 4000 5000 Load Current (mA) Figure 17. Output Ripple vs. Load Current, VIN=5 V and 3.6 V, VOUT=1.2 V and 0.9 V, Auto and FPWM (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 1000 Figure 18. Frequency vs. Load Current, VIN=5 V and 3.6 V, VOUT=1.2 V and 0.9 V, Auto PWM www.fairchildsemi.com 12 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Typical Characteristics (Continued) 80 60 70 50 Input Current (mA) Input Supply Current (A) Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25C; circuit and components according to Figure 1 and Table 1. 60 50 40 30 40 30 20 10 -40C -40C +25C +25C +85C 20 +85C 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 Input Supply Voltage (V) 4.0 4.5 5.0 5.5 Input Voltage (V) Figure 19. Quiescent Current vs. Input Voltage and Temperature, Auto PWM Figure 20. Quiescent Current vs. Input Voltage and Temperature, FPWM 60 70 3.6VIN, 1.2VOUT, 2A Load 3.6VIN, 0.9VOUT, 2A Load 50 60 PSRR (dB) Input Current (A) 5.0VIN, 0.9VOUT, 18mA Load, PFM 40 30 EN_BUCK=0, -40C EN_BUCK=0, +25C 20 50 40 EN_BUCK=0, +85C EN=0, +25C 30 10 0 20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 10 Input Voltage (V) 100 1,000 10,000 100,000 Frequency (Hz) Figure 21. Shutdown Current vs. Input Voltage and Temperature Figure 22. PSRR vs. Frequency Figure 23. Line Transient, 3-4 VIN, 1.2 VOUT, 10 s Edge, 50 Load Figure 24. Line Transient, 3-4 VIN, 1.2 VOUT, 10 s Edge, 1 A Load (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 13 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Typical Characteristics (Continued) Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25C; circuit and components according to Figure 1 and Table 1. Figure 25. Load Transient, 5 VIN, 0.9 VOUT, 0.3-3 A, 100 ns Edge Figure 26. Load Transient, 3.6 VIN, 1.2 VOUT, 0.3-3 A, 100 ns Edge Figure 27. Load Transient, 3.6 VIN, 1.2 VOUT, 0.3-3 A, 100 ns Edge, COUT=4x22 F Figure 28. Load Transient, 3.6 VIN, 1.2 VOUT, 1.5-6 A, 100 ns Edge, COUT=4x22 F Figure 29. Input Over-Voltage Protection (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 14 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Typical Characteristics (Continued) Unless otherwise specified, Auto PFM/PWM, VIN = 3.6 V, VOUT = 1.2 V, SCL = SDA = VSEL = EN = 1.8 V, TA = 25C; circuit and components according to Figure 1 and Table 1. Figure 30. Startup / Shutdown, No Load, VOUT=0.9 V Figure 31. Startup / Shutdown, 180 m Load, VOUT=0.9 V Figure 32. Overload Protection and Recovery Figure 33. Startup into Faulted Load, VOUT=0.9 V (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 15 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Typical Characteristics (Continued) The FAN53555 is a step-down switching voltage regulator that delivers a programmable output voltage from an input voltage supply of 2.5 V to 5.5 V. Using a proprietary architecture with synchronous rectification, the FAN53555 is capable of delivering 5 A at over 80% efficiency. Pulse currents as high as 6.5 A can be supported by the 05 option. The regulator operates at a nominal frequency of 2.4 MHz at full load, which reduces the value of the external components to 330 nH for the output inductor and 22 F for the output capacitor. High efficiency is maintained at light load with single-pulse PFM. output voltage. Synchronous rectification is inhibited during soft-start, allowing the IC to start into a pre-charged capacitive load. If large output capacitance values are used, the regulator may fail to start. Maximum COUT capacitance for successfully starting with a heavy constant-current load is approximately: COUTMAX ILIMPK ILOAD (1) where COUTMAX is expressed in F and ILOAD is the load current during soft-start, expressed in A. 2 The FAN53555 integrates an I C-compatible interface, allowing transfers up to 3.4 Mbps. This communication interface can be used to: Dynamically re-program the output voltage in 10 mV, 12.826 mV increments (option 04, 09, and 042), 12.5 mV increments (option 23), or 12.967 mV increments (option 24); Reprogram the mode to enable or disable PFM; Control voltage transition slew rate; or Enable / disable the regulator. If the regulator is at its current limit for 16 consecutive current limit cycles, the regulator shuts down and enters 3-state before reattempting soft-start 1700 ms later. This limits the duty cycle of full output current during soft-start to prevent excessive heating. The IC allows for software enable of the regulator, when EN is HIGH, through the BUCK_EN bits. BUCK_EN0 and BUCK_EN1 are both initialized HIGH in the 00, 04, 08, 09, 23, 24, and 042 options. These options start after a POR regardless of the state of the VSEL pin. Control Scheme In the 01 and 05 options, BUCK_EN0 and BUCK_EN1 are initialized to 10. Using these options, VSEL must be LOW after a POR if the IC is powering the processor used to 2 communicate through I C. The 03 option has the VSEL input to the modulator logic internally tied LOW. The FAN53555 uses a proprietary non-linear, fixed-frequency PWM modulator to deliver a fast load transient response, while maintaining a constant switching frequency over a wide range of operating conditions. The regulator performance is independent of the output capacitor ESR, allowing for the use of ceramic output capacitors. Although this type of operation normally results in a switching frequency that varies with input voltage and load current, an internal frequency loop holds the switching frequency constant over a large range of input voltages and load currents. Table 5. Hardware and Software Enable Pins For very light loads, the FAN53555 operates in Discontinuous Current Diode (DCM) single-pulse PFM, which produces low output ripple compared with other PFM architectures. Transition between PWM and PFM is relatively seamless, providing a smooth transition between DCM and CCM Modes. PFM can be disabled by programming the MODE bit HIGH in the VSEL registers. BITS EN VSEL BUCK_EN0 BUCK_EN1 Output 0 X X X OFF 1 0 0 X OFF 1 0 1 X ON 1 1 X 0 OFF 1 1 X 1 ON VSEL Pin and I2C Programming Output Voltage Enable and Soft-Start The output voltage is set by the NSELx control bits in VSEL0 and VSEL1 registers. The output voltage for options 00, 01, 03, 05, 08, and 18 is given as: When the EN pin is LOW; the IC is shut down, all internal circuits are off, and the part draws very little current. In this 2 state, I C cannot be written to or read from. For all options except the 04, 24, and 042 options, all register values are kept while EN pin is LOW. For the 04, 24 and 042 options; registers are reset to default values when EN pin is LOW. For all options, registers are reset to default values during a Power On Reset (POR). VOUT 0.60V NSELx 10mV (2) For example, when NSEL = 011111 (31 decimal), then VOUT = 0.60 + 0.310 = 0.91 V. For the 04, 042, and 09 options; the output voltage is given as: When the OUTPUT_DISCHARGE bit in the CONTROL register is enabled (logic HIGH) and the EN pin is LOW or the BUCK_ENx bit is LOW, a load is connected from VOUT to GND to discharge the output capacitors. VOUT 0.603V NSELx 12.826mV (3) For the 13 option, the output voltage is given as: VOUT 0.80V NSELx 10mV Raising EN while the BUCK_ENx bit is HIGH activates the part and begins the soft-start cycle. During soft-start, the modulator's internal reference is ramped slowly to minimize surge currents on the input and prevent overshoot of the (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 320 VOUT (4) www.fairchildsemi.com 16 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Operation Description Power Good (03 Option) VOUT 0.60V NSELx 12.5mV The PGOOD pin is an open-drain output indicating that the regulator is enabled when its state is HIGH. PGOOD pulls LOW under the following conditions: (5) For the 24 option, the output voltage is given as: VOUT 0.603V NSELx 12.967mV Regulator is disabled (EN pin LOW, disabled by I C, fault time-out, UVLO, OVP, over-temperature); Regulator is performing a soft-start. (6) Output voltage can also be controlled by toggling the VSEL pin LOW or HIGH. VSEL LOW corresponds to VSEL0 and VSEL HIGH corresponds to VSEL1. Upon POR, VSEL0 and VSEL1 are reset to their default voltages, shown in Table 9. 2 2 PGOOD remains HIGH during I C initiated VOUT transitions. Current Limiting A heavy load or short circuit on the output causes the current in the inductor to increase until a maximum current threshold is reached in the high-side switch. Upon reaching this point, the high-side switch turns off, preventing high currents from causing damage. Sixteen consecutive current limit cycles in current limit cause the regulator to shut down and stay off for about 1700 s before attempting a restart. Transition Slew Rate Limiting When transitioning from a low to high voltage, the IC can be programmed for one of eight possible slew rates using the SLEW bits in the CONTROL register. Table 6. Transition Slew Rate Decimal Bin Slew Rate 0 000 64.00 mV / s 1 001 32.00 mV / s 2 010 16.00 mV / s 3 011 8.00 mV / s When the die temperature increases, due to a high load condition and/or high ambient temperature, the output switching is disabled until the die temperature falls sufficiently. The junction temperature at which the thermal shutdown activates is nominally 150C with a 17C hysteresis. 4 100 4.00 mV / s Monitor Register (Reg05) 5 101 2.00 mV / s 6 110 1.00 mV / s The Monitor register indicates of the regulation state of the IC. If the IC is enabled and is regulating, its value is (1000 0000). 7 111 0.50 mV / s I2C Interface Thermal Shutdown The FAN53555's serial interface is compatible with Standard, 2 Fast, Fast Plus, and HS Mode I C-Bus(R) specifications. The FAN53555's SCL line is an input and its SDA line is a bidirectional open-drain output; it can only pull down the bus when active. The SDA line only pulls LOW during data reads and when signaling ACK. All data is shifted in MSB (bit 7) first. Transitions from high to low voltage rely on the output load to discharge VOUT to the new set point. Once the high-to-low transition begins, the IC stops switching until VOUT has reached the new set point. For options 04, 042, 09, 23, and 24 where the Dynamic Voltage Scaling (DVS) step is not 10 mV; the actual slew rate is the corresponding number shown in Table 6 scaled by the ratio of the DVS step to 10 mV. For example, the slew rate of option 13 for Bin=011 is 8.00 mV / s X 12.5 mV / 10 mV = 10.00 mV / s. I2C Slave Address In hex notation, the slave address assumes a 0 LS Bit. The hex slave address is C0 for all options except -42, which has a hex slave address of C4. 2 Under-Voltage Lockout Table 7. I C Slave Address When EN is HIGH, the under-voltage lockout keeps the part from operating until the input supply voltage rises HIGH enough to properly operate. This ensures proper operation of the regulator during startup or shutdown. Input Over-Voltage Protection (OVP) When VIN exceeds VSDWN (about 6.2 V) the IC stops switching to protect the circuitry from internal spikes above 6.5 V. An internal filter prevents the circuit from shutting down due to noise spikes. (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 Option Hex 00 to 24 42 C0 C4 Bits 7 6 5 4 3 2 1 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 R/ W R/ W Other slave addresses can be assigned. Contact a Fairchild Semiconductor representative. www.fairchildsemi.com 17 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator For the 23 option, the output voltage is given as: Slave Releases SDA As shown in Figure 34, data is normally transferred when SCL is LOW. Data is clocked in on the rising edge of SCL. Typically, data transitions shortly at or after the falling edge of SCL to allow ample time for the data to set up before the next SCL rising edge. tSU;STA tHD;STA ACK(0) or NACK(1) SLADDR MS Bit SCL Figure 37. REPEATED START Timing Data change allowed High-Speed (HS) Mode SDA The protocols for High-Speed (HS), Low-Speed (LS), and Fast-Speed (FS) Modes are identical, except the bus speed for HS mode is 3.4 MHz. HS Mode is entered when the bus master sends the HS master code 00001XXX after a START condition. The master code is sent in Fast or Fast-Plus Mode (less than 1 MHz clock); slaves do not ACK this transmission. tH tSU SCL Figure 34. Data Transfer Timing Each bus transaction begins and ends with SDA and SCL HIGH. A transaction begins with a START condition, which is defined as SDA transitioning from 1 to 0 with SCL HIGH, as shown in Figure 35. tHD;STA SDA The master generates a REPEATED START condition (Figure 35) that causes all slaves on the bus to switch to HS Mode. 2 The master then sends I C packets, as described above, using the HS Mode clock rate and timing. Slave Address MS Bit The bus remains in HS Mode until a STOP bit (Figure 36) is sent by the master. While in HS Mode, packets are separated by REPEATED START conditions (Figure 37). SCL Read and Write Transactions Figure 35. START Bit The following figures outline the sequences for data read and write. Bus control is signified by the shading of the packet, A transaction ends with a STOP condition, which is defined as SDA transitioning from 0 to 1 with SCL HIGH, as shown in Figure 36. Slave Releases Master Drives Master Drives Bus defined as and All addresses and data are MSB first. tHD;STO 2 Symbol SCL Figure 36. STOP Bit 7 bits Slave Address 0 Definition R REPEATED START, see Figure 37 P STOP, see Figure 36 S START, see Figure 35 ACK. The slave drives SDA to 0 to acknowledge the preceding packet. NACK. The slave sends a 1 to NACK the preceding packet. A During a read from the FAN53555, the master issues a REPEATED START after sending the register address, and before resending the slave address. The REPEATED START is a 1 to 0 transition on SDA while SCL is HIGH, as shown in Figure 37. S . Table 8. I C Bit Definitions for Figure 38 & Figure 39 ACK(0) or NACK(1) SDA Slave Drives Bus A R REPEATED START, see Figure 37. P STOP, see Figure 36. 0 8 bits 0 8 bits 0 A Reg Addr A Data A P Figure 38. Write Transaction 7 bits S Slave Address 0 0 8 bits 0 A Reg Addr A 7 bits R Slave Address 1 0 8 bits 1 A Data A P Figure 39. Read Transaction (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 18 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Bus Timing Table 9. Register Map Hex Address 00 01 02 03 04 05 Name VSEL0 VSEL1 POR Default Function Controls VOUT settings when VSEL pin = 0 Controls VOUT settings when VSEL pin = 1 Determines whether VOUT output discharge is CONTROL enabled and also the slew rate of positive transitions ID1 ID2 Read-only register identifies vendor and chip type Read-only register identifies die revision MONITOR Indicates device status (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 Option VOUT Binary Hex 00 1.050 10101101 AD 08, 18 1.020 10101010 AA 01, 03, 05 0.900 10011110 9E 04, 1.100 10100111 A7 24 1.225 10110000 B0 13 1.150 10100011 A3 23 1.150 10101100 AC 09 1.100 10100111 A7 00 1.200 11111100 FC 01, 05 1.000 01101000 68 04, 1.200 11101111 EF 24 1.212 10101111 AF 08, 18 1.150 10110111 B7 13 1.150 10100011 A3 23 1.150 10101100 AC 09 1.100 11100111 E7 00, 01, 03, 04, 05, 24 10000000 80 08, 09, 18 00000000 00 13, 23 10110000 B0 00, 13, 23, 24 10000000 80 01 10000001 81 03 10000011 83 04 10000100 84 05 10000101 85 08, 18 10001000 88 09 10001100 8C All 0000XXXX 0X All X0000000 X0 www.fairchildsemi.com 19 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Register Description The following table defines the operation of each register bit. Bold indicates power-on default values. Bit VSEL0 Name R/W 7 BUCK_EN0 6 MODE0 Value Description Register Address: 00 1 Software buck enable. When EN pin is LOW, the regulator is off. When EN pin is HIGH, BUCK_EN bit takes precedent. 0 Allow Auto-PFM Mode during light load. 1 Forced PWM Mode. 00 Option 101101 08, 18 Options 101010 Sets VOUT value from 0.6 to 1.23 V in 10 mV steps (see Eq. (2)). 01, 03, 05 Options 011110 5:0 VSEL1 7 NSEL0 R/W BUCK_EN1 04 Option 100111 09 Option 100111 13 Option 100011 Sets VOUT value from 0.8 to 1.43 V in 10 mV steps (see Eq. (4)). 23 Option 101100 Sets VOUT value from 0.6 to 1.3875 V in 12.5 mV steps (see Eq. (5)). 24 Option 110000 Sets VOUT value from 0.603 to 1.42 V in 12.967 mV steps (see Eq. (6)). Register Address: 01 00, 04, 08, 09,13, 18, 23, 24 Options 1 01, 05 Options 0 6 MODE1 Sets VOUT value from 0.603 to 1.411 V in 12.826 mV steps (see Eq. (3)). Software buck enable. When EN pin is LOW, the regulator is off. When EN pin is HIGH, BUCK_EN bit takes precedent. 08, 13, 18, 23, 24 Options 0 Allow AUTO-PFM Mode during light load. 00, 01, 04, 05, 09 Options 1 Forced PWM Mode. 00 Option 111100 01, 05 Options 101000 Sets VOUT value from 0.6 to 1.23 V in 10 mV steps (see Eq. (2)). 08, 18 Options 110111 5:0 NSEL1 04 Option 101111 09 Option 100111 Sets VOUT value from 0.603 to 1.411 V in 12.826 mV steps (see Eq. (3)). 13 Option 100011 Sets VOUT value from 0.8 to 1.43 V in 10 mV steps (see Eq. (4)). 23 Option 101100 Sets VOUT value from 0.6 to 1.3875 V in 12.5 mV steps (see Eq. (5)). 24 Option 101111 Sets VOUT value from 0.603 to 1.42 V in 12.967 mV steps (see Eq. (6)). (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 20 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Bit Definitions The following table defines the operation of each register bit. Bold indicates power-on default values. Bit Name CONTROL R/W Value Register Address: 02 08, 09, 18 Options 0 7 OUTPUT_DISCHARGE Description 00, 01, 03, 04, 05,13, 23, 24 Options 1 000 -111 When the regulator is disabled, VOUT is not discharged. When the regulator is disabled, VOUT discharges through an internal pull-down. 6:4 SLEW 3 Reserved 0 Always reads back 0 04, 09, 24 Options RESET 0 Setting to 1 resets all registers to default values. All other options Reserved 0 Always reads back 0 00 Always reads back 00 011 2 1:0 Reserved ID1 R 7:5 VENDOR 100 Reserved 0 DIE_ID ID2 R 7:4 Reserved Default value for 13 and 23 options Register Address: 03 4 3:0 Sets the slew rate for positive voltage transitions (see Table 6). Signifies Fairchild as the IC vendor Always reads back 0 0000 IC Type = 00 Option (FAN53555UC00X / FAN53555BUC24X) 0001 IC Type = 01 Option (FAN53555UC01X) 0011 IC Type = 03 Option (FAN53555UC03X) 0100 IC Type = 04 Option (FAN53555UC04X) 0100 IC Type = 042 Option (FAN53555UC042X) 0101 IC Type = 05 Option (FAN53555UC05X / FAN53555BUC05X) 1000 IC Type = 08, 18 Options (FAN53555UC08X / FAN53555BUC08X, FAN53555UC18X / FAN53555BUC18X) 1100 IC Type = 09 Option (FAN53555UC09X / FAN53555BUC09X) 0000 IC Type = 13 Option (FAN53555UC13X / FAN53555BUC13X) 0000 IC Type = 23 Option (FAN53555BUC23X) Register Address: 04 0000 Always reads back 0000 00 Option 0011 01 Option 0011 03 Option 0011 3:0 DIE_REV 04 Option 1111 24-Option 0100 IC mask revision 042 Option 1111 05 Option 0011 08, 18 Options 0001 (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 21 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Bit Definitions FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Bit Definitions The following table defines the operation of each register bit. Bold indicates power-on default values. Bit Name Value Description BUC08, BUC18 Options 1111 09 Option 1111 13 Option 1111 23 Option 1100 MONITOR R Register Address: 05 7 PGOOD 0 6:0 Not used 000 0000 (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 1: buck is enabled and soft-start is completed Always reads back 000 0000 www.fairchildsemi.com 22 Increasing COUT has negligible effect on loop stability and can be increased to reduce output voltage ripple or to improve transient response. Output voltage ripple, VOUT, is calculated by: Selecting the Inductor The output inductor must meet both the required inductance and the energy-handling capability of the application. The inductor value affects the average current limit, the output voltage ripple, and the efficiency. f C ESR2 1 VOUT IL SW OUT 2 D 1 D 8 fSW COUT The ripple current (I) of the regulator is: I VOUT VIN V VOUT IN L fSW where COUT is the effective output capacitance. (7) The capacitance of COUT decreases at higher output voltages, which results in higher VOUT. Equation (10) is only valid for Continuous Current Mode (CCM) operation, which occurs when the regulator is in PWM Mode. The maximum average load current, IMAX(LOAD), is related to the peak current limit, ILIM(PK), by the ripple current such that: IMAX(LOAD ) ILIM(PK ) I 2 For large COUT values, the regulator may fail to start under a load. If an inductor value greater than 1.0 H is used, at least 30 F of COUT should be used to ensure stability. (8) The FAN53555 is optimized for operation with L=330 nH, but is stable with inductances up to 1.0 H (nominal). The inductor should be rated to maintain at least 80% of its value at ILIM(PK). Failure to do so lowers the amount of DC current the IC can deliver. The lowest VOUT is obtained when the IC is in PWM Mode and, therefore, operating at 2.4 MHz. In PFM Mode, fSW is reduced, causing VOUT to increase. ESL Effects Efficiency is affected by the inductor DCR and inductance value. Decreasing the inductor value for a given physical size typically decreases the DCR; but since I increases, the RMS current increases, as do core and skin-effect losses. IRMS IOUT(DC) 2 I 2 12 The Equivalent Series Inductance (ESL) of the output capacitor network should be kept low to minimize the squarewave component of output ripple that results from the division ratio COUT ESL and the output inductor (LOUT). The squarewave component due to the ESL can be estimated as: (9) VOUT(SQ ) VIN The increased RMS current produces higher losses through the RDS(ON) of the IC MOSFETs as well as the inductor ESR. Increase (Eq.(11)) Decrease (11) To minimize ESL, try to use capacitors with the lowest ratio of length to width. 0805s have lower ESL than 1206s. If low output ripple is a chief concern, some vendors produce 0508 or 0612 capacitors with ultra-low ESL. Placing additional small-value capacitors near the load also reduces the highfrequency ripple components. Table 10. Effects of Inductor Value (from 330 nH Recommended) on Regulator Performance VOUT ESLCOUT L1 A good practice to minimize this ripple is to use multiple output capacitors to achieve the desired COUT value. For example, to obtain COUT=20 F, a single 22 F 0805 would produce twice the square wave ripple as two x 10 F 0805. Increasing the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor size, increased inductance usually results in an inductor with lower saturation current. IMAX(LOAD) (10) Transient Response Degraded Input Capacitor Inductor Current Rating The ceramic input capacitors should be placed as close as possible between the VIN pin and PGND to minimize the parasitic inductance. If a long wire is used to bring power to the IC, additional "bulk" capacitance (electrolytic or tantalum) should be placed between CIN and the power source lead to reduce under-damped ringing that can occur between the inductance of the power source leads and CIN. The current limit circuit can allow substantial peak currents to flow through L1 under worst-case conditions. If it is possible for the load to draw such currents, the inductor should be capable of sustaining the current or failing in a safe manner. For space-constrained applications, a lower current rating for L1 can be used. The FAN53555 may still protect these inductors in the event of a short circuit, but may not be able to protect the inductor from failure if the load is able to draw higher currents than the DC rating of the inductor. The effective CIN capacitance value decreases as VIN increases due to DC bias effects. This has no significant impact on regulator performance. Output Capacitor and VOUT Ripple Table 1 suggests 0805 capacitors, but 0603 capacitors may be used if space is at a premium. Due to voltage effects, the 0603 capacitors have a lower in-circuit capacitance than the 0805 package, which can degrade transient response and output ripple. (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 23 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Application Information Heat is removed from the IC through the solder bumps to the PCB copper. The junction-to-ambient thermal resistance (JA) is largely a function of the PCB layout (size, copper weight, and trace width) and the temperature rise from junction to ambient (T). 4. For the FAN53555UC, JA is 38C/W when mounted on its four-layer evaluation board in still air with two-ounce outer layer copper weight and one-ounce inner layers. Halving the copper thickness results in an increased JA of 48C/W. 5. PL ILOAD DCR L 2 2. Calculate total power dissipation using: 1 PT VOUT ILOAD 1 Determine IC losses by removing inductor losses (step 3) from total dissipation: (14) Determine device operating temperature: T PIC JA and (15) TIC TA T To calculate maximum operating temperature (<125C) for a specific application: Use efficiency graphs to determine efficiency for the desired VIN, VOUT, and load conditions. (13) PIC PT PL For long-term reliable operation, the IC's junction temperature (TJ) should be maintained below 125C. 1. Estimate inductor copper losses using: It is important to note that the RDS(ON) of the IC's power MOSFETs increases linearly with temperature at about 1.21%/C. This causes the efficiency () to degrade with increasing die temperature. (12) where is efficiency from Figure 7 through Figure 12. (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 24 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator 3. Thermal Considerations Connect VOUT to "+' side of COUT cap Do not connect AGND to GND. Place via in pad of AGND and connect directly to System GND Dedicated GND bumps for CIN and COUT, which connect directly to System GND of phone board Route all logic on this layer or inner layer VSEL EN SCL VOUT SDA GND GND AGND GND GND GND GND COUT CIN CIN1 VIN VIN SW SW VIN VIN SW SW VIN vias bring power to device L VOUT bus should be taken from + side capacitor Figure 40. Guidance for Layer 1 Dedicated GND bumps for CIN and COUT, which connect directly to System GND of phone board Route all logic on this layer or inner layer VSEL EN SCL VOUT SDA GND GND AGND GND GND GND GND VIN VIN SW SW VIN VIN SW SW Connect VOUT to "+' side of COUT cap Figure 41. Guidance for Layer 2 (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 25 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Layout Recommendation VSEL EN SCL VOUT SDA GND GND AGND GND GND GND GND VIN VIN SW SW VIN VIN SW SW Connect AGND directly to this layer Dedicated System Ground Figure 42. Guidance for Layer 3 1. FB trace connects to "+" side of COUT cap. 3. Do not place COUT near FAN53555, place cap near load Length should be less than 0.5 inches 2. Max trace resistance between FAN53555 and CPU should not exceed 30m Width (mils) 25 25 25 25 Table provides resistance values for given Copper Oz. Length (mils) 500 500 500 500 Copper (Oz) 2 1.5 1 0.5 Resistance (m) 4.2 4.9 5.8 7.6 Figure 43. Remote Sensing Schematic (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 www.fairchildsemi.com 26 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Dedicated GND bumps for CIN and COUT, which connect directly to System GND of phone board Dedicated GND bumps for CIN and COUT, which connect directly to System GND of phone board Route all logic on this layer or inner layer CIN CIN1 VSEL EN SCL VOUT SDA GND GND AGND GND GND GND GND VIN VIN SW SW VIN VIN SW SW VIN vias bring power to device L Length of VOUT bus leading to CPU should be less than 0.5inches Figure 44. Remote Sensing Guidance, Top Layer Product-Specific Dimensions Product E X Y Land Pattern FAN53555UC00 to FAN53555UC08X, FAN53555BUC05X 2.000 0.03 1.600 0.03 0.200 0.200 Option 1 FAN53555BUC08X, FAN53555BUC09X, FAN53555UC09X, FAN53555UC13X, FAN53555BUC13X, 2.015 0.03 FAN53555UC18X, FAN53555BUC18X, FAN53555BUC23X, FAN53555UC24X, FAN53555BUC24X, 1.615 0.03 0.2075 0.2075 Option 2 (c) 2010 Fairchild Semiconductor Corporation FAN53555 * Rev. 1.14 D www.fairchildsemi.com 27 FAN53555 -- 5 A, 2.4 MHz, Digitally Programmable TinyBuckTM Regulator Connect VOUT to "+' side of COUT cap Do not connect AGND to GND. Place via in pad of AGND and connect directly to System GND BALL A1 INDEX AREA F A E 1.20 B A1 Cu Pad 0.03 C 1.20 A1 2X 1.60 D 0.40 Mask Opening Mask Opening 0.40 0.40 option 1 0.03 C 2X TOP VIEW Cu Pad option 2 RECOMMENDED LAND PATTERN (NSMD TYPE) 0.06 C 0.625 0.547 0.05 C E C SEATING PLANE SIDE VIEWS D 0.005 1.20 0.40 20X E D C B 1.60 0.40 A 1 2 3 4 BOTTOM VIEW F C A B NOTES: A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCE PER ASMEY14.5M, 2009. D. DATUM C IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. G. DRAWING FILNAME: MKT-UC020AArev4. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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