LTC2152-12/ LTC2151-12/LTC2150-12 Single 12-Bit 250Msps/ 210Msps/170Msps ADCs Features n n n n n n n n n n n n Description The LTC(R)2152-12/LTC2151-12/LTC2150-12 are a family of 250Msps/210Msps/170Msps 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 68.5dB SNR and 90dB spurious free dynamic range (SFDR). The 1.25GHz input bandwidth allows the ADC to undersample high input frequencies with good performance. The latency is only five clock cycles. 68.5dB SNR 90dB SFDR Low Power: 347mW/333mW/306mW Total Single 1.8V Supply DDR LVDS Outputs Easy-to-Drive 1.5VP-P Input Range 1.25GHz Full Power Bandwidth S/H Optional Clock Duty Cycle Stabilizer Low Power Sleep and Nap Modes Serial SPI Port for Configuration Pin-Compatible 14-Bit Versions 40-Lead (6mm x 6mm) QFN Package DC specs include 0.26LSB INL (typ), 0.16LSB DNL (typ) and no missing codes over temperature. The transition noise is 0.54LSBRMS. Applications n n n n n n The digital outputs are double-data rate (DDR) LVDS. The ENC+ and ENC- inputs can be driven differentially with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. Communications Cellular Basestations Software Defined Radios Medical Imaging High Definition Video Testing and Measurement Instruments L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application LTC2152-12: 32K Point 2-Tone FFT, fIN = 71MHz and 69MHz, 250Msps VDD OVDD CLOCK S/H 12-BIT PIPELINED ADC CORRECTION LOGIC OUTPUT DRIVERS D10_11 * * * D0_1 OGND CLOCK/DUTY CYCLE CONTROL 21521012 TA01a GND -20 DDR LVDS AMPLITUDE (dBFS) ANALOG INPUT 0 -40 -60 -80 -100 -120 0 20 40 60 80 100 FREQUENCY (MHz) 120 21521012 TA01b 21521012f 1 LTC2152-12/ LTC2151-12/LTC2150-12 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) D8_9- D8_9+ D10_11- D10_11+ GND SDO SDI SCK CS PAR/SER TOP VIEW 40 39 38 37 36 35 34 33 32 31 VDD 1 30 OVDD VDD 2 29 D6_7+ GND 3 28 D6_7- AIN+ 4 27 CLKOUT+ AIN- 5 26 CLKOUT - GND 41 GND 6 25 D4_5+ SENSE 7 24 D4_5- VREF 8 23 D2_3+ VCM 9 22 D2_3- GND 10 21 OGND OVDD D0_1+ D0_1 - NC NC OF + OF - GND ENC- 11 12 13 14 15 16 17 18 19 20 ENC+ Supply Voltage VDD, OVDD................................................. -0.3V to 2V Analog Input Voltage AIN+, AIN -, PAR/SER, SENSE (Note 3)......................... -0.3V to (VDD + 0.2V) Digital Input Voltage ENC+, ENC- (Note 3)................. -0.3V to (VDD + 0.3V) CS, SDI, SCK (Note 4)............................ -0.3V to 3.9V SDO (Note 4).............................................. -0.3V to 3.9V Digital Output Voltage................. -0.3V to (OVDD + 0.3V) Operating Temperature Range LTC2152C, LTC2151C, LTC2150C.............. 0C to 70C LTC2152I, LTC2151I, LTC2150I............. -40C to 85C Storage Temperature Range................... -65C to 150C UJ PACKAGE 40-LEAD (6mm x 6mm) PLASTIC QFN TJMAX = 150C, JA = 33C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2152CUJ-12#PBF LTC2152CUJ-12#TRPBF LTC2152UJ-12 40-Lead (6mm x 6mm) Plastic QFN 0C to 70C LTC2152IUJ-12#PBF LTC2152IUJ-12#TRPBF LTC2152UJ-12 40-Lead (6mm x 6mm) Plastic QFN -40C to 85C LTC2151CUJ-12#PBF LTC2151CUJ-12#TRPBF LTC2151UJ-12 40-Lead (6mm x 6mm) Plastic QFN 0C to 70C LTC2151IUJ-12#PBF LTC2151IUJ-12#TRPBF LTC2151UJ-12 40-Lead (6mm x 6mm) Plastic QFN -40C to 85C LTC2150CUJ-12#PBF LTC2150CUJ-12#TRPBF LTC2150UJ-12 40-Lead (6mm x 6mm) Plastic QFN 0C to 70C LTC2150IUJ-12#PBF LTC2150IUJ-12#TRPBF LTC2150UJ-12 40-Lead (6mm x 6mm) Plastic QFN -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 21521012f 2 LTC2152-12/ LTC2151-12/LTC2150-12 Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) PARAMETER CONDITIONS MIN Resolution (No Missing Codes) l LTC2152-12 TYP MAX MIN 12 LTC2151-12 TYP MAX LTC2150-12 MIN TYP MAX 12 UNITS 12 Bits Integral Linearity Error Differential Analog Input (Note 6) l -1.2 0.26 1.2 -1.2 0.30 1.2 -1.2 0.30 1.2 LSB Differential Linearity Error Differential Analog Input l -0.6 0.16 0.6 -0.6 0.16 0.6 -0.6 0.16 0.6 LSB Offset Error (Note 7) l -13 5 13 -13 5 13 -13 5 13 mV Gain Error External Reference l -4 1 3 -4 1 3 -4 1 3 %FS Offset Drift Full-Scale Drift Internal Reference External Reference Transition Noise 20 20 20 V/C 30 10 30 10 30 10 ppm/C ppm/C 0.54 0.54 0.54 LSBRMS Analog Input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER VIN Analog Input Range (AIN+ - AIN-) CONDITIONS MIN TYP MAX UNITS 1.7V < VDD < 1.9V l 1.5 VIN(CM) Analog Input Common Mode (AIN+ + AIN-)/2 VP-P Differential Analog Input (Note 8) l VCM - 20mV VCM VCM + 20mV V VSENSE External Reference Mode External Reference Mode l 1.200 1.250 1.300 V IIN1 Analog Input Leakage Current 0 < AIN+, AIN- < VDD , No Encode l -1 1 A IIN2 SENSE Input Leakage Current 1.2V < SENSE < 1.3V l -1 1 A IIN3 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l -1 1 A tAP Sample-and-Hold Acquisition Delay Time 1 tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 CMRR Analog Input Common Mode Rejection Ratio BW-3B Full-Power Bandwidth ns psRMS 75 dB 1250 MHz Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 5) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 15MHz Input 70MHz Input 140MHz Input SFDR Spurious Free Dynamic Range 15MHz Input 2nd or 3rd Harmonic 70MHz Input 140MHz Input Spurious Free Dynamic Range 15MHz Input 4th Harmonic or Higher 70MHz Input 140MHz Input S/(N+D) Crosstalk Signal-to-Noise Plus Distortion Ratio Crosstalk Between Channels 15MHz Input 70MHz Input 140MHz Input Up to 315MHz Input MIN l l l l LTC2152-12 TYP MAX 67.1 68.5 68.4 68.0 72 90.6 88 80 81 98 95 85 66.5 68.5 68.4 67.7 -95 MIN LTC2151-12 TYP MAX 67.1 68.5 68.3 67.9 74 90.1 89 81 82 98 95 85 66.6 68.4 68.3 67.7 -95 LTC2150-12 MIN TYP MAX UNITS 67.3 68.5 68.3 67.8 dBFS dBFS dBFS 76 90 88 80 dBFS dBFS dBFS 83 98 95 84 dBFS dBFS dBFS 66.7 68.4 68.3 67.7 dBFS dBFS dBFS -95 dB 21521012f 3 LTC2152-12/ LTC2151-12/LTC2150-12 Internal Reference Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) PARAMETER CONDITIONS VCM Output Voltage IOUT = 0 MIN TYP MAX 0.439 * VDD - 18mV 0.439 * VDD 0.439 * VDD + 18mV VCM Output Temperature Drift UNITS V 37 VCM Output Resistance -1mA < IOUT < 1mA VREF Output Voltage IOUT = 0 ppm/C 4 1.225 1.250 VREF Output Temperature Drift 1.275 V 30 VREF Output Resistance -400A < IOUT < 1mA VREF Line Regulation 1.7V < VDD < 1.9V ppm/C 7 0.6 mV/V Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN VDD Analog Supply Voltage (Note 9) l 1.7 OVDD Output Supply Voltage LVDS Mode (Note 9) l 1.7 IVDD Analog Supply Current IOVDD Digital Supply Current PDISS Power Dissipation LTC2152-12 TYP MAX 1.8 MIN 1.9 1.7 1.7 LTC2151-12 TYP MAX 1.8 LTC2150-12 MIN TYP MAX 1.9 1.7 1.7 1.8 UNITS 1.9 V 1.8 1.9 1.8 1.9 1.8 1.9 V l 166 185 158 175 145 159 mA 1.75mA LVDS Mode 3.5mA LVDS Mode l 27 45 32 50 27 44 31 50 25 43 30 48 mA mA 1.75mA LVDS Mode 3.5mA LVDS Mode l 347 380 391 423 333 364 371 405 306 338 340 373 mW mW PNAP Nap Mode Power Clocked at fS(MAX) 105 99 93 mW PSLEEP Sleep Mode Power Clocked at fS(MAX) <2 <2 <2 mW Digital Inputs And Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1 1.9 V 1.5 V V 1.9 V ENCODE INPUTS (ENC+, ENC-) VID Differential Input Voltage (Note 8) l 0.2 VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 l 0.2 1.2 VIN Input Voltage Range ENC+, ENC- to GND RIN Input Resistance (See Figure 2) 10 k CIN Input Capacitance (Note 8) 2 pF DIGITAL INPUTS (CS, SDI, SCK) VIH High Level Input Voltage VDD = 1.8V l VIL Low Level Input Voltage VDD = 1.8V l IIN Input Current VIN = 0V to 1.8V l CIN Input Capacitance (Note 8) 1.3 V -10 0.6 V 10 A 3 pF SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used) ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V IOH Logic High Output Leakage Current SDO = 0V to 3.6V COUT Output Capacitance (Note 8) 200 l -10 10 4 A pF 21521012f 4 LTC2152-12/ LTC2151-12/LTC2150-12 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER DIGITAL DATA OUTPUTS CONDITIONS VOD Differential Output Voltage VOS Common Mode Output Voltage RTERM On-Chip Termination Resistance 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode Termination Enabled, OVDD = 1.8V l l l l MIN TYP MAX UNITS 247 125 1.125 1.125 350 175 1.250 1.250 100 454 250 1.375 1.375 mV mV V V Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) MIN LTC2152-12 TYP MAX MIN LTC2151-12 TYP MAX LTC2150-12 MIN TYP MAX SYMBOL PARAMETER CONDITIONS UNITS fS Sampling Frequency (Note 9) l 10 250 10 210 10 170 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 1.9 1.5 2 2 50 50 2.26 1.5 2.38 2.38 50 50 2.79 1.5 2.94 2.94 50 50 ns ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 1.9 1.5 2 2 50 50 2.26 1.5 2.38 2.38 50 50 2.79 1.5 2.94 2.94 50 50 ns ns DIGITAL DATA OUTPUTS SYMBOL PARAMETER CONDITIONS tD ENC to Data Delay tC ENC to CLKOUT Delay DATA to CLKOUT Skew tSKEW MIN LTC215X-12 TYP MAX UNITS CL = 5pF l 1.7 2 2.3 ns CL = 5pF l 1.3 1.6 2 ns t D - tC l 0.3 0.4 0.55 Pipeline Latency 5 5 ns Cycles SPI Port Timing (Note 8) tSCK SCK Period Write Mode, CSDO = 20pF Readback Mode RPULLUP = 2k, CSDO = 20pF 40 250 ns ns tS CS to SCK Set-Up Time l 5 ns tH SCK to CS Hold Time l 5 ns tDS SDI Set-Up Time l 5 ns tDH SDI Hold Time l 5 tDO SCK Falling to SDO Valid Readback Mode RPULLUP = 2k, CSDO = 20pF Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. l ns 125 ns Note 5: VDD = OVDD = 1.8V, fSAMPLE = 250MHz (LTC2152), 210MHz (LTC2151), or 170MHz (LTC2150), LVDS outputs, differential ENC+/ENC- = 2VP-P sine wave, input range = 1.5VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from -0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2's complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: Recommended operating conditions. 21521012f 5 LTC2152-12/ LTC2151-12/LTC2150-12 Typical Performance Characteristics LTC2152-12: Integral Nonlinearity (INL) LTC2152-12: Differential Nonlinearity (DNL) 0 0.50 2.0 1.5 -20 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 -0.5 AMPLITUDE (dBFS) 0.25 1.0 0 0 4095 -0.50 0 4095 OUTPUT CODE LTC2152-12: 32K Point FFT, fIN = 70MHz, -1dBFS, 250Msps 0 LTC2152-12: 32K Point FFT, fIN = 122MHz, -1dBFS, 250Msps -80 -100 -40 -60 -80 40 60 80 100 FREQUENCY (MHz) 120 -120 0 0 20 40 60 80 100 FREQUENCY (MHz) 120 -60 -80 -100 LTC2152-12: 32K Point FFT, fIN = 380MHz, -1dBFS, 250Msps 20 40 60 80 100 FREQUENCY (MHz) 120 21521012 G07 -80 0 20 -40 -60 -80 -120 40 60 80 100 FREQUENCY (MHz) 120 0 LTC2152-12: 32K Point FFT, fIN = 420MHz, -1dBFS, 250Msps -20 -40 -60 -80 -100 -100 0 -60 21521012 G06 AMPLITUDE (dBFS) -40 -40 -120 -20 AMPLITUDE (dBFS) -20 120 LTC2152-12: 32K Point FFT, fIN = 171MHz, -1dBFS, 250Msps 21521012 G05 LTC2152-12: 32K Point FFT, fIN = 229MHz, -1dBFS, 250Msps 40 60 80 100 FREQUENCY (MHz) -100 -100 20 20 -20 21521012 G04 AMPLITUDE (dBFS) 0 AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) -60 0 0 21521012 G03 -20 -40 -120 -120 21521012 G02 -20 0 -80 OUTPUT CODE 21521012 G01 -120 -60 -100 -1.5 0 -40 -0.25 -1.0 -2.0 LTC2152-12: 32K Point FFT, fIN = 15MHz, -1dBFS, 250Msps 0 20 40 60 80 100 FREQUENCY (MHz) 120 21521012 G08 -120 0 20 40 60 80 100 FREQUENCY (MHz) 120 21521012 G09 21521012f 6 LTC2152-12/ LTC2151-12/LTC2150-12 Typical Performance Characteristics 0 -40 -60 -80 -100 -120 -40 -60 -80 -100 0 20 40 60 80 100 FREQUENCY (MHz) -120 120 0 40 60 80 100 FREQUENCY (MHz) 20 -120 8000 6000 4000 30 15 2056 120 50 0 150 200 100 SAMPLE RATE (Msps) 110 250 dBFS 70 SFDR (dBFS) SNR (dBFS) 50 dBc 40 30 0 21521012 G16 0 50 40 20 10 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 AMPLITUDE (dBFS) 60 30 20 20 250 80 60 40 150 200 100 SAMPLE RATE (Msps) 90 70 60 50 LTC2152-12: SFDR vs Input Frequency, -1dBFS, 1.5V Range, 250Msps LTC2152-12: SNR vs Input Level, fIN = 70MHz, 1.5V Range, 250Msps dBFS 0 21521012 G15 21521012 G14 120 dBc 140 130 LVDS CURRENT 1.75mA 21521012 G13 LTC2152-12: SFDR vs Input Level, fIN = 70MHz, 1.5V Range, 250Msps 120 150 35 20 2000 40 60 80 100 FREQUENCY (MHz) 160 LVDS CURRENT 3.5mA 25 2052 OUTPUT CODE 20 LTC2152-12: IVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS IVDD (mA) IOVDD (mA) 10000 0 21521012 G12 40 14000 COUNT 120 170 45 16000 SFDR (dBFS) -80 -100 50 18000 80 -60 LTC2152-12: IOVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS 20000 0 2048 -40 21521012 G11 LTC2152-12: Shorted Input Histogram 12000 LTC2152-12: 32K Point 2-Tone FFT, fIN = 71MHz and 69MHz, 250Msps -20 215210 G10 100 0 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 LTC2152-12: 32K Point FFT, fIN = 907MHz, -1dBFS, 250Msps AMPLITUDE (dBFS) 0 LTC2152-12: 32K Point FFT, fIN = 567MHz, -1dBFS, 250Msps 10 -60 -50 -40 -30 -20 AMPLITUDE (dBFS) -10 0 21521012 G17 0 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz) 21521012 G18 21521012f 7 LTC2152-12/ LTC2151-12/LTC2150-12 Typical Performance Characteristics LTC2152-12: SNR vs Input Frequency, -1dBFS, 1.5V Range, 250Msps LTC2152-12: Frequency Response -0.5 75 -1.0 70 INPUT AMPLITUDE (dBFS) SNR (dBFS) 65 60 55 50 -2.0 -2.5 -3.0 -3.5 -4.0 45 40 -1.5 -4.5 -5.0 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz) 1000 100 INPUT FREQUENCY (MHz) 21521012 G19 LTC2151-12: Integral Nonlinearity INL 21521012 G20 LTC2151-12: Differential Nonlinearity DNL 0.50 2.0 0 1.5 -20 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 -0.5 AMPLITUDE (dBFS) 0.25 1.0 0 -40 -60 -80 -0.25 -1.0 -100 -1.5 -2.0 LTC2151-12: 32K Point FFT, fIN = 15MHz, -1dBFS, 210Msps 0 4095 -0.50 0 4095 -120 0 20 OUTPUT CODE OUTPUT CODE 40 60 80 FREQUENCY (MHz) 100 21521012 G22 21521012 G21 21521012 G23 0 -40 -60 -80 -100 -120 0 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 LTC2151-12: 32K Point FFT, fIN = 101MHz, -1dBFS, 210Msps -40 -60 -80 -100 0 20 40 60 80 FREQUENCY (MHz) 100 21521012 G24 -120 LTC2151-12: 32K Point FFT, fIN = 171MHz, -1dBFS, 210Msps -20 AMPLITUDE (dBFS) 0 LTC2151-12: 32K Point FFT, fIN = 71MHz, -1dBFS, 210Msps -40 -60 -80 -100 0 20 40 60 80 FREQUENCY (MHz) 100 21521012 G25 -120 0 20 40 60 80 FREQUENCY (MHz) 100 21521012 G26 21521012f 8 LTC2152-12/ LTC2151-12/LTC2150-12 Typical Performance Characteristics 0 -20 -20 -40 -60 -80 0 -20 -40 -60 -80 -100 -100 -120 0 20 40 60 80 FREQUENCY (MHz) 100 -120 0 0 20 40 60 80 FREQUENCY (MHz) -100 20 40 60 80 FREQUENCY (MHz) 100 -60 -80 -120 0 20 40 60 80 FREQUENCY (MHz) 100 2056 35 30 21521012 G33 15 100 150 140 130 LVDS CURRENT 1.75mA 120 20 2000 40 60 80 FREQUENCY (MHz) LTC2151-12: IVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS LVDS CURRENT 3.5mA 25 4000 20 21521012 G32 IVDD (mA) IOVDD (mA) 6000 0 160 40 14000 2048 2052 OUTPUT CODE -80 -120 45 16000 0 2044 -60 -100 50 18000 100 -40 LTC2151-12: IOVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS 8000 40 60 80 FREQUENCY (MHz) LTC2151-12: 32K Point 2-Tone FFT, fIN = 71MHz and 69MHz, 210Msps 21521012 G31 20000 COUNT 0 -40 LTC2151-12: Shorted Input Histogram 10000 20 -20 21521012 G30 12000 0 21521012 G29 LTC2151-12: 32K Point FFT, fIN = 907MHz, -1dBFS, 210Msps -100 0 -80 -120 AMPLITUDE (dBFS) -80 -120 100 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 -60 -60 21521012 G28 LTC2151-12: 32K Point FFT, fIN = 567MHz, -1dBFS, 210Msps -40 -40 -100 21521012 G27 0 LTC2151-12: 32K Point FFT, fIN = 417MHz, -1dBFS, 210Msps LTC2151-12: 32K Point FFT, fIN = 379MHz, -1dBFS, 210Msps AMPLITUDE (dBFS) 0 AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2151-12: 32K Point FFT, fIN = 227MHz, -1dBFS, 210Msps 0 42 128 168 84 SAMPLE RATE (Msps) 210 21521012 G34 110 0 42 126 168 84 SAMPLE RATE (Msps) 210 21521012 G35 21521012f 9 LTC2152-12/ LTC2151-12/LTC2150-12 Typical Performance Characteristics LTC2151-12: SNR vs Input Level, fIN = 70MHz, 1.5V Range, 210Msps LTC2151-12: SFDR vs Input Level, fIN = 70MHz, 1.5V Range, 210Msps 90 70 120 dBFS 100 dBFS 60 80 70 80 dBc 60 40 dBc 40 60 SFDR (dBFS) 50 SNR (dBFS) SFDR (dBFS) LTC2151-12: SFDR vs Input Level, -1dBFS, 1.5V Range, 210Msps 30 50 40 30 20 20 20 10 0 -80 -70 -60 -50 -40 -30 -20 -10 AMPLITUDE (dBFS) 0 10 0 10 -60 -50 -40 -30 -20 AMPLITUDE (dBFS) 21521012 G36 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz) 21521012 G38 LTC2151-12: Frequency Response -0.5 75 -1.0 70 -1.5 INPUT AMPLITUDE (dBFS) 65 SNR (dBFS) 0 0 21521012 G37 LTC2151-12: SNR vs Input Level, -1dBFS, 1.5V Range, 210Msps 60 55 50 -2.0 -2.5 -3.0 -3.5 -4.0 45 40 -10 -4.5 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz) -5.0 1000 100 INPUT FREQUENCY (MHz) 21521012 G39 21521012 G40 LTC2150-12: Differential Nonlinearity DNL LTC2150-12: Integral Nonlinearity INL 2.0 0 0.50 1.5 -20 DNL ERROR (LSB) INL ERROR (LSB) 0.5 0 -0.5 AMPLITUDE (dBFS) 0.25 1.0 0 -40 -60 -80 -0.25 -1.0 -100 -1.5 -2.0 LTC2150-12: 32K Point FFT, fIN = 15MHz, -1dBFS, 170Msps 0 4095 OUTPUT CODE -0.50 0 4095 OUTPUT CODE 21521012 G41 21521012 G42 -120 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 21521012 G43 21521012f 10 LTC2152-12/ LTC2151-12/LTC2150-12 Typical Performance Characteristics 0 -40 -60 -80 -100 -120 -40 -60 -80 -100 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 -120 0 0 10 20 30 40 50 60 FREQUENCY (MHz) -100 -120 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 -40 -60 -80 -120 0 0 -80 -100 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 21521012 G50 20 30 40 50 60 FREQUENCY (MHz) 80 LTC2150-12: 32K Point FFT, fIN = 420MHz, -1dBFS, 170Msps -60 -80 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 21521012 G49 0 LTC2150-12: 32K Point 2-Tone FFT, fIN = 71MHz and 69MHz, 170Msps -20 -40 -60 -80 -120 70 -40 -120 LTC2150-12: 32K Point FFT, fIN = 907MHz, -1dBFS, 170Msps -100 0 10 -100 AMPLITUDE (dBFS) -60 0 21521012 G46 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -120 21521012 G48 LTC2150-12: 32K Point FFT, fIN = 567MHz, -1dBFS, 170Msps -40 -80 -20 -100 -20 -120 80 LTC2150-12: 32K Point FFT, fIN = 380MHz, -1dBFS, 170Msps 21521012 G47 0 70 AMPLITUDE (dBFS) -80 -60 -100 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 -60 -40 21521012 G45 LTC2150-12: 32K Point FFT, fIN = 225MHz, -1dBFS, 170Msps -40 LTC2150-12: 32K Point FFT, fIN = 176MHz, -1dBFS, 170Msps -20 21521012 G44 0 0 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 LTC2150-12: 32K Point FFT, fIN = 121MHz, -1dBFS, 170Msps AMPLITUDE (dBFS) 0 LTC2150-12: 32K Point FFT, fIN = 70MHz, -1dBFS, 170Msps -40 -60 -80 -100 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 21521012 G51 -120 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 21521012 G52 21521012f 11 LTC2152-12/ LTC2151-12/LTC2150-12 Typical Performance Characteristics LTC2150-12: Shorted Input Histogram LTC2150-12: IOVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS 60 140 18000 55 135 16000 50 20000 14000 10000 8000 IVDD (mA) 12000 40 35 30 6000 4000 25 2000 20 0 2056 15 2064 2060 OUTPUT CODE LVDS CURRENT 1.75mA 110 0 34 136 102 68 SAMPLE RATE (Msps) 100 170 dBFS SFDR (dBFS) SNR (dBFS) 70 dBc 40 30 0 10 0 40 10 -60 -50 -40 -30 -20 AMPLITUDE (dBFS) 21521012 G56 -10 0 0 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz) 21521012 G58 21521012 G57 LTC2150-12: Frequency Response -0.5 75 -1.0 70 -1.5 INPUT AMPLITUDE (dBFS) 65 SNR (dBFS) 50 20 LTC2150-12: SNR vs Input Frequency, -1dBFS, 1.5V Range, 170Msps 60 55 50 -2.0 -2.5 -3.0 -3.5 -4.0 45 40 60 30 10 0 -80 -70 -60 -50 -40 -30 -20 -10 AMPLITUDE (dBFS) 170 80 20 20 102 136 68 SAMPLE RATE (Msps) 90 50 40 34 21521012 G55 dBFS 60 dBc 0 LTC2150-12: SFDR vs Input Frequency, -1dBFS, 1.5V Range, 170Msps 70 60 115 LTC2150-12: SNR vs Input Level, fIN = 70MHz, 1.5V Range, 170Msps 120 80 120 21521012 G54 LTC2150-12: SFDR vs Input Level, fIN = 70MHz, 1.5V Range, 170Msps 100 125 105 21521012 G53 SFDR (dBFS) 130 LVDS CURRENT 3.5mA 45 IOVDD (mA) COUNT LTC2150-12: IVDD vs Sample Rate, 15MHz Sine Wave Input, -1dBFS -4.5 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz) 21521012 G59 -5.0 1000 100 INPUT FREQUENCY (MHz) 21521012 G60 21521012f 12 LTC2152-12/ LTC2151-12/LTC2150-12 Pin Functions VDD (Pins 1, 2): 1.8V Analog Power Supply. Bypass to ground with 0.1F ceramic capacitor. Pins 1, 2 can share a bypass capacitor. GND (Pins 3, 6, 10, 13, 35, Exposed Pad Pin 41): ADC Power Ground. The exposed pad must be soldered to the PCB ground. AIN+ (Pin 4): Positive Differential Analog Input. AIN- (Pin 5): Negative Differential Analog Input. SENSE (Pin 7): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a 0.75V input range. An external reference between 1.2V and 1.3V applied to SENSE selects an input range of 0.6 * VSENSE. VREF (Pin 8): Reference Voltage Output. Bypass to ground with a 2.2F ceramic capacitor. Nominally 1.25V. VCM (Pin 9): Common Mode Bias Output; nominally equal to 0.439 * VDD. VCM should be used to bias the common mode of the analog inputs. Bypass to ground with a 0.1F ceramic capacitor. ENC+ (Pin 11): Encode Input. Conversion starts on the rising edge. ENC- (Pin 12): Encode Complement Input. Conversion starts on the falling edge. NC (Pins 16, 17): No Connection. OVDD (Pins 20, 30): 1.8V Output Driver Supply. Bypass each pin to ground with separate 0.1F ceramic capacitors. OGND (Pin 21): LVDS Driver Ground. SDO (Pin 36): In serial programming mode, (PAR/SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an opendrain N-channel MOSFET output that requires an external 2k pull-up resistor from 1.8V to 3.3V. If readback from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. SDI (Pin 37): In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In parallel programming mode (PAR/SER = VDD), SDI selects 3.5mA or 1.75mA LVDS output current (see Table 2). SCK (Pin 38): In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In parallel programming mode (PAR/SER = VDD), SCK controls the sleep mode (see Table 2). CS (Pin 39): In serial programming mode, (PAR/SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In parallel programming mode (PAR/ SER = VDD), CS controls the clock duty cycle stabilizer (see Table 2). PAR/SER (Pin 40): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI and SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK and SDI become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. 21521012f 13 LTC2152-12/ LTC2151-12/LTC2150-12 Pin Functions CLKOUT -/CLKOUT+ (Pins 26/27): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. LVDS Outputs (DDR LVDS) The following pins are differential LVDS outputs. The output current level is programmable. There is an optional internal 100 termination resistor between the pins of each LVDS output pair. OF-/OF+ (Pins 14/15): Over/Underflow Digital Output. OF+ is high when an overflow or underflow has occurred. This underflow is valid only when CLKOUT+ is low. In the second half clock cycle, the overflow is set to 0. D0_1-/D0_1+ to D10_11-/D10_11+ (Pins 18/19, 22/23, 24/25, 28/29, 31/32, 33/34): Double-Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D0, D2, D4, D6, D8, D10) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11) appear when CLKOUT+ is high. Functional Block Diagram VDD OVDD ANALOG INPUT 12-BIT PIPELINED ADC S/H VCM 0.1F CORRECTION LOGIC OUTPUT DRIVERS VCM BUFFER D10_11 * * * D0_1 DDR LVDS OGND BUFFER GND CLOCK CLOCK/DUTY CYCLE CONTROL CS SCK SDI SDO PAR/SER SPI VREF 2.2F 1.25V REFERENCE GND SENSE GND RANGE SELECT 21521012 F01 Figure 1. Functional Block Diagram 21521012f 14 LTC2152-12/ LTC2151-12/LTC2150-12 Timing Diagrams Double-Data Rate Output Timing, All Outputs Are Differential LVDS N tAP N+3 N+2 N+1 tL tH ENC- ENC+ CLKOUT + CLKOUT - tC D0_1- D0N-5 D0_1+ D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D10N-5 D11N-5 D10N-4 D11N-4 D10N-3 D11N-3 OFN-5 INVALID OFN-4 INVALID OFN-3 INVALID tD D10_11- D10_11+ OF - OF + 21521012 TD01 tSKEW SPI Port Timing (Readback Mode) tDS tS tDH tSCK tH CS SCK tDO SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 XX D7 HIGH IMPEDANCE XX D6 XX D5 XX D4 XX D3 XX D2 XX XX D1 D0 SPI Port Timing (Write Mode) CS SCK SDI SDO R/W HIGH IMPEDANCE A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 21521012 TD02 21521012f 15 LTC2152-12/ LTC2151-12/LTC2150-12 APPLICATIONS INFORMATION CONVERTER OPERATION INPUT DRIVE CIRCUITS The LTC2152-12/LTC2151-12/LTC2150-12 are 12-bit 250Msps/210Msps/170Msps A/D converters that are powered by a single 1.8V supply. The analog inputs must be driven differentially. The encode inputs should be driven differentially for optimal performance. The digital outputs are double-data rate LVDS. Additional features can be chosen by programming the mode control registers through a serial SPI port. Input Filtering ANALOG INPUT The analog input is a differential CMOS sample-and-hold circuit (Figure 2). It must be driven differentially around a common mode voltage set by the VCM output pin, which is nominally 0.439 * VDD. The inputs should swing from VCM - 0.375V to VCM + 0.375V. There should be a 180 phase difference between the inputs. If possible, there should be an RC lowpass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wide band noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application's input frequency. Transformer-Coupled Circuits Figure 3 shows the analog input being driven by an RF transformer with the common mode supplied through a pair of resistors via the VCM pin. At higher input frequencies a transmission line balun transformer (Figures 4 and 5) has better balance, resulting in lower A/D distortion. LTC2152-12 VDD + AIN RON 20 5 10 0.1F 0.1F 2pF IN VDD AIN- RON 20 5 VCM 2pF T1 1:1 4.7 LTC2152-12 AIN+ 25 2pF 25 2pF 10pF 0.1F 4.7 AIN- VDD T1: MACOM ETC1-1T 21521012 F03 Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz 1.2V 10k ENC+ 10 ENC- VCM 0.1F 0.1F T1 MABA 007159000000 IN 21521012 F02 Figure 2. Equivalent Input Circuit for Differential Input Clock T2 WBC1-1L AIN+ 45 45 0.1F LTC2152-12 4.7 0.1F 4.7 100 AIN- 21521012 F04 Figure 4. Recommended Front-End Circuit for Input Frequencies from 15MHz to 150MHz 21521012f 16 LTC2152-12/ LTC2151-12/LTC2150-12 Applications Information Amplifier Circuits VCM MABA 007159000000 IN 0.1F 10 0.1F T1 LTC2152-12 4.7 AIN+ 45 0.1F 100 45 0.1F 4.7 AIN- 21521012 F05 T1: MACOM ETC1-1-13 Figure 5. Recommended Front-End Circuit for Input Frequencies from 150MHz Up to 900MHz 50 0.1F 4.7 INPUT 0.1F 4.7 The LTC2152-12/LTC2151-12/LTC2150-12 has an internal 1.25V voltage reference. For a 1.5V input range with internal reference, connect SENSE to VDD. For a 1.5V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 7). LTC2152-12 3pF AIN+ 3pF At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 3 and 5) should convert the signal to differential before driving the A/D. The A/D cannot be driven single-ended. Reference VCM 0.1F 50 Figure 6 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC-coupled to the A/D so the amplifier's output common mode voltage can be optimally set to minimize distortion. AIN- 3pF 21521012 F06 Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals--do not route them next to digital traces on the circuit board. The encode inputs are internally biased to 1.2V through 10k equivalent resistance (Figure 8). If the common mode of the driver is within 1.1V to 1.5V, it is possible to drive Figure 6. Front-End Circuit Using a High Speed Differential Amplifier LTC2152-12 1.25V 5 VDD 1.2V VREF 2.2F 10k SCALER/ BUFFER SENSE ADC REFERENCE SENSE DETECTOR ENC- 21521012 F07 Figure 7. Reference Circuit 10k ENC+ 21521012 F08 Figure 8. Equivalent Encode Input Circuit 21521012f 17 LTC2152-12/ LTC2151-12/LTC2150-12 Applications Information the encode inputs directly. Otherwise, a transformer or coupling capacitors are needed (Figures 9 and 10). The maximum (peak) voltage of the input signal should never exceed VDD + 0.1V or go below -0.1V. For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (5%) duty cycle. Clock Duty Cycle Stabilizer DIGITAL OUTPUTS For good performance the encode signal should have a 50% (5%) duty cycle. If the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the encode signal changes frequency or is turned off, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock. The duty cycle stabilizer is enabled via SPI Register A2 (see SPI Control Register) or by CS in parallel programming mode. The digital outputs are double-data rate LVDS signals. Two data bits are multiplexed and output on each differential output pair. There are six LVDS output pairs (D0_1+/ D0_1- through D10_11-/D10_11+). Overflow (OF+/OF-) and the data output clock (CLKOUT+/CLKOUT-) each have an LVDS output pair. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. LTC2152-12 VDD 1.2V 10k 0.1F 10k 50 T1 100 0.1F 50 0.1F 21521012 F09 T1: MACOM ETC1-1-13 Figure 9. Sinusoidal Encode Drive LTC2152-12 VDD 1.2V 0.1F PECL OR LVDS INPUT 10k 10k ENC+ 100 0.1F ENC- 21521012 F10 Figure 10. PECL or LVDS Encode Drive 21521012f 18 LTC2152-12/ LTC2151-12/LTC2150-12 Applications Information An external 100 differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND, which are isolated from the A/D core power and ground. Programmable LVDS Output Current The default output driver current is 3.5mA. This current can be adjusted by serially programming mode control register A3 (see Table 3). Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. Optional LVDS Driver Internal Termination In most cases, using just an external 100 termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100 termination resistor can be enabled by serially programming mode control register A3. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. Overflow Bit The overflow output bit (OF) outputs a logic high when the analog input is either overranged or underranged. The overflow bit has the same pipeline latency as the data bits. When CLKINV is set to 0 in the SPI register A2, OF signal is valid when CLKOUT+ is low as shown in the Timing Diagram. Phase Shifting the Output Clock To allow adequate setup and hold time when latching the output data, the CLKOUT+ signal may need to be phase shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. Alternatively, the ADC can also phase shift the CLKOUT+/ CLKOUT- signals by serially programming mode control register A2. The output clock can be shifted by 0, 45, 90, or 135. To use the phase shifting feature, the clock duty cycle stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT+ and CLKOUT-, independently of the phase shift. The combination of these two features enables phase shifts of 45 up to 315 (Figure 11). ENC+ D0-D11, OF CLKOUT+ MODE CONTROL BITS PHASE SHIFT CLKINV CLKPHASE1 CLKPHASE0 0 0 0 0 45 0 0 1 90 0 1 0 135 0 1 1 180 1 0 0 225 1 0 1 270 1 1 0 315 1 1 1 21521012 F11 Figure 11. Phase-Shifting CLKOUT 21521012f 19 LTC2152-12/ LTC2151-12/LTC2150-12 Applications Information DATA FORMAT Table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. By default the output data format is offset binary. The 2's complement format can be selected by serially programming mode control register A4. CLKOUT OF D11-D0 (OFFSET BINARY) D11-D0 (2's COMPLEMENT) >0.75V 1 1111 1111 1111 0111 1111 1111 +0.75V 0 1111 1111 1111 0111 1111 1111 +0.7496337V 0 1111 1111 1110 0111 1111 1110 +0.0003662V 0 1000 0000 0001 0000 0000 0001 +0.000000V 0 1000 0000 0000 0000 0000 0000 -0.0003662V 0 0111 1111 1111 1111 1111 1111 -0.0007324V 0 0111 1111 1110 1111 1111 1110 -0.74963378V 0 0000 0000 0001 1000 0000 0001 -0.75V 0 0000 0000 0000 1000 0000 0000 < -0.75V 1 0000 0000 0000 1000 0000 0000 Digital Output Randomizer Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off-chip, these unwanted tones can be randomized, which reduces the unwanted tone amplitude. The digital output is randomized by applying an exclusiveOR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied--an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled by serially programming mode control register A4. OF OF D11 Table 1. Output Codes vs Input Voltage AIN+ - AIN- (1.5V Range) CLKOUT D11/D0 D10 RANDOMIZER ON D1 D10/D0 * * * D1/D0 D0 D0 21521012 F12 Figure 12. Functional Equivalent of Digital Output Randomizer PC BOARD CLKOUT FPGA OF D11/D0 LTC215X-12 D11 D10/D0 D1/D0 D0 * * * D10 D1 D0 21521012 F13 Figure 13. Unrandomizing for Randomized Digital Output Signal 21521012f 20 LTC2152-12/ LTC2151-12/LTC2150-12 Applications Information Alternate Bit Polarity Sleep Mode Another feature that may reduce digital feedback on the circuit board is the alternate bit polarity mode. When this mode is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11) are inverted before the output buffers. The even bits (D0, D2, D4, D6, D8, D10), OF and CLKOUT are not affected. This can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. The A/D may be placed in a power-down mode to conserve power. In sleep mode, the entire A/D converter is powered down, resulting in < 2mW power consumption. If the encode input signal is not disabled, the power consumption will be higher (up to 2mW at 250Msps). Sleep mode is enabled by mode control register A1 (serial programming mode), or by SCK (parallel programming mode). The digital output is decoded at the receiver by inverting the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit polarity mode is independent of the digital output randomizer--either both or neither function can be on at the same time. The alternate bit polarity mode is enabled by serially programming mode control register A4. Digital Output Test Patterns To allow in-circuit testing of the digital interface to the A/D, there are several test modes (activate by setting DTESTON) that force the A/D data outputs (OF, D11 to D0) to known values: All 1s: All outputs are 1 The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on VREF . For the suggested values in Figure 1, the A/D will stabilize after 0.1ms + 2500 * tp where tp is the period of the sampling clock. Nap Mode In nap mode the A/D core is powered down while the internal reference circuits stay active, allowing faster wakeup. Recovering from nap mode requires at least 100 clock cycles. Wake-up time from nap mode is guaranteed only if the clock is kept running, otherwise sleep mode, wake-up time conditions apply. Nap mode is enabled by setting register A1 in the serial programming mode. All 0s: All outputs are 0 DEVICE PROGRAMMING MODES Alternating: Outputs change from all 1s to all 0s on alternating samples The operating modes of the LTC215X-12 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Checkerboard: Outputs change from 1010101010101 to 0101010101010 on alternating samples. The digital output test patterns are enabled by serially programming mode control register A4. When enabled, the test patterns override all other formatting modes: 2's complement, randomizer, alternate-bit polarity. Output Disable The digital outputs may be disabled by serially programming mode control register A3. All digital outputs, including OF and CLKOUT, are disabled. The high impedance disabled state is intended for long periods of inactivity, it is not designed for multiplexing the data bus between multiple converters. Parallel Programming Mode To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK and SDI pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V CMOS logic. Table 2 shows the modes set by CS, SCK and SDI. 21521012f 21 LTC2152-12/ LTC2151-12/LTC2150-12 Applications Information Table 2. Parallel Programming Mode Control Bits) Software Reset PIN DESCRIPTION CS Clock Duty Cycle Stabilizer Control Bit If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset it is necessary to write 1 in register A0 (Bit D7). After the reset is complete, Bit D7 is automatically set back to zero. This register is WRITE-ONLY. 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On SCK Power-Down Control Bit 0 = Normal Operation 1 = Sleep Mode (entire ADC is powered down) SDI LVDS Current Selection Bit 0 = 3.5mA LVDS Current Mode 1 = 1.75mA LVDS Current Mode Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first sixteen rising edges of SCK. Any SCK rising edges after the first sixteen are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6:A0) will be read back on the SDO pin (see the Timing Diagrams). During a readback command the register is not updated and data on SDI is ignored. The SDO pin is an open-drain output that pulls to ground with a 200 impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and readback is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 3 shows a map of the mode control registers. GROUNDING AND BYPASSING The LTC215X-12 requires a printed circuit board with a clean unbroken ground plane in the first layer beneath the ADC. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM and VREF pins. Bypass capacitors must be located as close to the pins as possible. Size 0402 ceramic capacitors are recommended. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The analog inputs, encode signals and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. HEAT TRANSFER Most of the heat generated by the LTC215X-12 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. This pad should be connected to the internal ground planes by an array of vias. 21521012f 22 LTC2152-12/ LTC2151-12/LTC2150-12 Applications Information Table 3. Serial Programming Mode Register Map (PAR/SER = GND). An "X" indicates an unused bit. REGISTER A0: RESET REGISTER (ADDRESS 00h) WRITE-ONLY D7 D6 D5 D4 D3 D2 D1 D0 RESET X X X X X X X RESET Bit 7 Software Reset Bit 0 = Not Used 1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete. Bits 6-0 Unused bit. REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h) D7 D6 D5 D4 D3 D2 D1 D0 X X X X SLEEP NAP 0 0 Bits 7-4 Unused, these bits are read back as 0. Bit 3 SLEEP 0 = Normal Operation 1 = Power Down Entire ADC Bit 2 NAP 0 = Normal Mode 1 = Low Power Mode Bit 1-0 Must be set to 0. REGISTER A2: TIMING REGISTER (ADDRESS 02h) D7 X D6 D5 D4 D3 D2 D1 D0 X X X CLKINV CLKPHASE1 CLKPHASE0 DCS Bits 7-4 Unused, these bits are read back as 0. Bit 3 CLKINV Output Clock Invert Bit 0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams) 1 = Inverted CLKOUT Polarity Bits 2-1 CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits 00 = No CLKOUT Delay (as shown in the Timing Diagrams) 01 = CLKOUT+/CLKOUT- delayed by 45 (Clock Period * 1/8) 10 = CLKOUT+/CLKOUT- delayed by 90 (Clock Period * 1/4) 11 = CLKOUT+/CLKOUT- delayed by 135 (Clock Period * 3/8) Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on. Bit 0 DCS Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On 21521012f 23 LTC2152-12/ LTC2151-12/LTC2150-12 Applications Information REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h) D7 X D6 D5 D4 D3 D2 D1 D0 X X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF Bits 7-5 Unused, these bits are read back as 0. Bits 4-2 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current Bit 1 TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS output driver current is 2x the current set by ILVDS2:ILVDS0 Bit 0 OUTOFF Digital Output Mode Control Bits 0 = LVDS DDR 1 = LVDS Tristate (High Impedance) REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h) D7 D6 D5 D4 D3 D2 D1 D0 OUTTEST2 OUTTEST1 OUTTEST0 ABP 0 DTESTON RAND TWOSCOMP Bits 7-5 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits 000 = All Digital Outputs = 0 001 = All Digital Outputs = 1 010 = Alternating Output Pattern. OF, D11-D0 alternate between 00000 0000 0000 and 11111 1111 1111 100 = Checkerboard Output Pattern. OF, D11-D0 alternate between 01010 1010 1010 and 10101 0101 0101 Bit 4 ABP Alternate Bit Polarity Mode Control Bit 0 = Alternate Bit Polarity Mode Off 1 = Alternate Bit Polarity Mode On Bit 3 Must be set to 0. Bit 2 DTESTON Enable digital patterns (Bits 7-5) 0 = Normal Mode 1 = Enable the Digital Output Test Patterns Bit 1 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 0 TWOSCOMP Two's Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two's Complement Data Format 21521012f 24 LTC2152-12/ LTC2151-12/LTC2150-12 Applications Information 215210 F15 215210 F14 Silkscreen Top 215210 F16 Inner Layer 1 Inner Layer 2 215210 F17 215210 F18 Inner Layer 4 Inner Layer 3 215210 F19 Inner Layer 5 215210 F20 Bottom Layer 21521012f 25 LTC2152-12/ LTC2151-12/LTC2150-12 TYPICAL APPLICATIONS D8_9- VDD D8_9+ D10_11+ SDO SDI SCK CS PAR/SER D10_11- LTC2152-12 Schematic R19 10 3 4 R16 100 5 6 SENSE 7 8 VCM 10 C16 2.2F 9 10 41 C21 0.1F D8_9- 31 D10_11- 33 D8_9+ 32 SDO 36 GND 35 D10_11+ 34 VDD GND OVDD 30 29 D6_7+ 28 D6_7- AINA+ CLKOUT+ AINA- CLKOUT - LTC2152-12 GND SENSE 27 26 D4_5+ 25 D2_3+ 23 24 D4_5- VREF VCM D2_3- GND GND 0.1F OGND 22 21 D6_7+ D6_7- CLKOUT+ CLKOUT - D4_5+ D4_5- D2_3+ D2_3- DD R14 10 VDD 19 D0_1+ 20 OV AINA 2 17 NC 18 D0_1- - 1 15 OF + 16 NC AINA+ C13 2.2F 11 CLK+ 12 CLK- SENSE SCK 38 SDI 37 R9, 1k 13 GND 14 OF - TP3 PAR/SER 40 CS 39 0.2F 21521012 TA02 0.1F D0_1+ D0_1- NC NC OF + OF - 0.1F 0.1F 100 CLK+ CLK- 21521012f 26 LTC2152-12/ LTC2151-12/LTC2150-12 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UJ Package 40-Lead Plastic QFN (6mm x 6mm) (Reference LTC DWG # 05-08-1728 Rev O) 0.70 0.05 6.50 0.05 5.10 0.05 4.42 0.05 4.50 0.05 (4 SIDES) 4.42 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 0.10 (4 SIDES) 0.75 0.05 R = 0.10 TYP R = 0.115 TYP 39 40 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 4.50 REF (4-SIDES) 4.42 0.10 2 PIN 1 NOTCH R = 0.45 OR 0.35 45 CHAMFER 4.42 0.10 (UJ40) QFN REV O 0406 0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD 21521012f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC2152-12/ LTC2151-12/LTC2150-12 Typical Application LTC2152-12: 32K Point 2-Tone FFT, fIN = 71MHz and 69MHz, 250Msps VDD OVDD CLOCK S/H 12-BIT PIPELINED ADC CORRECTION LOGIC OUTPUT DRIVERS D10_11 * * * D0_1 OGND CLOCK/DUTY CYCLE CONTROL 21521012 TA03a GND -20 DDR LVDS AMPLITUDE (dBFS) ANALOG INPUT 0 -40 -60 -80 -100 -120 0 20 40 60 80 100 FREQUENCY (MHz) 120 21521012 TA03b Related Parts PART NUMBER DESCRIPTION COMMENTS LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 77.7dB SNR, 100dB SFDR, 64-Lead QFN Package LTC2157-14/LTC2156-14/ LTC2155-14 14-Bit, 250Msps/210Msps/170Msps, 1.8V Dual ADC, DDR LVDS Outputs 650mW/616mW/567mW, 70dB SNR, 90dB SFDR, 64-Lead QFN Package LTC2152-14/LTC2151-14/ LTC2150-14 14-Bit, 250Msps/210Msps/170Msps, 1.8V Dual ADC, DDR LVDS Outputs 356mW/338mW/313mW, 70dB SNR, 90dB SFDR, 40-Lead QFN Package LTC2262-14 14-Bit, 150Msps 1.8V ADC, Ultralow Power 149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 40-Lead QFN Package LT(R)5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator LT5527 400MHz to 3.7GHz High Linearity Downconverting Mixer 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports LT5575 800MHz to 2.7GHz Direct Conversion Quadrature Demodulator High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF and LO Transformer LTC6409 10GHz GBW, 1.1nV/Hz Differential Amplifier/ ADC Driver 88dB SFDR at 100MHz, Input Range Includes Ground 52mA Supply Current, 3mm x 2mm QFN Package LTC6412 800MHz, 31dB Range, Analog-Controlled Variable Gain Amplifier Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, 4mm x 4mm QFN-24 Package LTC6420-20 1.8GHz Dual Low Noise, Low Distortion Differential ADC Drivers for 300MHz IF Fixed Gain 10V/V, 1nV/Hz Total Input Noise, 80mA Supply Current per Amplifier, 3mm x 4mm QFN-20 Package LTM9002 14-Bit Dual Channel IF/Baseband Receiver Subsystem Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers LTM9003 12-Bit Digital Pre-Distortion Receiver Integrated 12-Bit ADC Down-Converter Mixer with 0.4GHz to 3.8GHz Input Frequency Range ADCs RF Mixers/Demodulators Amplifiers/Filters Receiver Subsystems 21521012f 28 Linear Technology Corporation LT1111 * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2011