DC1241B-BA - Linear Technology

LTM9001-Ax/LTM9001-Bx

9001fc

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

16-Bit IF/Baseband

Receiver Subsystem

The LTM

9001 is an integrated system in a package (SiP)

that includes a high-speed 16-bit A/D converter, matching

network, anti-aliasing ﬁ lter and a low noise, differential

ampliﬁ er with ﬁ xed gain. It is designed for digitizing wide

dynamic range signals with an intermediate frequency

(IF) range up to 300MHz. The ampliﬁ er allows either AC-

or DC-coupled input drive. A lowpass or bandpass ﬁ lter

network can be implemented with various bandwidths.

Contact Linear Technology regarding semi-custom

conﬁ gurations.

The LTM9001 is perfect for IF receivers in demanding

communications applications, with AC performance that

includes 72dBFS noise ﬂ oor and 82dB spurious free

dynamic range (SFDR) at 162.5MHz (LTM9001-AA).

The digital outputs can be either differential LVDS or single-

ended CMOS. There are two format options for the CMOS

outputs: a single bus running at the full data rate or two

demultiplexed buses running at half data rate. A separate

output power supply allows the CMOS output swing to

range from 0.5V to 3.3V.

The differential ENC+ and ENC– inputs may be driven with

a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional

clock duty cycle stabilizer allows high performance at full

speed with a wide range of clock duty cycles.

Simpliﬁ ed IF Receiver Channel

n Integrated 16-Bit, High-Speed ADC, Passive Filter

and Fixed Gain Differential Ampliﬁ er

n Up to 300MHz IF Range

Lowpass and Bandpass Filter Versions

n Low Noise, Low Distortion Ampliﬁ ers

Fixed Gain: 8dB, 14dB, 20dB or 26dB

50, 200 or 400 Input Impedance

n 75dB SNR, 83dB SFDR (LTM9001-AD)

n Integrated Bypass Capacitance, No External

Components Required

n Optional Internal Dither

n Optional Data Output Randomizer

n LVDS or CMOS Outputs

n 3.3V Single Supply

n Power Dissipation: 1.65W

n Clock Duty Cycle Stabilizer

n 11.25mm × 11.25mm × 2.32mm LGA Package

n Telecommunications

n High Sensitivity Receivers

n Cellular Base Stations

n Spectrum Analyzers

64k Point FFT, fIN = 162.4MHz,

–1dBFS, PGA = 1

9001 TA01

CLKOUT

VCC VDD = 3.3V

ENC+ENC–

ADC CONTROL PINS

DIFFERENTIAL

FIXED GAIN

AMPLIFIER

16-BIT

130Msps ADC

RF IN–

IN+

LTM9001

SENSE

GND

D15

•

0VDD = 0.5V TO 3.6V

OGND

CMOS

LVD S

SAW

ANTI-ALIAS

FILTER

AMPLITUDE (dBFS)

–80

–60

–40

–20

9001 TA01b

–100

–120

HD2HD3

FREQUENCY (MHz)

010 30 40

20 50 60

LTM9001-AA

L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks

and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

LTM9001-Ax/LTM9001-Bx

9001fc

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VCC) ................................ –0.3V to 3.6V

Supply Voltage (VDD) ................................... –0.3V to 4V

Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V

Analog Input Current (IN+, IN–) ............................±10mA

Digital Input Voltage

(Except AMPSHDN) ................. –0.3V to (VDD + 0.3V)

Digital Input Voltage

(AMPSHDN) ..............................–0.3V to (VCC + 0.3V)

Digital Output Voltage ................–0.3V to (OVDD + 0.3V)

Operating Temperature Range

LTM9001C................................................ 0°C to 70°C

LTM9001I .............................................–40°C to 85°C

Storage Temperature Range ...................–45°C to 125°C

Maximum Junction Temperature........................... 125°C

(Notes 1, 2)

ORDER INFORMATION

LEAD FREE FINISH PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTM9001CV-AA#PBF LTM9001V-AA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 0°C to 70°C

LTM9001IV-AA#PBF LTM9001V-AA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA –40°C to 85°C

LTM9001CV-AD#PBF LTM9001V-AD 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 0°C to 70°C

LTM9001IV-AD#PBF LTM9001V-AD 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA –40°C to 85°C

LTM9001CV-BA#PBF LTM9001V-BA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA 0°C to 70°C

LTM9001IV-BA#PBF LTM9001V-BA 81-Lead (11.25mm × 11.25mm × 2.3mm) LGA –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

GDIFF Gain DC, LTM9001-AA

fIN = 162.5MHz (Note 3)

l19.1 19.7

20.3 dB

DC, LTM9001-AD

fIN = 70MHz (Note 3)

l13.4 14

13.5

14.7 dB

DC, LTM9001-BA

fIN = 140MHz (Note 3)

l7.1 8.2

7.8

9.4 dB

GTEMP Gain Temperature Drift VIN = Maximum, (Note 3) 2 mdB/°C

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

IN–

234

LGA PACKAGE

TJMAX = 125°C, QJA = 15°C/W, QJCtop = 19°C/W

QJA DERIVED FROM 60mm s 70mm PCB WITH 4 LAYERS

WEIGHT = 0.71g

56789

DATA

TOP VIEWALL ELSE

= GND CONTROL

OGND

OVDD

VCC

DNC

VDD OGNDCONTROL OVDD

OGND

ENC+

IN+

ENC–

LTM9001-Ax/LTM9001-Bx

9001fc

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VINCM Input Common Mode Voltage Range (IN+ + IN–)/2 1.0–1.6 V

VIN Input Voltage Range at –1dBFS LTM9001-AA at 162.5MHz

LTM9001-AD at 70MHz

LTM9001-BA at 140MHz

233

424

820

mVP-P

RINDIFF Differential Input Impedance LTM9001-AA

LTM9001-AD

LTM9001-BA

200

400



CINDIFF Differential Input Capacitance Includes Parasitic 1 pF

VOS Offset Error (Note 6) Including Ampliﬁ er and ADC (LTM9001-AA)

Including Ampliﬁ er and ADC (LTM9001-AD)

Including Ampliﬁ er and ADC (LTM9001-BA)

–8

–11

–20

–3.2

–6

–10

–0.5

Offset Drift Including Ampliﬁ er and ADC ±10 µV/°C

Full-Scale Drift Internal Reference

External Reference

±30

±15

ppm/°C

CMRR Common Mode Rejection Ratio 60 dB

ISENSE SENSE Input Leakage Current 0V < SENSE < VDD l–3 3 µA

IMODE MODE Pin Pull-Down Current to GND 10 µA

ILVDS LVDS Pin Pull-Down Current to GND 10 µA

tAP Sample-and-Hold Acquisition Delay Time 1 ns

tJITTER Sample-and-Hold Acquisition Delay Time Jitter 70 fsRMS

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) l16 Bits

Integral Linearity Error Differential Input LTM9001-Ax (Notes 5, 7)

Differential Input LTM9001-BA (Notes 5, 7)

±2.4 ±8

±10

LSB

Differential Linearity Error Differential Input (Notes 5, 7) l±0.3 ±1 LSB

Transition Noise External Reference 1 LSBRMS

CONVERTER CHARACTERISTICS

The l indicates speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SNR Signal-to-Noise Ratio 162.5MHz Input (PGA = 0) LTM9001-AA

162.5MHz Input (PGA = 1) LTM9001-AA l67.2

68.5

dBFS

70MHz Input (PGA = 0) LTM9001-AD

70MHz Input (PGA = 1) LTM9001-AD

l71.2 75

dBFS

140MHz Input (PGA = 0) LTM9001-BA

140MHz Input (PGA = 1) LTM9001-BA

l67 69.2

67.2

dBFS

DYNAMIC ACCURACY

The l indicates speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS. (Note 4)

LTM9001-Ax/LTM9001-Bx

9001fc

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Encode Inputs (ENC+, ENC–)

VID Differential Input Voltage l0.2 V

VICM Common Mode Input Voltage Internally Set

Externally Set 1.2

1.6

3.1

RIN Input Resistance 100 

CIN Input Capacitance (Note 7) 3 pF

DIGITAL INPUTS AND OUTPUTS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

DYNAMIC ACCURACY

The l indicates speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SFDR Spurious Free Dynamic Range, 2nd or 3rd

Harmonic

162.5MHz Input (PGA = 0) LTM9001-AA

162.5MHz Input (PGA = 1) LTM9001-AA l72

dBc

70MHz Input (PGA = 0) LTM9001-AD

70MHz Input (PGA = 1) LTM9001-AD

l72.6 83

dBc

140MHz Input (PGA = 0) LTM9001-BA

140MHz Input (PGA = 1) LTM9001-BA

l64 72

dBc

SFDR Spurious Free Dynamic Range 4th or Higher 162.5MHz Input (PGA = 0) LTM9001-AA

162.5MHz Input (PGA = 1) LTM9001-AA l86

dBc

70MHz Input (PGA = 0) LTM9001-AD

70MHz Input (PGA = 1) LTM9001-AD

l84.5 95

dBc

140MHz Input (PGA = 0) LTM9001-BA

140MHz Input (PGA = 1) LTM9001-BA

l86 95

104

dBc

S/(N+D) Signal-to-Noise Plus Distortion Ratio 162.5MHz Input (PGA = 0) LTM9001-AA

162.5MHz Input (PGA = 1) LTM9001-AA l67

71.4

dBFS

70MHz Input (PGA = 0) LTM9001-AD

70MHz Input (PGA = 1) LTM9001-AD

l71.2 74.3

dBFS

140MHz Input (PGA = 0) LTM9001-BA

140MHz Input (PGA = 1) LTM9001-BA

l64 67.5

66.4

dBFS

SFDR Spurious Free Dynamic Range at –25dBFS,

Dither “OFF”

162.5MHz Input (PGA = 0) LTM9001-AA

162.5MHz Input (PGA = 1) LTM9001-AA

dBFS

Spurious Free Dynamic Range at –15dBFS,

Dither “OFF”

70MHz Input (PGA = 0) LTM9001-AD

70MHz Input (PGA = 1) LTM9001-AD

dBFS

Spurious Free Dynamic Range at –15dBFS,

Dither “OFF”

140MHz Input (PGA = 0) LTM9001-BA

140MHz Input (PGA = 1) LTM9001-BA

dBFS

SFDR Spurious Free Dynamic Range at –25dBFS,

Dither “ON”

162.5MHz Input (PGA = 0) LTM9001-AA

162.5MHz Input (PGA = 1) LTM9001-AA l90

100

dBFS

Spurious Free Dynamic Range at –15dBFS,

Dither “ON”

70MHz Input (PGA = 0) LTM9001-AD

70MHz Input (PGA = 1) LTM9001-AD

l90 92

dBFS

Spurious Free Dynamic Range at –15dBFS,

Dither “ON”

140MHz Input (PGA = 0) LTM9001-BA

140MHz Input (PGA = 1) LTM9001-BA

l90 95

dBFS

IMD3Third Order Intermodulation Distortion;

1MHz Tone Spacing, 2 Tones at –7dBFS

fIN = 162.5MHz LTM9001-AA

fIN = 70MHz LTM9001-AD

fIN = 140MHz LTM9001-BA

–78

–84

IIP3Equivalent Third Order Input Intercept Point,

2 Tone

fIN = 162.5MHz LTM9001-AA

fIN = 70MHz LTM9001-AD

fIN = 140MHz LTM9001-BA

26.5

29.2

dBm

LTM9001-Ax/LTM9001-Bx

9001fc

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

POWER REQUIREMENTS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VDD ADC Analog Supply Voltage (Note 8) l3.135 3.3 3.465 V

VCC Ampliﬁ er Supply Voltage 2.85 3.5 V

ICC Ampliﬁ er Supply Current l100 136 mA

PSHDN Total Shutdown Power AMPSHDN = ADCSHDN = 3.3V 10 mW

DIGITAL INPUTS AND OUTPUTS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Logic Inputs (DITH, PGA, ADCSHDN, RAND)

VIH High Level Input Voltage VDD = 3.3V l2V

VIL Low Level Input Voltage VDD = 3.3V l0.8 V

IIN Input Current VIN = 0V to VDD l±10 µA

CIN Input Capacitance (Note 7) 1.5 pF

Logic Inputs (AMPSHDN)

VIH High Level Input Voltage VCC = 3.3V l2V

VIL Low Level Input Voltage VCC = 3.3V l0.8 V

IIH Input High Current VIN = 2V 1.3 µA

IIL Input Low Current VIN = 0.8V 0.1 µA

CIN Input Capacitance (Note 7) 1.5 pF

Logic Outputs (CMOS Mode)

OVDD = 3.3V

VOH High Level Output Voltage VDD = 3.3V, IO = –10µA

VDD = 3.3V, IO = –200µA l3.1

3.299

3.29

VOL Low Level Output Voltage VDD = 3.3V, IO = 10µA

VDD = 3.3V, IO = 1.6mA l

0.01

0.1 0.4

ISOURCE Output Source Current VOUT = 0V –50 mA

ISINK Output Sink Current VOUT = 3.3V 50 mA

OVDD = 2.5V

VOH High Level Output Voltage VDD = 3.3V, IO = –200µA 2.49 V

VOL Low Level Output Voltage VDD = 3.3V, IO = 1.6mA 0.1 V

OVDD = 1.8V

VOH High Level Output Voltage VDD = 3.3V, IO = –200µA 1.79 V

VOL Low Level Output Voltage VDD = 3.3V, IO = 1.6µA 0.1 V

Logic Outputs (LVDS Mode)

Standard LVDS

VOD Differential Output Voltage 100 Differential Load l247 350 454 mV

VOS Output Common Mode Voltage 100 Differential Load l1.125 1.2 1.375 V

Low Power LVDS

VOD Differential Output Voltage 100 Differential Load l125 175 250 mV

VOS Output Common Mode Voltage 100 Differential Load l1.125 1.2 1.375 V

LTM9001-Ax/LTM9001-Bx

9001fc

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSSampling Frequency (Note 8) LTM9001-Ax

LTM9001-BA

130

160

MHz

tLENC Low Time (Note 7) Duty Cycle Stabilizer Off (LTM9001-Ax)

Duty Cycle Stabilizer Off (LTM9001-BA)

Duty Cycle Stabilizer On (LTM9001-Ax)

Duty Cycle Stabilizer On (LTM9001-BA)

3.65

2.97

2.6

2.1

3.846

3.125

3.846

3.125

1000

tHENC High Time (Note 7) Duty Cycle Stabilizer Off (LTM9001-Ax)

Duty Cycle Stabilizer Off (LTM9001-BA)

Duty Cycle Stabilizer On (LTM9001-Ax)

Duty Cycle Stabilizer On (LTM9001-BA)

3.65

2.97

2.6

2.1

3.846

3.125

3.846

3.125

1000

LVDS Output Mode (Standard and Low Power)

tDENC to DATA Delay (Note 7) l1.3 2.5 4 ns

tCENC to CLKOUT Delay (Note 7) l1.3 2.5 4 ns

tSKEW DATA to CLKOUT Skew (tC – tD) (Note 7) l–0.6 0 0.6 ns

tRISE Output Rise Time 0.5 ns

tFALL Output Fall Time 0.5 ns

Data Latency 7 Cycles

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

TIMING CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

POWER REQUIREMENTS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Standard LVDS Output Mode

OVDD Output Supply Voltage (Note 8) l3 3.3 3.6 V

IVDD Analog Supply Current LTM9001-Ax

LTM9001-BA

400

465

500

550

IOVDD Output Supply Current l74 90 mA

PDISS Power Dissipation LTM9001-Ax

LTM9001-BA

1564

1779

1947

2112

Low Power LVDS Output Mode

OVDD Output Supply Voltage (Note 8) l3 3.3 3.6 V

IVDD Analog Supply Current LTM9001-Ax

LTM9001-BA

400

465

500

550

IOVDD Output Supply Current l41 50 mA

PDISS Power Dissipation LTM9001-Ax

LTM9001-BA

1455

1670

1815

1980

CMOS Output Mode

OVDD Output Supply Voltage (Note 8) l0.5 3.6 V

IVDD Analog Supply Current LTM9001-Ax

LTM9001-BA

380

460

450

530

PDISS ADC Power Dissipation LTM9001-Ax

LTM9001-BA

1320

1584

1650

1914

PDISS(TOTAL) Total Power Dissipation LTM9001-Ax

LTM9001-BA

1650

1914

LTM9001-Ax/LTM9001-Bx

9001fc

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND

wired together (unless otherwise noted).

Note 3: Gain is measured from IN+/IN– through the ADC. The ampliﬁ er

gain is attenuated by the ﬁ lter, (See the typical performance characteristics

section for “IF Frequency Response”).

Note 4: VCC = VDD = 3.3V, fSAMPLE = maximum sample frequency, LVDS

outputs, differential ENC+/ENC– = 2VP-P with 1.6V common mode, input

range = –1dBFS with PGA = 0 with differential drive, AC-coupled inputs,

unless otherwise noted.

Note 5: Integral nonlinearity is deﬁ ned as the deviation of a code from

a “best ﬁ t straight line” to the transfer curve. The deviation is measured

from the center of the quantization band.

Note 6: Offset error is the voltage applied between the IN+ and IN– pins

required to make the output code ﬂ icker between 0000 0000 0000 0000

and 1111 1111 1111 1111.

Note 7: Guaranteed by design, not subject to test.

Note 8: Recommended operating conditions.

TIMING CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CMOS Output Mode

tDENC to DATA Delay (Note 7) l1.3 2.7 4 ns

tCENC to CLKOUT Delay (Note 7) l1.3 2.7 4 ns

tSKEW DATA to CLKOUT Skew (tC – tD) (Note 7) l–0.6 0 0.6 ns

Data Latency Full Rate CMOS

Demuxed

Cycles

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

LTM9001-Ax/LTM9001-Bx

9001fc

Full-Rate CMOS Output Mode Timing

All Outputs are Single-Ended and Have CMOS Levels

tAP

ANALOG

INPUT

N – 7 N – 6 N – 5 N – 4 N – 3

ENC–

ENC+

CLKOUTA

CLKOUTB

DA0-DA15, OFA

DB0-DB15, OFB

9001 TD02

HIGH IMPEDANCE

N + 1

N + 2

N + 4

N + 3

N – 7 N – 6 N – 5 N – 4 N – 3

ANALOG

INPUT

ENC–

ENC+

CLKOUT–

CLKOUT+

D0-D15, OF

9001 TD01

tAP N + 1

N + 2

N + 4

N + 3

LVDS Output Mode Timing

All Outputs are Differential and Have LVDS Levels

TIMING DIAGRAM

LTM9001-Ax/LTM9001-Bx

9001fc

TIMING DIAGRAM

Demultiplexed CMOS Output Mode Timing

All Outputs are Single-Ended and Have CMOS Levels

N – 8 N – 6 N – 4

N – 7 N – 5 N – 3

ENC–

ENC+

CLKOUTA

CLKOUTB

DA0-DA15, OFA

DB0-DB15, OFB

9001 TD03

tAP

ANALOG

INPUT

N + 1

N + 2

N + 4

N + 3

LTM9001-Ax/LTM9001-Bx

9001fc

TYPICAL PERFORMANCE CHARACTERISTICS

Best Fit Integral Non-Linearity

(INL) vs Output Code

Differential Non-Linearity (DNL)

vs Output Code

64k Point FFT, fIN = 162.4MHz,

–1dBFS, PGA = 0, RAND “Off”,

Dither “Off”

64k Point FFT, fIN = 162.4MHz,

–1dBFS, PGA = 1, RAND “Off”,

Dither “Off”

64k Point 2-Tone FFT, fIN = 161.5MHz,

and 163.5MHz, –7dBFS, PGA = 0,

RAND “Off”, Dither “Off”

IF Frequency ResponseInput Impedance vs Frequency

Shorted Inputs Histogram with

130k Samples

FREQUENCY (MHz)

120

FILTER GAIN (dB)

–4

–2

150 170 200

9001 G05

–6

–8

–10

130 140 160 180 190

FREQUENCY (MHz)

IMPEDANCE MAGNITUDE ()

IMPEDANCE PHASE (deg)

150

100

200

250 0

–45

–90

10010 1000

9001 G04

MAGNITUDE

PHASE

ADC OUTPUT CODE

33484

COUNT

5000

4000

3000

8000

7000

6000

9000

9001 G03

2000

1000

33504 33524 33544

ADC OUTPUT CODE

INL ERROR (LSB)

49152

9001 G02

–1

–2

–3

–4

–5

16384 32768 65536

ADC OUTPUT CODE

DNL ERROR (LSB)

0.1

0.3

0.4

0.2

0.5

49152

9001 G01

–0.1

–0.2

–0.3

–0.4

–0.5

16384 32768 65536

AMPLITUDE (dBFS)

–80

–60

–40

–20

9001 G06

–100

–120

HD3 HD2

FREQUENCY (MHz)

010 30 40

20 50 60

AMPLITUDE (dBFS)

–80

–60

–40

–20

9001 G07

–100

–120

HD2HD3

FREQUENCY (MHz)

010 30 40

20 50 60

AMPLITUDE (dBFS)

–80

–60

–40

–20

9001 G08

–100

–120

FREQUENCY (MHz)

010 30 40

20 50 60

(LTM9001-AA)

LTM9001-Ax/LTM9001-Bx

9001fc

64k Point 2-Tone FFT, fIN = 161.5MHz,

and 163.5MHz, –15dBFS, PGA = 0,

RAND “Off”, Dither “Off”

TYPICAL PERFORMANCE CHARACTERISTICS

64k Point FFT, fIN = 162.4MHz,

–15dBFS, PGA = 0, RAND “Off”,

Dither “Off”

64k Point FFT, fIN = 162.4MHz,

–15dBFS, PGA = 0, RAND “Off”,

Dither “On”

SFDR vs Input Level, fIN = 162.4MHz,

PGA = 0, RAND “Off”, Dither = “Off”

SFDR vs Input Level, fIN = 162.4MHz,

PGA = 0, RAND “Off”, Dither = “On”

SFDR and SNR vs Sample Rate,

fIN = 162.4MHz, –1dBFS, PGA = 0,

RAND “Off”, Dither “Off”

SFDR vs Input Common Mode Voltage,

fIN = 162.4MHz, –1dBFS, PGA = 0

SFDR vs VCC Supply Voltage,

fIN = 162.4MHz, –1dBFS,

PGA = 0

AMPLITUDE (dBFS)

–80

–60

–40

–20

9001 G09

–100

–120

FREQUENCY (MHz)

010 30 40

20 50 60

AMPLITUDE (dBFS)

–80

–60

–40

–20

9001 G10

–100

–120

FREQUENCY (MHz)

010 30 40

20 50 60

AMPLITUDE (dBFS)

–80

–60

–40

–20

9001 G11

–100

–120

FREQUENCY (MHz)

010 30 40

20 50 60

INPUT LEVEL (dBFS)

–90

SFDR (dBc AND dBFS)

100

120

140

–60 –40

9001 G12

–80 –70 –50 –30 –20 –10 0

SFDR dBc

SFDR dBFS

INPUT COMMON MODE VOLTAGE (V)

0.5

SFDR (dBc)

2.0 3.0

9001 G15

1.0 1.5 2.5

VCC SUPPLY VOLTAGE (V)

2.8

SFDR (dBc)

78.0

78.5

79.0

79.5

80.0

80.5

81.0

3.1 3.5

9001 G16

77.5

77.0

76.5

76.0

75.5

2.9 3.0 3.2 3.3 3.4

INPUT LEVEL (dBFS)

–90

SFDR (dBc AND dBFS)

100

120

140

–60 –40

9001 G13

–80 –70 –50 –30 –20 –10 0

SFDR dBc

SFDR dBFS

ADC SAMPLE RATE (Msps)

SFDR (dBc) AND SNR (dBFS)

150 250

9001 G14

50 100 200

SNR

SFDR

(LTM9001-AA)

LTM9001-Ax/LTM9001-Bx

9001fc

TYPICAL PERFORMANCE CHARACTERISTICS

(LTM9001-AD)

Input Impedance vs Frequency IF Frequency Response

64k Point FFT, fIN = 70MHz,

–1dBFS, PGA = 0, RAND “Off”,

Dither “Off”

64k Point 2-Tone FFT, fIN = 70MHz,

and ﬁ n = 74MHz, –7dBFS Per Tone,

PGA = 0, RAND “Off”, Dither “Off”

Differential Non-Linearity (DNL)

vs Output Code

Best Fit Integral Non-Linearity

(INL) vs Output Code SNR vs Frequency

OUTPUT CODE

DNL ERROR (LSB)

–0.2

0.0

0.2

0.4

0.6

0.8

1.0

49152 65536

9001 G25

–0.4

–0.6

–0.8

–1.0

16384 32768

OUTPUT CODE

INL ERROR (LSB)

–2.0

–1.5

–1.0

–0.5

0.0

2.0

1.0

1.5

0.5

2.5

3.0

3.5

4.0

49152 65536

9001 G26

–2.5

–3.0

–3.5

–4.0

16384 32768

FREQUENCY (MHz)

SNR (dB)

9001 G27

65 1 100 100010

FREQUENCY (MHz)

IMPEDANCE MAGNITUDE ()

9001 G28

220

140

160

100

120

180

200

IMPEDANCE PHASE (DEG)

–4

–6

–8

–2

–10

1 100 100010

MAGNITUDE

PHASE

FREQUENCY (MHz)

AMPLITUDE (dBFS)

9001 G29

–3

–7

–8

–9

–6

–5

–4

–2

–1

–1040 50 80 90 10060 70

FREQUENCY (MHz)

AMPLITUDE (dBFS)

9001 G30

–30

–70

–80

–90

–100

–110

–60

–50

–40

–20

–10

–120 0 10 40506020 30

HD2

HD3

FREQUENCY (MHz)

AMPLITUDE (dBFS)

9001 G31

–30

–70

–80

–90

–100

–110

–60

–50

–40

–20

–10

–120 010 40506020 30

LTM9001-Ax/LTM9001-Bx

9001fc

TYPICAL PERFORMANCE CHARACTERISTICS

(LTM9001-BA)

Input Impedance vs Frequency IF Frequency Response

64k Point FFT, fIN = 140MHz,

–1dBFS, PGA = 0, RAND “Off”,

Dither “Off”

64k Point FFT, fIN = 250MHz,

–1dBFS, PGA = 0, RAND “Off”,

Dither “Off”

64k Point 2-Tone FFT, fIN = 136MHz,

–7dBFS Per Tone, PGA = 0, RAND

“Off”, Dither “Off”

Differential Non-Linearity (DNL)

vs Output Code

Best Fit Integral Non-Linearity

(INL) vs Output Code SNR vs Frequency

OUTPUT CODE

DNL ERROR (LSB)

–0.2

0.0

0.2

0.4

0.6

0.8

1.0

49152 65536

9001 G17

–0.4

–0.6

–0.8

–1.0

16384 32768

OUTPUT CODE

INL ERROR (LSB)

–2.0

–1.5

–1.0

–0.5

0.0

2.0

1.0

1.5

0.5

2.5

3.0

3.5

4.0

49152 65536

9001 G18

–2.5

–3.0

–3.5

–4.0

16384 32768

FREQUENCY (MHz)

SNR (dB)

9001 G19

51 1 100 100010

FREQUENCY (MHz)

IMPEDANCE MAGNITUDE ()

IMPEDANCE PHASE (°C)

9001 G20

400

250

100

150

200

300

350

–24

–16

–8

–32

1 100 100010

MAGNITUDE

PHASE

FREQUENCY (MHz)

AMPLITUDE (dBFS)

9001 G21

–15

–25

–20

–10

–5

–30 1 100 100010

FREQUENCY (MHz)

AMPLITUDE (dBFS)

–60

–50

–40

–30

–20

–10

50 60

9001 G22

–70

–80

–90

–100

–110

–120

10 20 30 40

HD2

HD3

FREQUENCY (MHz)

AMPLITUDE (dBFS)

–60

–50

–40

–30

–20

–10

50 60 70 80

9001 G23

–70

–80

–90

–100

–110

–120

10 20 30 40

HD2

HD3

FREQUENCY (MHz)

AMPLITUDE (dBFS)

–60

–50

–40

–30

–20

–10

50 60

9001 G24

–70

–80

–90

–100

–110

–120

10 20 30 40

LTM9001-Ax/LTM9001-Bx

9001fc

Supply Pins

VCC (Pins E1, E2): 3.3V Analog Supply Pin for Ampliﬁ er.

The voltage on this pin provides power for the ampliﬁ er

stage only and is internally bypassed to GND.

VDD (Pins E5, D5): 3.3V Analog Supply Pin for ADC. This

supply is internally bypassed to GND.

OVDD (Pins A6, G9): Positive Supply for the ADC Output

Drivers. This supply is internally bypassed to OGND.

GND (Pins A1, A2, A4, B2, B4, C2, C4, D1, D2, D4, E4, F1,

F2, F4, G2, G4, H2, H4, J1, J2, J4): Analog Ground.

OGND (Pins A5, A9, G8, J9): ADC Output Driver Ground.

Analog Inputs

IN+ (Pin G1): Positive (Non-Inverting) Ampliﬁ er Input.

IN– (Pin H1): Negative (Inverting) Ampliﬁ er Input.

DNC (Pins C3, D3): Do Not Connect. These pins are used

for testing and should not be connected on the PCB. They

may be soldered to unconnected pads and should be well

isolated. The DNC pins connect to the signal path prior to

the ADC inputs; therefore, care should be taken to keep

other signals away from these sensitive nodes.

ENC+ (Pin C1): Positive Differential Encode Input. The

sampled analog input is held on the rising edge of ENC+.

This input is internally biased to 1.6V through a 6.2k

resistor. Output data can be latched on the rising edge

of ENC+. The Encode pins have a differential 100 input

impedance.

ENC– (Pin B1): Negative Differential Encode Input. The

sampled analog input is held on the falling edge of ENC–.

This input is internally biased to 1.6V through a 6.2k resistor.

Bypass to ground with a 0.1µF capacitor for a single-ended

encode signal. The encode pins have a differential 100

input impedance.

Control Inputs

SENSE (Pin J3): Reference Mode Select and External

Reference Input. Tie SENSE to VDD to select the internal

2.5V bandgap reference. An external reference of 2.5V

or 1.25V may be used; both reference values will set the

maximum full-scale input range.

AMPSHDN (Pin H3): Power Shutdown Pin for Ampliﬁ er.

This pin is a logic input referenced to analog ground.

AMPSHDN = low results in normal operation. AMPSHDN

= high results in powered down ampliﬁ er with typically

3mA ampliﬁ er supply current.

MODE (Pin G3): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to 0V selects

offset binary output format and disables the clock duty cycle

stabilizer. Connecting MODE to 1/3VDD selects offset binary

output format and enables the clock duty cycle stabilizer.

Connecting MODE to 2/3VDD selects 2’s complement

output format and enables the clock duty cycle stabilizer.

Connecting MODE to VDD selects 2’s complement output

format and disables the clock duty cycle stabilizer.

RAND (Pin F3): Digital Output Randomization Selection

Pin. RAND = low results in normal operation. RAND =

high selects D1 to D15 to be EXCLUSIVE-ORed with D0

(the LSB). The output can be decoded by again applying

an XOR operation between the LSB and all other bits. This

mode of operation reduces the effects of digital output

interference.

PGA (Pin E3): Programmable Gain Ampliﬁ er Control Pin.

PGA = low selects the normal (maximum) input voltage

range. PGA = high selects a 3.5dB reduced input range

for slightly better distortion performance at the expense

of SNR.

ADCSHDN (Pin B3): Power Shutdown Pin for ADC.

ADCSHDN = low results in normal operation. ADCSHDN

= high results in powered down analog circuitry and the

digital outputs are placed in a high impedance state.

DITH (Pin A3): Internal Dither Enable Pin. DITH = low

disables internal dither. DITH = high enables internal

dither. Refer to Internal Dither section of this data sheet

for details on dither operation.

LVDS (Pin F5): Data Output Mode Select Pin. Connecting

LVDS to 0V selects full rate CMOS mode. Connecting LVDS

to 1/3VDD selects demultiplexed CMOS mode. Connecting

LVDS to 2/3VDD selects low power LVDS mode. Connecting

LVDS to VDD selects standard LVDS mode.

PIN FUNCTIONS

LTM9001-Ax/LTM9001-Bx

9001fc

Top View of LGA Pinout (Looking Through Component)

9001 LGA01

IN–

23456789

DATA

TOP VIEWALL ELSE

= GND CONTROL

OGND

OVDD

VCC

DNC

VDD OGNDCONTROL OVDD

OGND

ENC+

IN+

ENC–

PIN FUNCTIONS

Digital Outputs

For CMOS Mode, Full Rate or Demultiplexed

DA0 to DA15 (Pins E9 to H5): Digital Outputs, A Bus.

DA15 is the MSB. Output bus for full rate CMOS mode

and demultiplexed mode.

CLKOUTA (Pin E8): Inverted Data Valid Output. CLKOUTA

will toggle at the sample rate in full rate CMOS mode or

at 1/2 the sample rate in demultiplexed mode. Latch the

data on the rising edge of CLKOUTA.

OFB (Pin E6): Overﬂ ow/Underﬂ ow Digital Output for the

B Bus. OFB is high when an overﬂ ow or underﬂ ow has

occurred on the B bus. OFB is in a high impedance state

in full rate CMOS mode.

DB0 to DB15 (Pins B5 to D9): Digital Outputs, B Bus. DB15

is the MSB. Active in demultiplexed mode. The B bus is in

a high impedance state in full rate CMOS mode.

CLKOUTB (Pin E7): Data Valid Output. CLKOUTB will toggle

at the sample rate in full rate CMOS mode or at 1/2 the

sample rate in demultiplexed mode. Latch the data on the

falling edge of CLKOUTB.

OFA (Pin G5): Overﬂ ow/Underﬂ ow Digital Output for the

A Bus. OFA is high when an overﬂ ow or underﬂ ow has

occurred on the A bus.

For LVDS Mode, Standard or Low Power

D0–/D0+ to D15–/D15+ (Pins B5 to G6): LVDS Digital Out-

puts. All LVDS outputs require differential 100 termination

resistors at the LVDS receiver. D15+/D15– is the MSB.

CLKOUT–/CLKOUT+ (Pins E6, E7): LVDS Data Valid Output.

Latch data on the rising edge of CLKOUT+, falling edge

of CLKOUT–.

OF–/OF+ (Pins H5, G5): Overﬂ ow/Underﬂ ow Digital Output.

OF is high when an over or under ﬂ ow has occurred.

Pin Conﬁ guration (LVDS Outputs/CMOS Outputs)

123456 7 8 9

J GND GND SENSE GND D14+/DA12 D14–/DA11 D12+/DA8 D12–/DA7 OGND

HIN

–GND AMPSHDN GND OF–/DA15 D15–/DA13 D13–/DA9 D11–/DA5 D11+/DA6

GIN

+GND MODE GND OF+/OFA D15+/DA14 D13+/DA10 OGND OVDD

F GND GND RAND GND LVDS D9–/DA1 D9+/DA2 D10–/DA3 D10+/DA4

CC VCC PGA GND VDD CLKOUT–/OFB CLKOUT+/CLKOUTB D8–/CLKOUTA D8+/DA0

D GND GND DNC GND VDD D6–/DB12 D6+/DB13 D7–/DB14 D7+/DB15

CENC

+GND DNC GND D0+/DB1 D4–/DB8 D4+/DB9 D5–/DB10 D5+/DB11

BENC

–GND ADCSHDN GND D0–/DB0 D1–/DB2 D1+/DB3 D3+/DB7 D3–/DB6

A GND GND DITH GND OGND OVDD D2–/DB4 D2+/DB5 OGND

LTM9001-Ax/LTM9001-Bx

9001fc

FUNCTIONAL BLOCK DIAGRAM

9001 BD

CLKOUT+

CLKOUT–

VDD

OVDD

ENC+ADC-

SHDN

RAND MODE LVDS DITH OGND

ENC–

INPUT

AMPLIFIER

PGA

ADC

REFERENCE

INPUT

S/H

CONTROL

LOGIC

OUTPUT

DRIVERS

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK DRIVER

INTERNAL

CLOCK SIGNALS

IN+

IN–

SENSE

AMPSHDN

VCC

D15± … D0±

OF+

OF–

ANTI-ALIAS

FILTER

FIRST

PIPELINED

ADC STAGE

VOLTAGE

REFERENCE

DITHER

SIGNAL

GENERATOR

SHIFT REGISTER AND ERROR CORRECTION

SECOND

PIPELINED

ADC STAGE

THIRD

PIPELINED

ADC STAGE

FOURTH

PIPELINED

ADC STAGE

FIFTH

PIPELINED

ADC STAGE

PGA GND

RANGE

SELECT

100

LTM9001-Ax/LTM9001-Bx

9001fc

OPERATION

DYNAMIC PERFORMANCE DEFINITIONS

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N+D)] is the

ratio between the RMS amplitude of the fundamental input

frequency and the RMS amplitude of all other frequency

components at the ADC output.

Signal-to-Noise Ratio

The signal-to-noise (SNR) is the ratio between the RMS

amplitude of the fundamental input frequency and the RMS

amplitude of all other frequency components, except the

ﬁ rst ﬁ ve harmonics.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD

is expressed as:

THD =–20Log (V22+V32+V42+...Vn2)/V1

⎛

⎝⎞

⎠

where V1 is the RMS amplitude of the fundamental

frequency and V2 through Vn are the amplitudes of the

second through nth harmonics.

Intermodulation Distortion

If the input signal consists of more than one spectral

component, the transfer function nonlinearity can produce

intermodulation distortion (IMD) in addition to THD. IMD is

the change in one sinusoidal input caused by the presence

of another sinusoidal input at a different frequency.

If two pure sine waves of frequencies fa and fb are applied

to the input, nonlinearities in the transfer function can create

distortion products at the sum and difference frequencies

of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.

For example, the 3rd order IMD terms include (2fa + fb),

(fa + 2fb), (2fa – fb) and (fa – 2fb). The 3rd order IMD is

deﬁ ned as the ration of the RMS value of either input tone

to the RMS value of the largest 3rd order IMD product.

Spurious Free Dynamic Range (SFDR)

The ratio of the RMS input signal amplitude to the RMS

value of the peak spurious spectral component expressed

in dBc. SFDR may also be calculated relative to full-scale

and expressed in dBFS.

Aperture Delay Time

Aperture delay is the time from when a rising ENC+ equals

the ENC– voltage to the instant that the input signal is held

by the sample and-hold circuit.

Aperture Delay Jitter

The variation in the aperture delay time from conversion

to conversion. This random variation will result in noise

when sampling an AC input. The signal to noise ratio due

to the jitter alone will be:

SNRJITTER = –20log (2π • fIN • tJITTER)

DESCRIPTION

The LTM9001 is an integrated system in a package (SiP)

µModule

receiver that includes a high-speed, sampling

16-bit A/D converter, matching network, anti-aliasing ﬁ lter

and a low noise, differential ampliﬁ er with ﬁ xed gain. It

is designed for digitizing high frequency, wide dynamic

range signals with an intermediate frequency (IF) range

up to 300MHz.

LTM9001-Ax/LTM9001-Bx

9001fc

Figure 1. Basic Functional Elements

9001 F01

AMPLIFIER ADC

ADC

INPUT

NETWORK

OPERATION

The following sections describe in further detail the func-

tional operation of the LTM9001. The SiP technology allows

the LTM9001 to be customized and this is described in

the ﬁ rst section. The remaining outline follows the basic

functional elements as shown in Figure 1.

Technology has in place a program to deliver other speed,

resolution, IF range, gain and ﬁ lter conﬁ gurations for a

wide range of applications. See Table 1 for the LTM9001-AA

conﬁ guration and potential options. These semi-custom

designs are based on existing ADCs and ampliﬁ ers with

an appropriately modiﬁ ed matching network. The ﬁ nal

subsystem is then tested to the exact parameters deﬁ ned

for the application. The ﬁ nal result is a fully integrated,

accurately tested and reliable solution. For more details

on the semi-custom receiver subsystem program, contact

Linear Technology.

Note that not all combinations of options in Table 1 are

possible at this time and speciﬁ ed performance may differ

signiﬁ cantly from existing values. This data sheet discusses

devices with LVDS and CMOS outputs. The lower speed

options that only support CMOS outputs are available on

a separate data sheet. The CMOS-only options have a

different pin assignment.

AMPLIFIER INFORMATION

The ampliﬁ ers used in the LTM9001 are low noise and low

distortion fully differential ADC drivers. The ampliﬁ ers are

very ﬂ exible in terms of I/O coupling. They can be AC- or

DC-coupled at the inputs. Users are advised to keep the

input common mode voltage between 1V and 1.6V for

proper operation. If the inputs are AC-coupled, the input

common mode voltage is automatically biased. The input

signal can be either single-ended or differential with almost

no difference in distortion performance.

Table 1. Semi-Custom Options

AMPLIFIER IF

RANGE

AMPLIFIER INPUT

IMPEDANCE AMPLIFIER GAIN FILTER

ADC SAMPLE

RATE

ADC

RESOLUTION OUTPUT PART NUMBER

300MHz 200 20dB 162.5MHz BPF, 50MHz BW 130Msps 16-bit LVDS/CMOS LTM9001-AA

300MHz 200 14dB 70MHz BPF, 25MHz BW 130Msps 16-bit LVDS/CMOS LTM9001-AD

300MHz 400 8dB DC-300MHz LPF 160Msps 16-bit LVDS/CMOS LTM9001-BA

Select Combination of Options from Columns Below

DC-300MHz 50 26dB LPF TBD 160Msps 16-bit LVDS/CMOS

DC-140MHz 200 20dB BPF TBD 130Msps 14-bit LVDS/CMOS

DC-70MHz 200 14dB 105Msps CMOS

DC-35MHz 400 8dB 80Msps CMOS

200 6dB 65Msps CMOS

40Msps CMOS

25Msps CMOS

10Msps CMOS

SEMI-CUSTOM OPTIONS

The µModule construction affords a new level of ﬂ exibility in

application-speciﬁ c standard products. Standard ADC and

ampliﬁ er components can be integrated regardless of their

process technology and matched with passive components

to a particular application. The LTM9001-AA, as the ﬁ rst

example, is conﬁ gured with a 16-bit ADC sampling at rates

up to 130Msps. The ampliﬁ er gain is 20dB with an input

impedance of 200 and an input range of 233mVP-P. The

matching network is designed to optimize the interface

between the ampliﬁ er output and the ADC under these

conditions. Additionally, there is a 2-pole bandpass ﬁ lter

designed for 162.5MHz ±25MHz.

However, other options are possible through Linear Tech-

nology’s semi-custom development program. Linear

LTM9001-Ax/LTM9001-Bx

9001fc

INPUT SPAN

The LTM9001 is conﬁ gured with a ﬁ xed input span and

input impedance. With the ampliﬁ er gain and the ADC

input network described above for LTM9001-AA, the full-

scale input range of the driver circuit is 233mVP-P. The

recommended ADC input span is achieved by tying the

SENSE pin to VDD. However, the ADC input span can be

changed by applying a DC voltage to the SENSE pin.

Input Impedance and Matching

The differential input impedance of the LTM9001 can be

50, 200 or 400. In some applications the differential

inputs may need to be terminated to a lower value imped-

ance, e.g. 50, in order to provide an impedance match

for the source. Several choices are available.

One approach is to use a differential shunt resistor

(Figure 2). Another approach is to employ a wide band

transformer (Figure 3). Both methods provide a wide band

match. The termination resistor or the transformer must

be placed close to the input pins in order to minimize the

reﬂ ection due to input mismatch.

Table 2. Differential Ampliﬁ er Input Termination Values

ZIN RT FIG 2

400Ω 57Ω

200Ω 66.5Ω

50Ω None

9001 F02

ZIN/2

LTM9001

ZIN/2

25

VIN

IN+

IN–

–

9001 F03

ZIN/2 RF

LTM9001

ZIN/2

25

VIN

–

••

IN+

IN–

Figure 2. Input Termination for Differential 50Ω Input Impedance

Using Shunt Resistor (See Table 2 for RT Values)

Figure 3. Input Termination for Differential 50Ω

Input Impedance Using a Wideband Transformer

OPERATION

ADC INPUT NETWORK

The passive network between the ampliﬁ er output stage

and the ADC input stage can be conﬁ gured for bandpass

or lowpass response with different cutoff frequencies and

bandwidths. The LTM9001-AA, for example, implements

a 2-pole bandpass ﬁ lter centered at 162.5MHz with

50MHz bandwidth. Note that the ﬁ lter attenuates the

signal at 162.5MHz by 1dB, making the overall gain of

the subsystem 19dB.

For production test purposes the ﬁ lter is designed to allow

DC inputs into the ADC.

CONVERTER INFORMATION

The analog-to-digital converter (ADC) is a CMOS pipelined

multistep converter with a front-end PGA. As shown in the

Functional Block Diagram, the converter has ﬁ ve pipelined

ADC stages; a sampled analog input will result in a digitized

value seven cycles later (see the Timing Diagram section).

The encode input is differential for improved common

mode noise immunity.

APPLICATIONS INFORMATION

LTM9001-Ax/LTM9001-Bx

9001fc

APPLICATIONS INFORMATION

9001 F04

ZIN/2

0.1µF

0.1µF RF

LTM9001

ZIN/2

50

RS/RT

VIN

–

0.1µF

IN+

IN–

Figure 4. Input Termination for Differential

50Ω Input Impedance Using Shunt Resistor

Alternatively, one could apply a narrowband impedance match

at the inputs for frequency selection and/or noise reduction.

Referring to Figure 4, ampliﬁ er inputs can be easily

conﬁ gured for single-ended input without a balun. The

signal is fed to one of the inputs through a matching

network while the other input is connected to the same

impedance. In general, the single-ended input impedance

and termination resistor RT are determined by the

combination of RS, ZIN/2 and RF.

Table 3. Single-Ended Ampliﬁ er Input Termination Values

ZIN RT FIG 4

400Ω 59Ω

200Ω 68.5Ω

50Ω 150Ω

The LTM9001 ampliﬁ er is stable with all source impedances.

The overall differential gain is affected by the source

impedance in Figure 5:

V = | VOUT/VIN | = (1000/(RS + ZIN/2))

The noise performance of the ampliﬁ er also depends upon

the source impedance and termination. For example, an

input 1:4 transformer in Figure 3 improves the input noise

ﬁ gure by adding 6dB voltage gain at the inputs.

Reference and SENSE Pin Operation

Figure 6 shows the converter reference circuitry consisting

of a 2.5V bandgap reference, a programmable gain ampliﬁ er

and control circuit. There are three modes of reference

operation: internal reference, 1.25V external reference

or 2.5V external reference. To use the internal reference,

Figure 5. Calculate Differential Gain

9001 F05

ZIN/2

LTM9001

ZIN/2

Rs/2

VIN

IN+

IN–

–

Figure 6. Reference Circuit

PGA

SENSE

INTERNAL

ADC

REFERENCE

RANGE

SELECT

AND GAIN

CONTROL

2.5V

BANDGAP

REFERENCE

TIE TO VDD TO USE

INTERNAL 2.5V

REFERENCE

OR INPUT FOR

EXTERNAL 2.5V

REFERENCE

OR INPUT FOR

EXTERNAL 1.25V

REFERENCE

9001 F06

tie the SENSE pin to VDD. To use an external reference,

simply apply either a 1.25V or 2.5V reference voltage to the

SENSE input pin. Both 1.25V and 2.5V applied to SENSE

will result in the maximum full-scale range.

LTM9001-Ax/LTM9001-Bx

9001fc

APPLICATIONS INFORMATION

PGA Pin

The PGA pin selects between two gain settings for the

ADC front-end. PGA = low selects the maximum input

span; PGA = high selects a 3.5dB lower input span. The

high input range has the best SNR. For applications with

high linearity requirements, the low input range will have

improved distortion; however, the SNR will be 1.8dB worse.

See the Typical Performance Characteristics section.

Driving the Encode Inputs

The noise performance of the converter can depend on

the encode signal quality as much as the analog input.

The encode inputs are intended to be driven differentially,

primarily for noise immunity from common mode noise

sources. Each input is biased through a 6k resistor to a

1.6V bias. The bias resistors set the DC operating point

for transformer coupled drive circuits and can set the logic

threshold for single-ended drive circuits.

Any noise present on the encode signal will result in ad-

ditional aperture jitter that will be RMS summed with the

inherent ADC aperture jitter. In applications where jitter

is critical (high input frequencies), take the following into

consideration:

1. Differential drive should be used.

2. Use the largest amplitude possible. If using transformer

coupling, use a higher turns ratio to increase the am-

plitude.

3. If the ADC is clocked with a ﬁ xed frequency sinusoidal

signal, ﬁ lter the encode signal to reduce wideband

noise.

4. Balance the capacitance and series resistance at both

encode inputs such that any coupled noise will appear

at both inputs as common mode noise.

The encode inputs have a common mode range of 1.2V

to VDD. Each input may be driven from ground to VDD for

single-ended drive.

The encode clock inputs have a differential 100 input

impedance. For 50 inputs e.g. signal generators, an

additional 100 impedance will provide an impedance

match, as shown in Figure 7b.

Maximum and Minimum Encode Rates

The maximum encode rate for the LTM9001-Ax is 130Msps

and 160Msps for LTM9001-BA. For the ADC to operate

properly the encode signal should have a 50% (±5%)

duty cycle. Each half cycle must have at least 3.65ns

(LTM9001-Ax, or 2.97ns for LTM9001-BA) for the ADC

internal circuitry to have enough settling time for proper

operation. Achieving a precise 50% duty cycle is easy with

differential sinusoidal drive using a transformer or using

symmetric differential logic such as PECL or LVDS. When

using a single-ended encode signal asymmetric rise and fall

times can result in duty cycles that are far from 50%.

VDD

LTM9001

9001 F07a

VDD

ENC–

ENC+

100

1.6V

TO INTERNAL

ADC CLOCK

DRIVERS

50

8.2pF

0.1µF

T1 = M/A-COM ETC1-1-13

50

LTM9001

9001 F07b

ENC–

ENC+

100

•

Figure 7a. Equivalent Encode Input Circuit Figure 7b. Transformer Driven Encode

LTM9001-Ax/LTM9001-Bx

9001fc

APPLICATIONS INFORMATION

An optional clock duty cycle stabilizer can be used if the

input clock does not have a 50% duty cycle. This circuit

uses the rising edge of ENC to sample the analog input.

The falling edge of ENC is ignored and an internal falling

edge is generated by a phase-locked loop. The input clock

duty cycle can vary from 30% to 70% and the clock duty

cycle stabilizer will maintain a constant 50% internal duty

cycle. If the clock is turned off for a long period of time,

the duty cycle stabilizer circuit will require one hundred

clock cycles for the PLL to lock onto the input clock. To

use the clock duty cycle stabilizer, the MODE pin must be

connected to 1/3VDD or 2/3VDD using external resistors.

The lower limit of the sample rate is determined by the

droop of the sample and hold circuits. The pipelined ar-

chitecture of this ADC relies on storing analog signals on

small valued capacitors. Junction leakage will discharge

the capacitors. The speciﬁ ed minimum operating frequency

for the LTM9001 is 1Msps.

DIGITAL OUTPUTS

Digital Output Modes

The LTM9001 can operate in four digital output modes:

standard LVDS, low power LVDS, full rate CMOS, and

demultiplexed CMOS. The LVDS pin selects the mode of

operation. This pin has a four level logic input, centered at

0, 1/3VDD, 2/3VDD and VDD. An external resistive divider

can be used to set the 1/3VDD and 2/3VDD logic levels.

Table 4 shows the logic states for the LVDS pin.

Table 4. LVDS Pin Function

LVDS DIGITAL OUTPUT MODE

0V(GND) Full-Rate CMOS

1/3VDD Demultiplexed CMOS

2/3VDD Low Power LVDS

VDD LVD S

Digital Output Buffers (CMOS Modes)

Figure 10 shows an equivalent circuit for a single output

buffer in CMOS mode, full-rate or demultiplexed. Each

buffer is powered by OVDD and OGND, isolated from the

ADC power and ground. The additional N-channel transistor

in the output driver allows operation down to low voltages.

The internal resistor in series with the output makes the

output appear as 50 to external circuitry and eliminates

the need for external damping resistors.

9001F8

ENC–

1.6V

VTHRESHOLD = 1.6V ENC+

0.1µF

LTM9001

Figure 8. Single-Ended ENC Drive,

Not Recommended for Low Jitter

Figure 9. ENC Drive Using a CMOS to PECL Translator

9001 F09

ENC–

ENC+

3.3V

165 165

261 261

MC100LVELT22 LTM9001

100

9001 F10

OVDD

VDD VDD

TYPICAL

DATA

OUTPUT

OGND

43

OVDD 0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

LTM9001

Figure 10. Equivalent Circuit for a Digital Output Buffer

LTM9001-Ax/LTM9001-Bx

9001fc

APPLICATIONS INFORMATION

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTM9001 should drive a minimum

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as an ALVCH16373

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF. A resistor in series with the

output may be used but is not required since the ADC has

a series resistor of 43 on chip.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

Digital Output Buffers (LVDS Modes)

Figure 11 shows an equivalent circuit for an LVDS output

pair. A 3.5mA current is steered from OUT+ to OUT– or vice

versa, which creates a ±350mV differential voltage across

the 100 termination resistor at the LVDS receiver.

A feedback loop regulates the common mode output volt-

age to 1.2V. For proper operation each LVDS output pair

must be terminated with an external 100 termination

resistor, even if the signal is not used (such as OF+/OF– or

CLKOUT+/CLKOUT–). To minimize noise the PC board

traces for each LVDS output pair should be routed close

together. To minimize clock skew all LVDS PC board traces

should have about the same length.

In low power LVDS mode 1.75mA is steered between

the differential outputs, resulting in ±175mV at the LVDS

receiver’s 100 termination resistor. The output common

mode voltage is 1.2V, the same as standard LVDS mode.

Data Format

The LTM9001 parallel digital output can be selected for

offset binary or 2’s complement format. The format is

selected with the MODE pin. This pin has a four level

logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An

external resistive divider can be used to set the 1/3VDD

and 2/3VDD logic levels. Table 5 shows the logic states

for the MODE pin.

Table 5. MODE Pin Function

MODE OUTPUT FORMAT CLOCK DUTY CYCLE STABILIZER

0V(GND) Offset Binary Off

1/3VDD Offset Binary On

2/3VDD 2’s Complement On

VDD 2’s Complement Off

Overﬂ ow Bit

An overﬂ ow output bit (OF) indicates when the converter is

overranged or underranged. In CMOS mode, a logic high on

the OFA pin indicates an overﬂ ow or underﬂ ow on the A data

bus, while a logic high on the OFB pin indicates an overﬂ ow

on the B data bus. In LVDS mode, a differential logic high

on OF+/OF– pins indicates an overﬂ ow or underﬂ ow.

Figure 11. Equivalent Output Buffer in LVDS Mode

9001 F11

3.5mA

1.20V

LVDS

RECEIVER

OGND

10k 10k

VDD

OVDD

3.3V

PREDRIVER

LOGIC

DATA

FROM

LATCH

–

OVDD

43

100

LTM9001

LTM9001-Ax/LTM9001-Bx

9001fc

APPLICATIONS INFORMATION

Output Clock

The ADC has a delayed version of the encode input available

as a digital output, CLKOUT. The CLKOUT pin can be used

to synchronize the converter data to the digital system.

This is necessary when using a sinusoidal encode.

In both CMOS modes, A bus data will be updated as CLK-

OUTA falls and CLKOUTB rises. In demultiplexed CMOS

mode the B bus data will be updated as CLKOUTA falls

and CLKOUTB rises.

In full rate CMOS mode, only the A data bus is active;

data may be latched on the rising edge of CLKOUTA or

the falling edge of CLKOUTB.

In demultiplexed CMOS mode CLKOUTA and CLKOUTB

will toggle at 1/2 the frequency of the encode signal. Both

the A bus and the B bus may be latched on the rising edge

of CLKOUTA or the falling edge of CLKOUTB.

Digital Output Randomizer

Interference from the ADC digital outputs is sometimes

unavoidable. Interference from the digital outputs may

be from capacitive or inductive coupling or coupling

through the ground plane. Even a tiny coupling factor can

result in discernible unwanted tones in the ADC output

spectrum.

By randomizing the digital output before it is transmitted

off chip, these unwanted tones can be randomized, trading

a slight increase in the noise ﬂ oor for a large reduction in

unwanted tone amplitude.

The digital output is “randomized” by applying an exclusive-

OR logic operation between the LSB and all other data

output bits. To decode, the reverse operation is applied;

that is, an exclusive-OR operation is applied between the

LSB and all other bits. The LSB, OF and CLKOUT output

are not affected. The output randomizer function is active

when the RAND pin is high.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

to the same power supply as for the logic being driven. For

Figure 12. Functional Equivalent of Digital Output Randomizer

Figure 13. Derandomizing a Randomized Digital Output

•

CLKOUT

D15/D0

D14/D0

D2/D0

D1/D0

D0D0

RAND = HIGH,

RANDOMIZER

ENABLED

D14

D15

CLKOUT

RAND

9001 F12

LTM9001

•

D14

D15

PC BOARD

FPGA

CLKOUT

D15 ⊕ D0

D14 ⊕ D0

D2 ⊕ D0

D1 ⊕ D0

9001 F13

LTM9001

LTM9001-Ax/LTM9001-Bx

9001fc

example, if the converter is driving a DSP powered by a

1.8V supply, then OVDD should be tied to that same 1.8V

supply. OVDD can be powered with any logic voltage up

to the 3.6V. OGND can be powered with any voltage from

ground up to 1V and must be less than OVDD. The logic

outputs will swing between OGND and OVDD.

Internal Dither

The LTM9001 is a 16-bit receiver subsystem with a very

linear transfer function; however, at low input levels even

slight imperfections in the transfer function will result in

unwanted tones. Small errors in the transfer function are

usually a result of ADC element mismatches. An optional

internal dither mode can be enabled to randomize the input

location on the ADC transfer curve, resulting in improved

SFDR for low signal levels.

As shown in Figure 14, the output of the sample-and-hold

ampliﬁ er is summed with the output of a dither DAC. The

dither DAC is driven by a long sequence pseudo-random

number generator; the random number fed to the dither

DAC is also subtracted from the ADC result. If the dither

DAC is precisely calibrated to the ADC, very little of the

dither signal will be seen at the output. The dither signal

that does leak through will appear as white noise. The dither

APPLICATIONS INFORMATION

Figure 14. Functional Equivalent Block Diagram of Internal Dither Circuit

IN –

IN +

S/H

AMP

DIGITAL

SUMMATION OUTPUT

DRIVERS

MULTIBIT DEEP

PSEUDO-RANDOM

NUMBER

GENERATOR

16-BIT

PIPELINED

ADC CORE

PRECISION

DAC

CLOCK/DUTY

CYCLE

CONTROL

CLKOUT

D15

•

ENC+

DITHER ENABLE

HIGH = DITHER ON

LOW = DITHER OFF

DITH

ENC–

9001 F14

LTM9001

DAC will cause a small elevation in the noise ﬂ oor of the

ADC, as compared to the noise ﬂ oor with dither off.

For best noise performance with the dither signal on, the

driving impedance connected across pins IN+/IN– should

closely match that of the module (see Table 1). A source

impedance that is resistive and matches that of the module

within 10% will give the best results.

Supply Sequencing

The VCC pin provides the supply to the ampliﬁ er and the VDD

pin provides the supply to the ADC. The ampliﬁ er and the

ADC are separate integrated circuits within the LTM9001;

however, there are no supply sequencing considerations

beyond standard practice. It is recommended that the

ampliﬁ er and ADC both use the same low noise, 3.3V

supply, but the ampliﬁ er may be operated from a lower

voltage level if desired. Both devices can operate from the

same 3.3V linear regulator but place a ferrite bead between

the VCC and VDD pins. Separate linear regulators can be

used without additional supply sequencing circuitry if they

have common input supplies.

LTM9001-Ax/LTM9001-Bx

9001fc

APPLICATIONS INFORMATION

Grounding and Bypassing

The LTM9001 requires a printed circuit board with a

clean unbroken ground plane; a multilayer board with an

internal ground plane is recommended. The pinout of the

LTM9001 has been optimized for a ﬂ ow-through layout

so that the interaction between inputs and digital outputs

is minimized. A continuous row of ground pads facilitate

a layout that ensures that digital and analog signal lines

are separated as much as possible.

The LTM9001 is internally bypassed with the ampliﬁ er (VCC)

and ADC (VDD) supplies returning to a common ground

(GND). The digital output supply (0VDD) is returned to

OGND. Additional bypass capacitance is optional and may

be required if power supply noise is signiﬁ cant.

The differential inputs should run parallel and close to each

other. The input traces should be as short as possible to

minimize capacitance and to minimize noise pickup.

Heat Transfer

Most of the heat generated by the LTM9001 is transferred

through the bottom-side ground pads. For good electrical

and thermal performance, it is critical that all ground pins

are connected to a ground plane of sufﬁ cient area with as

many vias as possible.

Recommended Layout

The high integration of the LTM9001 makes the PC board

layout very simple and easy. However, to optimize its electri-

cal and thermal performance, some layout considerations

are still necessary, see Figures 15-18.

• Use large PCB copper areas for ground. This helps to

dissipate heat in the package through the board and

also helps to shield sensitive on-board analog signals.

Common ground (GND) and output ground (OGND)

are electrically isolated on the LTM9001, but can be

connected on the PCB underneath the part to provide

a common return path.

• Use multiple ground vias. Using as many vias as pos-

sible helps to improve the thermal performance of the

board and creates necessary barriers separating analog

and digital traces on the board at high frequencies.

• Separate analog and digital traces as much as pos-

sible, using vias to create high-frequency barriers.

This will reduce digital feedback that can reduce the

signal-to-noise ratio (SNR) and dynamic range of the

LTM9001.

The quality of the paste print is an important factor in

producing high yield assemblies. It is recommended to

use a type 3 or 4 printing no-clean solder paste. The solder

stencil design should follow the guidelines outlined in

Application Note 100.

The LTM9001 employs gold-ﬁ nished pads for use with

Pb-based or tin-based solder paste. It is inherently Pb-free

and complies with the JEDEC (e4) standard. The materi-

als declaration is available online at http://www.linear.

com/designtools/leadfree/mat_dec.jsp.

LTM9001-Ax/LTM9001-Bx

9001fc

APPLICATIONS INFORMATION

Figure 15. Layer 1

Figure 17. Layer 3

Figure 16. Layer 2

Figure 18. Layer 4

LTM9001-Ax/LTM9001-Bx

9001fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

LGA Package

81-Lead (11.25mm × 11.25mm × 2.32mm)

(Reference LTC DWG # 05-08-1809 Rev A)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

2. ALL DIMENSIONS ARE IN MILLIMETERS

LAND DESIGNATION PER JESD MO-222, SPP-010 AND SPP-020

5. PRIMARY DATUM -Z- IS SEATING PLANE

6. THE TOTAL NUMBER OF PADS: 81

DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,

BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.

THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR A

MARKED FEATURE

SYMBOL

aaa

bbb

TOLERANCE

0.15

0.10

11.250

BSC

PACKAGE TOP VIEW

LGA 81 1107 REV A

11.250

BSC

PAD 1

CORNER

PADS

SEE NOTES

aaa Z

2.17 – 2.47

DETAIL A

PACKAGE SIDE VIEW

DETAIL A

SUBSTRATE

MOLD

CAP

0.27 – 0.37

1.90 – 2.10

bbb Z

1.27

BSC

0.605 – 0.665

0.25 × 45°

CHAMFER

×3

0.605 – 0.665

10.160

BSC

10.160

BSC

PAD 1

678951234

PACKAGE BOTTOM VIEW

5.080

3.810

2.540

0.000

1.270

0.9525

1.5875

5.080

2.540

3.810

5.080

3.810

1.270

2.540

1.270

0.000

1.5875

0.9525

SUGGESTED PCB LAYOUT

TOP VIEW

LTMXXXXXX

μModule

TRAY PIN 1

BEVEL

COMPONENT

PIN “A1”

PACKAGE IN TRAY LOADING ORIENTATION

LTM9001-Ax/LTM9001-Bx

9001fc

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

C 7/10 Updated Timing Characteristics section 6, 7

(Revision history begins at Rev C)

LTM9001-Ax/LTM9001-Bx

9001fc

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0710 REV C • PRINTED IN USA

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75

50

9001 TA02

GROUND–

REFERENCED

SOURCE +

–

75

51.1

3.3V

VCC

LTM9001IN+

IN–

LTM9001 with Ground-Referenced Single-Ended Input

TYPICAL APPLICATION