DS1644 - Dallas Semiconductor

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DS1644LPM

Nonvolatile Timekeeping RAM

DS1644LPM

041697 1/11

FEATURES

•Upward compatible with the DS1643AL T imekeeping

RAM to achieve higher RAM density

•Integrated NV SRAM, real time clock, crystal, power–

fail control circuit and lithium energy source

•Low profile socketable module

– 255 mil package height

•Clock registers are accessed identical to the static

RAM. These registers are resident in the eight top

RAM locations.

•Totally nonvolatile with over 10 years of operation in

the absence of power

•Access time of 120 ns and 150 ns

•Quartz accuracy ±1 minute a month @ 25°C, factory

calibrated

•BCD coded year, month, date, day, hours, minutes,

and seconds with leap year compensation valid up to

2100

•Power–fail write protection allows for ±10% VCC pow-

er supply tolerance

ORDERING INFORMATION

DS1644L–XXX

–120 120 ns access

150 ns access–150

Low Profile Module

PIN ASSIGNMENT

PFO

VCC

A14

A13

A12

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

34–PIN LOW PROFILE MODULE

PIN DESCRIPTION

A0–A14 – Address Input

CE – Chip Enable

OE – Output Enable

WE – Write Enable

VCC – +5 Volts

GND – Ground

DQ0-DQ7 – Data Input/Output

NC – No Connection

PFO – Power Fail Output

DESCRIPTION

The DS1644L is a low profile module that requires a

PLCC surface mountable socket and is functionally

equivalent to the DS1644. The DS1644L is a 32K x 8

nonvolatile static RAM with a full function real time clock

which are both accessible in a Byte–wide format. The

real time clock information resides in the eight upper-

most RAM locations. The RTC registers contain year,

month, date, day, hours, minutes, and seconds data in

24 hour BCD format. Corrections for the day of the

month and leap year are made automatically . The RTC

clock registers are double buffered to avoid access of in-

correct data that can occur during clock update cycles.

The double buf fered system also prevents time loss as

the timekeeping countdown continues unabated by ac-

cess to time register data. The DS1644L also contains

its own power–fail circuitry which deselects the device

when the VCC supply is in an out–of–tolerance condi-

tion. This feature prevents loss of data from unpredict-

able system operation brought on by low VCC as errant

access and update cycles are avoided.

DS1644LPM

041697 2/11

CLOCK OPERATIONS –

READING THE CLOCK

While the double buffered register structure reduces the

chance of reading incorrect data, internal updates to the

DS1644L clock registers should be halted before clock

data is read to prevent reading of data in transition.

However, halting the internal clock register updating

process does not affect clock accuracy. Updating is

halted when a one is written into the read bit, the seventh

most significant bit in the control register. As long as a

one remains in that position, updating is halted. After a

halt is issued, the registers reflect the count, that is day ,

date, and time that was current at the moment the halt

command was issued. However , the internal clock reg-

isters of the double buffered system continue to update

so that the clock accuracy is not affected by the access

of data. All of the DS1644L registers are updated simul-

taneously after the clock status is reset. Updating is

within a second after the read bit is written to zero.

DS1644L BLOCK DIAGRAM Figure 1

OSCILLA TOR AND

CLOCK COUNTDOWN

CHAIN

POWER MONITOR,

SWITCHING, AND

WRITE PROTECTION

VCC

POWER GOOD

CLOCK

REGISTERS

A0–A14

DQ0–DQ7

32.768 KHz

32K X 8

NV SRAM

PFO

VBAT

DS1644LPM

041697 3/11

DS1644L TRUTH TABLE Table 1

VCC CE OE WE MODE DQ POWER

5 VOLTS 10%

VIH X X DESELECT HIGH–Z STANDBY

5 VOLTS 10%

X X X DESELECT HIGH–Z STANDBY

5 VOLTS ± 10% VIL X VIL WRITE DATA IN ACTIVE

VIL VIL VIH READ DATA OUT ACTIVE

VIL VIH VIH READ HIGH–Z ACTIVE

<4.5 VOLTS

>VBAT X X X DESELECT HIGH–Z CMOS STANDBY

<VBAT X X X DESELECT HIGH–Z DATA RETENTION

MODE

SETTING THE CLOCK

The eighth bit of the control register is the write bit. Set-

ting the write bit to a one, like the read bit, halts updates

to the DS1644L registers. The user can then load them

with the correct day , date and time data in 24 hour BCD

format. Resetting the write bit to a zero then transfers

those values to the actual clock counters and allows

normal operation to resume.

STOPPING AND STARTING THE CLOCK

OSCILLATOR

The clock oscillator may be stopped at any time. To in-

crease the shelf life, the oscillator can be turned off to

minimize current drain from the battery. The OSC bit is

the MSB for the seconds registers. Setting it to a one

stops the oscillator.

FREQUENCY TEST BIT

Bit 6 of the day byte is the frequency test bit. When the

frequency test bit is set to logic “1” and the oscillator is

running, the LSB of the seconds register will toggle at

512 Hz. When the seconds register is being read, the

DQ0 line will toggle at the 512 Hz frequency as long as

conditions for access remain valid (i.e., CE low , OE low,

and address for seconds register remain valid and

stable).

CLOCK ACCURACY

The DS1644L is guaranteed to keep time accuracy to

within ±1 minute per month at 25°C. The clock is cali-

brated at the factory by Dallas Semiconductor using

special calibration nonvolatile tuning elements. The

DS1644L does not require additional calibration, and

temperature deviations will have a negligible effect in

most applications. For this reason, methods of field

clock calibration are not available and not necessary.

Attempts to calibrate the clock that may be used with

similar device types (MK48T08 family) will not have any

effect even though the DS1644L appears to accept cal-

ibration data.

DS1644LPM

041697 4/11

DS1644L REGISTER MAP – BANK1 Table 2

ADDRESS

DATA

FUNCTION

ADDRESS

B7B6B5B4B3B2B1B0

FUNCTION

7FFF – – – – – – – – YEAR 00–99

7FFE X X X – – – – – MONTH 01–12

7FFD X X – – – – – – DATE 01–31

7FFC X FT X X X – – – DAY 01–07

7FFB X X – – – – – – HOUR 00–23

7FFA X – – – – – – – MINUTES 00–59

7FF9 OSC – – – – – – – SECONDS 00–59

7FF8 W R X X X X X X CONTROL A

OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST

W = WRITE BIT X = UNUSED

NOTE:

All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1644L is in the read mode whenever WE (write

enable) is high, and CE (chip enable) is low . The device

architecture allows ripple-through access to any of the

address locations in the NV SRAM. Valid data will be

available at the DQ pins within tAA after the last address

input is stable, providing that the CE and OE access

times and states are satisfied. If CE or OE access times

are not met, valid data will be available at the latter of

chip enable access (tCEA) or at output enable access

time (tOEA). The state of the data input/output pins (DQ)

is controlled by CE and OE. If the outputs are activated

before tAA, the data lines are driven to an intermediate

state until tAA. If the address inputs are changed while

CE and OE remain valid, output data will remain valid for

output data hold time (tOH) but will then go indeterminate

until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1644L is in the write mode whenever WE and

CE are in their active state. The start of a write is refer-

enced to the latter occurring high to low transition of WE

or CE. The addresses must be held valid throughout the

cycle. CE or WE must return inactive for a minimum of

tWR prior to the initiation of another read or write cycle.

Data in must be valid tDS prior to the end of write and re-

main valid for tDH afterward. In a typical application, the

OE signal will be high during a write cycle. However,

OE can be active provided that care is taken with the

data bus to avoid bus contention. If OE is low prior to

WE transitioning low the data bus can become active

with read data defined by the address inputs. A low tran-

sition on WE will then disable the outputs tWEZ after WE

goes active.

DS1644LPM

041697 5/11

DATA RETENTION MODE

When VCC is within nominal limits (VCC > 4.5 volts) the

DS1644L can be accessed as described above with

read or write cycles. However, when VCC is below the

power fail point VPF (point at which write protection oc-

curs) the internal clock registers and RAM are blocked

from access. This is accomplished internally by inhibit-

ing access via the CE signal. At this time the power–fail

output signal (PFO) will be driven active low and will

remain active until VCC returns to nominal levels. When

VCC falls below the level of the internal battery supply,

power input is switched from the VCC pin to the internal

battery and clock activity, RAM, and clock data are

maintained from the battery until VCC is returned to

nominal level.

INTERNAL BATTERY LONGEVITY

The DS1644L has a self contained lithium power source

that is designed to provide energy for clock activity , and

clock and RAM data retention when the VCC supply is

not present. The capability of this internal power supply

is sufficient to power the DS1644L continuously for the

life of the equipment in which it is installed. For specifi-

cation purposes, the life expectancy is 10 years at 25°C

with the internal clock oscillator running in the absence

of VCC power. The DS1644L is shipped from Dallas

Semiconductor with the clock oscillator turned off, so

the expected life should be considered to start from the

time the clock oscillator is first turned on. Actual life ex-

pectancy of the DS1644L will be much longer than 10

years since no internal lithium battery energy is con-

sumed when VCC is present. In fact, in most applica-

tions, the life expectancy of the DS1644L will be approx-

imately equal to the shelf life (expected useful life of the

lithium battery with no load attached) of the lithium bat-

tery which may prove to be as long as 20 years.

DS1644LPM

041697 6/11

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground –0.3V to +7.0V

Operating Temperature 0°C to 70°C

Storage Temperature –20°C to +70°C

Soldering Temperature 260°C for 10 seconds (See Note 7)

* This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Supply Voltage VCC 4.5 5.0 5.5 V 1

Logic 1 Voltage All Inputs VIH 2.2 VCC+0.3 V

Logic 0 Voltage All Inputs VIL –0.3 0.8 V

DC ELECTRICAL CHARACTERISTICS (0°C ≤ tA ≤ 70°C; VCC=5.0V ± 10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Average VCC Power Supply Cur-

rent ICC1 75 mA 3

TTL Standby Current (CE = VIH) ICC2 6mA 3

CMOS Standby Current

(CE=VCC–0.2V) ICC3 4.0 mA 3

Input Leakage Current (any input) IIL –1 +1 µA

Output Leakage Current IOL –1 +1 µA

Output Logic 1 Voltage

(IOUT = –1.0 mA) VOH 2.4 V

Output Logic 0 Voltage

(IOUT = +2.1 mA) VOL 0.4 V

Write Protection Voltage VPF 4.0 4.25 4.5 V

DS1644LPM

041697 7/11

AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5.0V ± 10%)

PARAMETER

SYMBOL

DS1644L–120 DS1644L–150

UNITS

NOTES

PARAMETER

SYMBOL

MIN MAX MIN MAX

UNITS

NOTES

Read Cycle Time tRC 120 150 ns

Address Access Time tAA 120 150 ns

CE Access Time tCEA 120 150 ns

CE Data Off Time tCEZ 40 50 ns

Output Enable Access T ime tOEA 100 120 ns

Output Enable Data Off Time tOEZ 40 50 ns

Output Enable to DQ Low–Z tOEL 5 5 ns

CE to DQ Low–Z tCEL 5 5 ns

Output Hold from Address tOH 5 5 ns

Write Cycle Time tWC 120 150 ns

Address Setup T ime tAS 0 0 ns

CE Pulse Width tCEW 100 120 ns

Address Hold from End of Write tAH1

tAH2 5

30 5

30 ns

ns 5

Write Pulse Width tWEW 120 150 ns

WE Data Off Time tWEZ 40 50 ns

WE or CE Inactive T ime tWR 10 10 ns

Data Setup T ime tDS 85 110 ns

Data Hold T ime High tDH1

tDH2 0

25 0

25 ns

ns 5

AC TEST CONDITIONS

Input Levels: 0V to 3V

T ransition Times: 5 ns

CAPACITANCE (tA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Capacitance on all pins

(except DQ) CI7 pF

Capacitance on DQ pins CDQ 10 pF

DS1644LPM

041697 8/11

AC ELECTRICAL CHARACTERISTICS (POWER–UP/DOWN TIMING) (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

CE or WE at VIH before Power–

Down tPD 0µs

VPF (Max) to VPF (Min) VCC Fall

Time tF300 µs

VPF (Min) to VSO VCC Fall Time tFB 10 µs

VSO to VPF (Min) VCC Rise Time tRB 1µs

VPF (Min) to VPF (Max) VCC Rise

Time tR0µs

Power–Up tREC 15 25 35 ms

Expected Data Retention Time

(Oscillator On) tDR 10 years 4

DS1644L READ CYCLE TIMING

tRC tRC tWC

READ READ WRITE

tAH

tAS

tWEW

VALID INVALID OUTVALID OUT

tOEZ

tAA

tOH

tCEA

tCEL

tOEA

tOEL

A0–A14

DQ0–DQ7

tWR

DS1644LPM

041697 9/11

DS1644L WRITE CYCLE TIMING

tWC tWC tRC

WRITE WRITE READ

A0–A14

DQ0– VALID OUTVALID INVALID IN

VALID

OUT

tAA

tAH1

tOEA

tWEZ

tAS

tCEW

tCEZ tDS tDH2

tDH1

tDS

DQ7

tWR

tWEW

tWR

tAH2

POWER–DOWN/POWER–UP TIMING

VCC

tPD

tFB

DATA RETENTION

tDR

IBATT

VPF (MAX)

VPF (MIN)

tREC

tRB

VPF (MIN)

VSO

PFO PFO

VPF (MAX)

VPFVPF

DS1644LPM

041697 10/11

NOTES:

1. All voltages are referenced to ground.

2. Typical values are at 25°C and nominal supplies.

3. Outputs are open.

4. Data retention time is at 25°C and is calculated from

the date code on the device package. The date code

XXYY is the year followed by the week of the year

in which the device was manufactured. For exam-

ple, 9225, would mean the 25th week of 1992.

5. tAH1, tDH1 are measured from WE going high.

6. tAH2, tDH2 are measured from CE going high.

7. Unencapsulatesd Low Profile Modules are not rec-

ommended for processing through conventional

wavesoldering techniques. The Use of a PLCC

socket is recommended for production purposes.

OUTPUT LOAD

+5 VOLTS

100 pF

D.U.T.

1.8KΩ

1KΩ

RECOMMENDED DS1644L MODULE SOCKET LAND PATTERNS

EITHER A TWO OR FOUR SIDED SOCKET MAY BE

UTILIZED FOR DS1644LPM INSTALLATION.

DS1644LPM

041697 11/11

DS1644LPM 34–PIN LOW PROFILE MODULE

DIM MIN MAX

A 0.955 0.980

B 0.840 0.855

C 0.230 0.250

D 0.975 0.995

E 0.047 0.053

F 0.015 0.025

PKG INCHES

NOTE:

Please contact the factory for information on PLCC Sur-

face mountable sockets.