M-991-01SMTR - Clare - Product.Network

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DS-M-991-R02 1

M-991

Call Progress Tone Generator

RoHS

2002/95/EC e3

Part # Description

M-991 14-Pin Plastic DIP

M-991-01SM 16-Pin SOIC

M-991-01SMTR 16-Pin SOIC, Tape & Reel

Applications

Features Description

Ordering Information

Pin Configuration

• Telephone Systems

• Test Equipment

• Callback

• Security Systems

• Billing Systems

• Generates standard call progress tones

• Digital input control

• Linear (analog) output

• Power output capable of driving standard line

• 14-pin DIP and 16-pin SOIC package types

• Single supply 5V CMOS (low power)

• Inexpensive 3.58 MHz time base

• Temperature range from -25ºC to 70ºC

The M-991 is a call progress tone generator integrated

circuit for use in telephone systems. The circuit uses

low-power CMOS techniques to generate tones which

are digitally controlled and highly linear. The M-991 is

designed to permit operation with almost any system.

The use of integrated circuit techniques allows the

M-991 to incorporate the control, tone generating, and

power output buffer into a single 14-pin DIP or 16-pin

SOIC. A 3.58-MHz (color burst) crystal-controlled time

base guarantees accuracy and repeatability.

Block Diagram

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M-991

Absolute Maximum Ratings are stress ratings. Stresses in

excess of these ratings can cause permanent damage to

the device. Functional operation of the device at these or

any other conditions beyond those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to the absolute maximum ratings

for an extended period may degrade the device and affect

its reliability.

Absolute Maximum Ratings

Parameter Ratings Units

VDD 7V

Any Input Voltage VSS-0.6 to VDD+0.6 V

Operating Ambient Temperature -25 to +70 °C

Storage Temperature -55 to +125 °C

Parameter Min Typ Max Units Notes

Power Supply

and Reference

VDD 4.75 - 5.25 V 

Current Drain IDD - 2/4 - mA 8

VREF Pin:

Deviation From (VDD+VSS)/2 -2 - +2 %

Internal Resistance From VREF to VDD, VSS 3.25 - 6.75 k

Oscillator Frequency Deviation -0.01 - +0.01 % 7

External Clock (XOUT Open)

VIL 0 - 0.2 V

VIH VDD- 0.2 - VDD

Duty Cycle 40 - 60 %

XIN, XOUT Loading

Capacitance - - 10 pF 10

Resistance 20 - - M-

Tone Output Frequency Deviation -0.5 - +0.5 % -

Level 100 - 180 mV 2

Distorting Components -35 - - dB 3

Idle - - -60 dBm 4

OUTDRIVE Envelope Rise Time - - 4 ms 5

Control DX, CE Pins: 6

VIL - - 0.5 V

VIH 2.5 - -

Mute Pins:

VOL (ISINK = -100A) - - 1.5 V

VOH (ISOURCE = 100A) VDD- 1.5 - -

Timing Data Setup (tDS) 200 - - ns 11

Data Hold (tDH)10--ns

Chip Enable Fall (tPL)--90ns

Turn On Delay (tTO)--5ms

Turn Off Delay (tTD)--5ms

Mute Delay from Outdrive (tMO) - - 200 ns

Specifications

Notes: (Unless Otherwise Speciﬁ ed)

1 All DC voltages are referenced to VSS.

2 Vrms per tone, 540 load.

3 Any one frequency relative to the lowest level output tone (f<4000Hz)

4 0 dBm = 0.775Vrms.

5 To 90% maximum amplitude.

6 For all supply voltages in the operating range.

7 At XOUT pin as compared to 3.579545MHz.

8 OUTDRIVE with load > 5 k/OUTDRIVE with 540 load.

9 Resistance at VREF to VDD or VSS > 1M.

10 Crystal oscillator active.

11 Measured 90% to 10%.

M-991

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R02

Call progress tones are audible tones sent from

switching systems to calling parties (or equipment) to

indicate the status of calls. Calling parties can identify

the success of a placed call by what is heard after

dialing. The M-991 series utilizes a highly linear tone

generator that produces the unique frequencies (singly

or in pairs) that are common to call progress signals.

Duration and frequency selection are digitally

controlled (see the Data/Tone Selection table below for

data settings for a particular tone output). A typical

control sequence for the M-991 is: (1) set data lines to

desired frequency selection, (2) wait for data lines to

settle, (3) drive the chip enable (CE) low, (4) maintain

CE low for desired tone duration (Note: data lines may

be changed after data hold time), and (4) return CE to

a logic high. (Commonly used call progress tones are

Call Progress Tone Generation

shown in the Data/Tone Selection table below.) In a

bus-oriented system, noise on the data lines may

propagate through the device and appear at the

output. To safeguard against this, use an external latch

to lock the data into the device. In addition, it is good

practice to bypass the VREF pin to ground with a

small capacitor (0.01F) to reduce power supply

noise. The designer should be aware of device timing

requirements and design accordingly. The data input

pins may be tied high (+5 VDC) or low (ground) as

required, but D4 and D5 must be left open. Beware of

hardwiring the CE pin for dedicated tone generation.

This input is edge triggered. An RC network like that

shown in the Power-on Reset Circuit on Page 4 should

be used to momentarily reset the device immediately

following power-up to ensure proper operation.

D3 D2 D1 D0 Frequency (Hz) Use

0000300 440Dial Tone

0001400 offSpecial

0010440 offAlert Tone

0011440 480Audible Ring

0100440 620Pre-empt

0101480 offBell high tone

0110480 620Reorder (Bell low)

0111350 offSpecial

1000620 offSpecial

1001941 1209 DTMF " * "

Tone Name Frequency (Hz)

1 2 Interruption Rate

Dial 350 440 Steady

Reorder 480 620 Repeat, tones on and off 250 ms ± 25 ms each.

Busy 480 620 Repeat, tones on and off 500 ms ± 50 ms each.

Audible Ring 440 480 Repeat, tones on 2 ± 0.2 s, tones off 4 ± 0.4 s

Recall Dial 350 440 Three bursts tones on and off 100 ms ± 20 ms each followed by dial tone.

Special AR 440 480 Tones on 1 ± 0.2s, followed by single 440 Hz on for 0.2s on, and silence for 3 ± 0.3 s, repeat.

Intercept 440 620 Repeat alternating tones, each on for 230 ms ± 70 ms with total cycle of 500 ± 50 ms.

Call Waiting 440 off One burst 200 ± 100 ms

Busy Veriﬁ cation 440 off One burst of tone on 1.75 ± 0.25 s before attendant intrudes, followed by burst of tone 0.65 ± 0.15 s on, 8 to

20 s apart for as long as the call lasts

Executive Override 440 off One burst of tone for 3 ± 1 s before overriding station intrudes

Conﬁ rmation 350 440 Three bursts on and off 100 ms each or 100 ms on, 100 ms off, 300 ms on

Pin Function

CE Latches data and enables output (active low input)

D0 - D3 Data input pins (See Data/Tone Selection)

D4 - D5 Leave open

MUTE Output indicates that a signal is being generated at

OUTDRIVE.

OUTDRIVE Linear buffered tone output.

VDD Most positive power supply input pin.

VREF Internally generated mid-power supply voltage (output).

VSS Most negative power supply input pin.

XIN Crystal oscillator or digital clock input.

XOUT Crystal oscillator output.

Data/Tone Selection Pin Function

Standard Call Progress Tones

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M-991

Power-On Reset Circuit

Timing Diagram

Expanded Timing Diagram

Typical Application

Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications

and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of

Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability,

fitness for a particular purpose, or infringement of any intellectual property right.

The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other

applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental

damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.

Specification: DS-M-991-R02

OptoMOS® is a registered trademark of Clare, Inc.

6/20/2012

For additional information please visit our website at: www.clare.com

M-991

14-Pin DIP

16-Pin SOIC

Mechanical Dimensions

Dimensions

(inches)

Dimensions

(inches)

Tolerances

Inches Metric (mm)

Min Max Min Max

A - 0.210 - 5.33

A1 0.15 - 0.38 -

b 0.014 0.022 0.36 0.56

b2 0.045 0.070 1.1 1.8

C 0.008 0.014 0.20 0.36

D 0.735 0.775 18.7 19.7

E 0.300 0.325 7.6 8.3

E1 0.240 0.280 6.1 7.1

e 0.100 BSC 2.54 BSC

ec 0º15º0º15º

L 0.115 0.150 2.9 4.1

Tolerances

Inches Metric (mm)

Min Max Min Max

A 0.0926 0.1043 2.35 2.65

A1 0.0040 0.0118 0.10 0.30

b 0.013 0.020 0.33 0.51

D 0.3977 0.4133 10.10 10.50

E 0.2914 0.2992 7.4 7.6

e 0.050 BSC 1.27 BSC

H0.394 0.419 10.00 10.65

L 0.016 0.050 0.40 1.27